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Merge tag 'mfd-arizona-v3.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / exynos / exynos_hdmi.c
CommitLineData
d8408326
SWK		 1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
760285e7
DH		 17#include <drm/drmP.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_crtc_helper.h>
d8408326
SWK		 20
21#include "regs-hdmi.h"
22
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/wait.h>
26#include <linux/i2c.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/irq.h>
31#include <linux/delay.h>
32#include <linux/pm_runtime.h>
33#include <linux/clk.h>
34#include <linux/regulator/consumer.h>
22c4f428
RS		 35#include <linux/io.h>
36#include <linux/of_gpio.h>
d8408326
SWK		 37
38#include <drm/exynos_drm.h>
39
40#include "exynos_drm_drv.h"
41#include "exynos_drm_hdmi.h"
42
43#include "exynos_hdmi.h"
44
fca57122
TS		 45#include <linux/gpio.h>
46#include <media/s5p_hdmi.h>
47
1de425b0
ID		 48#define MAX_WIDTH 1920
49#define MAX_HEIGHT 1080
d8408326
SWK		 50#define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev))
51
a144c2e9
RS		 52/* AVI header and aspect ratio */
53#define HDMI_AVI_VERSION 0x02
54#define HDMI_AVI_LENGTH 0x0D
55#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
56#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
57
58/* AUI header info */
59#define HDMI_AUI_VERSION 0x01
60#define HDMI_AUI_LENGTH 0x0A
61
62/* HDMI infoframe to configure HDMI out packet header, AUI and AVI */
63enum HDMI_PACKET_TYPE {
64 /* refer to Table 5-8 Packet Type in HDMI specification v1.4a */
65 /* InfoFrame packet type */
66 HDMI_PACKET_TYPE_INFOFRAME = 0x80,
67 /* Vendor-Specific InfoFrame */
68 HDMI_PACKET_TYPE_VSI = HDMI_PACKET_TYPE_INFOFRAME + 1,
69 /* Auxiliary Video information InfoFrame */
70 HDMI_PACKET_TYPE_AVI = HDMI_PACKET_TYPE_INFOFRAME + 2,
71 /* Audio information InfoFrame */
72 HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4
73};
74
5a325071
RS		 75enum hdmi_type {
76 HDMI_TYPE13,
77 HDMI_TYPE14,
78};
79
590f418a
JS		 80struct hdmi_resources {
81 struct clk *hdmi;
82 struct clk *sclk_hdmi;
83 struct clk *sclk_pixel;
84 struct clk *sclk_hdmiphy;
85 struct clk *hdmiphy;
86 struct regulator_bulk_data *regul_bulk;
87 int regul_count;
88};
89
2f7e2ed0
SP		 90struct hdmi_tg_regs {
91 u8 cmd[1];
92 u8 h_fsz[2];
93 u8 hact_st[2];
94 u8 hact_sz[2];
95 u8 v_fsz[2];
96 u8 vsync[2];
97 u8 vsync2[2];
98 u8 vact_st[2];
99 u8 vact_sz[2];
100 u8 field_chg[2];
101 u8 vact_st2[2];
102 u8 vact_st3[2];
103 u8 vact_st4[2];
104 u8 vsync_top_hdmi[2];
105 u8 vsync_bot_hdmi[2];
106 u8 field_top_hdmi[2];
107 u8 field_bot_hdmi[2];
108 u8 tg_3d[1];
109};
110
6b986edf
RS		 111struct hdmi_v13_core_regs {
112 u8 h_blank[2];
113 u8 v_blank[3];
114 u8 h_v_line[3];
115 u8 vsync_pol[1];
116 u8 int_pro_mode[1];
117 u8 v_blank_f[3];
118 u8 h_sync_gen[3];
119 u8 v_sync_gen1[3];
120 u8 v_sync_gen2[3];
121 u8 v_sync_gen3[3];
122};
123
124struct hdmi_v14_core_regs {
2f7e2ed0
SP		 125 u8 h_blank[2];
126 u8 v2_blank[2];
127 u8 v1_blank[2];
128 u8 v_line[2];
129 u8 h_line[2];
130 u8 hsync_pol[1];
131 u8 vsync_pol[1];
132 u8 int_pro_mode[1];
133 u8 v_blank_f0[2];
134 u8 v_blank_f1[2];
135 u8 h_sync_start[2];
136 u8 h_sync_end[2];
137 u8 v_sync_line_bef_2[2];
138 u8 v_sync_line_bef_1[2];
139 u8 v_sync_line_aft_2[2];
140 u8 v_sync_line_aft_1[2];
141 u8 v_sync_line_aft_pxl_2[2];
142 u8 v_sync_line_aft_pxl_1[2];
143 u8 v_blank_f2[2]; /* for 3D mode */
144 u8 v_blank_f3[2]; /* for 3D mode */
145 u8 v_blank_f4[2]; /* for 3D mode */
146 u8 v_blank_f5[2]; /* for 3D mode */
147 u8 v_sync_line_aft_3[2];
148 u8 v_sync_line_aft_4[2];
149 u8 v_sync_line_aft_5[2];
150 u8 v_sync_line_aft_6[2];
151 u8 v_sync_line_aft_pxl_3[2];
152 u8 v_sync_line_aft_pxl_4[2];
153 u8 v_sync_line_aft_pxl_5[2];
154 u8 v_sync_line_aft_pxl_6[2];
155 u8 vact_space_1[2];
156 u8 vact_space_2[2];
157 u8 vact_space_3[2];
158 u8 vact_space_4[2];
159 u8 vact_space_5[2];
160 u8 vact_space_6[2];
161};
162
6b986edf
RS		 163struct hdmi_v13_conf {
164 struct hdmi_v13_core_regs core;
165 struct hdmi_tg_regs tg;
166};
167
2f7e2ed0 168struct hdmi_v14_conf {
6b986edf 169 struct hdmi_v14_core_regs core;
2f7e2ed0 170 struct hdmi_tg_regs tg;
6b986edf
RS		 171};
172
173struct hdmi_conf_regs {
174 int pixel_clock;
2f7e2ed0 175 int cea_video_id;
6b986edf
RS		 176 union {
177 struct hdmi_v13_conf v13_conf;
178 struct hdmi_v14_conf v14_conf;
179 } conf;
2f7e2ed0
SP		 180};
181
590f418a
JS		 182struct hdmi_context {
183 struct device *dev;
184 struct drm_device *drm_dev;
cf8fc4f1
JS		 185 bool hpd;
186 bool powered;
872d20d6 187 bool dvi_mode;
cf8fc4f1 188 struct mutex hdmi_mutex;
590f418a 189
590f418a 190 void __iomem *regs;
1055b39f 191 void *parent_ctx;
77006a7a 192 int irq;
590f418a
JS		 193
194 struct i2c_client *ddc_port;
195 struct i2c_client *hdmiphy_port;
196
6b986edf
RS		 197 /* current hdmiphy conf regs */
198 struct hdmi_conf_regs mode_conf;
590f418a
JS		 199
200 struct hdmi_resources res;
7ecd34e8 201
fca57122 202 int hpd_gpio;
5a325071
RS		 203
204 enum hdmi_type type;
590f418a
JS		 205};
206
6b986edf
RS		 207struct hdmiphy_config {
208 int pixel_clock;
209 u8 conf[32];
d8408326
SWK		 210};
211
6b986edf
RS		 212/* list of phy config settings */
213static const struct hdmiphy_config hdmiphy_v13_configs[] = {
214 {
215 .pixel_clock = 27000000,
216 .conf = {
217 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
218 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
219 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
220 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
221 },
d8408326 222 },
6b986edf
RS		 223 {
224 .pixel_clock = 27027000,
225 .conf = {
226 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
227 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
228 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
229 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
230 },
d8408326 231 },
6b986edf
RS		 232 {
233 .pixel_clock = 74176000,
234 .conf = {
235 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
236 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
237 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
238 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
239 },
d8408326 240 },
6b986edf
RS		 241 {
242 .pixel_clock = 74250000,
243 .conf = {
244 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
245 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
246 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
247 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
248 },
d8408326 249 },
6b986edf
RS		 250 {
251 .pixel_clock = 148500000,
252 .conf = {
253 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
254 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
255 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
256 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
257 },
d8408326
SWK		 258 },
259};
260
2f7e2ed0
SP		 261static const struct hdmiphy_config hdmiphy_v14_configs[] = {
262 {
263 .pixel_clock = 25200000,
264 .conf = {
265 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
266 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
267 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
268 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
269 },
3ecd70b1 270 },
2f7e2ed0
SP		 271 {
272 .pixel_clock = 27000000,
273 .conf = {
274 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
275 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
276 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
277 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
278 },
3ecd70b1 279 },
2f7e2ed0
SP		 280 {
281 .pixel_clock = 27027000,
282 .conf = {
283 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
284 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
285 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
286 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
287 },
3ecd70b1 288 },
2f7e2ed0
SP		 289 {
290 .pixel_clock = 36000000,
291 .conf = {
292 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
293 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
294 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
295 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
296 },
3ecd70b1 297 },
2f7e2ed0
SP		 298 {
299 .pixel_clock = 40000000,
300 .conf = {
301 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
302 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
303 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
304 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
305 },
3ecd70b1 306 },
2f7e2ed0
SP		 307 {
308 .pixel_clock = 65000000,
309 .conf = {
310 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
311 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
312 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
313 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
314 },
3ecd70b1 315 },
2f7e2ed0
SP		 316 {
317 .pixel_clock = 74176000,
318 .conf = {
319 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
320 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
321 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
322 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
323 },
3ecd70b1 324 },
2f7e2ed0
SP		 325 {
326 .pixel_clock = 74250000,
327 .conf = {
328 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
329 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
330 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
331 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
332 },
e540adf3 333 },
2f7e2ed0
SP		 334 {
335 .pixel_clock = 83500000,
336 .conf = {
337 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
338 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
339 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
340 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
341 },
e540adf3 342 },
2f7e2ed0
SP		 343 {
344 .pixel_clock = 106500000,
345 .conf = {
346 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
347 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
348 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
349 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
350 },
3ecd70b1 351 },
2f7e2ed0
SP		 352 {
353 .pixel_clock = 108000000,
354 .conf = {
355 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
356 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
357 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
358 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
359 },
3ecd70b1 360 },
2f7e2ed0
SP		 361 {
362 .pixel_clock = 146250000,
363 .conf = {
364 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
365 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
366 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
367 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
368 },
3ecd70b1 369 },
2f7e2ed0
SP		 370 {
371 .pixel_clock = 148500000,
372 .conf = {
373 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
374 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
375 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
376 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
377 },
3ecd70b1
JS		 378 },
379};
380
a144c2e9
RS		 381struct hdmi_infoframe {
382 enum HDMI_PACKET_TYPE type;
383 u8 ver;
384 u8 len;
385};
d8408326
SWK		 386
387static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
388{
389 return readl(hdata->regs + reg_id);
390}
391
392static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
393 u32 reg_id, u8 value)
394{
395 writeb(value, hdata->regs + reg_id);
396}
397
398static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
399 u32 reg_id, u32 value, u32 mask)
400{
401 u32 old = readl(hdata->regs + reg_id);
402 value = (value & mask) | (old & ~mask);
403 writel(value, hdata->regs + reg_id);
404}
405
3ecd70b1 406static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
d8408326
SWK		 407{
408#define DUMPREG(reg_id) \
409 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
410 readl(hdata->regs + reg_id))
411 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
412 DUMPREG(HDMI_INTC_FLAG);
413 DUMPREG(HDMI_INTC_CON);
414 DUMPREG(HDMI_HPD_STATUS);
3ecd70b1
JS		 415 DUMPREG(HDMI_V13_PHY_RSTOUT);
416 DUMPREG(HDMI_V13_PHY_VPLL);
417 DUMPREG(HDMI_V13_PHY_CMU);
418 DUMPREG(HDMI_V13_CORE_RSTOUT);
419
420 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
421 DUMPREG(HDMI_CON_0);
422 DUMPREG(HDMI_CON_1);
423 DUMPREG(HDMI_CON_2);
424 DUMPREG(HDMI_SYS_STATUS);
425 DUMPREG(HDMI_V13_PHY_STATUS);
426 DUMPREG(HDMI_STATUS_EN);
427 DUMPREG(HDMI_HPD);
428 DUMPREG(HDMI_MODE_SEL);
429 DUMPREG(HDMI_V13_HPD_GEN);
430 DUMPREG(HDMI_V13_DC_CONTROL);
431 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
432
433 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
434 DUMPREG(HDMI_H_BLANK_0);
435 DUMPREG(HDMI_H_BLANK_1);
436 DUMPREG(HDMI_V13_V_BLANK_0);
437 DUMPREG(HDMI_V13_V_BLANK_1);
438 DUMPREG(HDMI_V13_V_BLANK_2);
439 DUMPREG(HDMI_V13_H_V_LINE_0);
440 DUMPREG(HDMI_V13_H_V_LINE_1);
441 DUMPREG(HDMI_V13_H_V_LINE_2);
442 DUMPREG(HDMI_VSYNC_POL);
443 DUMPREG(HDMI_INT_PRO_MODE);
444 DUMPREG(HDMI_V13_V_BLANK_F_0);
445 DUMPREG(HDMI_V13_V_BLANK_F_1);
446 DUMPREG(HDMI_V13_V_BLANK_F_2);
447 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
448 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
449 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
450 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
451 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
452 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
453 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
454 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
455 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
456 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
457 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
458 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
459
460 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
461 DUMPREG(HDMI_TG_CMD);
462 DUMPREG(HDMI_TG_H_FSZ_L);
463 DUMPREG(HDMI_TG_H_FSZ_H);
464 DUMPREG(HDMI_TG_HACT_ST_L);
465 DUMPREG(HDMI_TG_HACT_ST_H);
466 DUMPREG(HDMI_TG_HACT_SZ_L);
467 DUMPREG(HDMI_TG_HACT_SZ_H);
468 DUMPREG(HDMI_TG_V_FSZ_L);
469 DUMPREG(HDMI_TG_V_FSZ_H);
470 DUMPREG(HDMI_TG_VSYNC_L);
471 DUMPREG(HDMI_TG_VSYNC_H);
472 DUMPREG(HDMI_TG_VSYNC2_L);
473 DUMPREG(HDMI_TG_VSYNC2_H);
474 DUMPREG(HDMI_TG_VACT_ST_L);
475 DUMPREG(HDMI_TG_VACT_ST_H);
476 DUMPREG(HDMI_TG_VACT_SZ_L);
477 DUMPREG(HDMI_TG_VACT_SZ_H);
478 DUMPREG(HDMI_TG_FIELD_CHG_L);
479 DUMPREG(HDMI_TG_FIELD_CHG_H);
480 DUMPREG(HDMI_TG_VACT_ST2_L);
481 DUMPREG(HDMI_TG_VACT_ST2_H);
482 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
483 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
484 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
485 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
486 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
487 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
488 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
489 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
490#undef DUMPREG
491}
492
493static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
494{
495 int i;
496
497#define DUMPREG(reg_id) \
498 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
499 readl(hdata->regs + reg_id))
500
501 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
502 DUMPREG(HDMI_INTC_CON);
503 DUMPREG(HDMI_INTC_FLAG);
504 DUMPREG(HDMI_HPD_STATUS);
505 DUMPREG(HDMI_INTC_CON_1);
506 DUMPREG(HDMI_INTC_FLAG_1);
507 DUMPREG(HDMI_PHY_STATUS_0);
508 DUMPREG(HDMI_PHY_STATUS_PLL);
509 DUMPREG(HDMI_PHY_CON_0);
d8408326
SWK		 510 DUMPREG(HDMI_PHY_RSTOUT);
511 DUMPREG(HDMI_PHY_VPLL);
512 DUMPREG(HDMI_PHY_CMU);
513 DUMPREG(HDMI_CORE_RSTOUT);
514
515 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
516 DUMPREG(HDMI_CON_0);
517 DUMPREG(HDMI_CON_1);
518 DUMPREG(HDMI_CON_2);
519 DUMPREG(HDMI_SYS_STATUS);
3ecd70b1 520 DUMPREG(HDMI_PHY_STATUS_0);
d8408326
SWK		 521 DUMPREG(HDMI_STATUS_EN);
522 DUMPREG(HDMI_HPD);
523 DUMPREG(HDMI_MODE_SEL);
3ecd70b1 524 DUMPREG(HDMI_ENC_EN);
d8408326
SWK		 525 DUMPREG(HDMI_DC_CONTROL);
526 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
527
528 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
529 DUMPREG(HDMI_H_BLANK_0);
530 DUMPREG(HDMI_H_BLANK_1);
3ecd70b1
JS		 531 DUMPREG(HDMI_V2_BLANK_0);
532 DUMPREG(HDMI_V2_BLANK_1);
533 DUMPREG(HDMI_V1_BLANK_0);
534 DUMPREG(HDMI_V1_BLANK_1);
535 DUMPREG(HDMI_V_LINE_0);
536 DUMPREG(HDMI_V_LINE_1);
537 DUMPREG(HDMI_H_LINE_0);
538 DUMPREG(HDMI_H_LINE_1);
539 DUMPREG(HDMI_HSYNC_POL);
540
d8408326
SWK		 541 DUMPREG(HDMI_VSYNC_POL);
542 DUMPREG(HDMI_INT_PRO_MODE);
3ecd70b1
JS		 543 DUMPREG(HDMI_V_BLANK_F0_0);
544 DUMPREG(HDMI_V_BLANK_F0_1);
545 DUMPREG(HDMI_V_BLANK_F1_0);
546 DUMPREG(HDMI_V_BLANK_F1_1);
547
548 DUMPREG(HDMI_H_SYNC_START_0);
549 DUMPREG(HDMI_H_SYNC_START_1);
550 DUMPREG(HDMI_H_SYNC_END_0);
551 DUMPREG(HDMI_H_SYNC_END_1);
552
553 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
554 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
555 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
556 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
557
558 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
559 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
560 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
561 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
562
563 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
564 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
565 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
566 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
567
568 DUMPREG(HDMI_V_BLANK_F2_0);
569 DUMPREG(HDMI_V_BLANK_F2_1);
570 DUMPREG(HDMI_V_BLANK_F3_0);
571 DUMPREG(HDMI_V_BLANK_F3_1);
572 DUMPREG(HDMI_V_BLANK_F4_0);
573 DUMPREG(HDMI_V_BLANK_F4_1);
574 DUMPREG(HDMI_V_BLANK_F5_0);
575 DUMPREG(HDMI_V_BLANK_F5_1);
576
577 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
578 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
579 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
580 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
581 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
582 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
583 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
584 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
585
586 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
587 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
588 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
589 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
590 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
591 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
592 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
593 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
594
595 DUMPREG(HDMI_VACT_SPACE_1_0);
596 DUMPREG(HDMI_VACT_SPACE_1_1);
597 DUMPREG(HDMI_VACT_SPACE_2_0);
598 DUMPREG(HDMI_VACT_SPACE_2_1);
599 DUMPREG(HDMI_VACT_SPACE_3_0);
600 DUMPREG(HDMI_VACT_SPACE_3_1);
601 DUMPREG(HDMI_VACT_SPACE_4_0);
602 DUMPREG(HDMI_VACT_SPACE_4_1);
603 DUMPREG(HDMI_VACT_SPACE_5_0);
604 DUMPREG(HDMI_VACT_SPACE_5_1);
605 DUMPREG(HDMI_VACT_SPACE_6_0);
606 DUMPREG(HDMI_VACT_SPACE_6_1);
d8408326
SWK		 607
608 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
609 DUMPREG(HDMI_TG_CMD);
610 DUMPREG(HDMI_TG_H_FSZ_L);
611 DUMPREG(HDMI_TG_H_FSZ_H);
612 DUMPREG(HDMI_TG_HACT_ST_L);
613 DUMPREG(HDMI_TG_HACT_ST_H);
614 DUMPREG(HDMI_TG_HACT_SZ_L);
615 DUMPREG(HDMI_TG_HACT_SZ_H);
616 DUMPREG(HDMI_TG_V_FSZ_L);
617 DUMPREG(HDMI_TG_V_FSZ_H);
618 DUMPREG(HDMI_TG_VSYNC_L);
619 DUMPREG(HDMI_TG_VSYNC_H);
620 DUMPREG(HDMI_TG_VSYNC2_L);
621 DUMPREG(HDMI_TG_VSYNC2_H);
622 DUMPREG(HDMI_TG_VACT_ST_L);
623 DUMPREG(HDMI_TG_VACT_ST_H);
624 DUMPREG(HDMI_TG_VACT_SZ_L);
625 DUMPREG(HDMI_TG_VACT_SZ_H);
626 DUMPREG(HDMI_TG_FIELD_CHG_L);
627 DUMPREG(HDMI_TG_FIELD_CHG_H);
628 DUMPREG(HDMI_TG_VACT_ST2_L);
629 DUMPREG(HDMI_TG_VACT_ST2_H);
3ecd70b1
JS		 630 DUMPREG(HDMI_TG_VACT_ST3_L);
631 DUMPREG(HDMI_TG_VACT_ST3_H);
632 DUMPREG(HDMI_TG_VACT_ST4_L);
633 DUMPREG(HDMI_TG_VACT_ST4_H);
d8408326
SWK		 634 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
635 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
636 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
637 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
638 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
639 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
640 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
641 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
3ecd70b1
JS		 642 DUMPREG(HDMI_TG_3D);
643
644 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
645 DUMPREG(HDMI_AVI_CON);
646 DUMPREG(HDMI_AVI_HEADER0);
647 DUMPREG(HDMI_AVI_HEADER1);
648 DUMPREG(HDMI_AVI_HEADER2);
649 DUMPREG(HDMI_AVI_CHECK_SUM);
650 DUMPREG(HDMI_VSI_CON);
651 DUMPREG(HDMI_VSI_HEADER0);
652 DUMPREG(HDMI_VSI_HEADER1);
653 DUMPREG(HDMI_VSI_HEADER2);
654 for (i = 0; i < 7; ++i)
655 DUMPREG(HDMI_VSI_DATA(i));
656
d8408326
SWK		 657#undef DUMPREG
658}
659
3ecd70b1
JS		 660static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
661{
5a325071 662 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 663 hdmi_v13_regs_dump(hdata, prefix);
664 else
665 hdmi_v14_regs_dump(hdata, prefix);
666}
667
a144c2e9
RS		 668static u8 hdmi_chksum(struct hdmi_context *hdata,
669 u32 start, u8 len, u32 hdr_sum)
670{
671 int i;
672
673 /* hdr_sum : header0 + header1 + header2
674 * start : start address of packet byte1
675 * len : packet bytes - 1 */
676 for (i = 0; i < len; ++i)
677 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
678
679 /* return 2's complement of 8 bit hdr_sum */
680 return (u8)(~(hdr_sum & 0xff) + 1);
681}
682
683static void hdmi_reg_infoframe(struct hdmi_context *hdata,
684 struct hdmi_infoframe *infoframe)
685{
686 u32 hdr_sum;
687 u8 chksum;
688 u32 aspect_ratio;
689 u32 mod;
690 u32 vic;
691
692 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
693
694 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
695 if (hdata->dvi_mode) {
696 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
697 HDMI_VSI_CON_DO_NOT_TRANSMIT);
698 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
699 HDMI_AVI_CON_DO_NOT_TRANSMIT);
700 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
701 return;
702 }
703
704 switch (infoframe->type) {
705 case HDMI_PACKET_TYPE_AVI:
706 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
707 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
708 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
709 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
710 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
711
712 /* Output format zero hardcoded ,RGB YBCR selection */
713 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
714 AVI_ACTIVE_FORMAT_VALID |
715 AVI_UNDERSCANNED_DISPLAY_VALID);
716
717 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
718
719 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
720 AVI_SAME_AS_PIC_ASPECT_RATIO);
721
6b986edf 722 vic = hdata->mode_conf.cea_video_id;
a144c2e9
RS		 723 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
724
725 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
726 infoframe->len, hdr_sum);
727 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
728 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
729 break;
730 case HDMI_PACKET_TYPE_AUI:
731 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
732 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
733 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
734 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
735 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
736 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
737 infoframe->len, hdr_sum);
738 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
739 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
740 break;
741 default:
742 break;
743 }
744}
745
d8408326
SWK		 746static bool hdmi_is_connected(void *ctx)
747{
f9309d1b 748 struct hdmi_context *hdata = ctx;
d8408326 749
cf8fc4f1 750 return hdata->hpd;
d8408326
SWK		 751}
752
9c08e4ba 753static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
d8408326
SWK		 754{
755 struct edid *raw_edid;
f9309d1b 756 struct hdmi_context *hdata = ctx;
d8408326
SWK		 757
758 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
759
760 if (!hdata->ddc_port)
9c08e4ba 761 return ERR_PTR(-ENODEV);
d8408326
SWK		 762
763 raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
9c08e4ba
RS		 764 if (!raw_edid)
765 return ERR_PTR(-ENODEV);
766
767 hdata->dvi_mode = !drm_detect_hdmi_monitor(raw_edid);
768 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
769 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
770 raw_edid->width_cm, raw_edid->height_cm);
d8408326 771
9c08e4ba 772 return raw_edid;
d8408326
SWK		 773}
774
6b986edf 775static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
d8408326 776{
6b986edf
RS		 777 const struct hdmiphy_config *confs;
778 int count, i;
1de425b0 779
6b986edf 780 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2f7e2ed0 781
6b986edf
RS		 782 if (hdata->type == HDMI_TYPE13) {
783 confs = hdmiphy_v13_configs;
784 count = ARRAY_SIZE(hdmiphy_v13_configs);
785 } else if (hdata->type == HDMI_TYPE14) {
786 confs = hdmiphy_v14_configs;
787 count = ARRAY_SIZE(hdmiphy_v14_configs);
788 } else
789 return -EINVAL;
790
791 for (i = 0; i < count; i++)
792 if (confs[i].pixel_clock == pixel_clock)
2f7e2ed0 793 return i;
2f7e2ed0
SP		 794
795 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
796 return -EINVAL;
797}
798
438c0f85 799static int hdmi_check_timing(void *ctx, struct fb_videomode *timing)
3ecd70b1 800{
f9309d1b 801 struct hdmi_context *hdata = ctx;
6b986edf 802 int ret;
3ecd70b1
JS		 803
804 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
805
438c0f85
RS		 806 DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", timing->xres,
807 timing->yres, timing->refresh,
808 timing->vmode);
3ecd70b1 809
6b986edf
RS		 810 ret = hdmi_find_phy_conf(hdata, timing->pixclock);
811 if (ret < 0)
812 return ret;
813 return 0;
3ecd70b1
JS		 814}
815
3e148baf
SWK		 816static void hdmi_set_acr(u32 freq, u8 *acr)
817{
818 u32 n, cts;
819
820 switch (freq) {
821 case 32000:
822 n = 4096;
823 cts = 27000;
824 break;
825 case 44100:
826 n = 6272;
827 cts = 30000;
828 break;
829 case 88200:
830 n = 12544;
831 cts = 30000;
832 break;
833 case 176400:
834 n = 25088;
835 cts = 30000;
836 break;
837 case 48000:
838 n = 6144;
839 cts = 27000;
840 break;
841 case 96000:
842 n = 12288;
843 cts = 27000;
844 break;
845 case 192000:
846 n = 24576;
847 cts = 27000;
848 break;
849 default:
850 n = 0;
851 cts = 0;
852 break;
853 }
854
855 acr[1] = cts >> 16;
856 acr[2] = cts >> 8 & 0xff;
857 acr[3] = cts & 0xff;
858
859 acr[4] = n >> 16;
860 acr[5] = n >> 8 & 0xff;
861 acr[6] = n & 0xff;
862}
863
864static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
865{
866 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
867 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
868 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
869 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
870 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
871 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
872 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
873 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
874 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
875
5a325071 876 if (hdata->type == HDMI_TYPE13)
3e148baf
SWK		 877 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
878 else
879 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
880}
881
882static void hdmi_audio_init(struct hdmi_context *hdata)
883{
884 u32 sample_rate, bits_per_sample, frame_size_code;
885 u32 data_num, bit_ch, sample_frq;
886 u32 val;
887 u8 acr[7];
888
889 sample_rate = 44100;
890 bits_per_sample = 16;
891 frame_size_code = 0;
892
893 switch (bits_per_sample) {
894 case 20:
895 data_num = 2;
896 bit_ch = 1;
897 break;
898 case 24:
899 data_num = 3;
900 bit_ch = 1;
901 break;
902 default:
903 data_num = 1;
904 bit_ch = 0;
905 break;
906 }
907
908 hdmi_set_acr(sample_rate, acr);
909 hdmi_reg_acr(hdata, acr);
910
911 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
912 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
913 | HDMI_I2S_MUX_ENABLE);
914
915 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
916 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
917
918 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
919
920 sample_frq = (sample_rate == 44100) ? 0 :
921 (sample_rate == 48000) ? 2 :
922 (sample_rate == 32000) ? 3 :
923 (sample_rate == 96000) ? 0xa : 0x0;
924
925 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
926 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
927
928 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
929 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
930
931 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
932 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
933 | HDMI_I2S_SEL_LRCK(6));
934 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
935 | HDMI_I2S_SEL_SDATA2(4));
936 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
937 | HDMI_I2S_SEL_SDATA2(2));
938 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
939
940 /* I2S_CON_1 & 2 */
941 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
942 | HDMI_I2S_L_CH_LOW_POL);
943 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
944 | HDMI_I2S_SET_BIT_CH(bit_ch)
945 | HDMI_I2S_SET_SDATA_BIT(data_num)
946 | HDMI_I2S_BASIC_FORMAT);
947
948 /* Configure register related to CUV information */
949 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
950 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
951 | HDMI_I2S_COPYRIGHT
952 | HDMI_I2S_LINEAR_PCM
953 | HDMI_I2S_CONSUMER_FORMAT);
954 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
955 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
956 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
957 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
958 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
959 HDMI_I2S_ORG_SMP_FREQ_44_1
960 | HDMI_I2S_WORD_LEN_MAX24_24BITS
961 | HDMI_I2S_WORD_LEN_MAX_24BITS);
962
963 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
964}
965
966static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
967{
872d20d6 968 if (hdata->dvi_mode)
3e148baf
SWK		 969 return;
970
971 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
972 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
973 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
974}
975
d8408326
SWK		 976static void hdmi_conf_reset(struct hdmi_context *hdata)
977{
3ecd70b1
JS		 978 u32 reg;
979
5a325071 980 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 981 reg = HDMI_V13_CORE_RSTOUT;
982 else
983 reg = HDMI_CORE_RSTOUT;
984
d8408326 985 /* resetting HDMI core */
3ecd70b1 986 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
09760ea3 987 usleep_range(10000, 12000);
3ecd70b1 988 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
09760ea3 989 usleep_range(10000, 12000);
d8408326
SWK		 990}
991
992static void hdmi_conf_init(struct hdmi_context *hdata)
993{
a144c2e9
RS		 994 struct hdmi_infoframe infoframe;
995
77006a7a 996 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
d8408326
SWK		 997 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
998 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
d8408326
SWK		 999
1000 /* choose HDMI mode */
1001 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1002 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1003 /* disable bluescreen */
1004 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
3ecd70b1 1005
872d20d6
SWK		 1006 if (hdata->dvi_mode) {
1007 /* choose DVI mode */
1008 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1009 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1010 hdmi_reg_writeb(hdata, HDMI_CON_2,
1011 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1012 }
1013
5a325071 1014 if (hdata->type == HDMI_TYPE13) {
3ecd70b1
JS		 1015 /* choose bluescreen (fecal) color */
1016 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1017 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1018 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1019
1020 /* enable AVI packet every vsync, fixes purple line problem */
1021 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1022 /* force RGB, look to CEA-861-D, table 7 for more detail */
1023 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1024 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1025
1026 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1027 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1028 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1029 } else {
a144c2e9
RS		 1030 infoframe.type = HDMI_PACKET_TYPE_AVI;
1031 infoframe.ver = HDMI_AVI_VERSION;
1032 infoframe.len = HDMI_AVI_LENGTH;
1033 hdmi_reg_infoframe(hdata, &infoframe);
1034
1035 infoframe.type = HDMI_PACKET_TYPE_AUI;
1036 infoframe.ver = HDMI_AUI_VERSION;
1037 infoframe.len = HDMI_AUI_LENGTH;
1038 hdmi_reg_infoframe(hdata, &infoframe);
1039
3ecd70b1 1040 /* enable AVI packet every vsync, fixes purple line problem */
3ecd70b1
JS		 1041 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1042 }
d8408326
SWK		 1043}
1044
3ecd70b1 1045static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
d8408326 1046{
6b986edf
RS		 1047 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1048 const struct hdmi_v13_core_regs *core =
1049 &hdata->mode_conf.conf.v13_conf.core;
3ecd70b1
JS		 1050 int tries;
1051
1052 /* setting core registers */
1053 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1054 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1055 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1056 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1057 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1058 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1059 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1060 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1061 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1062 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1063 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1064 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1065 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1066 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1067 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1068 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1069 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1070 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1071 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1072 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1073 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1074 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1075 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1076 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1077 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1078 /* Timing generator registers */
6b986edf
RS		 1079 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1080 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1081 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1082 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1083 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1084 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1085 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1086 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1087 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1088 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1089 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1090 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1091 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1092 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1093 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1094 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1095 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1096 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1097 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1098 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1099 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1100 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1101 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1102 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1103 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1104 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1105 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1106 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
3ecd70b1
JS		 1107
1108 /* waiting for HDMIPHY's PLL to get to steady state */
1109 for (tries = 100; tries; --tries) {
1110 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1111 if (val & HDMI_PHY_STATUS_READY)
1112 break;
09760ea3 1113 usleep_range(1000, 2000);
3ecd70b1
JS		 1114 }
1115 /* steady state not achieved */
1116 if (tries == 0) {
1117 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1118 hdmi_regs_dump(hdata, "timing apply");
1119 }
1120
1121 clk_disable(hdata->res.sclk_hdmi);
1122 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1123 clk_enable(hdata->res.sclk_hdmi);
1124
1125 /* enable HDMI and timing generator */
1126 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1127 if (core->int_pro_mode[0])
1128 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1129 HDMI_FIELD_EN);
1130 else
1131 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1132}
1133
1134static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1135{
6b986edf
RS		 1136 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1137 const struct hdmi_v14_core_regs *core =
1138 &hdata->mode_conf.conf.v14_conf.core;
d8408326
SWK		 1139 int tries;
1140
1141 /* setting core registers */
1142 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1143 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
3ecd70b1
JS		 1144 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1145 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1146 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1147 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1148 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1149 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1150 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1151 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1152 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
d8408326
SWK		 1153 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1154 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
3ecd70b1
JS		 1155 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1156 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1157 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1158 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1159 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1160 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1161 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1162 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1163 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1164 core->v_sync_line_bef_2[0]);
1165 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1166 core->v_sync_line_bef_2[1]);
1167 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1168 core->v_sync_line_bef_1[0]);
1169 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1170 core->v_sync_line_bef_1[1]);
1171 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1172 core->v_sync_line_aft_2[0]);
1173 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1174 core->v_sync_line_aft_2[1]);
1175 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1176 core->v_sync_line_aft_1[0]);
1177 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1178 core->v_sync_line_aft_1[1]);
1179 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1180 core->v_sync_line_aft_pxl_2[0]);
1181 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1182 core->v_sync_line_aft_pxl_2[1]);
1183 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1184 core->v_sync_line_aft_pxl_1[0]);
1185 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1186 core->v_sync_line_aft_pxl_1[1]);
1187 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1188 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1189 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1190 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1191 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1192 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1193 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1194 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1195 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1196 core->v_sync_line_aft_3[0]);
1197 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1198 core->v_sync_line_aft_3[1]);
1199 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1200 core->v_sync_line_aft_4[0]);
1201 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1202 core->v_sync_line_aft_4[1]);
1203 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1204 core->v_sync_line_aft_5[0]);
1205 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1206 core->v_sync_line_aft_5[1]);
1207 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1208 core->v_sync_line_aft_6[0]);
1209 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1210 core->v_sync_line_aft_6[1]);
1211 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1212 core->v_sync_line_aft_pxl_3[0]);
1213 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1214 core->v_sync_line_aft_pxl_3[1]);
1215 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1216 core->v_sync_line_aft_pxl_4[0]);
1217 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1218 core->v_sync_line_aft_pxl_4[1]);
1219 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1220 core->v_sync_line_aft_pxl_5[0]);
1221 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1222 core->v_sync_line_aft_pxl_5[1]);
1223 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1224 core->v_sync_line_aft_pxl_6[0]);
1225 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1226 core->v_sync_line_aft_pxl_6[1]);
1227 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1228 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1229 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1230 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1231 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1232 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1233 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1234 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1235 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1236 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1237 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1238 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1239
d8408326 1240 /* Timing generator registers */
2f7e2ed0
SP		 1241 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1242 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1243 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1244 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1245 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1246 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1247 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1248 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1249 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1250 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1251 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1252 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1253 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1254 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1255 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1256 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1257 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1258 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1259 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1260 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1261 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1262 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1263 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1264 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1265 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1266 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1267 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1268 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1269 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1270 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1271 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1272 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1273 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
d8408326
SWK		 1274
1275 /* waiting for HDMIPHY's PLL to get to steady state */
1276 for (tries = 100; tries; --tries) {
3ecd70b1 1277 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
d8408326
SWK		 1278 if (val & HDMI_PHY_STATUS_READY)
1279 break;
09760ea3 1280 usleep_range(1000, 2000);
d8408326
SWK		 1281 }
1282 /* steady state not achieved */
1283 if (tries == 0) {
1284 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1285 hdmi_regs_dump(hdata, "timing apply");
1286 }
1287
1288 clk_disable(hdata->res.sclk_hdmi);
1289 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1290 clk_enable(hdata->res.sclk_hdmi);
1291
1292 /* enable HDMI and timing generator */
1293 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1294 if (core->int_pro_mode[0])
1295 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1296 HDMI_FIELD_EN);
1297 else
1298 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1299}
1300
3ecd70b1
JS		 1301static void hdmi_timing_apply(struct hdmi_context *hdata)
1302{
5a325071 1303 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 1304 hdmi_v13_timing_apply(hdata);
1305 else
1306 hdmi_v14_timing_apply(hdata);
1307}
1308
d8408326
SWK		 1309static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1310{
1311 u8 buffer[2];
3ecd70b1 1312 u32 reg;
d8408326
SWK		 1313
1314 clk_disable(hdata->res.sclk_hdmi);
1315 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1316 clk_enable(hdata->res.sclk_hdmi);
1317
1318 /* operation mode */
1319 buffer[0] = 0x1f;
1320 buffer[1] = 0x00;
1321
1322 if (hdata->hdmiphy_port)
1323 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1324
5a325071 1325 if (hdata->type == HDMI_TYPE13)
3ecd70b1
JS		 1326 reg = HDMI_V13_PHY_RSTOUT;
1327 else
1328 reg = HDMI_PHY_RSTOUT;
1329
d8408326 1330 /* reset hdmiphy */
3ecd70b1 1331 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
09760ea3 1332 usleep_range(10000, 12000);
3ecd70b1 1333 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
09760ea3 1334 usleep_range(10000, 12000);
d8408326
SWK		 1335}
1336
a5562257
RS		 1337static void hdmiphy_poweron(struct hdmi_context *hdata)
1338{
1339 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1340
1341 if (hdata->type == HDMI_TYPE14)
1342 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1343 HDMI_PHY_POWER_OFF_EN);
1344}
1345
1346static void hdmiphy_poweroff(struct hdmi_context *hdata)
1347{
1348 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1349
1350 if (hdata->type == HDMI_TYPE14)
1351 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1352 HDMI_PHY_POWER_OFF_EN);
1353}
1354
d8408326
SWK		 1355static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1356{
3ecd70b1 1357 const u8 *hdmiphy_data;
d8408326
SWK		 1358 u8 buffer[32];
1359 u8 operation[2];
1360 u8 read_buffer[32] = {0, };
1361 int ret;
1362 int i;
1363
1364 if (!hdata->hdmiphy_port) {
1365 DRM_ERROR("hdmiphy is not attached\n");
1366 return;
1367 }
1368
1369 /* pixel clock */
6b986edf
RS		 1370 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1371 if (i < 0) {
1372 DRM_ERROR("failed to find hdmiphy conf\n");
1373 return;
1374 }
1375
5f46c333 1376 if (hdata->type == HDMI_TYPE13)
6b986edf 1377 hdmiphy_data = hdmiphy_v13_configs[i].conf;
5f46c333 1378 else
2f7e2ed0 1379 hdmiphy_data = hdmiphy_v14_configs[i].conf;
3ecd70b1
JS		 1380
1381 memcpy(buffer, hdmiphy_data, 32);
d8408326
SWK		 1382 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1383 if (ret != 32) {
1384 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1385 return;
1386 }
1387
09760ea3 1388 usleep_range(10000, 12000);
d8408326
SWK		 1389
1390 /* operation mode */
1391 operation[0] = 0x1f;
1392 operation[1] = 0x80;
1393
1394 ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1395 if (ret != 2) {
1396 DRM_ERROR("failed to enable hdmiphy\n");
1397 return;
1398 }
1399
1400 ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1401 if (ret < 0) {
1402 DRM_ERROR("failed to read hdmiphy config\n");
1403 return;
1404 }
1405
1406 for (i = 0; i < ret; i++)
1407 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1408 "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1409}
1410
1411static void hdmi_conf_apply(struct hdmi_context *hdata)
1412{
d8408326
SWK		 1413 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1414
1415 hdmiphy_conf_reset(hdata);
1416 hdmiphy_conf_apply(hdata);
1417
cf8fc4f1 1418 mutex_lock(&hdata->hdmi_mutex);
d8408326
SWK		 1419 hdmi_conf_reset(hdata);
1420 hdmi_conf_init(hdata);
cf8fc4f1
JS		 1421 mutex_unlock(&hdata->hdmi_mutex);
1422
3e148baf 1423 hdmi_audio_init(hdata);
d8408326
SWK		 1424
1425 /* setting core registers */
3ecd70b1 1426 hdmi_timing_apply(hdata);
3e148baf 1427 hdmi_audio_control(hdata, true);
d8408326
SWK		 1428
1429 hdmi_regs_dump(hdata, "start");
1430}
1431
2f7e2ed0
SP		 1432static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1433{
1434 int i;
1435 BUG_ON(num_bytes > 4);
1436 for (i = 0; i < num_bytes; i++)
1437 reg_pair[i] = (value >> (8 * i)) & 0xff;
1438}
1439
6b986edf 1440static void hdmi_v13_mode_set(struct hdmi_context *hdata,
2f7e2ed0
SP		 1441 struct drm_display_mode *m)
1442{
6b986edf
RS		 1443 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1444 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1445 unsigned int val;
2f7e2ed0 1446
6b986edf
RS		 1447 hdata->mode_conf.cea_video_id =
1448 drm_match_cea_mode((struct drm_display_mode *)m);
1449 hdata->mode_conf.pixel_clock = m->clock * 1000;
1450
1451 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1452 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1453
1454 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1455 hdmi_set_reg(core->vsync_pol, 1, val);
1456
1457 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1458 hdmi_set_reg(core->int_pro_mode, 1, val);
1459
1460 val = (m->hsync_start - m->hdisplay - 2);
1461 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1462 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1463 hdmi_set_reg(core->h_sync_gen, 3, val);
1464
1465 /*
1466 * Quirk requirement for exynos HDMI IP design,
1467 * 2 pixels less than the actual calculation for hsync_start
1468 * and end.
1469 */
1470
1471 /* Following values & calculations differ for different type of modes */
1472 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1473 /* Interlaced Mode */
1474 val = ((m->vsync_end - m->vdisplay) / 2);
1475 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1476 hdmi_set_reg(core->v_sync_gen1, 3, val);
1477
1478 val = m->vtotal / 2;
1479 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1480 hdmi_set_reg(core->v_blank, 3, val);
1481
1482 val = (m->vtotal +
1483 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1484 val |= m->vtotal << 11;
1485 hdmi_set_reg(core->v_blank_f, 3, val);
1486
1487 val = ((m->vtotal / 2) + 7);
1488 val |= ((m->vtotal / 2) + 2) << 12;
1489 hdmi_set_reg(core->v_sync_gen2, 3, val);
1490
1491 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1492 val |= ((m->htotal / 2) +
1493 (m->hsync_start - m->hdisplay)) << 12;
1494 hdmi_set_reg(core->v_sync_gen3, 3, val);
1495
1496 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1497 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1498
1499 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1500 } else {
1501 /* Progressive Mode */
1502
1503 val = m->vtotal;
1504 val |= (m->vtotal - m->vdisplay) << 11;
1505 hdmi_set_reg(core->v_blank, 3, val);
1506
1507 hdmi_set_reg(core->v_blank_f, 3, 0);
2f7e2ed0 1508
6b986edf
RS		 1509 val = (m->vsync_end - m->vdisplay);
1510 val |= ((m->vsync_start - m->vdisplay) << 12);
1511 hdmi_set_reg(core->v_sync_gen1, 3, val);
1512
1513 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1514 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1515 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1516 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1517 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1518 }
1519
1520 /* Timing generator registers */
1521 hdmi_set_reg(tg->cmd, 1, 0x0);
1522 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1523 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1524 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1525 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1526 hdmi_set_reg(tg->vsync, 2, 0x1);
1527 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1528 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1529 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1530 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1531 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1532 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1533 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1534}
1535
1536static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1537 struct drm_display_mode *m)
1538{
1539 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1540 struct hdmi_v14_core_regs *core =
1541 &hdata->mode_conf.conf.v14_conf.core;
1542
1543 hdata->mode_conf.cea_video_id =
1544 drm_match_cea_mode((struct drm_display_mode *)m);
2f7e2ed0 1545 hdata->mode_conf.pixel_clock = m->clock * 1000;
6b986edf 1546
2f7e2ed0
SP		 1547 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1548 hdmi_set_reg(core->v_line, 2, m->vtotal);
1549 hdmi_set_reg(core->h_line, 2, m->htotal);
1550 hdmi_set_reg(core->hsync_pol, 1,
1551 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1552 hdmi_set_reg(core->vsync_pol, 1,
1553 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1554 hdmi_set_reg(core->int_pro_mode, 1,
1555 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1556
1557 /*
1558 * Quirk requirement for exynos 5 HDMI IP design,
1559 * 2 pixels less than the actual calculation for hsync_start
1560 * and end.
1561 */
1562
1563 /* Following values & calculations differ for different type of modes */
1564 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1565 /* Interlaced Mode */
1566 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1567 (m->vsync_end - m->vdisplay) / 2);
1568 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1569 (m->vsync_start - m->vdisplay) / 2);
1570 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1571 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1572 hdmi_set_reg(core->v_blank_f0, 2, (m->vtotal +
1573 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1574 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1575 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1576 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1577 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1578 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1579 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1580 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1581 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1582 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1583 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1584 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1585 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1586 } else {
1587 /* Progressive Mode */
1588 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1589 m->vsync_end - m->vdisplay);
1590 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1591 m->vsync_start - m->vdisplay);
1592 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1593 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1594 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1595 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1596 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1597 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1598 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1599 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1600 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1601 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1602 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1603 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1604 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1605 }
1606
1607 /* Following values & calculations are same irrespective of mode type */
1608 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1609 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1610 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1611 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1612 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1613 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1614 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1615 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1616 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1617 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1618 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1619 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1620 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1621 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1622 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1623 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1624 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1625 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1626 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1627 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1628
1629 /* Timing generator registers */
1630 hdmi_set_reg(tg->cmd, 1, 0x0);
1631 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1632 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1633 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1634 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1635 hdmi_set_reg(tg->vsync, 2, 0x1);
1636 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1637 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1638 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1639 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1640 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1641 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1642 hdmi_set_reg(tg->tg_3d, 1, 0x0);
2f7e2ed0
SP		 1643}
1644
d8408326
SWK		 1645static void hdmi_mode_set(void *ctx, void *mode)
1646{
f9309d1b 1647 struct hdmi_context *hdata = ctx;
6b986edf 1648 struct drm_display_mode *m = mode;
d8408326 1649
6b986edf
RS		 1650 DRM_DEBUG_KMS("[%s]: xres=%d, yres=%d, refresh=%d, intl=%s\n",
1651 __func__, m->hdisplay, m->vdisplay,
1652 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1653 "INTERLACED" : "PROGERESSIVE");
d8408326 1654
5f46c333 1655 if (hdata->type == HDMI_TYPE13)
6b986edf 1656 hdmi_v13_mode_set(hdata, mode);
5f46c333 1657 else
2f7e2ed0 1658 hdmi_v14_mode_set(hdata, mode);
d8408326
SWK		 1659}
1660
1de425b0
ID		 1661static void hdmi_get_max_resol(void *ctx, unsigned int *width,
1662 unsigned int *height)
1663{
1664 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1665
1666 *width = MAX_WIDTH;
1667 *height = MAX_HEIGHT;
1668}
1669
d8408326
SWK		 1670static void hdmi_commit(void *ctx)
1671{
f9309d1b 1672 struct hdmi_context *hdata = ctx;
d8408326
SWK		 1673
1674 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1675
dda9012b
S		 1676 mutex_lock(&hdata->hdmi_mutex);
1677 if (!hdata->powered) {
1678 mutex_unlock(&hdata->hdmi_mutex);
1679 return;
1680 }
1681 mutex_unlock(&hdata->hdmi_mutex);
1682
d8408326 1683 hdmi_conf_apply(hdata);
cf8fc4f1
JS		 1684}
1685
1686static void hdmi_poweron(struct hdmi_context *hdata)
1687{
1688 struct hdmi_resources *res = &hdata->res;
1689
1690 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1691
1692 mutex_lock(&hdata->hdmi_mutex);
1693 if (hdata->powered) {
1694 mutex_unlock(&hdata->hdmi_mutex);
1695 return;
1696 }
d8408326 1697
cf8fc4f1
JS		 1698 hdata->powered = true;
1699
cf8fc4f1
JS		 1700 mutex_unlock(&hdata->hdmi_mutex);
1701
cf8fc4f1
JS		 1702 regulator_bulk_enable(res->regul_count, res->regul_bulk);
1703 clk_enable(res->hdmiphy);
1704 clk_enable(res->hdmi);
1705 clk_enable(res->sclk_hdmi);
a5562257
RS		 1706
1707 hdmiphy_poweron(hdata);
cf8fc4f1
JS		 1708}
1709
1710static void hdmi_poweroff(struct hdmi_context *hdata)
1711{
1712 struct hdmi_resources *res = &hdata->res;
1713
1714 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1715
1716 mutex_lock(&hdata->hdmi_mutex);
1717 if (!hdata->powered)
1718 goto out;
1719 mutex_unlock(&hdata->hdmi_mutex);
1720
1721 /*
1722 * The TV power domain needs any condition of hdmiphy to turn off and
1723 * its reset state seems to meet the condition.
1724 */
1725 hdmiphy_conf_reset(hdata);
a5562257 1726 hdmiphy_poweroff(hdata);
cf8fc4f1
JS		 1727
1728 clk_disable(res->sclk_hdmi);
1729 clk_disable(res->hdmi);
1730 clk_disable(res->hdmiphy);
1731 regulator_bulk_disable(res->regul_count, res->regul_bulk);
1732
cf8fc4f1 1733 mutex_lock(&hdata->hdmi_mutex);
cf8fc4f1
JS		 1734
1735 hdata->powered = false;
1736
1737out:
1738 mutex_unlock(&hdata->hdmi_mutex);
d8408326
SWK		 1739}
1740
cf8fc4f1 1741static void hdmi_dpms(void *ctx, int mode)
d8408326 1742{
f9309d1b 1743 struct hdmi_context *hdata = ctx;
d8408326 1744
64327cb3 1745 DRM_DEBUG_KMS("[%d] %s mode %d\n", __LINE__, __func__, mode);
d8408326 1746
cf8fc4f1
JS		 1747 switch (mode) {
1748 case DRM_MODE_DPMS_ON:
64327cb3
RS		 1749 if (pm_runtime_suspended(hdata->dev))
1750 pm_runtime_get_sync(hdata->dev);
cf8fc4f1
JS		 1751 break;
1752 case DRM_MODE_DPMS_STANDBY:
1753 case DRM_MODE_DPMS_SUSPEND:
1754 case DRM_MODE_DPMS_OFF:
64327cb3
RS		 1755 if (!pm_runtime_suspended(hdata->dev))
1756 pm_runtime_put_sync(hdata->dev);
cf8fc4f1
JS		 1757 break;
1758 default:
1759 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1760 break;
d8408326
SWK		 1761 }
1762}
1763
578b6065
JS		 1764static struct exynos_hdmi_ops hdmi_ops = {
1765 /* display */
1766 .is_connected = hdmi_is_connected,
1767 .get_edid = hdmi_get_edid,
1768 .check_timing = hdmi_check_timing,
578b6065
JS		 1769
1770 /* manager */
d8408326 1771 .mode_set = hdmi_mode_set,
1de425b0 1772 .get_max_resol = hdmi_get_max_resol,
d8408326 1773 .commit = hdmi_commit,
cf8fc4f1 1774 .dpms = hdmi_dpms,
d8408326
SWK		 1775};
1776
77006a7a 1777static irqreturn_t hdmi_irq_thread(int irq, void *arg)
cf8fc4f1
JS		 1778{
1779 struct exynos_drm_hdmi_context *ctx = arg;
1780 struct hdmi_context *hdata = ctx->ctx;
1781
cf8fc4f1 1782 mutex_lock(&hdata->hdmi_mutex);
fca57122 1783 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
cf8fc4f1
JS		 1784 mutex_unlock(&hdata->hdmi_mutex);
1785
1786 if (ctx->drm_dev)
1787 drm_helper_hpd_irq_event(ctx->drm_dev);
1788
cf8fc4f1
JS		 1789 return IRQ_HANDLED;
1790}
1791
56550d94 1792static int hdmi_resources_init(struct hdmi_context *hdata)
d8408326
SWK		 1793{
1794 struct device *dev = hdata->dev;
1795 struct hdmi_resources *res = &hdata->res;
1796 static char *supply[] = {
1797 "hdmi-en",
1798 "vdd",
1799 "vdd_osc",
1800 "vdd_pll",
1801 };
1802 int i, ret;
1803
1804 DRM_DEBUG_KMS("HDMI resource init\n");
1805
adc837ac 1806 memset(res, 0, sizeof(*res));
d8408326
SWK		 1807
1808 /* get clocks, power */
9f49d9fb 1809 res->hdmi = devm_clk_get(dev, "hdmi");
ee7cbafa 1810 if (IS_ERR(res->hdmi)) {
d8408326
SWK		 1811 DRM_ERROR("failed to get clock 'hdmi'\n");
1812 goto fail;
1813 }
9f49d9fb 1814 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
ee7cbafa 1815 if (IS_ERR(res->sclk_hdmi)) {
d8408326
SWK		 1816 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1817 goto fail;
1818 }
9f49d9fb 1819 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
ee7cbafa 1820 if (IS_ERR(res->sclk_pixel)) {
d8408326
SWK		 1821 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1822 goto fail;
1823 }
9f49d9fb 1824 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
ee7cbafa 1825 if (IS_ERR(res->sclk_hdmiphy)) {
d8408326
SWK		 1826 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1827 goto fail;
1828 }
9f49d9fb 1829 res->hdmiphy = devm_clk_get(dev, "hdmiphy");
ee7cbafa 1830 if (IS_ERR(res->hdmiphy)) {
d8408326
SWK		 1831 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1832 goto fail;
1833 }
1834
1835 clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
1836
9f49d9fb 1837 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
adc837ac 1838 sizeof(res->regul_bulk[0]), GFP_KERNEL);
d8408326
SWK		 1839 if (!res->regul_bulk) {
1840 DRM_ERROR("failed to get memory for regulators\n");
1841 goto fail;
1842 }
1843 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1844 res->regul_bulk[i].supply = supply[i];
1845 res->regul_bulk[i].consumer = NULL;
1846 }
9f49d9fb 1847 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
d8408326
SWK		 1848 if (ret) {
1849 DRM_ERROR("failed to get regulators\n");
1850 goto fail;
1851 }
1852 res->regul_count = ARRAY_SIZE(supply);
1853
1854 return 0;
1855fail:
1856 DRM_ERROR("HDMI resource init - failed\n");
1857 return -ENODEV;
1858}
1859
d8408326
SWK		 1860static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
1861
1862void hdmi_attach_ddc_client(struct i2c_client *ddc)
1863{
1864 if (ddc)
1865 hdmi_ddc = ddc;
1866}
d8408326
SWK		 1867
1868void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
1869{
1870 if (hdmiphy)
1871 hdmi_hdmiphy = hdmiphy;
1872}
d8408326 1873
22c4f428
RS		 1874#ifdef CONFIG_OF
1875static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
1876 (struct device *dev)
1877{
1878 struct device_node *np = dev->of_node;
1879 struct s5p_hdmi_platform_data *pd;
1880 enum of_gpio_flags flags;
1881 u32 value;
1882
1883 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1884 if (!pd) {
1885 DRM_ERROR("memory allocation for pdata failed\n");
1886 goto err_data;
1887 }
1888
1889 if (!of_find_property(np, "hpd-gpio", &value)) {
1890 DRM_ERROR("no hpd gpio property found\n");
1891 goto err_data;
1892 }
1893
1894 pd->hpd_gpio = of_get_named_gpio_flags(np, "hpd-gpio", 0, &flags);
1895
1896 return pd;
1897
1898err_data:
1899 return NULL;
1900}
1901#else
1902static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
1903 (struct device *dev)
1904{
1905 return NULL;
1906}
1907#endif
1908
c119ed05
TS		 1909static struct platform_device_id hdmi_driver_types[] = {
1910 {
1911 .name = "s5pv210-hdmi",
1912 .driver_data = HDMI_TYPE13,
1913 }, {
1914 .name = "exynos4-hdmi",
1915 .driver_data = HDMI_TYPE13,
1916 }, {
1917 .name = "exynos4-hdmi14",
22c4f428
RS		 1918 .driver_data = HDMI_TYPE14,
1919 }, {
1920 .name = "exynos5-hdmi",
1921 .driver_data = HDMI_TYPE14,
1922 }, {
1923 /* end node */
1924 }
1925};
1926
65da0350 1927#ifdef CONFIG_OF
22c4f428
RS		 1928static struct of_device_id hdmi_match_types[] = {
1929 {
1930 .compatible = "samsung,exynos5-hdmi",
1931 .data = (void *)HDMI_TYPE14,
c119ed05
TS		 1932 }, {
1933 /* end node */
1934 }
1935};
65da0350 1936#endif
c119ed05 1937
56550d94 1938static int hdmi_probe(struct platform_device *pdev)
d8408326
SWK		 1939{
1940 struct device *dev = &pdev->dev;
1941 struct exynos_drm_hdmi_context *drm_hdmi_ctx;
1942 struct hdmi_context *hdata;
fca57122 1943 struct s5p_hdmi_platform_data *pdata;
d8408326
SWK		 1944 struct resource *res;
1945 int ret;
1946
1947 DRM_DEBUG_KMS("[%d]\n", __LINE__);
1948
d873ab99 1949 if (dev->of_node) {
22c4f428
RS		 1950 pdata = drm_hdmi_dt_parse_pdata(dev);
1951 if (IS_ERR(pdata)) {
1952 DRM_ERROR("failed to parse dt\n");
1953 return PTR_ERR(pdata);
1954 }
1955 } else {
d873ab99 1956 pdata = dev->platform_data;
22c4f428
RS		 1957 }
1958
d8408326
SWK		 1959 if (!pdata) {
1960 DRM_ERROR("no platform data specified\n");
1961 return -EINVAL;
1962 }
1963
d873ab99 1964 drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
a6e65072 1965 GFP_KERNEL);
d8408326
SWK		 1966 if (!drm_hdmi_ctx) {
1967 DRM_ERROR("failed to allocate common hdmi context.\n");
1968 return -ENOMEM;
1969 }
1970
d873ab99 1971 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context),
a6e65072 1972 GFP_KERNEL);
d8408326
SWK		 1973 if (!hdata) {
1974 DRM_ERROR("out of memory\n");
d8408326
SWK		 1975 return -ENOMEM;
1976 }
1977
cf8fc4f1
JS		 1978 mutex_init(&hdata->hdmi_mutex);
1979
d8408326
SWK		 1980 drm_hdmi_ctx->ctx = (void *)hdata;
1981 hdata->parent_ctx = (void *)drm_hdmi_ctx;
1982
1983 platform_set_drvdata(pdev, drm_hdmi_ctx);
1984
22c4f428
RS		 1985 if (dev->of_node) {
1986 const struct of_device_id *match;
1987 match = of_match_node(of_match_ptr(hdmi_match_types),
d873ab99 1988 dev->of_node);
1a4513b3
SK		 1989 if (match == NULL)
1990 return -ENODEV;
22c4f428
RS		 1991 hdata->type = (enum hdmi_type)match->data;
1992 } else {
1993 hdata->type = (enum hdmi_type)platform_get_device_id
5a325071 1994 (pdev)->driver_data;
22c4f428
RS		 1995 }
1996
fca57122 1997 hdata->hpd_gpio = pdata->hpd_gpio;
d8408326
SWK		 1998 hdata->dev = dev;
1999
2000 ret = hdmi_resources_init(hdata);
22c4f428 2001
d8408326 2002 if (ret) {
22c4f428 2003 DRM_ERROR("hdmi_resources_init failed\n");
9f49d9fb 2004 return -EINVAL;
d8408326
SWK		 2005 }
2006
2007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d873ab99 2008 hdata->regs = devm_ioremap_resource(dev, res);
d4ed6025
TR		 2009 if (IS_ERR(hdata->regs))
2010 return PTR_ERR(hdata->regs);
d8408326 2011
d873ab99 2012 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
fca57122
TS		 2013 if (ret) {
2014 DRM_ERROR("failed to request HPD gpio\n");
9f49d9fb 2015 return ret;
fca57122
TS		 2016 }
2017
d8408326
SWK		 2018 /* DDC i2c driver */
2019 if (i2c_add_driver(&ddc_driver)) {
2020 DRM_ERROR("failed to register ddc i2c driver\n");
9f49d9fb 2021 return -ENOENT;
d8408326
SWK		 2022 }
2023
2024 hdata->ddc_port = hdmi_ddc;
2025
2026 /* hdmiphy i2c driver */
2027 if (i2c_add_driver(&hdmiphy_driver)) {
2028 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2029 ret = -ENOENT;
2030 goto err_ddc;
2031 }
2032
2033 hdata->hdmiphy_port = hdmi_hdmiphy;
2034
77006a7a
SP		 2035 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2036 if (hdata->irq < 0) {
2037 DRM_ERROR("failed to get GPIO irq\n");
2038 ret = hdata->irq;
cf8fc4f1
JS		 2039 goto err_hdmiphy;
2040 }
2041
fca57122
TS		 2042 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2043
dcb9a7c7 2044 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
77006a7a 2045 hdmi_irq_thread, IRQF_TRIGGER_RISING |
cf8fc4f1 2046 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
77006a7a 2047 "hdmi", drm_hdmi_ctx);
d8408326 2048 if (ret) {
77006a7a 2049 DRM_ERROR("failed to register hdmi interrupt\n");
66265a2e 2050 goto err_hdmiphy;
d8408326 2051 }
d8408326 2052
768c3059
RS		 2053 /* Attach HDMI Driver to common hdmi. */
2054 exynos_hdmi_drv_attach(drm_hdmi_ctx);
2055
d8408326 2056 /* register specific callbacks to common hdmi. */
578b6065 2057 exynos_hdmi_ops_register(&hdmi_ops);
d8408326 2058
cf8fc4f1 2059 pm_runtime_enable(dev);
d8408326
SWK		 2060
2061 return 0;
2062
d8408326
SWK		 2063err_hdmiphy:
2064 i2c_del_driver(&hdmiphy_driver);
2065err_ddc:
2066 i2c_del_driver(&ddc_driver);
d8408326
SWK		 2067 return ret;
2068}
2069
56550d94 2070static int hdmi_remove(struct platform_device *pdev)
d8408326 2071{
cf8fc4f1 2072 struct device *dev = &pdev->dev;
d8408326
SWK		 2073
2074 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2075
cf8fc4f1 2076 pm_runtime_disable(dev);
d8408326 2077
d8408326
SWK		 2078 /* hdmiphy i2c driver */
2079 i2c_del_driver(&hdmiphy_driver);
2080 /* DDC i2c driver */
2081 i2c_del_driver(&ddc_driver);
2082
d8408326
SWK		 2083 return 0;
2084}
2085
ab27af85
JS		 2086#ifdef CONFIG_PM_SLEEP
2087static int hdmi_suspend(struct device *dev)
2088{
2089 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2090 struct hdmi_context *hdata = ctx->ctx;
2091
64327cb3
RS		 2092 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2093
77006a7a 2094 disable_irq(hdata->irq);
ab27af85
JS		 2095
2096 hdata->hpd = false;
2097 if (ctx->drm_dev)
2098 drm_helper_hpd_irq_event(ctx->drm_dev);
2099
64327cb3
RS		 2100 if (pm_runtime_suspended(dev)) {
2101 DRM_DEBUG_KMS("%s : Already suspended\n", __func__);
2102 return 0;
2103 }
2104
ab27af85
JS		 2105 hdmi_poweroff(hdata);
2106
2107 return 0;
2108}
2109
2110static int hdmi_resume(struct device *dev)
2111{
2112 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2113 struct hdmi_context *hdata = ctx->ctx;
2114
64327cb3
RS		 2115 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2116
2117 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2118
77006a7a 2119 enable_irq(hdata->irq);
64327cb3
RS		 2120
2121 if (!pm_runtime_suspended(dev)) {
2122 DRM_DEBUG_KMS("%s : Already resumed\n", __func__);
2123 return 0;
2124 }
2125
2126 hdmi_poweron(hdata);
2127
2128 return 0;
2129}
2130#endif
2131
2132#ifdef CONFIG_PM_RUNTIME
2133static int hdmi_runtime_suspend(struct device *dev)
2134{
2135 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2136 struct hdmi_context *hdata = ctx->ctx;
2137 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2138
2139 hdmi_poweroff(hdata);
2140
2141 return 0;
2142}
2143
2144static int hdmi_runtime_resume(struct device *dev)
2145{
2146 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2147 struct hdmi_context *hdata = ctx->ctx;
2148 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2149
2150 hdmi_poweron(hdata);
2151
ab27af85
JS		 2152 return 0;
2153}
2154#endif
2155
64327cb3
RS		 2156static const struct dev_pm_ops hdmi_pm_ops = {
2157 SET_SYSTEM_SLEEP_PM_OPS(hdmi_suspend, hdmi_resume)
2158 SET_RUNTIME_PM_OPS(hdmi_runtime_suspend, hdmi_runtime_resume, NULL)
2159};
ab27af85 2160
d8408326
SWK		 2161struct platform_driver hdmi_driver = {
2162 .probe = hdmi_probe,
56550d94 2163 .remove = hdmi_remove,
c119ed05 2164 .id_table = hdmi_driver_types,
d8408326 2165 .driver = {
22c4f428 2166 .name = "exynos-hdmi",
d8408326 2167 .owner = THIS_MODULE,
ab27af85 2168 .pm = &hdmi_pm_ops,
65da0350 2169 .of_match_table = of_match_ptr(hdmi_match_types),
d8408326
SWK		 2170 },
2171};
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