]> git.proxmox.com Git - mirror_ubuntu-kernels.git/blame - drivers/gpu/drm/gma500/cdv_intel_dp.c
projects / mirror_ubuntu-kernels.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[mirror_ubuntu-kernels.git] / drivers / gpu / drm / gma500 / cdv_intel_dp.c
CommitLineData
8695b612
AC		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
612a9aab
LT		 30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
8695b612
AC		 33#include "psb_drv.h"
34#include "psb_intel_drv.h"
8695b612 35#include "psb_intel_reg.h"
612a9aab 36#include <drm/drm_dp_helper.h>
8695b612 37
d112a816
ZY		 38#define _wait_for(COND, MS, W) ({ \
39 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
40 int ret__ = 0; \
41 while (! (COND)) { \
42 if (time_after(jiffies, timeout__)) { \
43 ret__ = -ETIMEDOUT; \
44 break; \
45 } \
46 if (W && !in_dbg_master()) msleep(W); \
47 } \
48 ret__; \
49})
50
51#define wait_for(COND, MS) _wait_for(COND, MS, 1)
8695b612
AC		 52
53#define DP_LINK_STATUS_SIZE 6
54#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
55
56#define DP_LINK_CONFIGURATION_SIZE 9
57
58#define CDV_FAST_LINK_TRAIN 1
59
37e7b184 60struct cdv_intel_dp {
8695b612
AC		 61 uint32_t output_reg;
62 uint32_t DP;
63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
64 bool has_audio;
65 int force_audio;
66 uint32_t color_range;
67 uint8_t link_bw;
68 uint8_t lane_count;
69 uint8_t dpcd[4];
37e7b184 70 struct psb_intel_encoder *encoder;
8695b612
AC		 71 struct i2c_adapter adapter;
72 struct i2c_algo_dp_aux_data algo;
73 uint8_t train_set[4];
74 uint8_t link_status[DP_LINK_STATUS_SIZE];
d112a816
ZY		 75 int panel_power_up_delay;
76 int panel_power_down_delay;
77 int panel_power_cycle_delay;
78 int backlight_on_delay;
79 int backlight_off_delay;
80 struct drm_display_mode *panel_fixed_mode; /* for eDP */
81 bool panel_on;
8695b612
AC		 82};
83
84struct ddi_regoff {
85 uint32_t PreEmph1;
86 uint32_t PreEmph2;
87 uint32_t VSwing1;
88 uint32_t VSwing2;
89 uint32_t VSwing3;
90 uint32_t VSwing4;
91 uint32_t VSwing5;
92};
93
94static struct ddi_regoff ddi_DP_train_table[] = {
95 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
96 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
97 .VSwing5 = 0x8158,},
98 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
99 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
100 .VSwing5 = 0x8258,},
101};
102
103static uint32_t dp_vswing_premph_table[] = {
104 0x55338954, 0x4000,
105 0x554d8954, 0x2000,
106 0x55668954, 0,
107 0x559ac0d4, 0x6000,
108};
109/**
110 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
111 * @intel_dp: DP struct
112 *
113 * If a CPU or PCH DP output is attached to an eDP panel, this function
114 * will return true, and false otherwise.
115 */
37e7b184 116static bool is_edp(struct psb_intel_encoder *encoder)
8695b612 117{
37e7b184 118 return encoder->type == INTEL_OUTPUT_EDP;
8695b612
AC		 119}
120
121
37e7b184
AC		 122static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
123static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
124static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
8695b612
AC		 125
126static int
37e7b184 127cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
8695b612 128{
37e7b184 129 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 130 int max_lane_count = 4;
131
132 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
133 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
134 switch (max_lane_count) {
135 case 1: case 2: case 4:
136 break;
137 default:
138 max_lane_count = 4;
139 }
140 }
141 return max_lane_count;
142}
143
144static int
37e7b184 145cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
8695b612 146{
37e7b184 147 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 148 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
149
150 switch (max_link_bw) {
151 case DP_LINK_BW_1_62:
152 case DP_LINK_BW_2_7:
153 break;
154 default:
155 max_link_bw = DP_LINK_BW_1_62;
156 break;
157 }
158 return max_link_bw;
159}
160
161static int
37e7b184 162cdv_intel_dp_link_clock(uint8_t link_bw)
8695b612
AC		 163{
164 if (link_bw == DP_LINK_BW_2_7)
165 return 270000;
166 else
167 return 162000;
168}
169
170static int
37e7b184 171cdv_intel_dp_link_required(int pixel_clock, int bpp)
8695b612
AC		 172{
173 return (pixel_clock * bpp + 7) / 8;
174}
175
176static int
37e7b184 177cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
8695b612
AC		 178{
179 return (max_link_clock * max_lanes * 19) / 20;
180}
181
d112a816
ZY		 182static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder)
183{
184 struct drm_device *dev = intel_encoder->base.dev;
185 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
186 u32 pp;
187
188 if (intel_dp->panel_on) {
189 DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
190 return;
191 }
192 DRM_DEBUG_KMS("\n");
193
194 pp = REG_READ(PP_CONTROL);
195
196 pp |= EDP_FORCE_VDD;
197 REG_WRITE(PP_CONTROL, pp);
198 REG_READ(PP_CONTROL);
199 msleep(intel_dp->panel_power_up_delay);
200}
201
202static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder)
203{
204 struct drm_device *dev = intel_encoder->base.dev;
205 u32 pp;
206
207 DRM_DEBUG_KMS("\n");
208 pp = REG_READ(PP_CONTROL);
209
210 pp &= ~EDP_FORCE_VDD;
211 REG_WRITE(PP_CONTROL, pp);
212 REG_READ(PP_CONTROL);
213
214}
215
216/* Returns true if the panel was already on when called */
217static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder)
218{
219 struct drm_device *dev = intel_encoder->base.dev;
220 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
221 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
222
223 if (intel_dp->panel_on)
224 return true;
225
226 DRM_DEBUG_KMS("\n");
227 pp = REG_READ(PP_CONTROL);
228 pp &= ~PANEL_UNLOCK_MASK;
229
230 pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);
231 REG_WRITE(PP_CONTROL, pp);
232 REG_READ(PP_CONTROL);
233
234 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
235 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
236 intel_dp->panel_on = false;
237 } else
238 intel_dp->panel_on = true;
239 msleep(intel_dp->panel_power_up_delay);
240
241 return false;
242}
243
244static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder)
245{
246 struct drm_device *dev = intel_encoder->base.dev;
247 u32 pp, idle_off_mask = PP_ON ;
248 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
249
250 DRM_DEBUG_KMS("\n");
251
252 pp = REG_READ(PP_CONTROL);
253
254 if ((pp & POWER_TARGET_ON) == 0)
255 return;
256
257 intel_dp->panel_on = false;
258 pp &= ~PANEL_UNLOCK_MASK;
259 /* ILK workaround: disable reset around power sequence */
260
261 pp &= ~POWER_TARGET_ON;
262 pp &= ~EDP_FORCE_VDD;
263 pp &= ~EDP_BLC_ENABLE;
264 REG_WRITE(PP_CONTROL, pp);
265 REG_READ(PP_CONTROL);
266 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
267
268 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
269 DRM_DEBUG_KMS("Error in turning off Panel\n");
270 }
271
272 msleep(intel_dp->panel_power_cycle_delay);
273 DRM_DEBUG_KMS("Over\n");
274}
275
276static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder)
277{
278 struct drm_device *dev = intel_encoder->base.dev;
279 u32 pp;
280
281 DRM_DEBUG_KMS("\n");
282 /*
283 * If we enable the backlight right away following a panel power
284 * on, we may see slight flicker as the panel syncs with the eDP
285 * link. So delay a bit to make sure the image is solid before
286 * allowing it to appear.
287 */
288 msleep(300);
289 pp = REG_READ(PP_CONTROL);
290
291 pp |= EDP_BLC_ENABLE;
292 REG_WRITE(PP_CONTROL, pp);
293 gma_backlight_enable(dev);
294}
295
296static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder)
297{
298 struct drm_device *dev = intel_encoder->base.dev;
299 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
300 u32 pp;
301
302 DRM_DEBUG_KMS("\n");
303 gma_backlight_disable(dev);
304 msleep(10);
305 pp = REG_READ(PP_CONTROL);
306
307 pp &= ~EDP_BLC_ENABLE;
308 REG_WRITE(PP_CONTROL, pp);
309 msleep(intel_dp->backlight_off_delay);
310}
311
8695b612 312static int
37e7b184 313cdv_intel_dp_mode_valid(struct drm_connector *connector,
8695b612
AC		 314 struct drm_display_mode *mode)
315{
37e7b184 316 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
d112a816 317 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
37e7b184
AC		 318 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
319 int max_lanes = cdv_intel_dp_max_lane_count(encoder);
d112a816 320 struct drm_psb_private *dev_priv = connector->dev->dev_private;
8695b612 321
d112a816
ZY		 322 if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
323 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
8695b612 324 return MODE_PANEL;
d112a816 325 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
8695b612
AC		 326 return MODE_PANEL;
327 }
328
329 /* only refuse the mode on non eDP since we have seen some weird eDP panels
330 which are outside spec tolerances but somehow work by magic */
37e7b184 331 if (!is_edp(encoder) &&
d112a816 332 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
37e7b184 333 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
8695b612
AC		 334 return MODE_CLOCK_HIGH;
335
d112a816
ZY		 336 if (is_edp(encoder)) {
337 if (cdv_intel_dp_link_required(mode->clock, 24)
338 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))
339 return MODE_CLOCK_HIGH;
340
341 }
8695b612
AC		 342 if (mode->clock < 10000)
343 return MODE_CLOCK_LOW;
344
345 return MODE_OK;
346}
347
348static uint32_t
349pack_aux(uint8_t *src, int src_bytes)
350{
351 int i;
352 uint32_t v = 0;
353
354 if (src_bytes > 4)
355 src_bytes = 4;
356 for (i = 0; i < src_bytes; i++)
357 v |= ((uint32_t) src[i]) << ((3-i) * 8);
358 return v;
359}
360
361static void
362unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
363{
364 int i;
365 if (dst_bytes > 4)
366 dst_bytes = 4;
367 for (i = 0; i < dst_bytes; i++)
368 dst[i] = src >> ((3-i) * 8);
369}
370
371static int
37e7b184 372cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
8695b612
AC		 373 uint8_t *send, int send_bytes,
374 uint8_t *recv, int recv_size)
375{
37e7b184 376 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612 377 uint32_t output_reg = intel_dp->output_reg;
37e7b184 378 struct drm_device *dev = encoder->base.dev;
8695b612
AC		 379 uint32_t ch_ctl = output_reg + 0x10;
380 uint32_t ch_data = ch_ctl + 4;
381 int i;
382 int recv_bytes;
383 uint32_t status;
384 uint32_t aux_clock_divider;
385 int try, precharge;
386
387 /* The clock divider is based off the hrawclk,
388 * and would like to run at 2MHz. So, take the
389 * hrawclk value and divide by 2 and use that
390 * On CDV platform it uses 200MHz as hrawclk.
391 *
392 */
393 aux_clock_divider = 200 / 2;
394
395 precharge = 4;
d112a816
ZY		 396 if (is_edp(encoder))
397 precharge = 10;
8695b612
AC		 398
399 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
400 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
401 REG_READ(ch_ctl));
402 return -EBUSY;
403 }
404
405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
408 for (i = 0; i < send_bytes; i += 4)
409 REG_WRITE(ch_data + i,
410 pack_aux(send + i, send_bytes - i));
411
412 /* Send the command and wait for it to complete */
413 REG_WRITE(ch_ctl,
414 DP_AUX_CH_CTL_SEND_BUSY |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
422 for (;;) {
423 status = REG_READ(ch_ctl);
424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
425 break;
426 udelay(100);
427 }
428
429 /* Clear done status and any errors */
430 REG_WRITE(ch_ctl,
431 status |
432 DP_AUX_CH_CTL_DONE |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
435 if (status & DP_AUX_CH_CTL_DONE)
436 break;
437 }
438
439 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
440 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
441 return -EBUSY;
442 }
443
444 /* Check for timeout or receive error.
445 * Timeouts occur when the sink is not connected
446 */
447 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
448 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
449 return -EIO;
450 }
451
452 /* Timeouts occur when the device isn't connected, so they're
453 * "normal" -- don't fill the kernel log with these */
454 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
455 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
456 return -ETIMEDOUT;
457 }
458
459 /* Unload any bytes sent back from the other side */
460 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
461 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
462 if (recv_bytes > recv_size)
463 recv_bytes = recv_size;
464
465 for (i = 0; i < recv_bytes; i += 4)
466 unpack_aux(REG_READ(ch_data + i),
467 recv + i, recv_bytes - i);
468
469 return recv_bytes;
470}
471
472/* Write data to the aux channel in native mode */
473static int
37e7b184 474cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
8695b612
AC		 475 uint16_t address, uint8_t *send, int send_bytes)
476{
477 int ret;
478 uint8_t msg[20];
479 int msg_bytes;
480 uint8_t ack;
481
482 if (send_bytes > 16)
483 return -1;
484 msg[0] = AUX_NATIVE_WRITE << 4;
485 msg[1] = address >> 8;
486 msg[2] = address & 0xff;
487 msg[3] = send_bytes - 1;
488 memcpy(&msg[4], send, send_bytes);
489 msg_bytes = send_bytes + 4;
490 for (;;) {
37e7b184 491 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
8695b612
AC		 492 if (ret < 0)
493 return ret;
494 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
495 break;
496 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
497 udelay(100);
498 else
499 return -EIO;
500 }
501 return send_bytes;
502}
503
504/* Write a single byte to the aux channel in native mode */
505static int
37e7b184 506cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
8695b612
AC		 507 uint16_t address, uint8_t byte)
508{
37e7b184 509 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
8695b612
AC		 510}
511
512/* read bytes from a native aux channel */
513static int
37e7b184 514cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
8695b612
AC		 515 uint16_t address, uint8_t *recv, int recv_bytes)
516{
517 uint8_t msg[4];
518 int msg_bytes;
519 uint8_t reply[20];
520 int reply_bytes;
521 uint8_t ack;
522 int ret;
523
524 msg[0] = AUX_NATIVE_READ << 4;
525 msg[1] = address >> 8;
526 msg[2] = address & 0xff;
527 msg[3] = recv_bytes - 1;
528
529 msg_bytes = 4;
530 reply_bytes = recv_bytes + 1;
531
532 for (;;) {
37e7b184 533 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
8695b612
AC		 534 reply, reply_bytes);
535 if (ret == 0)
536 return -EPROTO;
537 if (ret < 0)
538 return ret;
539 ack = reply[0];
540 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
541 memcpy(recv, reply + 1, ret - 1);
542 return ret - 1;
543 }
544 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
545 udelay(100);
546 else
547 return -EIO;
548 }
549}
550
551static int
37e7b184 552cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
8695b612
AC		 553 uint8_t write_byte, uint8_t *read_byte)
554{
555 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
37e7b184
AC		 556 struct cdv_intel_dp *intel_dp = container_of(adapter,
557 struct cdv_intel_dp,
8695b612 558 adapter);
37e7b184 559 struct psb_intel_encoder *encoder = intel_dp->encoder;
8695b612
AC		 560 uint16_t address = algo_data->address;
561 uint8_t msg[5];
562 uint8_t reply[2];
563 unsigned retry;
564 int msg_bytes;
565 int reply_bytes;
566 int ret;
567
568 /* Set up the command byte */
569 if (mode & MODE_I2C_READ)
570 msg[0] = AUX_I2C_READ << 4;
571 else
572 msg[0] = AUX_I2C_WRITE << 4;
573
574 if (!(mode & MODE_I2C_STOP))
575 msg[0] |= AUX_I2C_MOT << 4;
576
577 msg[1] = address >> 8;
578 msg[2] = address;
579
580 switch (mode) {
581 case MODE_I2C_WRITE:
582 msg[3] = 0;
583 msg[4] = write_byte;
584 msg_bytes = 5;
585 reply_bytes = 1;
586 break;
587 case MODE_I2C_READ:
588 msg[3] = 0;
589 msg_bytes = 4;
590 reply_bytes = 2;
591 break;
592 default:
593 msg_bytes = 3;
594 reply_bytes = 1;
595 break;
596 }
597
598 for (retry = 0; retry < 5; retry++) {
37e7b184 599 ret = cdv_intel_dp_aux_ch(encoder,
8695b612
AC		 600 msg, msg_bytes,
601 reply, reply_bytes);
602 if (ret < 0) {
603 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
604 return ret;
605 }
606
607 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
608 case AUX_NATIVE_REPLY_ACK:
609 /* I2C-over-AUX Reply field is only valid
610 * when paired with AUX ACK.
611 */
612 break;
613 case AUX_NATIVE_REPLY_NACK:
614 DRM_DEBUG_KMS("aux_ch native nack\n");
615 return -EREMOTEIO;
616 case AUX_NATIVE_REPLY_DEFER:
617 udelay(100);
618 continue;
619 default:
620 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
621 reply[0]);
622 return -EREMOTEIO;
623 }
624
625 switch (reply[0] & AUX_I2C_REPLY_MASK) {
626 case AUX_I2C_REPLY_ACK:
627 if (mode == MODE_I2C_READ) {
628 *read_byte = reply[1];
629 }
630 return reply_bytes - 1;
631 case AUX_I2C_REPLY_NACK:
632 DRM_DEBUG_KMS("aux_i2c nack\n");
633 return -EREMOTEIO;
634 case AUX_I2C_REPLY_DEFER:
635 DRM_DEBUG_KMS("aux_i2c defer\n");
636 udelay(100);
637 break;
638 default:
639 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
640 return -EREMOTEIO;
641 }
642 }
643
644 DRM_ERROR("too many retries, giving up\n");
645 return -EREMOTEIO;
646}
647
648static int
37e7b184 649cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
8695b612 650{
37e7b184 651 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
d112a816
ZY		 652 int ret;
653
8695b612 654 DRM_DEBUG_KMS("i2c_init %s\n", name);
d112a816 655
8695b612
AC		 656 intel_dp->algo.running = false;
657 intel_dp->algo.address = 0;
37e7b184 658 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
8695b612
AC		 659
660 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
661 intel_dp->adapter.owner = THIS_MODULE;
662 intel_dp->adapter.class = I2C_CLASS_DDC;
663 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
664 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
665 intel_dp->adapter.algo_data = &intel_dp->algo;
37e7b184 666 intel_dp->adapter.dev.parent = &connector->base.kdev;
8695b612 667
d112a816
ZY		 668 if (is_edp(encoder))
669 cdv_intel_edp_panel_vdd_on(encoder);
670 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
671 if (is_edp(encoder))
672 cdv_intel_edp_panel_vdd_off(encoder);
673
674 return ret;
675}
676
677void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
678 struct drm_display_mode *adjusted_mode)
679{
680 adjusted_mode->hdisplay = fixed_mode->hdisplay;
681 adjusted_mode->hsync_start = fixed_mode->hsync_start;
682 adjusted_mode->hsync_end = fixed_mode->hsync_end;
683 adjusted_mode->htotal = fixed_mode->htotal;
684
685 adjusted_mode->vdisplay = fixed_mode->vdisplay;
686 adjusted_mode->vsync_start = fixed_mode->vsync_start;
687 adjusted_mode->vsync_end = fixed_mode->vsync_end;
688 adjusted_mode->vtotal = fixed_mode->vtotal;
689
690 adjusted_mode->clock = fixed_mode->clock;
691
692 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
8695b612
AC		 693}
694
695static bool
37e7b184 696cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
8695b612
AC		 697 struct drm_display_mode *adjusted_mode)
698{
d112a816 699 struct drm_psb_private *dev_priv = encoder->dev->dev_private;
37e7b184
AC		 700 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
701 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612 702 int lane_count, clock;
37e7b184
AC		 703 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
704 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
8695b612 705 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
d112a816
ZY		 706 int refclock = mode->clock;
707 int bpp = 24;
8695b612 708
d112a816
ZY		 709 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
710 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
711 refclock = intel_dp->panel_fixed_mode->clock;
712 bpp = dev_priv->edp.bpp;
713 }
8695b612
AC		 714
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 for (clock = max_clock; clock >= 0; clock--) {
37e7b184 717 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
8695b612 718
d112a816 719 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) {
8695b612
AC		 720 intel_dp->link_bw = bws[clock];
721 intel_dp->lane_count = lane_count;
37e7b184 722 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
8695b612
AC		 723 DRM_DEBUG_KMS("Display port link bw %02x lane "
724 "count %d clock %d\n",
725 intel_dp->link_bw, intel_dp->lane_count,
726 adjusted_mode->clock);
727 return true;
728 }
729 }
730 }
d112a816
ZY		 731 if (is_edp(intel_encoder)) {
732 /* okay we failed just pick the highest */
733 intel_dp->lane_count = max_lane_count;
734 intel_dp->link_bw = bws[max_clock];
735 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
736 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
737 "count %d clock %d\n",
738 intel_dp->link_bw, intel_dp->lane_count,
739 adjusted_mode->clock);
740
741 return true;
742 }
8695b612
AC		 743 return false;
744}
745
37e7b184 746struct cdv_intel_dp_m_n {
8695b612
AC		 747 uint32_t tu;
748 uint32_t gmch_m;
749 uint32_t gmch_n;
750 uint32_t link_m;
751 uint32_t link_n;
752};
753
754static void
d112a816 755cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den)
8695b612
AC		 756{
757 /*
758 while (*num > 0xffffff || *den > 0xffffff) {
759 *num >>= 1;
760 *den >>= 1;
761 }*/
762 uint64_t value, m;
763 m = *num;
764 value = m * (0x800000);
765 m = do_div(value, *den);
766 *num = value;
767 *den = 0x800000;
768}
769
770static void
37e7b184 771cdv_intel_dp_compute_m_n(int bpp,
8695b612
AC		 772 int nlanes,
773 int pixel_clock,
774 int link_clock,
37e7b184 775 struct cdv_intel_dp_m_n *m_n)
8695b612
AC		 776{
777 m_n->tu = 64;
778 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
779 m_n->gmch_n = link_clock * nlanes;
d112a816 780 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
8695b612
AC		 781 m_n->link_m = pixel_clock;
782 m_n->link_n = link_clock;
d112a816 783 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
8695b612
AC		 784}
785
786void
37e7b184 787cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
8695b612
AC		 788 struct drm_display_mode *adjusted_mode)
789{
790 struct drm_device *dev = crtc->dev;
d112a816 791 struct drm_psb_private *dev_priv = dev->dev_private;
8695b612
AC		 792 struct drm_mode_config *mode_config = &dev->mode_config;
793 struct drm_encoder *encoder;
794 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
795 int lane_count = 4, bpp = 24;
37e7b184 796 struct cdv_intel_dp_m_n m_n;
8695b612
AC		 797 int pipe = intel_crtc->pipe;
798
799 /*
800 * Find the lane count in the intel_encoder private
801 */
802 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
37e7b184
AC		 803 struct psb_intel_encoder *intel_encoder;
804 struct cdv_intel_dp *intel_dp;
8695b612
AC		 805
806 if (encoder->crtc != crtc)
807 continue;
808
37e7b184
AC		 809 intel_encoder = to_psb_intel_encoder(encoder);
810 intel_dp = intel_encoder->dev_priv;
811 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
8695b612
AC		 812 lane_count = intel_dp->lane_count;
813 break;
37e7b184 814 } else if (is_edp(intel_encoder)) {
8695b612 815 lane_count = intel_dp->lane_count;
d112a816 816 bpp = dev_priv->edp.bpp;
8695b612
AC		 817 break;
818 }
819 }
820
821 /*
822 * Compute the GMCH and Link ratios. The '3' here is
823 * the number of bytes_per_pixel post-LUT, which we always
824 * set up for 8-bits of R/G/B, or 3 bytes total.
825 */
37e7b184 826 cdv_intel_dp_compute_m_n(bpp, lane_count,
8695b612
AC		 827 mode->clock, adjusted_mode->clock, &m_n);
828
829 {
830 REG_WRITE(PIPE_GMCH_DATA_M(pipe),
831 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
832 m_n.gmch_m);
833 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
834 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
835 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
836 }
837}
838
839static void
37e7b184 840cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8695b612
AC		 841 struct drm_display_mode *adjusted_mode)
842{
37e7b184 843 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
8695b612
AC		 844 struct drm_crtc *crtc = encoder->crtc;
845 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
37e7b184 846 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
d112a816 847 struct drm_device *dev = encoder->dev;
8695b612
AC		 848
849 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
850 intel_dp->DP |= intel_dp->color_range;
851
852 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
853 intel_dp->DP |= DP_SYNC_HS_HIGH;
854 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
855 intel_dp->DP |= DP_SYNC_VS_HIGH;
856
857 intel_dp->DP |= DP_LINK_TRAIN_OFF;
858
859 switch (intel_dp->lane_count) {
860 case 1:
861 intel_dp->DP |= DP_PORT_WIDTH_1;
862 break;
863 case 2:
864 intel_dp->DP |= DP_PORT_WIDTH_2;
865 break;
866 case 4:
867 intel_dp->DP |= DP_PORT_WIDTH_4;
868 break;
869 }
870 if (intel_dp->has_audio)
871 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
872
873 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
874 intel_dp->link_configuration[0] = intel_dp->link_bw;
875 intel_dp->link_configuration[1] = intel_dp->lane_count;
876
877 /*
878 * Check for DPCD version > 1.1 and enhanced framing support
879 */
880 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
881 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
882 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
883 intel_dp->DP |= DP_ENHANCED_FRAMING;
884 }
885
886 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
887 if (intel_crtc->pipe == 1)
888 intel_dp->DP |= DP_PIPEB_SELECT;
889
d112a816 890 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
8695b612 891 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
d112a816
ZY		 892 if (is_edp(intel_encoder)) {
893 uint32_t pfit_control;
894 cdv_intel_edp_panel_on(intel_encoder);
895
896 if (mode->hdisplay != adjusted_mode->hdisplay ||
897 mode->vdisplay != adjusted_mode->vdisplay)
898 pfit_control = PFIT_ENABLE;
899 else
900 pfit_control = 0;
901
902 pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
903
904 REG_WRITE(PFIT_CONTROL, pfit_control);
905 }
8695b612
AC		 906}
907
908
909/* If the sink supports it, try to set the power state appropriately */
37e7b184 910static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
8695b612 911{
37e7b184 912 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 913 int ret, i;
914
915 /* Should have a valid DPCD by this point */
916 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
917 return;
918
919 if (mode != DRM_MODE_DPMS_ON) {
37e7b184 920 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
8695b612
AC		 921 DP_SET_POWER_D3);
922 if (ret != 1)
923 DRM_DEBUG_DRIVER("failed to write sink power state\n");
924 } else {
925 /*
926 * When turning on, we need to retry for 1ms to give the sink
927 * time to wake up.
928 */
929 for (i = 0; i < 3; i++) {
37e7b184 930 ret = cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 931 DP_SET_POWER,
932 DP_SET_POWER_D0);
933 if (ret == 1)
934 break;
935 udelay(1000);
936 }
937 }
938}
939
37e7b184 940static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
8695b612 941{
37e7b184 942 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
d112a816 943 int edp = is_edp(intel_encoder);
8695b612 944
d112a816
ZY		 945 if (edp) {
946 cdv_intel_edp_backlight_off(intel_encoder);
947 cdv_intel_edp_panel_off(intel_encoder);
948 cdv_intel_edp_panel_vdd_on(intel_encoder);
949 }
8695b612 950 /* Wake up the sink first */
37e7b184
AC		 951 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
952 cdv_intel_dp_link_down(intel_encoder);
d112a816
ZY		 953 if (edp)
954 cdv_intel_edp_panel_vdd_off(intel_encoder);
8695b612
AC		 955}
956
37e7b184 957static void cdv_intel_dp_commit(struct drm_encoder *encoder)
8695b612 958{
37e7b184 959 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
d112a816 960 int edp = is_edp(intel_encoder);
8695b612 961
d112a816
ZY		 962 if (edp)
963 cdv_intel_edp_panel_on(intel_encoder);
37e7b184
AC		 964 cdv_intel_dp_start_link_train(intel_encoder);
965 cdv_intel_dp_complete_link_train(intel_encoder);
d112a816
ZY		 966 if (edp)
967 cdv_intel_edp_backlight_on(intel_encoder);
8695b612
AC		 968}
969
970static void
37e7b184 971cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
8695b612 972{
37e7b184
AC		 973 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
974 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612
AC		 975 struct drm_device *dev = encoder->dev;
976 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
d112a816 977 int edp = is_edp(intel_encoder);
8695b612
AC		 978
979 if (mode != DRM_MODE_DPMS_ON) {
d112a816
ZY		 980 if (edp) {
981 cdv_intel_edp_backlight_off(intel_encoder);
982 cdv_intel_edp_panel_vdd_on(intel_encoder);
983 }
37e7b184
AC		 984 cdv_intel_dp_sink_dpms(intel_encoder, mode);
985 cdv_intel_dp_link_down(intel_encoder);
d112a816
ZY		 986 if (edp) {
987 cdv_intel_edp_panel_vdd_off(intel_encoder);
988 cdv_intel_edp_panel_off(intel_encoder);
989 }
8695b612 990 } else {
d112a816
ZY		 991 if (edp)
992 cdv_intel_edp_panel_on(intel_encoder);
37e7b184 993 cdv_intel_dp_sink_dpms(intel_encoder, mode);
8695b612 994 if (!(dp_reg & DP_PORT_EN)) {
37e7b184
AC		 995 cdv_intel_dp_start_link_train(intel_encoder);
996 cdv_intel_dp_complete_link_train(intel_encoder);
8695b612 997 }
d112a816
ZY		 998 if (edp)
999 cdv_intel_edp_backlight_on(intel_encoder);
8695b612
AC		 1000 }
1001}
1002
1003/*
1004 * Native read with retry for link status and receiver capability reads for
1005 * cases where the sink may still be asleep.
1006 */
1007static bool
37e7b184 1008cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
8695b612
AC		 1009 uint8_t *recv, int recv_bytes)
1010{
1011 int ret, i;
1012
1013 /*
1014 * Sinks are *supposed* to come up within 1ms from an off state,
1015 * but we're also supposed to retry 3 times per the spec.
1016 */
1017 for (i = 0; i < 3; i++) {
37e7b184 1018 ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
8695b612
AC		 1019 recv_bytes);
1020 if (ret == recv_bytes)
1021 return true;
1022 udelay(1000);
1023 }
1024
1025 return false;
1026}
1027
1028/*
1029 * Fetch AUX CH registers 0x202 - 0x207 which contain
1030 * link status information
1031 */
1032static bool
37e7b184 1033cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
8695b612 1034{
37e7b184
AC		 1035 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1036 return cdv_intel_dp_aux_native_read_retry(encoder,
8695b612
AC		 1037 DP_LANE0_1_STATUS,
1038 intel_dp->link_status,
1039 DP_LINK_STATUS_SIZE);
1040}
1041
1042static uint8_t
37e7b184 1043cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1044 int r)
1045{
1046 return link_status[r - DP_LANE0_1_STATUS];
1047}
1048
1049static uint8_t
37e7b184 1050cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1051 int lane)
1052{
1053 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1054 int s = ((lane & 1) ?
1055 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1056 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
37e7b184 1057 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1058
1059 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1060}
1061
1062static uint8_t
37e7b184 1063cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1064 int lane)
1065{
1066 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1067 int s = ((lane & 1) ?
1068 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1069 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
37e7b184 1070 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1071
1072 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1073}
1074
1075
1076#if 0
1077static char *voltage_names[] = {
1078 "0.4V", "0.6V", "0.8V", "1.2V"
1079};
1080static char *pre_emph_names[] = {
1081 "0dB", "3.5dB", "6dB", "9.5dB"
1082};
1083static char *link_train_names[] = {
1084 "pattern 1", "pattern 2", "idle", "off"
1085};
1086#endif
1087
1088#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
1089/*
1090static uint8_t
37e7b184 1091cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
8695b612
AC		 1092{
1093 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1094 case DP_TRAIN_VOLTAGE_SWING_400:
1095 return DP_TRAIN_PRE_EMPHASIS_6;
1096 case DP_TRAIN_VOLTAGE_SWING_600:
1097 return DP_TRAIN_PRE_EMPHASIS_6;
1098 case DP_TRAIN_VOLTAGE_SWING_800:
1099 return DP_TRAIN_PRE_EMPHASIS_3_5;
1100 case DP_TRAIN_VOLTAGE_SWING_1200:
1101 default:
1102 return DP_TRAIN_PRE_EMPHASIS_0;
1103 }
1104}
1105*/
1106static void
37e7b184 1107cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
8695b612 1108{
37e7b184 1109 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1110 uint8_t v = 0;
1111 uint8_t p = 0;
1112 int lane;
1113
1114 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37e7b184
AC		 1115 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1116 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
8695b612
AC		 1117
1118 if (this_v > v)
1119 v = this_v;
1120 if (this_p > p)
1121 p = this_p;
1122 }
1123
1124 if (v >= CDV_DP_VOLTAGE_MAX)
1125 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1126
1127 if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
1128 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1129
1130 for (lane = 0; lane < 4; lane++)
1131 intel_dp->train_set[lane] = v | p;
1132}
1133
1134
1135static uint8_t
37e7b184 1136cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
8695b612
AC		 1137 int lane)
1138{
1139 int i = DP_LANE0_1_STATUS + (lane >> 1);
1140 int s = (lane & 1) * 4;
37e7b184 1141 uint8_t l = cdv_intel_dp_link_status(link_status, i);
8695b612
AC		 1142
1143 return (l >> s) & 0xf;
1144}
1145
1146/* Check for clock recovery is done on all channels */
1147static bool
37e7b184 1148cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
8695b612
AC		 1149{
1150 int lane;
1151 uint8_t lane_status;
1152
1153 for (lane = 0; lane < lane_count; lane++) {
37e7b184 1154 lane_status = cdv_intel_get_lane_status(link_status, lane);
8695b612
AC		 1155 if ((lane_status & DP_LANE_CR_DONE) == 0)
1156 return false;
1157 }
1158 return true;
1159}
1160
1161/* Check to see if channel eq is done on all channels */
1162#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1163 DP_LANE_CHANNEL_EQ_DONE|\
1164 DP_LANE_SYMBOL_LOCKED)
1165static bool
37e7b184 1166cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
8695b612 1167{
37e7b184 1168 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1169 uint8_t lane_align;
1170 uint8_t lane_status;
1171 int lane;
1172
37e7b184 1173 lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
8695b612
AC		 1174 DP_LANE_ALIGN_STATUS_UPDATED);
1175 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1176 return false;
1177 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37e7b184 1178 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
8695b612
AC		 1179 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1180 return false;
1181 }
1182 return true;
1183}
1184
1185static bool
37e7b184 1186cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
8695b612
AC		 1187 uint32_t dp_reg_value,
1188 uint8_t dp_train_pat)
1189{
1190
37e7b184 1191 struct drm_device *dev = encoder->base.dev;
8695b612 1192 int ret;
37e7b184 1193 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1194
1195 REG_WRITE(intel_dp->output_reg, dp_reg_value);
1196 REG_READ(intel_dp->output_reg);
1197
37e7b184 1198 ret = cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 1199 DP_TRAINING_PATTERN_SET,
1200 dp_train_pat);
1201
1202 if (ret != 1) {
1203 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
1204 dp_train_pat);
1205 return false;
1206 }
1207
1208 return true;
1209}
1210
1211
1212static bool
37e7b184 1213cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
8695b612
AC		 1214 uint8_t dp_train_pat)
1215{
1216
1217 int ret;
37e7b184 1218 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612 1219
37e7b184 1220 ret = cdv_intel_dp_aux_native_write(encoder,
8695b612
AC		 1221 DP_TRAINING_LANE0_SET,
1222 intel_dp->train_set,
1223 intel_dp->lane_count);
1224
1225 if (ret != intel_dp->lane_count) {
1226 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
1227 intel_dp->train_set[0], intel_dp->lane_count);
1228 return false;
1229 }
1230 return true;
1231}
1232
1233static void
37e7b184 1234cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
8695b612 1235{
37e7b184
AC		 1236 struct drm_device *dev = encoder->base.dev;
1237 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1238 struct ddi_regoff *ddi_reg;
1239 int vswing, premph, index;
1240
1241 if (intel_dp->output_reg == DP_B)
1242 ddi_reg = &ddi_DP_train_table[0];
1243 else
1244 ddi_reg = &ddi_DP_train_table[1];
1245
1246 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
1247 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
1248 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1249
1250 if (vswing + premph > 3)
1251 return;
1252#ifdef CDV_FAST_LINK_TRAIN
1253 return;
1254#endif
1255 DRM_DEBUG_KMS("Test2\n");
1256 //return ;
37e7b184 1257 cdv_sb_reset(dev);
8695b612
AC		 1258 /* ;Swing voltage programming
1259 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
37e7b184 1260 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
8695b612
AC		 1261
1262 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
37e7b184 1263 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
8695b612
AC		 1264
1265 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1266 * The VSwing_PreEmph table is also considered based on the vswing/premp
1267 */
1268 index = (vswing + premph) * 2;
1269 if (premph == 1 && vswing == 1) {
37e7b184 1270 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
8695b612 1271 } else
37e7b184 1272 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
8695b612
AC		 1273
1274 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1275 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
37e7b184 1276 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
8695b612 1277 else
37e7b184 1278 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
8695b612
AC		 1279
1280 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
37e7b184 1281 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
8695b612
AC		 1282
1283 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
37e7b184 1284 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
8695b612
AC		 1285
1286 /* ;Pre emphasis programming
1287 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1288 */
37e7b184 1289 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
8695b612
AC		 1290
1291 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1292 index = 2 * premph + 1;
37e7b184 1293 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
8695b612
AC		 1294 return;
1295}
1296
1297
1298/* Enable corresponding port and start training pattern 1 */
1299static void
37e7b184 1300cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
8695b612 1301{
37e7b184
AC		 1302 struct drm_device *dev = encoder->base.dev;
1303 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1304 int i;
1305 uint8_t voltage;
1306 bool clock_recovery = false;
1307 int tries;
1308 u32 reg;
1309 uint32_t DP = intel_dp->DP;
1310
1311 DP |= DP_PORT_EN;
37e7b184 1312 DP &= ~DP_LINK_TRAIN_MASK;
8695b612 1313
37e7b184
AC		 1314 reg = DP;
1315 reg |= DP_LINK_TRAIN_PAT_1;
8695b612
AC		 1316 /* Enable output, wait for it to become active */
1317 REG_WRITE(intel_dp->output_reg, reg);
1318 REG_READ(intel_dp->output_reg);
1319 psb_intel_wait_for_vblank(dev);
1320
1321 DRM_DEBUG_KMS("Link config\n");
1322 /* Write the link configuration data */
37e7b184 1323 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
8695b612
AC		 1324 intel_dp->link_configuration,
1325 2);
1326
1327 memset(intel_dp->train_set, 0, 4);
1328 voltage = 0;
1329 tries = 0;
1330 clock_recovery = false;
1331
1332 DRM_DEBUG_KMS("Start train\n");
1333 reg = DP | DP_LINK_TRAIN_PAT_1;
1334
1335
1336 for (;;) {
1337 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
d112a816
ZY		 1338 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1339 intel_dp->train_set[0],
1340 intel_dp->link_configuration[0],
1341 intel_dp->link_configuration[1]);
8695b612 1342
37e7b184 1343 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
8695b612
AC		 1344 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1345 }
37e7b184 1346 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
8695b612
AC		 1347 /* Set training pattern 1 */
1348
37e7b184 1349 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
8695b612
AC		 1350
1351 udelay(200);
37e7b184 1352 if (!cdv_intel_dp_get_link_status(encoder))
8695b612
AC		 1353 break;
1354
d112a816
ZY		 1355 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1356 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1357 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1358
37e7b184 1359 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
8695b612
AC		 1360 DRM_DEBUG_KMS("PT1 train is done\n");
1361 clock_recovery = true;
1362 break;
1363 }
1364
1365 /* Check to see if we've tried the max voltage */
1366 for (i = 0; i < intel_dp->lane_count; i++)
1367 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1368 break;
1369 if (i == intel_dp->lane_count)
1370 break;
1371
1372 /* Check to see if we've tried the same voltage 5 times */
1373 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1374 ++tries;
1375 if (tries == 5)
1376 break;
1377 } else
1378 tries = 0;
1379 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1380
1381 /* Compute new intel_dp->train_set as requested by target */
37e7b184 1382 cdv_intel_get_adjust_train(encoder);
8695b612
AC		 1383
1384 }
1385
1386 if (!clock_recovery) {
1387 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1388 }
1389
1390 intel_dp->DP = DP;
1391}
1392
1393static void
37e7b184 1394cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
8695b612 1395{
37e7b184
AC		 1396 struct drm_device *dev = encoder->base.dev;
1397 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1398 bool channel_eq = false;
1399 int tries, cr_tries;
1400 u32 reg;
1401 uint32_t DP = intel_dp->DP;
1402
1403 /* channel equalization */
1404 tries = 0;
1405 cr_tries = 0;
1406 channel_eq = false;
1407
1408 DRM_DEBUG_KMS("\n");
1409 reg = DP | DP_LINK_TRAIN_PAT_2;
1410
1411 for (;;) {
d112a816
ZY		 1412
1413 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1414 intel_dp->train_set[0],
1415 intel_dp->link_configuration[0],
1416 intel_dp->link_configuration[1]);
1417 /* channel eq pattern */
1418
37e7b184 1419 if (!cdv_intel_dp_set_link_train(encoder, reg,
8695b612
AC		 1420 DP_TRAINING_PATTERN_2)) {
1421 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1422 }
1423 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1424
1425 if (cr_tries > 5) {
1426 DRM_ERROR("failed to train DP, aborting\n");
37e7b184 1427 cdv_intel_dp_link_down(encoder);
8695b612
AC		 1428 break;
1429 }
1430
37e7b184 1431 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
8695b612 1432
37e7b184 1433 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
8695b612
AC		 1434
1435 udelay(1000);
37e7b184 1436 if (!cdv_intel_dp_get_link_status(encoder))
8695b612
AC		 1437 break;
1438
d112a816
ZY		 1439 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1440 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1441 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1442
8695b612 1443 /* Make sure clock is still ok */
37e7b184
AC		 1444 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1445 cdv_intel_dp_start_link_train(encoder);
8695b612
AC		 1446 cr_tries++;
1447 continue;
1448 }
1449
37e7b184 1450 if (cdv_intel_channel_eq_ok(encoder)) {
8695b612
AC		 1451 DRM_DEBUG_KMS("PT2 train is done\n");
1452 channel_eq = true;
1453 break;
1454 }
1455
1456 /* Try 5 times, then try clock recovery if that fails */
1457 if (tries > 5) {
37e7b184
AC		 1458 cdv_intel_dp_link_down(encoder);
1459 cdv_intel_dp_start_link_train(encoder);
8695b612
AC		 1460 tries = 0;
1461 cr_tries++;
1462 continue;
1463 }
1464
1465 /* Compute new intel_dp->train_set as requested by target */
37e7b184 1466 cdv_intel_get_adjust_train(encoder);
8695b612
AC		 1467 ++tries;
1468
1469 }
1470
1471 reg = DP | DP_LINK_TRAIN_OFF;
1472
1473 REG_WRITE(intel_dp->output_reg, reg);
1474 REG_READ(intel_dp->output_reg);
37e7b184 1475 cdv_intel_dp_aux_native_write_1(encoder,
8695b612
AC		 1476 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1477}
1478
1479static void
37e7b184 1480cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
8695b612 1481{
37e7b184
AC		 1482 struct drm_device *dev = encoder->base.dev;
1483 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1484 uint32_t DP = intel_dp->DP;
1485
1486 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1487 return;
1488
1489 DRM_DEBUG_KMS("\n");
1490
1491
1492 {
1493 DP &= ~DP_LINK_TRAIN_MASK;
1494 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1495 }
1496 REG_READ(intel_dp->output_reg);
1497
1498 msleep(17);
1499
1500 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1501 REG_READ(intel_dp->output_reg);
1502}
1503
1504static enum drm_connector_status
37e7b184 1505cdv_dp_detect(struct psb_intel_encoder *encoder)
8695b612 1506{
37e7b184 1507 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1508 enum drm_connector_status status;
1509
1510 status = connector_status_disconnected;
37e7b184 1511 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
8695b612
AC		 1512 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1513 {
1514 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1515 status = connector_status_connected;
1516 }
1517 if (status == connector_status_connected)
1518 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1519 intel_dp->dpcd[0], intel_dp->dpcd[1],
1520 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1521 return status;
1522}
1523
1524/**
1525 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1526 *
1527 * \return true if DP port is connected.
1528 * \return false if DP port is disconnected.
1529 */
1530static enum drm_connector_status
37e7b184 1531cdv_intel_dp_detect(struct drm_connector *connector, bool force)
8695b612 1532{
37e7b184
AC		 1533 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1534 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1535 enum drm_connector_status status;
1536 struct edid *edid = NULL;
d112a816 1537 int edp = is_edp(encoder);
8695b612
AC		 1538
1539 intel_dp->has_audio = false;
1540
d112a816
ZY		 1541 if (edp)
1542 cdv_intel_edp_panel_vdd_on(encoder);
37e7b184 1543 status = cdv_dp_detect(encoder);
d112a816
ZY		 1544 if (status != connector_status_connected) {
1545 if (edp)
1546 cdv_intel_edp_panel_vdd_off(encoder);
8695b612 1547 return status;
d112a816 1548 }
8695b612
AC		 1549
1550 if (intel_dp->force_audio) {
1551 intel_dp->has_audio = intel_dp->force_audio > 0;
1552 } else {
1553 edid = drm_get_edid(connector, &intel_dp->adapter);
1554 if (edid) {
1555 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8695b612
AC		 1556 kfree(edid);
1557 }
1558 }
d112a816
ZY		 1559 if (edp)
1560 cdv_intel_edp_panel_vdd_off(encoder);
8695b612
AC		 1561
1562 return connector_status_connected;
1563}
1564
37e7b184 1565static int cdv_intel_dp_get_modes(struct drm_connector *connector)
8695b612 1566{
37e7b184
AC		 1567 struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
1568 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
8695b612
AC		 1569 struct edid *edid = NULL;
1570 int ret = 0;
d112a816 1571 int edp = is_edp(intel_encoder);
8695b612
AC		 1572
1573
37e7b184 1574 edid = drm_get_edid(connector, &intel_dp->adapter);
8695b612 1575 if (edid) {
37e7b184
AC		 1576 drm_mode_connector_update_edid_property(connector, edid);
1577 ret = drm_add_edid_modes(connector, edid);
8695b612
AC		 1578 kfree(edid);
1579 }
1580
d112a816
ZY		 1581 if (is_edp(intel_encoder)) {
1582 struct drm_device *dev = connector->dev;
1583 struct drm_psb_private *dev_priv = dev->dev_private;
1584
1585 cdv_intel_edp_panel_vdd_off(intel_encoder);
1586 if (ret) {
1587 if (edp && !intel_dp->panel_fixed_mode) {
1588 struct drm_display_mode *newmode;
1589 list_for_each_entry(newmode, &connector->probed_modes,
1590 head) {
1591 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1592 intel_dp->panel_fixed_mode =
1593 drm_mode_duplicate(dev, newmode);
1594 break;
1595 }
1596 }
1597 }
1598
1599 return ret;
1600 }
1601 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
1602 intel_dp->panel_fixed_mode =
1603 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1604 if (intel_dp->panel_fixed_mode) {
1605 intel_dp->panel_fixed_mode->type |=
1606 DRM_MODE_TYPE_PREFERRED;
1607 }
1608 }
1609 if (intel_dp->panel_fixed_mode != NULL) {
1610 struct drm_display_mode *mode;
1611 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1612 drm_mode_probed_add(connector, mode);
1613 return 1;
1614 }
1615 }
1616
8695b612
AC		 1617 return ret;
1618}
1619
1620static bool
37e7b184 1621cdv_intel_dp_detect_audio(struct drm_connector *connector)
8695b612 1622{
37e7b184
AC		 1623 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1624 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1625 struct edid *edid;
1626 bool has_audio = false;
d112a816
ZY		 1627 int edp = is_edp(encoder);
1628
1629 if (edp)
1630 cdv_intel_edp_panel_vdd_on(encoder);
8695b612
AC		 1631
1632 edid = drm_get_edid(connector, &intel_dp->adapter);
1633 if (edid) {
1634 has_audio = drm_detect_monitor_audio(edid);
8695b612
AC		 1635 kfree(edid);
1636 }
d112a816
ZY		 1637 if (edp)
1638 cdv_intel_edp_panel_vdd_off(encoder);
8695b612
AC		 1639
1640 return has_audio;
1641}
1642
1643static int
37e7b184 1644cdv_intel_dp_set_property(struct drm_connector *connector,
8695b612
AC		 1645 struct drm_property *property,
1646 uint64_t val)
1647{
1648 struct drm_psb_private *dev_priv = connector->dev->dev_private;
37e7b184
AC		 1649 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1650 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
8695b612
AC		 1651 int ret;
1652
1653 ret = drm_connector_property_set_value(connector, property, val);
1654 if (ret)
1655 return ret;
1656
1657 if (property == dev_priv->force_audio_property) {
1658 int i = val;
1659 bool has_audio;
1660
1661 if (i == intel_dp->force_audio)
1662 return 0;
1663
1664 intel_dp->force_audio = i;
1665
1666 if (i == 0)
37e7b184 1667 has_audio = cdv_intel_dp_detect_audio(connector);
8695b612
AC		 1668 else
1669 has_audio = i > 0;
1670
1671 if (has_audio == intel_dp->has_audio)
1672 return 0;
1673
1674 intel_dp->has_audio = has_audio;
1675 goto done;
1676 }
1677
1678 if (property == dev_priv->broadcast_rgb_property) {
1679 if (val == !!intel_dp->color_range)
1680 return 0;
1681
1682 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1683 goto done;
1684 }
1685
1686 return -EINVAL;
1687
1688done:
37e7b184
AC		 1689 if (encoder->base.crtc) {
1690 struct drm_crtc *crtc = encoder->base.crtc;
8695b612
AC		 1691 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1692 crtc->x, crtc->y,
1693 crtc->fb);
1694 }
1695
1696 return 0;
1697}
1698
1699static void
d112a816 1700cdv_intel_dp_destroy(struct drm_connector *connector)
8695b612 1701{
37e7b184
AC		 1702 struct psb_intel_encoder *psb_intel_encoder =
1703 psb_intel_attached_encoder(connector);
1704 struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
8695b612 1705
d112a816
ZY		 1706 if (is_edp(psb_intel_encoder)) {
1707 /* cdv_intel_panel_destroy_backlight(connector->dev); */
1708 if (intel_dp->panel_fixed_mode) {
1709 kfree(intel_dp->panel_fixed_mode);
1710 intel_dp->panel_fixed_mode = NULL;
1711 }
1712 }
8695b612
AC		 1713 i2c_del_adapter(&intel_dp->adapter);
1714 drm_sysfs_connector_remove(connector);
1715 drm_connector_cleanup(connector);
1716 kfree(connector);
1717}
1718
37e7b184 1719static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
8695b612
AC		 1720{
1721 drm_encoder_cleanup(encoder);
1722}
1723
37e7b184
AC		 1724static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
1725 .dpms = cdv_intel_dp_dpms,
1726 .mode_fixup = cdv_intel_dp_mode_fixup,
1727 .prepare = cdv_intel_dp_prepare,
1728 .mode_set = cdv_intel_dp_mode_set,
1729 .commit = cdv_intel_dp_commit,
8695b612
AC		 1730};
1731
37e7b184 1732static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
8695b612 1733 .dpms = drm_helper_connector_dpms,
37e7b184 1734 .detect = cdv_intel_dp_detect,
8695b612 1735 .fill_modes = drm_helper_probe_single_connector_modes,
37e7b184
AC		 1736 .set_property = cdv_intel_dp_set_property,
1737 .destroy = cdv_intel_dp_destroy,
8695b612
AC		 1738};
1739
37e7b184
AC		 1740static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
1741 .get_modes = cdv_intel_dp_get_modes,
1742 .mode_valid = cdv_intel_dp_mode_valid,
8695b612
AC		 1743 .best_encoder = psb_intel_best_encoder,
1744};
1745
37e7b184
AC		 1746static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
1747 .destroy = cdv_intel_dp_encoder_destroy,
8695b612
AC		 1748};
1749
1750
37e7b184 1751static void cdv_intel_dp_add_properties(struct drm_connector *connector)
8695b612 1752{
37e7b184
AC		 1753 cdv_intel_attach_force_audio_property(connector);
1754 cdv_intel_attach_broadcast_rgb_property(connector);
8695b612
AC		 1755}
1756
d112a816
ZY		 1757/* check the VBT to see whether the eDP is on DP-D port */
1758static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
1759{
1760 struct drm_psb_private *dev_priv = dev->dev_private;
1761 struct child_device_config *p_child;
1762 int i;
1763
1764 if (!dev_priv->child_dev_num)
1765 return false;
1766
1767 for (i = 0; i < dev_priv->child_dev_num; i++) {
1768 p_child = dev_priv->child_dev + i;
1769
1770 if (p_child->dvo_port == PORT_IDPC &&
1771 p_child->device_type == DEVICE_TYPE_eDP)
1772 return true;
1773 }
1774 return false;
1775}
1776
9a9f5786
ZY		 1777/* Cedarview display clock gating
1778
1779 We need this disable dot get correct behaviour while enabling
1780 DP/eDP. TODO - investigate if we can turn it back to normality
1781 after enabling */
1782static void cdv_disable_intel_clock_gating(struct drm_device *dev)
1783{
1784 u32 reg_value;
1785 reg_value = REG_READ(DSPCLK_GATE_D);
1786
1787 reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
1788 DPUNIT_PIPEA_GATE_DISABLE |
1789 DPCUNIT_CLOCK_GATE_DISABLE |
1790 DPLSUNIT_CLOCK_GATE_DISABLE |
1791 DPOUNIT_CLOCK_GATE_DISABLE |
1792 DPIOUNIT_CLOCK_GATE_DISABLE);
1793
1794 REG_WRITE(DSPCLK_GATE_D, reg_value);
1795
1796 udelay(500);
1797}
1798
8695b612 1799void
37e7b184 1800cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
8695b612 1801{
37e7b184
AC		 1802 struct psb_intel_encoder *psb_intel_encoder;
1803 struct psb_intel_connector *psb_intel_connector;
8695b612
AC		 1804 struct drm_connector *connector;
1805 struct drm_encoder *encoder;
37e7b184 1806 struct cdv_intel_dp *intel_dp;
8695b612 1807 const char *name = NULL;
d112a816 1808 int type = DRM_MODE_CONNECTOR_DisplayPort;
8695b612 1809
37e7b184
AC		 1810 psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
1811 if (!psb_intel_encoder)
8695b612 1812 return;
37e7b184
AC		 1813 psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
1814 if (!psb_intel_connector)
1815 goto err_connector;
1816 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
1817 if (!intel_dp)
1818 goto err_priv;
1819
d112a816
ZY		 1820 if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
1821 type = DRM_MODE_CONNECTOR_eDP;
1822
37e7b184
AC		 1823 connector = &psb_intel_connector->base;
1824 encoder = &psb_intel_encoder->base;
8695b612 1825
d112a816 1826 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
37e7b184 1827 drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
8695b612 1828
37e7b184 1829 psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
d112a816
ZY		 1830
1831 if (type == DRM_MODE_CONNECTOR_DisplayPort)
1832 psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1833 else
1834 psb_intel_encoder->type = INTEL_OUTPUT_EDP;
1835
37e7b184
AC		 1836
1837 psb_intel_encoder->dev_priv=intel_dp;
1838 intel_dp->encoder = psb_intel_encoder;
8695b612
AC		 1839 intel_dp->output_reg = output_reg;
1840
37e7b184
AC		 1841 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
1842 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
8695b612
AC		 1843
1844 connector->polled = DRM_CONNECTOR_POLL_HPD;
37e7b184
AC		 1845 connector->interlace_allowed = false;
1846 connector->doublescan_allowed = false;
8695b612
AC		 1847
1848 drm_sysfs_connector_add(connector);
1849
1850 /* Set up the DDC bus. */
1851 switch (output_reg) {
1852 case DP_B:
1853 name = "DPDDC-B";
37e7b184 1854 psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
8695b612
AC		 1855 break;
1856 case DP_C:
1857 name = "DPDDC-C";
37e7b184 1858 psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
8695b612
AC		 1859 break;
1860 }
1861
9a9f5786
ZY		 1862 cdv_disable_intel_clock_gating(dev);
1863
37e7b184
AC		 1864 cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
1865 /* FIXME:fail check */
1866 cdv_intel_dp_add_properties(connector);
d112a816
ZY		 1867
1868 if (is_edp(psb_intel_encoder)) {
1869 int ret;
1870 struct edp_power_seq cur;
1871 u32 pp_on, pp_off, pp_div;
1872 u32 pwm_ctrl;
1873
1874 pp_on = REG_READ(PP_CONTROL);
1875 pp_on &= ~PANEL_UNLOCK_MASK;
1876 pp_on |= PANEL_UNLOCK_REGS;
1877
1878 REG_WRITE(PP_CONTROL, pp_on);
1879
1880 pwm_ctrl = REG_READ(BLC_PWM_CTL2);
1881 pwm_ctrl |= PWM_PIPE_B;
1882 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
1883
1884 pp_on = REG_READ(PP_ON_DELAYS);
1885 pp_off = REG_READ(PP_OFF_DELAYS);
1886 pp_div = REG_READ(PP_DIVISOR);
1887
1888 /* Pull timing values out of registers */
1889 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
1890 PANEL_POWER_UP_DELAY_SHIFT;
1891
1892 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
1893 PANEL_LIGHT_ON_DELAY_SHIFT;
1894
1895 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
1896 PANEL_LIGHT_OFF_DELAY_SHIFT;
1897
1898 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
1899 PANEL_POWER_DOWN_DELAY_SHIFT;
1900
1901 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
1902 PANEL_POWER_CYCLE_DELAY_SHIFT);
1903
1904 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1905 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
1906
1907
1908 intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
1909 intel_dp->backlight_on_delay = cur.t8 / 10;
1910 intel_dp->backlight_off_delay = cur.t9 / 10;
1911 intel_dp->panel_power_down_delay = cur.t10 / 10;
1912 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
1913
1914 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
1915 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
1916 intel_dp->panel_power_cycle_delay);
1917
1918 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
1919 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
1920
1921
1922 cdv_intel_edp_panel_vdd_on(psb_intel_encoder);
1923 ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV,
1924 intel_dp->dpcd,
1925 sizeof(intel_dp->dpcd));
1926 cdv_intel_edp_panel_vdd_off(psb_intel_encoder);
1927 if (ret == 0) {
1928 /* if this fails, presume the device is a ghost */
1929 DRM_INFO("failed to retrieve link info, disabling eDP\n");
1930 cdv_intel_dp_encoder_destroy(encoder);
1931 cdv_intel_dp_destroy(connector);
1932 goto err_priv;
1933 } else {
1934 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1935 intel_dp->dpcd[0], intel_dp->dpcd[1],
1936 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1937
1938 }
1939 /* The CDV reference driver moves pnale backlight setup into the displays that
1940 have a backlight: this is a good idea and one we should probably adopt, however
1941 we need to migrate all the drivers before we can do that */
1942 /*cdv_intel_panel_setup_backlight(dev); */
1943 }
37e7b184 1944 return;
8695b612 1945
37e7b184
AC		 1946err_priv:
1947 kfree(psb_intel_connector);
1948err_connector:
1949 kfree(psb_intel_encoder);
8695b612 1950}
Ubuntu combined Linux kernel mirror