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Commit | Line | Data |
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8c8f1c95 AC |
1 | /* |
2 | * Copyright (c) 2007, Intel Corporation. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com> | |
19 | * Alan Cox <alan@linux.intel.com> | |
20 | */ | |
21 | ||
22 | #include <drm/drmP.h> | |
e912b6d2 | 23 | #include <linux/shmem_fs.h> |
8c8f1c95 | 24 | #include "psb_drv.h" |
ae012bdc | 25 | #include "blitter.h" |
8c8f1c95 AC |
26 | |
27 | ||
28 | /* | |
29 | * GTT resource allocator - manage page mappings in GTT space | |
30 | */ | |
31 | ||
32 | /** | |
33 | * psb_gtt_mask_pte - generate GTT pte entry | |
34 | * @pfn: page number to encode | |
35 | * @type: type of memory in the GTT | |
36 | * | |
37 | * Set the GTT entry for the appropriate memory type. | |
38 | */ | |
39 | static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type) | |
40 | { | |
41 | uint32_t mask = PSB_PTE_VALID; | |
42 | ||
398b4706 AC |
43 | /* Ensure we explode rather than put an invalid low mapping of |
44 | a high mapping page into the gtt */ | |
45 | BUG_ON(pfn & ~(0xFFFFFFFF >> PAGE_SHIFT)); | |
46 | ||
8c8f1c95 AC |
47 | if (type & PSB_MMU_CACHED_MEMORY) |
48 | mask |= PSB_PTE_CACHED; | |
49 | if (type & PSB_MMU_RO_MEMORY) | |
50 | mask |= PSB_PTE_RO; | |
51 | if (type & PSB_MMU_WO_MEMORY) | |
52 | mask |= PSB_PTE_WO; | |
53 | ||
54 | return (pfn << PAGE_SHIFT) | mask; | |
55 | } | |
56 | ||
57 | /** | |
58 | * psb_gtt_entry - find the GTT entries for a gtt_range | |
59 | * @dev: our DRM device | |
60 | * @r: our GTT range | |
61 | * | |
62 | * Given a gtt_range object return the GTT offset of the page table | |
63 | * entries for this gtt_range | |
64 | */ | |
eab37607 | 65 | static u32 __iomem *psb_gtt_entry(struct drm_device *dev, struct gtt_range *r) |
8c8f1c95 AC |
66 | { |
67 | struct drm_psb_private *dev_priv = dev->dev_private; | |
68 | unsigned long offset; | |
69 | ||
70 | offset = r->resource.start - dev_priv->gtt_mem->start; | |
71 | ||
72 | return dev_priv->gtt_map + (offset >> PAGE_SHIFT); | |
73 | } | |
74 | ||
75 | /** | |
76 | * psb_gtt_insert - put an object into the GTT | |
77 | * @dev: our DRM device | |
78 | * @r: our GTT range | |
79 | * | |
80 | * Take our preallocated GTT range and insert the GEM object into | |
a746092b AC |
81 | * the GTT. This is protected via the gtt mutex which the caller |
82 | * must hold. | |
8c8f1c95 | 83 | */ |
070839ea PJ |
84 | static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r, |
85 | int resume) | |
8c8f1c95 | 86 | { |
eab37607 KS |
87 | u32 __iomem *gtt_slot; |
88 | u32 pte; | |
8c8f1c95 AC |
89 | struct page **pages; |
90 | int i; | |
91 | ||
92 | if (r->pages == NULL) { | |
93 | WARN_ON(1); | |
94 | return -EINVAL; | |
95 | } | |
96 | ||
97 | WARN_ON(r->stolen); /* refcount these maybe ? */ | |
98 | ||
99 | gtt_slot = psb_gtt_entry(dev, r); | |
100 | pages = r->pages; | |
101 | ||
070839ea PJ |
102 | if (!resume) { |
103 | /* Make sure changes are visible to the GPU */ | |
104 | set_pages_array_wc(pages, r->npage); | |
105 | } | |
8c8f1c95 AC |
106 | |
107 | /* Write our page entries into the GTT itself */ | |
a6ba582d | 108 | for (i = r->roll; i < r->npage; i++) { |
ae012bdc PJ |
109 | pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]), |
110 | PSB_MMU_CACHED_MEMORY); | |
a6ba582d AC |
111 | iowrite32(pte, gtt_slot++); |
112 | } | |
113 | for (i = 0; i < r->roll; i++) { | |
ae012bdc PJ |
114 | pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]), |
115 | PSB_MMU_CACHED_MEMORY); | |
8c8f1c95 AC |
116 | iowrite32(pte, gtt_slot++); |
117 | } | |
118 | /* Make sure all the entries are set before we return */ | |
119 | ioread32(gtt_slot - 1); | |
a6ba582d | 120 | |
8c8f1c95 AC |
121 | return 0; |
122 | } | |
123 | ||
124 | /** | |
125 | * psb_gtt_remove - remove an object from the GTT | |
126 | * @dev: our DRM device | |
127 | * @r: our GTT range | |
128 | * | |
129 | * Remove a preallocated GTT range from the GTT. Overwrite all the | |
a746092b AC |
130 | * page table entries with the dummy page. This is protected via the gtt |
131 | * mutex which the caller must hold. | |
8c8f1c95 | 132 | */ |
ae012bdc | 133 | void psb_gtt_remove(struct drm_device *dev, struct gtt_range *r) |
8c8f1c95 AC |
134 | { |
135 | struct drm_psb_private *dev_priv = dev->dev_private; | |
eab37607 KS |
136 | u32 __iomem *gtt_slot; |
137 | u32 pte; | |
8c8f1c95 AC |
138 | int i; |
139 | ||
140 | WARN_ON(r->stolen); | |
141 | ||
142 | gtt_slot = psb_gtt_entry(dev, r); | |
ae012bdc PJ |
143 | pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page), |
144 | PSB_MMU_CACHED_MEMORY); | |
8c8f1c95 AC |
145 | |
146 | for (i = 0; i < r->npage; i++) | |
147 | iowrite32(pte, gtt_slot++); | |
148 | ioread32(gtt_slot - 1); | |
149 | set_pages_array_wb(r->pages, r->npage); | |
150 | } | |
151 | ||
a6ba582d AC |
152 | /** |
153 | * psb_gtt_roll - set scrolling position | |
154 | * @dev: our DRM device | |
155 | * @r: the gtt mapping we are using | |
156 | * @roll: roll offset | |
157 | * | |
158 | * Roll an existing pinned mapping by moving the pages through the GTT. | |
159 | * This allows us to implement hardware scrolling on the consoles without | |
160 | * a 2D engine | |
161 | */ | |
162 | void psb_gtt_roll(struct drm_device *dev, struct gtt_range *r, int roll) | |
163 | { | |
eab37607 KS |
164 | u32 __iomem *gtt_slot; |
165 | u32 pte; | |
a6ba582d AC |
166 | int i; |
167 | ||
168 | if (roll >= r->npage) { | |
169 | WARN_ON(1); | |
170 | return; | |
171 | } | |
172 | ||
173 | r->roll = roll; | |
174 | ||
175 | /* Not currently in the GTT - no worry we will write the mapping at | |
176 | the right position when it gets pinned */ | |
177 | if (!r->stolen && !r->in_gart) | |
178 | return; | |
179 | ||
180 | gtt_slot = psb_gtt_entry(dev, r); | |
181 | ||
182 | for (i = r->roll; i < r->npage; i++) { | |
ae012bdc PJ |
183 | pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]), |
184 | PSB_MMU_CACHED_MEMORY); | |
a6ba582d AC |
185 | iowrite32(pte, gtt_slot++); |
186 | } | |
187 | for (i = 0; i < r->roll; i++) { | |
ae012bdc PJ |
188 | pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]), |
189 | PSB_MMU_CACHED_MEMORY); | |
a6ba582d AC |
190 | iowrite32(pte, gtt_slot++); |
191 | } | |
192 | ioread32(gtt_slot - 1); | |
193 | } | |
194 | ||
8c8f1c95 AC |
195 | /** |
196 | * psb_gtt_attach_pages - attach and pin GEM pages | |
197 | * @gt: the gtt range | |
198 | * | |
199 | * Pin and build an in kernel list of the pages that back our GEM object. | |
a746092b AC |
200 | * While we hold this the pages cannot be swapped out. This is protected |
201 | * via the gtt mutex which the caller must hold. | |
8c8f1c95 AC |
202 | */ |
203 | static int psb_gtt_attach_pages(struct gtt_range *gt) | |
204 | { | |
8b9ba7a3 | 205 | struct page **pages; |
8c8f1c95 AC |
206 | |
207 | WARN_ON(gt->pages); | |
208 | ||
0cdbe8ac | 209 | pages = drm_gem_get_pages(>->gem); |
8b9ba7a3 RC |
210 | if (IS_ERR(pages)) |
211 | return PTR_ERR(pages); | |
8c8f1c95 | 212 | |
b9aa8510 | 213 | gt->npage = gt->gem.size / PAGE_SIZE; |
8b9ba7a3 | 214 | gt->pages = pages; |
8c8f1c95 | 215 | |
8c8f1c95 | 216 | return 0; |
8c8f1c95 AC |
217 | } |
218 | ||
219 | /** | |
220 | * psb_gtt_detach_pages - attach and pin GEM pages | |
221 | * @gt: the gtt range | |
222 | * | |
223 | * Undo the effect of psb_gtt_attach_pages. At this point the pages | |
224 | * must have been removed from the GTT as they could now be paged out | |
a746092b AC |
225 | * and move bus address. This is protected via the gtt mutex which the |
226 | * caller must hold. | |
8c8f1c95 AC |
227 | */ |
228 | static void psb_gtt_detach_pages(struct gtt_range *gt) | |
229 | { | |
8b9ba7a3 | 230 | drm_gem_put_pages(>->gem, gt->pages, true, false); |
8c8f1c95 AC |
231 | gt->pages = NULL; |
232 | } | |
233 | ||
234 | /** | |
235 | * psb_gtt_pin - pin pages into the GTT | |
236 | * @gt: range to pin | |
237 | * | |
238 | * Pin a set of pages into the GTT. The pins are refcounted so that | |
239 | * multiple pins need multiple unpins to undo. | |
240 | * | |
241 | * Non GEM backed objects treat this as a no-op as they are always GTT | |
242 | * backed objects. | |
243 | */ | |
244 | int psb_gtt_pin(struct gtt_range *gt) | |
245 | { | |
246 | int ret = 0; | |
247 | struct drm_device *dev = gt->gem.dev; | |
248 | struct drm_psb_private *dev_priv = dev->dev_private; | |
ae012bdc | 249 | u32 gpu_base = dev_priv->gtt.gatt_start; |
8c8f1c95 AC |
250 | |
251 | mutex_lock(&dev_priv->gtt_mutex); | |
252 | ||
253 | if (gt->in_gart == 0 && gt->stolen == 0) { | |
254 | ret = psb_gtt_attach_pages(gt); | |
255 | if (ret < 0) | |
256 | goto out; | |
070839ea | 257 | ret = psb_gtt_insert(dev, gt, 0); |
8c8f1c95 AC |
258 | if (ret < 0) { |
259 | psb_gtt_detach_pages(gt); | |
260 | goto out; | |
261 | } | |
ae012bdc PJ |
262 | psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu), |
263 | gt->pages, (gpu_base + gt->offset), | |
264 | gt->npage, 0, 0, PSB_MMU_CACHED_MEMORY); | |
8c8f1c95 AC |
265 | } |
266 | gt->in_gart++; | |
267 | out: | |
268 | mutex_unlock(&dev_priv->gtt_mutex); | |
269 | return ret; | |
270 | } | |
271 | ||
272 | /** | |
273 | * psb_gtt_unpin - Drop a GTT pin requirement | |
274 | * @gt: range to pin | |
275 | * | |
276 | * Undoes the effect of psb_gtt_pin. On the last drop the GEM object | |
277 | * will be removed from the GTT which will also drop the page references | |
278 | * and allow the VM to clean up or page stuff. | |
279 | * | |
280 | * Non GEM backed objects treat this as a no-op as they are always GTT | |
281 | * backed objects. | |
282 | */ | |
283 | void psb_gtt_unpin(struct gtt_range *gt) | |
284 | { | |
285 | struct drm_device *dev = gt->gem.dev; | |
286 | struct drm_psb_private *dev_priv = dev->dev_private; | |
ae012bdc PJ |
287 | u32 gpu_base = dev_priv->gtt.gatt_start; |
288 | int ret; | |
8c8f1c95 | 289 | |
ae012bdc | 290 | /* While holding the gtt_mutex no new blits can be initiated */ |
8c8f1c95 AC |
291 | mutex_lock(&dev_priv->gtt_mutex); |
292 | ||
ae012bdc PJ |
293 | /* Wait for any possible usage of the memory to be finished */ |
294 | ret = gma_blt_wait_idle(dev_priv); | |
295 | if (ret) { | |
296 | DRM_ERROR("Failed to idle the blitter, unpin failed!"); | |
297 | goto out; | |
298 | } | |
299 | ||
8c8f1c95 AC |
300 | WARN_ON(!gt->in_gart); |
301 | ||
302 | gt->in_gart--; | |
303 | if (gt->in_gart == 0 && gt->stolen == 0) { | |
ae012bdc PJ |
304 | psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu), |
305 | (gpu_base + gt->offset), gt->npage, 0, 0); | |
8c8f1c95 AC |
306 | psb_gtt_remove(dev, gt); |
307 | psb_gtt_detach_pages(gt); | |
308 | } | |
ae012bdc PJ |
309 | |
310 | out: | |
8c8f1c95 AC |
311 | mutex_unlock(&dev_priv->gtt_mutex); |
312 | } | |
313 | ||
314 | /* | |
315 | * GTT resource allocator - allocate and manage GTT address space | |
316 | */ | |
317 | ||
318 | /** | |
319 | * psb_gtt_alloc_range - allocate GTT address space | |
320 | * @dev: Our DRM device | |
321 | * @len: length (bytes) of address space required | |
322 | * @name: resource name | |
323 | * @backed: resource should be backed by stolen pages | |
324 | * | |
325 | * Ask the kernel core to find us a suitable range of addresses | |
326 | * to use for a GTT mapping. | |
327 | * | |
328 | * Returns a gtt_range structure describing the object, or NULL on | |
329 | * error. On successful return the resource is both allocated and marked | |
330 | * as in use. | |
331 | */ | |
332 | struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len, | |
c269c685 | 333 | const char *name, int backed, u32 align) |
8c8f1c95 AC |
334 | { |
335 | struct drm_psb_private *dev_priv = dev->dev_private; | |
336 | struct gtt_range *gt; | |
337 | struct resource *r = dev_priv->gtt_mem; | |
338 | int ret; | |
339 | unsigned long start, end; | |
340 | ||
341 | if (backed) { | |
342 | /* The start of the GTT is the stolen pages */ | |
343 | start = r->start; | |
344 | end = r->start + dev_priv->gtt.stolen_size - 1; | |
345 | } else { | |
346 | /* The rest we will use for GEM backed objects */ | |
347 | start = r->start + dev_priv->gtt.stolen_size; | |
348 | end = r->end; | |
349 | } | |
350 | ||
351 | gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL); | |
352 | if (gt == NULL) | |
353 | return NULL; | |
354 | gt->resource.name = name; | |
355 | gt->stolen = backed; | |
356 | gt->in_gart = backed; | |
a6ba582d | 357 | gt->roll = 0; |
8c8f1c95 AC |
358 | /* Ensure this is set for non GEM objects */ |
359 | gt->gem.dev = dev; | |
360 | ret = allocate_resource(dev_priv->gtt_mem, >->resource, | |
c269c685 | 361 | len, start, end, align, NULL, NULL); |
8c8f1c95 AC |
362 | if (ret == 0) { |
363 | gt->offset = gt->resource.start - r->start; | |
364 | return gt; | |
365 | } | |
366 | kfree(gt); | |
367 | return NULL; | |
368 | } | |
369 | ||
370 | /** | |
371 | * psb_gtt_free_range - release GTT address space | |
372 | * @dev: our DRM device | |
373 | * @gt: a mapping created with psb_gtt_alloc_range | |
374 | * | |
375 | * Release a resource that was allocated with psb_gtt_alloc_range. If the | |
376 | * object has been pinned by mmap users we clean this up here currently. | |
377 | */ | |
378 | void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt) | |
379 | { | |
380 | /* Undo the mmap pin if we are destroying the object */ | |
381 | if (gt->mmapping) { | |
382 | psb_gtt_unpin(gt); | |
383 | gt->mmapping = 0; | |
384 | } | |
385 | WARN_ON(gt->in_gart && !gt->stolen); | |
386 | release_resource(>->resource); | |
387 | kfree(gt); | |
388 | } | |
389 | ||
ffe94d9c | 390 | static void psb_gtt_alloc(struct drm_device *dev) |
8c8f1c95 AC |
391 | { |
392 | struct drm_psb_private *dev_priv = dev->dev_private; | |
393 | init_rwsem(&dev_priv->gtt.sem); | |
394 | } | |
395 | ||
396 | void psb_gtt_takedown(struct drm_device *dev) | |
397 | { | |
398 | struct drm_psb_private *dev_priv = dev->dev_private; | |
399 | ||
400 | if (dev_priv->gtt_map) { | |
401 | iounmap(dev_priv->gtt_map); | |
402 | dev_priv->gtt_map = NULL; | |
403 | } | |
404 | if (dev_priv->gtt_initialized) { | |
405 | pci_write_config_word(dev->pdev, PSB_GMCH_CTRL, | |
406 | dev_priv->gmch_ctrl); | |
407 | PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); | |
408 | (void) PSB_RVDC32(PSB_PGETBL_CTL); | |
409 | } | |
410 | if (dev_priv->vram_addr) | |
411 | iounmap(dev_priv->gtt_map); | |
412 | } | |
413 | ||
414 | int psb_gtt_init(struct drm_device *dev, int resume) | |
415 | { | |
416 | struct drm_psb_private *dev_priv = dev->dev_private; | |
417 | unsigned gtt_pages; | |
418 | unsigned long stolen_size, vram_stolen_size; | |
419 | unsigned i, num_pages; | |
420 | unsigned pfn_base; | |
8c8f1c95 AC |
421 | struct psb_gtt *pg; |
422 | ||
423 | int ret = 0; | |
424 | uint32_t pte; | |
425 | ||
070839ea PJ |
426 | if (!resume) { |
427 | mutex_init(&dev_priv->gtt_mutex); | |
428 | psb_gtt_alloc(dev); | |
429 | } | |
8c8f1c95 | 430 | |
8c8f1c95 AC |
431 | pg = &dev_priv->gtt; |
432 | ||
433 | /* Enable the GTT */ | |
434 | pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl); | |
435 | pci_write_config_word(dev->pdev, PSB_GMCH_CTRL, | |
436 | dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); | |
437 | ||
438 | dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); | |
439 | PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); | |
440 | (void) PSB_RVDC32(PSB_PGETBL_CTL); | |
441 | ||
442 | /* The root resource we allocate address space from */ | |
443 | dev_priv->gtt_initialized = 1; | |
444 | ||
445 | pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK; | |
446 | ||
447 | /* | |
a746092b AC |
448 | * The video mmu has a hw bug when accessing 0x0D0000000. |
449 | * Make gatt start at 0x0e000,0000. This doesn't actually | |
450 | * matter for us but may do if the video acceleration ever | |
451 | * gets opened up. | |
8c8f1c95 AC |
452 | */ |
453 | pg->mmu_gatt_start = 0xE0000000; | |
454 | ||
455 | pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE); | |
456 | gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) | |
457 | >> PAGE_SHIFT; | |
055bf38d | 458 | /* CDV doesn't report this. In which case the system has 64 gtt pages */ |
8c8f1c95 | 459 | if (pg->gtt_start == 0 || gtt_pages == 0) { |
055bf38d | 460 | dev_dbg(dev->dev, "GTT PCI BAR not initialized.\n"); |
8c8f1c95 AC |
461 | gtt_pages = 64; |
462 | pg->gtt_start = dev_priv->pge_ctl; | |
463 | } | |
464 | ||
465 | pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE); | |
466 | pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE) | |
467 | >> PAGE_SHIFT; | |
468 | dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE]; | |
469 | ||
470 | if (pg->gatt_pages == 0 || pg->gatt_start == 0) { | |
471 | static struct resource fudge; /* Preferably peppermint */ | |
055bf38d | 472 | /* This can occur on CDV systems. Fudge it in this case. |
8c8f1c95 AC |
473 | We really don't care what imaginary space is being allocated |
474 | at this point */ | |
055bf38d | 475 | dev_dbg(dev->dev, "GATT PCI BAR not initialized.\n"); |
8c8f1c95 AC |
476 | pg->gatt_start = 0x40000000; |
477 | pg->gatt_pages = (128 * 1024 * 1024) >> PAGE_SHIFT; | |
a746092b AC |
478 | /* This is a little confusing but in fact the GTT is providing |
479 | a view from the GPU into memory and not vice versa. As such | |
480 | this is really allocating space that is not the same as the | |
481 | CPU address space on CDV */ | |
8c8f1c95 AC |
482 | fudge.start = 0x40000000; |
483 | fudge.end = 0x40000000 + 128 * 1024 * 1024 - 1; | |
484 | fudge.name = "fudge"; | |
485 | fudge.flags = IORESOURCE_MEM; | |
486 | dev_priv->gtt_mem = &fudge; | |
487 | } | |
488 | ||
489 | pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base); | |
490 | vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base | |
491 | - PAGE_SIZE; | |
492 | ||
493 | stolen_size = vram_stolen_size; | |
494 | ||
31a0685a AC |
495 | dev_dbg(dev->dev, "Stolen memory base 0x%x, size %luK\n", |
496 | dev_priv->stolen_base, vram_stolen_size / 1024); | |
8c8f1c95 AC |
497 | |
498 | if (resume && (gtt_pages != pg->gtt_pages) && | |
499 | (stolen_size != pg->stolen_size)) { | |
500 | dev_err(dev->dev, "GTT resume error.\n"); | |
501 | ret = -EINVAL; | |
502 | goto out_err; | |
503 | } | |
504 | ||
505 | pg->gtt_pages = gtt_pages; | |
506 | pg->stolen_size = stolen_size; | |
507 | dev_priv->vram_stolen_size = vram_stolen_size; | |
508 | ||
509 | /* | |
510 | * Map the GTT and the stolen memory area | |
511 | */ | |
070839ea PJ |
512 | if (!resume) |
513 | dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start, | |
8c8f1c95 AC |
514 | gtt_pages << PAGE_SHIFT); |
515 | if (!dev_priv->gtt_map) { | |
516 | dev_err(dev->dev, "Failure to map gtt.\n"); | |
517 | ret = -ENOMEM; | |
518 | goto out_err; | |
519 | } | |
520 | ||
070839ea PJ |
521 | if (!resume) |
522 | dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, | |
523 | stolen_size); | |
ae012bdc | 524 | |
8c8f1c95 AC |
525 | if (!dev_priv->vram_addr) { |
526 | dev_err(dev->dev, "Failure to map stolen base.\n"); | |
527 | ret = -ENOMEM; | |
528 | goto out_err; | |
529 | } | |
530 | ||
531 | /* | |
532 | * Insert vram stolen pages into the GTT | |
533 | */ | |
534 | ||
535 | pfn_base = dev_priv->stolen_base >> PAGE_SHIFT; | |
f728bd1a | 536 | num_pages = vram_stolen_size >> PAGE_SHIFT; |
31a0685a | 537 | dev_dbg(dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n", |
8c8f1c95 AC |
538 | num_pages, pfn_base << PAGE_SHIFT, 0); |
539 | for (i = 0; i < num_pages; ++i) { | |
ae012bdc | 540 | pte = psb_gtt_mask_pte(pfn_base + i, PSB_MMU_CACHED_MEMORY); |
8c8f1c95 AC |
541 | iowrite32(pte, dev_priv->gtt_map + i); |
542 | } | |
543 | ||
544 | /* | |
545 | * Init rest of GTT to the scratch page to avoid accidents or scribbles | |
546 | */ | |
547 | ||
548 | pfn_base = page_to_pfn(dev_priv->scratch_page); | |
ae012bdc | 549 | pte = psb_gtt_mask_pte(pfn_base, PSB_MMU_CACHED_MEMORY); |
8c8f1c95 AC |
550 | for (; i < gtt_pages; ++i) |
551 | iowrite32(pte, dev_priv->gtt_map + i); | |
552 | ||
553 | (void) ioread32(dev_priv->gtt_map + i - 1); | |
554 | return 0; | |
555 | ||
556 | out_err: | |
557 | psb_gtt_takedown(dev); | |
558 | return ret; | |
559 | } | |
070839ea PJ |
560 | |
561 | int psb_gtt_restore(struct drm_device *dev) | |
562 | { | |
563 | struct drm_psb_private *dev_priv = dev->dev_private; | |
564 | struct resource *r = dev_priv->gtt_mem->child; | |
565 | struct gtt_range *range; | |
1611f845 | 566 | unsigned int restored = 0, total = 0, size = 0; |
070839ea PJ |
567 | |
568 | /* On resume, the gtt_mutex is already initialized */ | |
569 | mutex_lock(&dev_priv->gtt_mutex); | |
570 | psb_gtt_init(dev, 1); | |
571 | ||
572 | while (r != NULL) { | |
573 | range = container_of(r, struct gtt_range, resource); | |
1611f845 | 574 | if (range->pages) { |
070839ea | 575 | psb_gtt_insert(dev, range, 1); |
1611f845 PJ |
576 | size += range->resource.end - range->resource.start; |
577 | restored++; | |
578 | } | |
070839ea | 579 | r = r->sibling; |
1611f845 | 580 | total++; |
070839ea PJ |
581 | } |
582 | mutex_unlock(&dev_priv->gtt_mutex); | |
1611f845 PJ |
583 | DRM_DEBUG_DRIVER("Restored %u of %u gtt ranges (%u KB)", restored, |
584 | total, (size / 1024)); | |
070839ea PJ |
585 | |
586 | return 0; | |
587 | } |