]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/gma500/psb_drv.h
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gma500: Rename the ioctls to avoid clashing with the legacy drivers
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
28#include "psb_drm.h"
29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
45#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
46#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
47
48/*
49 * Driver definitions
50 */
51
52#define DRIVER_NAME "gma500"
53#define DRIVER_DESC "DRM driver for the Intel GMA500"
54
55#define PSB_DRM_DRIVER_DATE "2011-06-06"
56#define PSB_DRM_DRIVER_MAJOR 1
57#define PSB_DRM_DRIVER_MINOR 0
58#define PSB_DRM_DRIVER_PATCHLEVEL 0
59
60/*
61 * Hardware offsets
62 */
63#define PSB_VDC_OFFSET 0x00000000
64#define PSB_VDC_SIZE 0x000080000
65#define MRST_MMIO_SIZE 0x0000C0000
66#define MDFLD_MMIO_SIZE 0x000100000
67#define PSB_SGX_SIZE 0x8000
68#define PSB_SGX_OFFSET 0x00040000
69#define MRST_SGX_OFFSET 0x00080000
70/*
71 * PCI resource identifiers
72 */
73#define PSB_MMIO_RESOURCE 0
74#define PSB_GATT_RESOURCE 2
75#define PSB_GTT_RESOURCE 3
76/*
77 * PCI configuration
78 */
79#define PSB_GMCH_CTRL 0x52
80#define PSB_BSM 0x5C
81#define _PSB_GMCH_ENABLED 0x4
82#define PSB_PGETBL_CTL 0x2020
83#define _PSB_PGETBL_ENABLED 0x00000001
84#define PSB_SGX_2D_SLAVE_PORT 0x4000
85
86/* To get rid of */
87#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
88#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
89
90/*
91 * SGX side MMU definitions (these can probably go)
92 */
93
94/*
95 * Flags for external memory type field.
96 */
97#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
98#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
99#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
100/*
101 * PTE's and PDE's
102 */
103#define PSB_PDE_MASK 0x003FFFFF
104#define PSB_PDE_SHIFT 22
105#define PSB_PTE_SHIFT 12
106/*
107 * Cache control
108 */
109#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
110#define PSB_PTE_WO 0x0002 /* Write only */
111#define PSB_PTE_RO 0x0004 /* Read only */
112#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
113
114/*
115 * VDC registers and bits
116 */
117#define PSB_MSVDX_CLOCKGATING 0x2064
118#define PSB_TOPAZ_CLOCKGATING 0x2068
119#define PSB_HWSTAM 0x2098
120#define PSB_INSTPM 0x20C0
121#define PSB_INT_IDENTITY_R 0x20A4
122#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
123#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
124#define _PSB_DPST_PIPEB_FLAG (1<<4)
125#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
126#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
127#define _PSB_DPST_PIPEA_FLAG (1<<6)
128#define _PSB_PIPEA_EVENT_FLAG (1<<6)
129#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
130#define _MDFLD_MIPIA_FLAG (1<<16)
131#define _MDFLD_MIPIC_FLAG (1<<17)
132#define _PSB_IRQ_SGX_FLAG (1<<18)
133#define _PSB_IRQ_MSVDX_FLAG (1<<19)
134#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
135
136/* This flag includes all the display IRQ bits excepts the vblank irqs. */
137#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
138 _MDFLD_PIPEB_EVENT_FLAG | \
139 _PSB_PIPEA_EVENT_FLAG | \
140 _PSB_VSYNC_PIPEA_FLAG | \
141 _MDFLD_MIPIA_FLAG | \
142 _MDFLD_MIPIC_FLAG)
143#define PSB_INT_IDENTITY_R 0x20A4
144#define PSB_INT_MASK_R 0x20A8
145#define PSB_INT_ENABLE_R 0x20A0
146
147#define _PSB_MMU_ER_MASK 0x0001FF00
148#define _PSB_MMU_ER_HOST (1 << 16)
149#define GPIOA 0x5010
150#define GPIOB 0x5014
151#define GPIOC 0x5018
152#define GPIOD 0x501c
153#define GPIOE 0x5020
154#define GPIOF 0x5024
155#define GPIOG 0x5028
156#define GPIOH 0x502c
157#define GPIO_CLOCK_DIR_MASK (1 << 0)
158#define GPIO_CLOCK_DIR_IN (0 << 1)
159#define GPIO_CLOCK_DIR_OUT (1 << 1)
160#define GPIO_CLOCK_VAL_MASK (1 << 2)
161#define GPIO_CLOCK_VAL_OUT (1 << 3)
162#define GPIO_CLOCK_VAL_IN (1 << 4)
163#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
164#define GPIO_DATA_DIR_MASK (1 << 8)
165#define GPIO_DATA_DIR_IN (0 << 9)
166#define GPIO_DATA_DIR_OUT (1 << 9)
167#define GPIO_DATA_VAL_MASK (1 << 10)
168#define GPIO_DATA_VAL_OUT (1 << 11)
169#define GPIO_DATA_VAL_IN (1 << 12)
170#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
171
172#define VCLK_DIVISOR_VGA0 0x6000
173#define VCLK_DIVISOR_VGA1 0x6004
174#define VCLK_POST_DIV 0x6010
175
176#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
177#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
178#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
179#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
180#define PSB_COMM_USER_IRQ (1024 >> 2)
181#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
182#define PSB_COMM_FW (2048 >> 2)
183
184#define PSB_UIRQ_VISTEST 1
185#define PSB_UIRQ_OOM_REPLY 2
186#define PSB_UIRQ_FIRE_TA_REPLY 3
187#define PSB_UIRQ_FIRE_RASTER_REPLY 4
188
189#define PSB_2D_SIZE (256*1024*1024)
190#define PSB_MAX_RELOC_PAGES 1024
191
192#define PSB_LOW_REG_OFFS 0x0204
193#define PSB_HIGH_REG_OFFS 0x0600
194
195#define PSB_NUM_VBLANKS 2
196
197
198#define PSB_2D_SIZE (256*1024*1024)
199#define PSB_MAX_RELOC_PAGES 1024
200
201#define PSB_LOW_REG_OFFS 0x0204
202#define PSB_HIGH_REG_OFFS 0x0600
203
204#define PSB_NUM_VBLANKS 2
205#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
206#define PSB_LID_DELAY (DRM_HZ / 10)
207
208#define MDFLD_PNW_B0 0x04
209#define MDFLD_PNW_C0 0x08
210
211#define MDFLD_DSR_2D_3D_0 (1 << 0)
212#define MDFLD_DSR_2D_3D_2 (1 << 1)
213#define MDFLD_DSR_CURSOR_0 (1 << 2)
214#define MDFLD_DSR_CURSOR_2 (1 << 3)
215#define MDFLD_DSR_OVERLAY_0 (1 << 4)
216#define MDFLD_DSR_OVERLAY_2 (1 << 5)
217#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
218#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
219#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
220#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
221
222#define MDFLD_DSR_RR 45
223#define MDFLD_DPU_ENABLE (1 << 31)
224#define MDFLD_DSR_FULLSCREEN (1 << 30)
225#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
226
227#define PSB_PWR_STATE_ON 1
228#define PSB_PWR_STATE_OFF 2
229
230#define PSB_PMPOLICY_NOPM 0
231#define PSB_PMPOLICY_CLOCKGATING 1
232#define PSB_PMPOLICY_POWERDOWN 2
233
234#define PSB_PMSTATE_POWERUP 0
235#define PSB_PMSTATE_CLOCKGATED 1
236#define PSB_PMSTATE_POWERDOWN 2
237#define PSB_PCIx_MSI_ADDR_LOC 0x94
238#define PSB_PCIx_MSI_DATA_LOC 0x98
239
240/* Medfield crystal settings */
241#define KSEL_CRYSTAL_19 1
242#define KSEL_BYPASS_19 5
243#define KSEL_BYPASS_25 6
244#define KSEL_BYPASS_83_100 7
245
246struct opregion_header;
247struct opregion_acpi;
248struct opregion_swsci;
249struct opregion_asle;
250
251struct psb_intel_opregion {
252 struct opregion_header *header;
253 struct opregion_acpi *acpi;
254 struct opregion_swsci *swsci;
255 struct opregion_asle *asle;
256 int enabled;
257};
258
259struct psb_ops;
260
261struct drm_psb_private {
262 struct drm_device *dev;
263 const struct psb_ops *ops;
264
265 struct psb_gtt gtt;
266
267 /* GTT Memory manager */
268 struct psb_gtt_mm *gtt_mm;
269 struct page *scratch_page;
270 u32 *gtt_map;
271 uint32_t stolen_base;
272 void *vram_addr;
273 unsigned long vram_stolen_size;
274 int gtt_initialized;
275 u16 gmch_ctrl; /* Saved GTT setup */
276 u32 pge_ctl;
277
278 struct mutex gtt_mutex;
279 struct resource *gtt_mem; /* Our PCI resource */
280
281 struct psb_mmu_driver *mmu;
282 struct psb_mmu_pd *pf_pd;
283
284 /*
285 * Register base
286 */
287
288 uint8_t *sgx_reg;
289 uint8_t *vdc_reg;
290 uint32_t gatt_free_offset;
291
292 /*
293 * Fencing / irq.
294 */
295
296 uint32_t vdc_irq_mask;
297 uint32_t pipestat[PSB_NUM_PIPE];
298
299 spinlock_t irqmask_lock;
300
301 /*
302 * Power
303 */
304
305 bool suspended;
306 bool display_power;
307 int display_count;
308
309 /*
310 * Modesetting
311 */
312 struct psb_intel_mode_device mode_dev;
313
314 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
315 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
316 uint32_t num_pipe;
317
318 /*
319 * OSPM info (Power management base) (can go ?)
320 */
321 uint32_t ospm_base;
322
323 /*
324 * Sizes info
325 */
326
5c49fd3a
AC		 327 u32 fuse_reg_value;
328 u32 video_device_fuse;
329
330 /* PCI revision ID for B0:D2:F0 */
331 uint8_t platform_rev_id;
332
333 /*
334 * LVDS info
335 */
336 int backlight_duty_cycle; /* restore backlight to this value */
337 bool panel_wants_dither;
338 struct drm_display_mode *panel_fixed_mode;
339 struct drm_display_mode *lfp_lvds_vbt_mode;
340 struct drm_display_mode *sdvo_lvds_vbt_mode;
341
342 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
343 struct psb_intel_i2c_chan *lvds_i2c_bus;
344
345 /* Feature bits from the VBIOS */
346 unsigned int int_tv_support:1;
347 unsigned int lvds_dither:1;
348 unsigned int lvds_vbt:1;
349 unsigned int int_crt_support:1;
350 unsigned int lvds_use_ssc:1;
351 int lvds_ssc_freq;
352 bool is_lvds_on;
353 bool is_mipi_on;
354 u32 mipi_ctrl_display;
355
356 unsigned int core_freq;
357 uint32_t iLVDS_enable;
358
359 /* Runtime PM state */
360 int rpm_enabled;
361
362 /* MID specific */
363 struct oaktrail_vbt vbt_data;
364 struct oaktrail_gct_data gct_data;
365
366 /* MIPI Panel type etc */
367 int panel_id;
368 bool dual_mipi; /* dual display - DPI & DBI */
369 bool dpi_panel_on; /* The DPI panel power is on */
370 bool dpi_panel_on2; /* The DPI panel power is on */
371 bool dbi_panel_on; /* The DBI panel power is on */
372 bool dbi_panel_on2; /* The DBI panel power is on */
373 u32 dsr_fb_update; /* DSR FB update counter */
374
375 /* Moorestown HDMI state */
376 struct oaktrail_hdmi_dev *hdmi_priv;
377
378 /* Moorestown pipe config register value cache */
379 uint32_t pipeconf;
380 uint32_t pipeconf1;
381 uint32_t pipeconf2;
382
383 /* Moorestown plane control register value cache */
384 uint32_t dspcntr;
385 uint32_t dspcntr1;
386 uint32_t dspcntr2;
387
388 /* Moorestown MM backlight cache */
389 uint8_t saveBKLTCNT;
390 uint8_t saveBKLTREQ;
391 uint8_t saveBKLTBRTL;
392
393 /*
394 * Register state
395 */
396 uint32_t saveDSPACNTR;
397 uint32_t saveDSPBCNTR;
398 uint32_t savePIPEACONF;
399 uint32_t savePIPEBCONF;
400 uint32_t savePIPEASRC;
401 uint32_t savePIPEBSRC;
402 uint32_t saveFPA0;
403 uint32_t saveFPA1;
404 uint32_t saveDPLL_A;
405 uint32_t saveDPLL_A_MD;
406 uint32_t saveHTOTAL_A;
407 uint32_t saveHBLANK_A;
408 uint32_t saveHSYNC_A;
409 uint32_t saveVTOTAL_A;
410 uint32_t saveVBLANK_A;
411 uint32_t saveVSYNC_A;
412 uint32_t saveDSPASTRIDE;
413 uint32_t saveDSPASIZE;
414 uint32_t saveDSPAPOS;
415 uint32_t saveDSPABASE;
416 uint32_t saveDSPASURF;
417 uint32_t saveDSPASTATUS;
418 uint32_t saveFPB0;
419 uint32_t saveFPB1;
420 uint32_t saveDPLL_B;
421 uint32_t saveDPLL_B_MD;
422 uint32_t saveHTOTAL_B;
423 uint32_t saveHBLANK_B;
424 uint32_t saveHSYNC_B;
425 uint32_t saveVTOTAL_B;
426 uint32_t saveVBLANK_B;
427 uint32_t saveVSYNC_B;
428 uint32_t saveDSPBSTRIDE;
429 uint32_t saveDSPBSIZE;
430 uint32_t saveDSPBPOS;
431 uint32_t saveDSPBBASE;
432 uint32_t saveDSPBSURF;
433 uint32_t saveDSPBSTATUS;
434 uint32_t saveVCLK_DIVISOR_VGA0;
435 uint32_t saveVCLK_DIVISOR_VGA1;
436 uint32_t saveVCLK_POST_DIV;
437 uint32_t saveVGACNTRL;
438 uint32_t saveADPA;
439 uint32_t saveLVDS;
440 uint32_t saveDVOA;
441 uint32_t saveDVOB;
442 uint32_t saveDVOC;
443 uint32_t savePP_ON;
444 uint32_t savePP_OFF;
445 uint32_t savePP_CONTROL;
446 uint32_t savePP_CYCLE;
447 uint32_t savePFIT_CONTROL;
448 uint32_t savePaletteA[256];
449 uint32_t savePaletteB[256];
450 uint32_t saveBLC_PWM_CTL2;
451 uint32_t saveBLC_PWM_CTL;
452 uint32_t saveCLOCKGATING;
453 uint32_t saveDSPARB;
454 uint32_t saveDSPATILEOFF;
455 uint32_t saveDSPBTILEOFF;
456 uint32_t saveDSPAADDR;
457 uint32_t saveDSPBADDR;
458 uint32_t savePFIT_AUTO_RATIOS;
459 uint32_t savePFIT_PGM_RATIOS;
460 uint32_t savePP_ON_DELAYS;
461 uint32_t savePP_OFF_DELAYS;
462 uint32_t savePP_DIVISOR;
463 uint32_t saveBSM;
464 uint32_t saveVBT;
465 uint32_t saveBCLRPAT_A;
466 uint32_t saveBCLRPAT_B;
467 uint32_t saveDSPALINOFF;
468 uint32_t saveDSPBLINOFF;
469 uint32_t savePERF_MODE;
470 uint32_t saveDSPFW1;
471 uint32_t saveDSPFW2;
472 uint32_t saveDSPFW3;
473 uint32_t saveDSPFW4;
474 uint32_t saveDSPFW5;
475 uint32_t saveDSPFW6;
476 uint32_t saveCHICKENBIT;
477 uint32_t saveDSPACURSOR_CTRL;
478 uint32_t saveDSPBCURSOR_CTRL;
479 uint32_t saveDSPACURSOR_BASE;
480 uint32_t saveDSPBCURSOR_BASE;
481 uint32_t saveDSPACURSOR_POS;
482 uint32_t saveDSPBCURSOR_POS;
483 uint32_t save_palette_a[256];
484 uint32_t save_palette_b[256];
485 uint32_t saveOV_OVADD;
486 uint32_t saveOV_OGAMC0;
487 uint32_t saveOV_OGAMC1;
488 uint32_t saveOV_OGAMC2;
489 uint32_t saveOV_OGAMC3;
490 uint32_t saveOV_OGAMC4;
491 uint32_t saveOV_OGAMC5;
492 uint32_t saveOVC_OVADD;
493 uint32_t saveOVC_OGAMC0;
494 uint32_t saveOVC_OGAMC1;
495 uint32_t saveOVC_OGAMC2;
496 uint32_t saveOVC_OGAMC3;
497 uint32_t saveOVC_OGAMC4;
498 uint32_t saveOVC_OGAMC5;
499
500 /* MSI reg save */
501 uint32_t msi_addr;
502 uint32_t msi_data;
503
504 /* Medfield specific register save state */
505 uint32_t saveHDMIPHYMISCCTL;
506 uint32_t saveHDMIB_CONTROL;
507 uint32_t saveDSPCCNTR;
508 uint32_t savePIPECCONF;
509 uint32_t savePIPECSRC;
510 uint32_t saveHTOTAL_C;
511 uint32_t saveHBLANK_C;
512 uint32_t saveHSYNC_C;
513 uint32_t saveVTOTAL_C;
514 uint32_t saveVBLANK_C;
515 uint32_t saveVSYNC_C;
516 uint32_t saveDSPCSTRIDE;
517 uint32_t saveDSPCSIZE;
518 uint32_t saveDSPCPOS;
519 uint32_t saveDSPCSURF;
520 uint32_t saveDSPCSTATUS;
521 uint32_t saveDSPCLINOFF;
522 uint32_t saveDSPCTILEOFF;
523 uint32_t saveDSPCCURSOR_CTRL;
524 uint32_t saveDSPCCURSOR_BASE;
525 uint32_t saveDSPCCURSOR_POS;
526 uint32_t save_palette_c[256];
527 uint32_t saveOV_OVADD_C;
528 uint32_t saveOV_OGAMC0_C;
529 uint32_t saveOV_OGAMC1_C;
530 uint32_t saveOV_OGAMC2_C;
531 uint32_t saveOV_OGAMC3_C;
532 uint32_t saveOV_OGAMC4_C;
533 uint32_t saveOV_OGAMC5_C;
534
535 /* DSI register save */
536 uint32_t saveDEVICE_READY_REG;
537 uint32_t saveINTR_EN_REG;
538 uint32_t saveDSI_FUNC_PRG_REG;
539 uint32_t saveHS_TX_TIMEOUT_REG;
540 uint32_t saveLP_RX_TIMEOUT_REG;
541 uint32_t saveTURN_AROUND_TIMEOUT_REG;
542 uint32_t saveDEVICE_RESET_REG;
543 uint32_t saveDPI_RESOLUTION_REG;
544 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
545 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
546 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
547 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
548 uint32_t saveVERT_SYNC_PAD_COUNT_REG;
549 uint32_t saveVERT_BACK_PORCH_COUNT_REG;
550 uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
551 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
552 uint32_t saveINIT_COUNT_REG;
553 uint32_t saveMAX_RET_PAK_REG;
554 uint32_t saveVIDEO_FMT_REG;
555 uint32_t saveEOT_DISABLE_REG;
556 uint32_t saveLP_BYTECLK_REG;
557 uint32_t saveHS_LS_DBI_ENABLE_REG;
558 uint32_t saveTXCLKESC_REG;
559 uint32_t saveDPHY_PARAM_REG;
560 uint32_t saveMIPI_CONTROL_REG;
561 uint32_t saveMIPI;
562 uint32_t saveMIPI_C;
563
564 /* DPST register save */
565 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
566 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
567 uint32_t savePWM_CONTROL_LOGIC;
568
569 /*
570 * DSI info.
571 */
572 void * dbi_dsr_info;
573 void * dbi_dpu_info;
574 void * dsi_configs[2];
575 /*
576 * LID-Switch
577 */
578 spinlock_t lid_lock;
579 struct timer_list lid_timer;
580 struct psb_intel_opregion opregion;
581 u32 *lid_state;
582 u32 lid_last_state;
583
584 /*
585 * Watchdog
586 */
587
588 uint32_t apm_reg;
589 uint16_t apm_base;
590
591 /*
592 * Used for modifying backlight from
593 * xrandr -- consider removing and using HAL instead
594 */
595 struct backlight_device *backlight_device;
596 struct drm_property *backlight_property;
597 uint32_t blc_adj1;
598 uint32_t blc_adj2;
599
600 void *fbdev;
601
602 /* 2D acceleration */
603 struct mutex mutex_2d;
604};
605
606
607/*
608 * Operations for each board type
609 */
610
611struct psb_ops {
612 const char *name;
613 unsigned int accel_2d:1;
614 int pipes; /* Number of output pipes */
615 int crtcs; /* Number of CRTCs */
616 int sgx_offset; /* Base offset of SGX device */
617
618 /* Sub functions */
619 struct drm_crtc_helper_funcs const *crtc_helper;
620 struct drm_crtc_funcs const *crtc_funcs;
621
622 /* Setup hooks */
623 int (*chip_setup)(struct drm_device *dev);
624 void (*chip_teardown)(struct drm_device *dev);
625
626 /* Display management hooks */
627 int (*output_init)(struct drm_device *dev);
628 /* Power management hooks */
629 void (*init_pm)(struct drm_device *dev);
630 int (*save_regs)(struct drm_device *dev);
631 int (*restore_regs)(struct drm_device *dev);
632 int (*power_up)(struct drm_device *dev);
633 int (*power_down)(struct drm_device *dev);
634
635 void (*lvds_bl_power)(struct drm_device *dev, bool on);
636#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
637 /* Backlight */
638 int (*backlight_init)(struct drm_device *dev);
639#endif
640 int i2c_bus; /* I2C bus identifier for Moorestown */
641};
642
643
644
645struct psb_mmu_driver;
646
647extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
648extern int drm_pick_crtcs(struct drm_device *dev);
649
650static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
651{
652 return (struct drm_psb_private *) dev->dev_private;
653}
654
655/*
656 * MMU stuff.
657 */
658
659extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
660 int trap_pagefaults,
661 int invalid_type,
662 struct drm_psb_private *dev_priv);
663extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
664extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
665 *driver);
666extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
667 uint32_t gtt_start, uint32_t gtt_pages);
668extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
669 int trap_pagefaults,
670 int invalid_type);
671extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
672extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
673extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
674 unsigned long address,
675 uint32_t num_pages);
676extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
677 uint32_t start_pfn,
678 unsigned long address,
679 uint32_t num_pages, int type);
680extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
681 unsigned long *pfn);
682
683/*
684 * Enable / disable MMU for different requestors.
685 */
686
687
688extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
689extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
690 unsigned long address, uint32_t num_pages,
691 uint32_t desired_tile_stride,
692 uint32_t hw_tile_stride, int type);
693extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
694 unsigned long address, uint32_t num_pages,
695 uint32_t desired_tile_stride,
696 uint32_t hw_tile_stride);
697/*
698 *psb_irq.c
699 */
700
701extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
702extern int psb_irq_enable_dpst(struct drm_device *dev);
703extern int psb_irq_disable_dpst(struct drm_device *dev);
704extern void psb_irq_preinstall(struct drm_device *dev);
705extern int psb_irq_postinstall(struct drm_device *dev);
706extern void psb_irq_uninstall(struct drm_device *dev);
707extern void psb_irq_turn_on_dpst(struct drm_device *dev);
708extern void psb_irq_turn_off_dpst(struct drm_device *dev);
709
710extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
711extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
712extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
713extern int psb_enable_vblank(struct drm_device *dev, int crtc);
714extern void psb_disable_vblank(struct drm_device *dev, int crtc);
715void
716psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
717
718void
719psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
720
721extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
722
723/*
724 * intel_opregion.c
725 */
726extern int gma_intel_opregion_init(struct drm_device *dev);
727extern int gma_intel_opregion_exit(struct drm_device *dev);
728
729/*
730 * framebuffer.c
731 */
732extern int psbfb_probed(struct drm_device *dev);
733extern int psbfb_remove(struct drm_device *dev,
734 struct drm_framebuffer *fb);
735/*
736 * accel_2d.c
737 */
738extern void psbfb_copyarea(struct fb_info *info,
739 const struct fb_copyarea *region);
740extern int psbfb_sync(struct fb_info *info);
741extern void psb_spank(struct drm_psb_private *dev_priv);
742
743/*
744 * psb_reset.c
745 */
746
747extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
748extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
749extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
750
751/* modesetting */
752extern void psb_modeset_init(struct drm_device *dev);
753extern void psb_modeset_cleanup(struct drm_device *dev);
754extern int psb_fbdev_init(struct drm_device *dev);
755
756/* backlight.c */
757int gma_backlight_init(struct drm_device *dev);
758void gma_backlight_exit(struct drm_device *dev);
759
760/* oaktrail_crtc.c */
761extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
762
763/* oaktrail_lvds.c */
764extern void oaktrail_lvds_init(struct drm_device *dev,
765 struct psb_intel_mode_device *mode_dev);
766
767/* psb_intel_display.c */
768extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
769extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
770
771/* psb_intel_lvds.c */
772extern const struct drm_connector_helper_funcs
773 psb_intel_lvds_connector_helper_funcs;
774extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
775
776/* gem.c */
777extern int psb_gem_init_object(struct drm_gem_object *obj);
778extern void psb_gem_free_object(struct drm_gem_object *obj);
779extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
780 struct drm_file *file);
781extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
782 struct drm_mode_create_dumb *args);
783extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
784 uint32_t handle);
785extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
786 uint32_t handle, uint64_t *offset);
787extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
788extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
789 struct drm_file *file);
790extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file);
792
793/* psb_device.c */
794extern const struct psb_ops psb_chip_ops;
795
796/* oaktrail_device.c */
797extern const struct psb_ops oaktrail_chip_ops;
798
799/* cdv_device.c */
800extern const struct psb_ops cdv_chip_ops;
801
802/*
803 * Debug print bits setting
804 */
805#define PSB_D_GENERAL (1 << 0)
806#define PSB_D_INIT (1 << 1)
807#define PSB_D_IRQ (1 << 2)
808#define PSB_D_ENTRY (1 << 3)
809/* debug the get H/V BP/FP count */
810#define PSB_D_HV (1 << 4)
811#define PSB_D_DBI_BF (1 << 5)
812#define PSB_D_PM (1 << 6)
813#define PSB_D_RENDER (1 << 7)
814#define PSB_D_REG (1 << 8)
815#define PSB_D_MSVDX (1 << 9)
816#define PSB_D_TOPAZ (1 << 10)
817
818extern int drm_psb_no_fb;
819extern int drm_idle_check_interval;
820
821/*
822 * Utilities
823 */
824
825static inline u32 MRST_MSG_READ32(uint port, uint offset)
826{
827 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
828 uint32_t ret_val = 0;
829 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
830 pci_write_config_dword(pci_root, 0xD0, mcr);
831 pci_read_config_dword(pci_root, 0xD4, &ret_val);
832 pci_dev_put(pci_root);
833 return ret_val;
834}
835static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
836{
837 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
838 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
839 pci_write_config_dword(pci_root, 0xD4, value);
840 pci_write_config_dword(pci_root, 0xD0, mcr);
841 pci_dev_put(pci_root);
842}
843static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
844{
845 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
846 uint32_t ret_val = 0;
847 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
848 pci_write_config_dword(pci_root, 0xD0, mcr);
849 pci_read_config_dword(pci_root, 0xD4, &ret_val);
850 pci_dev_put(pci_root);
851 return ret_val;
852}
853static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
854{
855 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
856 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
857 pci_write_config_dword(pci_root, 0xD4, value);
858 pci_write_config_dword(pci_root, 0xD0, mcr);
859 pci_dev_put(pci_root);
860}
861
862static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
863{
864 struct drm_psb_private *dev_priv = dev->dev_private;
865 return ioread32(dev_priv->vdc_reg + reg);
866}
867
868#define REG_READ(reg) REGISTER_READ(dev, (reg))
869
870static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
871 uint32_t val)
872{
873 struct drm_psb_private *dev_priv = dev->dev_private;
874 iowrite32((val), dev_priv->vdc_reg + (reg));
875}
876
877#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
878
879static inline void REGISTER_WRITE16(struct drm_device *dev,
880 uint32_t reg, uint32_t val)
881{
882 struct drm_psb_private *dev_priv = dev->dev_private;
883 iowrite16((val), dev_priv->vdc_reg + (reg));
884}
885
886#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
887
888static inline void REGISTER_WRITE8(struct drm_device *dev,
889 uint32_t reg, uint32_t val)
890{
891 struct drm_psb_private *dev_priv = dev->dev_private;
892 iowrite8((val), dev_priv->vdc_reg + (reg));
893}
894
895#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
896
897#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
898#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
899
900/* #define TRAP_SGX_PM_FAULT 1 */
901#ifdef TRAP_SGX_PM_FAULT
902#define PSB_RSGX32(_offs) \
903({ \
904 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
905 printk(KERN_ERR \
906 "access sgx when it's off!! (READ) %s, %d\n", \
907 __FILE__, __LINE__); \
908 melay(1000); \
909 } \
910 ioread32(dev_priv->sgx_reg + (_offs)); \
911})
912#else
913#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
914#endif
915#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
916
917#define MSVDX_REG_DUMP 0
918
919#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
920#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
921
922#endif
ubuntu-zesty-kernel mirror