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gma500: mark framebuffer pages write combining
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / gma500 / psb_drv.h
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5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
e036ba59 45#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 46#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
47#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
48
49/*
50 * Driver definitions
51 */
52
53#define DRIVER_NAME "gma500"
54#define DRIVER_DESC "DRM driver for the Intel GMA500"
55
56#define PSB_DRM_DRIVER_DATE "2011-06-06"
57#define PSB_DRM_DRIVER_MAJOR 1
58#define PSB_DRM_DRIVER_MINOR 0
59#define PSB_DRM_DRIVER_PATCHLEVEL 0
60
61/*
62 * Hardware offsets
63 */
64#define PSB_VDC_OFFSET 0x00000000
65#define PSB_VDC_SIZE 0x000080000
66#define MRST_MMIO_SIZE 0x0000C0000
67#define MDFLD_MMIO_SIZE 0x000100000
68#define PSB_SGX_SIZE 0x8000
69#define PSB_SGX_OFFSET 0x00040000
70#define MRST_SGX_OFFSET 0x00080000
71/*
72 * PCI resource identifiers
73 */
74#define PSB_MMIO_RESOURCE 0
75#define PSB_GATT_RESOURCE 2
76#define PSB_GTT_RESOURCE 3
77/*
78 * PCI configuration
79 */
80#define PSB_GMCH_CTRL 0x52
81#define PSB_BSM 0x5C
82#define _PSB_GMCH_ENABLED 0x4
83#define PSB_PGETBL_CTL 0x2020
84#define _PSB_PGETBL_ENABLED 0x00000001
85#define PSB_SGX_2D_SLAVE_PORT 0x4000
86
87/* To get rid of */
88#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
90
91/*
92 * SGX side MMU definitions (these can probably go)
93 */
94
95/*
96 * Flags for external memory type field.
97 */
98#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
99#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
100#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
101/*
102 * PTE's and PDE's
103 */
104#define PSB_PDE_MASK 0x003FFFFF
105#define PSB_PDE_SHIFT 22
106#define PSB_PTE_SHIFT 12
107/*
108 * Cache control
109 */
110#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
111#define PSB_PTE_WO 0x0002 /* Write only */
112#define PSB_PTE_RO 0x0004 /* Read only */
113#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
114
115/*
116 * VDC registers and bits
117 */
118#define PSB_MSVDX_CLOCKGATING 0x2064
119#define PSB_TOPAZ_CLOCKGATING 0x2068
120#define PSB_HWSTAM 0x2098
121#define PSB_INSTPM 0x20C0
122#define PSB_INT_IDENTITY_R 0x20A4
123#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
124#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
125#define _PSB_DPST_PIPEB_FLAG (1<<4)
126#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
127#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
128#define _PSB_DPST_PIPEA_FLAG (1<<6)
129#define _PSB_PIPEA_EVENT_FLAG (1<<6)
130#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
131#define _MDFLD_MIPIA_FLAG (1<<16)
132#define _MDFLD_MIPIC_FLAG (1<<17)
133#define _PSB_IRQ_SGX_FLAG (1<<18)
134#define _PSB_IRQ_MSVDX_FLAG (1<<19)
135#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
136
700e59f6
PJ		 137#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
138 _PSB_VSYNC_PIPEB_FLAG)
139
5c49fd3a
AC		 140/* This flag includes all the display IRQ bits excepts the vblank irqs. */
141#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
142 _MDFLD_PIPEB_EVENT_FLAG | \
143 _PSB_PIPEA_EVENT_FLAG | \
144 _PSB_VSYNC_PIPEA_FLAG | \
145 _MDFLD_MIPIA_FLAG | \
146 _MDFLD_MIPIC_FLAG)
147#define PSB_INT_IDENTITY_R 0x20A4
148#define PSB_INT_MASK_R 0x20A8
149#define PSB_INT_ENABLE_R 0x20A0
150
151#define _PSB_MMU_ER_MASK 0x0001FF00
152#define _PSB_MMU_ER_HOST (1 << 16)
153#define GPIOA 0x5010
154#define GPIOB 0x5014
155#define GPIOC 0x5018
156#define GPIOD 0x501c
157#define GPIOE 0x5020
158#define GPIOF 0x5024
159#define GPIOG 0x5028
160#define GPIOH 0x502c
161#define GPIO_CLOCK_DIR_MASK (1 << 0)
162#define GPIO_CLOCK_DIR_IN (0 << 1)
163#define GPIO_CLOCK_DIR_OUT (1 << 1)
164#define GPIO_CLOCK_VAL_MASK (1 << 2)
165#define GPIO_CLOCK_VAL_OUT (1 << 3)
166#define GPIO_CLOCK_VAL_IN (1 << 4)
167#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
168#define GPIO_DATA_DIR_MASK (1 << 8)
169#define GPIO_DATA_DIR_IN (0 << 9)
170#define GPIO_DATA_DIR_OUT (1 << 9)
171#define GPIO_DATA_VAL_MASK (1 << 10)
172#define GPIO_DATA_VAL_OUT (1 << 11)
173#define GPIO_DATA_VAL_IN (1 << 12)
174#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
175
176#define VCLK_DIVISOR_VGA0 0x6000
177#define VCLK_DIVISOR_VGA1 0x6004
178#define VCLK_POST_DIV 0x6010
179
180#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
181#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
182#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
183#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
184#define PSB_COMM_USER_IRQ (1024 >> 2)
185#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
186#define PSB_COMM_FW (2048 >> 2)
187
188#define PSB_UIRQ_VISTEST 1
189#define PSB_UIRQ_OOM_REPLY 2
190#define PSB_UIRQ_FIRE_TA_REPLY 3
191#define PSB_UIRQ_FIRE_RASTER_REPLY 4
192
193#define PSB_2D_SIZE (256*1024*1024)
194#define PSB_MAX_RELOC_PAGES 1024
195
196#define PSB_LOW_REG_OFFS 0x0204
197#define PSB_HIGH_REG_OFFS 0x0600
198
199#define PSB_NUM_VBLANKS 2
200
201
202#define PSB_2D_SIZE (256*1024*1024)
203#define PSB_MAX_RELOC_PAGES 1024
204
205#define PSB_LOW_REG_OFFS 0x0204
206#define PSB_HIGH_REG_OFFS 0x0600
207
208#define PSB_NUM_VBLANKS 2
209#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
210#define PSB_LID_DELAY (DRM_HZ / 10)
211
212#define MDFLD_PNW_B0 0x04
213#define MDFLD_PNW_C0 0x08
214
215#define MDFLD_DSR_2D_3D_0 (1 << 0)
216#define MDFLD_DSR_2D_3D_2 (1 << 1)
217#define MDFLD_DSR_CURSOR_0 (1 << 2)
218#define MDFLD_DSR_CURSOR_2 (1 << 3)
219#define MDFLD_DSR_OVERLAY_0 (1 << 4)
220#define MDFLD_DSR_OVERLAY_2 (1 << 5)
221#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
222#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
223#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
224#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
225
226#define MDFLD_DSR_RR 45
227#define MDFLD_DPU_ENABLE (1 << 31)
228#define MDFLD_DSR_FULLSCREEN (1 << 30)
229#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
230
231#define PSB_PWR_STATE_ON 1
232#define PSB_PWR_STATE_OFF 2
233
234#define PSB_PMPOLICY_NOPM 0
235#define PSB_PMPOLICY_CLOCKGATING 1
236#define PSB_PMPOLICY_POWERDOWN 2
237
238#define PSB_PMSTATE_POWERUP 0
239#define PSB_PMSTATE_CLOCKGATED 1
240#define PSB_PMSTATE_POWERDOWN 2
241#define PSB_PCIx_MSI_ADDR_LOC 0x94
242#define PSB_PCIx_MSI_DATA_LOC 0x98
243
244/* Medfield crystal settings */
245#define KSEL_CRYSTAL_19 1
246#define KSEL_BYPASS_19 5
247#define KSEL_BYPASS_25 6
248#define KSEL_BYPASS_83_100 7
249
250struct opregion_header;
251struct opregion_acpi;
252struct opregion_swsci;
253struct opregion_asle;
254
255struct psb_intel_opregion {
256 struct opregion_header *header;
257 struct opregion_acpi *acpi;
258 struct opregion_swsci *swsci;
259 struct opregion_asle *asle;
260 int enabled;
261};
262
5736995b
PJ		 263struct sdvo_device_mapping {
264 u8 initialized;
265 u8 dvo_port;
266 u8 slave_addr;
267 u8 dvo_wiring;
268 u8 i2c_pin;
269 u8 i2c_speed;
270 u8 ddc_pin;
271};
272
5c0c1d50
PJ		 273struct intel_gmbus {
274 struct i2c_adapter adapter;
275 struct i2c_adapter *force_bit;
276 u32 reg0;
277};
278
648a8e34
AC		 279/*
280 * Register save state. This is used to hold the context when the
281 * device is powered off. In the case of Oaktrail this can (but does not
282 * yet) include screen blank. Operations occuring during the save
283 * update the register cache instead.
284 */
285struct psb_state {
286 uint32_t saveDSPACNTR;
287 uint32_t saveDSPBCNTR;
288 uint32_t savePIPEACONF;
289 uint32_t savePIPEBCONF;
290 uint32_t savePIPEASRC;
291 uint32_t savePIPEBSRC;
292 uint32_t saveFPA0;
293 uint32_t saveFPA1;
294 uint32_t saveDPLL_A;
295 uint32_t saveDPLL_A_MD;
296 uint32_t saveHTOTAL_A;
297 uint32_t saveHBLANK_A;
298 uint32_t saveHSYNC_A;
299 uint32_t saveVTOTAL_A;
300 uint32_t saveVBLANK_A;
301 uint32_t saveVSYNC_A;
302 uint32_t saveDSPASTRIDE;
303 uint32_t saveDSPASIZE;
304 uint32_t saveDSPAPOS;
305 uint32_t saveDSPABASE;
306 uint32_t saveDSPASURF;
307 uint32_t saveDSPASTATUS;
308 uint32_t saveFPB0;
309 uint32_t saveFPB1;
310 uint32_t saveDPLL_B;
311 uint32_t saveDPLL_B_MD;
312 uint32_t saveHTOTAL_B;
313 uint32_t saveHBLANK_B;
314 uint32_t saveHSYNC_B;
315 uint32_t saveVTOTAL_B;
316 uint32_t saveVBLANK_B;
317 uint32_t saveVSYNC_B;
318 uint32_t saveDSPBSTRIDE;
319 uint32_t saveDSPBSIZE;
320 uint32_t saveDSPBPOS;
321 uint32_t saveDSPBBASE;
322 uint32_t saveDSPBSURF;
323 uint32_t saveDSPBSTATUS;
324 uint32_t saveVCLK_DIVISOR_VGA0;
325 uint32_t saveVCLK_DIVISOR_VGA1;
326 uint32_t saveVCLK_POST_DIV;
327 uint32_t saveVGACNTRL;
328 uint32_t saveADPA;
329 uint32_t saveLVDS;
330 uint32_t saveDVOA;
331 uint32_t saveDVOB;
332 uint32_t saveDVOC;
333 uint32_t savePP_ON;
334 uint32_t savePP_OFF;
335 uint32_t savePP_CONTROL;
336 uint32_t savePP_CYCLE;
337 uint32_t savePFIT_CONTROL;
338 uint32_t savePaletteA[256];
339 uint32_t savePaletteB[256];
648a8e34
AC		 340 uint32_t saveCLOCKGATING;
341 uint32_t saveDSPARB;
342 uint32_t saveDSPATILEOFF;
343 uint32_t saveDSPBTILEOFF;
344 uint32_t saveDSPAADDR;
345 uint32_t saveDSPBADDR;
346 uint32_t savePFIT_AUTO_RATIOS;
347 uint32_t savePFIT_PGM_RATIOS;
348 uint32_t savePP_ON_DELAYS;
349 uint32_t savePP_OFF_DELAYS;
350 uint32_t savePP_DIVISOR;
648a8e34
AC		 351 uint32_t saveBCLRPAT_A;
352 uint32_t saveBCLRPAT_B;
353 uint32_t saveDSPALINOFF;
354 uint32_t saveDSPBLINOFF;
355 uint32_t savePERF_MODE;
356 uint32_t saveDSPFW1;
357 uint32_t saveDSPFW2;
358 uint32_t saveDSPFW3;
359 uint32_t saveDSPFW4;
360 uint32_t saveDSPFW5;
361 uint32_t saveDSPFW6;
362 uint32_t saveCHICKENBIT;
363 uint32_t saveDSPACURSOR_CTRL;
364 uint32_t saveDSPBCURSOR_CTRL;
365 uint32_t saveDSPACURSOR_BASE;
366 uint32_t saveDSPBCURSOR_BASE;
367 uint32_t saveDSPACURSOR_POS;
368 uint32_t saveDSPBCURSOR_POS;
369 uint32_t save_palette_a[256];
370 uint32_t save_palette_b[256];
371 uint32_t saveOV_OVADD;
372 uint32_t saveOV_OGAMC0;
373 uint32_t saveOV_OGAMC1;
374 uint32_t saveOV_OGAMC2;
375 uint32_t saveOV_OGAMC3;
376 uint32_t saveOV_OGAMC4;
377 uint32_t saveOV_OGAMC5;
378 uint32_t saveOVC_OVADD;
379 uint32_t saveOVC_OGAMC0;
380 uint32_t saveOVC_OGAMC1;
381 uint32_t saveOVC_OGAMC2;
382 uint32_t saveOVC_OGAMC3;
383 uint32_t saveOVC_OGAMC4;
384 uint32_t saveOVC_OGAMC5;
385
386 /* DPST register save */
387 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
388 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
389 uint32_t savePWM_CONTROL_LOGIC;
390};
391
026abc33
KS		 392struct medfield_state {
393 uint32_t saveDPLL_A;
394 uint32_t saveFPA0;
395 uint32_t savePIPEACONF;
396 uint32_t saveHTOTAL_A;
397 uint32_t saveHBLANK_A;
398 uint32_t saveHSYNC_A;
399 uint32_t saveVTOTAL_A;
400 uint32_t saveVBLANK_A;
401 uint32_t saveVSYNC_A;
402 uint32_t savePIPEASRC;
403 uint32_t saveDSPASTRIDE;
404 uint32_t saveDSPALINOFF;
405 uint32_t saveDSPATILEOFF;
406 uint32_t saveDSPASIZE;
407 uint32_t saveDSPAPOS;
408 uint32_t saveDSPASURF;
409 uint32_t saveDSPACNTR;
410 uint32_t saveDSPASTATUS;
411 uint32_t save_palette_a[256];
412 uint32_t saveMIPI;
413
414 uint32_t saveDPLL_B;
415 uint32_t saveFPB0;
416 uint32_t savePIPEBCONF;
417 uint32_t saveHTOTAL_B;
418 uint32_t saveHBLANK_B;
419 uint32_t saveHSYNC_B;
420 uint32_t saveVTOTAL_B;
421 uint32_t saveVBLANK_B;
422 uint32_t saveVSYNC_B;
423 uint32_t savePIPEBSRC;
424 uint32_t saveDSPBSTRIDE;
425 uint32_t saveDSPBLINOFF;
426 uint32_t saveDSPBTILEOFF;
427 uint32_t saveDSPBSIZE;
428 uint32_t saveDSPBPOS;
429 uint32_t saveDSPBSURF;
430 uint32_t saveDSPBCNTR;
431 uint32_t saveDSPBSTATUS;
432 uint32_t save_palette_b[256];
433
434 uint32_t savePIPECCONF;
435 uint32_t saveHTOTAL_C;
436 uint32_t saveHBLANK_C;
437 uint32_t saveHSYNC_C;
438 uint32_t saveVTOTAL_C;
439 uint32_t saveVBLANK_C;
440 uint32_t saveVSYNC_C;
441 uint32_t savePIPECSRC;
442 uint32_t saveDSPCSTRIDE;
443 uint32_t saveDSPCLINOFF;
444 uint32_t saveDSPCTILEOFF;
445 uint32_t saveDSPCSIZE;
446 uint32_t saveDSPCPOS;
447 uint32_t saveDSPCSURF;
448 uint32_t saveDSPCCNTR;
449 uint32_t saveDSPCSTATUS;
450 uint32_t save_palette_c[256];
451 uint32_t saveMIPI_C;
452
453 uint32_t savePFIT_CONTROL;
454 uint32_t savePFIT_PGM_RATIOS;
455 uint32_t saveHDMIPHYMISCCTL;
456 uint32_t saveHDMIB_CONTROL;
457};
458
09016a11
AC		 459struct cdv_state {
460 uint32_t saveDSPCLK_GATE_D;
461 uint32_t saveRAMCLK_GATE_D;
462 uint32_t saveDSPARB;
463 uint32_t saveDSPFW[6];
464 uint32_t saveADPA;
465 uint32_t savePP_CONTROL;
466 uint32_t savePFIT_PGM_RATIOS;
467 uint32_t saveLVDS;
468 uint32_t savePFIT_CONTROL;
469 uint32_t savePP_ON_DELAYS;
470 uint32_t savePP_OFF_DELAYS;
471 uint32_t savePP_CYCLE;
472 uint32_t saveVGACNTRL;
473 uint32_t saveIER;
474 uint32_t saveIMR;
475 u8 saveLBB;
476};
477
c6265ff5
AC		 478struct psb_save_area {
479 uint32_t saveBSM;
480 uint32_t saveVBT;
481 union {
482 struct psb_state psb;
026abc33 483 struct medfield_state mdfld;
09016a11 484 struct cdv_state cdv;
c6265ff5
AC		 485 };
486 uint32_t saveBLC_PWM_CTL2;
487 uint32_t saveBLC_PWM_CTL;
488};
489
5c49fd3a
AC		 490struct psb_ops;
491
04bd564f
AC		 492#define PSB_NUM_PIPE 3
493
5c49fd3a
AC		 494struct drm_psb_private {
495 struct drm_device *dev;
496 const struct psb_ops *ops;
497
498 struct psb_gtt gtt;
499
500 /* GTT Memory manager */
501 struct psb_gtt_mm *gtt_mm;
502 struct page *scratch_page;
503 u32 *gtt_map;
504 uint32_t stolen_base;
505 void *vram_addr;
506 unsigned long vram_stolen_size;
507 int gtt_initialized;
508 u16 gmch_ctrl; /* Saved GTT setup */
509 u32 pge_ctl;
510
511 struct mutex gtt_mutex;
512 struct resource *gtt_mem; /* Our PCI resource */
513
514 struct psb_mmu_driver *mmu;
515 struct psb_mmu_pd *pf_pd;
516
517 /*
518 * Register base
519 */
520
521 uint8_t *sgx_reg;
522 uint8_t *vdc_reg;
523 uint32_t gatt_free_offset;
524
525 /*
526 * Fencing / irq.
527 */
528
529 uint32_t vdc_irq_mask;
530 uint32_t pipestat[PSB_NUM_PIPE];
531
532 spinlock_t irqmask_lock;
533
534 /*
535 * Power
536 */
537
538 bool suspended;
539 bool display_power;
540 int display_count;
541
542 /*
543 * Modesetting
544 */
545 struct psb_intel_mode_device mode_dev;
546
547 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
548 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
549 uint32_t num_pipe;
550
551 /*
552 * OSPM info (Power management base) (can go ?)
553 */
554 uint32_t ospm_base;
555
556 /*
557 * Sizes info
558 */
559
5c49fd3a
AC		 560 u32 fuse_reg_value;
561 u32 video_device_fuse;
562
563 /* PCI revision ID for B0:D2:F0 */
564 uint8_t platform_rev_id;
565
5c0c1d50
PJ		 566 /* gmbus */
567 struct intel_gmbus *gmbus;
568
5736995b
PJ		 569 /* Used by SDVO */
570 int crt_ddc_pin;
571 /* FIXME: The mappings should be parsed from bios but for now we can
572 pretend there are no mappings available */
573 struct sdvo_device_mapping sdvo_mappings[2];
574 u32 hotplug_supported_mask;
575 struct drm_property *broadcast_rgb_property;
576 struct drm_property *force_audio_property;
577
5c49fd3a
AC		 578 /*
579 * LVDS info
580 */
581 int backlight_duty_cycle; /* restore backlight to this value */
582 bool panel_wants_dither;
583 struct drm_display_mode *panel_fixed_mode;
584 struct drm_display_mode *lfp_lvds_vbt_mode;
585 struct drm_display_mode *sdvo_lvds_vbt_mode;
586
587 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 588 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 589
590 /* Feature bits from the VBIOS */
591 unsigned int int_tv_support:1;
592 unsigned int lvds_dither:1;
593 unsigned int lvds_vbt:1;
594 unsigned int int_crt_support:1;
595 unsigned int lvds_use_ssc:1;
596 int lvds_ssc_freq;
597 bool is_lvds_on;
598 bool is_mipi_on;
599 u32 mipi_ctrl_display;
600
601 unsigned int core_freq;
602 uint32_t iLVDS_enable;
603
604 /* Runtime PM state */
605 int rpm_enabled;
606
607 /* MID specific */
608 struct oaktrail_vbt vbt_data;
609 struct oaktrail_gct_data gct_data;
610
933315ac 611 /* Oaktrail HDMI state */
5c49fd3a 612 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 613
5c49fd3a
AC		 614 /*
615 * Register state
616 */
c6265ff5
AC		 617
618 struct psb_save_area regs;
619
5c49fd3a
AC		 620 /* MSI reg save */
621 uint32_t msi_addr;
622 uint32_t msi_data;
623
5c49fd3a 624
5c49fd3a
AC		 625 /*
626 * LID-Switch
627 */
628 spinlock_t lid_lock;
629 struct timer_list lid_timer;
630 struct psb_intel_opregion opregion;
631 u32 *lid_state;
632 u32 lid_last_state;
633
634 /*
635 * Watchdog
636 */
637
638 uint32_t apm_reg;
639 uint16_t apm_base;
640
641 /*
642 * Used for modifying backlight from
643 * xrandr -- consider removing and using HAL instead
644 */
645 struct backlight_device *backlight_device;
646 struct drm_property *backlight_property;
647 uint32_t blc_adj1;
648 uint32_t blc_adj2;
649
650 void *fbdev;
651
652 /* 2D acceleration */
9242fe23 653 spinlock_t lock_2d;
026abc33
KS		 654
655 /*
656 * Panel brightness
657 */
658 int brightness;
659 int brightness_adjusted;
660
661 bool dsr_enable;
662 u32 dsr_fb_update;
663 bool dpi_panel_on[3];
664 void *dsi_configs[2];
665 u32 bpp;
666 u32 bpp2;
667
668 u32 pipeconf[3];
669 u32 dspcntr[3];
670
671 int mdfld_panel_id;
642c52fc
AC		 672
673 bool dplla_96mhz; /* DPLL data from the VBT */
5c49fd3a
AC		 674};
675
676
677/*
678 * Operations for each board type
679 */
680
681struct psb_ops {
682 const char *name;
683 unsigned int accel_2d:1;
684 int pipes; /* Number of output pipes */
685 int crtcs; /* Number of CRTCs */
686 int sgx_offset; /* Base offset of SGX device */
687
688 /* Sub functions */
689 struct drm_crtc_helper_funcs const *crtc_helper;
690 struct drm_crtc_funcs const *crtc_funcs;
691
692 /* Setup hooks */
693 int (*chip_setup)(struct drm_device *dev);
694 void (*chip_teardown)(struct drm_device *dev);
695
696 /* Display management hooks */
697 int (*output_init)(struct drm_device *dev);
698 /* Power management hooks */
699 void (*init_pm)(struct drm_device *dev);
700 int (*save_regs)(struct drm_device *dev);
701 int (*restore_regs)(struct drm_device *dev);
702 int (*power_up)(struct drm_device *dev);
703 int (*power_down)(struct drm_device *dev);
704
705 void (*lvds_bl_power)(struct drm_device *dev, bool on);
706#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
707 /* Backlight */
708 int (*backlight_init)(struct drm_device *dev);
709#endif
710 int i2c_bus; /* I2C bus identifier for Moorestown */
711};
712
713
714
715struct psb_mmu_driver;
716
717extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
718extern int drm_pick_crtcs(struct drm_device *dev);
719
720static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
721{
722 return (struct drm_psb_private *) dev->dev_private;
723}
724
725/*
726 * MMU stuff.
727 */
728
729extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
730 int trap_pagefaults,
731 int invalid_type,
732 struct drm_psb_private *dev_priv);
733extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
734extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
735 *driver);
736extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
737 uint32_t gtt_start, uint32_t gtt_pages);
738extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
739 int trap_pagefaults,
740 int invalid_type);
741extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
742extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
743extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
744 unsigned long address,
745 uint32_t num_pages);
746extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
747 uint32_t start_pfn,
748 unsigned long address,
749 uint32_t num_pages, int type);
750extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
751 unsigned long *pfn);
752
753/*
754 * Enable / disable MMU for different requestors.
755 */
756
757
758extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
759extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
760 unsigned long address, uint32_t num_pages,
761 uint32_t desired_tile_stride,
762 uint32_t hw_tile_stride, int type);
763extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
764 unsigned long address, uint32_t num_pages,
765 uint32_t desired_tile_stride,
766 uint32_t hw_tile_stride);
767/*
768 *psb_irq.c
769 */
770
771extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
772extern int psb_irq_enable_dpst(struct drm_device *dev);
773extern int psb_irq_disable_dpst(struct drm_device *dev);
774extern void psb_irq_preinstall(struct drm_device *dev);
775extern int psb_irq_postinstall(struct drm_device *dev);
776extern void psb_irq_uninstall(struct drm_device *dev);
777extern void psb_irq_turn_on_dpst(struct drm_device *dev);
778extern void psb_irq_turn_off_dpst(struct drm_device *dev);
779
780extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
781extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
782extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
783extern int psb_enable_vblank(struct drm_device *dev, int crtc);
784extern void psb_disable_vblank(struct drm_device *dev, int crtc);
785void
786psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
787
788void
789psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
790
791extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
792
793/*
794 * intel_opregion.c
795 */
796extern int gma_intel_opregion_init(struct drm_device *dev);
797extern int gma_intel_opregion_exit(struct drm_device *dev);
798
799/*
800 * framebuffer.c
801 */
802extern int psbfb_probed(struct drm_device *dev);
803extern int psbfb_remove(struct drm_device *dev,
804 struct drm_framebuffer *fb);
805/*
806 * accel_2d.c
807 */
808extern void psbfb_copyarea(struct fb_info *info,
809 const struct fb_copyarea *region);
810extern int psbfb_sync(struct fb_info *info);
811extern void psb_spank(struct drm_psb_private *dev_priv);
812
813/*
814 * psb_reset.c
815 */
816
817extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
818extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
819extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
820
821/* modesetting */
822extern void psb_modeset_init(struct drm_device *dev);
823extern void psb_modeset_cleanup(struct drm_device *dev);
824extern int psb_fbdev_init(struct drm_device *dev);
825
826/* backlight.c */
827int gma_backlight_init(struct drm_device *dev);
828void gma_backlight_exit(struct drm_device *dev);
829
830/* oaktrail_crtc.c */
831extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
832
833/* oaktrail_lvds.c */
834extern void oaktrail_lvds_init(struct drm_device *dev,
835 struct psb_intel_mode_device *mode_dev);
836
837/* psb_intel_display.c */
838extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
839extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
840
841/* psb_intel_lvds.c */
842extern const struct drm_connector_helper_funcs
843 psb_intel_lvds_connector_helper_funcs;
844extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
845
846/* gem.c */
847extern int psb_gem_init_object(struct drm_gem_object *obj);
848extern void psb_gem_free_object(struct drm_gem_object *obj);
849extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
850 struct drm_file *file);
851extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
852 struct drm_mode_create_dumb *args);
853extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
854 uint32_t handle);
855extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
856 uint32_t handle, uint64_t *offset);
857extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
858extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
859 struct drm_file *file);
860extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
861 struct drm_file *file);
862
863/* psb_device.c */
864extern const struct psb_ops psb_chip_ops;
865
866/* oaktrail_device.c */
867extern const struct psb_ops oaktrail_chip_ops;
868
026abc33
KS		 869/* mdlfd_device.c */
870extern const struct psb_ops mdfld_chip_ops;
871
5c49fd3a
AC		 872/* cdv_device.c */
873extern const struct psb_ops cdv_chip_ops;
874
875/*
876 * Debug print bits setting
877 */
878#define PSB_D_GENERAL (1 << 0)
879#define PSB_D_INIT (1 << 1)
880#define PSB_D_IRQ (1 << 2)
881#define PSB_D_ENTRY (1 << 3)
882/* debug the get H/V BP/FP count */
883#define PSB_D_HV (1 << 4)
884#define PSB_D_DBI_BF (1 << 5)
885#define PSB_D_PM (1 << 6)
886#define PSB_D_RENDER (1 << 7)
887#define PSB_D_REG (1 << 8)
888#define PSB_D_MSVDX (1 << 9)
889#define PSB_D_TOPAZ (1 << 10)
890
891extern int drm_psb_no_fb;
892extern int drm_idle_check_interval;
893
894/*
895 * Utilities
896 */
897
898static inline u32 MRST_MSG_READ32(uint port, uint offset)
899{
900 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
901 uint32_t ret_val = 0;
902 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
903 pci_write_config_dword(pci_root, 0xD0, mcr);
904 pci_read_config_dword(pci_root, 0xD4, &ret_val);
905 pci_dev_put(pci_root);
906 return ret_val;
907}
908static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
909{
910 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
911 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
912 pci_write_config_dword(pci_root, 0xD4, value);
913 pci_write_config_dword(pci_root, 0xD0, mcr);
914 pci_dev_put(pci_root);
915}
916static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
917{
918 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
919 uint32_t ret_val = 0;
920 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
921 pci_write_config_dword(pci_root, 0xD0, mcr);
922 pci_read_config_dword(pci_root, 0xD4, &ret_val);
923 pci_dev_put(pci_root);
924 return ret_val;
925}
926static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
927{
928 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
929 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
930 pci_write_config_dword(pci_root, 0xD4, value);
931 pci_write_config_dword(pci_root, 0xD0, mcr);
932 pci_dev_put(pci_root);
933}
934
935static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
936{
937 struct drm_psb_private *dev_priv = dev->dev_private;
938 return ioread32(dev_priv->vdc_reg + reg);
939}
940
941#define REG_READ(reg) REGISTER_READ(dev, (reg))
942
943static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
944 uint32_t val)
945{
946 struct drm_psb_private *dev_priv = dev->dev_private;
947 iowrite32((val), dev_priv->vdc_reg + (reg));
948}
949
950#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
951
952static inline void REGISTER_WRITE16(struct drm_device *dev,
953 uint32_t reg, uint32_t val)
954{
955 struct drm_psb_private *dev_priv = dev->dev_private;
956 iowrite16((val), dev_priv->vdc_reg + (reg));
957}
958
959#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
960
961static inline void REGISTER_WRITE8(struct drm_device *dev,
962 uint32_t reg, uint32_t val)
963{
964 struct drm_psb_private *dev_priv = dev->dev_private;
965 iowrite8((val), dev_priv->vdc_reg + (reg));
966}
967
968#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
969
970#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
971#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
972
973/* #define TRAP_SGX_PM_FAULT 1 */
974#ifdef TRAP_SGX_PM_FAULT
975#define PSB_RSGX32(_offs) \
976({ \
977 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
978 printk(KERN_ERR \
979 "access sgx when it's off!! (READ) %s, %d\n", \
980 __FILE__, __LINE__); \
981 melay(1000); \
982 } \
983 ioread32(dev_priv->sgx_reg + (_offs)); \
984})
985#else
986#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
987#endif
988#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
989
990#define MSVDX_REG_DUMP 0
991
992#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
993#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
994
995#endif
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