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drm/i915: Call hsw_fdi_link_train() directly()
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / display / intel_ddi.c
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45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
cfda08cd 32#include "intel_combo_phy.h"
ec7f29ff 33#include "intel_connector.h"
fdc24cf3 34#include "intel_ddi.h"
1d455f8d 35#include "intel_display_types.h"
27fec1f9 36#include "intel_dp.h"
e075094f 37#include "intel_dp_link_training.h"
b1ad4c39 38#include "intel_dpio_phy.h"
1dd07e56 39#include "intel_dsi.h"
8834e365 40#include "intel_fifo_underrun.h"
3ce2ea65 41#include "intel_gmbus.h"
408bd917 42#include "intel_hdcp.h"
0550691d 43#include "intel_hdmi.h"
dbeb38d9 44#include "intel_hotplug.h"
f3e18947 45#include "intel_lspcon.h"
44c1220a 46#include "intel_panel.h"
55367a27 47#include "intel_psr.h"
bdacf087 48#include "intel_sprite.h"
bc85328f 49#include "intel_tc.h"
b375d0ef 50#include "intel_vdsc.h"
45244b87 51
10122051
JN		 52struct ddi_buf_trans {
53 u32 trans1; /* balance leg enable, de-emph level */
54 u32 trans2; /* vref sel, vswing */
f8896f5d 55 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 56};
57
97eeb872
VS		 58static const u8 index_to_dp_signal_levels[] = {
59 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
60 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
61 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
62 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
63 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
64 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
65 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
66 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
67 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
68 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
69};
70
45244b87
ED		 71/* HDMI/DVI modes ignore everything but the last 2 items. So we share
72 * them for both DP and FDI transports, allowing those ports to
73 * automatically adapt to HDMI connections as well
74 */
10122051 75static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 76 { 0x00FFFFFF, 0x0006000E, 0x0 },
77 { 0x00D75FFF, 0x0005000A, 0x0 },
78 { 0x00C30FFF, 0x00040006, 0x0 },
79 { 0x80AAAFFF, 0x000B0000, 0x0 },
80 { 0x00FFFFFF, 0x0005000A, 0x0 },
81 { 0x00D75FFF, 0x000C0004, 0x0 },
82 { 0x80C30FFF, 0x000B0000, 0x0 },
83 { 0x00FFFFFF, 0x00040006, 0x0 },
84 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 85};
86
10122051 87static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 88 { 0x00FFFFFF, 0x0007000E, 0x0 },
89 { 0x00D75FFF, 0x000F000A, 0x0 },
90 { 0x00C30FFF, 0x00060006, 0x0 },
91 { 0x00AAAFFF, 0x001E0000, 0x0 },
92 { 0x00FFFFFF, 0x000F000A, 0x0 },
93 { 0x00D75FFF, 0x00160004, 0x0 },
94 { 0x00C30FFF, 0x001E0000, 0x0 },
95 { 0x00FFFFFF, 0x00060006, 0x0 },
96 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 97};
98
10122051
JN		 99static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
100 /* Idx NT mV d T mV d db */
f8896f5d
DW		 101 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
102 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
103 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
104 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
105 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
106 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
107 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
108 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
109 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
110 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
111 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
112 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 113};
114
10122051 115static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 116 { 0x00FFFFFF, 0x00000012, 0x0 },
117 { 0x00EBAFFF, 0x00020011, 0x0 },
118 { 0x00C71FFF, 0x0006000F, 0x0 },
119 { 0x00AAAFFF, 0x000E000A, 0x0 },
120 { 0x00FFFFFF, 0x00020011, 0x0 },
121 { 0x00DB6FFF, 0x0005000F, 0x0 },
122 { 0x00BEEFFF, 0x000A000C, 0x0 },
123 { 0x00FFFFFF, 0x0005000F, 0x0 },
124 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 125};
126
10122051 127static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 128 { 0x00FFFFFF, 0x0007000E, 0x0 },
129 { 0x00D75FFF, 0x000E000A, 0x0 },
130 { 0x00BEFFFF, 0x00140006, 0x0 },
131 { 0x80B2CFFF, 0x001B0002, 0x0 },
132 { 0x00FFFFFF, 0x000E000A, 0x0 },
133 { 0x00DB6FFF, 0x00160005, 0x0 },
134 { 0x80C71FFF, 0x001A0002, 0x0 },
135 { 0x00F7DFFF, 0x00180004, 0x0 },
136 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 137};
138
10122051 139static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 140 { 0x00FFFFFF, 0x0001000E, 0x0 },
141 { 0x00D75FFF, 0x0004000A, 0x0 },
142 { 0x00C30FFF, 0x00070006, 0x0 },
143 { 0x00AAAFFF, 0x000C0000, 0x0 },
144 { 0x00FFFFFF, 0x0004000A, 0x0 },
145 { 0x00D75FFF, 0x00090004, 0x0 },
146 { 0x00C30FFF, 0x000C0000, 0x0 },
147 { 0x00FFFFFF, 0x00070006, 0x0 },
148 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 149};
150
10122051
JN		 151static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
152 /* Idx NT mV d T mV df db */
f8896f5d
DW		 153 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
154 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
155 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
156 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
157 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
158 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
159 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
160 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
161 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
162 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 163};
164
5f8b2531 165/* Skylake H and S */
7f88e3af 166static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 167 { 0x00002016, 0x000000A0, 0x0 },
168 { 0x00005012, 0x0000009B, 0x0 },
169 { 0x00007011, 0x00000088, 0x0 },
d7097cff 170 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 171 { 0x00002016, 0x0000009B, 0x0 },
172 { 0x00005012, 0x00000088, 0x0 },
d7097cff 173 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 174 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 175 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 176};
177
f8896f5d
DW		 178/* Skylake U */
179static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 180 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 181 { 0x00005012, 0x00000088, 0x0 },
5ac90567 182 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 183 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 184 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 185 { 0x80005012, 0x000000C0, 0x1 },
186 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 187 { 0x00002016, 0x00000088, 0x0 },
d7097cff 188 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 189};
190
5f8b2531
RV		 191/* Skylake Y */
192static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 193 { 0x00000018, 0x000000A2, 0x0 },
194 { 0x00005012, 0x00000088, 0x0 },
5ac90567 195 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 196 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 197 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 198 { 0x80005012, 0x000000C0, 0x3 },
199 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 200 { 0x00000018, 0x00000088, 0x0 },
d7097cff 201 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 202};
203
0fdd4918
RV		 204/* Kabylake H and S */
205static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
206 { 0x00002016, 0x000000A0, 0x0 },
207 { 0x00005012, 0x0000009B, 0x0 },
208 { 0x00007011, 0x00000088, 0x0 },
209 { 0x80009010, 0x000000C0, 0x1 },
210 { 0x00002016, 0x0000009B, 0x0 },
211 { 0x00005012, 0x00000088, 0x0 },
212 { 0x80007011, 0x000000C0, 0x1 },
213 { 0x00002016, 0x00000097, 0x0 },
214 { 0x80005012, 0x000000C0, 0x1 },
215};
216
217/* Kabylake U */
218static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
219 { 0x0000201B, 0x000000A1, 0x0 },
220 { 0x00005012, 0x00000088, 0x0 },
221 { 0x80007011, 0x000000CD, 0x3 },
222 { 0x80009010, 0x000000C0, 0x3 },
223 { 0x0000201B, 0x0000009D, 0x0 },
224 { 0x80005012, 0x000000C0, 0x3 },
225 { 0x80007011, 0x000000C0, 0x3 },
226 { 0x00002016, 0x0000004F, 0x0 },
227 { 0x80005012, 0x000000C0, 0x3 },
228};
229
230/* Kabylake Y */
231static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
232 { 0x00001017, 0x000000A1, 0x0 },
233 { 0x00005012, 0x00000088, 0x0 },
234 { 0x80007011, 0x000000CD, 0x3 },
235 { 0x8000800F, 0x000000C0, 0x3 },
236 { 0x00001017, 0x0000009D, 0x0 },
237 { 0x80005012, 0x000000C0, 0x3 },
238 { 0x80007011, 0x000000C0, 0x3 },
239 { 0x00001017, 0x0000004C, 0x0 },
240 { 0x80005012, 0x000000C0, 0x3 },
241};
242
f8896f5d 243/*
0fdd4918 244 * Skylake/Kabylake H and S
f8896f5d
DW		 245 * eDP 1.4 low vswing translation parameters
246 */
7ad14a29 247static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 248 { 0x00000018, 0x000000A8, 0x0 },
249 { 0x00004013, 0x000000A9, 0x0 },
250 { 0x00007011, 0x000000A2, 0x0 },
251 { 0x00009010, 0x0000009C, 0x0 },
252 { 0x00000018, 0x000000A9, 0x0 },
253 { 0x00006013, 0x000000A2, 0x0 },
254 { 0x00007011, 0x000000A6, 0x0 },
255 { 0x00000018, 0x000000AB, 0x0 },
256 { 0x00007013, 0x0000009F, 0x0 },
257 { 0x00000018, 0x000000DF, 0x0 },
258};
259
260/*
0fdd4918 261 * Skylake/Kabylake U
f8896f5d
DW		 262 * eDP 1.4 low vswing translation parameters
263 */
264static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
265 { 0x00000018, 0x000000A8, 0x0 },
266 { 0x00004013, 0x000000A9, 0x0 },
267 { 0x00007011, 0x000000A2, 0x0 },
268 { 0x00009010, 0x0000009C, 0x0 },
269 { 0x00000018, 0x000000A9, 0x0 },
270 { 0x00006013, 0x000000A2, 0x0 },
271 { 0x00007011, 0x000000A6, 0x0 },
272 { 0x00002016, 0x000000AB, 0x0 },
273 { 0x00005013, 0x0000009F, 0x0 },
274 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 275};
276
f8896f5d 277/*
0fdd4918 278 * Skylake/Kabylake Y
f8896f5d
DW		 279 * eDP 1.4 low vswing translation parameters
280 */
5f8b2531 281static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 282 { 0x00000018, 0x000000A8, 0x0 },
283 { 0x00004013, 0x000000AB, 0x0 },
284 { 0x00007011, 0x000000A4, 0x0 },
285 { 0x00009010, 0x000000DF, 0x0 },
286 { 0x00000018, 0x000000AA, 0x0 },
287 { 0x00006013, 0x000000A4, 0x0 },
288 { 0x00007011, 0x0000009D, 0x0 },
289 { 0x00000018, 0x000000A0, 0x0 },
290 { 0x00006012, 0x000000DF, 0x0 },
291 { 0x00000018, 0x0000008A, 0x0 },
292};
7ad14a29 293
0fdd4918 294/* Skylake/Kabylake U, H and S */
7f88e3af 295static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 296 { 0x00000018, 0x000000AC, 0x0 },
297 { 0x00005012, 0x0000009D, 0x0 },
298 { 0x00007011, 0x00000088, 0x0 },
299 { 0x00000018, 0x000000A1, 0x0 },
300 { 0x00000018, 0x00000098, 0x0 },
301 { 0x00004013, 0x00000088, 0x0 },
2e78416e 302 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 303 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 304 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
305 { 0x80003015, 0x000000C0, 0x1 },
306 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 307};
308
0fdd4918 309/* Skylake/Kabylake Y */
5f8b2531 310static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 311 { 0x00000018, 0x000000A1, 0x0 },
312 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 313 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 314 { 0x00000018, 0x000000A4, 0x0 },
315 { 0x00000018, 0x0000009D, 0x0 },
316 { 0x00004013, 0x00000080, 0x0 },
2e78416e 317 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 318 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 319 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
320 { 0x80003015, 0x000000C0, 0x3 },
321 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 322};
323
96fb9f9b 324struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 325 u8 margin; /* swing value */
326 u8 scale; /* scale value */
327 u8 enable; /* scale enable */
328 u8 deemphasis;
96fb9f9b
VK		 329};
330
96fb9f9b
VK		 331static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
332 /* Idx NT mV diff db */
043eaf36
VS		 333 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
334 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
335 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
336 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
337 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
338 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
339 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
340 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
341 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
342 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 343};
344
d9d7000d
SJ		 345static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
346 /* Idx NT mV diff db */
043eaf36
VS		 347 { 26, 0, 0, 128, }, /* 0: 200 0 */
348 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
349 { 48, 0, 0, 96, }, /* 2: 200 4 */
350 { 54, 0, 0, 69, }, /* 3: 200 6 */
351 { 32, 0, 0, 128, }, /* 4: 250 0 */
352 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
353 { 54, 0, 0, 85, }, /* 6: 250 4 */
354 { 43, 0, 0, 128, }, /* 7: 300 0 */
355 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
356 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 357};
358
96fb9f9b
VK		 359/* BSpec has 2 recommended values - entries 0 and 8.
360 * Using the entry with higher vswing.
361 */
362static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
363 /* Idx NT mV diff db */
043eaf36
VS		 364 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
365 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
366 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
367 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
368 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
369 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
370 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
371 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
372 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
373 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 374};
375
83fb7ab4 376struct cnl_ddi_buf_trans {
fb5f4e96
VS		 377 u8 dw2_swing_sel;
378 u8 dw7_n_scalar;
379 u8 dw4_cursor_coeff;
380 u8 dw4_post_cursor_2;
381 u8 dw4_post_cursor_1;
83fb7ab4
RV		 382};
383
384/* Voltage Swing Programming for VccIO 0.85V for DP */
385static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
386 /* NT mV Trans mV db */
387 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
388 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
389 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
390 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
391 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
392 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
393 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
394 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
395 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
396 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
397};
398
399/* Voltage Swing Programming for VccIO 0.85V for HDMI */
400static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
401 /* NT mV Trans mV db */
402 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
403 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
404 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
405 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
406 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
407 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
408 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
409};
410
411/* Voltage Swing Programming for VccIO 0.85V for eDP */
412static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
413 /* NT mV Trans mV db */
414 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
415 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
416 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
417 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
418 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
419 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
420 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
421 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
422 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423};
424
425/* Voltage Swing Programming for VccIO 0.95V for DP */
426static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
427 /* NT mV Trans mV db */
428 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
429 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
430 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
431 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
432 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
433 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
434 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
435 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
436 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
437 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
438};
439
440/* Voltage Swing Programming for VccIO 0.95V for HDMI */
441static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
442 /* NT mV Trans mV db */
443 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
444 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
445 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
446 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
447 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
448 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
449 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
450 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
451 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
452 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
453 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
454};
455
456/* Voltage Swing Programming for VccIO 0.95V for eDP */
457static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
458 /* NT mV Trans mV db */
459 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
460 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
461 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
462 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
463 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
464 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
465 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
466 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
467 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
468 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469};
470
471/* Voltage Swing Programming for VccIO 1.05V for DP */
472static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
473 /* NT mV Trans mV db */
474 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
475 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
476 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
477 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
478 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
479 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
480 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
481 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
482 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
483 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
484};
485
486/* Voltage Swing Programming for VccIO 1.05V for HDMI */
487static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
488 /* NT mV Trans mV db */
489 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
490 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
491 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
492 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
493 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
494 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
495 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
496 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
497 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
498 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
499 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
500};
501
502/* Voltage Swing Programming for VccIO 1.05V for eDP */
503static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
504 /* NT mV Trans mV db */
505 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
506 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
507 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
508 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
509 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
510 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
511 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
512 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
513 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
514};
515
b265a2a6
CT		 516/* icl_combo_phy_ddi_translations */
517static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
518 /* NT mV Trans mV db */
519 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
520 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
521 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
522 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
523 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
524 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
525 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
526 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
527 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
528 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 529};
530
b265a2a6
CT		 531static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
532 /* NT mV Trans mV db */
533 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
534 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
535 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
536 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
537 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
538 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
539 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
540 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
541 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
542 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 543};
544
b265a2a6
CT		 545static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
546 /* NT mV Trans mV db */
547 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
548 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
549 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
550 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
551 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
552 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
553 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
554 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
555 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
556 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 557};
558
b265a2a6
CT		 559static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
560 /* NT mV Trans mV db */
561 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
562 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
563 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
564 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
565 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
566 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
567 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 568};
569
cd96bea7
MN		 570struct icl_mg_phy_ddi_buf_trans {
571 u32 cri_txdeemph_override_5_0;
572 u32 cri_txdeemph_override_11_6;
573 u32 cri_txdeemph_override_17_12;
574};
575
576static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
577 /* Voltage swing pre-emphasis */
578 { 0x0, 0x1B, 0x00 }, /* 0 0 */
579 { 0x0, 0x23, 0x08 }, /* 0 1 */
580 { 0x0, 0x2D, 0x12 }, /* 0 2 */
581 { 0x0, 0x00, 0x00 }, /* 0 3 */
582 { 0x0, 0x23, 0x00 }, /* 1 0 */
583 { 0x0, 0x2B, 0x09 }, /* 1 1 */
584 { 0x0, 0x2E, 0x11 }, /* 1 2 */
585 { 0x0, 0x2F, 0x00 }, /* 2 0 */
586 { 0x0, 0x33, 0x0C }, /* 2 1 */
587 { 0x0, 0x00, 0x00 }, /* 3 0 */
588};
589
978c3e53
CT		 590struct tgl_dkl_phy_ddi_buf_trans {
591 u32 dkl_vswing_control;
592 u32 dkl_preshoot_control;
593 u32 dkl_de_emphasis_control;
594};
595
362bfb99 596static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
978c3e53
CT		 597 /* VS pre-emp Non-trans mV Pre-emph dB */
598 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
599 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */
600 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */
601 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
602 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
603 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */
604 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
605 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
606 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
607 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
608};
609
362bfb99
MR		 610static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
611 /* HDMI Preset VS Pre-emph */
612 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
613 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
614 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
615 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
616 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
617 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
618 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
619 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
620 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
621 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
622};
623
a930acd9
VS		 624static const struct ddi_buf_trans *
625bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
626{
627 if (dev_priv->vbt.edp.low_vswing) {
628 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
629 return bdw_ddi_translations_edp;
630 } else {
631 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
632 return bdw_ddi_translations_dp;
633 }
634}
635
acee2998 636static const struct ddi_buf_trans *
78ab0bae 637skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 638{
0fdd4918 639 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 640 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 641 return skl_y_ddi_translations_dp;
0fdd4918 642 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 643 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 644 return skl_u_ddi_translations_dp;
f8896f5d 645 } else {
f8896f5d 646 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 647 return skl_ddi_translations_dp;
f8896f5d 648 }
f8896f5d
DW		 649}
650
0fdd4918
RV		 651static const struct ddi_buf_trans *
652kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
653{
6ce1c33d 654 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
0fdd4918
RV		 655 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
656 return kbl_y_ddi_translations_dp;
da411a48 657 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 658 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
659 return kbl_u_ddi_translations_dp;
660 } else {
661 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
662 return kbl_ddi_translations_dp;
663 }
664}
665
acee2998 666static const struct ddi_buf_trans *
78ab0bae 667skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 668{
06411f08 669 if (dev_priv->vbt.edp.low_vswing) {
6ce1c33d
VS		 670 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
671 IS_CFL_ULX(dev_priv)) {
5f8b2531 672 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 673 return skl_y_ddi_translations_edp;
da411a48
RV		 674 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
675 IS_CFL_ULT(dev_priv)) {
f8896f5d 676 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 677 return skl_u_ddi_translations_edp;
f8896f5d 678 } else {
f8896f5d 679 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 680 return skl_ddi_translations_edp;
f8896f5d
DW		 681 }
682 }
cd1101cb 683
da411a48 684 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 685 return kbl_get_buf_trans_dp(dev_priv, n_entries);
686 else
687 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 688}
689
690static const struct ddi_buf_trans *
78ab0bae 691skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 692{
6ce1c33d
VS		 693 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
694 IS_CFL_ULX(dev_priv)) {
5f8b2531 695 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 696 return skl_y_ddi_translations_hdmi;
f8896f5d 697 } else {
f8896f5d 698 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 699 return skl_ddi_translations_hdmi;
f8896f5d 700 }
f8896f5d
DW		 701}
702
edba48fd
VS		 703static int skl_buf_trans_num_entries(enum port port, int n_entries)
704{
705 /* Only DDIA and DDIE can select the 10th register with DP */
706 if (port == PORT_A || port == PORT_E)
707 return min(n_entries, 10);
708 else
709 return min(n_entries, 9);
710}
711
d8fe2c7f
VS		 712static const struct ddi_buf_trans *
713intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 714 enum port port, int *n_entries)
d8fe2c7f
VS		 715{
716 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 717 const struct ddi_buf_trans *ddi_translations =
718 kbl_get_buf_trans_dp(dev_priv, n_entries);
719 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
720 return ddi_translations;
d8fe2c7f 721 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 722 const struct ddi_buf_trans *ddi_translations =
723 skl_get_buf_trans_dp(dev_priv, n_entries);
724 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
725 return ddi_translations;
d8fe2c7f
VS		 726 } else if (IS_BROADWELL(dev_priv)) {
727 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
728 return bdw_ddi_translations_dp;
729 } else if (IS_HASWELL(dev_priv)) {
730 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
731 return hsw_ddi_translations_dp;
732 }
733
734 *n_entries = 0;
735 return NULL;
736}
737
738static const struct ddi_buf_trans *
739intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 740 enum port port, int *n_entries)
d8fe2c7f
VS		 741{
742 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 743 const struct ddi_buf_trans *ddi_translations =
744 skl_get_buf_trans_edp(dev_priv, n_entries);
745 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
746 return ddi_translations;
d8fe2c7f
VS		 747 } else if (IS_BROADWELL(dev_priv)) {
748 return bdw_get_buf_trans_edp(dev_priv, n_entries);
749 } else if (IS_HASWELL(dev_priv)) {
750 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
751 return hsw_ddi_translations_dp;
752 }
753
754 *n_entries = 0;
755 return NULL;
756}
757
758static const struct ddi_buf_trans *
759intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
760 int *n_entries)
761{
762 if (IS_BROADWELL(dev_priv)) {
763 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
764 return bdw_ddi_translations_fdi;
765 } else if (IS_HASWELL(dev_priv)) {
766 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
767 return hsw_ddi_translations_fdi;
768 }
769
770 *n_entries = 0;
771 return NULL;
772}
773
975786ee
VS		 774static const struct ddi_buf_trans *
775intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
776 int *n_entries)
777{
778 if (IS_GEN9_BC(dev_priv)) {
779 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
780 } else if (IS_BROADWELL(dev_priv)) {
781 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
782 return bdw_ddi_translations_hdmi;
783 } else if (IS_HASWELL(dev_priv)) {
784 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
785 return hsw_ddi_translations_hdmi;
786 }
787
788 *n_entries = 0;
789 return NULL;
790}
791
7d4f37b5
VS		 792static const struct bxt_ddi_buf_trans *
793bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
794{
795 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
796 return bxt_ddi_translations_dp;
797}
798
799static const struct bxt_ddi_buf_trans *
800bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
801{
802 if (dev_priv->vbt.edp.low_vswing) {
803 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
804 return bxt_ddi_translations_edp;
805 }
806
807 return bxt_get_buf_trans_dp(dev_priv, n_entries);
808}
809
810static const struct bxt_ddi_buf_trans *
811bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
812{
813 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
814 return bxt_ddi_translations_hdmi;
815}
816
cf3e0fb4
RV		 817static const struct cnl_ddi_buf_trans *
818cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
819{
820 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
821
822 if (voltage == VOLTAGE_INFO_0_85V) {
823 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
824 return cnl_ddi_translations_hdmi_0_85V;
825 } else if (voltage == VOLTAGE_INFO_0_95V) {
826 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
827 return cnl_ddi_translations_hdmi_0_95V;
828 } else if (voltage == VOLTAGE_INFO_1_05V) {
829 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
830 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 831 } else {
832 *n_entries = 1; /* shut up gcc */
cf3e0fb4 833 MISSING_CASE(voltage);
83482ca3 834 }
cf3e0fb4
RV		 835 return NULL;
836}
837
838static const struct cnl_ddi_buf_trans *
839cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
840{
841 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
842
843 if (voltage == VOLTAGE_INFO_0_85V) {
844 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
845 return cnl_ddi_translations_dp_0_85V;
846 } else if (voltage == VOLTAGE_INFO_0_95V) {
847 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
848 return cnl_ddi_translations_dp_0_95V;
849 } else if (voltage == VOLTAGE_INFO_1_05V) {
850 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
851 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 852 } else {
853 *n_entries = 1; /* shut up gcc */
cf3e0fb4 854 MISSING_CASE(voltage);
83482ca3 855 }
cf3e0fb4
RV		 856 return NULL;
857}
858
859static const struct cnl_ddi_buf_trans *
860cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
861{
862 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
863
864 if (dev_priv->vbt.edp.low_vswing) {
865 if (voltage == VOLTAGE_INFO_0_85V) {
866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
867 return cnl_ddi_translations_edp_0_85V;
868 } else if (voltage == VOLTAGE_INFO_0_95V) {
869 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
870 return cnl_ddi_translations_edp_0_95V;
871 } else if (voltage == VOLTAGE_INFO_1_05V) {
872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
873 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 874 } else {
875 *n_entries = 1; /* shut up gcc */
cf3e0fb4 876 MISSING_CASE(voltage);
83482ca3 877 }
cf3e0fb4
RV		 878 return NULL;
879 } else {
880 return cnl_get_buf_trans_dp(dev_priv, n_entries);
881 }
882}
883
b265a2a6 884static const struct cnl_ddi_buf_trans *
4a8134d5
MR		 885icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
886 int *n_entries)
fb5c8e9d 887{
b265a2a6
CT		 888 if (type == INTEL_OUTPUT_HDMI) {
889 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
890 return icl_combo_phy_ddi_translations_hdmi;
891 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
892 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
893 return icl_combo_phy_ddi_translations_edp_hbr3;
894 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
895 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
896 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 897 }
b265a2a6
CT		 898
899 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
900 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 901}
902
8d8bb85e
VS		 903static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
904{
7a0073d6 905 struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
d02ace87 906 int n_entries, level, default_entry;
d8fe2ab6 907 enum phy phy = intel_port_to_phy(dev_priv, port);
8d8bb85e 908
978c3e53
CT		 909 if (INTEL_GEN(dev_priv) >= 12) {
910 if (intel_phy_is_combo(dev_priv, phy))
911 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
912 0, &n_entries);
913 else
362bfb99 914 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
978c3e53
CT		 915 default_entry = n_entries - 1;
916 } else if (INTEL_GEN(dev_priv) == 11) {
d8fe2ab6 917 if (intel_phy_is_combo(dev_priv, phy))
4a8134d5 918 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
b265a2a6 919 0, &n_entries);
dccc7228
MN		 920 else
921 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
922 default_entry = n_entries - 1;
923 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 924 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
925 default_entry = n_entries - 1;
043eaf36 926 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 927 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
928 default_entry = n_entries - 1;
bf503556 929 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 930 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
931 default_entry = 8;
8d8bb85e 932 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 933 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
934 default_entry = 7;
8d8bb85e 935 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 936 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
937 default_entry = 6;
8d8bb85e
VS		 938 } else {
939 WARN(1, "ddi translation table missing\n");
975786ee 940 return 0;
8d8bb85e
VS		 941 }
942
d02ace87 943 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 944 return 0;
7a0073d6
JN		 945
946 if (port_info->hdmi_level_shift_set)
947 level = port_info->hdmi_level_shift;
948 else
949 level = default_entry;
950
d02ace87
VS		 951 if (WARN_ON_ONCE(level >= n_entries))
952 level = n_entries - 1;
21b39d2a 953
d02ace87 954 return level;
8d8bb85e
VS		 955}
956
e58623cb
AR		 957/*
958 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 959 * values in advance. This function programs the correct values for
960 * DP/eDP/FDI use cases.
45244b87 961 */
3a6d84e6
VS		 962static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
963 const struct intel_crtc_state *crtc_state)
45244b87 964{
6a7e4f99 965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 966 u32 iboost_bit = 0;
7d1c42e6 967 int i, n_entries;
0fce04c8 968 enum port port = encoder->port;
10122051 969 const struct ddi_buf_trans *ddi_translations;
e58623cb 970
3a6d84e6
VS		 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
973 &n_entries);
974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 976 &n_entries);
3a6d84e6 977 else
edba48fd 978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 979 &n_entries);
e58623cb 980
edba48fd
VS		 981 /* If we're boosting the current, set bit 31 of trans1 */
982 if (IS_GEN9_BC(dev_priv) &&
983 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 985
7d1c42e6 986 for (i = 0; i < n_entries; i++) {
9712e688
VS		 987 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
988 ddi_translations[i].trans1 | iboost_bit);
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
990 ddi_translations[i].trans2);
45244b87 991 }
32bdc400
VS		 992}
993
994/*
995 * Starting with Haswell, DDI port buffers must be programmed with correct
996 * values in advance. This function programs the correct values for
997 * HDMI/DVI use cases.
998 */
7ea79333 999static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 1000 int level)
32bdc400
VS		 1001{
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003 u32 iboost_bit = 0;
d02ace87 1004 int n_entries;
0fce04c8 1005 enum port port = encoder->port;
d02ace87 1006 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 1007
d02ace87 1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 1009
d02ace87 1010 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 1011 return;
d02ace87
VS		 1012 if (WARN_ON_ONCE(level >= n_entries))
1013 level = n_entries - 1;
21b39d2a 1014
975786ee
VS		 1015 /* If we're boosting the current, set bit 31 of trans1 */
1016 if (IS_GEN9_BC(dev_priv) &&
1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 1019
6acab15a 1020 /* Entry 9 is for HDMI: */
ed9c77d2 1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 1022 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 1024 ddi_translations[level].trans2);
45244b87
ED		 1025}
1026
248138b5
PZ		 1027static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028 enum port port)
1029{
f0f59a00 1030 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 1031 int i;
1032
3449ca85 1033 for (i = 0; i < 16; i++) {
248138b5
PZ		 1034 udelay(1);
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036 return;
1037 }
1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039}
c82e4d26 1040
3d0c5005 1041static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 1042{
0823eb9c 1043 switch (pll->info->id) {
c856052a
ACO		 1044 case DPLL_ID_WRPLL1:
1045 return PORT_CLK_SEL_WRPLL1;
1046 case DPLL_ID_WRPLL2:
1047 return PORT_CLK_SEL_WRPLL2;
1048 case DPLL_ID_SPLL:
1049 return PORT_CLK_SEL_SPLL;
1050 case DPLL_ID_LCPLL_810:
1051 return PORT_CLK_SEL_LCPLL_810;
1052 case DPLL_ID_LCPLL_1350:
1053 return PORT_CLK_SEL_LCPLL_1350;
1054 case DPLL_ID_LCPLL_2700:
1055 return PORT_CLK_SEL_LCPLL_2700;
1056 default:
0823eb9c 1057 MISSING_CASE(pll->info->id);
c856052a
ACO		 1058 return PORT_CLK_SEL_NONE;
1059 }
1060}
1061
20fd2ab7 1062static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1063 const struct intel_crtc_state *crtc_state)
c27e917e 1064{
0e5fa646
ML		 1065 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1066 int clock = crtc_state->port_clock;
c27e917e
PZ		 1067 const enum intel_dpll_id id = pll->info->id;
1068
1069 switch (id) {
1070 default:
20fd2ab7
LDM		 1071 /*
1072 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1073 * here, so do warn if this get passed in
1074 */
c27e917e 1075 MISSING_CASE(id);
c27e917e 1076 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1077 case DPLL_ID_ICL_TBTPLL:
1078 switch (clock) {
1079 case 162000:
1080 return DDI_CLK_SEL_TBT_162;
1081 case 270000:
1082 return DDI_CLK_SEL_TBT_270;
1083 case 540000:
1084 return DDI_CLK_SEL_TBT_540;
1085 case 810000:
1086 return DDI_CLK_SEL_TBT_810;
1087 default:
1088 MISSING_CASE(clock);
7a61a6de 1089 return DDI_CLK_SEL_NONE;
1fa11ee2 1090 }
c27e917e
PZ		 1091 case DPLL_ID_ICL_MGPLL1:
1092 case DPLL_ID_ICL_MGPLL2:
1093 case DPLL_ID_ICL_MGPLL3:
1094 case DPLL_ID_ICL_MGPLL4:
6677c3b1
JRS		 1095 case DPLL_ID_TGL_MGPLL5:
1096 case DPLL_ID_TGL_MGPLL6:
c27e917e
PZ		 1097 return DDI_CLK_SEL_MG;
1098 }
1099}
1100
c82e4d26
ED		 1101/* Starting with Haswell, different DDI ports can work in FDI mode for
1102 * connection to the PCH-located connectors. For this, it is necessary to train
1103 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1104 *
1105 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1106 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1107 * DDI A (which is used for eDP)
1108 */
1109
6a6d79de 1110void hsw_fdi_link_train(struct intel_encoder *encoder,
dc4a1094 1111 const struct intel_crtc_state *crtc_state)
c82e4d26 1112{
6a6d79de
VS		 1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
c856052a 1115 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1116
6a6d79de 1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99 1118
04945641
PZ		 1119 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1120 * mode set "sequence for CRT port" document:
1121 * - TP1 to TP2 time with the default value
1122 * - FDI delay to 90h
8693a824
DL		 1123 *
1124 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1125 */
eede3b53 1126 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1127 FDI_RX_PWRDN_LANE0_VAL(2) |
1128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1129
1130 /* Enable the PCH Receiver FDI PLL */
3e68320e 1131 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1132 FDI_RX_PLL_ENABLE |
dc4a1094 1133 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1134 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1135 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1136 udelay(220);
1137
1138 /* Switch from Rawclk to PCDclk */
1139 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1141
1142 /* Configure Port Clock Select */
dc4a1094 1143 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1144 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1145 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1146
1147 /* Start the training iterating through available voltages and emphasis,
1148 * testing each value twice. */
10122051 1149 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1150 /* Configure DP_TP_CTL with auto-training */
1151 I915_WRITE(DP_TP_CTL(PORT_E),
1152 DP_TP_CTL_FDI_AUTOTRAIN |
1153 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1154 DP_TP_CTL_LINK_TRAIN_PAT1 |
1155 DP_TP_CTL_ENABLE);
1156
876a8cdf
DL		 1157 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1158 * DDI E does not support port reversal, the functionality is
1159 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1160 * port reversal bit */
c82e4d26 1161 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1162 DDI_BUF_CTL_ENABLE |
dc4a1094 1163 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1164 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1165 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1166
1167 udelay(600);
1168
04945641 1169 /* Program PCH FDI Receiver TU */
eede3b53 1170 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1171
1172 /* Enable PCH FDI Receiver with auto-training */
1173 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1174 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1175 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1176
1177 /* Wait for FDI receiver lane calibration */
1178 udelay(30);
1179
1180 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1181 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1182 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1183 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1184 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1185
1186 /* Wait for FDI auto training time */
1187 udelay(5);
c82e4d26
ED		 1188
1189 temp = I915_READ(DP_TP_STATUS(PORT_E));
1190 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1191 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1192 break;
1193 }
c82e4d26 1194
a308ccb3
VS		 1195 /*
1196 * Leave things enabled even if we failed to train FDI.
1197 * Results in less fireworks from the state checker.
1198 */
1199 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1200 DRM_ERROR("FDI link training failed!\n");
1201 break;
c82e4d26 1202 }
04945641 1203
5b421c57
VS		 1204 rx_ctl_val &= ~FDI_RX_ENABLE;
1205 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1206 POSTING_READ(FDI_RX_CTL(PIPE_A));
1207
248138b5
PZ		 1208 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1209 temp &= ~DDI_BUF_CTL_ENABLE;
1210 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1211 POSTING_READ(DDI_BUF_CTL(PORT_E));
1212
04945641 1213 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1214 temp = I915_READ(DP_TP_CTL(PORT_E));
1215 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1216 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1217 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1218 POSTING_READ(DP_TP_CTL(PORT_E));
1219
1220 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1221
04945641 1222 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1223 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1224 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1225 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1226 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1227 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1228 }
1229
a308ccb3
VS		 1230 /* Enable normal pixel sending for FDI */
1231 I915_WRITE(DP_TP_CTL(PORT_E),
1232 DP_TP_CTL_FDI_AUTOTRAIN |
1233 DP_TP_CTL_LINK_TRAIN_NORMAL |
1234 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1235 DP_TP_CTL_ENABLE);
c82e4d26 1236}
0e72a5b5 1237
d7c530b2 1238static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1239{
1240 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1241 struct intel_digital_port *intel_dig_port =
1242 enc_to_dig_port(&encoder->base);
1243
1244 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1245 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1246 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1247}
1248
8d9ddbcb 1249static struct intel_encoder *
e9ce1a62 1250intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1251{
e9ce1a62 1252 struct drm_device *dev = crtc->base.dev;
1524e93e 1253 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1254 int num_encoders = 0;
1255
1524e93e
SS		 1256 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1257 ret = encoder;
8d9ddbcb
PZ		 1258 num_encoders++;
1259 }
1260
1261 if (num_encoders != 1)
84f44ce7 1262 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1263 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1264
1265 BUG_ON(ret == NULL);
1266 return ret;
1267}
1268
f0f59a00
VS		 1269static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1270 i915_reg_t reg)
11578553 1271{
0f52c097 1272 int refclk;
11578553
JB		 1273 int n, p, r;
1274 u32 wrpll;
1275
1276 wrpll = I915_READ(reg);
4a95e36f
VS		 1277 switch (wrpll & WRPLL_REF_MASK) {
1278 case WRPLL_REF_SPECIAL_HSW:
86761789
VS		 1279 /*
1280 * muxed-SSC for BDW.
1281 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1282 * for the non-SSC reference frequency.
1283 */
1284 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1285 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1286 refclk = 24;
1287 else
1288 refclk = 135;
1289 break;
1290 }
1291 /* fall through */
4a95e36f 1292 case WRPLL_REF_PCH_SSC:
11578553
JB		 1293 /*
1294 * We could calculate spread here, but our checking
1295 * code only cares about 5% accuracy, and spread is a max of
1296 * 0.5% downspread.
1297 */
1298 refclk = 135;
1299 break;
4a95e36f 1300 case WRPLL_REF_LCPLL:
0f52c097 1301 refclk = 2700;
11578553
JB		 1302 break;
1303 default:
86761789 1304 MISSING_CASE(wrpll);
11578553
JB		 1305 return 0;
1306 }
1307
1308 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1309 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1310 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1311
20f0ec16
JB		 1312 /* Convert to KHz, p & r have a fixed point portion */
1313 return (refclk * n * 100) / (p * r);
11578553
JB		 1314}
1315
947f4417 1316static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1317{
3d0c5005 1318 u32 p0, p1, p2, dco_freq;
540e732c 1319
947f4417
LDM		 1320 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1321 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1322
947f4417
LDM		 1323 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1324 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1325 else
1326 p1 = 1;
1327
1328
1329 switch (p0) {
1330 case DPLL_CFGCR2_PDIV_1:
1331 p0 = 1;
1332 break;
1333 case DPLL_CFGCR2_PDIV_2:
1334 p0 = 2;
1335 break;
1336 case DPLL_CFGCR2_PDIV_3:
1337 p0 = 3;
1338 break;
1339 case DPLL_CFGCR2_PDIV_7:
1340 p0 = 7;
1341 break;
1342 }
1343
1344 switch (p2) {
1345 case DPLL_CFGCR2_KDIV_5:
1346 p2 = 5;
1347 break;
1348 case DPLL_CFGCR2_KDIV_2:
1349 p2 = 2;
1350 break;
1351 case DPLL_CFGCR2_KDIV_3:
1352 p2 = 3;
1353 break;
1354 case DPLL_CFGCR2_KDIV_1:
1355 p2 = 1;
1356 break;
1357 }
1358
947f4417
LDM		 1359 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1360 * 24 * 1000;
540e732c 1361
947f4417
LDM		 1362 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1363 * 24 * 1000) / 0x8000;
540e732c 1364
b8449c43
YX		 1365 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1366 return 0;
1367
540e732c
S		 1368 return dco_freq / (p0 * p1 * p2 * 5);
1369}
1370
8327af28 1371int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1372 struct intel_dpll_hw_state *pll_state)
a9701a89 1373{
3d0c5005 1374 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1375
5e65216d
LDM		 1376 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1377 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1378
5e65216d
LDM		 1379 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1380 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1381 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1382 else
1383 p1 = 1;
1384
1385
1386 switch (p0) {
1387 case DPLL_CFGCR1_PDIV_2:
1388 p0 = 2;
1389 break;
1390 case DPLL_CFGCR1_PDIV_3:
1391 p0 = 3;
1392 break;
1393 case DPLL_CFGCR1_PDIV_5:
1394 p0 = 5;
1395 break;
1396 case DPLL_CFGCR1_PDIV_7:
1397 p0 = 7;
1398 break;
1399 }
1400
1401 switch (p2) {
1402 case DPLL_CFGCR1_KDIV_1:
1403 p2 = 1;
1404 break;
1405 case DPLL_CFGCR1_KDIV_2:
1406 p2 = 2;
1407 break;
2ee7fd1e
VS		 1408 case DPLL_CFGCR1_KDIV_3:
1409 p2 = 3;
a9701a89
RV		 1410 break;
1411 }
1412
9f9d594d 1413 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1414
5e65216d
LDM		 1415 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1416 * ref_clock;
a9701a89 1417
5e65216d 1418 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1419 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1420
0e005888
PZ		 1421 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1422 return 0;
1423
a9701a89
RV		 1424 return dco_freq / (p0 * p1 * p2 * 5);
1425}
1426
7b19f544
MN		 1427static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1428 enum port port)
1429{
1430 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1431
1432 switch (val) {
1433 case DDI_CLK_SEL_NONE:
1434 return 0;
1435 case DDI_CLK_SEL_TBT_162:
1436 return 162000;
1437 case DDI_CLK_SEL_TBT_270:
1438 return 270000;
1439 case DDI_CLK_SEL_TBT_540:
1440 return 540000;
1441 case DDI_CLK_SEL_TBT_810:
1442 return 810000;
1443 default:
1444 MISSING_CASE(val);
1445 return 0;
1446 }
1447}
1448
1449static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1450 const struct intel_dpll_hw_state *pll_state)
7b19f544 1451{
02c99d26 1452 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1453 u64 tmp;
1454
02c99d26 1455 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1456
ee7de6ad
JRS		 1457 if (INTEL_GEN(dev_priv) >= 12) {
1458 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1459 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1460 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1461
1462 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1463 m2_frac = pll_state->mg_pll_bias &
1464 DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1465 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1466 } else {
1467 m2_frac = 0;
1468 }
1469 } else {
1470 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1471 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1472
1473 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1474 m2_frac = pll_state->mg_pll_div0 &
1475 MG_PLL_DIV0_FBDIV_FRAC_MASK;
1476 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1477 } else {
1478 m2_frac = 0;
1479 }
1480 }
7b19f544 1481
02c99d26
LDM		 1482 switch (pll_state->mg_clktop2_hsclkctl &
1483 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1484 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1485 div1 = 2;
1486 break;
1487 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1488 div1 = 3;
1489 break;
1490 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1491 div1 = 5;
1492 break;
1493 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1494 div1 = 7;
1495 break;
1496 default:
02c99d26 1497 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1498 return 0;
1499 }
1500
02c99d26
LDM		 1501 div2 = (pll_state->mg_clktop2_hsclkctl &
1502 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1503 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1504
7b19f544
MN		 1505 /* div2 value of 0 is same as 1 means no div */
1506 if (div2 == 0)
1507 div2 = 1;
1508
1509 /*
1510 * Adjust the original formula to delay the division by 2^22 in order to
1511 * minimize possible rounding errors.
1512 */
02c99d26
LDM		 1513 tmp = (u64)m1 * m2_int * ref_clock +
1514 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1515 tmp = div_u64(tmp, 5 * div1 * div2);
1516
1517 return tmp;
1518}
1519
398a017e
VS		 1520static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1521{
1522 int dotclock;
1523
1524 if (pipe_config->has_pch_encoder)
1525 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1526 &pipe_config->fdi_m_n);
37a5650b 1527 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1528 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1529 &pipe_config->dp_m_n);
2969a78a
ID		 1530 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1531 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
398a017e
VS		 1532 else
1533 dotclock = pipe_config->port_clock;
1534
16668f48
GM		 1535 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1536 !intel_crtc_has_dp_encoder(pipe_config))
b22ca995
SS		 1537 dotclock *= 2;
1538
398a017e
VS		 1539 if (pipe_config->pixel_multiplier)
1540 dotclock /= pipe_config->pixel_multiplier;
1541
1326a92c 1542 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
398a017e 1543}
540e732c 1544
51c83cfa
MN		 1545static void icl_ddi_clock_get(struct intel_encoder *encoder,
1546 struct intel_crtc_state *pipe_config)
1547{
1548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1549 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1550 enum port port = encoder->port;
d8fe2ab6 1551 enum phy phy = intel_port_to_phy(dev_priv, port);
5e65216d 1552 int link_clock;
51c83cfa 1553
d8fe2ab6 1554 if (intel_phy_is_combo(dev_priv, phy)) {
5e65216d 1555 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1556 } else {
077973c8
LDM		 1557 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1558 pipe_config->shared_dpll);
1559
7b19f544
MN		 1560 if (pll_id == DPLL_ID_ICL_TBTPLL)
1561 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1562 else
02c99d26 1563 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1564 }
1565
1566 pipe_config->port_clock = link_clock;
02c99d26 1567
51c83cfa
MN		 1568 ddi_dotclock_get(pipe_config);
1569}
1570
a9701a89
RV		 1571static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1572 struct intel_crtc_state *pipe_config)
1573{
1574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1575 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1576 int link_clock;
a9701a89 1577
5e65216d
LDM		 1578 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1579 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1580 } else {
5e65216d 1581 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1582
1583 switch (link_clock) {
1584 case DPLL_CFGCR0_LINK_RATE_810:
1585 link_clock = 81000;
1586 break;
1587 case DPLL_CFGCR0_LINK_RATE_1080:
1588 link_clock = 108000;
1589 break;
1590 case DPLL_CFGCR0_LINK_RATE_1350:
1591 link_clock = 135000;
1592 break;
1593 case DPLL_CFGCR0_LINK_RATE_1620:
1594 link_clock = 162000;
1595 break;
1596 case DPLL_CFGCR0_LINK_RATE_2160:
1597 link_clock = 216000;
1598 break;
1599 case DPLL_CFGCR0_LINK_RATE_2700:
1600 link_clock = 270000;
1601 break;
1602 case DPLL_CFGCR0_LINK_RATE_3240:
1603 link_clock = 324000;
1604 break;
1605 case DPLL_CFGCR0_LINK_RATE_4050:
1606 link_clock = 405000;
1607 break;
1608 default:
1609 WARN(1, "Unsupported link rate\n");
1610 break;
1611 }
1612 link_clock *= 2;
1613 }
1614
1615 pipe_config->port_clock = link_clock;
1616
1617 ddi_dotclock_get(pipe_config);
1618}
1619
540e732c 1620static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1621 struct intel_crtc_state *pipe_config)
540e732c 1622{
947f4417
LDM		 1623 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1624 int link_clock;
540e732c 1625
947f4417
LDM		 1626 /*
1627 * ctrl1 register is already shifted for each pll, just use 0 to get
1628 * the internal shift for each field
1629 */
1630 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1631 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1632 } else {
947f4417
LDM		 1633 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1634 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1635
1636 switch (link_clock) {
71cd8423 1637 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1638 link_clock = 81000;
1639 break;
71cd8423 1640 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1641 link_clock = 108000;
1642 break;
71cd8423 1643 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1644 link_clock = 135000;
1645 break;
71cd8423 1646 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1647 link_clock = 162000;
1648 break;
71cd8423 1649 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1650 link_clock = 216000;
1651 break;
71cd8423 1652 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1653 link_clock = 270000;
1654 break;
1655 default:
1656 WARN(1, "Unsupported link rate\n");
1657 break;
1658 }
1659 link_clock *= 2;
1660 }
1661
1662 pipe_config->port_clock = link_clock;
1663
398a017e 1664 ddi_dotclock_get(pipe_config);
540e732c
S		 1665}
1666
3d51278a 1667static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1668 struct intel_crtc_state *pipe_config)
11578553 1669{
fac5e23e 1670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1671 int link_clock = 0;
1672 u32 val, pll;
1673
c856052a 1674 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1675 switch (val & PORT_CLK_SEL_MASK) {
1676 case PORT_CLK_SEL_LCPLL_810:
1677 link_clock = 81000;
1678 break;
1679 case PORT_CLK_SEL_LCPLL_1350:
1680 link_clock = 135000;
1681 break;
1682 case PORT_CLK_SEL_LCPLL_2700:
1683 link_clock = 270000;
1684 break;
1685 case PORT_CLK_SEL_WRPLL1:
01403de3 1686 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1687 break;
1688 case PORT_CLK_SEL_WRPLL2:
01403de3 1689 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1690 break;
1691 case PORT_CLK_SEL_SPLL:
4a95e36f
VS		 1692 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1693 if (pll == SPLL_FREQ_810MHz)
11578553 1694 link_clock = 81000;
4a95e36f 1695 else if (pll == SPLL_FREQ_1350MHz)
11578553 1696 link_clock = 135000;
4a95e36f 1697 else if (pll == SPLL_FREQ_2700MHz)
11578553
JB		 1698 link_clock = 270000;
1699 else {
1700 WARN(1, "bad spll freq\n");
1701 return;
1702 }
1703 break;
1704 default:
1705 WARN(1, "bad port clock sel\n");
1706 return;
1707 }
1708
1709 pipe_config->port_clock = link_clock * 2;
1710
398a017e 1711 ddi_dotclock_get(pipe_config);
11578553
JB		 1712}
1713
47c9877e 1714static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1715{
9e2c8475 1716 struct dpll clock;
aa610dcb 1717
aa610dcb 1718 clock.m1 = 2;
47c9877e
LDM		 1719 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1720 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1721 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1722 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1723 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1724 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1725
1726 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1727}
1728
1729static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1730 struct intel_crtc_state *pipe_config)
977bb38d 1731{
47c9877e
LDM		 1732 pipe_config->port_clock =
1733 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1734
398a017e 1735 ddi_dotclock_get(pipe_config);
977bb38d
S		 1736}
1737
35686a44
VS		 1738static void intel_ddi_clock_get(struct intel_encoder *encoder,
1739 struct intel_crtc_state *pipe_config)
3d51278a 1740{
0853723b 1741 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1742
2dd24a9c 1743 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1744 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1745 else if (IS_CANNONLAKE(dev_priv))
1746 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1747 else if (IS_GEN9_LP(dev_priv))
1748 bxt_ddi_clock_get(encoder, pipe_config);
1749 else if (IS_GEN9_BC(dev_priv))
1750 skl_ddi_clock_get(encoder, pipe_config);
1751 else if (INTEL_GEN(dev_priv) <= 8)
1752 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1753}
1754
0c06fa15
GM		 1755void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1756 const struct drm_connector_state *conn_state)
dae84799 1757{
2225f3c6 1758 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
e9ce1a62 1759 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1760 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1761 u32 temp;
dae84799 1762
5448f53f
VS		 1763 if (!intel_crtc_has_dp_encoder(crtc_state))
1764 return;
4d1de975 1765
5448f53f
VS		 1766 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1767
3e706dff 1768 temp = DP_MSA_MISC_SYNC_CLOCK;
dc5977da 1769
5448f53f
VS		 1770 switch (crtc_state->pipe_bpp) {
1771 case 18:
3e706dff 1772 temp |= DP_MSA_MISC_6_BPC;
5448f53f
VS		 1773 break;
1774 case 24:
3e706dff 1775 temp |= DP_MSA_MISC_8_BPC;
5448f53f
VS		 1776 break;
1777 case 30:
3e706dff 1778 temp |= DP_MSA_MISC_10_BPC;
5448f53f
VS		 1779 break;
1780 case 36:
3e706dff 1781 temp |= DP_MSA_MISC_12_BPC;
5448f53f
VS		 1782 break;
1783 default:
1784 MISSING_CASE(crtc_state->pipe_bpp);
1785 break;
dae84799 1786 }
5448f53f 1787
cae154fc
VS		 1788 /* nonsense combination */
1789 WARN_ON(crtc_state->limited_color_range &&
1790 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1791
1792 if (crtc_state->limited_color_range)
3e706dff 1793 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
cae154fc 1794
668b6c17
SS		 1795 /*
1796 * As per DP 1.2 spec section 2.3.4.3 while sending
1797 * YCBCR 444 signals we should program MSA MISC1/0 fields with
646d3dc8 1798 * colorspace information.
668b6c17
SS		 1799 */
1800 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3e706dff 1801 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
646d3dc8 1802
ec4401d3
GM		 1803 /*
1804 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1805 * of Color Encoding Format and Content Color Gamut] while sending
0c06fa15
GM		 1806 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1807 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
ec4401d3 1808 */
bd8c9cca 1809 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
3e706dff 1810 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
0c06fa15 1811
5448f53f 1812 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1813}
1814
99389390
JRS		 1815/*
1816 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1817 *
1818 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1819 * intel_ddi_config_transcoder_func().
1820 */
1821static u32
1822intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1823{
2225f3c6 1824 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1524e93e 1825 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1826 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1827 enum pipe pipe = crtc->pipe;
3dc38eea 1828 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1829 enum port port = encoder->port;
3d0c5005 1830 u32 temp;
8d9ddbcb 1831
ad80a810
PZ		 1832 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1833 temp = TRANS_DDI_FUNC_ENABLE;
df16b636
MK		 1834 if (INTEL_GEN(dev_priv) >= 12)
1835 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1836 else
1837 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1838
3dc38eea 1839 switch (crtc_state->pipe_bpp) {
dfcef252 1840 case 18:
ad80a810 1841 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1842 break;
1843 case 24:
ad80a810 1844 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1845 break;
1846 case 30:
ad80a810 1847 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1848 break;
1849 case 36:
ad80a810 1850 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1851 break;
1852 default:
4e53c2e0 1853 BUG();
dfcef252 1854 }
72662e10 1855
1326a92c 1856 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1857 temp |= TRANS_DDI_PVSYNC;
1326a92c 1858 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1859 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1860
e6f0bfc4
PZ		 1861 if (cpu_transcoder == TRANSCODER_EDP) {
1862 switch (pipe) {
1863 case PIPE_A:
c7670b10
PZ		 1864 /* On Haswell, can only use the always-on power well for
1865 * eDP when not using the panel fitter, and when not
1866 * using motion blur mitigation (which we don't
1867 * support). */
dc0c0bfe 1868 if (crtc_state->pch_pfit.force_thru)
d6dd9eb1
DV		 1869 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1870 else
1871 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1872 break;
1873 case PIPE_B:
1874 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1875 break;
1876 case PIPE_C:
1877 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1878 break;
1879 default:
1880 BUG();
1881 break;
1882 }
1883 }
1884
742745f1 1885 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1886 if (crtc_state->has_hdmi_sink)
ad80a810 1887 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1888 else
ad80a810 1889 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1890
1891 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1892 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1893 if (crtc_state->hdmi_high_tmds_clock_ratio)
1894 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1895 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1896 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1897 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1898 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1899 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1900 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
b3545e08
LDM		 1901
1902 if (INTEL_GEN(dev_priv) >= 12)
1903 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
8d9ddbcb 1904 } else {
742745f1
VS		 1905 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1906 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1907 }
1908
99389390
JRS		 1909 return temp;
1910}
1911
1912void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1913{
2225f3c6 1914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
99389390
JRS		 1915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1917 u32 temp;
1918
1919 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
ff15e5a0
JRS		 1920 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1921 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
99389390
JRS		 1922 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1923}
1924
1925/*
1926 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1927 * bit.
1928 */
1929static void
1930intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1931{
2225f3c6 1932 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
99389390
JRS		 1933 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1934 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1935 u32 temp;
1936
1937 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1938 temp &= ~TRANS_DDI_FUNC_ENABLE;
ad80a810 1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1940}
72662e10 1941
90c3e219 1942void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1943{
2225f3c6 1944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
90c3e219
CT		 1945 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1946 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1947 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1948 u32 val = I915_READ(reg);
8d9ddbcb 1949
df16b636
MK		 1950 if (INTEL_GEN(dev_priv) >= 12) {
1951 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1952 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1953 } else {
1954 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1955 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1956 }
8d9ddbcb 1957 I915_WRITE(reg, val);
90c3e219
CT		 1958
1959 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1960 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1961 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1962 /* Quirk time at 100ms for reliable operation */
1963 msleep(100);
1964 }
72662e10
ED		 1965}
1966
2320175f
SP		 1967int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1968 bool enable)
1969{
1970 struct drm_device *dev = intel_encoder->base.dev;
1971 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1972 intel_wakeref_t wakeref;
2320175f
SP		 1973 enum pipe pipe = 0;
1974 int ret = 0;
3d0c5005 1975 u32 tmp;
2320175f 1976
0e6e0be4
CW		 1977 wakeref = intel_display_power_get_if_enabled(dev_priv,
1978 intel_encoder->power_domain);
1979 if (WARN_ON(!wakeref))
2320175f
SP		 1980 return -ENXIO;
1981
1982 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1983 ret = -EIO;
1984 goto out;
1985 }
1986
1987 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1988 if (enable)
1989 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1990 else
1991 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1992 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1993out:
0e6e0be4 1994 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1995 return ret;
1996}
1997
bcbc889b
PZ		 1998bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1999{
2000 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 2001 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 2002 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 2003 int type = intel_connector->base.connector_type;
0fce04c8 2004 enum port port = encoder->port;
bcbc889b 2005 enum transcoder cpu_transcoder;
0e6e0be4
CW		 2006 intel_wakeref_t wakeref;
2007 enum pipe pipe = 0;
3d0c5005 2008 u32 tmp;
e27daab4 2009 bool ret;
bcbc889b 2010
0e6e0be4
CW		 2011 wakeref = intel_display_power_get_if_enabled(dev_priv,
2012 encoder->power_domain);
2013 if (!wakeref)
882244a3
PZ		 2014 return false;
2015
1524e93e 2016 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 2017 ret = false;
2018 goto out;
2019 }
bcbc889b 2020
bc7e3525 2021 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 2022 cpu_transcoder = TRANSCODER_EDP;
2023 else
1a240d4d 2024 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 2025
2026 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2027
2028 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2029 case TRANS_DDI_MODE_SELECT_HDMI:
2030 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 2031 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2032 break;
bcbc889b
PZ		 2033
2034 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 2035 ret = type == DRM_MODE_CONNECTOR_eDP ||
2036 type == DRM_MODE_CONNECTOR_DisplayPort;
2037 break;
2038
0e32b39c
DA		 2039 case TRANS_DDI_MODE_SELECT_DP_MST:
2040 /* if the transcoder is in MST state then
2041 * connector isn't connected */
e27daab4
ID		 2042 ret = false;
2043 break;
bcbc889b
PZ		 2044
2045 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 2046 ret = type == DRM_MODE_CONNECTOR_VGA;
2047 break;
bcbc889b
PZ		 2048
2049 default:
e27daab4
ID		 2050 ret = false;
2051 break;
bcbc889b 2052 }
e27daab4
ID		 2053
2054out:
0e6e0be4 2055 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 2056
2057 return ret;
bcbc889b
PZ		 2058}
2059
9199c322
ID		 2060static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2061 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 2062{
2063 struct drm_device *dev = encoder->base.dev;
fac5e23e 2064 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 2065 enum port port = encoder->port;
0e6e0be4 2066 intel_wakeref_t wakeref;
3657e927 2067 enum pipe p;
85234cdc 2068 u32 tmp;
9199c322
ID		 2069 u8 mst_pipe_mask;
2070
2071 *pipe_mask = 0;
2072 *is_dp_mst = false;
85234cdc 2073
0e6e0be4
CW		 2074 wakeref = intel_display_power_get_if_enabled(dev_priv,
2075 encoder->power_domain);
2076 if (!wakeref)
9199c322 2077 return;
e27daab4 2078
fe43d3f5 2079 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 2080 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 2081 goto out;
85234cdc 2082
bc7e3525 2083 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 2084 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2085
ad80a810 2086 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 2087 default:
2088 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2089 /* fallthrough */
ad80a810
PZ		 2090 case TRANS_DDI_EDP_INPUT_A_ON:
2091 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 2092 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 2093 break;
2094 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 2095 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 2096 break;
2097 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 2098 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 2099 break;
2100 }
2101
e27daab4
ID		 2102 goto out;
2103 }
0e32b39c 2104
9199c322 2105 mst_pipe_mask = 0;
3657e927 2106 for_each_pipe(dev_priv, p) {
9199c322 2107 enum transcoder cpu_transcoder = (enum transcoder)p;
df16b636 2108 unsigned int port_mask, ddi_select;
6aa3bef1
JRS		 2109 intel_wakeref_t trans_wakeref;
2110
2111 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2112 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2113 if (!trans_wakeref)
2114 continue;
df16b636
MK		 2115
2116 if (INTEL_GEN(dev_priv) >= 12) {
2117 port_mask = TGL_TRANS_DDI_PORT_MASK;
2118 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2119 } else {
2120 port_mask = TRANS_DDI_PORT_MASK;
2121 ddi_select = TRANS_DDI_SELECT_PORT(port);
2122 }
3657e927
MK		 2123
2124 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6aa3bef1
JRS		 2125 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2126 trans_wakeref);
e27daab4 2127
df16b636 2128 if ((tmp & port_mask) != ddi_select)
9199c322 2129 continue;
e27daab4 2130
9199c322
ID		 2131 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2132 TRANS_DDI_MODE_SELECT_DP_MST)
2133 mst_pipe_mask |= BIT(p);
e27daab4 2134
9199c322 2135 *pipe_mask |= BIT(p);
85234cdc
DV		 2136 }
2137
9199c322 2138 if (!*pipe_mask)
66a990dd
VS		 2139 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2140 encoder->base.base.id, encoder->base.name);
9199c322
ID		 2141
2142 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
66a990dd
VS		 2143 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2144 encoder->base.base.id, encoder->base.name,
2145 *pipe_mask);
9199c322
ID		 2146 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2147 }
2148
2149 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
66a990dd
VS		 2150 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2151 encoder->base.base.id, encoder->base.name,
2152 *pipe_mask, mst_pipe_mask);
9199c322
ID		 2153 else
2154 *is_dp_mst = mst_pipe_mask;
85234cdc 2155
e27daab4 2156out:
9199c322 2157 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2158 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2159 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2160 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0 2161 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
66a990dd
VS		 2162 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2163 "(PHY_CTL %08x)\n", encoder->base.base.id,
2164 encoder->base.name, tmp);
e93da0a0
ID		 2165 }
2166
0e6e0be4 2167 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2168}
e27daab4 2169
9199c322
ID		 2170bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2171 enum pipe *pipe)
2172{
2173 u8 pipe_mask;
2174 bool is_mst;
2175
2176 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2177
2178 if (is_mst || !pipe_mask)
2179 return false;
2180
2181 *pipe = ffs(pipe_mask) - 1;
2182
2183 return true;
85234cdc
DV		 2184}
2185
52528055 2186static inline enum intel_display_power_domain
bdaa29b6 2187intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2188{
9e3b5ce9 2189 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2190 * DC states enabled at the same time, while for driver initiated AUX
2191 * transfers we need the same AUX IOs to be powered but with DC states
2192 * disabled. Accordingly use the AUX power domain here which leaves DC
2193 * states enabled.
2194 * However, for non-A AUX ports the corresponding non-EDP transcoders
2195 * would have already enabled power well 2 and DC_OFF. This means we can
2196 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2197 * specific AUX_IO reference without powering up any extra wells.
2198 * Note that PSR is enabled only on Port A even though this function
2199 * returns the correct domain for other ports too.
2200 */
563d22a0 2201 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2202 intel_aux_power_domain(dig_port);
52528055
ID		 2203}
2204
3a52fb7e
ID		 2205static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2206 struct intel_crtc_state *crtc_state)
62b69566 2207{
8e4a3ad9 2208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2209 struct intel_digital_port *dig_port;
d8fe2ab6 2210 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
62b69566 2211
52528055
ID		 2212 /*
2213 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2214 * happen since fake-MST encoders don't set their get_power_domains()
2215 * hook.
52528055
ID		 2216 */
2217 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2218 return;
b79ebe74
ID		 2219
2220 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2221 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2222
8e4a3ad9
ID		 2223 /*
2224 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2225 * ports.
2226 */
2227 if (intel_crtc_has_dp_encoder(crtc_state) ||
d8fe2ab6 2228 intel_phy_is_tc(dev_priv, phy))
3a52fb7e
ID		 2229 intel_display_power_get(dev_priv,
2230 intel_ddi_main_link_aux_domain(dig_port));
52528055 2231
a24c62f9
MN		 2232 /*
2233 * VDSC power is needed when DSC is enabled
2234 */
010663a6 2235 if (crtc_state->dsc.compression_enable)
3a52fb7e
ID		 2236 intel_display_power_get(dev_priv,
2237 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2238}
2239
3dc38eea 2240void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2241{
2225f3c6 2242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
e9ce1a62 2243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2244 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2245 enum port port = encoder->port;
3dc38eea 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2247
df16b636
MK		 2248 if (cpu_transcoder != TRANSCODER_EDP) {
2249 if (INTEL_GEN(dev_priv) >= 12)
2250 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2251 TGL_TRANS_CLK_SEL_PORT(port));
2252 else
2253 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2254 TRANS_CLK_SEL_PORT(port));
2255 }
fc914639
PZ		 2256}
2257
3dc38eea 2258void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2259{
2225f3c6 2260 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3dc38eea 2261 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2262
df16b636
MK		 2263 if (cpu_transcoder != TRANSCODER_EDP) {
2264 if (INTEL_GEN(dev_priv) >= 12)
2265 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2266 TGL_TRANS_CLK_SEL_DISABLED);
2267 else
2268 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2269 TRANS_CLK_SEL_DISABLED);
2270 }
fc914639
PZ		 2271}
2272
a7d8dbc0 2273static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2274 enum port port, u8 iboost)
f8896f5d 2275{
a7d8dbc0
VS		 2276 u32 tmp;
2277
2278 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2279 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2280 if (iboost)
2281 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2282 else
2283 tmp |= BALANCE_LEG_DISABLE(port);
2284 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2285}
2286
081dfcfa
VS		 2287static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2288 int level, enum intel_output_type type)
a7d8dbc0
VS		 2289{
2290 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2292 enum port port = encoder->port;
3d0c5005 2293 u8 iboost;
f8896f5d 2294
081dfcfa
VS		 2295 if (type == INTEL_OUTPUT_HDMI)
2296 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2297 else
2298 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2299
081dfcfa
VS		 2300 if (iboost == 0) {
2301 const struct ddi_buf_trans *ddi_translations;
2302 int n_entries;
2303
2304 if (type == INTEL_OUTPUT_HDMI)
2305 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2306 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2307 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2308 else
edba48fd 2309 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2310
21b39d2a
VS		 2311 if (WARN_ON_ONCE(!ddi_translations))
2312 return;
2313 if (WARN_ON_ONCE(level >= n_entries))
2314 level = n_entries - 1;
2315
081dfcfa 2316 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2317 }
2318
2319 /* Make sure that the requested I_boost is valid */
2320 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2321 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2322 return;
2323 }
2324
a7d8dbc0 2325 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2326
a7d8dbc0
VS		 2327 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2328 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2329}
2330
7d4f37b5
VS		 2331static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2332 int level, enum intel_output_type type)
96fb9f9b 2333{
7d4f37b5 2334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2335 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2336 enum port port = encoder->port;
043eaf36 2337 int n_entries;
7d4f37b5
VS		 2338
2339 if (type == INTEL_OUTPUT_HDMI)
2340 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2341 else if (type == INTEL_OUTPUT_EDP)
2342 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2343 else
2344 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2345
21b39d2a
VS		 2346 if (WARN_ON_ONCE(!ddi_translations))
2347 return;
2348 if (WARN_ON_ONCE(level >= n_entries))
2349 level = n_entries - 1;
2350
b6e08203
ACO		 2351 bxt_ddi_phy_set_signal_level(dev_priv, port,
2352 ddi_translations[level].margin,
2353 ddi_translations[level].scale,
2354 ddi_translations[level].enable,
2355 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2356}
2357
ffe5111e
VS		 2358u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2359{
2360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2362 enum port port = encoder->port;
d8fe2ab6 2363 enum phy phy = intel_port_to_phy(dev_priv, port);
ffe5111e
VS		 2364 int n_entries;
2365
978c3e53
CT		 2366 if (INTEL_GEN(dev_priv) >= 12) {
2367 if (intel_phy_is_combo(dev_priv, phy))
2368 icl_get_combo_buf_trans(dev_priv, encoder->type,
2369 intel_dp->link_rate, &n_entries);
2370 else
362bfb99 2371 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
978c3e53 2372 } else if (INTEL_GEN(dev_priv) == 11) {
d8fe2ab6 2373 if (intel_phy_is_combo(dev_priv, phy))
4a8134d5 2374 icl_get_combo_buf_trans(dev_priv, encoder->type,
b265a2a6 2375 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2376 else
2377 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2378 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2379 if (encoder->type == INTEL_OUTPUT_EDP)
2380 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2381 else
2382 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2383 } else if (IS_GEN9_LP(dev_priv)) {
2384 if (encoder->type == INTEL_OUTPUT_EDP)
2385 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2386 else
2387 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2388 } else {
2389 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2390 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2391 else
edba48fd 2392 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2393 }
ffe5111e
VS		 2394
2395 if (WARN_ON(n_entries < 1))
2396 n_entries = 1;
2397 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2398 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2399
2400 return index_to_dp_signal_levels[n_entries - 1] &
2401 DP_TRAIN_VOLTAGE_SWING_MASK;
2402}
2403
4718a365
VS		 2404/*
2405 * We assume that the full set of pre-emphasis values can be
2406 * used on all DDI platforms. Should that change we need to
2407 * rethink this code.
2408 */
2409u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2410{
2411 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2413 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2415 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2417 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2419 default:
2420 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2421 }
2422}
2423
f3cf4ba4
VS		 2424static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2425 int level, enum intel_output_type type)
cf54ca8b 2426{
f3cf4ba4 2427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2428 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2429 enum port port = encoder->port;
f3cf4ba4
VS		 2430 int n_entries, ln;
2431 u32 val;
cf54ca8b 2432
f3cf4ba4 2433 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2434 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2435 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2436 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2437 else
2438 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2439
21b39d2a 2440 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2441 return;
21b39d2a 2442 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2443 level = n_entries - 1;
cf54ca8b
RV		 2444
2445 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2446 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2447 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2448 val |= SCALING_MODE_SEL(2);
2449 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2450
2451 /* Program PORT_TX_DW2 */
2452 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2453 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2454 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2455 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2456 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2457 /* Rcomp scalar is fixed as 0x98 for every table entry */
2458 val |= RCOMP_SCALAR(0x98);
2459 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2460
20303eb4 2461 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2462 /* We cannot write to GRP. It would overrite individual loadgen */
2463 for (ln = 0; ln < 4; ln++) {
9194e42a 2464 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2465 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2466 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2467 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2468 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2469 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2470 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2471 }
2472
20303eb4 2473 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2474 /* All DW5 values are fixed for every table entry */
2475 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2476 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2477 val |= RTERM_SELECT(6);
2478 val |= TAP3_DISABLE;
2479 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2480
20303eb4 2481 /* Program PORT_TX_DW7 */
cf54ca8b 2482 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2483 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2484 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2485 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2486}
2487
f3cf4ba4
VS		 2488static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2489 int level, enum intel_output_type type)
cf54ca8b 2490{
0091abc3 2491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2492 enum port port = encoder->port;
f3cf4ba4 2493 int width, rate, ln;
cf54ca8b 2494 u32 val;
0091abc3 2495
f3cf4ba4 2496 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2497 width = 4;
f3cf4ba4 2498 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2499 } else {
f3cf4ba4
VS		 2500 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2501
2502 width = intel_dp->lane_count;
2503 rate = intel_dp->link_rate;
0091abc3 2504 }
cf54ca8b
RV		 2505
2506 /*
2507 * 1. If port type is eDP or DP,
2508 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2509 * else clear to 0b.
2510 */
2511 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2512 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2513 val |= COMMON_KEEPER_EN;
2514 else
2515 val &= ~COMMON_KEEPER_EN;
2516 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2517
2518 /* 2. Program loadgen select */
2519 /*
0091abc3
CT		 2520 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2521 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2522 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2523 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2524 */
0091abc3 2525 for (ln = 0; ln <= 3; ln++) {
9194e42a 2526 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2527 val &= ~LOADGEN_SELECT;
2528
a8e45a1c
NM		 2529 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2530 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2531 val |= LOADGEN_SELECT;
2532 }
9194e42a 2533 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2534 }
cf54ca8b
RV		 2535
2536 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2537 val = I915_READ(CNL_PORT_CL1CM_DW5);
2538 val |= SUS_CLOCK_CONFIG;
2539 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2540
2541 /* 4. Clear training enable to change swing values */
2542 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2543 val &= ~TX_TRAINING_EN;
2544 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2545
2546 /* 5. Program swing and de-emphasis */
f3cf4ba4 2547 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2548
2549 /* 6. Set training enable to trigger update */
2550 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2551 val |= TX_TRAINING_EN;
2552 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2553}
2554
fb5c8e9d 2555static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
dc867bc7 2556 u32 level, enum phy phy, int type,
b265a2a6 2557 int rate)
fb5c8e9d 2558{
b265a2a6 2559 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2560 u32 n_entries, val;
2561 int ln;
2562
4a8134d5
MR		 2563 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2564 &n_entries);
fb5c8e9d
MN		 2565 if (!ddi_translations)
2566 return;
2567
2568 if (level >= n_entries) {
2569 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2570 level = n_entries - 1;
2571 }
2572
b265a2a6 2573 /* Set PORT_TX_DW5 */
dc867bc7 2574 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
b265a2a6
CT		 2575 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2576 TAP2_DISABLE | TAP3_DISABLE);
2577 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2578 val |= RTERM_SELECT(0x6);
b265a2a6 2579 val |= TAP3_DISABLE;
dc867bc7 2580 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2581
2582 /* Program PORT_TX_DW2 */
dc867bc7 2583 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
fb5c8e9d
MN		 2584 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2585 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2586 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2587 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2588 /* Program Rcomp scalar for every table entry */
b265a2a6 2589 val |= RCOMP_SCALAR(0x98);
dc867bc7 2590 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
fb5c8e9d
MN		 2591
2592 /* Program PORT_TX_DW4 */
2593 /* We cannot write to GRP. It would overwrite individual loadgen. */
2594 for (ln = 0; ln <= 3; ln++) {
dc867bc7 2595 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
fb5c8e9d
MN		 2596 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2597 CURSOR_COEFF_MASK);
b265a2a6
CT		 2598 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2599 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2600 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
dc867bc7 2601 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
fb5c8e9d 2602 }
b265a2a6
CT		 2603
2604 /* Program PORT_TX_DW7 */
dc867bc7 2605 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
b265a2a6
CT		 2606 val &= ~N_SCALAR_MASK;
2607 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
dc867bc7 2608 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
fb5c8e9d
MN		 2609}
2610
2611static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2612 u32 level,
2613 enum intel_output_type type)
2614{
2615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
dc867bc7 2616 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
fb5c8e9d
MN		 2617 int width = 0;
2618 int rate = 0;
2619 u32 val;
2620 int ln = 0;
2621
2622 if (type == INTEL_OUTPUT_HDMI) {
2623 width = 4;
2624 /* Rate is always < than 6GHz for HDMI */
2625 } else {
2626 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2627
2628 width = intel_dp->lane_count;
2629 rate = intel_dp->link_rate;
2630 }
2631
2632 /*
2633 * 1. If port type is eDP or DP,
2634 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2635 * else clear to 0b.
2636 */
dc867bc7 2637 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
fb5c8e9d
MN		 2638 if (type == INTEL_OUTPUT_HDMI)
2639 val &= ~COMMON_KEEPER_EN;
2640 else
2641 val |= COMMON_KEEPER_EN;
dc867bc7 2642 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
fb5c8e9d
MN		 2643
2644 /* 2. Program loadgen select */
2645 /*
2646 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2647 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2648 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2649 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2650 */
2651 for (ln = 0; ln <= 3; ln++) {
dc867bc7 2652 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
fb5c8e9d
MN		 2653 val &= ~LOADGEN_SELECT;
2654
2655 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2656 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2657 val |= LOADGEN_SELECT;
2658 }
dc867bc7 2659 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
fb5c8e9d
MN		 2660 }
2661
2662 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
dc867bc7 2663 val = I915_READ(ICL_PORT_CL_DW5(phy));
fb5c8e9d 2664 val |= SUS_CLOCK_CONFIG;
dc867bc7 2665 I915_WRITE(ICL_PORT_CL_DW5(phy), val);
fb5c8e9d
MN		 2666
2667 /* 4. Clear training enable to change swing values */
dc867bc7 2668 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
fb5c8e9d 2669 val &= ~TX_TRAINING_EN;
dc867bc7 2670 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2671
2672 /* 5. Program swing and de-emphasis */
dc867bc7 2673 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
fb5c8e9d
MN		 2674
2675 /* 6. Set training enable to trigger update */
dc867bc7 2676 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
fb5c8e9d 2677 val |= TX_TRAINING_EN;
dc867bc7 2678 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2679}
2680
07685c82
MN		 2681static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2682 int link_clock,
2683 u32 level)
2684{
2685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f21e8b80 2686 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
07685c82
MN		 2687 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2688 u32 n_entries, val;
2689 int ln;
2690
2691 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2692 ddi_translations = icl_mg_phy_ddi_translations;
2693 /* The table does not have values for level 3 and level 9. */
2694 if (level >= n_entries || level == 3 || level == 9) {
2695 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2696 level, n_entries - 2);
2697 level = n_entries - 2;
2698 }
2699
2700 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2701 for (ln = 0; ln < 2; ln++) {
f21e8b80 2702 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
07685c82 2703 val &= ~CRI_USE_FS32;
f21e8b80 2704 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
07685c82 2705
f21e8b80 2706 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
07685c82 2707 val &= ~CRI_USE_FS32;
f21e8b80 2708 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
07685c82
MN		 2709 }
2710
2711 /* Program MG_TX_SWINGCTRL with values from vswing table */
2712 for (ln = 0; ln < 2; ln++) {
f21e8b80 2713 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
07685c82
MN		 2714 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2715 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2716 ddi_translations[level].cri_txdeemph_override_17_12);
f21e8b80 2717 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
07685c82 2718
f21e8b80 2719 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
07685c82
MN		 2720 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2721 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2722 ddi_translations[level].cri_txdeemph_override_17_12);
f21e8b80 2723 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
07685c82
MN		 2724 }
2725
2726 /* Program MG_TX_DRVCTRL with values from vswing table */
2727 for (ln = 0; ln < 2; ln++) {
f21e8b80 2728 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
07685c82
MN		 2729 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2730 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2731 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2732 ddi_translations[level].cri_txdeemph_override_5_0) |
2733 CRI_TXDEEMPH_OVERRIDE_11_6(
2734 ddi_translations[level].cri_txdeemph_override_11_6) |
2735 CRI_TXDEEMPH_OVERRIDE_EN;
f21e8b80 2736 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
07685c82 2737
f21e8b80 2738 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
07685c82
MN		 2739 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2740 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2741 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2742 ddi_translations[level].cri_txdeemph_override_5_0) |
2743 CRI_TXDEEMPH_OVERRIDE_11_6(
2744 ddi_translations[level].cri_txdeemph_override_11_6) |
2745 CRI_TXDEEMPH_OVERRIDE_EN;
f21e8b80 2746 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
07685c82
MN		 2747
2748 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2749 }
2750
2751 /*
2752 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2753 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2754 * values from table for which TX1 and TX2 enabled.
2755 */
2756 for (ln = 0; ln < 2; ln++) {
f21e8b80 2757 val = I915_READ(MG_CLKHUB(ln, tc_port));
07685c82
MN		 2758 if (link_clock < 300000)
2759 val |= CFG_LOW_RATE_LKREN_EN;
2760 else
2761 val &= ~CFG_LOW_RATE_LKREN_EN;
f21e8b80 2762 I915_WRITE(MG_CLKHUB(ln, tc_port), val);
07685c82
MN		 2763 }
2764
2765 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2766 for (ln = 0; ln < 2; ln++) {
f21e8b80 2767 val = I915_READ(MG_TX1_DCC(ln, tc_port));
07685c82
MN		 2768 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2769 if (link_clock <= 500000) {
2770 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2771 } else {
2772 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2773 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2774 }
f21e8b80 2775 I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
07685c82 2776
f21e8b80 2777 val = I915_READ(MG_TX2_DCC(ln, tc_port));
07685c82
MN		 2778 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2779 if (link_clock <= 500000) {
2780 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2781 } else {
2782 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2783 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2784 }
f21e8b80 2785 I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
07685c82
MN		 2786 }
2787
2788 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2789 for (ln = 0; ln < 2; ln++) {
f21e8b80 2790 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
07685c82 2791 val |= CRI_CALCINIT;
f21e8b80 2792 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
07685c82 2793
f21e8b80 2794 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
07685c82 2795 val |= CRI_CALCINIT;
f21e8b80 2796 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
07685c82
MN		 2797 }
2798}
2799
2800static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2801 int link_clock,
2802 u32 level,
fb5c8e9d
MN		 2803 enum intel_output_type type)
2804{
176597a1 2805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
d8fe2ab6 2806 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
fb5c8e9d 2807
d8fe2ab6 2808 if (intel_phy_is_combo(dev_priv, phy))
fb5c8e9d
MN		 2809 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2810 else
07685c82 2811 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2812}
2813
978c3e53
CT		 2814static void
2815tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2816 u32 level)
2817{
2818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2819 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2820 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2821 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2822
362bfb99
MR		 2823 if (encoder->type == INTEL_OUTPUT_HDMI) {
2824 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2825 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2826 } else {
2827 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2828 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2829 }
978c3e53
CT		 2830
2831 if (level >= n_entries)
2832 level = n_entries - 1;
2833
2834 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2835 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2836 DKL_TX_VSWING_CONTROL_MASK);
2837 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2838 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2839 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2840
2841 for (ln = 0; ln < 2; ln++) {
2842 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
2843
2d69c42e
JRS		 2844 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
2845
978c3e53
CT		 2846 /* All the registers are RMW */
2847 val = I915_READ(DKL_TX_DPCNTL0(tc_port));
2848 val &= ~dpcnt_mask;
2849 val |= dpcnt_val;
2850 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
2851
2852 val = I915_READ(DKL_TX_DPCNTL1(tc_port));
2853 val &= ~dpcnt_mask;
2854 val |= dpcnt_val;
2855 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
2856
2857 val = I915_READ(DKL_TX_DPCNTL2(tc_port));
2858 val &= ~DKL_TX_DP20BITMODE;
2859 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
2860 }
2861}
2862
2863static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2864 int link_clock,
2865 u32 level,
2866 enum intel_output_type type)
2867{
2868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2869 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2870
2871 if (intel_phy_is_combo(dev_priv, phy))
2872 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2873 else
2874 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2875}
2876
3d0c5005 2877static u32 translate_signal_level(int signal_levels)
f8896f5d 2878{
97eeb872 2879 int i;
f8896f5d 2880
97eeb872
VS		 2881 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2882 if (index_to_dp_signal_levels[i] == signal_levels)
2883 return i;
f8896f5d
DW		 2884 }
2885
97eeb872
VS		 2886 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2887 signal_levels);
2888
2889 return 0;
f8896f5d
DW		 2890}
2891
3d0c5005 2892static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2893{
3d0c5005 2894 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2895 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2896 DP_TRAIN_PRE_EMPHASIS_MASK);
2897
2898 return translate_signal_level(signal_levels);
2899}
2900
d509af6c 2901u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2902{
2903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2904 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2905 struct intel_encoder *encoder = &dport->base;
d02ace87 2906 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2907
978c3e53
CT		 2908 if (INTEL_GEN(dev_priv) >= 12)
2909 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2910 level, encoder->type);
2911 else if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2912 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2913 level, encoder->type);
fb5c8e9d 2914 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2915 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2916 else
7d4f37b5 2917 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2918
2919 return 0;
2920}
2921
3d0c5005 2922u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2923{
2924 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2925 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2926 struct intel_encoder *encoder = &dport->base;
d02ace87 2927 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2928
b976dc53 2929 if (IS_GEN9_BC(dev_priv))
081dfcfa 2930 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2931
f8896f5d
DW		 2932 return DDI_BUF_TRANS_SELECT(level);
2933}
2934
bb1c7edc 2935static inline
3d0c5005 2936u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
befa372b 2937 enum phy phy)
bb1c7edc 2938{
befa372b
MR		 2939 if (intel_phy_is_combo(dev_priv, phy)) {
2940 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2941 } else if (intel_phy_is_tc(dev_priv, phy)) {
2942 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2943 (enum port)phy);
bb1c7edc
MK		 2944
2945 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2946 }
2947
2948 return 0;
2949}
2950
3b8c0d5b
JN		 2951static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2952 const struct intel_crtc_state *crtc_state)
c27e917e 2953{
3b8c0d5b 2954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2955 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
befa372b 2956 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3b8c0d5b 2957 u32 val;
c27e917e 2958
3b8c0d5b 2959 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2960
befa372b
MR		 2961 val = I915_READ(ICL_DPCLKA_CFGCR0);
2962 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
c27e917e 2963
befa372b
MR		 2964 if (intel_phy_is_combo(dev_priv, phy)) {
2965 /*
2966 * Even though this register references DDIs, note that we
2967 * want to pass the PHY rather than the port (DDI). For
2968 * ICL, port=phy in all cases so it doesn't matter, but for
2969 * EHL the bspec notes the following:
2970 *
2971 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2972 * Clock Select chooses the PLL for both DDIA and DDID and
2973 * drives port A in all cases."
2974 */
2975 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2976 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2977 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2978 POSTING_READ(ICL_DPCLKA_CFGCR0);
c27e917e 2979 }
3b8c0d5b 2980
befa372b
MR		 2981 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2982 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3b8c0d5b
JN		 2983
2984 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2985}
2986
3b8c0d5b 2987static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2988{
3b8c0d5b 2989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
befa372b 2990 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3b8c0d5b 2991 u32 val;
c27e917e 2992
3b8c0d5b 2993 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2994
befa372b
MR		 2995 val = I915_READ(ICL_DPCLKA_CFGCR0);
2996 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2997 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
c27e917e 2998
3b8c0d5b 2999 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 3000}
3001
70332ac5
ID		 3002void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3003{
3004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 3005 u32 val;
1dd07e56
ID		 3006 enum port port;
3007 u32 port_mask;
3008 bool ddi_clk_needed;
30f5ccfa
ID		 3009
3010 /*
3011 * In case of DP MST, we sanitize the primary encoder only, not the
3012 * virtual ones.
3013 */
3014 if (encoder->type == INTEL_OUTPUT_DP_MST)
3015 return;
3016
30f5ccfa
ID		 3017 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3018 u8 pipe_mask;
3019 bool is_mst;
3020
3021 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3022 /*
3023 * In the unlikely case that BIOS enables DP in MST mode, just
3024 * warn since our MST HW readout is incomplete.
3025 */
3026 if (WARN_ON(is_mst))
3027 return;
3028 }
70332ac5 3029
1dd07e56
ID		 3030 port_mask = BIT(encoder->port);
3031 ddi_clk_needed = encoder->base.crtc;
70332ac5 3032
1dd07e56
ID		 3033 if (encoder->type == INTEL_OUTPUT_DSI) {
3034 struct intel_encoder *other_encoder;
70332ac5 3035
1dd07e56
ID		 3036 port_mask = intel_dsi_encoder_ports(encoder);
3037 /*
3038 * Sanity check that we haven't incorrectly registered another
3039 * encoder using any of the ports of this DSI encoder.
3040 */
3041 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3042 if (other_encoder == encoder)
3043 continue;
3044
3045 if (WARN_ON(port_mask & BIT(other_encoder->port)))
3046 return;
3047 }
3048 /*
942d1cf4
VK		 3049 * For DSI we keep the ddi clocks gated
3050 * except during enable/disable sequence.
1dd07e56 3051 */
942d1cf4 3052 ddi_clk_needed = false;
1dd07e56
ID		 3053 }
3054
befa372b 3055 val = I915_READ(ICL_DPCLKA_CFGCR0);
1dd07e56 3056 for_each_port_masked(port, port_mask) {
befa372b
MR		 3057 enum phy phy = intel_port_to_phy(dev_priv, port);
3058
1dd07e56
ID		 3059 bool ddi_clk_ungated = !(val &
3060 icl_dpclka_cfgcr0_clk_off(dev_priv,
befa372b 3061 phy));
1dd07e56
ID		 3062
3063 if (ddi_clk_needed == ddi_clk_ungated)
3064 continue;
3065
3066 /*
3067 * Punt on the case now where clock is gated, but it would
3068 * be needed by the port. Something else is really broken then.
3069 */
3070 if (WARN_ON(ddi_clk_needed))
3071 continue;
3072
befa372b
MR		 3073 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3074 phy_name(port));
3075 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3076 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
1dd07e56 3077 }
70332ac5
ID		 3078}
3079
d7c530b2 3080static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 3081 const struct intel_crtc_state *crtc_state)
6441ab5f 3082{
e404ba8d 3083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3084 enum port port = encoder->port;
d8fe2ab6 3085 enum phy phy = intel_port_to_phy(dev_priv, port);
3d0c5005 3086 u32 val;
0e5fa646 3087 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 3088
c856052a
ACO		 3089 if (WARN_ON(!pll))
3090 return;
3091
04bf68bb 3092 mutex_lock(&dev_priv->dpll_lock);
8edcda12 3093
2dd24a9c 3094 if (INTEL_GEN(dev_priv) >= 11) {
d8fe2ab6 3095 if (!intel_phy_is_combo(dev_priv, phy))
c27e917e 3096 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 3097 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c2052d6e
JRS		 3098 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3099 /*
3100 * MG does not exist but the programming is required
3101 * to ungate DDIC and DDID
3102 */
3103 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
c27e917e 3104 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 3105 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3106 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 3107 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 3108 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 3109 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 3110
555e38d2
RV		 3111 /*
3112 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3113 * This step and the step before must be done with separate
3114 * register writes.
3115 */
3116 val = I915_READ(DPCLKA_CFGCR0);
87145d95 3117 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 3118 I915_WRITE(DPCLKA_CFGCR0, val);
3119 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 3120 /* DDI -> PLL mapping */
efa80add
S		 3121 val = I915_READ(DPLL_CTRL2);
3122
3123 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 3124 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 3125 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 3126 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3127
3128 I915_WRITE(DPLL_CTRL2, val);
5416d871 3129
c56b89f1 3130 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 3131 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 3132 }
8edcda12
RV		 3133
3134 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 3135}
3136
6b8506d5
VS		 3137static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3138{
3139 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3140 enum port port = encoder->port;
d8fe2ab6 3141 enum phy phy = intel_port_to_phy(dev_priv, port);
6b8506d5 3142
2dd24a9c 3143 if (INTEL_GEN(dev_priv) >= 11) {
c2052d6e
JRS		 3144 if (!intel_phy_is_combo(dev_priv, phy) ||
3145 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
c27e917e
PZ		 3146 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3147 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 3148 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3149 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 3150 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 3151 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3152 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 3153 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 3154 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 3155 }
6b8506d5
VS		 3156}
3157
8aaf5cbd
JRS		 3158static void
3159icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
cb9ff519
ID		 3160{
3161 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
f21e8b80 3162 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
8aaf5cbd 3163 u32 val, bits;
9c11b121 3164 int ln;
cb9ff519
ID		 3165
3166 if (tc_port == PORT_TC_NONE)
3167 return;
3168
8aaf5cbd
JRS		 3169 bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3170 MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3171 MG_DP_MODE_CFG_GAONPWR_GATING;
cb9ff519 3172
9c11b121 3173 for (ln = 0; ln < 2; ln++) {
978c3e53
CT		 3174 if (INTEL_GEN(dev_priv) >= 12) {
3175 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
3176 val = I915_READ(DKL_DP_MODE(tc_port));
3177 } else {
f21e8b80 3178 val = I915_READ(MG_DP_MODE(ln, tc_port));
978c3e53
CT		 3179 }
3180
8aaf5cbd
JRS		 3181 if (enable)
3182 val |= bits;
3183 else
3184 val &= ~bits;
978c3e53
CT		 3185
3186 if (INTEL_GEN(dev_priv) >= 12)
3187 I915_WRITE(DKL_DP_MODE(tc_port), val);
3188 else
f21e8b80 3189 I915_WRITE(MG_DP_MODE(ln, tc_port), val);
cb9ff519
ID		 3190 }
3191
978c3e53
CT		 3192 if (INTEL_GEN(dev_priv) == 11) {
3193 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
3194 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3195 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3196 MG_MISC_SUS0_CFG_TRPWR_GATING |
3197 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3198 MG_MISC_SUS0_CFG_DGPWR_GATING;
8aaf5cbd 3199
978c3e53
CT		 3200 val = I915_READ(MG_MISC_SUS0(tc_port));
3201 if (enable)
3202 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3203 else
3204 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3205 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3206 }
cb9ff519
ID		 3207}
3208
3b51be4e
CT		 3209static void
3210icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3211 const struct intel_crtc_state *crtc_state)
93b662d3
ID		 3212{
3213 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
f21e8b80 3214 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
3b51be4e
CT		 3215 u32 ln0, ln1, pin_assignment;
3216 u8 width;
93b662d3 3217
e9b7e142 3218 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
93b662d3
ID		 3219 return;
3220
978c3e53
CT		 3221 if (INTEL_GEN(dev_priv) >= 12) {
3222 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3223 ln0 = I915_READ(DKL_DP_MODE(tc_port));
3224 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3225 ln1 = I915_READ(DKL_DP_MODE(tc_port));
3226 } else {
f21e8b80
JRS		 3227 ln0 = I915_READ(MG_DP_MODE(0, tc_port));
3228 ln1 = I915_READ(MG_DP_MODE(1, tc_port));
978c3e53 3229 }
93b662d3 3230
3b51be4e
CT		 3231 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3232 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
93b662d3 3233
3b51be4e
CT		 3234 /* DPPATC */
3235 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3236 width = crtc_state->lane_count;
93b662d3 3237
3b51be4e
CT		 3238 switch (pin_assignment) {
3239 case 0x0:
3240 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3241 if (width == 1) {
3242 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3243 } else {
3244 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3245 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3246 }
3247 break;
3248 case 0x1:
3249 if (width == 4) {
3250 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3251 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3252 }
3253 break;
3254 case 0x2:
3255 if (width == 2) {
3256 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3257 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3258 }
3259 break;
3260 case 0x3:
3261 case 0x5:
3262 if (width == 1) {
93b662d3 3263 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
93b662d3 3264 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3b51be4e
CT		 3265 } else {
3266 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3267 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
93b662d3
ID		 3268 }
3269 break;
3b51be4e
CT		 3270 case 0x4:
3271 case 0x6:
3272 if (width == 1) {
3273 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3274 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3275 } else {
3276 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3277 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3278 }
93b662d3 3279 break;
93b662d3 3280 default:
3b51be4e 3281 MISSING_CASE(pin_assignment);
93b662d3
ID		 3282 }
3283
978c3e53
CT		 3284 if (INTEL_GEN(dev_priv) >= 12) {
3285 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3286 I915_WRITE(DKL_DP_MODE(tc_port), ln0);
3287 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3288 I915_WRITE(DKL_DP_MODE(tc_port), ln1);
3289 } else {
f21e8b80
JRS		 3290 I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
3291 I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
978c3e53 3292 }
93b662d3
ID		 3293}
3294
a322b975
AS		 3295static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3296 const struct intel_crtc_state *crtc_state)
3297{
3298 if (!crtc_state->fec_enable)
3299 return;
3300
3301 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3302 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3303}
3304
5c44b938
AS		 3305static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3306 const struct intel_crtc_state *crtc_state)
3307{
3308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4444df6e 3309 struct intel_dp *intel_dp;
5c44b938
AS		 3310 u32 val;
3311
3312 if (!crtc_state->fec_enable)
3313 return;
3314
4444df6e
LDM		 3315 intel_dp = enc_to_intel_dp(&encoder->base);
3316 val = I915_READ(intel_dp->regs.dp_tp_ctl);
5c44b938 3317 val |= DP_TP_CTL_FEC_ENABLE;
4444df6e 3318 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
5c44b938 3319
4444df6e 3320 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4cb3b44d 3321 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
5c44b938
AS		 3322 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3323}
3324
d6a09cee
AS		 3325static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3326 const struct intel_crtc_state *crtc_state)
3327{
3328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4444df6e 3329 struct intel_dp *intel_dp;
d6a09cee
AS		 3330 u32 val;
3331
3332 if (!crtc_state->fec_enable)
3333 return;
3334
4444df6e
LDM		 3335 intel_dp = enc_to_intel_dp(&encoder->base);
3336 val = I915_READ(intel_dp->regs.dp_tp_ctl);
d6a09cee 3337 val &= ~DP_TP_CTL_FEC_ENABLE;
4444df6e
LDM		 3338 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3339 POSTING_READ(intel_dp->regs.dp_tp_ctl);
d6a09cee
AS		 3340}
3341
bdacf087
AG		 3342static void
3343tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3344{
2225f3c6 3345 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
bdacf087
AG		 3346 u32 val;
3347
3348 if (!cstate->dc3co_exitline)
3349 return;
3350
3351 val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3352 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3353 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3354}
3355
3356static void
3357tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3358{
3359 u32 val, exit_scanlines;
2225f3c6 3360 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
bdacf087
AG		 3361
3362 if (!cstate->dc3co_exitline)
3363 return;
3364
3365 exit_scanlines = cstate->dc3co_exitline;
3366 exit_scanlines <<= EXITLINE_SHIFT;
3367 val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3368 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3369 val |= exit_scanlines;
3370 val |= EXITLINE_ENABLE;
3371 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3372}
3373
3374static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
3375 struct intel_crtc_state *cstate)
3376{
3377 u32 exit_scanlines;
2225f3c6 3378 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
1326a92c 3379 u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
bdacf087
AG		 3380
3381 cstate->dc3co_exitline = 0;
3382
3383 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
3384 return;
3385
3386 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
2225f3c6 3387 if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
bdacf087
AG		 3388 encoder->port != PORT_A)
3389 return;
3390
1326a92c 3391 if (!cstate->has_psr2 || !cstate->hw.active)
bdacf087
AG		 3392 return;
3393
3394 /*
3395 * DC3CO Exit time 200us B.Spec 49196
3396 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
3397 */
3398 exit_scanlines =
1326a92c 3399 intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
bdacf087
AG		 3400
3401 if (WARN_ON(exit_scanlines > crtc_vdisplay))
3402 return;
3403
3404 cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
3405 DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
3406}
3407
3408static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
3409{
3410 u32 val;
2225f3c6 3411 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
bdacf087
AG		 3412
3413 if (INTEL_GEN(dev_priv) < 12)
3414 return;
3415
3416 val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
3417
3418 if (val & EXITLINE_ENABLE)
3419 crtc_state->dc3co_exitline = val & EXITLINE_MASK;
3420}
3421
99389390
JRS		 3422static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3423 const struct intel_crtc_state *crtc_state,
3424 const struct drm_connector_state *conn_state)
3425{
3426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3428 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3429 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3430 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3431 int level = intel_ddi_dp_level(intel_dp);
4444df6e 3432 enum transcoder transcoder = crtc_state->cpu_transcoder;
99389390 3433
bdacf087 3434 tgl_set_psr2_transcoder_exitline(crtc_state);
99389390
JRS		 3435 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3436 crtc_state->lane_count, is_mst);
3437
4444df6e
LDM		 3438 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3439 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3440
5e19c0b0
MR		 3441 /*
3442 * 1. Enable Power Wells
3443 *
3444 * This was handled at the beginning of intel_atomic_commit_tail(),
3445 * before we called down into this function.
3446 */
99389390 3447
5e19c0b0 3448 /* 2. Enable Panel Power if PPS is required */
99389390
JRS		 3449 intel_edp_panel_on(intel_dp);
3450
3451 /*
5e19c0b0
MR		 3452 * 3. For non-TBT Type-C ports, set FIA lane count
3453 * (DFLEXDPSP.DPX4TXLATC)
3454 *
3455 * This was done before tgl_ddi_pre_enable_dp by
3456 * haswell_crtc_enable()->intel_encoders_pre_pll_enable().
99389390
JRS		 3457 */
3458
5e19c0b0
MR		 3459 /*
3460 * 4. Enable the port PLL.
3461 *
3462 * The PLL enabling itself was already done before this function by
3463 * haswell_crtc_enable()->intel_enable_shared_dpll(). We need only
3464 * configure the PLL to port mapping here.
3465 */
6171e58b
CT		 3466 intel_ddi_clk_select(encoder, crtc_state);
3467
5e19c0b0 3468 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
99389390
JRS		 3469 if (!intel_phy_is_tc(dev_priv, phy) ||
3470 dig_port->tc_mode != TC_PORT_TBT_ALT)
3471 intel_display_power_get(dev_priv,
3472 dig_port->ddi_io_power_domain);
3473
5e19c0b0 3474 /* 6. Program DP_MODE */
3b51be4e 3475 icl_program_mg_dp_mode(dig_port, crtc_state);
99389390
JRS		 3476
3477 /*
5e19c0b0
MR		 3478 * 7. The rest of the below are substeps under the bspec's "Enable and
3479 * Train Display Port" step. Note that steps that are specific to
3480 * MST will be handled by intel_mst_pre_enable_dp() before/after it
3481 * calls into this function. Also intel_mst_pre_enable_dp() only calls
3482 * us when active_mst_links==0, so any steps designated for "single
3483 * stream or multi-stream master transcoder" can just be performed
3484 * unconditionally here.
3485 */
3486
3487 /*
3488 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3489 * Transcoder.
99389390
JRS		 3490 */
3491 intel_ddi_enable_pipe_clock(crtc_state);
3492
5e19c0b0
MR		 3493 /*
3494 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3495 * Transport Select
3496 */
99389390
JRS		 3497 intel_ddi_config_transcoder_func(crtc_state);
3498
5e19c0b0
MR		 3499 /*
3500 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3501 * selected
3502 *
3503 * This will be handled by the intel_dp_start_link_train() farther
3504 * down this function.
3505 */
3506
3507 /*
3508 * 7.d Type C with DP alternate or fixed/legacy/static connection -
3509 * Disable PHY clock gating per Type-C DDI Buffer page
3510 */
8aaf5cbd 3511 icl_phy_set_clock_gating(dig_port, false);
99389390 3512
5e19c0b0 3513 /* 7.e Configure voltage swing and related IO settings */
978c3e53 3514 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
99389390
JRS		 3515 encoder->type);
3516
5e19c0b0
MR		 3517 /*
3518 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3519 * the used lanes of the DDI.
3520 */
99389390
JRS		 3521 if (intel_phy_is_combo(dev_priv, phy)) {
3522 bool lane_reversal =
3523 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3524
3525 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3526 crtc_state->lane_count,
3527 lane_reversal);
3528 }
3529
5e19c0b0
MR		 3530 /*
3531 * 7.g Configure and enable DDI_BUF_CTL
3532 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3533 * after 500 us.
3534 *
3535 * We only configure what the register value will be here. Actual
3536 * enabling happens during link training farther down.
3537 */
99389390
JRS		 3538 intel_ddi_init_dp_buf_reg(encoder);
3539
3540 if (!is_mst)
3541 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3542
3543 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3544 /*
3545 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3546 * in the FEC_CONFIGURATION register to 1 before initiating link
3547 * training
3548 */
3549 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
5e19c0b0
MR		 3550
3551 /*
3552 * 7.i Follow DisplayPort specification training sequence (see notes for
3553 * failure handling)
3554 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3555 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3556 * (timeout after 800 us)
3557 */
99389390
JRS		 3558 intel_dp_start_link_train(intel_dp);
3559
5e19c0b0 3560 /* 7.k Set DP_TP_CTL link training to Normal */
eadf6f91
MN		 3561 if (!is_trans_port_sync_mode(crtc_state))
3562 intel_dp_stop_link_train(intel_dp);
99389390 3563
978c3e53
CT		 3564 /*
3565 * TODO: enable clock gating
3566 *
3567 * It is not written in DP enabling sequence but "PHY Clockgating
3568 * programming" states that clock gating should be enabled after the
3569 * link training but doing so causes all the following trainings to fail
3570 * so not enabling it for now.
3571 */
3572
5e19c0b0 3573 /* 7.l Configure and enable FEC if needed */
99389390
JRS		 3574 intel_ddi_enable_fec(encoder, crtc_state);
3575 intel_dsc_enable(encoder, crtc_state);
3576}
3577
3578static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3579 const struct intel_crtc_state *crtc_state,
3580 const struct drm_connector_state *conn_state)
e404ba8d 3581{
ba88d153
MN		 3582 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3583 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3584 enum port port = encoder->port;
dc867bc7 3585 enum phy phy = intel_port_to_phy(dev_priv, port);
62b69566 3586 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3587 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3588 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3589
45e0327e 3590 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3591
45e0327e
VS		 3592 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3593 crtc_state->lane_count, is_mst);
680b71c2 3594
4444df6e
LDM		 3595 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3596 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3597
680b71c2 3598 intel_edp_panel_on(intel_dp);
32bdc400 3599
0e5fa646 3600 intel_ddi_clk_select(encoder, crtc_state);
62b69566 3601
d8fe2ab6 3602 if (!intel_phy_is_tc(dev_priv, phy) ||
3b2ed431
ID		 3603 dig_port->tc_mode != TC_PORT_TBT_ALT)
3604 intel_display_power_get(dev_priv,
3605 dig_port->ddi_io_power_domain);
62b69566 3606
3b51be4e 3607 icl_program_mg_dp_mode(dig_port, crtc_state);
8aaf5cbd 3608 icl_phy_set_clock_gating(dig_port, false);
340a44be 3609
2dd24a9c 3610 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3611 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3612 level, encoder->type);
fb5c8e9d 3613 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3614 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3615 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3616 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3617 else
3a6d84e6 3618 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3619
d8fe2ab6 3620 if (intel_phy_is_combo(dev_priv, phy)) {
cfda08cd
ID		 3621 bool lane_reversal =
3622 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3623
dc867bc7 3624 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
cfda08cd
ID		 3625 crtc_state->lane_count,
3626 lane_reversal);
3627 }
3628
ba88d153 3629 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3630 if (!is_mst)
3631 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3632 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3633 true);
a322b975 3634 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153 3635 intel_dp_start_link_train(intel_dp);
eadf6f91
MN		 3636 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3637 !is_trans_port_sync_mode(crtc_state))
ba88d153 3638 intel_dp_stop_link_train(intel_dp);
afb2c443 3639
5c44b938
AS		 3640 intel_ddi_enable_fec(encoder, crtc_state);
3641
8aaf5cbd 3642 icl_phy_set_clock_gating(dig_port, true);
bc334d91 3643
2b5cf4ef
ID		 3644 if (!is_mst)
3645 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3646
3647 intel_dsc_enable(encoder, crtc_state);
ba88d153 3648}
901c2daf 3649
99389390
JRS		 3650static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3651 const struct intel_crtc_state *crtc_state,
3652 const struct drm_connector_state *conn_state)
3653{
3654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3655
3656 if (INTEL_GEN(dev_priv) >= 12)
3657 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3658 else
3659 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
0c06fa15 3660
bd8c9cca
GM		 3661 /* MST will call a setting of MSA after an allocating of Virtual Channel
3662 * from MST encoder pre_enable callback.
3663 */
3664 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3665 intel_ddi_set_dp_msa(crtc_state, conn_state);
99389390
JRS		 3666}
3667
ba88d153 3668static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3669 const struct intel_crtc_state *crtc_state,
45e0327e 3670 const struct drm_connector_state *conn_state)
ba88d153 3671{
f99be1b3
VS		 3672 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3673 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3674 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3675 enum port port = encoder->port;
ba88d153 3676 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3677 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3678
ba88d153 3679 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3680 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3681
3682 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3683
3b51be4e 3684 icl_program_mg_dp_mode(dig_port, crtc_state);
8aaf5cbd 3685 icl_phy_set_clock_gating(dig_port, false);
cb9ff519 3686
978c3e53
CT		 3687 if (INTEL_GEN(dev_priv) >= 12)
3688 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3689 level, INTEL_OUTPUT_HDMI);
3690 else if (INTEL_GEN(dev_priv) == 11)
07685c82
MN		 3691 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3692 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3693 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3694 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3695 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3696 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3697 else
7ea79333 3698 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3699
8aaf5cbd 3700 icl_phy_set_clock_gating(dig_port, true);
cb9ff519 3701
2f7460a7 3702 if (IS_GEN9_BC(dev_priv))
081dfcfa 3703 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3704
c7373764
ID		 3705 intel_ddi_enable_pipe_clock(crtc_state);
3706
790ea70c 3707 intel_dig_port->set_infoframes(encoder,
45e0327e 3708 crtc_state->has_infoframe,
f99be1b3 3709 crtc_state, conn_state);
ba88d153 3710}
32bdc400 3711
1524e93e 3712static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3713 const struct intel_crtc_state *crtc_state,
5f88a9c6 3714 const struct drm_connector_state *conn_state)
ba88d153 3715{
2225f3c6 3716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
45e0327e
VS		 3717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3718 enum pipe pipe = crtc->pipe;
30cf6db8 3719
1939ba51
VS		 3720 /*
3721 * When called from DP MST code:
3722 * - conn_state will be NULL
3723 * - encoder will be the main encoder (ie. mst->primary)
3724 * - the main connector associated with this port
3725 * won't be active or linked to a crtc
3726 * - crtc_state will be the state of the first stream to
3727 * be activated on this port, and it may not be the same
3728 * stream that will be deactivated last, but each stream
3729 * should have a state that is identical when it comes to
3730 * the DP link parameteres
3731 */
3732
45e0327e 3733 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3734
3b8c0d5b
JN		 3735 if (INTEL_GEN(dev_priv) >= 11)
3736 icl_map_plls_to_ports(encoder, crtc_state);
3737
364a3fe1
JN		 3738 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3739
06c812d7 3740 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3741 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3742 } else {
3743 struct intel_lspcon *lspcon =
3744 enc_to_intel_lspcon(&encoder->base);
3745
45e0327e 3746 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3747 if (lspcon->active) {
3748 struct intel_digital_port *dig_port =
3749 enc_to_dig_port(&encoder->base);
3750
3751 dig_port->set_infoframes(encoder,
3752 crtc_state->has_infoframe,
3753 crtc_state, conn_state);
3754 }
3755 }
6441ab5f
PZ		 3756}
3757
d6a09cee
AS		 3758static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3759 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3760{
3761 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3762 enum port port = encoder->port;
e725f645
VS		 3763 bool wait = false;
3764 u32 val;
3765
3766 val = I915_READ(DDI_BUF_CTL(port));
3767 if (val & DDI_BUF_CTL_ENABLE) {
3768 val &= ~DDI_BUF_CTL_ENABLE;
3769 I915_WRITE(DDI_BUF_CTL(port), val);
3770 wait = true;
3771 }
3772
e468ff06 3773 if (intel_crtc_has_dp_encoder(crtc_state)) {
4444df6e
LDM		 3774 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3775
3776 val = I915_READ(intel_dp->regs.dp_tp_ctl);
e468ff06
LDM		 3777 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3778 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
4444df6e 3779 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
e468ff06 3780 }
e725f645 3781
d6a09cee
AS		 3782 /* Disable FEC in DP Sink */
3783 intel_ddi_disable_fec_state(encoder, crtc_state);
3784
e725f645
VS		 3785 if (wait)
3786 intel_wait_ddi_buf_idle(dev_priv, port);
3787}
3788
f45f3da7
VS		 3789static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3790 const struct intel_crtc_state *old_crtc_state,
3791 const struct drm_connector_state *old_conn_state)
6441ab5f 3792{
f45f3da7
VS		 3793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3794 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3795 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3796 bool is_mst = intel_crtc_has_type(old_crtc_state,
3797 INTEL_OUTPUT_DP_MST);
d8fe2ab6 3798 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2886e93f 3799
78eaaba3
JRS		 3800 /*
3801 * Power down sink before disabling the port, otherwise we end
3802 * up getting interrupts from the sink on detecting link loss.
3803 */
3804 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3805
3ca8f191 3806 if (INTEL_GEN(dev_priv) < 12 && !is_mst)
50a7efb2 3807 intel_ddi_disable_pipe_clock(old_crtc_state);
c5f93fcf 3808
d6a09cee 3809 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3810
3ca8f191
JRS		 3811 /*
3812 * From TGL spec: "If single stream or multi-stream master transcoder:
3813 * Configure Transcoder Clock select to direct no clock to the
3814 * transcoder"
3815 */
3816 if (INTEL_GEN(dev_priv) >= 12)
3817 intel_ddi_disable_pipe_clock(old_crtc_state);
3818
f45f3da7
VS		 3819 intel_edp_panel_vdd_on(intel_dp);
3820 intel_edp_panel_off(intel_dp);
a836bdf9 3821
d8fe2ab6 3822 if (!intel_phy_is_tc(dev_priv, phy) ||
3b2ed431
ID		 3823 dig_port->tc_mode != TC_PORT_TBT_ALT)
3824 intel_display_power_put_unchecked(dev_priv,
3825 dig_port->ddi_io_power_domain);
c5f93fcf 3826
f45f3da7 3827 intel_ddi_clk_disable(encoder);
bdacf087 3828 tgl_clear_psr2_transcoder_exitline(old_crtc_state);
f45f3da7 3829}
c5f93fcf 3830
f45f3da7
VS		 3831static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3832 const struct intel_crtc_state *old_crtc_state,
3833 const struct drm_connector_state *old_conn_state)
3834{
3835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3836 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3837 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3838
790ea70c 3839 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3840 old_crtc_state, old_conn_state);
3841
afb2c443
ID		 3842 intel_ddi_disable_pipe_clock(old_crtc_state);
3843
d6a09cee 3844 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3845
0e6e0be4
CW		 3846 intel_display_power_put_unchecked(dev_priv,
3847 dig_port->ddi_io_power_domain);
b2ccb822 3848
f45f3da7
VS		 3849 intel_ddi_clk_disable(encoder);
3850
3851 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3852}
3853
3854static void intel_ddi_post_disable(struct intel_encoder *encoder,
3855 const struct intel_crtc_state *old_crtc_state,
3856 const struct drm_connector_state *old_conn_state)
3857{
3b8c0d5b
JN		 3858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3859
f45f3da7 3860 /*
1939ba51
VS		 3861 * When called from DP MST code:
3862 * - old_conn_state will be NULL
3863 * - encoder will be the main encoder (ie. mst->primary)
3864 * - the main connector associated with this port
3865 * won't be active or linked to a crtc
3866 * - old_crtc_state will be the state of the last stream to
3867 * be deactivated on this port, and it may not be the same
3868 * stream that was activated last, but each stream
3869 * should have a state that is identical when it comes to
3870 * the DP link parameteres
f45f3da7 3871 */
1939ba51
VS		 3872
3873 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3874 intel_ddi_post_disable_hdmi(encoder,
3875 old_crtc_state, old_conn_state);
3876 else
3877 intel_ddi_post_disable_dp(encoder,
3878 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3879
3880 if (INTEL_GEN(dev_priv) >= 11)
3881 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3882}
3883
1524e93e 3884void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3885 const struct intel_crtc_state *old_crtc_state,
3886 const struct drm_connector_state *old_conn_state)
b7076546 3887{
1524e93e 3888 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3889 u32 val;
b7076546
ML		 3890
3891 /*
3892 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3893 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3894 * step 13 is the correct place for it. Step 18 is where it was
3895 * originally before the BUN.
3896 */
3897 val = I915_READ(FDI_RX_CTL(PIPE_A));
3898 val &= ~FDI_RX_ENABLE;
3899 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3900
d6a09cee 3901 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3902 intel_ddi_clk_disable(encoder);
b7076546
ML		 3903
3904 val = I915_READ(FDI_RX_MISC(PIPE_A));
3905 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3906 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3907 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3908
3909 val = I915_READ(FDI_RX_CTL(PIPE_A));
3910 val &= ~FDI_PCDCLK;
3911 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3912
3913 val = I915_READ(FDI_RX_CTL(PIPE_A));
3914 val &= ~FDI_RX_PLL_ENABLE;
3915 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3916}
3917
15d05f0e
VS		 3918static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3919 const struct intel_crtc_state *crtc_state,
3920 const struct drm_connector_state *conn_state)
72662e10 3921{
15d05f0e
VS		 3922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3923 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3924 enum port port = encoder->port;
72662e10 3925
15d05f0e
VS		 3926 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3927 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3928
15d05f0e
VS		 3929 intel_edp_backlight_on(crtc_state, conn_state);
3930 intel_psr_enable(intel_dp, crtc_state);
bb71fb00 3931 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
b246cf21 3932 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
15d05f0e 3933 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3934
15d05f0e
VS		 3935 if (crtc_state->has_audio)
3936 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3937}
3938
8f19b401
ID		 3939static i915_reg_t
3940gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3941 enum port port)
3942{
12c4d4c1
VS		 3943 static const enum transcoder trans[] = {
3944 [PORT_A] = TRANSCODER_EDP,
3945 [PORT_B] = TRANSCODER_A,
3946 [PORT_C] = TRANSCODER_B,
3947 [PORT_D] = TRANSCODER_C,
3948 [PORT_E] = TRANSCODER_A,
8f19b401
ID		 3949 };
3950
3951 WARN_ON(INTEL_GEN(dev_priv) < 9);
3952
3953 if (WARN_ON(port < PORT_A || port > PORT_E))
3954 port = PORT_A;
3955
12c4d4c1 3956 return CHICKEN_TRANS(trans[port]);
8f19b401
ID		 3957}
3958
15d05f0e
VS		 3959static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3960 const struct intel_crtc_state *crtc_state,
3961 const struct drm_connector_state *conn_state)
3962{
3963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3964 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3965 struct drm_connector *connector = conn_state->connector;
0fce04c8 3966 enum port port = encoder->port;
15d05f0e 3967
277ab5ab
VS		 3968 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3969 crtc_state->hdmi_high_tmds_clock_ratio,
3970 crtc_state->hdmi_scrambling))
3971 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3972 connector->base.id, connector->name);
15d05f0e 3973
0519c102
VS		 3974 /* Display WA #1143: skl,kbl,cfl */
3975 if (IS_GEN9_BC(dev_priv)) {
3976 /*
3977 * For some reason these chicken bits have been
3978 * stuffed into a transcoder register, event though
3979 * the bits affect a specific DDI port rather than
3980 * a specific transcoder.
3981 */
8f19b401 3982 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3983 u32 val;
3984
8f19b401 3985 val = I915_READ(reg);
0519c102
VS		 3986
3987 if (port == PORT_E)
3988 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3989 DDIE_TRAINING_OVERRIDE_VALUE;
3990 else
3991 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3992 DDI_TRAINING_OVERRIDE_VALUE;
3993
8f19b401
ID		 3994 I915_WRITE(reg, val);
3995 POSTING_READ(reg);
0519c102
VS		 3996
3997 udelay(1);
3998
3999 if (port == PORT_E)
4000 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
4001 DDIE_TRAINING_OVERRIDE_VALUE);
4002 else
4003 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
4004 DDI_TRAINING_OVERRIDE_VALUE);
4005
8f19b401 4006 I915_WRITE(reg, val);
0519c102
VS		 4007 }
4008
15d05f0e
VS		 4009 /* In HDMI/DVI mode, the port width, and swing/emphasis values
4010 * are ignored so nothing special needs to be done besides
4011 * enabling the port.
4012 */
4013 I915_WRITE(DDI_BUF_CTL(port),
4014 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 4015
15d05f0e
VS		 4016 if (crtc_state->has_audio)
4017 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4018}
4019
4020static void intel_enable_ddi(struct intel_encoder *encoder,
4021 const struct intel_crtc_state *crtc_state,
4022 const struct drm_connector_state *conn_state)
4023{
4024 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4025 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
4026 else
4027 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 4028
4029 /* Enable hdcp if it's desired */
4030 if (conn_state->content_protection ==
4031 DRM_MODE_CONTENT_PROTECTION_DESIRED)
d456512c 4032 intel_hdcp_enable(to_intel_connector(conn_state->connector),
67e1d5ed 4033 crtc_state->cpu_transcoder,
d456512c 4034 (u8)conn_state->hdcp_content_type);
5ab432ef
DV		 4035}
4036
33f083f0
VS		 4037static void intel_disable_ddi_dp(struct intel_encoder *encoder,
4038 const struct intel_crtc_state *old_crtc_state,
4039 const struct drm_connector_state *old_conn_state)
5ab432ef 4040{
33f083f0 4041 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 4042
edb2e530
VS		 4043 intel_dp->link_trained = false;
4044
37255d8d 4045 if (old_crtc_state->has_audio)
8ec47de2
VS		 4046 intel_audio_codec_disable(encoder,
4047 old_crtc_state, old_conn_state);
2831d842 4048
33f083f0
VS		 4049 intel_edp_drrs_disable(intel_dp, old_crtc_state);
4050 intel_psr_disable(intel_dp, old_crtc_state);
4051 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 4052 /* Disable the decompression in DP Sink */
4053 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4054 false);
33f083f0 4055}
15953637 4056
33f083f0
VS		 4057static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
4058 const struct intel_crtc_state *old_crtc_state,
4059 const struct drm_connector_state *old_conn_state)
4060{
277ab5ab
VS		 4061 struct drm_connector *connector = old_conn_state->connector;
4062
33f083f0 4063 if (old_crtc_state->has_audio)
8ec47de2
VS		 4064 intel_audio_codec_disable(encoder,
4065 old_crtc_state, old_conn_state);
d6c50ff8 4066
277ab5ab
VS		 4067 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4068 false, false))
4069 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4070 connector->base.id, connector->name);
33f083f0
VS		 4071}
4072
4073static void intel_disable_ddi(struct intel_encoder *encoder,
4074 const struct intel_crtc_state *old_crtc_state,
4075 const struct drm_connector_state *old_conn_state)
4076{
ee5e5e7a
SP		 4077 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4078
33f083f0
VS		 4079 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4080 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
4081 else
4082 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 4083}
79f689aa 4084
2ef82327
HG		 4085static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
4086 const struct intel_crtc_state *crtc_state,
4087 const struct drm_connector_state *conn_state)
4088{
4089 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4090
0c06fa15 4091 intel_ddi_set_dp_msa(crtc_state, conn_state);
5aa2c9ae 4092
23ec9f52 4093 intel_psr_update(intel_dp, crtc_state);
2ef82327 4094 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 4095
4096 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 4097}
4098
4099static void intel_ddi_update_pipe(struct intel_encoder *encoder,
4100 const struct intel_crtc_state *crtc_state,
4101 const struct drm_connector_state *conn_state)
4102{
d456512c
R		 4103 struct intel_connector *connector =
4104 to_intel_connector(conn_state->connector);
4105 struct intel_hdcp *hdcp = &connector->hdcp;
4106 bool content_protection_type_changed =
4107 (conn_state->hdcp_content_type != hdcp->content_type &&
4108 conn_state->content_protection !=
4109 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
4110
2ef82327
HG		 4111 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4112 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1 4113
d456512c
R		 4114 /*
4115 * During the HDCP encryption session if Type change is requested,
4116 * disable the HDCP and reenable it with new TYPE value.
4117 */
634852d1 4118 if (conn_state->content_protection ==
d456512c
R		 4119 DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
4120 content_protection_type_changed)
4121 intel_hdcp_disable(connector);
4122
4123 /*
4124 * Mark the hdcp state as DESIRED after the hdcp disable of type
4125 * change procedure.
4126 */
4127 if (content_protection_type_changed) {
4128 mutex_lock(&hdcp->mutex);
4129 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4130 schedule_work(&hdcp->prop_work);
4131 mutex_unlock(&hdcp->mutex);
4132 }
4133
4134 if (conn_state->content_protection ==
4135 DRM_MODE_CONTENT_PROTECTION_DESIRED ||
4136 content_protection_type_changed)
67e1d5ed
VS		 4137 intel_hdcp_enable(connector,
4138 crtc_state->cpu_transcoder,
4139 (u8)conn_state->hdcp_content_type);
2ef82327
HG		 4140}
4141
24a7bfe0
ID		 4142static void
4143intel_ddi_update_prepare(struct intel_atomic_state *state,
4144 struct intel_encoder *encoder,
4145 struct intel_crtc *crtc)
4146{
4147 struct intel_crtc_state *crtc_state =
4148 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4149 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4150
4151 WARN_ON(crtc && crtc->active);
4152
4153 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
1326a92c 4154 if (crtc_state && crtc_state->hw.active)
24a7bfe0
ID		 4155 intel_update_active_dpll(state, crtc, encoder);
4156}
4157
4158static void
4159intel_ddi_update_complete(struct intel_atomic_state *state,
4160 struct intel_encoder *encoder,
4161 struct intel_crtc *crtc)
4162{
4163 intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
4164}
4165
bdaa29b6
ID		 4166static void
4167intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
4168 const struct intel_crtc_state *crtc_state,
4169 const struct drm_connector_state *conn_state)
03ad7d88 4170{
bdaa29b6 4171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 4172 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
d8fe2ab6
MR		 4173 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4174 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
bdaa29b6 4175
24a7bfe0
ID		 4176 if (is_tc_port)
4177 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4178
4179 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
bdaa29b6
ID		 4180 intel_display_power_get(dev_priv,
4181 intel_ddi_main_link_aux_domain(dig_port));
4182
9d44dcb9
LDM		 4183 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4184 /*
4185 * Program the lane count for static/dynamic connections on
4186 * Type-C ports. Skip this step for TBT.
4187 */
4188 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4189 else if (IS_GEN9_LP(dev_priv))
bdaa29b6
ID		 4190 bxt_ddi_phy_set_lane_optim_mask(encoder,
4191 crtc_state->lane_lat_optim_mask);
bdaa29b6
ID		 4192}
4193
4194static void
4195intel_ddi_post_pll_disable(struct intel_encoder *encoder,
4196 const struct intel_crtc_state *crtc_state,
4197 const struct drm_connector_state *conn_state)
4198{
4199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4200 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
d8fe2ab6
MR		 4201 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4202 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
bdaa29b6 4203
24a7bfe0 4204 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
0e6e0be4
CW		 4205 intel_display_power_put_unchecked(dev_priv,
4206 intel_ddi_main_link_aux_domain(dig_port));
24a7bfe0
ID		 4207
4208 if (is_tc_port)
4209 intel_tc_port_put_link(dig_port);
03ad7d88
MN		 4210}
4211
97068c1b 4212static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 4213{
ad64217b
ACO		 4214 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4215 struct drm_i915_private *dev_priv =
4216 to_i915(intel_dig_port->base.base.dev);
8f4f2797 4217 enum port port = intel_dig_port->base.port;
35ac28a8 4218 u32 dp_tp_ctl, ddi_buf_ctl;
f3e227df 4219 bool wait = false;
c19b0669 4220
35ac28a8
LDM		 4221 dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
4222
4223 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4224 ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
4225 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4226 I915_WRITE(DDI_BUF_CTL(port),
4227 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
c19b0669
PZ		 4228 wait = true;
4229 }
4230
35ac28a8
LDM		 4231 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4232 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4233 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4444df6e 4234 POSTING_READ(intel_dp->regs.dp_tp_ctl);
c19b0669
PZ		 4235
4236 if (wait)
4237 intel_wait_ddi_buf_idle(dev_priv, port);
4238 }
4239
35ac28a8
LDM		 4240 dp_tp_ctl = DP_TP_CTL_ENABLE |
4241 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 4242 if (intel_dp->link_mst)
35ac28a8 4243 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
0e32b39c 4244 else {
35ac28a8 4245 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
0e32b39c 4246 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
35ac28a8 4247 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
0e32b39c 4248 }
35ac28a8 4249 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4444df6e 4250 POSTING_READ(intel_dp->regs.dp_tp_ctl);
c19b0669
PZ		 4251
4252 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4253 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
4254 POSTING_READ(DDI_BUF_CTL(port));
4255
4256 udelay(600);
4257}
00c09d70 4258
2085cc5d
VS		 4259static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4260 enum transcoder cpu_transcoder)
9935f7fa 4261{
2085cc5d
VS		 4262 if (cpu_transcoder == TRANSCODER_EDP)
4263 return false;
9935f7fa 4264
2085cc5d
VS		 4265 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4266 return false;
4267
4268 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
4269 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 4270}
4271
53e9bf5e
VS		 4272void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4273 struct intel_crtc_state *crtc_state)
4274{
2dd24a9c 4275 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 4276 crtc_state->min_voltage_level = 1;
36c1f028
RV		 4277 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4278 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 4279}
4280
6801c18c 4281void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 4282 struct intel_crtc_state *pipe_config)
045ac3b5 4283{
fac5e23e 4284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2225f3c6 4285 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
0cb09a97 4286 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
045ac3b5
JB		 4287 u32 temp, flags = 0;
4288
4d1de975
JN		 4289 /* XXX: DSI transcoder paranoia */
4290 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
4291 return;
4292
fbacb15e
JN		 4293 intel_dsc_get_config(encoder, pipe_config);
4294
045ac3b5
JB		 4295 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
4296 if (temp & TRANS_DDI_PHSYNC)
4297 flags |= DRM_MODE_FLAG_PHSYNC;
4298 else
4299 flags |= DRM_MODE_FLAG_NHSYNC;
4300 if (temp & TRANS_DDI_PVSYNC)
4301 flags |= DRM_MODE_FLAG_PVSYNC;
4302 else
4303 flags |= DRM_MODE_FLAG_NVSYNC;
4304
1326a92c 4305 pipe_config->hw.adjusted_mode.flags |= flags;
42571aef
VS		 4306
4307 switch (temp & TRANS_DDI_BPC_MASK) {
4308 case TRANS_DDI_BPC_6:
4309 pipe_config->pipe_bpp = 18;
4310 break;
4311 case TRANS_DDI_BPC_8:
4312 pipe_config->pipe_bpp = 24;
4313 break;
4314 case TRANS_DDI_BPC_10:
4315 pipe_config->pipe_bpp = 30;
4316 break;
4317 case TRANS_DDI_BPC_12:
4318 pipe_config->pipe_bpp = 36;
4319 break;
4320 default:
4321 break;
4322 }
eb14cb74
VS		 4323
4324 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4325 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 4326 pipe_config->has_hdmi_sink = true;
bbd440fb 4327
e5e70d4a
VS		 4328 pipe_config->infoframes.enable |=
4329 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4330
4331 if (pipe_config->infoframes.enable)
bbd440fb 4332 pipe_config->has_infoframe = true;
15953637 4333
ab2cb2cb 4334 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 4335 pipe_config->hdmi_scrambling = true;
4336 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4337 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 4338 /* fall through */
eb14cb74 4339 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 4340 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 4341 pipe_config->lane_count = 4;
4342 break;
eb14cb74 4343 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 4344 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 4345 break;
4346 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 4347 if (encoder->type == INTEL_OUTPUT_EDP)
4348 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4349 else
4350 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4351 pipe_config->lane_count =
4352 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4353 intel_dp_get_m_n(intel_crtc, pipe_config);
8aa940c8
ML		 4354
4355 if (INTEL_GEN(dev_priv) >= 11) {
4356 i915_reg_t dp_tp_ctl;
4357
4358 if (IS_GEN(dev_priv, 11))
4359 dp_tp_ctl = DP_TP_CTL(encoder->port);
4360 else
4361 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4362
4363 pipe_config->fec_enable =
4364 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4365
4366 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4367 encoder->base.base.id, encoder->base.name,
4368 pipe_config->fec_enable);
4369 }
4370
e1214b95 4371 break;
eb14cb74 4372 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 4373 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 4374 pipe_config->lane_count =
4375 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 4376 intel_dp_get_m_n(intel_crtc, pipe_config);
4377 break;
4378 default:
4379 break;
4380 }
10214420 4381
bdacf087
AG		 4382 if (encoder->type == INTEL_OUTPUT_EDP)
4383 tgl_dc3co_exitline_get_config(pipe_config);
4384
9935f7fa 4385 pipe_config->has_audio =
2085cc5d 4386 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 4387
6aa23e65
JN		 4388 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4389 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 4390 /*
4391 * This is a big fat ugly hack.
4392 *
4393 * Some machines in UEFI boot mode provide us a VBT that has 18
4394 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4395 * unknown we fail to light up. Yet the same BIOS boots up with
4396 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4397 * max, not what it tells us to use.
4398 *
4399 * Note: This will still be broken if the eDP panel is not lit
4400 * up by the BIOS, and thus we can't get the mode at module
4401 * load.
4402 */
4403 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 4404 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4405 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 4406 }
11578553 4407
22606a18 4408 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 4409
cc3f90f0 4410 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 4411 pipe_config->lane_lat_optim_mask =
4412 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 4413
4414 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 4415
4416 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4417
4418 intel_read_infoframe(encoder, pipe_config,
4419 HDMI_INFOFRAME_TYPE_AVI,
4420 &pipe_config->infoframes.avi);
4421 intel_read_infoframe(encoder, pipe_config,
4422 HDMI_INFOFRAME_TYPE_SPD,
4423 &pipe_config->infoframes.spd);
4424 intel_read_infoframe(encoder, pipe_config,
4425 HDMI_INFOFRAME_TYPE_VENDOR,
4426 &pipe_config->infoframes.hdmi);
b37f588e
US		 4427 intel_read_infoframe(encoder, pipe_config,
4428 HDMI_INFOFRAME_TYPE_DRM,
4429 &pipe_config->infoframes.drm);
045ac3b5
JB		 4430}
4431
7e732cac
VS		 4432static enum intel_output_type
4433intel_ddi_compute_output_type(struct intel_encoder *encoder,
4434 struct intel_crtc_state *crtc_state,
4435 struct drm_connector_state *conn_state)
4436{
4437 switch (conn_state->connector->connector_type) {
4438 case DRM_MODE_CONNECTOR_HDMIA:
4439 return INTEL_OUTPUT_HDMI;
4440 case DRM_MODE_CONNECTOR_eDP:
4441 return INTEL_OUTPUT_EDP;
4442 case DRM_MODE_CONNECTOR_DisplayPort:
4443 return INTEL_OUTPUT_DP;
4444 default:
4445 MISSING_CASE(conn_state->connector->connector_type);
4446 return INTEL_OUTPUT_UNUSED;
4447 }
4448}
4449
204474a6
LP		 4450static int intel_ddi_compute_config(struct intel_encoder *encoder,
4451 struct intel_crtc_state *pipe_config,
4452 struct drm_connector_state *conn_state)
00c09d70 4453{
2225f3c6 4454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
fac5e23e 4455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 4456 enum port port = encoder->port;
95a7a2ae 4457 int ret;
00c09d70 4458
bc7e3525 4459 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 4460 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4461
bdacf087 4462 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
0a478c27 4463 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
bdacf087 4464 } else {
0a478c27 4465 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
bdacf087
AG		 4466 tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4467 }
4468
7a412b8f
VS		 4469 if (ret)
4470 return ret;
95a7a2ae 4471
dc0c0bfe
VS		 4472 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4473 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4474 pipe_config->pch_pfit.force_thru =
4475 pipe_config->pch_pfit.enabled ||
4476 pipe_config->crc_enabled;
4477
7a412b8f 4478 if (IS_GEN9_LP(dev_priv))
95a7a2ae 4479 pipe_config->lane_lat_optim_mask =
5161d058 4480 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 4481
53e9bf5e
VS		 4482 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4483
7a412b8f 4484 return 0;
00c09d70
PZ		 4485}
4486
f6bff60e
ID		 4487static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4488{
4489 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
f6bff60e
ID		 4490
4491 intel_dp_encoder_flush_work(encoder);
4492
f6bff60e
ID		 4493 drm_encoder_cleanup(encoder);
4494 kfree(dig_port);
4495}
4496
00c09d70 4497static const struct drm_encoder_funcs intel_ddi_funcs = {
32691b58 4498 .reset = intel_dp_encoder_reset,
f6bff60e 4499 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 4500};
4501
4a28ae58
PZ		 4502static struct intel_connector *
4503intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4504{
4505 struct intel_connector *connector;
8f4f2797 4506 enum port port = intel_dig_port->base.port;
4a28ae58 4507
9bdbd0b9 4508 connector = intel_connector_alloc();
4a28ae58
PZ		 4509 if (!connector)
4510 return NULL;
4511
4512 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
97068c1b
VS		 4513 intel_dig_port->dp.prepare_link_retrain =
4514 intel_ddi_prepare_link_retrain;
4515
4a28ae58
PZ		 4516 if (!intel_dp_init_connector(intel_dig_port, connector)) {
4517 kfree(connector);
4518 return NULL;
4519 }
4520
4521 return connector;
4522}
4523
dba14b27
VS		 4524static int modeset_pipe(struct drm_crtc *crtc,
4525 struct drm_modeset_acquire_ctx *ctx)
4526{
4527 struct drm_atomic_state *state;
4528 struct drm_crtc_state *crtc_state;
4529 int ret;
4530
4531 state = drm_atomic_state_alloc(crtc->dev);
4532 if (!state)
4533 return -ENOMEM;
4534
4535 state->acquire_ctx = ctx;
4536
4537 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4538 if (IS_ERR(crtc_state)) {
4539 ret = PTR_ERR(crtc_state);
4540 goto out;
4541 }
4542
b8fe992a 4543 crtc_state->connectors_changed = true;
dba14b27 4544
dba14b27 4545 ret = drm_atomic_commit(state);
a551cd66 4546out:
dba14b27
VS		 4547 drm_atomic_state_put(state);
4548
4549 return ret;
4550}
4551
4552static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4553 struct drm_modeset_acquire_ctx *ctx)
4554{
4555 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4556 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4557 struct intel_connector *connector = hdmi->attached_connector;
4558 struct i2c_adapter *adapter =
4559 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4560 struct drm_connector_state *conn_state;
4561 struct intel_crtc_state *crtc_state;
4562 struct intel_crtc *crtc;
4563 u8 config;
4564 int ret;
4565
4566 if (!connector || connector->base.status != connector_status_connected)
4567 return 0;
4568
4569 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4570 ctx);
4571 if (ret)
4572 return ret;
4573
4574 conn_state = connector->base.state;
4575
4576 crtc = to_intel_crtc(conn_state->crtc);
4577 if (!crtc)
4578 return 0;
4579
4580 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4581 if (ret)
4582 return ret;
4583
4584 crtc_state = to_intel_crtc_state(crtc->base.state);
4585
4586 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4587
1326a92c 4588 if (!crtc_state->hw.active)
dba14b27
VS		 4589 return 0;
4590
4591 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4592 !crtc_state->hdmi_scrambling)
4593 return 0;
4594
4595 if (conn_state->commit &&
4596 !try_wait_for_completion(&conn_state->commit->hw_done))
4597 return 0;
4598
4599 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4600 if (ret < 0) {
4601 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4602 return 0;
4603 }
4604
4605 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4606 crtc_state->hdmi_high_tmds_clock_ratio &&
4607 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4608 crtc_state->hdmi_scrambling)
4609 return 0;
4610
4611 /*
4612 * HDMI 2.0 says that one should not send scrambled data
4613 * prior to configuring the sink scrambling, and that
4614 * TMDS clock/data transmission should be suspended when
4615 * changing the TMDS clock rate in the sink. So let's
4616 * just do a full modeset here, even though some sinks
4617 * would be perfectly happy if were to just reconfigure
4618 * the SCDC settings on the fly.
4619 */
4620 return modeset_pipe(&crtc->base, ctx);
4621}
4622
3944709d
ID		 4623static enum intel_hotplug_state
4624intel_ddi_hotplug(struct intel_encoder *encoder,
4625 struct intel_connector *connector,
4626 bool irq_received)
dba14b27 4627{
bb80c925 4628 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
dba14b27 4629 struct drm_modeset_acquire_ctx ctx;
3944709d 4630 enum intel_hotplug_state state;
dba14b27
VS		 4631 int ret;
4632
3944709d 4633 state = intel_encoder_hotplug(encoder, connector, irq_received);
dba14b27
VS		 4634
4635 drm_modeset_acquire_init(&ctx, 0);
4636
4637 for (;;) {
c85d200e
VS		 4638 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4639 ret = intel_hdmi_reset_link(encoder, &ctx);
4640 else
4641 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4642
4643 if (ret == -EDEADLK) {
4644 drm_modeset_backoff(&ctx);
4645 continue;
4646 }
4647
4648 break;
4649 }
4650
4651 drm_modeset_drop_locks(&ctx);
4652 drm_modeset_acquire_fini(&ctx);
4653 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4654
bb80c925
JRS		 4655 /*
4656 * Unpowered type-c dongles can take some time to boot and be
4657 * responsible, so here giving some time to those dongles to power up
4658 * and then retrying the probe.
4659 *
4660 * On many platforms the HDMI live state signal is known to be
4661 * unreliable, so we can't use it to detect if a sink is connected or
4662 * not. Instead we detect if it's connected based on whether we can
4663 * read the EDID or not. That in turn has a problem during disconnect,
4664 * since the HPD interrupt may be raised before the DDC lines get
4665 * disconnected (due to how the required length of DDC vs. HPD
4666 * connector pins are specified) and so we'll still be able to get a
4667 * valid EDID. To solve this schedule another detection cycle if this
4668 * time around we didn't detect any change in the sink's connection
4669 * status.
4670 */
4671 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4672 !dig_port->dp.is_mst)
4673 state = INTEL_HOTPLUG_RETRY;
4674
3944709d 4675 return state;
dba14b27
VS		 4676}
4677
4a28ae58
PZ		 4678static struct intel_connector *
4679intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4680{
4681 struct intel_connector *connector;
8f4f2797 4682 enum port port = intel_dig_port->base.port;
4a28ae58 4683
9bdbd0b9 4684 connector = intel_connector_alloc();
4a28ae58
PZ		 4685 if (!connector)
4686 return NULL;
4687
4688 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4689 intel_hdmi_init_connector(intel_dig_port, connector);
4690
4691 return connector;
4692}
4693
436009b5
RV		 4694static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4695{
4696 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4697
8f4f2797 4698 if (dport->base.port != PORT_A)
436009b5
RV		 4699 return false;
4700
4701 if (dport->saved_port_bits & DDI_A_4_LANES)
4702 return false;
4703
4704 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4705 * supported configuration
4706 */
4707 if (IS_GEN9_LP(dev_priv))
4708 return true;
4709
4710 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4711 * one who does also have a full A/E split called
4712 * DDI_F what makes DDI_E useless. However for this
4713 * case let's trust VBT info.
4714 */
4715 if (IS_CANNONLAKE(dev_priv) &&
4716 !intel_bios_is_port_present(dev_priv, PORT_E))
4717 return true;
4718
4719 return false;
4720}
4721
3d2011cf
MK		 4722static int
4723intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4724{
4725 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4726 enum port port = intel_dport->base.port;
4727 int max_lanes = 4;
4728
4729 if (INTEL_GEN(dev_priv) >= 11)
4730 return max_lanes;
4731
4732 if (port == PORT_A || port == PORT_E) {
4733 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4734 max_lanes = port == PORT_A ? 4 : 0;
4735 else
4736 /* Both A and E share 2 lanes */
4737 max_lanes = 2;
4738 }
4739
4740 /*
4741 * Some BIOS might fail to set this bit on port A if eDP
4742 * wasn't lit up at boot. Force this bit set when needed
4743 * so we use the proper lane count for our calculations.
4744 */
4745 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4746 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4747 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4748 max_lanes = 4;
4749 }
4750
4751 return max_lanes;
4752}
4753
c39055b0 4754void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4755{
f6bff60e
ID		 4756 struct ddi_vbt_port_info *port_info =
4757 &dev_priv->vbt.ddi_port_info[port];
00c09d70 4758 struct intel_digital_port *intel_dig_port;
70dfbc29 4759 struct intel_encoder *encoder;
ff662124 4760 bool init_hdmi, init_dp, init_lspcon = false;
d8fe2ab6 4761 enum phy phy = intel_port_to_phy(dev_priv, port);
10e7bec3 4762
f6bff60e
ID		 4763 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4764 init_dp = port_info->supports_dp;
ff662124
SS		 4765
4766 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4767 /*
4768 * Lspcon device needs to be driven with DP connector
4769 * with special detection sequence. So make sure DP
4770 * is initialized before lspcon.
4771 */
4772 init_dp = true;
4773 init_lspcon = true;
4774 init_hdmi = false;
4775 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4776 }
4777
311a2094 4778 if (!init_dp && !init_hdmi) {
500ea70d 4779 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4780 port_name(port));
500ea70d 4781 return;
311a2094 4782 }
00c09d70 4783
b14c5679 4784 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4785 if (!intel_dig_port)
4786 return;
4787
70dfbc29 4788 encoder = &intel_dig_port->base;
00c09d70 4789
70dfbc29 4790 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
580d8ed5 4791 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4792
70dfbc29
LDM		 4793 encoder->hotplug = intel_ddi_hotplug;
4794 encoder->compute_output_type = intel_ddi_compute_output_type;
4795 encoder->compute_config = intel_ddi_compute_config;
4796 encoder->enable = intel_enable_ddi;
4797 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4798 encoder->post_pll_disable = intel_ddi_post_pll_disable;
4799 encoder->pre_enable = intel_ddi_pre_enable;
4800 encoder->disable = intel_disable_ddi;
4801 encoder->post_disable = intel_ddi_post_disable;
4802 encoder->update_pipe = intel_ddi_update_pipe;
4803 encoder->get_hw_state = intel_ddi_get_hw_state;
4804 encoder->get_config = intel_ddi_get_config;
4805 encoder->suspend = intel_dp_encoder_suspend;
4806 encoder->get_power_domains = intel_ddi_get_power_domains;
4807
4808 encoder->type = INTEL_OUTPUT_DDI;
4809 encoder->power_domain = intel_port_to_power_domain(port);
4810 encoder->port = port;
4811 encoder->cloneable = 0;
4812 encoder->pipe_mask = ~0;
00c09d70 4813
1e6aa7e5
JN		 4814 if (INTEL_GEN(dev_priv) >= 11)
4815 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4816 DDI_BUF_PORT_REVERSAL;
4817 else
4818 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4819 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
70dfbc29 4820
3d2011cf
MK		 4821 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4822 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4823 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4824
d8fe2ab6 4825 if (intel_phy_is_tc(dev_priv, phy)) {
ab7bc4e1
ID		 4826 bool is_legacy = !port_info->supports_typec_usb &&
4827 !port_info->supports_tbt;
4828
4829 intel_tc_port_init(intel_dig_port, is_legacy);
24a7bfe0 4830
70dfbc29
LDM		 4831 encoder->update_prepare = intel_ddi_update_prepare;
4832 encoder->update_complete = intel_ddi_update_complete;
ab7bc4e1 4833 }
f6bff60e 4834
327f8d8c
LDM		 4835 WARN_ON(port > PORT_I);
4836 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4837 port - PORT_A;
62b69566 4838
f68d697e
CW		 4839 if (init_dp) {
4840 if (!intel_ddi_init_dp_connector(intel_dig_port))
4841 goto err;
13cf5504 4842
f68d697e 4843 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4844 }
21a8e6a4 4845
311a2094
PZ		 4846 /* In theory we don't need the encoder->type check, but leave it just in
4847 * case we have some really bad VBTs... */
70dfbc29 4848 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
f68d697e
CW		 4849 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4850 goto err;
21a8e6a4 4851 }
f68d697e 4852
ff662124
SS		 4853 if (init_lspcon) {
4854 if (lspcon_init(intel_dig_port))
4855 /* TODO: handle hdmi info frame part */
4856 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4857 port_name(port));
4858 else
4859 /*
4860 * LSPCON init faied, but DP init was success, so
4861 * lets try to drive as DP++ port.
4862 */
4863 DRM_ERROR("LSPCON init failed on port %c\n",
4864 port_name(port));
4865 }
4866
06c812d7 4867 intel_infoframe_init(intel_dig_port);
f6bff60e 4868
f68d697e
CW		 4869 return;
4870
4871err:
70dfbc29 4872 drm_encoder_cleanup(&encoder->base);
f68d697e 4873 kfree(intel_dig_port);
00c09d70 4874}
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