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drm/i915/tgl: Access the right register when handling PSR interruptions
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / display / intel_ddi.c
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45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
cfda08cd 32#include "intel_combo_phy.h"
ec7f29ff 33#include "intel_connector.h"
fdc24cf3 34#include "intel_ddi.h"
1d455f8d 35#include "intel_display_types.h"
27fec1f9 36#include "intel_dp.h"
e075094f 37#include "intel_dp_link_training.h"
b1ad4c39 38#include "intel_dpio_phy.h"
1dd07e56 39#include "intel_dsi.h"
8834e365 40#include "intel_fifo_underrun.h"
3ce2ea65 41#include "intel_gmbus.h"
408bd917 42#include "intel_hdcp.h"
0550691d 43#include "intel_hdmi.h"
dbeb38d9 44#include "intel_hotplug.h"
f3e18947 45#include "intel_lspcon.h"
44c1220a 46#include "intel_panel.h"
55367a27 47#include "intel_psr.h"
bc85328f 48#include "intel_tc.h"
b375d0ef 49#include "intel_vdsc.h"
45244b87 50
10122051
JN		 51struct ddi_buf_trans {
52 u32 trans1; /* balance leg enable, de-emph level */
53 u32 trans2; /* vref sel, vswing */
f8896f5d 54 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 55};
56
97eeb872
VS		 57static const u8 index_to_dp_signal_levels[] = {
58 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
59 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
60 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
61 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
62 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
63 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
64 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
65 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
68};
69
45244b87
ED		 70/* HDMI/DVI modes ignore everything but the last 2 items. So we share
71 * them for both DP and FDI transports, allowing those ports to
72 * automatically adapt to HDMI connections as well
73 */
10122051 74static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 75 { 0x00FFFFFF, 0x0006000E, 0x0 },
76 { 0x00D75FFF, 0x0005000A, 0x0 },
77 { 0x00C30FFF, 0x00040006, 0x0 },
78 { 0x80AAAFFF, 0x000B0000, 0x0 },
79 { 0x00FFFFFF, 0x0005000A, 0x0 },
80 { 0x00D75FFF, 0x000C0004, 0x0 },
81 { 0x80C30FFF, 0x000B0000, 0x0 },
82 { 0x00FFFFFF, 0x00040006, 0x0 },
83 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 84};
85
10122051 86static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 87 { 0x00FFFFFF, 0x0007000E, 0x0 },
88 { 0x00D75FFF, 0x000F000A, 0x0 },
89 { 0x00C30FFF, 0x00060006, 0x0 },
90 { 0x00AAAFFF, 0x001E0000, 0x0 },
91 { 0x00FFFFFF, 0x000F000A, 0x0 },
92 { 0x00D75FFF, 0x00160004, 0x0 },
93 { 0x00C30FFF, 0x001E0000, 0x0 },
94 { 0x00FFFFFF, 0x00060006, 0x0 },
95 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 96};
97
10122051
JN		 98static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
99 /* Idx NT mV d T mV d db */
f8896f5d
DW		 100 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
101 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
102 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
103 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
104 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
105 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
106 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
107 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
108 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
109 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
110 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
111 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 112};
113
10122051 114static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 115 { 0x00FFFFFF, 0x00000012, 0x0 },
116 { 0x00EBAFFF, 0x00020011, 0x0 },
117 { 0x00C71FFF, 0x0006000F, 0x0 },
118 { 0x00AAAFFF, 0x000E000A, 0x0 },
119 { 0x00FFFFFF, 0x00020011, 0x0 },
120 { 0x00DB6FFF, 0x0005000F, 0x0 },
121 { 0x00BEEFFF, 0x000A000C, 0x0 },
122 { 0x00FFFFFF, 0x0005000F, 0x0 },
123 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 124};
125
10122051 126static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 127 { 0x00FFFFFF, 0x0007000E, 0x0 },
128 { 0x00D75FFF, 0x000E000A, 0x0 },
129 { 0x00BEFFFF, 0x00140006, 0x0 },
130 { 0x80B2CFFF, 0x001B0002, 0x0 },
131 { 0x00FFFFFF, 0x000E000A, 0x0 },
132 { 0x00DB6FFF, 0x00160005, 0x0 },
133 { 0x80C71FFF, 0x001A0002, 0x0 },
134 { 0x00F7DFFF, 0x00180004, 0x0 },
135 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 136};
137
10122051 138static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 139 { 0x00FFFFFF, 0x0001000E, 0x0 },
140 { 0x00D75FFF, 0x0004000A, 0x0 },
141 { 0x00C30FFF, 0x00070006, 0x0 },
142 { 0x00AAAFFF, 0x000C0000, 0x0 },
143 { 0x00FFFFFF, 0x0004000A, 0x0 },
144 { 0x00D75FFF, 0x00090004, 0x0 },
145 { 0x00C30FFF, 0x000C0000, 0x0 },
146 { 0x00FFFFFF, 0x00070006, 0x0 },
147 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 148};
149
10122051
JN		 150static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
151 /* Idx NT mV d T mV df db */
f8896f5d
DW		 152 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
153 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
154 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
155 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
156 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
157 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
158 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
159 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
160 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
161 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 162};
163
5f8b2531 164/* Skylake H and S */
7f88e3af 165static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 166 { 0x00002016, 0x000000A0, 0x0 },
167 { 0x00005012, 0x0000009B, 0x0 },
168 { 0x00007011, 0x00000088, 0x0 },
d7097cff 169 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 170 { 0x00002016, 0x0000009B, 0x0 },
171 { 0x00005012, 0x00000088, 0x0 },
d7097cff 172 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 173 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 174 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 175};
176
f8896f5d
DW		 177/* Skylake U */
178static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 179 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 180 { 0x00005012, 0x00000088, 0x0 },
5ac90567 181 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 182 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 183 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 184 { 0x80005012, 0x000000C0, 0x1 },
185 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 186 { 0x00002016, 0x00000088, 0x0 },
d7097cff 187 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 188};
189
5f8b2531
RV		 190/* Skylake Y */
191static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 192 { 0x00000018, 0x000000A2, 0x0 },
193 { 0x00005012, 0x00000088, 0x0 },
5ac90567 194 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 195 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 196 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 197 { 0x80005012, 0x000000C0, 0x3 },
198 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 199 { 0x00000018, 0x00000088, 0x0 },
d7097cff 200 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 201};
202
0fdd4918
RV		 203/* Kabylake H and S */
204static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
205 { 0x00002016, 0x000000A0, 0x0 },
206 { 0x00005012, 0x0000009B, 0x0 },
207 { 0x00007011, 0x00000088, 0x0 },
208 { 0x80009010, 0x000000C0, 0x1 },
209 { 0x00002016, 0x0000009B, 0x0 },
210 { 0x00005012, 0x00000088, 0x0 },
211 { 0x80007011, 0x000000C0, 0x1 },
212 { 0x00002016, 0x00000097, 0x0 },
213 { 0x80005012, 0x000000C0, 0x1 },
214};
215
216/* Kabylake U */
217static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
218 { 0x0000201B, 0x000000A1, 0x0 },
219 { 0x00005012, 0x00000088, 0x0 },
220 { 0x80007011, 0x000000CD, 0x3 },
221 { 0x80009010, 0x000000C0, 0x3 },
222 { 0x0000201B, 0x0000009D, 0x0 },
223 { 0x80005012, 0x000000C0, 0x3 },
224 { 0x80007011, 0x000000C0, 0x3 },
225 { 0x00002016, 0x0000004F, 0x0 },
226 { 0x80005012, 0x000000C0, 0x3 },
227};
228
229/* Kabylake Y */
230static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
231 { 0x00001017, 0x000000A1, 0x0 },
232 { 0x00005012, 0x00000088, 0x0 },
233 { 0x80007011, 0x000000CD, 0x3 },
234 { 0x8000800F, 0x000000C0, 0x3 },
235 { 0x00001017, 0x0000009D, 0x0 },
236 { 0x80005012, 0x000000C0, 0x3 },
237 { 0x80007011, 0x000000C0, 0x3 },
238 { 0x00001017, 0x0000004C, 0x0 },
239 { 0x80005012, 0x000000C0, 0x3 },
240};
241
f8896f5d 242/*
0fdd4918 243 * Skylake/Kabylake H and S
f8896f5d
DW		 244 * eDP 1.4 low vswing translation parameters
245 */
7ad14a29 246static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 247 { 0x00000018, 0x000000A8, 0x0 },
248 { 0x00004013, 0x000000A9, 0x0 },
249 { 0x00007011, 0x000000A2, 0x0 },
250 { 0x00009010, 0x0000009C, 0x0 },
251 { 0x00000018, 0x000000A9, 0x0 },
252 { 0x00006013, 0x000000A2, 0x0 },
253 { 0x00007011, 0x000000A6, 0x0 },
254 { 0x00000018, 0x000000AB, 0x0 },
255 { 0x00007013, 0x0000009F, 0x0 },
256 { 0x00000018, 0x000000DF, 0x0 },
257};
258
259/*
0fdd4918 260 * Skylake/Kabylake U
f8896f5d
DW		 261 * eDP 1.4 low vswing translation parameters
262 */
263static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
264 { 0x00000018, 0x000000A8, 0x0 },
265 { 0x00004013, 0x000000A9, 0x0 },
266 { 0x00007011, 0x000000A2, 0x0 },
267 { 0x00009010, 0x0000009C, 0x0 },
268 { 0x00000018, 0x000000A9, 0x0 },
269 { 0x00006013, 0x000000A2, 0x0 },
270 { 0x00007011, 0x000000A6, 0x0 },
271 { 0x00002016, 0x000000AB, 0x0 },
272 { 0x00005013, 0x0000009F, 0x0 },
273 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 274};
275
f8896f5d 276/*
0fdd4918 277 * Skylake/Kabylake Y
f8896f5d
DW		 278 * eDP 1.4 low vswing translation parameters
279 */
5f8b2531 280static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 281 { 0x00000018, 0x000000A8, 0x0 },
282 { 0x00004013, 0x000000AB, 0x0 },
283 { 0x00007011, 0x000000A4, 0x0 },
284 { 0x00009010, 0x000000DF, 0x0 },
285 { 0x00000018, 0x000000AA, 0x0 },
286 { 0x00006013, 0x000000A4, 0x0 },
287 { 0x00007011, 0x0000009D, 0x0 },
288 { 0x00000018, 0x000000A0, 0x0 },
289 { 0x00006012, 0x000000DF, 0x0 },
290 { 0x00000018, 0x0000008A, 0x0 },
291};
7ad14a29 292
0fdd4918 293/* Skylake/Kabylake U, H and S */
7f88e3af 294static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 295 { 0x00000018, 0x000000AC, 0x0 },
296 { 0x00005012, 0x0000009D, 0x0 },
297 { 0x00007011, 0x00000088, 0x0 },
298 { 0x00000018, 0x000000A1, 0x0 },
299 { 0x00000018, 0x00000098, 0x0 },
300 { 0x00004013, 0x00000088, 0x0 },
2e78416e 301 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 302 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 303 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
304 { 0x80003015, 0x000000C0, 0x1 },
305 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 306};
307
0fdd4918 308/* Skylake/Kabylake Y */
5f8b2531 309static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 310 { 0x00000018, 0x000000A1, 0x0 },
311 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 312 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 313 { 0x00000018, 0x000000A4, 0x0 },
314 { 0x00000018, 0x0000009D, 0x0 },
315 { 0x00004013, 0x00000080, 0x0 },
2e78416e 316 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 317 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 318 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
319 { 0x80003015, 0x000000C0, 0x3 },
320 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 321};
322
96fb9f9b 323struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 324 u8 margin; /* swing value */
325 u8 scale; /* scale value */
326 u8 enable; /* scale enable */
327 u8 deemphasis;
96fb9f9b
VK		 328};
329
96fb9f9b
VK		 330static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
331 /* Idx NT mV diff db */
043eaf36
VS		 332 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
333 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
334 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
335 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
336 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
337 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
338 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
339 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
340 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
341 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 342};
343
d9d7000d
SJ		 344static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
345 /* Idx NT mV diff db */
043eaf36
VS		 346 { 26, 0, 0, 128, }, /* 0: 200 0 */
347 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
348 { 48, 0, 0, 96, }, /* 2: 200 4 */
349 { 54, 0, 0, 69, }, /* 3: 200 6 */
350 { 32, 0, 0, 128, }, /* 4: 250 0 */
351 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
352 { 54, 0, 0, 85, }, /* 6: 250 4 */
353 { 43, 0, 0, 128, }, /* 7: 300 0 */
354 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
355 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 356};
357
96fb9f9b
VK		 358/* BSpec has 2 recommended values - entries 0 and 8.
359 * Using the entry with higher vswing.
360 */
361static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
362 /* Idx NT mV diff db */
043eaf36
VS		 363 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
364 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
365 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
366 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
367 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
368 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
369 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
370 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
371 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
372 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 373};
374
83fb7ab4 375struct cnl_ddi_buf_trans {
fb5f4e96
VS		 376 u8 dw2_swing_sel;
377 u8 dw7_n_scalar;
378 u8 dw4_cursor_coeff;
379 u8 dw4_post_cursor_2;
380 u8 dw4_post_cursor_1;
83fb7ab4
RV		 381};
382
383/* Voltage Swing Programming for VccIO 0.85V for DP */
384static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
385 /* NT mV Trans mV db */
386 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
387 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
388 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
389 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
390 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
391 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
392 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
393 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
394 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
395 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
396};
397
398/* Voltage Swing Programming for VccIO 0.85V for HDMI */
399static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
400 /* NT mV Trans mV db */
401 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
402 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
403 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
404 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
405 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
406 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
407 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
408};
409
410/* Voltage Swing Programming for VccIO 0.85V for eDP */
411static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
412 /* NT mV Trans mV db */
413 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
414 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
415 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
416 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
417 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
418 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
419 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
420 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
421 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
422};
423
424/* Voltage Swing Programming for VccIO 0.95V for DP */
425static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
426 /* NT mV Trans mV db */
427 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
428 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
429 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
430 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
431 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
432 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
433 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
434 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
435 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
436 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
437};
438
439/* Voltage Swing Programming for VccIO 0.95V for HDMI */
440static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
441 /* NT mV Trans mV db */
442 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
443 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
444 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
445 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
446 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
447 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
448 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
449 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
450 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
451 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
452 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
453};
454
455/* Voltage Swing Programming for VccIO 0.95V for eDP */
456static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
457 /* NT mV Trans mV db */
458 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
459 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
461 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
462 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
463 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
464 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
465 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
466 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
467 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
468};
469
470/* Voltage Swing Programming for VccIO 1.05V for DP */
471static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
472 /* NT mV Trans mV db */
473 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
474 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
475 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
476 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
477 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
478 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
479 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
480 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
481 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
483};
484
485/* Voltage Swing Programming for VccIO 1.05V for HDMI */
486static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
487 /* NT mV Trans mV db */
488 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
489 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
490 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
491 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
492 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
493 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
494 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
495 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
496 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
497 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
498 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
499};
500
501/* Voltage Swing Programming for VccIO 1.05V for eDP */
502static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
503 /* NT mV Trans mV db */
504 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
505 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
506 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
507 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
508 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
509 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
510 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
511 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
512 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
513};
514
b265a2a6
CT		 515/* icl_combo_phy_ddi_translations */
516static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
517 /* NT mV Trans mV db */
518 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
519 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
520 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
521 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
522 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
523 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
524 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
525 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
526 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
527 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 528};
529
b265a2a6
CT		 530static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
531 /* NT mV Trans mV db */
532 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
533 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
534 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
535 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
536 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
537 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
538 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
539 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
540 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
541 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 542};
543
b265a2a6
CT		 544static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
545 /* NT mV Trans mV db */
546 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
547 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
548 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
549 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
550 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
551 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
552 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
553 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
554 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
555 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 556};
557
b265a2a6
CT		 558static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
559 /* NT mV Trans mV db */
560 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
561 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
562 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
563 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
564 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
565 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
566 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 567};
568
cd96bea7
MN		 569struct icl_mg_phy_ddi_buf_trans {
570 u32 cri_txdeemph_override_5_0;
571 u32 cri_txdeemph_override_11_6;
572 u32 cri_txdeemph_override_17_12;
573};
574
575static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
576 /* Voltage swing pre-emphasis */
577 { 0x0, 0x1B, 0x00 }, /* 0 0 */
578 { 0x0, 0x23, 0x08 }, /* 0 1 */
579 { 0x0, 0x2D, 0x12 }, /* 0 2 */
580 { 0x0, 0x00, 0x00 }, /* 0 3 */
581 { 0x0, 0x23, 0x00 }, /* 1 0 */
582 { 0x0, 0x2B, 0x09 }, /* 1 1 */
583 { 0x0, 0x2E, 0x11 }, /* 1 2 */
584 { 0x0, 0x2F, 0x00 }, /* 2 0 */
585 { 0x0, 0x33, 0x0C }, /* 2 1 */
586 { 0x0, 0x00, 0x00 }, /* 3 0 */
587};
588
a930acd9
VS		 589static const struct ddi_buf_trans *
590bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
591{
592 if (dev_priv->vbt.edp.low_vswing) {
593 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
594 return bdw_ddi_translations_edp;
595 } else {
596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 return bdw_ddi_translations_dp;
598 }
599}
600
acee2998 601static const struct ddi_buf_trans *
78ab0bae 602skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 603{
0fdd4918 604 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 605 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 606 return skl_y_ddi_translations_dp;
0fdd4918 607 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 608 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 609 return skl_u_ddi_translations_dp;
f8896f5d 610 } else {
f8896f5d 611 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 612 return skl_ddi_translations_dp;
f8896f5d 613 }
f8896f5d
DW		 614}
615
0fdd4918
RV		 616static const struct ddi_buf_trans *
617kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
618{
6ce1c33d 619 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
0fdd4918
RV		 620 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
621 return kbl_y_ddi_translations_dp;
da411a48 622 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 623 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
624 return kbl_u_ddi_translations_dp;
625 } else {
626 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
627 return kbl_ddi_translations_dp;
628 }
629}
630
acee2998 631static const struct ddi_buf_trans *
78ab0bae 632skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 633{
06411f08 634 if (dev_priv->vbt.edp.low_vswing) {
6ce1c33d
VS		 635 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
636 IS_CFL_ULX(dev_priv)) {
5f8b2531 637 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 638 return skl_y_ddi_translations_edp;
da411a48
RV		 639 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
640 IS_CFL_ULT(dev_priv)) {
f8896f5d 641 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 642 return skl_u_ddi_translations_edp;
f8896f5d 643 } else {
f8896f5d 644 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 645 return skl_ddi_translations_edp;
f8896f5d
DW		 646 }
647 }
cd1101cb 648
da411a48 649 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 650 return kbl_get_buf_trans_dp(dev_priv, n_entries);
651 else
652 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 653}
654
655static const struct ddi_buf_trans *
78ab0bae 656skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 657{
6ce1c33d
VS		 658 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
659 IS_CFL_ULX(dev_priv)) {
5f8b2531 660 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 661 return skl_y_ddi_translations_hdmi;
f8896f5d 662 } else {
f8896f5d 663 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 664 return skl_ddi_translations_hdmi;
f8896f5d 665 }
f8896f5d
DW		 666}
667
edba48fd
VS		 668static int skl_buf_trans_num_entries(enum port port, int n_entries)
669{
670 /* Only DDIA and DDIE can select the 10th register with DP */
671 if (port == PORT_A || port == PORT_E)
672 return min(n_entries, 10);
673 else
674 return min(n_entries, 9);
675}
676
d8fe2c7f
VS		 677static const struct ddi_buf_trans *
678intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 679 enum port port, int *n_entries)
d8fe2c7f
VS		 680{
681 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 682 const struct ddi_buf_trans *ddi_translations =
683 kbl_get_buf_trans_dp(dev_priv, n_entries);
684 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
685 return ddi_translations;
d8fe2c7f 686 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 687 const struct ddi_buf_trans *ddi_translations =
688 skl_get_buf_trans_dp(dev_priv, n_entries);
689 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
690 return ddi_translations;
d8fe2c7f
VS		 691 } else if (IS_BROADWELL(dev_priv)) {
692 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
693 return bdw_ddi_translations_dp;
694 } else if (IS_HASWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 return hsw_ddi_translations_dp;
697 }
698
699 *n_entries = 0;
700 return NULL;
701}
702
703static const struct ddi_buf_trans *
704intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 705 enum port port, int *n_entries)
d8fe2c7f
VS		 706{
707 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 708 const struct ddi_buf_trans *ddi_translations =
709 skl_get_buf_trans_edp(dev_priv, n_entries);
710 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
711 return ddi_translations;
d8fe2c7f
VS		 712 } else if (IS_BROADWELL(dev_priv)) {
713 return bdw_get_buf_trans_edp(dev_priv, n_entries);
714 } else if (IS_HASWELL(dev_priv)) {
715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
716 return hsw_ddi_translations_dp;
717 }
718
719 *n_entries = 0;
720 return NULL;
721}
722
723static const struct ddi_buf_trans *
724intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
725 int *n_entries)
726{
727 if (IS_BROADWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
729 return bdw_ddi_translations_fdi;
730 } else if (IS_HASWELL(dev_priv)) {
731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 return hsw_ddi_translations_fdi;
733 }
734
735 *n_entries = 0;
736 return NULL;
737}
738
975786ee
VS		 739static const struct ddi_buf_trans *
740intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
741 int *n_entries)
742{
743 if (IS_GEN9_BC(dev_priv)) {
744 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
745 } else if (IS_BROADWELL(dev_priv)) {
746 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
747 return bdw_ddi_translations_hdmi;
748 } else if (IS_HASWELL(dev_priv)) {
749 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
750 return hsw_ddi_translations_hdmi;
751 }
752
753 *n_entries = 0;
754 return NULL;
755}
756
7d4f37b5
VS		 757static const struct bxt_ddi_buf_trans *
758bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
759{
760 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
761 return bxt_ddi_translations_dp;
762}
763
764static const struct bxt_ddi_buf_trans *
765bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
766{
767 if (dev_priv->vbt.edp.low_vswing) {
768 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
769 return bxt_ddi_translations_edp;
770 }
771
772 return bxt_get_buf_trans_dp(dev_priv, n_entries);
773}
774
775static const struct bxt_ddi_buf_trans *
776bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
777{
778 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
779 return bxt_ddi_translations_hdmi;
780}
781
cf3e0fb4
RV		 782static const struct cnl_ddi_buf_trans *
783cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
784{
785 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
786
787 if (voltage == VOLTAGE_INFO_0_85V) {
788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
789 return cnl_ddi_translations_hdmi_0_85V;
790 } else if (voltage == VOLTAGE_INFO_0_95V) {
791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
792 return cnl_ddi_translations_hdmi_0_95V;
793 } else if (voltage == VOLTAGE_INFO_1_05V) {
794 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
795 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 796 } else {
797 *n_entries = 1; /* shut up gcc */
cf3e0fb4 798 MISSING_CASE(voltage);
83482ca3 799 }
cf3e0fb4
RV		 800 return NULL;
801}
802
803static const struct cnl_ddi_buf_trans *
804cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
805{
806 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
807
808 if (voltage == VOLTAGE_INFO_0_85V) {
809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
810 return cnl_ddi_translations_dp_0_85V;
811 } else if (voltage == VOLTAGE_INFO_0_95V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
813 return cnl_ddi_translations_dp_0_95V;
814 } else if (voltage == VOLTAGE_INFO_1_05V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
816 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 817 } else {
818 *n_entries = 1; /* shut up gcc */
cf3e0fb4 819 MISSING_CASE(voltage);
83482ca3 820 }
cf3e0fb4
RV		 821 return NULL;
822}
823
824static const struct cnl_ddi_buf_trans *
825cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
826{
827 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
828
829 if (dev_priv->vbt.edp.low_vswing) {
830 if (voltage == VOLTAGE_INFO_0_85V) {
831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
832 return cnl_ddi_translations_edp_0_85V;
833 } else if (voltage == VOLTAGE_INFO_0_95V) {
834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
835 return cnl_ddi_translations_edp_0_95V;
836 } else if (voltage == VOLTAGE_INFO_1_05V) {
837 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
838 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 839 } else {
840 *n_entries = 1; /* shut up gcc */
cf3e0fb4 841 MISSING_CASE(voltage);
83482ca3 842 }
cf3e0fb4
RV		 843 return NULL;
844 } else {
845 return cnl_get_buf_trans_dp(dev_priv, n_entries);
846 }
847}
848
b265a2a6 849static const struct cnl_ddi_buf_trans *
4a8134d5
MR		 850icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
851 int *n_entries)
fb5c8e9d 852{
b265a2a6
CT		 853 if (type == INTEL_OUTPUT_HDMI) {
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
855 return icl_combo_phy_ddi_translations_hdmi;
856 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
858 return icl_combo_phy_ddi_translations_edp_hbr3;
859 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
860 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
861 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 862 }
b265a2a6
CT		 863
864 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
865 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 866}
867
8d8bb85e
VS		 868static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
869{
d02ace87 870 int n_entries, level, default_entry;
d8fe2ab6 871 enum phy phy = intel_port_to_phy(dev_priv, port);
8d8bb85e 872
d02ace87 873 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 874
2dd24a9c 875 if (INTEL_GEN(dev_priv) >= 11) {
d8fe2ab6 876 if (intel_phy_is_combo(dev_priv, phy))
4a8134d5 877 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
b265a2a6 878 0, &n_entries);
dccc7228
MN		 879 else
880 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
881 default_entry = n_entries - 1;
882 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 883 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
884 default_entry = n_entries - 1;
043eaf36 885 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 886 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
887 default_entry = n_entries - 1;
bf503556 888 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 889 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
890 default_entry = 8;
8d8bb85e 891 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 892 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
893 default_entry = 7;
8d8bb85e 894 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 895 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
896 default_entry = 6;
8d8bb85e
VS		 897 } else {
898 WARN(1, "ddi translation table missing\n");
975786ee 899 return 0;
8d8bb85e
VS		 900 }
901
902 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 903 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
904 level = default_entry;
8d8bb85e 905
d02ace87 906 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 907 return 0;
d02ace87
VS		 908 if (WARN_ON_ONCE(level >= n_entries))
909 level = n_entries - 1;
21b39d2a 910
d02ace87 911 return level;
8d8bb85e
VS		 912}
913
e58623cb
AR		 914/*
915 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 916 * values in advance. This function programs the correct values for
917 * DP/eDP/FDI use cases.
45244b87 918 */
3a6d84e6
VS		 919static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
920 const struct intel_crtc_state *crtc_state)
45244b87 921{
6a7e4f99 922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 923 u32 iboost_bit = 0;
7d1c42e6 924 int i, n_entries;
0fce04c8 925 enum port port = encoder->port;
10122051 926 const struct ddi_buf_trans *ddi_translations;
e58623cb 927
3a6d84e6
VS		 928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
929 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
930 &n_entries);
931 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 932 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 933 &n_entries);
3a6d84e6 934 else
edba48fd 935 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 936 &n_entries);
e58623cb 937
edba48fd
VS		 938 /* If we're boosting the current, set bit 31 of trans1 */
939 if (IS_GEN9_BC(dev_priv) &&
940 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
941 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 942
7d1c42e6 943 for (i = 0; i < n_entries; i++) {
9712e688
VS		 944 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
945 ddi_translations[i].trans1 | iboost_bit);
946 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
947 ddi_translations[i].trans2);
45244b87 948 }
32bdc400
VS		 949}
950
951/*
952 * Starting with Haswell, DDI port buffers must be programmed with correct
953 * values in advance. This function programs the correct values for
954 * HDMI/DVI use cases.
955 */
7ea79333 956static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 957 int level)
32bdc400
VS		 958{
959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
960 u32 iboost_bit = 0;
d02ace87 961 int n_entries;
0fce04c8 962 enum port port = encoder->port;
d02ace87 963 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 964
d02ace87 965 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 966
d02ace87 967 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 968 return;
d02ace87
VS		 969 if (WARN_ON_ONCE(level >= n_entries))
970 level = n_entries - 1;
21b39d2a 971
975786ee
VS		 972 /* If we're boosting the current, set bit 31 of trans1 */
973 if (IS_GEN9_BC(dev_priv) &&
974 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
975 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 976
6acab15a 977 /* Entry 9 is for HDMI: */
ed9c77d2 978 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 979 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 980 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 981 ddi_translations[level].trans2);
45244b87
ED		 982}
983
248138b5
PZ		 984static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
985 enum port port)
986{
f0f59a00 987 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 988 int i;
989
3449ca85 990 for (i = 0; i < 16; i++) {
248138b5
PZ		 991 udelay(1);
992 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
993 return;
994 }
995 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
996}
c82e4d26 997
3d0c5005 998static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 999{
0823eb9c 1000 switch (pll->info->id) {
c856052a
ACO		 1001 case DPLL_ID_WRPLL1:
1002 return PORT_CLK_SEL_WRPLL1;
1003 case DPLL_ID_WRPLL2:
1004 return PORT_CLK_SEL_WRPLL2;
1005 case DPLL_ID_SPLL:
1006 return PORT_CLK_SEL_SPLL;
1007 case DPLL_ID_LCPLL_810:
1008 return PORT_CLK_SEL_LCPLL_810;
1009 case DPLL_ID_LCPLL_1350:
1010 return PORT_CLK_SEL_LCPLL_1350;
1011 case DPLL_ID_LCPLL_2700:
1012 return PORT_CLK_SEL_LCPLL_2700;
1013 default:
0823eb9c 1014 MISSING_CASE(pll->info->id);
c856052a
ACO		 1015 return PORT_CLK_SEL_NONE;
1016 }
1017}
1018
20fd2ab7 1019static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1020 const struct intel_crtc_state *crtc_state)
c27e917e 1021{
0e5fa646
ML		 1022 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1023 int clock = crtc_state->port_clock;
c27e917e
PZ		 1024 const enum intel_dpll_id id = pll->info->id;
1025
1026 switch (id) {
1027 default:
20fd2ab7
LDM		 1028 /*
1029 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1030 * here, so do warn if this get passed in
1031 */
c27e917e 1032 MISSING_CASE(id);
c27e917e 1033 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1034 case DPLL_ID_ICL_TBTPLL:
1035 switch (clock) {
1036 case 162000:
1037 return DDI_CLK_SEL_TBT_162;
1038 case 270000:
1039 return DDI_CLK_SEL_TBT_270;
1040 case 540000:
1041 return DDI_CLK_SEL_TBT_540;
1042 case 810000:
1043 return DDI_CLK_SEL_TBT_810;
1044 default:
1045 MISSING_CASE(clock);
7a61a6de 1046 return DDI_CLK_SEL_NONE;
1fa11ee2 1047 }
c27e917e
PZ		 1048 case DPLL_ID_ICL_MGPLL1:
1049 case DPLL_ID_ICL_MGPLL2:
1050 case DPLL_ID_ICL_MGPLL3:
1051 case DPLL_ID_ICL_MGPLL4:
1052 return DDI_CLK_SEL_MG;
1053 }
1054}
1055
c82e4d26
ED		 1056/* Starting with Haswell, different DDI ports can work in FDI mode for
1057 * connection to the PCH-located connectors. For this, it is necessary to train
1058 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1059 *
1060 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1061 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1062 * DDI A (which is used for eDP)
1063 */
1064
dc4a1094
ACO		 1065void hsw_fdi_link_train(struct intel_crtc *crtc,
1066 const struct intel_crtc_state *crtc_state)
c82e4d26 1067{
4cbe4b2b 1068 struct drm_device *dev = crtc->base.dev;
fac5e23e 1069 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1070 struct intel_encoder *encoder;
c856052a 1071 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1072
4cbe4b2b 1073 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1074 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1075 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1076 }
1077
04945641
PZ		 1078 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1079 * mode set "sequence for CRT port" document:
1080 * - TP1 to TP2 time with the default value
1081 * - FDI delay to 90h
8693a824
DL		 1082 *
1083 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1084 */
eede3b53 1085 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1086 FDI_RX_PWRDN_LANE0_VAL(2) |
1087 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1088
1089 /* Enable the PCH Receiver FDI PLL */
3e68320e 1090 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1091 FDI_RX_PLL_ENABLE |
dc4a1094 1092 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1094 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1095 udelay(220);
1096
1097 /* Switch from Rawclk to PCDclk */
1098 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1100
1101 /* Configure Port Clock Select */
dc4a1094 1102 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1103 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1104 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1105
1106 /* Start the training iterating through available voltages and emphasis,
1107 * testing each value twice. */
10122051 1108 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1109 /* Configure DP_TP_CTL with auto-training */
1110 I915_WRITE(DP_TP_CTL(PORT_E),
1111 DP_TP_CTL_FDI_AUTOTRAIN |
1112 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1113 DP_TP_CTL_LINK_TRAIN_PAT1 |
1114 DP_TP_CTL_ENABLE);
1115
876a8cdf
DL		 1116 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1117 * DDI E does not support port reversal, the functionality is
1118 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1119 * port reversal bit */
c82e4d26 1120 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1121 DDI_BUF_CTL_ENABLE |
dc4a1094 1122 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1123 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1124 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1125
1126 udelay(600);
1127
04945641 1128 /* Program PCH FDI Receiver TU */
eede3b53 1129 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1130
1131 /* Enable PCH FDI Receiver with auto-training */
1132 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1133 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1134 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1135
1136 /* Wait for FDI receiver lane calibration */
1137 udelay(30);
1138
1139 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1140 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1141 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1142 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1143 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1144
1145 /* Wait for FDI auto training time */
1146 udelay(5);
c82e4d26
ED		 1147
1148 temp = I915_READ(DP_TP_STATUS(PORT_E));
1149 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1150 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1151 break;
1152 }
c82e4d26 1153
a308ccb3
VS		 1154 /*
1155 * Leave things enabled even if we failed to train FDI.
1156 * Results in less fireworks from the state checker.
1157 */
1158 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1159 DRM_ERROR("FDI link training failed!\n");
1160 break;
c82e4d26 1161 }
04945641 1162
5b421c57
VS		 1163 rx_ctl_val &= ~FDI_RX_ENABLE;
1164 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1165 POSTING_READ(FDI_RX_CTL(PIPE_A));
1166
248138b5
PZ		 1167 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1168 temp &= ~DDI_BUF_CTL_ENABLE;
1169 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1170 POSTING_READ(DDI_BUF_CTL(PORT_E));
1171
04945641 1172 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1173 temp = I915_READ(DP_TP_CTL(PORT_E));
1174 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1175 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1176 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1177 POSTING_READ(DP_TP_CTL(PORT_E));
1178
1179 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1180
04945641 1181 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1185 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1186 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1187 }
1188
a308ccb3
VS		 1189 /* Enable normal pixel sending for FDI */
1190 I915_WRITE(DP_TP_CTL(PORT_E),
1191 DP_TP_CTL_FDI_AUTOTRAIN |
1192 DP_TP_CTL_LINK_TRAIN_NORMAL |
1193 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1194 DP_TP_CTL_ENABLE);
c82e4d26 1195}
0e72a5b5 1196
d7c530b2 1197static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1198{
1199 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1200 struct intel_digital_port *intel_dig_port =
1201 enc_to_dig_port(&encoder->base);
1202
1203 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1204 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1205 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1206}
1207
8d9ddbcb 1208static struct intel_encoder *
e9ce1a62 1209intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1210{
e9ce1a62 1211 struct drm_device *dev = crtc->base.dev;
1524e93e 1212 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1213 int num_encoders = 0;
1214
1524e93e
SS		 1215 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1216 ret = encoder;
8d9ddbcb
PZ		 1217 num_encoders++;
1218 }
1219
1220 if (num_encoders != 1)
84f44ce7 1221 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1222 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1223
1224 BUG_ON(ret == NULL);
1225 return ret;
1226}
1227
f0f59a00
VS		 1228static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1229 i915_reg_t reg)
11578553 1230{
0f52c097 1231 int refclk;
11578553
JB		 1232 int n, p, r;
1233 u32 wrpll;
1234
1235 wrpll = I915_READ(reg);
4a95e36f
VS		 1236 switch (wrpll & WRPLL_REF_MASK) {
1237 case WRPLL_REF_SPECIAL_HSW:
86761789
VS		 1238 /*
1239 * muxed-SSC for BDW.
1240 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1241 * for the non-SSC reference frequency.
1242 */
1243 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1244 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1245 refclk = 24;
1246 else
1247 refclk = 135;
1248 break;
1249 }
1250 /* fall through */
4a95e36f 1251 case WRPLL_REF_PCH_SSC:
11578553
JB		 1252 /*
1253 * We could calculate spread here, but our checking
1254 * code only cares about 5% accuracy, and spread is a max of
1255 * 0.5% downspread.
1256 */
1257 refclk = 135;
1258 break;
4a95e36f 1259 case WRPLL_REF_LCPLL:
0f52c097 1260 refclk = 2700;
11578553
JB		 1261 break;
1262 default:
86761789 1263 MISSING_CASE(wrpll);
11578553
JB		 1264 return 0;
1265 }
1266
1267 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1268 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1269 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1270
20f0ec16
JB		 1271 /* Convert to KHz, p & r have a fixed point portion */
1272 return (refclk * n * 100) / (p * r);
11578553
JB		 1273}
1274
947f4417 1275static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1276{
3d0c5005 1277 u32 p0, p1, p2, dco_freq;
540e732c 1278
947f4417
LDM		 1279 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1280 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1281
947f4417
LDM		 1282 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1283 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1284 else
1285 p1 = 1;
1286
1287
1288 switch (p0) {
1289 case DPLL_CFGCR2_PDIV_1:
1290 p0 = 1;
1291 break;
1292 case DPLL_CFGCR2_PDIV_2:
1293 p0 = 2;
1294 break;
1295 case DPLL_CFGCR2_PDIV_3:
1296 p0 = 3;
1297 break;
1298 case DPLL_CFGCR2_PDIV_7:
1299 p0 = 7;
1300 break;
1301 }
1302
1303 switch (p2) {
1304 case DPLL_CFGCR2_KDIV_5:
1305 p2 = 5;
1306 break;
1307 case DPLL_CFGCR2_KDIV_2:
1308 p2 = 2;
1309 break;
1310 case DPLL_CFGCR2_KDIV_3:
1311 p2 = 3;
1312 break;
1313 case DPLL_CFGCR2_KDIV_1:
1314 p2 = 1;
1315 break;
1316 }
1317
947f4417
LDM		 1318 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1319 * 24 * 1000;
540e732c 1320
947f4417
LDM		 1321 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1322 * 24 * 1000) / 0x8000;
540e732c 1323
b8449c43
YX		 1324 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1325 return 0;
1326
540e732c
S		 1327 return dco_freq / (p0 * p1 * p2 * 5);
1328}
1329
8327af28 1330int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1331 struct intel_dpll_hw_state *pll_state)
a9701a89 1332{
3d0c5005 1333 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1334
5e65216d
LDM		 1335 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1336 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1337
5e65216d
LDM		 1338 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1339 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1340 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1341 else
1342 p1 = 1;
1343
1344
1345 switch (p0) {
1346 case DPLL_CFGCR1_PDIV_2:
1347 p0 = 2;
1348 break;
1349 case DPLL_CFGCR1_PDIV_3:
1350 p0 = 3;
1351 break;
1352 case DPLL_CFGCR1_PDIV_5:
1353 p0 = 5;
1354 break;
1355 case DPLL_CFGCR1_PDIV_7:
1356 p0 = 7;
1357 break;
1358 }
1359
1360 switch (p2) {
1361 case DPLL_CFGCR1_KDIV_1:
1362 p2 = 1;
1363 break;
1364 case DPLL_CFGCR1_KDIV_2:
1365 p2 = 2;
1366 break;
2ee7fd1e
VS		 1367 case DPLL_CFGCR1_KDIV_3:
1368 p2 = 3;
a9701a89
RV		 1369 break;
1370 }
1371
9f9d594d 1372 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1373
5e65216d
LDM		 1374 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1375 * ref_clock;
a9701a89 1376
5e65216d 1377 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1378 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1379
0e005888
PZ		 1380 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1381 return 0;
1382
a9701a89
RV		 1383 return dco_freq / (p0 * p1 * p2 * 5);
1384}
1385
7b19f544
MN		 1386static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1387 enum port port)
1388{
1389 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1390
1391 switch (val) {
1392 case DDI_CLK_SEL_NONE:
1393 return 0;
1394 case DDI_CLK_SEL_TBT_162:
1395 return 162000;
1396 case DDI_CLK_SEL_TBT_270:
1397 return 270000;
1398 case DDI_CLK_SEL_TBT_540:
1399 return 540000;
1400 case DDI_CLK_SEL_TBT_810:
1401 return 810000;
1402 default:
1403 MISSING_CASE(val);
1404 return 0;
1405 }
1406}
1407
1408static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1409 const struct intel_dpll_hw_state *pll_state)
7b19f544 1410{
02c99d26 1411 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1412 u64 tmp;
1413
02c99d26 1414 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1415
02c99d26
LDM		 1416 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1417 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1418 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1419 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1420 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1421
02c99d26
LDM		 1422 switch (pll_state->mg_clktop2_hsclkctl &
1423 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1424 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1425 div1 = 2;
1426 break;
1427 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1428 div1 = 3;
1429 break;
1430 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1431 div1 = 5;
1432 break;
1433 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1434 div1 = 7;
1435 break;
1436 default:
02c99d26 1437 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1438 return 0;
1439 }
1440
02c99d26
LDM		 1441 div2 = (pll_state->mg_clktop2_hsclkctl &
1442 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1443 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1444
7b19f544
MN		 1445 /* div2 value of 0 is same as 1 means no div */
1446 if (div2 == 0)
1447 div2 = 1;
1448
1449 /*
1450 * Adjust the original formula to delay the division by 2^22 in order to
1451 * minimize possible rounding errors.
1452 */
02c99d26
LDM		 1453 tmp = (u64)m1 * m2_int * ref_clock +
1454 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1455 tmp = div_u64(tmp, 5 * div1 * div2);
1456
1457 return tmp;
1458}
1459
398a017e
VS		 1460static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1461{
1462 int dotclock;
1463
1464 if (pipe_config->has_pch_encoder)
1465 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1466 &pipe_config->fdi_m_n);
37a5650b 1467 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1468 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1469 &pipe_config->dp_m_n);
2969a78a
ID		 1470 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1471 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
398a017e
VS		 1472 else
1473 dotclock = pipe_config->port_clock;
1474
16668f48
GM		 1475 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1476 !intel_crtc_has_dp_encoder(pipe_config))
b22ca995
SS		 1477 dotclock *= 2;
1478
398a017e
VS		 1479 if (pipe_config->pixel_multiplier)
1480 dotclock /= pipe_config->pixel_multiplier;
1481
1482 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1483}
540e732c 1484
51c83cfa
MN		 1485static void icl_ddi_clock_get(struct intel_encoder *encoder,
1486 struct intel_crtc_state *pipe_config)
1487{
1488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1489 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1490 enum port port = encoder->port;
d8fe2ab6 1491 enum phy phy = intel_port_to_phy(dev_priv, port);
5e65216d 1492 int link_clock;
51c83cfa 1493
d8fe2ab6 1494 if (intel_phy_is_combo(dev_priv, phy)) {
5e65216d 1495 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1496 } else {
077973c8
LDM		 1497 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1498 pipe_config->shared_dpll);
1499
7b19f544
MN		 1500 if (pll_id == DPLL_ID_ICL_TBTPLL)
1501 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1502 else
02c99d26 1503 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1504 }
1505
1506 pipe_config->port_clock = link_clock;
02c99d26 1507
51c83cfa
MN		 1508 ddi_dotclock_get(pipe_config);
1509}
1510
a9701a89
RV		 1511static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1512 struct intel_crtc_state *pipe_config)
1513{
1514 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1515 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1516 int link_clock;
a9701a89 1517
5e65216d
LDM		 1518 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1519 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1520 } else {
5e65216d 1521 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1522
1523 switch (link_clock) {
1524 case DPLL_CFGCR0_LINK_RATE_810:
1525 link_clock = 81000;
1526 break;
1527 case DPLL_CFGCR0_LINK_RATE_1080:
1528 link_clock = 108000;
1529 break;
1530 case DPLL_CFGCR0_LINK_RATE_1350:
1531 link_clock = 135000;
1532 break;
1533 case DPLL_CFGCR0_LINK_RATE_1620:
1534 link_clock = 162000;
1535 break;
1536 case DPLL_CFGCR0_LINK_RATE_2160:
1537 link_clock = 216000;
1538 break;
1539 case DPLL_CFGCR0_LINK_RATE_2700:
1540 link_clock = 270000;
1541 break;
1542 case DPLL_CFGCR0_LINK_RATE_3240:
1543 link_clock = 324000;
1544 break;
1545 case DPLL_CFGCR0_LINK_RATE_4050:
1546 link_clock = 405000;
1547 break;
1548 default:
1549 WARN(1, "Unsupported link rate\n");
1550 break;
1551 }
1552 link_clock *= 2;
1553 }
1554
1555 pipe_config->port_clock = link_clock;
1556
1557 ddi_dotclock_get(pipe_config);
1558}
1559
540e732c 1560static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1561 struct intel_crtc_state *pipe_config)
540e732c 1562{
947f4417
LDM		 1563 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1564 int link_clock;
540e732c 1565
947f4417
LDM		 1566 /*
1567 * ctrl1 register is already shifted for each pll, just use 0 to get
1568 * the internal shift for each field
1569 */
1570 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1571 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1572 } else {
947f4417
LDM		 1573 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1574 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1575
1576 switch (link_clock) {
71cd8423 1577 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1578 link_clock = 81000;
1579 break;
71cd8423 1580 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1581 link_clock = 108000;
1582 break;
71cd8423 1583 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1584 link_clock = 135000;
1585 break;
71cd8423 1586 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1587 link_clock = 162000;
1588 break;
71cd8423 1589 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1590 link_clock = 216000;
1591 break;
71cd8423 1592 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1593 link_clock = 270000;
1594 break;
1595 default:
1596 WARN(1, "Unsupported link rate\n");
1597 break;
1598 }
1599 link_clock *= 2;
1600 }
1601
1602 pipe_config->port_clock = link_clock;
1603
398a017e 1604 ddi_dotclock_get(pipe_config);
540e732c
S		 1605}
1606
3d51278a 1607static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1608 struct intel_crtc_state *pipe_config)
11578553 1609{
fac5e23e 1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1611 int link_clock = 0;
1612 u32 val, pll;
1613
c856052a 1614 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1615 switch (val & PORT_CLK_SEL_MASK) {
1616 case PORT_CLK_SEL_LCPLL_810:
1617 link_clock = 81000;
1618 break;
1619 case PORT_CLK_SEL_LCPLL_1350:
1620 link_clock = 135000;
1621 break;
1622 case PORT_CLK_SEL_LCPLL_2700:
1623 link_clock = 270000;
1624 break;
1625 case PORT_CLK_SEL_WRPLL1:
01403de3 1626 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1627 break;
1628 case PORT_CLK_SEL_WRPLL2:
01403de3 1629 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1630 break;
1631 case PORT_CLK_SEL_SPLL:
4a95e36f
VS		 1632 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1633 if (pll == SPLL_FREQ_810MHz)
11578553 1634 link_clock = 81000;
4a95e36f 1635 else if (pll == SPLL_FREQ_1350MHz)
11578553 1636 link_clock = 135000;
4a95e36f 1637 else if (pll == SPLL_FREQ_2700MHz)
11578553
JB		 1638 link_clock = 270000;
1639 else {
1640 WARN(1, "bad spll freq\n");
1641 return;
1642 }
1643 break;
1644 default:
1645 WARN(1, "bad port clock sel\n");
1646 return;
1647 }
1648
1649 pipe_config->port_clock = link_clock * 2;
1650
398a017e 1651 ddi_dotclock_get(pipe_config);
11578553
JB		 1652}
1653
47c9877e 1654static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1655{
9e2c8475 1656 struct dpll clock;
aa610dcb 1657
aa610dcb 1658 clock.m1 = 2;
47c9877e
LDM		 1659 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1660 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1661 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1662 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1663 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1664 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1665
1666 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1667}
1668
1669static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1670 struct intel_crtc_state *pipe_config)
977bb38d 1671{
47c9877e
LDM		 1672 pipe_config->port_clock =
1673 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1674
398a017e 1675 ddi_dotclock_get(pipe_config);
977bb38d
S		 1676}
1677
35686a44
VS		 1678static void intel_ddi_clock_get(struct intel_encoder *encoder,
1679 struct intel_crtc_state *pipe_config)
3d51278a 1680{
0853723b 1681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1682
2dd24a9c 1683 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1684 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1685 else if (IS_CANNONLAKE(dev_priv))
1686 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1687 else if (IS_GEN9_LP(dev_priv))
1688 bxt_ddi_clock_get(encoder, pipe_config);
1689 else if (IS_GEN9_BC(dev_priv))
1690 skl_ddi_clock_get(encoder, pipe_config);
1691 else if (INTEL_GEN(dev_priv) <= 8)
1692 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1693}
1694
3dc38eea 1695void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1696{
3dc38eea 1697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1699 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1700 u32 temp;
dae84799 1701
5448f53f
VS		 1702 if (!intel_crtc_has_dp_encoder(crtc_state))
1703 return;
4d1de975 1704
5448f53f
VS		 1705 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1706
1707 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1708
1709 if (crtc_state->limited_color_range)
1710 temp |= TRANS_MSA_CEA_RANGE;
1711
5448f53f
VS		 1712 switch (crtc_state->pipe_bpp) {
1713 case 18:
1714 temp |= TRANS_MSA_6_BPC;
1715 break;
1716 case 24:
1717 temp |= TRANS_MSA_8_BPC;
1718 break;
1719 case 30:
1720 temp |= TRANS_MSA_10_BPC;
1721 break;
1722 case 36:
1723 temp |= TRANS_MSA_12_BPC;
1724 break;
1725 default:
1726 MISSING_CASE(crtc_state->pipe_bpp);
1727 break;
dae84799 1728 }
5448f53f 1729
668b6c17
SS		 1730 /*
1731 * As per DP 1.2 spec section 2.3.4.3 while sending
1732 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1733 * colorspace information. The output colorspace encoding is BT601.
1734 */
1735 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1736 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
ec4401d3
GM		 1737 /*
1738 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1739 * of Color Encoding Format and Content Color Gamut] while sending
1740 * YCBCR 420 signals we should program MSA MISC1 fields which
1741 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1742 */
1743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1744 temp |= TRANS_MSA_USE_VSC_SDP;
5448f53f 1745 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1746}
1747
3dc38eea
ACO		 1748void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1749 bool state)
0e32b39c 1750{
3dc38eea 1751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1753 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1754 u32 temp;
7e732cac 1755
0e32b39c
DA		 1756 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1757 if (state == true)
1758 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1759 else
1760 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1761 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1762}
1763
99389390
JRS		 1764/*
1765 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1766 *
1767 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1768 * intel_ddi_config_transcoder_func().
1769 */
1770static u32
1771intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1772{
3dc38eea 1773 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1774 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1776 enum pipe pipe = crtc->pipe;
3dc38eea 1777 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1778 enum port port = encoder->port;
3d0c5005 1779 u32 temp;
8d9ddbcb 1780
ad80a810
PZ		 1781 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1782 temp = TRANS_DDI_FUNC_ENABLE;
df16b636
MK		 1783 if (INTEL_GEN(dev_priv) >= 12)
1784 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1785 else
1786 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1787
3dc38eea 1788 switch (crtc_state->pipe_bpp) {
dfcef252 1789 case 18:
ad80a810 1790 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1791 break;
1792 case 24:
ad80a810 1793 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1794 break;
1795 case 30:
ad80a810 1796 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1797 break;
1798 case 36:
ad80a810 1799 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1800 break;
1801 default:
4e53c2e0 1802 BUG();
dfcef252 1803 }
72662e10 1804
3dc38eea 1805 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1806 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1807 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1808 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1809
e6f0bfc4
PZ		 1810 if (cpu_transcoder == TRANSCODER_EDP) {
1811 switch (pipe) {
1812 case PIPE_A:
c7670b10
PZ		 1813 /* On Haswell, can only use the always-on power well for
1814 * eDP when not using the panel fitter, and when not
1815 * using motion blur mitigation (which we don't
1816 * support). */
dc0c0bfe 1817 if (crtc_state->pch_pfit.force_thru)
d6dd9eb1
DV		 1818 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1819 else
1820 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1821 break;
1822 case PIPE_B:
1823 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1824 break;
1825 case PIPE_C:
1826 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1827 break;
1828 default:
1829 BUG();
1830 break;
1831 }
1832 }
1833
742745f1 1834 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1835 if (crtc_state->has_hdmi_sink)
ad80a810 1836 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1837 else
ad80a810 1838 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1839
1840 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1841 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1842 if (crtc_state->hdmi_high_tmds_clock_ratio)
1843 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1844 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1845 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1846 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1847 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1848 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1849 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1850 } else {
742745f1
VS		 1851 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1852 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1853 }
1854
99389390
JRS		 1855 return temp;
1856}
1857
1858void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1859{
1860 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1861 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1862 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1863 u32 temp;
1864
1865 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1866 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1867}
1868
1869/*
1870 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1871 * bit.
1872 */
1873static void
1874intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1875{
1876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1878 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1879 u32 temp;
1880
1881 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1882 temp &= ~TRANS_DDI_FUNC_ENABLE;
ad80a810 1883 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1884}
72662e10 1885
90c3e219 1886void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1887{
90c3e219
CT		 1888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1890 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1891 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1892 u32 val = I915_READ(reg);
8d9ddbcb 1893
df16b636
MK		 1894 if (INTEL_GEN(dev_priv) >= 12) {
1895 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1896 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1897 } else {
1898 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1899 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1900 }
8d9ddbcb 1901 I915_WRITE(reg, val);
90c3e219
CT		 1902
1903 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1904 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1905 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1906 /* Quirk time at 100ms for reliable operation */
1907 msleep(100);
1908 }
72662e10
ED		 1909}
1910
2320175f
SP		 1911int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1912 bool enable)
1913{
1914 struct drm_device *dev = intel_encoder->base.dev;
1915 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1916 intel_wakeref_t wakeref;
2320175f
SP		 1917 enum pipe pipe = 0;
1918 int ret = 0;
3d0c5005 1919 u32 tmp;
2320175f 1920
0e6e0be4
CW		 1921 wakeref = intel_display_power_get_if_enabled(dev_priv,
1922 intel_encoder->power_domain);
1923 if (WARN_ON(!wakeref))
2320175f
SP		 1924 return -ENXIO;
1925
1926 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1927 ret = -EIO;
1928 goto out;
1929 }
1930
1931 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1932 if (enable)
1933 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1934 else
1935 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1936 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1937out:
0e6e0be4 1938 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1939 return ret;
1940}
1941
bcbc889b
PZ		 1942bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1943{
1944 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1945 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1946 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1947 int type = intel_connector->base.connector_type;
0fce04c8 1948 enum port port = encoder->port;
bcbc889b 1949 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1950 intel_wakeref_t wakeref;
1951 enum pipe pipe = 0;
3d0c5005 1952 u32 tmp;
e27daab4 1953 bool ret;
bcbc889b 1954
0e6e0be4
CW		 1955 wakeref = intel_display_power_get_if_enabled(dev_priv,
1956 encoder->power_domain);
1957 if (!wakeref)
882244a3
PZ		 1958 return false;
1959
1524e93e 1960 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1961 ret = false;
1962 goto out;
1963 }
bcbc889b 1964
bc7e3525 1965 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1966 cpu_transcoder = TRANSCODER_EDP;
1967 else
1a240d4d 1968 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1969
1970 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1971
1972 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1973 case TRANS_DDI_MODE_SELECT_HDMI:
1974 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1975 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1976 break;
bcbc889b
PZ		 1977
1978 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1979 ret = type == DRM_MODE_CONNECTOR_eDP ||
1980 type == DRM_MODE_CONNECTOR_DisplayPort;
1981 break;
1982
0e32b39c
DA		 1983 case TRANS_DDI_MODE_SELECT_DP_MST:
1984 /* if the transcoder is in MST state then
1985 * connector isn't connected */
e27daab4
ID		 1986 ret = false;
1987 break;
bcbc889b
PZ		 1988
1989 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1990 ret = type == DRM_MODE_CONNECTOR_VGA;
1991 break;
bcbc889b
PZ		 1992
1993 default:
e27daab4
ID		 1994 ret = false;
1995 break;
bcbc889b 1996 }
e27daab4
ID		 1997
1998out:
0e6e0be4 1999 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 2000
2001 return ret;
bcbc889b
PZ		 2002}
2003
9199c322
ID		 2004static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2005 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 2006{
2007 struct drm_device *dev = encoder->base.dev;
fac5e23e 2008 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 2009 enum port port = encoder->port;
0e6e0be4 2010 intel_wakeref_t wakeref;
3657e927 2011 enum pipe p;
85234cdc 2012 u32 tmp;
9199c322
ID		 2013 u8 mst_pipe_mask;
2014
2015 *pipe_mask = 0;
2016 *is_dp_mst = false;
85234cdc 2017
0e6e0be4
CW		 2018 wakeref = intel_display_power_get_if_enabled(dev_priv,
2019 encoder->power_domain);
2020 if (!wakeref)
9199c322 2021 return;
e27daab4 2022
fe43d3f5 2023 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 2024 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 2025 goto out;
85234cdc 2026
bc7e3525 2027 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 2028 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2029
ad80a810 2030 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 2031 default:
2032 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2033 /* fallthrough */
ad80a810
PZ		 2034 case TRANS_DDI_EDP_INPUT_A_ON:
2035 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 2036 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 2037 break;
2038 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 2039 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 2040 break;
2041 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 2042 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 2043 break;
2044 }
2045
e27daab4
ID		 2046 goto out;
2047 }
0e32b39c 2048
9199c322 2049 mst_pipe_mask = 0;
3657e927 2050 for_each_pipe(dev_priv, p) {
9199c322 2051 enum transcoder cpu_transcoder = (enum transcoder)p;
df16b636 2052 unsigned int port_mask, ddi_select;
6aa3bef1
JRS		 2053 intel_wakeref_t trans_wakeref;
2054
2055 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2056 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2057 if (!trans_wakeref)
2058 continue;
df16b636
MK		 2059
2060 if (INTEL_GEN(dev_priv) >= 12) {
2061 port_mask = TGL_TRANS_DDI_PORT_MASK;
2062 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2063 } else {
2064 port_mask = TRANS_DDI_PORT_MASK;
2065 ddi_select = TRANS_DDI_SELECT_PORT(port);
2066 }
3657e927
MK		 2067
2068 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6aa3bef1
JRS		 2069 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2070 trans_wakeref);
e27daab4 2071
df16b636 2072 if ((tmp & port_mask) != ddi_select)
9199c322 2073 continue;
e27daab4 2074
9199c322
ID		 2075 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2076 TRANS_DDI_MODE_SELECT_DP_MST)
2077 mst_pipe_mask |= BIT(p);
e27daab4 2078
9199c322 2079 *pipe_mask |= BIT(p);
85234cdc
DV		 2080 }
2081
9199c322 2082 if (!*pipe_mask)
66a990dd
VS		 2083 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2084 encoder->base.base.id, encoder->base.name);
9199c322
ID		 2085
2086 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
66a990dd
VS		 2087 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2088 encoder->base.base.id, encoder->base.name,
2089 *pipe_mask);
9199c322
ID		 2090 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2091 }
2092
2093 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
66a990dd
VS		 2094 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2095 encoder->base.base.id, encoder->base.name,
2096 *pipe_mask, mst_pipe_mask);
9199c322
ID		 2097 else
2098 *is_dp_mst = mst_pipe_mask;
85234cdc 2099
e27daab4 2100out:
9199c322 2101 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2102 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2103 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2104 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0 2105 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
66a990dd
VS		 2106 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2107 "(PHY_CTL %08x)\n", encoder->base.base.id,
2108 encoder->base.name, tmp);
e93da0a0
ID		 2109 }
2110
0e6e0be4 2111 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2112}
e27daab4 2113
9199c322
ID		 2114bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2115 enum pipe *pipe)
2116{
2117 u8 pipe_mask;
2118 bool is_mst;
2119
2120 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2121
2122 if (is_mst || !pipe_mask)
2123 return false;
2124
2125 *pipe = ffs(pipe_mask) - 1;
2126
2127 return true;
85234cdc
DV		 2128}
2129
52528055 2130static inline enum intel_display_power_domain
bdaa29b6 2131intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2132{
9e3b5ce9 2133 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2134 * DC states enabled at the same time, while for driver initiated AUX
2135 * transfers we need the same AUX IOs to be powered but with DC states
2136 * disabled. Accordingly use the AUX power domain here which leaves DC
2137 * states enabled.
2138 * However, for non-A AUX ports the corresponding non-EDP transcoders
2139 * would have already enabled power well 2 and DC_OFF. This means we can
2140 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2141 * specific AUX_IO reference without powering up any extra wells.
2142 * Note that PSR is enabled only on Port A even though this function
2143 * returns the correct domain for other ports too.
2144 */
563d22a0 2145 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2146 intel_aux_power_domain(dig_port);
52528055
ID		 2147}
2148
3a52fb7e
ID		 2149static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2150 struct intel_crtc_state *crtc_state)
62b69566 2151{
8e4a3ad9 2152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2153 struct intel_digital_port *dig_port;
d8fe2ab6 2154 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
62b69566 2155
52528055
ID		 2156 /*
2157 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2158 * happen since fake-MST encoders don't set their get_power_domains()
2159 * hook.
52528055
ID		 2160 */
2161 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2162 return;
b79ebe74
ID		 2163
2164 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2165 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2166
8e4a3ad9
ID		 2167 /*
2168 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2169 * ports.
2170 */
2171 if (intel_crtc_has_dp_encoder(crtc_state) ||
d8fe2ab6 2172 intel_phy_is_tc(dev_priv, phy))
3a52fb7e
ID		 2173 intel_display_power_get(dev_priv,
2174 intel_ddi_main_link_aux_domain(dig_port));
52528055 2175
a24c62f9
MN		 2176 /*
2177 * VDSC power is needed when DSC is enabled
2178 */
2179 if (crtc_state->dsc_params.compression_enable)
3a52fb7e
ID		 2180 intel_display_power_get(dev_priv,
2181 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2182}
2183
3dc38eea 2184void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2185{
3dc38eea 2186 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2187 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2188 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2189 enum port port = encoder->port;
3dc38eea 2190 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2191
df16b636
MK		 2192 if (cpu_transcoder != TRANSCODER_EDP) {
2193 if (INTEL_GEN(dev_priv) >= 12)
2194 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2195 TGL_TRANS_CLK_SEL_PORT(port));
2196 else
2197 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2198 TRANS_CLK_SEL_PORT(port));
2199 }
fc914639
PZ		 2200}
2201
3dc38eea 2202void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2203{
3dc38eea
ACO		 2204 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2205 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2206
df16b636
MK		 2207 if (cpu_transcoder != TRANSCODER_EDP) {
2208 if (INTEL_GEN(dev_priv) >= 12)
2209 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2210 TGL_TRANS_CLK_SEL_DISABLED);
2211 else
2212 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2213 TRANS_CLK_SEL_DISABLED);
2214 }
fc914639
PZ		 2215}
2216
a7d8dbc0 2217static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2218 enum port port, u8 iboost)
f8896f5d 2219{
a7d8dbc0
VS		 2220 u32 tmp;
2221
2222 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2223 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2224 if (iboost)
2225 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2226 else
2227 tmp |= BALANCE_LEG_DISABLE(port);
2228 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2229}
2230
081dfcfa
VS		 2231static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2232 int level, enum intel_output_type type)
a7d8dbc0
VS		 2233{
2234 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2236 enum port port = encoder->port;
3d0c5005 2237 u8 iboost;
f8896f5d 2238
081dfcfa
VS		 2239 if (type == INTEL_OUTPUT_HDMI)
2240 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2241 else
2242 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2243
081dfcfa
VS		 2244 if (iboost == 0) {
2245 const struct ddi_buf_trans *ddi_translations;
2246 int n_entries;
2247
2248 if (type == INTEL_OUTPUT_HDMI)
2249 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2250 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2251 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2252 else
edba48fd 2253 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2254
21b39d2a
VS		 2255 if (WARN_ON_ONCE(!ddi_translations))
2256 return;
2257 if (WARN_ON_ONCE(level >= n_entries))
2258 level = n_entries - 1;
2259
081dfcfa 2260 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2261 }
2262
2263 /* Make sure that the requested I_boost is valid */
2264 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2265 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2266 return;
2267 }
2268
a7d8dbc0 2269 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2270
a7d8dbc0
VS		 2271 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2272 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2273}
2274
7d4f37b5
VS		 2275static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2276 int level, enum intel_output_type type)
96fb9f9b 2277{
7d4f37b5 2278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2279 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2280 enum port port = encoder->port;
043eaf36 2281 int n_entries;
7d4f37b5
VS		 2282
2283 if (type == INTEL_OUTPUT_HDMI)
2284 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2285 else if (type == INTEL_OUTPUT_EDP)
2286 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2287 else
2288 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2289
21b39d2a
VS		 2290 if (WARN_ON_ONCE(!ddi_translations))
2291 return;
2292 if (WARN_ON_ONCE(level >= n_entries))
2293 level = n_entries - 1;
2294
b6e08203
ACO		 2295 bxt_ddi_phy_set_signal_level(dev_priv, port,
2296 ddi_translations[level].margin,
2297 ddi_translations[level].scale,
2298 ddi_translations[level].enable,
2299 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2300}
2301
ffe5111e
VS		 2302u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2303{
2304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2305 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2306 enum port port = encoder->port;
d8fe2ab6 2307 enum phy phy = intel_port_to_phy(dev_priv, port);
ffe5111e
VS		 2308 int n_entries;
2309
2dd24a9c 2310 if (INTEL_GEN(dev_priv) >= 11) {
d8fe2ab6 2311 if (intel_phy_is_combo(dev_priv, phy))
4a8134d5 2312 icl_get_combo_buf_trans(dev_priv, encoder->type,
b265a2a6 2313 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2314 else
2315 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2316 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2317 if (encoder->type == INTEL_OUTPUT_EDP)
2318 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2319 else
2320 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2321 } else if (IS_GEN9_LP(dev_priv)) {
2322 if (encoder->type == INTEL_OUTPUT_EDP)
2323 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2324 else
2325 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2326 } else {
2327 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2328 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2329 else
edba48fd 2330 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2331 }
ffe5111e
VS		 2332
2333 if (WARN_ON(n_entries < 1))
2334 n_entries = 1;
2335 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2336 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2337
2338 return index_to_dp_signal_levels[n_entries - 1] &
2339 DP_TRAIN_VOLTAGE_SWING_MASK;
2340}
2341
4718a365
VS		 2342/*
2343 * We assume that the full set of pre-emphasis values can be
2344 * used on all DDI platforms. Should that change we need to
2345 * rethink this code.
2346 */
2347u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2348{
2349 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2350 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2351 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2353 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2355 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2357 default:
2358 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2359 }
2360}
2361
f3cf4ba4
VS		 2362static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2363 int level, enum intel_output_type type)
cf54ca8b 2364{
f3cf4ba4 2365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2366 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2367 enum port port = encoder->port;
f3cf4ba4
VS		 2368 int n_entries, ln;
2369 u32 val;
cf54ca8b 2370
f3cf4ba4 2371 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2372 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2373 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2374 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2375 else
2376 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2377
21b39d2a 2378 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2379 return;
21b39d2a 2380 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2381 level = n_entries - 1;
cf54ca8b
RV		 2382
2383 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2384 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2385 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2386 val |= SCALING_MODE_SEL(2);
2387 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2388
2389 /* Program PORT_TX_DW2 */
2390 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2391 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2392 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2393 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2394 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2395 /* Rcomp scalar is fixed as 0x98 for every table entry */
2396 val |= RCOMP_SCALAR(0x98);
2397 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2398
20303eb4 2399 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2400 /* We cannot write to GRP. It would overrite individual loadgen */
2401 for (ln = 0; ln < 4; ln++) {
9194e42a 2402 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2403 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2404 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2405 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2406 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2407 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2408 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2409 }
2410
20303eb4 2411 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2412 /* All DW5 values are fixed for every table entry */
2413 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2414 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2415 val |= RTERM_SELECT(6);
2416 val |= TAP3_DISABLE;
2417 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2418
20303eb4 2419 /* Program PORT_TX_DW7 */
cf54ca8b 2420 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2421 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2422 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2423 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2424}
2425
f3cf4ba4
VS		 2426static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2427 int level, enum intel_output_type type)
cf54ca8b 2428{
0091abc3 2429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2430 enum port port = encoder->port;
f3cf4ba4 2431 int width, rate, ln;
cf54ca8b 2432 u32 val;
0091abc3 2433
f3cf4ba4 2434 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2435 width = 4;
f3cf4ba4 2436 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2437 } else {
f3cf4ba4
VS		 2438 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2439
2440 width = intel_dp->lane_count;
2441 rate = intel_dp->link_rate;
0091abc3 2442 }
cf54ca8b
RV		 2443
2444 /*
2445 * 1. If port type is eDP or DP,
2446 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2447 * else clear to 0b.
2448 */
2449 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2450 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2451 val |= COMMON_KEEPER_EN;
2452 else
2453 val &= ~COMMON_KEEPER_EN;
2454 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2455
2456 /* 2. Program loadgen select */
2457 /*
0091abc3
CT		 2458 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2459 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2460 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2461 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2462 */
0091abc3 2463 for (ln = 0; ln <= 3; ln++) {
9194e42a 2464 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2465 val &= ~LOADGEN_SELECT;
2466
a8e45a1c
NM		 2467 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2468 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2469 val |= LOADGEN_SELECT;
2470 }
9194e42a 2471 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2472 }
cf54ca8b
RV		 2473
2474 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2475 val = I915_READ(CNL_PORT_CL1CM_DW5);
2476 val |= SUS_CLOCK_CONFIG;
2477 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2478
2479 /* 4. Clear training enable to change swing values */
2480 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2481 val &= ~TX_TRAINING_EN;
2482 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2483
2484 /* 5. Program swing and de-emphasis */
f3cf4ba4 2485 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2486
2487 /* 6. Set training enable to trigger update */
2488 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2489 val |= TX_TRAINING_EN;
2490 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2491}
2492
fb5c8e9d 2493static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
dc867bc7 2494 u32 level, enum phy phy, int type,
b265a2a6 2495 int rate)
fb5c8e9d 2496{
b265a2a6 2497 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2498 u32 n_entries, val;
2499 int ln;
2500
4a8134d5
MR		 2501 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2502 &n_entries);
fb5c8e9d
MN		 2503 if (!ddi_translations)
2504 return;
2505
2506 if (level >= n_entries) {
2507 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2508 level = n_entries - 1;
2509 }
2510
b265a2a6 2511 /* Set PORT_TX_DW5 */
dc867bc7 2512 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
b265a2a6
CT		 2513 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2514 TAP2_DISABLE | TAP3_DISABLE);
2515 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2516 val |= RTERM_SELECT(0x6);
b265a2a6 2517 val |= TAP3_DISABLE;
dc867bc7 2518 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2519
2520 /* Program PORT_TX_DW2 */
dc867bc7 2521 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
fb5c8e9d
MN		 2522 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2523 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2524 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2525 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2526 /* Program Rcomp scalar for every table entry */
b265a2a6 2527 val |= RCOMP_SCALAR(0x98);
dc867bc7 2528 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
fb5c8e9d
MN		 2529
2530 /* Program PORT_TX_DW4 */
2531 /* We cannot write to GRP. It would overwrite individual loadgen. */
2532 for (ln = 0; ln <= 3; ln++) {
dc867bc7 2533 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
fb5c8e9d
MN		 2534 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2535 CURSOR_COEFF_MASK);
b265a2a6
CT		 2536 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2537 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2538 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
dc867bc7 2539 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
fb5c8e9d 2540 }
b265a2a6
CT		 2541
2542 /* Program PORT_TX_DW7 */
dc867bc7 2543 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
b265a2a6
CT		 2544 val &= ~N_SCALAR_MASK;
2545 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
dc867bc7 2546 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
fb5c8e9d
MN		 2547}
2548
2549static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2550 u32 level,
2551 enum intel_output_type type)
2552{
2553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
dc867bc7 2554 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
fb5c8e9d
MN		 2555 int width = 0;
2556 int rate = 0;
2557 u32 val;
2558 int ln = 0;
2559
2560 if (type == INTEL_OUTPUT_HDMI) {
2561 width = 4;
2562 /* Rate is always < than 6GHz for HDMI */
2563 } else {
2564 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2565
2566 width = intel_dp->lane_count;
2567 rate = intel_dp->link_rate;
2568 }
2569
2570 /*
2571 * 1. If port type is eDP or DP,
2572 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2573 * else clear to 0b.
2574 */
dc867bc7 2575 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
fb5c8e9d
MN		 2576 if (type == INTEL_OUTPUT_HDMI)
2577 val &= ~COMMON_KEEPER_EN;
2578 else
2579 val |= COMMON_KEEPER_EN;
dc867bc7 2580 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
fb5c8e9d
MN		 2581
2582 /* 2. Program loadgen select */
2583 /*
2584 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2585 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2586 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2587 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2588 */
2589 for (ln = 0; ln <= 3; ln++) {
dc867bc7 2590 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
fb5c8e9d
MN		 2591 val &= ~LOADGEN_SELECT;
2592
2593 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2594 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2595 val |= LOADGEN_SELECT;
2596 }
dc867bc7 2597 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
fb5c8e9d
MN		 2598 }
2599
2600 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
dc867bc7 2601 val = I915_READ(ICL_PORT_CL_DW5(phy));
fb5c8e9d 2602 val |= SUS_CLOCK_CONFIG;
dc867bc7 2603 I915_WRITE(ICL_PORT_CL_DW5(phy), val);
fb5c8e9d
MN		 2604
2605 /* 4. Clear training enable to change swing values */
dc867bc7 2606 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
fb5c8e9d 2607 val &= ~TX_TRAINING_EN;
dc867bc7 2608 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2609
2610 /* 5. Program swing and de-emphasis */
dc867bc7 2611 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
fb5c8e9d
MN		 2612
2613 /* 6. Set training enable to trigger update */
dc867bc7 2614 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
fb5c8e9d 2615 val |= TX_TRAINING_EN;
dc867bc7 2616 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
fb5c8e9d
MN		 2617}
2618
07685c82
MN		 2619static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2620 int link_clock,
2621 u32 level)
2622{
2623 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2624 enum port port = encoder->port;
2625 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2626 u32 n_entries, val;
2627 int ln;
2628
2629 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2630 ddi_translations = icl_mg_phy_ddi_translations;
2631 /* The table does not have values for level 3 and level 9. */
2632 if (level >= n_entries || level == 3 || level == 9) {
2633 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2634 level, n_entries - 2);
2635 level = n_entries - 2;
2636 }
2637
2638 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2639 for (ln = 0; ln < 2; ln++) {
58106b7d 2640 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2641 val &= ~CRI_USE_FS32;
58106b7d 2642 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2643
58106b7d 2644 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2645 val &= ~CRI_USE_FS32;
58106b7d 2646 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2647 }
2648
2649 /* Program MG_TX_SWINGCTRL with values from vswing table */
2650 for (ln = 0; ln < 2; ln++) {
58106b7d 2651 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2652 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2653 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2654 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2655 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2656
58106b7d 2657 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2658 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2659 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2660 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2661 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2662 }
2663
2664 /* Program MG_TX_DRVCTRL with values from vswing table */
2665 for (ln = 0; ln < 2; ln++) {
58106b7d 2666 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2667 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2668 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2669 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2670 ddi_translations[level].cri_txdeemph_override_5_0) |
2671 CRI_TXDEEMPH_OVERRIDE_11_6(
2672 ddi_translations[level].cri_txdeemph_override_11_6) |
2673 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2674 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2675
58106b7d 2676 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2677 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2678 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2679 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2680 ddi_translations[level].cri_txdeemph_override_5_0) |
2681 CRI_TXDEEMPH_OVERRIDE_11_6(
2682 ddi_translations[level].cri_txdeemph_override_11_6) |
2683 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2684 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2685
2686 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2687 }
2688
2689 /*
2690 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2691 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2692 * values from table for which TX1 and TX2 enabled.
2693 */
2694 for (ln = 0; ln < 2; ln++) {
58106b7d 2695 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2696 if (link_clock < 300000)
2697 val |= CFG_LOW_RATE_LKREN_EN;
2698 else
2699 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2700 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2701 }
2702
2703 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2704 for (ln = 0; ln < 2; ln++) {
58106b7d 2705 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2706 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2707 if (link_clock <= 500000) {
2708 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2709 } else {
2710 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2711 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2712 }
58106b7d 2713 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2714
58106b7d 2715 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2716 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2717 if (link_clock <= 500000) {
2718 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2719 } else {
2720 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2721 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2722 }
58106b7d 2723 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2724 }
2725
2726 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2727 for (ln = 0; ln < 2; ln++) {
58106b7d 2728 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2729 val |= CRI_CALCINIT;
58106b7d 2730 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2731
58106b7d 2732 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2733 val |= CRI_CALCINIT;
58106b7d 2734 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2735 }
2736}
2737
2738static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2739 int link_clock,
2740 u32 level,
fb5c8e9d
MN		 2741 enum intel_output_type type)
2742{
176597a1 2743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
d8fe2ab6 2744 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
fb5c8e9d 2745
d8fe2ab6 2746 if (intel_phy_is_combo(dev_priv, phy))
fb5c8e9d
MN		 2747 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2748 else
07685c82 2749 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2750}
2751
3d0c5005 2752static u32 translate_signal_level(int signal_levels)
f8896f5d 2753{
97eeb872 2754 int i;
f8896f5d 2755
97eeb872
VS		 2756 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2757 if (index_to_dp_signal_levels[i] == signal_levels)
2758 return i;
f8896f5d
DW		 2759 }
2760
97eeb872
VS		 2761 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2762 signal_levels);
2763
2764 return 0;
f8896f5d
DW		 2765}
2766
3d0c5005 2767static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2768{
3d0c5005 2769 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2770 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2771 DP_TRAIN_PRE_EMPHASIS_MASK);
2772
2773 return translate_signal_level(signal_levels);
2774}
2775
d509af6c 2776u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2777{
2778 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2779 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2780 struct intel_encoder *encoder = &dport->base;
d02ace87 2781 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2782
2dd24a9c 2783 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2784 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2785 level, encoder->type);
fb5c8e9d 2786 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2787 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2788 else
7d4f37b5 2789 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2790
2791 return 0;
2792}
2793
3d0c5005 2794u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2795{
2796 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2797 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2798 struct intel_encoder *encoder = &dport->base;
d02ace87 2799 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2800
b976dc53 2801 if (IS_GEN9_BC(dev_priv))
081dfcfa 2802 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2803
f8896f5d
DW		 2804 return DDI_BUF_TRANS_SELECT(level);
2805}
2806
bb1c7edc 2807static inline
3d0c5005 2808u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
befa372b 2809 enum phy phy)
bb1c7edc 2810{
befa372b
MR		 2811 if (intel_phy_is_combo(dev_priv, phy)) {
2812 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2813 } else if (intel_phy_is_tc(dev_priv, phy)) {
2814 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2815 (enum port)phy);
bb1c7edc
MK		 2816
2817 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2818 }
2819
2820 return 0;
2821}
2822
3b8c0d5b
JN		 2823static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2824 const struct intel_crtc_state *crtc_state)
c27e917e 2825{
3b8c0d5b 2826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2827 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
befa372b 2828 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3b8c0d5b 2829 u32 val;
c27e917e 2830
3b8c0d5b 2831 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2832
befa372b
MR		 2833 val = I915_READ(ICL_DPCLKA_CFGCR0);
2834 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
c27e917e 2835
befa372b
MR		 2836 if (intel_phy_is_combo(dev_priv, phy)) {
2837 /*
2838 * Even though this register references DDIs, note that we
2839 * want to pass the PHY rather than the port (DDI). For
2840 * ICL, port=phy in all cases so it doesn't matter, but for
2841 * EHL the bspec notes the following:
2842 *
2843 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2844 * Clock Select chooses the PLL for both DDIA and DDID and
2845 * drives port A in all cases."
2846 */
2847 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2848 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2849 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2850 POSTING_READ(ICL_DPCLKA_CFGCR0);
c27e917e 2851 }
3b8c0d5b 2852
befa372b
MR		 2853 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2854 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3b8c0d5b
JN		 2855
2856 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2857}
2858
3b8c0d5b 2859static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2860{
3b8c0d5b 2861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
befa372b 2862 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3b8c0d5b 2863 u32 val;
c27e917e 2864
3b8c0d5b 2865 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2866
befa372b
MR		 2867 val = I915_READ(ICL_DPCLKA_CFGCR0);
2868 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2869 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
c27e917e 2870
3b8c0d5b 2871 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2872}
2873
70332ac5
ID		 2874void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2875{
2876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2877 u32 val;
1dd07e56
ID		 2878 enum port port;
2879 u32 port_mask;
2880 bool ddi_clk_needed;
30f5ccfa
ID		 2881
2882 /*
2883 * In case of DP MST, we sanitize the primary encoder only, not the
2884 * virtual ones.
2885 */
2886 if (encoder->type == INTEL_OUTPUT_DP_MST)
2887 return;
2888
30f5ccfa
ID		 2889 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2890 u8 pipe_mask;
2891 bool is_mst;
2892
2893 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2894 /*
2895 * In the unlikely case that BIOS enables DP in MST mode, just
2896 * warn since our MST HW readout is incomplete.
2897 */
2898 if (WARN_ON(is_mst))
2899 return;
2900 }
70332ac5 2901
1dd07e56
ID		 2902 port_mask = BIT(encoder->port);
2903 ddi_clk_needed = encoder->base.crtc;
70332ac5 2904
1dd07e56
ID		 2905 if (encoder->type == INTEL_OUTPUT_DSI) {
2906 struct intel_encoder *other_encoder;
70332ac5 2907
1dd07e56
ID		 2908 port_mask = intel_dsi_encoder_ports(encoder);
2909 /*
2910 * Sanity check that we haven't incorrectly registered another
2911 * encoder using any of the ports of this DSI encoder.
2912 */
2913 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2914 if (other_encoder == encoder)
2915 continue;
2916
2917 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2918 return;
2919 }
2920 /*
942d1cf4
VK		 2921 * For DSI we keep the ddi clocks gated
2922 * except during enable/disable sequence.
1dd07e56 2923 */
942d1cf4 2924 ddi_clk_needed = false;
1dd07e56
ID		 2925 }
2926
befa372b 2927 val = I915_READ(ICL_DPCLKA_CFGCR0);
1dd07e56 2928 for_each_port_masked(port, port_mask) {
befa372b
MR		 2929 enum phy phy = intel_port_to_phy(dev_priv, port);
2930
1dd07e56
ID		 2931 bool ddi_clk_ungated = !(val &
2932 icl_dpclka_cfgcr0_clk_off(dev_priv,
befa372b 2933 phy));
1dd07e56
ID		 2934
2935 if (ddi_clk_needed == ddi_clk_ungated)
2936 continue;
2937
2938 /*
2939 * Punt on the case now where clock is gated, but it would
2940 * be needed by the port. Something else is really broken then.
2941 */
2942 if (WARN_ON(ddi_clk_needed))
2943 continue;
2944
befa372b
MR		 2945 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2946 phy_name(port));
2947 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2948 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
1dd07e56 2949 }
70332ac5
ID		 2950}
2951
d7c530b2 2952static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2953 const struct intel_crtc_state *crtc_state)
6441ab5f 2954{
e404ba8d 2955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2956 enum port port = encoder->port;
d8fe2ab6 2957 enum phy phy = intel_port_to_phy(dev_priv, port);
3d0c5005 2958 u32 val;
0e5fa646 2959 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2960
c856052a
ACO		 2961 if (WARN_ON(!pll))
2962 return;
2963
04bf68bb 2964 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2965
2dd24a9c 2966 if (INTEL_GEN(dev_priv) >= 11) {
d8fe2ab6 2967 if (!intel_phy_is_combo(dev_priv, phy))
c27e917e 2968 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2969 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c2052d6e
JRS		 2970 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2971 /*
2972 * MG does not exist but the programming is required
2973 * to ungate DDIC and DDID
2974 */
2975 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
c27e917e 2976 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2977 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2978 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2979 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2980 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2981 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2982
555e38d2
RV		 2983 /*
2984 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2985 * This step and the step before must be done with separate
2986 * register writes.
2987 */
2988 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2989 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2990 I915_WRITE(DPCLKA_CFGCR0, val);
2991 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2992 /* DDI -> PLL mapping */
efa80add
S		 2993 val = I915_READ(DPLL_CTRL2);
2994
2995 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2996 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2997 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2998 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2999
3000 I915_WRITE(DPLL_CTRL2, val);
5416d871 3001
c56b89f1 3002 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 3003 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 3004 }
8edcda12
RV		 3005
3006 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 3007}
3008
6b8506d5
VS		 3009static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3010{
3011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3012 enum port port = encoder->port;
d8fe2ab6 3013 enum phy phy = intel_port_to_phy(dev_priv, port);
6b8506d5 3014
2dd24a9c 3015 if (INTEL_GEN(dev_priv) >= 11) {
c2052d6e
JRS		 3016 if (!intel_phy_is_combo(dev_priv, phy) ||
3017 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
c27e917e
PZ		 3018 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3019 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 3020 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3021 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 3022 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 3023 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3024 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 3025 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 3026 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 3027 }
6b8506d5
VS		 3028}
3029
cb9ff519
ID		 3030static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
3031{
3032 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3033 enum port port = dig_port->base.port;
3034 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 3035 u32 val;
9c11b121 3036 int ln;
cb9ff519
ID		 3037
3038 if (tc_port == PORT_TC_NONE)
3039 return;
3040
9c11b121
ID		 3041 for (ln = 0; ln < 2; ln++) {
3042 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 3043 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
3044 MG_DP_MODE_CFG_TRPWR_GATING |
3045 MG_DP_MODE_CFG_CLNPWR_GATING |
3046 MG_DP_MODE_CFG_DIGPWR_GATING |
3047 MG_DP_MODE_CFG_GAONPWR_GATING;
9c11b121 3048 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 3049 }
3050
3051 val = I915_READ(MG_MISC_SUS0(tc_port));
3052 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
3053 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3054 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3055 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3056 MG_MISC_SUS0_CFG_TRPWR_GATING |
3057 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3058 MG_MISC_SUS0_CFG_DGPWR_GATING;
3059 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3060}
3061
3062static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3063{
3064 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3065 enum port port = dig_port->base.port;
3066 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 3067 u32 val;
9c11b121 3068 int ln;
cb9ff519
ID		 3069
3070 if (tc_port == PORT_TC_NONE)
3071 return;
3072
9c11b121
ID		 3073 for (ln = 0; ln < 2; ln++) {
3074 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 3075 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3076 MG_DP_MODE_CFG_TRPWR_GATING |
3077 MG_DP_MODE_CFG_CLNPWR_GATING |
3078 MG_DP_MODE_CFG_DIGPWR_GATING |
3079 MG_DP_MODE_CFG_GAONPWR_GATING);
9c11b121 3080 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 3081 }
3082
3083 val = I915_READ(MG_MISC_SUS0(tc_port));
3084 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3085 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3086 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3087 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3088 MG_MISC_SUS0_CFG_TRPWR_GATING |
3089 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3090 MG_MISC_SUS0_CFG_DGPWR_GATING);
3091 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3092}
3093
93b662d3
ID		 3094static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3095{
3096 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3097 enum port port = intel_dig_port->base.port;
c905eb28 3098 u32 ln0, ln1, lane_mask;
93b662d3 3099
e9b7e142 3100 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
93b662d3
ID		 3101 return;
3102
37fc7845
JRS		 3103 ln0 = I915_READ(MG_DP_MODE(0, port));
3104 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3 3105
e9b7e142
ID		 3106 switch (intel_dig_port->tc_mode) {
3107 case TC_PORT_DP_ALT:
93b662d3
ID		 3108 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3109 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3110
c905eb28 3111 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
93b662d3 3112
c905eb28 3113 switch (lane_mask) {
93b662d3
ID		 3114 case 0x1:
3115 case 0x4:
3116 break;
3117 case 0x2:
3118 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3119 break;
3120 case 0x3:
3121 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3122 MG_DP_MODE_CFG_DP_X2_MODE;
3123 break;
3124 case 0x8:
3125 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3126 break;
3127 case 0xC:
3128 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3129 MG_DP_MODE_CFG_DP_X2_MODE;
3130 break;
3131 case 0xF:
3132 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3133 MG_DP_MODE_CFG_DP_X2_MODE;
3134 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3135 MG_DP_MODE_CFG_DP_X2_MODE;
3136 break;
3137 default:
c905eb28 3138 MISSING_CASE(lane_mask);
93b662d3
ID		 3139 }
3140 break;
3141
3142 case TC_PORT_LEGACY:
3143 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3144 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3145 break;
3146
3147 default:
e9b7e142 3148 MISSING_CASE(intel_dig_port->tc_mode);
93b662d3
ID		 3149 return;
3150 }
3151
37fc7845
JRS		 3152 I915_WRITE(MG_DP_MODE(0, port), ln0);
3153 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3154}
3155
a322b975
AS		 3156static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3157 const struct intel_crtc_state *crtc_state)
3158{
3159 if (!crtc_state->fec_enable)
3160 return;
3161
3162 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3163 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3164}
3165
5c44b938
AS		 3166static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3167 const struct intel_crtc_state *crtc_state)
3168{
3169 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3170 enum port port = encoder->port;
3171 u32 val;
3172
3173 if (!crtc_state->fec_enable)
3174 return;
3175
3176 val = I915_READ(DP_TP_CTL(port));
3177 val |= DP_TP_CTL_FEC_ENABLE;
3178 I915_WRITE(DP_TP_CTL(port), val);
3179
4cb3b44d
DCS		 3180 if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
3181 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
5c44b938
AS		 3182 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3183}
3184
d6a09cee
AS		 3185static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3186 const struct intel_crtc_state *crtc_state)
3187{
3188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3189 enum port port = encoder->port;
3190 u32 val;
3191
3192 if (!crtc_state->fec_enable)
3193 return;
3194
3195 val = I915_READ(DP_TP_CTL(port));
3196 val &= ~DP_TP_CTL_FEC_ENABLE;
3197 I915_WRITE(DP_TP_CTL(port), val);
3198 POSTING_READ(DP_TP_CTL(port));
3199}
3200
99389390
JRS		 3201static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3202 const struct intel_crtc_state *crtc_state,
3203 const struct drm_connector_state *conn_state)
3204{
3205 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3207 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3208 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3209 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3210 int level = intel_ddi_dp_level(intel_dp);
3211
3212 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3213 crtc_state->lane_count, is_mst);
3214
3215 /* 1.a got on intel_atomic_commit_tail() */
3216
3217 /* 2. */
3218 intel_edp_panel_on(intel_dp);
3219
3220 /*
3221 * 1.b, 3. and 4. is done before tgl_ddi_pre_enable_dp() by:
3222 * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
3223 * haswell_crtc_enable()->intel_enable_shared_dpll()
3224 */
3225
3226 /* 5. */
3227 if (!intel_phy_is_tc(dev_priv, phy) ||
3228 dig_port->tc_mode != TC_PORT_TBT_ALT)
3229 intel_display_power_get(dev_priv,
3230 dig_port->ddi_io_power_domain);
3231
3232 /* 6. */
3233 icl_program_mg_dp_mode(dig_port);
3234
3235 /*
3236 * 7.a - Steps in this function should only be executed over MST
3237 * master, what will be taken in care by MST hook
3238 * intel_mst_pre_enable_dp()
3239 */
3240 intel_ddi_enable_pipe_clock(crtc_state);
3241
3242 /* 7.b */
3243 intel_ddi_config_transcoder_func(crtc_state);
3244
3245 /* 7.d */
3246 icl_disable_phy_clock_gating(dig_port);
3247
3248 /* 7.e */
3249 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3250 encoder->type);
3251
3252 /* 7.f */
3253 if (intel_phy_is_combo(dev_priv, phy)) {
3254 bool lane_reversal =
3255 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3256
3257 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3258 crtc_state->lane_count,
3259 lane_reversal);
3260 }
3261
3262 /* 7.g */
3263 intel_ddi_init_dp_buf_reg(encoder);
3264
3265 if (!is_mst)
3266 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3267
3268 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3269 /*
3270 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3271 * in the FEC_CONFIGURATION register to 1 before initiating link
3272 * training
3273 */
3274 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3275 /* 7.c, 7.h, 7.i, 7.j */
3276 intel_dp_start_link_train(intel_dp);
3277
3278 /* 7.k */
3279 intel_dp_stop_link_train(intel_dp);
3280
3281 /* 7.l */
3282 intel_ddi_enable_fec(encoder, crtc_state);
3283 intel_dsc_enable(encoder, crtc_state);
3284}
3285
3286static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3287 const struct intel_crtc_state *crtc_state,
3288 const struct drm_connector_state *conn_state)
e404ba8d 3289{
ba88d153
MN		 3290 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3292 enum port port = encoder->port;
dc867bc7 3293 enum phy phy = intel_port_to_phy(dev_priv, port);
62b69566 3294 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3295 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3296 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3297
45e0327e 3298 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3299
45e0327e
VS		 3300 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3301 crtc_state->lane_count, is_mst);
680b71c2
VS		 3302
3303 intel_edp_panel_on(intel_dp);
32bdc400 3304
0e5fa646 3305 intel_ddi_clk_select(encoder, crtc_state);
62b69566 3306
d8fe2ab6 3307 if (!intel_phy_is_tc(dev_priv, phy) ||
3b2ed431
ID		 3308 dig_port->tc_mode != TC_PORT_TBT_ALT)
3309 intel_display_power_get(dev_priv,
3310 dig_port->ddi_io_power_domain);
62b69566 3311
93b662d3 3312 icl_program_mg_dp_mode(dig_port);
bc334d91 3313 icl_disable_phy_clock_gating(dig_port);
340a44be 3314
2dd24a9c 3315 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3316 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3317 level, encoder->type);
fb5c8e9d 3318 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3319 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3320 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3321 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3322 else
3a6d84e6 3323 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3324
d8fe2ab6 3325 if (intel_phy_is_combo(dev_priv, phy)) {
cfda08cd
ID		 3326 bool lane_reversal =
3327 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3328
dc867bc7 3329 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
cfda08cd
ID		 3330 crtc_state->lane_count,
3331 lane_reversal);
3332 }
3333
ba88d153 3334 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3335 if (!is_mst)
3336 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3337 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3338 true);
a322b975 3339 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3340 intel_dp_start_link_train(intel_dp);
3341 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3342 intel_dp_stop_link_train(intel_dp);
afb2c443 3343
5c44b938
AS		 3344 intel_ddi_enable_fec(encoder, crtc_state);
3345
bc334d91
PZ		 3346 icl_enable_phy_clock_gating(dig_port);
3347
2b5cf4ef
ID		 3348 if (!is_mst)
3349 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3350
3351 intel_dsc_enable(encoder, crtc_state);
ba88d153 3352}
901c2daf 3353
99389390
JRS		 3354static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3355 const struct intel_crtc_state *crtc_state,
3356 const struct drm_connector_state *conn_state)
3357{
3358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3359
3360 if (INTEL_GEN(dev_priv) >= 12)
3361 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3362 else
3363 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3364}
3365
ba88d153 3366static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3367 const struct intel_crtc_state *crtc_state,
45e0327e 3368 const struct drm_connector_state *conn_state)
ba88d153 3369{
f99be1b3
VS		 3370 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3371 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3373 enum port port = encoder->port;
ba88d153 3374 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3375 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3376
ba88d153 3377 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3378 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3379
3380 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3381
93b662d3 3382 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3383 icl_disable_phy_clock_gating(dig_port);
3384
2dd24a9c 3385 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3386 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3387 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3388 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3389 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3390 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3391 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3392 else
7ea79333 3393 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3394
cb9ff519
ID		 3395 icl_enable_phy_clock_gating(dig_port);
3396
2f7460a7 3397 if (IS_GEN9_BC(dev_priv))
081dfcfa 3398 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3399
c7373764
ID		 3400 intel_ddi_enable_pipe_clock(crtc_state);
3401
790ea70c 3402 intel_dig_port->set_infoframes(encoder,
45e0327e 3403 crtc_state->has_infoframe,
f99be1b3 3404 crtc_state, conn_state);
ba88d153 3405}
32bdc400 3406
1524e93e 3407static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3408 const struct intel_crtc_state *crtc_state,
5f88a9c6 3409 const struct drm_connector_state *conn_state)
ba88d153 3410{
45e0327e
VS		 3411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3412 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3413 enum pipe pipe = crtc->pipe;
30cf6db8 3414
1939ba51
VS		 3415 /*
3416 * When called from DP MST code:
3417 * - conn_state will be NULL
3418 * - encoder will be the main encoder (ie. mst->primary)
3419 * - the main connector associated with this port
3420 * won't be active or linked to a crtc
3421 * - crtc_state will be the state of the first stream to
3422 * be activated on this port, and it may not be the same
3423 * stream that will be deactivated last, but each stream
3424 * should have a state that is identical when it comes to
3425 * the DP link parameteres
3426 */
3427
45e0327e 3428 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3429
3b8c0d5b
JN		 3430 if (INTEL_GEN(dev_priv) >= 11)
3431 icl_map_plls_to_ports(encoder, crtc_state);
3432
364a3fe1
JN		 3433 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3434
06c812d7 3435 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3436 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3437 } else {
3438 struct intel_lspcon *lspcon =
3439 enc_to_intel_lspcon(&encoder->base);
3440
45e0327e 3441 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3442 if (lspcon->active) {
3443 struct intel_digital_port *dig_port =
3444 enc_to_dig_port(&encoder->base);
3445
3446 dig_port->set_infoframes(encoder,
3447 crtc_state->has_infoframe,
3448 crtc_state, conn_state);
3449 }
3450 }
6441ab5f
PZ		 3451}
3452
d6a09cee
AS		 3453static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3454 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3455{
3456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3457 enum port port = encoder->port;
e725f645
VS		 3458 bool wait = false;
3459 u32 val;
3460
3461 val = I915_READ(DDI_BUF_CTL(port));
3462 if (val & DDI_BUF_CTL_ENABLE) {
3463 val &= ~DDI_BUF_CTL_ENABLE;
3464 I915_WRITE(DDI_BUF_CTL(port), val);
3465 wait = true;
3466 }
3467
3468 val = I915_READ(DP_TP_CTL(port));
3469 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3470 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3471 I915_WRITE(DP_TP_CTL(port), val);
3472
d6a09cee
AS		 3473 /* Disable FEC in DP Sink */
3474 intel_ddi_disable_fec_state(encoder, crtc_state);
3475
e725f645
VS		 3476 if (wait)
3477 intel_wait_ddi_buf_idle(dev_priv, port);
3478}
3479
f45f3da7
VS		 3480static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3481 const struct intel_crtc_state *old_crtc_state,
3482 const struct drm_connector_state *old_conn_state)
6441ab5f 3483{
f45f3da7
VS		 3484 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3485 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3486 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3487 bool is_mst = intel_crtc_has_type(old_crtc_state,
3488 INTEL_OUTPUT_DP_MST);
d8fe2ab6 3489 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2886e93f 3490
2b5cf4ef
ID		 3491 if (!is_mst) {
3492 intel_ddi_disable_pipe_clock(old_crtc_state);
3493 /*
3494 * Power down sink before disabling the port, otherwise we end
3495 * up getting interrupts from the sink on detecting link loss.
3496 */
be1c63c8 3497 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3498 }
c5f93fcf 3499
d6a09cee 3500 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3501
f45f3da7
VS		 3502 intel_edp_panel_vdd_on(intel_dp);
3503 intel_edp_panel_off(intel_dp);
a836bdf9 3504
d8fe2ab6 3505 if (!intel_phy_is_tc(dev_priv, phy) ||
3b2ed431
ID		 3506 dig_port->tc_mode != TC_PORT_TBT_ALT)
3507 intel_display_power_put_unchecked(dev_priv,
3508 dig_port->ddi_io_power_domain);
c5f93fcf 3509
f45f3da7
VS		 3510 intel_ddi_clk_disable(encoder);
3511}
c5f93fcf 3512
f45f3da7
VS		 3513static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3514 const struct intel_crtc_state *old_crtc_state,
3515 const struct drm_connector_state *old_conn_state)
3516{
3517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3518 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3519 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3520
790ea70c 3521 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3522 old_crtc_state, old_conn_state);
3523
afb2c443
ID		 3524 intel_ddi_disable_pipe_clock(old_crtc_state);
3525
d6a09cee 3526 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3527
0e6e0be4
CW		 3528 intel_display_power_put_unchecked(dev_priv,
3529 dig_port->ddi_io_power_domain);
b2ccb822 3530
f45f3da7
VS		 3531 intel_ddi_clk_disable(encoder);
3532
3533 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3534}
3535
3536static void intel_ddi_post_disable(struct intel_encoder *encoder,
3537 const struct intel_crtc_state *old_crtc_state,
3538 const struct drm_connector_state *old_conn_state)
3539{
3b8c0d5b
JN		 3540 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3541
f45f3da7 3542 /*
1939ba51
VS		 3543 * When called from DP MST code:
3544 * - old_conn_state will be NULL
3545 * - encoder will be the main encoder (ie. mst->primary)
3546 * - the main connector associated with this port
3547 * won't be active or linked to a crtc
3548 * - old_crtc_state will be the state of the last stream to
3549 * be deactivated on this port, and it may not be the same
3550 * stream that was activated last, but each stream
3551 * should have a state that is identical when it comes to
3552 * the DP link parameteres
f45f3da7 3553 */
1939ba51
VS		 3554
3555 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3556 intel_ddi_post_disable_hdmi(encoder,
3557 old_crtc_state, old_conn_state);
3558 else
3559 intel_ddi_post_disable_dp(encoder,
3560 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3561
3562 if (INTEL_GEN(dev_priv) >= 11)
3563 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3564}
3565
1524e93e 3566void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3567 const struct intel_crtc_state *old_crtc_state,
3568 const struct drm_connector_state *old_conn_state)
b7076546 3569{
1524e93e 3570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3571 u32 val;
b7076546
ML		 3572
3573 /*
3574 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3575 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3576 * step 13 is the correct place for it. Step 18 is where it was
3577 * originally before the BUN.
3578 */
3579 val = I915_READ(FDI_RX_CTL(PIPE_A));
3580 val &= ~FDI_RX_ENABLE;
3581 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3582
d6a09cee 3583 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3584 intel_ddi_clk_disable(encoder);
b7076546
ML		 3585
3586 val = I915_READ(FDI_RX_MISC(PIPE_A));
3587 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3588 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3589 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3590
3591 val = I915_READ(FDI_RX_CTL(PIPE_A));
3592 val &= ~FDI_PCDCLK;
3593 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3594
3595 val = I915_READ(FDI_RX_CTL(PIPE_A));
3596 val &= ~FDI_RX_PLL_ENABLE;
3597 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3598}
3599
15d05f0e
VS		 3600static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3601 const struct intel_crtc_state *crtc_state,
3602 const struct drm_connector_state *conn_state)
72662e10 3603{
15d05f0e
VS		 3604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3605 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3606 enum port port = encoder->port;
72662e10 3607
15d05f0e
VS		 3608 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3609 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3610
15d05f0e
VS		 3611 intel_edp_backlight_on(crtc_state, conn_state);
3612 intel_psr_enable(intel_dp, crtc_state);
3c053a96 3613 intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
15d05f0e 3614 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3615
15d05f0e
VS		 3616 if (crtc_state->has_audio)
3617 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3618}
3619
8f19b401
ID		 3620static i915_reg_t
3621gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3622 enum port port)
3623{
3624 static const i915_reg_t regs[] = {
3625 [PORT_A] = CHICKEN_TRANS_EDP,
3626 [PORT_B] = CHICKEN_TRANS_A,
3627 [PORT_C] = CHICKEN_TRANS_B,
3628 [PORT_D] = CHICKEN_TRANS_C,
3629 [PORT_E] = CHICKEN_TRANS_A,
3630 };
3631
3632 WARN_ON(INTEL_GEN(dev_priv) < 9);
3633
3634 if (WARN_ON(port < PORT_A || port > PORT_E))
3635 port = PORT_A;
3636
3637 return regs[port];
3638}
3639
15d05f0e
VS		 3640static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3641 const struct intel_crtc_state *crtc_state,
3642 const struct drm_connector_state *conn_state)
3643{
3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3645 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3646 struct drm_connector *connector = conn_state->connector;
0fce04c8 3647 enum port port = encoder->port;
15d05f0e 3648
277ab5ab
VS		 3649 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3650 crtc_state->hdmi_high_tmds_clock_ratio,
3651 crtc_state->hdmi_scrambling))
3652 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3653 connector->base.id, connector->name);
15d05f0e 3654
0519c102
VS		 3655 /* Display WA #1143: skl,kbl,cfl */
3656 if (IS_GEN9_BC(dev_priv)) {
3657 /*
3658 * For some reason these chicken bits have been
3659 * stuffed into a transcoder register, event though
3660 * the bits affect a specific DDI port rather than
3661 * a specific transcoder.
3662 */
8f19b401 3663 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3664 u32 val;
3665
8f19b401 3666 val = I915_READ(reg);
0519c102
VS		 3667
3668 if (port == PORT_E)
3669 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3670 DDIE_TRAINING_OVERRIDE_VALUE;
3671 else
3672 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3673 DDI_TRAINING_OVERRIDE_VALUE;
3674
8f19b401
ID		 3675 I915_WRITE(reg, val);
3676 POSTING_READ(reg);
0519c102
VS		 3677
3678 udelay(1);
3679
3680 if (port == PORT_E)
3681 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3682 DDIE_TRAINING_OVERRIDE_VALUE);
3683 else
3684 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3685 DDI_TRAINING_OVERRIDE_VALUE);
3686
8f19b401 3687 I915_WRITE(reg, val);
0519c102
VS		 3688 }
3689
15d05f0e
VS		 3690 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3691 * are ignored so nothing special needs to be done besides
3692 * enabling the port.
3693 */
3694 I915_WRITE(DDI_BUF_CTL(port),
3695 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3696
15d05f0e
VS		 3697 if (crtc_state->has_audio)
3698 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3699}
3700
3701static void intel_enable_ddi(struct intel_encoder *encoder,
3702 const struct intel_crtc_state *crtc_state,
3703 const struct drm_connector_state *conn_state)
3704{
3705 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3706 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3707 else
3708 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3709
3710 /* Enable hdcp if it's desired */
3711 if (conn_state->content_protection ==
3712 DRM_MODE_CONTENT_PROTECTION_DESIRED)
d456512c
R		 3713 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3714 (u8)conn_state->hdcp_content_type);
5ab432ef
DV		 3715}
3716
33f083f0
VS		 3717static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3718 const struct intel_crtc_state *old_crtc_state,
3719 const struct drm_connector_state *old_conn_state)
5ab432ef 3720{
33f083f0 3721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3722
edb2e530
VS		 3723 intel_dp->link_trained = false;
3724
37255d8d 3725 if (old_crtc_state->has_audio)
8ec47de2
VS		 3726 intel_audio_codec_disable(encoder,
3727 old_crtc_state, old_conn_state);
2831d842 3728
33f083f0
VS		 3729 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3730 intel_psr_disable(intel_dp, old_crtc_state);
3731 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3732 /* Disable the decompression in DP Sink */
3733 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3734 false);
33f083f0 3735}
15953637 3736
33f083f0
VS		 3737static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3738 const struct intel_crtc_state *old_crtc_state,
3739 const struct drm_connector_state *old_conn_state)
3740{
277ab5ab
VS		 3741 struct drm_connector *connector = old_conn_state->connector;
3742
33f083f0 3743 if (old_crtc_state->has_audio)
8ec47de2
VS		 3744 intel_audio_codec_disable(encoder,
3745 old_crtc_state, old_conn_state);
d6c50ff8 3746
277ab5ab
VS		 3747 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3748 false, false))
3749 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3750 connector->base.id, connector->name);
33f083f0
VS		 3751}
3752
3753static void intel_disable_ddi(struct intel_encoder *encoder,
3754 const struct intel_crtc_state *old_crtc_state,
3755 const struct drm_connector_state *old_conn_state)
3756{
ee5e5e7a
SP		 3757 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3758
33f083f0
VS		 3759 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3760 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3761 else
3762 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3763}
79f689aa 3764
2ef82327
HG		 3765static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3766 const struct intel_crtc_state *crtc_state,
3767 const struct drm_connector_state *conn_state)
3768{
3769 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3770
5aa2c9ae
VS		 3771 intel_ddi_set_pipe_settings(crtc_state);
3772
23ec9f52 3773 intel_psr_update(intel_dp, crtc_state);
2ef82327 3774 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3775
3776 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3777}
3778
3779static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3780 const struct intel_crtc_state *crtc_state,
3781 const struct drm_connector_state *conn_state)
3782{
d456512c
R		 3783 struct intel_connector *connector =
3784 to_intel_connector(conn_state->connector);
3785 struct intel_hdcp *hdcp = &connector->hdcp;
3786 bool content_protection_type_changed =
3787 (conn_state->hdcp_content_type != hdcp->content_type &&
3788 conn_state->content_protection !=
3789 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
3790
2ef82327
HG		 3791 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3792 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1 3793
d456512c
R		 3794 /*
3795 * During the HDCP encryption session if Type change is requested,
3796 * disable the HDCP and reenable it with new TYPE value.
3797 */
634852d1 3798 if (conn_state->content_protection ==
d456512c
R		 3799 DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
3800 content_protection_type_changed)
3801 intel_hdcp_disable(connector);
3802
3803 /*
3804 * Mark the hdcp state as DESIRED after the hdcp disable of type
3805 * change procedure.
3806 */
3807 if (content_protection_type_changed) {
3808 mutex_lock(&hdcp->mutex);
3809 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3810 schedule_work(&hdcp->prop_work);
3811 mutex_unlock(&hdcp->mutex);
3812 }
3813
3814 if (conn_state->content_protection ==
3815 DRM_MODE_CONTENT_PROTECTION_DESIRED ||
3816 content_protection_type_changed)
3817 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
2ef82327
HG		 3818}
3819
24a7bfe0
ID		 3820static void
3821intel_ddi_update_prepare(struct intel_atomic_state *state,
3822 struct intel_encoder *encoder,
3823 struct intel_crtc *crtc)
3824{
3825 struct intel_crtc_state *crtc_state =
3826 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3827 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3828
3829 WARN_ON(crtc && crtc->active);
3830
3831 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3832 if (crtc_state && crtc_state->base.active)
3833 intel_update_active_dpll(state, crtc, encoder);
3834}
3835
3836static void
3837intel_ddi_update_complete(struct intel_atomic_state *state,
3838 struct intel_encoder *encoder,
3839 struct intel_crtc *crtc)
3840{
3841 intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3842}
3843
bdaa29b6
ID		 3844static void
3845intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3846 const struct intel_crtc_state *crtc_state,
3847 const struct drm_connector_state *conn_state)
03ad7d88 3848{
bdaa29b6 3849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3850 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
d8fe2ab6
MR		 3851 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3852 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
bdaa29b6 3853
24a7bfe0
ID		 3854 if (is_tc_port)
3855 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3856
3857 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
bdaa29b6
ID		 3858 intel_display_power_get(dev_priv,
3859 intel_ddi_main_link_aux_domain(dig_port));
3860
9d44dcb9
LDM		 3861 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3862 /*
3863 * Program the lane count for static/dynamic connections on
3864 * Type-C ports. Skip this step for TBT.
3865 */
3866 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3867 else if (IS_GEN9_LP(dev_priv))
bdaa29b6
ID		 3868 bxt_ddi_phy_set_lane_optim_mask(encoder,
3869 crtc_state->lane_lat_optim_mask);
bdaa29b6
ID		 3870}
3871
3872static void
3873intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3874 const struct intel_crtc_state *crtc_state,
3875 const struct drm_connector_state *conn_state)
3876{
3877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3878 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
d8fe2ab6
MR		 3879 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3880 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
bdaa29b6 3881
24a7bfe0 3882 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
0e6e0be4
CW		 3883 intel_display_power_put_unchecked(dev_priv,
3884 intel_ddi_main_link_aux_domain(dig_port));
24a7bfe0
ID		 3885
3886 if (is_tc_port)
3887 intel_tc_port_put_link(dig_port);
03ad7d88
MN		 3888}
3889
97068c1b 3890static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3891{
ad64217b
ACO		 3892 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3893 struct drm_i915_private *dev_priv =
3894 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3895 enum port port = intel_dig_port->base.port;
3d0c5005 3896 u32 val;
f3e227df 3897 bool wait = false;
c19b0669
PZ		 3898
3899 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3900 val = I915_READ(DDI_BUF_CTL(port));
3901 if (val & DDI_BUF_CTL_ENABLE) {
3902 val &= ~DDI_BUF_CTL_ENABLE;
3903 I915_WRITE(DDI_BUF_CTL(port), val);
3904 wait = true;
3905 }
3906
3907 val = I915_READ(DP_TP_CTL(port));
3908 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3909 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3910 I915_WRITE(DP_TP_CTL(port), val);
3911 POSTING_READ(DP_TP_CTL(port));
3912
3913 if (wait)
3914 intel_wait_ddi_buf_idle(dev_priv, port);
3915 }
3916
0e32b39c 3917 val = DP_TP_CTL_ENABLE |
c19b0669 3918 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3919 if (intel_dp->link_mst)
0e32b39c
DA		 3920 val |= DP_TP_CTL_MODE_MST;
3921 else {
3922 val |= DP_TP_CTL_MODE_SST;
3923 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3924 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3925 }
c19b0669
PZ		 3926 I915_WRITE(DP_TP_CTL(port), val);
3927 POSTING_READ(DP_TP_CTL(port));
3928
3929 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3930 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3931 POSTING_READ(DDI_BUF_CTL(port));
3932
3933 udelay(600);
3934}
00c09d70 3935
2085cc5d
VS		 3936static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3937 enum transcoder cpu_transcoder)
9935f7fa 3938{
2085cc5d
VS		 3939 if (cpu_transcoder == TRANSCODER_EDP)
3940 return false;
9935f7fa 3941
2085cc5d
VS		 3942 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3943 return false;
3944
3945 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3946 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3947}
3948
53e9bf5e
VS		 3949void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3950 struct intel_crtc_state *crtc_state)
3951{
2dd24a9c 3952 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3953 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3954 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3955 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3956}
3957
6801c18c 3958void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3959 struct intel_crtc_state *pipe_config)
045ac3b5 3960{
fac5e23e 3961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3962 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3963 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
045ac3b5
JB		 3964 u32 temp, flags = 0;
3965
4d1de975
JN		 3966 /* XXX: DSI transcoder paranoia */
3967 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3968 return;
3969
045ac3b5
JB		 3970 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3971 if (temp & TRANS_DDI_PHSYNC)
3972 flags |= DRM_MODE_FLAG_PHSYNC;
3973 else
3974 flags |= DRM_MODE_FLAG_NHSYNC;
3975 if (temp & TRANS_DDI_PVSYNC)
3976 flags |= DRM_MODE_FLAG_PVSYNC;
3977 else
3978 flags |= DRM_MODE_FLAG_NVSYNC;
3979
2d112de7 3980 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3981
3982 switch (temp & TRANS_DDI_BPC_MASK) {
3983 case TRANS_DDI_BPC_6:
3984 pipe_config->pipe_bpp = 18;
3985 break;
3986 case TRANS_DDI_BPC_8:
3987 pipe_config->pipe_bpp = 24;
3988 break;
3989 case TRANS_DDI_BPC_10:
3990 pipe_config->pipe_bpp = 30;
3991 break;
3992 case TRANS_DDI_BPC_12:
3993 pipe_config->pipe_bpp = 36;
3994 break;
3995 default:
3996 break;
3997 }
eb14cb74
VS		 3998
3999 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4000 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 4001 pipe_config->has_hdmi_sink = true;
bbd440fb 4002
e5e70d4a
VS		 4003 pipe_config->infoframes.enable |=
4004 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4005
4006 if (pipe_config->infoframes.enable)
bbd440fb 4007 pipe_config->has_infoframe = true;
15953637 4008
ab2cb2cb 4009 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 4010 pipe_config->hdmi_scrambling = true;
4011 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4012 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 4013 /* fall through */
eb14cb74 4014 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 4015 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 4016 pipe_config->lane_count = 4;
4017 break;
eb14cb74 4018 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 4019 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 4020 break;
4021 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 4022 if (encoder->type == INTEL_OUTPUT_EDP)
4023 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4024 else
4025 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4026 pipe_config->lane_count =
4027 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4028 intel_dp_get_m_n(intel_crtc, pipe_config);
4029 break;
eb14cb74 4030 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 4031 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 4032 pipe_config->lane_count =
4033 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 4034 intel_dp_get_m_n(intel_crtc, pipe_config);
4035 break;
4036 default:
4037 break;
4038 }
10214420 4039
9935f7fa 4040 pipe_config->has_audio =
2085cc5d 4041 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 4042
6aa23e65
JN		 4043 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4044 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 4045 /*
4046 * This is a big fat ugly hack.
4047 *
4048 * Some machines in UEFI boot mode provide us a VBT that has 18
4049 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4050 * unknown we fail to light up. Yet the same BIOS boots up with
4051 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4052 * max, not what it tells us to use.
4053 *
4054 * Note: This will still be broken if the eDP panel is not lit
4055 * up by the BIOS, and thus we can't get the mode at module
4056 * load.
4057 */
4058 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 4059 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4060 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 4061 }
11578553 4062
22606a18 4063 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 4064
cc3f90f0 4065 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 4066 pipe_config->lane_lat_optim_mask =
4067 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 4068
4069 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 4070
4071 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4072
4073 intel_read_infoframe(encoder, pipe_config,
4074 HDMI_INFOFRAME_TYPE_AVI,
4075 &pipe_config->infoframes.avi);
4076 intel_read_infoframe(encoder, pipe_config,
4077 HDMI_INFOFRAME_TYPE_SPD,
4078 &pipe_config->infoframes.spd);
4079 intel_read_infoframe(encoder, pipe_config,
4080 HDMI_INFOFRAME_TYPE_VENDOR,
4081 &pipe_config->infoframes.hdmi);
b37f588e
US		 4082 intel_read_infoframe(encoder, pipe_config,
4083 HDMI_INFOFRAME_TYPE_DRM,
4084 &pipe_config->infoframes.drm);
045ac3b5
JB		 4085}
4086
7e732cac
VS		 4087static enum intel_output_type
4088intel_ddi_compute_output_type(struct intel_encoder *encoder,
4089 struct intel_crtc_state *crtc_state,
4090 struct drm_connector_state *conn_state)
4091{
4092 switch (conn_state->connector->connector_type) {
4093 case DRM_MODE_CONNECTOR_HDMIA:
4094 return INTEL_OUTPUT_HDMI;
4095 case DRM_MODE_CONNECTOR_eDP:
4096 return INTEL_OUTPUT_EDP;
4097 case DRM_MODE_CONNECTOR_DisplayPort:
4098 return INTEL_OUTPUT_DP;
4099 default:
4100 MISSING_CASE(conn_state->connector->connector_type);
4101 return INTEL_OUTPUT_UNUSED;
4102 }
4103}
4104
204474a6
LP		 4105static int intel_ddi_compute_config(struct intel_encoder *encoder,
4106 struct intel_crtc_state *pipe_config,
4107 struct drm_connector_state *conn_state)
00c09d70 4108{
dc0c0bfe 4109 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
fac5e23e 4110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 4111 enum port port = encoder->port;
95a7a2ae 4112 int ret;
00c09d70 4113
bc7e3525 4114 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 4115 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4116
7e732cac 4117 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 4118 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 4119 else
0a478c27 4120 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
7a412b8f
VS		 4121 if (ret)
4122 return ret;
95a7a2ae 4123
dc0c0bfe
VS		 4124 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4125 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4126 pipe_config->pch_pfit.force_thru =
4127 pipe_config->pch_pfit.enabled ||
4128 pipe_config->crc_enabled;
4129
7a412b8f 4130 if (IS_GEN9_LP(dev_priv))
95a7a2ae 4131 pipe_config->lane_lat_optim_mask =
5161d058 4132 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 4133
53e9bf5e
VS		 4134 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4135
7a412b8f 4136 return 0;
00c09d70
PZ		 4137}
4138
f6bff60e
ID		 4139static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4140{
4141 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
f6bff60e
ID		 4142
4143 intel_dp_encoder_flush_work(encoder);
4144
f6bff60e
ID		 4145 drm_encoder_cleanup(encoder);
4146 kfree(dig_port);
4147}
4148
00c09d70 4149static const struct drm_encoder_funcs intel_ddi_funcs = {
32691b58 4150 .reset = intel_dp_encoder_reset,
f6bff60e 4151 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 4152};
4153
4a28ae58
PZ		 4154static struct intel_connector *
4155intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4156{
4157 struct intel_connector *connector;
8f4f2797 4158 enum port port = intel_dig_port->base.port;
4a28ae58 4159
9bdbd0b9 4160 connector = intel_connector_alloc();
4a28ae58
PZ		 4161 if (!connector)
4162 return NULL;
4163
4164 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
97068c1b
VS		 4165 intel_dig_port->dp.prepare_link_retrain =
4166 intel_ddi_prepare_link_retrain;
4167
4a28ae58
PZ		 4168 if (!intel_dp_init_connector(intel_dig_port, connector)) {
4169 kfree(connector);
4170 return NULL;
4171 }
4172
4173 return connector;
4174}
4175
dba14b27
VS		 4176static int modeset_pipe(struct drm_crtc *crtc,
4177 struct drm_modeset_acquire_ctx *ctx)
4178{
4179 struct drm_atomic_state *state;
4180 struct drm_crtc_state *crtc_state;
4181 int ret;
4182
4183 state = drm_atomic_state_alloc(crtc->dev);
4184 if (!state)
4185 return -ENOMEM;
4186
4187 state->acquire_ctx = ctx;
4188
4189 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4190 if (IS_ERR(crtc_state)) {
4191 ret = PTR_ERR(crtc_state);
4192 goto out;
4193 }
4194
b8fe992a 4195 crtc_state->connectors_changed = true;
dba14b27 4196
dba14b27 4197 ret = drm_atomic_commit(state);
a551cd66 4198out:
dba14b27
VS		 4199 drm_atomic_state_put(state);
4200
4201 return ret;
4202}
4203
4204static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4205 struct drm_modeset_acquire_ctx *ctx)
4206{
4207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4208 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4209 struct intel_connector *connector = hdmi->attached_connector;
4210 struct i2c_adapter *adapter =
4211 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4212 struct drm_connector_state *conn_state;
4213 struct intel_crtc_state *crtc_state;
4214 struct intel_crtc *crtc;
4215 u8 config;
4216 int ret;
4217
4218 if (!connector || connector->base.status != connector_status_connected)
4219 return 0;
4220
4221 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4222 ctx);
4223 if (ret)
4224 return ret;
4225
4226 conn_state = connector->base.state;
4227
4228 crtc = to_intel_crtc(conn_state->crtc);
4229 if (!crtc)
4230 return 0;
4231
4232 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4233 if (ret)
4234 return ret;
4235
4236 crtc_state = to_intel_crtc_state(crtc->base.state);
4237
4238 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4239
4240 if (!crtc_state->base.active)
4241 return 0;
4242
4243 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4244 !crtc_state->hdmi_scrambling)
4245 return 0;
4246
4247 if (conn_state->commit &&
4248 !try_wait_for_completion(&conn_state->commit->hw_done))
4249 return 0;
4250
4251 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4252 if (ret < 0) {
4253 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4254 return 0;
4255 }
4256
4257 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4258 crtc_state->hdmi_high_tmds_clock_ratio &&
4259 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4260 crtc_state->hdmi_scrambling)
4261 return 0;
4262
4263 /*
4264 * HDMI 2.0 says that one should not send scrambled data
4265 * prior to configuring the sink scrambling, and that
4266 * TMDS clock/data transmission should be suspended when
4267 * changing the TMDS clock rate in the sink. So let's
4268 * just do a full modeset here, even though some sinks
4269 * would be perfectly happy if were to just reconfigure
4270 * the SCDC settings on the fly.
4271 */
4272 return modeset_pipe(&crtc->base, ctx);
4273}
4274
3944709d
ID		 4275static enum intel_hotplug_state
4276intel_ddi_hotplug(struct intel_encoder *encoder,
4277 struct intel_connector *connector,
4278 bool irq_received)
dba14b27 4279{
bb80c925 4280 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
dba14b27 4281 struct drm_modeset_acquire_ctx ctx;
3944709d 4282 enum intel_hotplug_state state;
dba14b27
VS		 4283 int ret;
4284
3944709d 4285 state = intel_encoder_hotplug(encoder, connector, irq_received);
dba14b27
VS		 4286
4287 drm_modeset_acquire_init(&ctx, 0);
4288
4289 for (;;) {
c85d200e
VS		 4290 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4291 ret = intel_hdmi_reset_link(encoder, &ctx);
4292 else
4293 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4294
4295 if (ret == -EDEADLK) {
4296 drm_modeset_backoff(&ctx);
4297 continue;
4298 }
4299
4300 break;
4301 }
4302
4303 drm_modeset_drop_locks(&ctx);
4304 drm_modeset_acquire_fini(&ctx);
4305 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4306
bb80c925
JRS		 4307 /*
4308 * Unpowered type-c dongles can take some time to boot and be
4309 * responsible, so here giving some time to those dongles to power up
4310 * and then retrying the probe.
4311 *
4312 * On many platforms the HDMI live state signal is known to be
4313 * unreliable, so we can't use it to detect if a sink is connected or
4314 * not. Instead we detect if it's connected based on whether we can
4315 * read the EDID or not. That in turn has a problem during disconnect,
4316 * since the HPD interrupt may be raised before the DDC lines get
4317 * disconnected (due to how the required length of DDC vs. HPD
4318 * connector pins are specified) and so we'll still be able to get a
4319 * valid EDID. To solve this schedule another detection cycle if this
4320 * time around we didn't detect any change in the sink's connection
4321 * status.
4322 */
4323 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4324 !dig_port->dp.is_mst)
4325 state = INTEL_HOTPLUG_RETRY;
4326
3944709d 4327 return state;
dba14b27
VS		 4328}
4329
4a28ae58
PZ		 4330static struct intel_connector *
4331intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4332{
4333 struct intel_connector *connector;
8f4f2797 4334 enum port port = intel_dig_port->base.port;
4a28ae58 4335
9bdbd0b9 4336 connector = intel_connector_alloc();
4a28ae58
PZ		 4337 if (!connector)
4338 return NULL;
4339
4340 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4341 intel_hdmi_init_connector(intel_dig_port, connector);
4342
4343 return connector;
4344}
4345
436009b5
RV		 4346static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4347{
4348 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4349
8f4f2797 4350 if (dport->base.port != PORT_A)
436009b5
RV		 4351 return false;
4352
4353 if (dport->saved_port_bits & DDI_A_4_LANES)
4354 return false;
4355
4356 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4357 * supported configuration
4358 */
4359 if (IS_GEN9_LP(dev_priv))
4360 return true;
4361
4362 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4363 * one who does also have a full A/E split called
4364 * DDI_F what makes DDI_E useless. However for this
4365 * case let's trust VBT info.
4366 */
4367 if (IS_CANNONLAKE(dev_priv) &&
4368 !intel_bios_is_port_present(dev_priv, PORT_E))
4369 return true;
4370
4371 return false;
4372}
4373
3d2011cf
MK		 4374static int
4375intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4376{
4377 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4378 enum port port = intel_dport->base.port;
4379 int max_lanes = 4;
4380
4381 if (INTEL_GEN(dev_priv) >= 11)
4382 return max_lanes;
4383
4384 if (port == PORT_A || port == PORT_E) {
4385 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4386 max_lanes = port == PORT_A ? 4 : 0;
4387 else
4388 /* Both A and E share 2 lanes */
4389 max_lanes = 2;
4390 }
4391
4392 /*
4393 * Some BIOS might fail to set this bit on port A if eDP
4394 * wasn't lit up at boot. Force this bit set when needed
4395 * so we use the proper lane count for our calculations.
4396 */
4397 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4398 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4399 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4400 max_lanes = 4;
4401 }
4402
4403 return max_lanes;
4404}
4405
c39055b0 4406void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4407{
f6bff60e
ID		 4408 struct ddi_vbt_port_info *port_info =
4409 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4410 struct intel_digital_port *intel_dig_port;
4411 struct intel_encoder *intel_encoder;
4412 struct drm_encoder *encoder;
ff662124 4413 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4414 enum pipe pipe;
d8fe2ab6 4415 enum phy phy = intel_port_to_phy(dev_priv, port);
10e7bec3 4416
f6bff60e
ID		 4417 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4418 init_dp = port_info->supports_dp;
ff662124
SS		 4419
4420 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4421 /*
4422 * Lspcon device needs to be driven with DP connector
4423 * with special detection sequence. So make sure DP
4424 * is initialized before lspcon.
4425 */
4426 init_dp = true;
4427 init_lspcon = true;
4428 init_hdmi = false;
4429 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4430 }
4431
311a2094 4432 if (!init_dp && !init_hdmi) {
500ea70d 4433 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4434 port_name(port));
500ea70d 4435 return;
311a2094 4436 }
00c09d70 4437
b14c5679 4438 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4439 if (!intel_dig_port)
4440 return;
4441
00c09d70
PZ		 4442 intel_encoder = &intel_dig_port->base;
4443 encoder = &intel_encoder->base;
4444
c39055b0 4445 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4446 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4447
c85d200e 4448 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4449 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4450 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4451 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4452 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4453 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4454 intel_encoder->pre_enable = intel_ddi_pre_enable;
4455 intel_encoder->disable = intel_disable_ddi;
4456 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4457 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4458 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4459 intel_encoder->get_config = intel_ddi_get_config;
a171f8e7 4460 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 4461 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4462 intel_encoder->type = INTEL_OUTPUT_DDI;
4463 intel_encoder->power_domain = intel_port_to_power_domain(port);
4464 intel_encoder->port = port;
3d2011cf 4465 intel_encoder->cloneable = 0;
570b16b5
MK		 4466 for_each_pipe(dev_priv, pipe)
4467 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4468
1e6aa7e5
JN		 4469 if (INTEL_GEN(dev_priv) >= 11)
4470 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4471 DDI_BUF_PORT_REVERSAL;
4472 else
4473 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4474 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4475 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4476 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4477 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4478
d8fe2ab6 4479 if (intel_phy_is_tc(dev_priv, phy)) {
ab7bc4e1
ID		 4480 bool is_legacy = !port_info->supports_typec_usb &&
4481 !port_info->supports_tbt;
4482
4483 intel_tc_port_init(intel_dig_port, is_legacy);
24a7bfe0
ID		 4484
4485 intel_encoder->update_prepare = intel_ddi_update_prepare;
4486 intel_encoder->update_complete = intel_ddi_update_complete;
ab7bc4e1 4487 }
f6bff60e 4488
62b69566
ACO		 4489 switch (port) {
4490 case PORT_A:
4491 intel_dig_port->ddi_io_power_domain =
4492 POWER_DOMAIN_PORT_DDI_A_IO;
4493 break;
4494 case PORT_B:
4495 intel_dig_port->ddi_io_power_domain =
4496 POWER_DOMAIN_PORT_DDI_B_IO;
4497 break;
4498 case PORT_C:
4499 intel_dig_port->ddi_io_power_domain =
4500 POWER_DOMAIN_PORT_DDI_C_IO;
4501 break;
4502 case PORT_D:
4503 intel_dig_port->ddi_io_power_domain =
4504 POWER_DOMAIN_PORT_DDI_D_IO;
4505 break;
4506 case PORT_E:
4507 intel_dig_port->ddi_io_power_domain =
4508 POWER_DOMAIN_PORT_DDI_E_IO;
4509 break;
9787e835
RV		 4510 case PORT_F:
4511 intel_dig_port->ddi_io_power_domain =
4512 POWER_DOMAIN_PORT_DDI_F_IO;
4513 break;
6c8337da
VK		 4514 case PORT_G:
4515 intel_dig_port->ddi_io_power_domain =
4516 POWER_DOMAIN_PORT_DDI_G_IO;
4517 break;
4518 case PORT_H:
4519 intel_dig_port->ddi_io_power_domain =
4520 POWER_DOMAIN_PORT_DDI_H_IO;
4521 break;
4522 case PORT_I:
4523 intel_dig_port->ddi_io_power_domain =
4524 POWER_DOMAIN_PORT_DDI_I_IO;
4525 break;
62b69566
ACO		 4526 default:
4527 MISSING_CASE(port);
4528 }
4529
f68d697e
CW		 4530 if (init_dp) {
4531 if (!intel_ddi_init_dp_connector(intel_dig_port))
4532 goto err;
13cf5504 4533
f68d697e 4534 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4535 }
21a8e6a4 4536
311a2094
PZ		 4537 /* In theory we don't need the encoder->type check, but leave it just in
4538 * case we have some really bad VBTs... */
f68d697e
CW		 4539 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4540 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4541 goto err;
21a8e6a4 4542 }
f68d697e 4543
ff662124
SS		 4544 if (init_lspcon) {
4545 if (lspcon_init(intel_dig_port))
4546 /* TODO: handle hdmi info frame part */
4547 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4548 port_name(port));
4549 else
4550 /*
4551 * LSPCON init faied, but DP init was success, so
4552 * lets try to drive as DP++ port.
4553 */
4554 DRM_ERROR("LSPCON init failed on port %c\n",
4555 port_name(port));
4556 }
4557
06c812d7 4558 intel_infoframe_init(intel_dig_port);
f6bff60e 4559
f68d697e
CW		 4560 return;
4561
4562err:
4563 drm_encoder_cleanup(encoder);
4564 kfree(intel_dig_port);
00c09d70 4565}
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