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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
dba14b27 | 28 | #include <drm/drm_scdc_helper.h> |
331c201a | 29 | |
45244b87 | 30 | #include "i915_drv.h" |
331c201a | 31 | #include "intel_audio.h" |
cfda08cd | 32 | #include "intel_combo_phy.h" |
ec7f29ff | 33 | #include "intel_connector.h" |
fdc24cf3 | 34 | #include "intel_ddi.h" |
1d455f8d | 35 | #include "intel_display_types.h" |
27fec1f9 | 36 | #include "intel_dp.h" |
e075094f | 37 | #include "intel_dp_link_training.h" |
b1ad4c39 | 38 | #include "intel_dpio_phy.h" |
1dd07e56 | 39 | #include "intel_dsi.h" |
8834e365 | 40 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 41 | #include "intel_gmbus.h" |
408bd917 | 42 | #include "intel_hdcp.h" |
0550691d | 43 | #include "intel_hdmi.h" |
dbeb38d9 | 44 | #include "intel_hotplug.h" |
f3e18947 | 45 | #include "intel_lspcon.h" |
44c1220a | 46 | #include "intel_panel.h" |
55367a27 | 47 | #include "intel_psr.h" |
bdacf087 | 48 | #include "intel_sprite.h" |
bc85328f | 49 | #include "intel_tc.h" |
b375d0ef | 50 | #include "intel_vdsc.h" |
45244b87 | 51 | |
10122051 JN |
52 | struct ddi_buf_trans { |
53 | u32 trans1; /* balance leg enable, de-emph level */ | |
54 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 55 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
56 | }; |
57 | ||
97eeb872 VS |
58 | static const u8 index_to_dp_signal_levels[] = { |
59 | [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
60 | [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
61 | [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
62 | [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, | |
63 | [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
64 | [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
65 | [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
66 | [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
67 | [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
68 | [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
69 | }; | |
70 | ||
45244b87 ED |
71 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
72 | * them for both DP and FDI transports, allowing those ports to | |
73 | * automatically adapt to HDMI connections as well | |
74 | */ | |
10122051 | 75 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
76 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
77 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
78 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
79 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
80 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
81 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
82 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
83 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
84 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
85 | }; |
86 | ||
10122051 | 87 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
88 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
89 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
90 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
91 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
92 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
93 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
94 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
95 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
96 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
97 | }; |
98 | ||
10122051 JN |
99 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
100 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
101 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
102 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
103 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
104 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
105 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
106 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
107 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
108 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
109 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
110 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
111 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
112 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
113 | }; |
114 | ||
10122051 | 115 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
116 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
117 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
118 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
119 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
120 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
121 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
122 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
123 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
124 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
125 | }; |
126 | ||
10122051 | 127 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
128 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
129 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
130 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
131 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
132 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
133 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
134 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
135 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
136 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
137 | }; |
138 | ||
10122051 | 139 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
140 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
141 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
142 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
143 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
144 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
145 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
146 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
147 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
148 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
149 | }; |
150 | ||
10122051 JN |
151 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
152 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
153 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
154 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
155 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
156 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
157 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
158 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
159 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
160 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
161 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
162 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
163 | }; |
164 | ||
5f8b2531 | 165 | /* Skylake H and S */ |
7f88e3af | 166 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
167 | { 0x00002016, 0x000000A0, 0x0 }, |
168 | { 0x00005012, 0x0000009B, 0x0 }, | |
169 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 170 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
171 | { 0x00002016, 0x0000009B, 0x0 }, |
172 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 173 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 174 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 175 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
176 | }; |
177 | ||
f8896f5d DW |
178 | /* Skylake U */ |
179 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 180 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 181 | { 0x00005012, 0x00000088, 0x0 }, |
5ac90567 | 182 | { 0x80007011, 0x000000CD, 0x1 }, |
d7097cff | 183 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 184 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
185 | { 0x80005012, 0x000000C0, 0x1 }, |
186 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 187 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 188 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
189 | }; |
190 | ||
5f8b2531 RV |
191 | /* Skylake Y */ |
192 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
193 | { 0x00000018, 0x000000A2, 0x0 }, |
194 | { 0x00005012, 0x00000088, 0x0 }, | |
5ac90567 | 195 | { 0x80007011, 0x000000CD, 0x3 }, |
d7097cff | 196 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 197 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
198 | { 0x80005012, 0x000000C0, 0x3 }, |
199 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 200 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 201 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
202 | }; |
203 | ||
0fdd4918 RV |
204 | /* Kabylake H and S */ |
205 | static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { | |
206 | { 0x00002016, 0x000000A0, 0x0 }, | |
207 | { 0x00005012, 0x0000009B, 0x0 }, | |
208 | { 0x00007011, 0x00000088, 0x0 }, | |
209 | { 0x80009010, 0x000000C0, 0x1 }, | |
210 | { 0x00002016, 0x0000009B, 0x0 }, | |
211 | { 0x00005012, 0x00000088, 0x0 }, | |
212 | { 0x80007011, 0x000000C0, 0x1 }, | |
213 | { 0x00002016, 0x00000097, 0x0 }, | |
214 | { 0x80005012, 0x000000C0, 0x1 }, | |
215 | }; | |
216 | ||
217 | /* Kabylake U */ | |
218 | static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { | |
219 | { 0x0000201B, 0x000000A1, 0x0 }, | |
220 | { 0x00005012, 0x00000088, 0x0 }, | |
221 | { 0x80007011, 0x000000CD, 0x3 }, | |
222 | { 0x80009010, 0x000000C0, 0x3 }, | |
223 | { 0x0000201B, 0x0000009D, 0x0 }, | |
224 | { 0x80005012, 0x000000C0, 0x3 }, | |
225 | { 0x80007011, 0x000000C0, 0x3 }, | |
226 | { 0x00002016, 0x0000004F, 0x0 }, | |
227 | { 0x80005012, 0x000000C0, 0x3 }, | |
228 | }; | |
229 | ||
230 | /* Kabylake Y */ | |
231 | static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { | |
232 | { 0x00001017, 0x000000A1, 0x0 }, | |
233 | { 0x00005012, 0x00000088, 0x0 }, | |
234 | { 0x80007011, 0x000000CD, 0x3 }, | |
235 | { 0x8000800F, 0x000000C0, 0x3 }, | |
236 | { 0x00001017, 0x0000009D, 0x0 }, | |
237 | { 0x80005012, 0x000000C0, 0x3 }, | |
238 | { 0x80007011, 0x000000C0, 0x3 }, | |
239 | { 0x00001017, 0x0000004C, 0x0 }, | |
240 | { 0x80005012, 0x000000C0, 0x3 }, | |
241 | }; | |
242 | ||
f8896f5d | 243 | /* |
0fdd4918 | 244 | * Skylake/Kabylake H and S |
f8896f5d DW |
245 | * eDP 1.4 low vswing translation parameters |
246 | */ | |
7ad14a29 | 247 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
248 | { 0x00000018, 0x000000A8, 0x0 }, |
249 | { 0x00004013, 0x000000A9, 0x0 }, | |
250 | { 0x00007011, 0x000000A2, 0x0 }, | |
251 | { 0x00009010, 0x0000009C, 0x0 }, | |
252 | { 0x00000018, 0x000000A9, 0x0 }, | |
253 | { 0x00006013, 0x000000A2, 0x0 }, | |
254 | { 0x00007011, 0x000000A6, 0x0 }, | |
255 | { 0x00000018, 0x000000AB, 0x0 }, | |
256 | { 0x00007013, 0x0000009F, 0x0 }, | |
257 | { 0x00000018, 0x000000DF, 0x0 }, | |
258 | }; | |
259 | ||
260 | /* | |
0fdd4918 | 261 | * Skylake/Kabylake U |
f8896f5d DW |
262 | * eDP 1.4 low vswing translation parameters |
263 | */ | |
264 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
265 | { 0x00000018, 0x000000A8, 0x0 }, | |
266 | { 0x00004013, 0x000000A9, 0x0 }, | |
267 | { 0x00007011, 0x000000A2, 0x0 }, | |
268 | { 0x00009010, 0x0000009C, 0x0 }, | |
269 | { 0x00000018, 0x000000A9, 0x0 }, | |
270 | { 0x00006013, 0x000000A2, 0x0 }, | |
271 | { 0x00007011, 0x000000A6, 0x0 }, | |
272 | { 0x00002016, 0x000000AB, 0x0 }, | |
273 | { 0x00005013, 0x0000009F, 0x0 }, | |
274 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
275 | }; |
276 | ||
f8896f5d | 277 | /* |
0fdd4918 | 278 | * Skylake/Kabylake Y |
f8896f5d DW |
279 | * eDP 1.4 low vswing translation parameters |
280 | */ | |
5f8b2531 | 281 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
282 | { 0x00000018, 0x000000A8, 0x0 }, |
283 | { 0x00004013, 0x000000AB, 0x0 }, | |
284 | { 0x00007011, 0x000000A4, 0x0 }, | |
285 | { 0x00009010, 0x000000DF, 0x0 }, | |
286 | { 0x00000018, 0x000000AA, 0x0 }, | |
287 | { 0x00006013, 0x000000A4, 0x0 }, | |
288 | { 0x00007011, 0x0000009D, 0x0 }, | |
289 | { 0x00000018, 0x000000A0, 0x0 }, | |
290 | { 0x00006012, 0x000000DF, 0x0 }, | |
291 | { 0x00000018, 0x0000008A, 0x0 }, | |
292 | }; | |
7ad14a29 | 293 | |
0fdd4918 | 294 | /* Skylake/Kabylake U, H and S */ |
7f88e3af | 295 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
296 | { 0x00000018, 0x000000AC, 0x0 }, |
297 | { 0x00005012, 0x0000009D, 0x0 }, | |
298 | { 0x00007011, 0x00000088, 0x0 }, | |
299 | { 0x00000018, 0x000000A1, 0x0 }, | |
300 | { 0x00000018, 0x00000098, 0x0 }, | |
301 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 302 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 303 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
304 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
305 | { 0x80003015, 0x000000C0, 0x1 }, | |
306 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
307 | }; |
308 | ||
0fdd4918 | 309 | /* Skylake/Kabylake Y */ |
5f8b2531 | 310 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
f8896f5d DW |
311 | { 0x00000018, 0x000000A1, 0x0 }, |
312 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 313 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
314 | { 0x00000018, 0x000000A4, 0x0 }, |
315 | { 0x00000018, 0x0000009D, 0x0 }, | |
316 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 317 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 318 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
319 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
320 | { 0x80003015, 0x000000C0, 0x3 }, | |
321 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
322 | }; |
323 | ||
96fb9f9b | 324 | struct bxt_ddi_buf_trans { |
ac3ad6c6 VS |
325 | u8 margin; /* swing value */ |
326 | u8 scale; /* scale value */ | |
327 | u8 enable; /* scale enable */ | |
328 | u8 deemphasis; | |
96fb9f9b VK |
329 | }; |
330 | ||
96fb9f9b VK |
331 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
332 | /* Idx NT mV diff db */ | |
043eaf36 VS |
333 | { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ |
334 | { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ | |
335 | { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ | |
336 | { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ | |
337 | { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ | |
338 | { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ | |
339 | { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ | |
340 | { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ | |
341 | { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ | |
342 | { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ | |
96fb9f9b VK |
343 | }; |
344 | ||
d9d7000d SJ |
345 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
346 | /* Idx NT mV diff db */ | |
043eaf36 VS |
347 | { 26, 0, 0, 128, }, /* 0: 200 0 */ |
348 | { 38, 0, 0, 112, }, /* 1: 200 1.5 */ | |
349 | { 48, 0, 0, 96, }, /* 2: 200 4 */ | |
350 | { 54, 0, 0, 69, }, /* 3: 200 6 */ | |
351 | { 32, 0, 0, 128, }, /* 4: 250 0 */ | |
352 | { 48, 0, 0, 104, }, /* 5: 250 1.5 */ | |
353 | { 54, 0, 0, 85, }, /* 6: 250 4 */ | |
354 | { 43, 0, 0, 128, }, /* 7: 300 0 */ | |
355 | { 54, 0, 0, 101, }, /* 8: 300 1.5 */ | |
356 | { 48, 0, 0, 128, }, /* 9: 300 0 */ | |
d9d7000d SJ |
357 | }; |
358 | ||
96fb9f9b VK |
359 | /* BSpec has 2 recommended values - entries 0 and 8. |
360 | * Using the entry with higher vswing. | |
361 | */ | |
362 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
363 | /* Idx NT mV diff db */ | |
043eaf36 VS |
364 | { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ |
365 | { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ | |
366 | { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ | |
367 | { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ | |
368 | { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ | |
369 | { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ | |
370 | { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ | |
371 | { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ | |
372 | { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ | |
373 | { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ | |
96fb9f9b VK |
374 | }; |
375 | ||
83fb7ab4 | 376 | struct cnl_ddi_buf_trans { |
fb5f4e96 VS |
377 | u8 dw2_swing_sel; |
378 | u8 dw7_n_scalar; | |
379 | u8 dw4_cursor_coeff; | |
380 | u8 dw4_post_cursor_2; | |
381 | u8 dw4_post_cursor_1; | |
83fb7ab4 RV |
382 | }; |
383 | ||
384 | /* Voltage Swing Programming for VccIO 0.85V for DP */ | |
385 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { | |
386 | /* NT mV Trans mV db */ | |
387 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
388 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ | |
389 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ | |
390 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ | |
391 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
392 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ | |
393 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ | |
394 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ | |
395 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ | |
396 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
397 | }; | |
398 | ||
399 | /* Voltage Swing Programming for VccIO 0.85V for HDMI */ | |
400 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { | |
401 | /* NT mV Trans mV db */ | |
402 | { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
403 | { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ | |
404 | { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ | |
405 | { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ | |
406 | { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ | |
407 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ | |
408 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
409 | }; | |
410 | ||
411 | /* Voltage Swing Programming for VccIO 0.85V for eDP */ | |
412 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { | |
413 | /* NT mV Trans mV db */ | |
414 | { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
415 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
416 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
417 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
418 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
419 | { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
420 | { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ | |
421 | { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ | |
422 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
423 | }; | |
424 | ||
425 | /* Voltage Swing Programming for VccIO 0.95V for DP */ | |
426 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { | |
427 | /* NT mV Trans mV db */ | |
428 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
429 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ | |
430 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ | |
431 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ | |
432 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
433 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ | |
434 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ | |
435 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ | |
436 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ | |
437 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
438 | }; | |
439 | ||
440 | /* Voltage Swing Programming for VccIO 0.95V for HDMI */ | |
441 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { | |
442 | /* NT mV Trans mV db */ | |
443 | { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
444 | { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
445 | { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
446 | { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
447 | { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
448 | { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
449 | { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ | |
450 | { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ | |
451 | { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ | |
452 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ | |
453 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
454 | }; | |
455 | ||
456 | /* Voltage Swing Programming for VccIO 0.95V for eDP */ | |
457 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { | |
458 | /* NT mV Trans mV db */ | |
459 | { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
460 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
461 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
462 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
463 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
464 | { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
465 | { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ | |
466 | { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ | |
467 | { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ | |
468 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
469 | }; | |
470 | ||
471 | /* Voltage Swing Programming for VccIO 1.05V for DP */ | |
472 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { | |
473 | /* NT mV Trans mV db */ | |
474 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
475 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
476 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
477 | { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ | |
478 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
479 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
480 | { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ | |
481 | { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ | |
482 | { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ | |
483 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
484 | }; | |
485 | ||
486 | /* Voltage Swing Programming for VccIO 1.05V for HDMI */ | |
487 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { | |
488 | /* NT mV Trans mV db */ | |
489 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
490 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
491 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
492 | { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
493 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
494 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
495 | { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ | |
496 | { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ | |
497 | { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ | |
498 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ | |
499 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
500 | }; | |
501 | ||
502 | /* Voltage Swing Programming for VccIO 1.05V for eDP */ | |
503 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { | |
504 | /* NT mV Trans mV db */ | |
505 | { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
506 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
507 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
508 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
509 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
510 | { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
511 | { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ | |
512 | { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ | |
513 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
514 | }; | |
515 | ||
b265a2a6 CT |
516 | /* icl_combo_phy_ddi_translations */ |
517 | static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { | |
518 | /* NT mV Trans mV db */ | |
519 | { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
520 | { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ | |
521 | { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ | |
522 | { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ | |
523 | { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
524 | { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ | |
525 | { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ | |
526 | { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ | |
527 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ | |
528 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
19b904f8 MN |
529 | }; |
530 | ||
b265a2a6 CT |
531 | static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { |
532 | /* NT mV Trans mV db */ | |
533 | { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ | |
534 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ | |
535 | { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ | |
536 | { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ | |
537 | { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ | |
538 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ | |
539 | { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ | |
540 | { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ | |
541 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ | |
542 | { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
19b904f8 MN |
543 | }; |
544 | ||
b265a2a6 CT |
545 | static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { |
546 | /* NT mV Trans mV db */ | |
547 | { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
548 | { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ | |
549 | { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ | |
550 | { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ | |
551 | { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
552 | { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ | |
553 | { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ | |
554 | { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ | |
555 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ | |
556 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
19b904f8 MN |
557 | }; |
558 | ||
b265a2a6 CT |
559 | static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { |
560 | /* NT mV Trans mV db */ | |
561 | { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
562 | { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ | |
563 | { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ | |
564 | { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ | |
565 | { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ | |
566 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ | |
567 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
19b904f8 MN |
568 | }; |
569 | ||
cd96bea7 MN |
570 | struct icl_mg_phy_ddi_buf_trans { |
571 | u32 cri_txdeemph_override_5_0; | |
572 | u32 cri_txdeemph_override_11_6; | |
573 | u32 cri_txdeemph_override_17_12; | |
574 | }; | |
575 | ||
576 | static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { | |
577 | /* Voltage swing pre-emphasis */ | |
578 | { 0x0, 0x1B, 0x00 }, /* 0 0 */ | |
579 | { 0x0, 0x23, 0x08 }, /* 0 1 */ | |
580 | { 0x0, 0x2D, 0x12 }, /* 0 2 */ | |
581 | { 0x0, 0x00, 0x00 }, /* 0 3 */ | |
582 | { 0x0, 0x23, 0x00 }, /* 1 0 */ | |
583 | { 0x0, 0x2B, 0x09 }, /* 1 1 */ | |
584 | { 0x0, 0x2E, 0x11 }, /* 1 2 */ | |
585 | { 0x0, 0x2F, 0x00 }, /* 2 0 */ | |
586 | { 0x0, 0x33, 0x0C }, /* 2 1 */ | |
587 | { 0x0, 0x00, 0x00 }, /* 3 0 */ | |
588 | }; | |
589 | ||
978c3e53 CT |
590 | struct tgl_dkl_phy_ddi_buf_trans { |
591 | u32 dkl_vswing_control; | |
592 | u32 dkl_preshoot_control; | |
593 | u32 dkl_de_emphasis_control; | |
594 | }; | |
595 | ||
596 | static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = { | |
597 | /* VS pre-emp Non-trans mV Pre-emph dB */ | |
598 | { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ | |
599 | { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ | |
600 | { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ | |
601 | { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ | |
602 | { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ | |
603 | { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ | |
604 | { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ | |
605 | { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ | |
606 | { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ | |
607 | { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ | |
608 | }; | |
609 | ||
a930acd9 VS |
610 | static const struct ddi_buf_trans * |
611 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
612 | { | |
613 | if (dev_priv->vbt.edp.low_vswing) { | |
614 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
615 | return bdw_ddi_translations_edp; | |
616 | } else { | |
617 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
618 | return bdw_ddi_translations_dp; | |
619 | } | |
620 | } | |
621 | ||
acee2998 | 622 | static const struct ddi_buf_trans * |
78ab0bae | 623 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 624 | { |
0fdd4918 | 625 | if (IS_SKL_ULX(dev_priv)) { |
5f8b2531 | 626 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 627 | return skl_y_ddi_translations_dp; |
0fdd4918 | 628 | } else if (IS_SKL_ULT(dev_priv)) { |
f8896f5d | 629 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 630 | return skl_u_ddi_translations_dp; |
f8896f5d | 631 | } else { |
f8896f5d | 632 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 633 | return skl_ddi_translations_dp; |
f8896f5d | 634 | } |
f8896f5d DW |
635 | } |
636 | ||
0fdd4918 RV |
637 | static const struct ddi_buf_trans * |
638 | kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
639 | { | |
6ce1c33d | 640 | if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { |
0fdd4918 RV |
641 | *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); |
642 | return kbl_y_ddi_translations_dp; | |
da411a48 | 643 | } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { |
0fdd4918 RV |
644 | *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); |
645 | return kbl_u_ddi_translations_dp; | |
646 | } else { | |
647 | *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); | |
648 | return kbl_ddi_translations_dp; | |
649 | } | |
650 | } | |
651 | ||
acee2998 | 652 | static const struct ddi_buf_trans * |
78ab0bae | 653 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 654 | { |
06411f08 | 655 | if (dev_priv->vbt.edp.low_vswing) { |
6ce1c33d VS |
656 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || |
657 | IS_CFL_ULX(dev_priv)) { | |
5f8b2531 | 658 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 659 | return skl_y_ddi_translations_edp; |
da411a48 RV |
660 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || |
661 | IS_CFL_ULT(dev_priv)) { | |
f8896f5d | 662 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 663 | return skl_u_ddi_translations_edp; |
f8896f5d | 664 | } else { |
f8896f5d | 665 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 666 | return skl_ddi_translations_edp; |
f8896f5d DW |
667 | } |
668 | } | |
cd1101cb | 669 | |
da411a48 | 670 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
0fdd4918 RV |
671 | return kbl_get_buf_trans_dp(dev_priv, n_entries); |
672 | else | |
673 | return skl_get_buf_trans_dp(dev_priv, n_entries); | |
f8896f5d DW |
674 | } |
675 | ||
676 | static const struct ddi_buf_trans * | |
78ab0bae | 677 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 678 | { |
6ce1c33d VS |
679 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || |
680 | IS_CFL_ULX(dev_priv)) { | |
5f8b2531 | 681 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 682 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 683 | } else { |
f8896f5d | 684 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 685 | return skl_ddi_translations_hdmi; |
f8896f5d | 686 | } |
f8896f5d DW |
687 | } |
688 | ||
edba48fd VS |
689 | static int skl_buf_trans_num_entries(enum port port, int n_entries) |
690 | { | |
691 | /* Only DDIA and DDIE can select the 10th register with DP */ | |
692 | if (port == PORT_A || port == PORT_E) | |
693 | return min(n_entries, 10); | |
694 | else | |
695 | return min(n_entries, 9); | |
696 | } | |
697 | ||
d8fe2c7f VS |
698 | static const struct ddi_buf_trans * |
699 | intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, | |
edba48fd | 700 | enum port port, int *n_entries) |
d8fe2c7f VS |
701 | { |
702 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { | |
edba48fd VS |
703 | const struct ddi_buf_trans *ddi_translations = |
704 | kbl_get_buf_trans_dp(dev_priv, n_entries); | |
705 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
706 | return ddi_translations; | |
d8fe2c7f | 707 | } else if (IS_SKYLAKE(dev_priv)) { |
edba48fd VS |
708 | const struct ddi_buf_trans *ddi_translations = |
709 | skl_get_buf_trans_dp(dev_priv, n_entries); | |
710 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
711 | return ddi_translations; | |
d8fe2c7f VS |
712 | } else if (IS_BROADWELL(dev_priv)) { |
713 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
714 | return bdw_ddi_translations_dp; | |
715 | } else if (IS_HASWELL(dev_priv)) { | |
716 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
717 | return hsw_ddi_translations_dp; | |
718 | } | |
719 | ||
720 | *n_entries = 0; | |
721 | return NULL; | |
722 | } | |
723 | ||
724 | static const struct ddi_buf_trans * | |
725 | intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, | |
edba48fd | 726 | enum port port, int *n_entries) |
d8fe2c7f VS |
727 | { |
728 | if (IS_GEN9_BC(dev_priv)) { | |
edba48fd VS |
729 | const struct ddi_buf_trans *ddi_translations = |
730 | skl_get_buf_trans_edp(dev_priv, n_entries); | |
731 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
732 | return ddi_translations; | |
d8fe2c7f VS |
733 | } else if (IS_BROADWELL(dev_priv)) { |
734 | return bdw_get_buf_trans_edp(dev_priv, n_entries); | |
735 | } else if (IS_HASWELL(dev_priv)) { | |
736 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
737 | return hsw_ddi_translations_dp; | |
738 | } | |
739 | ||
740 | *n_entries = 0; | |
741 | return NULL; | |
742 | } | |
743 | ||
744 | static const struct ddi_buf_trans * | |
745 | intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, | |
746 | int *n_entries) | |
747 | { | |
748 | if (IS_BROADWELL(dev_priv)) { | |
749 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); | |
750 | return bdw_ddi_translations_fdi; | |
751 | } else if (IS_HASWELL(dev_priv)) { | |
752 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); | |
753 | return hsw_ddi_translations_fdi; | |
754 | } | |
755 | ||
756 | *n_entries = 0; | |
757 | return NULL; | |
758 | } | |
759 | ||
975786ee VS |
760 | static const struct ddi_buf_trans * |
761 | intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, | |
762 | int *n_entries) | |
763 | { | |
764 | if (IS_GEN9_BC(dev_priv)) { | |
765 | return skl_get_buf_trans_hdmi(dev_priv, n_entries); | |
766 | } else if (IS_BROADWELL(dev_priv)) { | |
767 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
768 | return bdw_ddi_translations_hdmi; | |
769 | } else if (IS_HASWELL(dev_priv)) { | |
770 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
771 | return hsw_ddi_translations_hdmi; | |
772 | } | |
773 | ||
774 | *n_entries = 0; | |
775 | return NULL; | |
776 | } | |
777 | ||
7d4f37b5 VS |
778 | static const struct bxt_ddi_buf_trans * |
779 | bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
780 | { | |
781 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); | |
782 | return bxt_ddi_translations_dp; | |
783 | } | |
784 | ||
785 | static const struct bxt_ddi_buf_trans * | |
786 | bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
787 | { | |
788 | if (dev_priv->vbt.edp.low_vswing) { | |
789 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); | |
790 | return bxt_ddi_translations_edp; | |
791 | } | |
792 | ||
793 | return bxt_get_buf_trans_dp(dev_priv, n_entries); | |
794 | } | |
795 | ||
796 | static const struct bxt_ddi_buf_trans * | |
797 | bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) | |
798 | { | |
799 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
800 | return bxt_ddi_translations_hdmi; | |
801 | } | |
802 | ||
cf3e0fb4 RV |
803 | static const struct cnl_ddi_buf_trans * |
804 | cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) | |
805 | { | |
806 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
807 | ||
808 | if (voltage == VOLTAGE_INFO_0_85V) { | |
809 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); | |
810 | return cnl_ddi_translations_hdmi_0_85V; | |
811 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
812 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); | |
813 | return cnl_ddi_translations_hdmi_0_95V; | |
814 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
815 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); | |
816 | return cnl_ddi_translations_hdmi_1_05V; | |
83482ca3 AB |
817 | } else { |
818 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 819 | MISSING_CASE(voltage); |
83482ca3 | 820 | } |
cf3e0fb4 RV |
821 | return NULL; |
822 | } | |
823 | ||
824 | static const struct cnl_ddi_buf_trans * | |
825 | cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
826 | { | |
827 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
828 | ||
829 | if (voltage == VOLTAGE_INFO_0_85V) { | |
830 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); | |
831 | return cnl_ddi_translations_dp_0_85V; | |
832 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
833 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); | |
834 | return cnl_ddi_translations_dp_0_95V; | |
835 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
836 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); | |
837 | return cnl_ddi_translations_dp_1_05V; | |
83482ca3 AB |
838 | } else { |
839 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 840 | MISSING_CASE(voltage); |
83482ca3 | 841 | } |
cf3e0fb4 RV |
842 | return NULL; |
843 | } | |
844 | ||
845 | static const struct cnl_ddi_buf_trans * | |
846 | cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
847 | { | |
848 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
849 | ||
850 | if (dev_priv->vbt.edp.low_vswing) { | |
851 | if (voltage == VOLTAGE_INFO_0_85V) { | |
852 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); | |
853 | return cnl_ddi_translations_edp_0_85V; | |
854 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
855 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); | |
856 | return cnl_ddi_translations_edp_0_95V; | |
857 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
858 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); | |
859 | return cnl_ddi_translations_edp_1_05V; | |
83482ca3 AB |
860 | } else { |
861 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 862 | MISSING_CASE(voltage); |
83482ca3 | 863 | } |
cf3e0fb4 RV |
864 | return NULL; |
865 | } else { | |
866 | return cnl_get_buf_trans_dp(dev_priv, n_entries); | |
867 | } | |
868 | } | |
869 | ||
b265a2a6 | 870 | static const struct cnl_ddi_buf_trans * |
4a8134d5 MR |
871 | icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, |
872 | int *n_entries) | |
fb5c8e9d | 873 | { |
b265a2a6 CT |
874 | if (type == INTEL_OUTPUT_HDMI) { |
875 | *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); | |
876 | return icl_combo_phy_ddi_translations_hdmi; | |
877 | } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { | |
878 | *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); | |
879 | return icl_combo_phy_ddi_translations_edp_hbr3; | |
880 | } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { | |
881 | *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); | |
882 | return icl_combo_phy_ddi_translations_edp_hbr2; | |
fb5c8e9d | 883 | } |
b265a2a6 CT |
884 | |
885 | *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); | |
886 | return icl_combo_phy_ddi_translations_dp_hbr2; | |
fb5c8e9d MN |
887 | } |
888 | ||
8d8bb85e VS |
889 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
890 | { | |
d02ace87 | 891 | int n_entries, level, default_entry; |
d8fe2ab6 | 892 | enum phy phy = intel_port_to_phy(dev_priv, port); |
8d8bb85e | 893 | |
d02ace87 | 894 | level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
8d8bb85e | 895 | |
978c3e53 CT |
896 | if (INTEL_GEN(dev_priv) >= 12) { |
897 | if (intel_phy_is_combo(dev_priv, phy)) | |
898 | icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, | |
899 | 0, &n_entries); | |
900 | else | |
901 | n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); | |
902 | default_entry = n_entries - 1; | |
903 | } else if (INTEL_GEN(dev_priv) == 11) { | |
d8fe2ab6 | 904 | if (intel_phy_is_combo(dev_priv, phy)) |
4a8134d5 | 905 | icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, |
b265a2a6 | 906 | 0, &n_entries); |
dccc7228 MN |
907 | else |
908 | n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); | |
909 | default_entry = n_entries - 1; | |
910 | } else if (IS_CANNONLAKE(dev_priv)) { | |
d02ace87 VS |
911 | cnl_get_buf_trans_hdmi(dev_priv, &n_entries); |
912 | default_entry = n_entries - 1; | |
043eaf36 | 913 | } else if (IS_GEN9_LP(dev_priv)) { |
d02ace87 VS |
914 | bxt_get_buf_trans_hdmi(dev_priv, &n_entries); |
915 | default_entry = n_entries - 1; | |
bf503556 | 916 | } else if (IS_GEN9_BC(dev_priv)) { |
d02ace87 VS |
917 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
918 | default_entry = 8; | |
8d8bb85e | 919 | } else if (IS_BROADWELL(dev_priv)) { |
d02ace87 VS |
920 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
921 | default_entry = 7; | |
8d8bb85e | 922 | } else if (IS_HASWELL(dev_priv)) { |
d02ace87 VS |
923 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
924 | default_entry = 6; | |
8d8bb85e VS |
925 | } else { |
926 | WARN(1, "ddi translation table missing\n"); | |
975786ee | 927 | return 0; |
8d8bb85e VS |
928 | } |
929 | ||
930 | /* Choose a good default if VBT is badly populated */ | |
d02ace87 VS |
931 | if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries) |
932 | level = default_entry; | |
8d8bb85e | 933 | |
d02ace87 | 934 | if (WARN_ON_ONCE(n_entries == 0)) |
21b39d2a | 935 | return 0; |
d02ace87 VS |
936 | if (WARN_ON_ONCE(level >= n_entries)) |
937 | level = n_entries - 1; | |
21b39d2a | 938 | |
d02ace87 | 939 | return level; |
8d8bb85e VS |
940 | } |
941 | ||
e58623cb AR |
942 | /* |
943 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
32bdc400 VS |
944 | * values in advance. This function programs the correct values for |
945 | * DP/eDP/FDI use cases. | |
45244b87 | 946 | */ |
3a6d84e6 VS |
947 | static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, |
948 | const struct intel_crtc_state *crtc_state) | |
45244b87 | 949 | { |
6a7e4f99 | 950 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 951 | u32 iboost_bit = 0; |
7d1c42e6 | 952 | int i, n_entries; |
0fce04c8 | 953 | enum port port = encoder->port; |
10122051 | 954 | const struct ddi_buf_trans *ddi_translations; |
e58623cb | 955 | |
3a6d84e6 VS |
956 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) |
957 | ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, | |
958 | &n_entries); | |
959 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) | |
edba48fd | 960 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, |
7d1c42e6 | 961 | &n_entries); |
3a6d84e6 | 962 | else |
edba48fd | 963 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, |
7d1c42e6 | 964 | &n_entries); |
e58623cb | 965 | |
edba48fd VS |
966 | /* If we're boosting the current, set bit 31 of trans1 */ |
967 | if (IS_GEN9_BC(dev_priv) && | |
968 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) | |
969 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
45244b87 | 970 | |
7d1c42e6 | 971 | for (i = 0; i < n_entries; i++) { |
9712e688 VS |
972 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
973 | ddi_translations[i].trans1 | iboost_bit); | |
974 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
975 | ddi_translations[i].trans2); | |
45244b87 | 976 | } |
32bdc400 VS |
977 | } |
978 | ||
979 | /* | |
980 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
981 | * values in advance. This function programs the correct values for | |
982 | * HDMI/DVI use cases. | |
983 | */ | |
7ea79333 | 984 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, |
d02ace87 | 985 | int level) |
32bdc400 VS |
986 | { |
987 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
988 | u32 iboost_bit = 0; | |
d02ace87 | 989 | int n_entries; |
0fce04c8 | 990 | enum port port = encoder->port; |
d02ace87 | 991 | const struct ddi_buf_trans *ddi_translations; |
ce4dd49e | 992 | |
d02ace87 | 993 | ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
1edaaa2f | 994 | |
d02ace87 | 995 | if (WARN_ON_ONCE(!ddi_translations)) |
21b39d2a | 996 | return; |
d02ace87 VS |
997 | if (WARN_ON_ONCE(level >= n_entries)) |
998 | level = n_entries - 1; | |
21b39d2a | 999 | |
975786ee VS |
1000 | /* If we're boosting the current, set bit 31 of trans1 */ |
1001 | if (IS_GEN9_BC(dev_priv) && | |
1002 | dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) | |
1003 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
32bdc400 | 1004 | |
6acab15a | 1005 | /* Entry 9 is for HDMI: */ |
ed9c77d2 | 1006 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
d02ace87 | 1007 | ddi_translations[level].trans1 | iboost_bit); |
ed9c77d2 | 1008 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
d02ace87 | 1009 | ddi_translations[level].trans2); |
45244b87 ED |
1010 | } |
1011 | ||
248138b5 PZ |
1012 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
1013 | enum port port) | |
1014 | { | |
f0f59a00 | 1015 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
1016 | int i; |
1017 | ||
3449ca85 | 1018 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
1019 | udelay(1); |
1020 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
1021 | return; | |
1022 | } | |
1023 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
1024 | } | |
c82e4d26 | 1025 | |
3d0c5005 | 1026 | static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) |
c856052a | 1027 | { |
0823eb9c | 1028 | switch (pll->info->id) { |
c856052a ACO |
1029 | case DPLL_ID_WRPLL1: |
1030 | return PORT_CLK_SEL_WRPLL1; | |
1031 | case DPLL_ID_WRPLL2: | |
1032 | return PORT_CLK_SEL_WRPLL2; | |
1033 | case DPLL_ID_SPLL: | |
1034 | return PORT_CLK_SEL_SPLL; | |
1035 | case DPLL_ID_LCPLL_810: | |
1036 | return PORT_CLK_SEL_LCPLL_810; | |
1037 | case DPLL_ID_LCPLL_1350: | |
1038 | return PORT_CLK_SEL_LCPLL_1350; | |
1039 | case DPLL_ID_LCPLL_2700: | |
1040 | return PORT_CLK_SEL_LCPLL_2700; | |
1041 | default: | |
0823eb9c | 1042 | MISSING_CASE(pll->info->id); |
c856052a ACO |
1043 | return PORT_CLK_SEL_NONE; |
1044 | } | |
1045 | } | |
1046 | ||
20fd2ab7 | 1047 | static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, |
3d0c5005 | 1048 | const struct intel_crtc_state *crtc_state) |
c27e917e | 1049 | { |
0e5fa646 ML |
1050 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1051 | int clock = crtc_state->port_clock; | |
c27e917e PZ |
1052 | const enum intel_dpll_id id = pll->info->id; |
1053 | ||
1054 | switch (id) { | |
1055 | default: | |
20fd2ab7 LDM |
1056 | /* |
1057 | * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used | |
1058 | * here, so do warn if this get passed in | |
1059 | */ | |
c27e917e | 1060 | MISSING_CASE(id); |
c27e917e | 1061 | return DDI_CLK_SEL_NONE; |
1fa11ee2 PZ |
1062 | case DPLL_ID_ICL_TBTPLL: |
1063 | switch (clock) { | |
1064 | case 162000: | |
1065 | return DDI_CLK_SEL_TBT_162; | |
1066 | case 270000: | |
1067 | return DDI_CLK_SEL_TBT_270; | |
1068 | case 540000: | |
1069 | return DDI_CLK_SEL_TBT_540; | |
1070 | case 810000: | |
1071 | return DDI_CLK_SEL_TBT_810; | |
1072 | default: | |
1073 | MISSING_CASE(clock); | |
7a61a6de | 1074 | return DDI_CLK_SEL_NONE; |
1fa11ee2 | 1075 | } |
c27e917e PZ |
1076 | case DPLL_ID_ICL_MGPLL1: |
1077 | case DPLL_ID_ICL_MGPLL2: | |
1078 | case DPLL_ID_ICL_MGPLL3: | |
1079 | case DPLL_ID_ICL_MGPLL4: | |
6677c3b1 JRS |
1080 | case DPLL_ID_TGL_MGPLL5: |
1081 | case DPLL_ID_TGL_MGPLL6: | |
c27e917e PZ |
1082 | return DDI_CLK_SEL_MG; |
1083 | } | |
1084 | } | |
1085 | ||
c82e4d26 ED |
1086 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
1087 | * connection to the PCH-located connectors. For this, it is necessary to train | |
1088 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
1089 | * | |
1090 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
1091 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
1092 | * DDI A (which is used for eDP) | |
1093 | */ | |
1094 | ||
dc4a1094 ACO |
1095 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
1096 | const struct intel_crtc_state *crtc_state) | |
c82e4d26 | 1097 | { |
4cbe4b2b | 1098 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1099 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a7e4f99 | 1100 | struct intel_encoder *encoder; |
c856052a | 1101 | u32 temp, i, rx_ctl_val, ddi_pll_sel; |
c82e4d26 | 1102 | |
4cbe4b2b | 1103 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
6a7e4f99 | 1104 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); |
3a6d84e6 | 1105 | intel_prepare_dp_ddi_buffers(encoder, crtc_state); |
6a7e4f99 VS |
1106 | } |
1107 | ||
04945641 PZ |
1108 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
1109 | * mode set "sequence for CRT port" document: | |
1110 | * - TP1 to TP2 time with the default value | |
1111 | * - FDI delay to 90h | |
8693a824 DL |
1112 | * |
1113 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 1114 | */ |
eede3b53 | 1115 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
1116 | FDI_RX_PWRDN_LANE0_VAL(2) | |
1117 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
1118 | ||
1119 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 1120 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 1121 | FDI_RX_PLL_ENABLE | |
dc4a1094 | 1122 | FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
eede3b53 VS |
1123 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
1124 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
1125 | udelay(220); |
1126 | ||
1127 | /* Switch from Rawclk to PCDclk */ | |
1128 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 1129 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
1130 | |
1131 | /* Configure Port Clock Select */ | |
dc4a1094 | 1132 | ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); |
c856052a ACO |
1133 | I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); |
1134 | WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
1135 | |
1136 | /* Start the training iterating through available voltages and emphasis, | |
1137 | * testing each value twice. */ | |
10122051 | 1138 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
1139 | /* Configure DP_TP_CTL with auto-training */ |
1140 | I915_WRITE(DP_TP_CTL(PORT_E), | |
1141 | DP_TP_CTL_FDI_AUTOTRAIN | | |
1142 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
1143 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
1144 | DP_TP_CTL_ENABLE); | |
1145 | ||
876a8cdf DL |
1146 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
1147 | * DDI E does not support port reversal, the functionality is | |
1148 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
1149 | * port reversal bit */ | |
c82e4d26 | 1150 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 1151 | DDI_BUF_CTL_ENABLE | |
dc4a1094 | 1152 | ((crtc_state->fdi_lanes - 1) << 1) | |
c5fe6a06 | 1153 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 1154 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
1155 | |
1156 | udelay(600); | |
1157 | ||
04945641 | 1158 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 1159 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
1160 | |
1161 | /* Enable PCH FDI Receiver with auto-training */ | |
1162 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
1163 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
1164 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
1165 | |
1166 | /* Wait for FDI receiver lane calibration */ | |
1167 | udelay(30); | |
1168 | ||
1169 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 1170 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 1171 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
1172 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
1173 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
1174 | |
1175 | /* Wait for FDI auto training time */ | |
1176 | udelay(5); | |
c82e4d26 ED |
1177 | |
1178 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
1179 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 1180 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
1181 | break; |
1182 | } | |
c82e4d26 | 1183 | |
a308ccb3 VS |
1184 | /* |
1185 | * Leave things enabled even if we failed to train FDI. | |
1186 | * Results in less fireworks from the state checker. | |
1187 | */ | |
1188 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
1189 | DRM_ERROR("FDI link training failed!\n"); | |
1190 | break; | |
c82e4d26 | 1191 | } |
04945641 | 1192 | |
5b421c57 VS |
1193 | rx_ctl_val &= ~FDI_RX_ENABLE; |
1194 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); | |
1195 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
1196 | ||
248138b5 PZ |
1197 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
1198 | temp &= ~DDI_BUF_CTL_ENABLE; | |
1199 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
1200 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
1201 | ||
04945641 | 1202 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
1203 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
1204 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1205 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1206 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
1207 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
1208 | ||
1209 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 | 1210 | |
04945641 | 1211 | /* Reset FDI_RX_MISC pwrdn lanes */ |
eede3b53 | 1212 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
1213 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
1214 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
1215 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
1216 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
1217 | } |
1218 | ||
a308ccb3 VS |
1219 | /* Enable normal pixel sending for FDI */ |
1220 | I915_WRITE(DP_TP_CTL(PORT_E), | |
1221 | DP_TP_CTL_FDI_AUTOTRAIN | | |
1222 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
1223 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
1224 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 1225 | } |
0e72a5b5 | 1226 | |
d7c530b2 | 1227 | static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
44905a27 DA |
1228 | { |
1229 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1230 | struct intel_digital_port *intel_dig_port = | |
1231 | enc_to_dig_port(&encoder->base); | |
1232 | ||
1233 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 1234 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 1235 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
1236 | } |
1237 | ||
8d9ddbcb | 1238 | static struct intel_encoder * |
e9ce1a62 | 1239 | intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) |
8d9ddbcb | 1240 | { |
e9ce1a62 | 1241 | struct drm_device *dev = crtc->base.dev; |
1524e93e | 1242 | struct intel_encoder *encoder, *ret = NULL; |
8d9ddbcb PZ |
1243 | int num_encoders = 0; |
1244 | ||
1524e93e SS |
1245 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
1246 | ret = encoder; | |
8d9ddbcb PZ |
1247 | num_encoders++; |
1248 | } | |
1249 | ||
1250 | if (num_encoders != 1) | |
84f44ce7 | 1251 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
e9ce1a62 | 1252 | pipe_name(crtc->pipe)); |
8d9ddbcb PZ |
1253 | |
1254 | BUG_ON(ret == NULL); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
f0f59a00 VS |
1258 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
1259 | i915_reg_t reg) | |
11578553 | 1260 | { |
0f52c097 | 1261 | int refclk; |
11578553 JB |
1262 | int n, p, r; |
1263 | u32 wrpll; | |
1264 | ||
1265 | wrpll = I915_READ(reg); | |
4a95e36f VS |
1266 | switch (wrpll & WRPLL_REF_MASK) { |
1267 | case WRPLL_REF_SPECIAL_HSW: | |
86761789 VS |
1268 | /* |
1269 | * muxed-SSC for BDW. | |
1270 | * non-SSC for non-ULT HSW. Check FUSE_STRAP3 | |
1271 | * for the non-SSC reference frequency. | |
1272 | */ | |
1273 | if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { | |
1274 | if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) | |
1275 | refclk = 24; | |
1276 | else | |
1277 | refclk = 135; | |
1278 | break; | |
1279 | } | |
1280 | /* fall through */ | |
4a95e36f | 1281 | case WRPLL_REF_PCH_SSC: |
11578553 JB |
1282 | /* |
1283 | * We could calculate spread here, but our checking | |
1284 | * code only cares about 5% accuracy, and spread is a max of | |
1285 | * 0.5% downspread. | |
1286 | */ | |
1287 | refclk = 135; | |
1288 | break; | |
4a95e36f | 1289 | case WRPLL_REF_LCPLL: |
0f52c097 | 1290 | refclk = 2700; |
11578553 JB |
1291 | break; |
1292 | default: | |
86761789 | 1293 | MISSING_CASE(wrpll); |
11578553 JB |
1294 | return 0; |
1295 | } | |
1296 | ||
1297 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
1298 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
1299 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
1300 | ||
20f0ec16 JB |
1301 | /* Convert to KHz, p & r have a fixed point portion */ |
1302 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
1303 | } |
1304 | ||
947f4417 | 1305 | static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) |
540e732c | 1306 | { |
3d0c5005 | 1307 | u32 p0, p1, p2, dco_freq; |
540e732c | 1308 | |
947f4417 LDM |
1309 | p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; |
1310 | p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; | |
540e732c | 1311 | |
947f4417 LDM |
1312 | if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) |
1313 | p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
540e732c S |
1314 | else |
1315 | p1 = 1; | |
1316 | ||
1317 | ||
1318 | switch (p0) { | |
1319 | case DPLL_CFGCR2_PDIV_1: | |
1320 | p0 = 1; | |
1321 | break; | |
1322 | case DPLL_CFGCR2_PDIV_2: | |
1323 | p0 = 2; | |
1324 | break; | |
1325 | case DPLL_CFGCR2_PDIV_3: | |
1326 | p0 = 3; | |
1327 | break; | |
1328 | case DPLL_CFGCR2_PDIV_7: | |
1329 | p0 = 7; | |
1330 | break; | |
1331 | } | |
1332 | ||
1333 | switch (p2) { | |
1334 | case DPLL_CFGCR2_KDIV_5: | |
1335 | p2 = 5; | |
1336 | break; | |
1337 | case DPLL_CFGCR2_KDIV_2: | |
1338 | p2 = 2; | |
1339 | break; | |
1340 | case DPLL_CFGCR2_KDIV_3: | |
1341 | p2 = 3; | |
1342 | break; | |
1343 | case DPLL_CFGCR2_KDIV_1: | |
1344 | p2 = 1; | |
1345 | break; | |
1346 | } | |
1347 | ||
947f4417 LDM |
1348 | dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) |
1349 | * 24 * 1000; | |
540e732c | 1350 | |
947f4417 LDM |
1351 | dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) |
1352 | * 24 * 1000) / 0x8000; | |
540e732c | 1353 | |
b8449c43 YX |
1354 | if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) |
1355 | return 0; | |
1356 | ||
540e732c S |
1357 | return dco_freq / (p0 * p1 * p2 * 5); |
1358 | } | |
1359 | ||
8327af28 | 1360 | int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
5e65216d | 1361 | struct intel_dpll_hw_state *pll_state) |
a9701a89 | 1362 | { |
3d0c5005 | 1363 | u32 p0, p1, p2, dco_freq, ref_clock; |
a9701a89 | 1364 | |
5e65216d LDM |
1365 | p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; |
1366 | p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; | |
a9701a89 | 1367 | |
5e65216d LDM |
1368 | if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) |
1369 | p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> | |
a9701a89 RV |
1370 | DPLL_CFGCR1_QDIV_RATIO_SHIFT; |
1371 | else | |
1372 | p1 = 1; | |
1373 | ||
1374 | ||
1375 | switch (p0) { | |
1376 | case DPLL_CFGCR1_PDIV_2: | |
1377 | p0 = 2; | |
1378 | break; | |
1379 | case DPLL_CFGCR1_PDIV_3: | |
1380 | p0 = 3; | |
1381 | break; | |
1382 | case DPLL_CFGCR1_PDIV_5: | |
1383 | p0 = 5; | |
1384 | break; | |
1385 | case DPLL_CFGCR1_PDIV_7: | |
1386 | p0 = 7; | |
1387 | break; | |
1388 | } | |
1389 | ||
1390 | switch (p2) { | |
1391 | case DPLL_CFGCR1_KDIV_1: | |
1392 | p2 = 1; | |
1393 | break; | |
1394 | case DPLL_CFGCR1_KDIV_2: | |
1395 | p2 = 2; | |
1396 | break; | |
2ee7fd1e VS |
1397 | case DPLL_CFGCR1_KDIV_3: |
1398 | p2 = 3; | |
a9701a89 RV |
1399 | break; |
1400 | } | |
1401 | ||
9f9d594d | 1402 | ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); |
a9701a89 | 1403 | |
5e65216d LDM |
1404 | dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) |
1405 | * ref_clock; | |
a9701a89 | 1406 | |
5e65216d | 1407 | dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> |
442aa277 | 1408 | DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; |
a9701a89 | 1409 | |
0e005888 PZ |
1410 | if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) |
1411 | return 0; | |
1412 | ||
a9701a89 RV |
1413 | return dco_freq / (p0 * p1 * p2 * 5); |
1414 | } | |
1415 | ||
7b19f544 MN |
1416 | static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, |
1417 | enum port port) | |
1418 | { | |
1419 | u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; | |
1420 | ||
1421 | switch (val) { | |
1422 | case DDI_CLK_SEL_NONE: | |
1423 | return 0; | |
1424 | case DDI_CLK_SEL_TBT_162: | |
1425 | return 162000; | |
1426 | case DDI_CLK_SEL_TBT_270: | |
1427 | return 270000; | |
1428 | case DDI_CLK_SEL_TBT_540: | |
1429 | return 540000; | |
1430 | case DDI_CLK_SEL_TBT_810: | |
1431 | return 810000; | |
1432 | default: | |
1433 | MISSING_CASE(val); | |
1434 | return 0; | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, | |
02c99d26 | 1439 | const struct intel_dpll_hw_state *pll_state) |
7b19f544 | 1440 | { |
02c99d26 | 1441 | u32 m1, m2_int, m2_frac, div1, div2, ref_clock; |
7b19f544 MN |
1442 | u64 tmp; |
1443 | ||
02c99d26 | 1444 | ref_clock = dev_priv->cdclk.hw.ref; |
7b19f544 | 1445 | |
ee7de6ad JRS |
1446 | if (INTEL_GEN(dev_priv) >= 12) { |
1447 | m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; | |
1448 | m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; | |
1449 | m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; | |
1450 | ||
1451 | if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { | |
1452 | m2_frac = pll_state->mg_pll_bias & | |
1453 | DKL_PLL_BIAS_FBDIV_FRAC_MASK; | |
1454 | m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; | |
1455 | } else { | |
1456 | m2_frac = 0; | |
1457 | } | |
1458 | } else { | |
1459 | m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; | |
1460 | m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; | |
1461 | ||
1462 | if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { | |
1463 | m2_frac = pll_state->mg_pll_div0 & | |
1464 | MG_PLL_DIV0_FBDIV_FRAC_MASK; | |
1465 | m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; | |
1466 | } else { | |
1467 | m2_frac = 0; | |
1468 | } | |
1469 | } | |
7b19f544 | 1470 | |
02c99d26 LDM |
1471 | switch (pll_state->mg_clktop2_hsclkctl & |
1472 | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { | |
7b19f544 MN |
1473 | case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: |
1474 | div1 = 2; | |
1475 | break; | |
1476 | case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: | |
1477 | div1 = 3; | |
1478 | break; | |
1479 | case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: | |
1480 | div1 = 5; | |
1481 | break; | |
1482 | case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: | |
1483 | div1 = 7; | |
1484 | break; | |
1485 | default: | |
02c99d26 | 1486 | MISSING_CASE(pll_state->mg_clktop2_hsclkctl); |
7b19f544 MN |
1487 | return 0; |
1488 | } | |
1489 | ||
02c99d26 LDM |
1490 | div2 = (pll_state->mg_clktop2_hsclkctl & |
1491 | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> | |
7b19f544 | 1492 | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; |
02c99d26 | 1493 | |
7b19f544 MN |
1494 | /* div2 value of 0 is same as 1 means no div */ |
1495 | if (div2 == 0) | |
1496 | div2 = 1; | |
1497 | ||
1498 | /* | |
1499 | * Adjust the original formula to delay the division by 2^22 in order to | |
1500 | * minimize possible rounding errors. | |
1501 | */ | |
02c99d26 LDM |
1502 | tmp = (u64)m1 * m2_int * ref_clock + |
1503 | (((u64)m1 * m2_frac * ref_clock) >> 22); | |
7b19f544 MN |
1504 | tmp = div_u64(tmp, 5 * div1 * div2); |
1505 | ||
1506 | return tmp; | |
1507 | } | |
1508 | ||
398a017e VS |
1509 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
1510 | { | |
1511 | int dotclock; | |
1512 | ||
1513 | if (pipe_config->has_pch_encoder) | |
1514 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1515 | &pipe_config->fdi_m_n); | |
37a5650b | 1516 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
398a017e VS |
1517 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1518 | &pipe_config->dp_m_n); | |
2969a78a ID |
1519 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) |
1520 | dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; | |
398a017e VS |
1521 | else |
1522 | dotclock = pipe_config->port_clock; | |
1523 | ||
16668f48 GM |
1524 | if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && |
1525 | !intel_crtc_has_dp_encoder(pipe_config)) | |
b22ca995 SS |
1526 | dotclock *= 2; |
1527 | ||
398a017e VS |
1528 | if (pipe_config->pixel_multiplier) |
1529 | dotclock /= pipe_config->pixel_multiplier; | |
1530 | ||
1531 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
1532 | } | |
540e732c | 1533 | |
51c83cfa MN |
1534 | static void icl_ddi_clock_get(struct intel_encoder *encoder, |
1535 | struct intel_crtc_state *pipe_config) | |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5e65216d | 1538 | struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; |
51c83cfa | 1539 | enum port port = encoder->port; |
d8fe2ab6 | 1540 | enum phy phy = intel_port_to_phy(dev_priv, port); |
5e65216d | 1541 | int link_clock; |
51c83cfa | 1542 | |
d8fe2ab6 | 1543 | if (intel_phy_is_combo(dev_priv, phy)) { |
5e65216d | 1544 | link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); |
51c83cfa | 1545 | } else { |
077973c8 LDM |
1546 | enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, |
1547 | pipe_config->shared_dpll); | |
1548 | ||
7b19f544 MN |
1549 | if (pll_id == DPLL_ID_ICL_TBTPLL) |
1550 | link_clock = icl_calc_tbt_pll_link(dev_priv, port); | |
1551 | else | |
02c99d26 | 1552 | link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); |
51c83cfa MN |
1553 | } |
1554 | ||
1555 | pipe_config->port_clock = link_clock; | |
02c99d26 | 1556 | |
51c83cfa MN |
1557 | ddi_dotclock_get(pipe_config); |
1558 | } | |
1559 | ||
a9701a89 RV |
1560 | static void cnl_ddi_clock_get(struct intel_encoder *encoder, |
1561 | struct intel_crtc_state *pipe_config) | |
1562 | { | |
1563 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5e65216d LDM |
1564 | struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; |
1565 | int link_clock; | |
a9701a89 | 1566 | |
5e65216d LDM |
1567 | if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { |
1568 | link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); | |
a9701a89 | 1569 | } else { |
5e65216d | 1570 | link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; |
a9701a89 RV |
1571 | |
1572 | switch (link_clock) { | |
1573 | case DPLL_CFGCR0_LINK_RATE_810: | |
1574 | link_clock = 81000; | |
1575 | break; | |
1576 | case DPLL_CFGCR0_LINK_RATE_1080: | |
1577 | link_clock = 108000; | |
1578 | break; | |
1579 | case DPLL_CFGCR0_LINK_RATE_1350: | |
1580 | link_clock = 135000; | |
1581 | break; | |
1582 | case DPLL_CFGCR0_LINK_RATE_1620: | |
1583 | link_clock = 162000; | |
1584 | break; | |
1585 | case DPLL_CFGCR0_LINK_RATE_2160: | |
1586 | link_clock = 216000; | |
1587 | break; | |
1588 | case DPLL_CFGCR0_LINK_RATE_2700: | |
1589 | link_clock = 270000; | |
1590 | break; | |
1591 | case DPLL_CFGCR0_LINK_RATE_3240: | |
1592 | link_clock = 324000; | |
1593 | break; | |
1594 | case DPLL_CFGCR0_LINK_RATE_4050: | |
1595 | link_clock = 405000; | |
1596 | break; | |
1597 | default: | |
1598 | WARN(1, "Unsupported link rate\n"); | |
1599 | break; | |
1600 | } | |
1601 | link_clock *= 2; | |
1602 | } | |
1603 | ||
1604 | pipe_config->port_clock = link_clock; | |
1605 | ||
1606 | ddi_dotclock_get(pipe_config); | |
1607 | } | |
1608 | ||
540e732c | 1609 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
947f4417 | 1610 | struct intel_crtc_state *pipe_config) |
540e732c | 1611 | { |
947f4417 LDM |
1612 | struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; |
1613 | int link_clock; | |
540e732c | 1614 | |
947f4417 LDM |
1615 | /* |
1616 | * ctrl1 register is already shifted for each pll, just use 0 to get | |
1617 | * the internal shift for each field | |
1618 | */ | |
1619 | if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { | |
1620 | link_clock = skl_calc_wrpll_link(pll_state); | |
540e732c | 1621 | } else { |
947f4417 LDM |
1622 | link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); |
1623 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); | |
540e732c S |
1624 | |
1625 | switch (link_clock) { | |
71cd8423 | 1626 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
1627 | link_clock = 81000; |
1628 | break; | |
71cd8423 | 1629 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
1630 | link_clock = 108000; |
1631 | break; | |
71cd8423 | 1632 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
1633 | link_clock = 135000; |
1634 | break; | |
71cd8423 | 1635 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
1636 | link_clock = 162000; |
1637 | break; | |
71cd8423 | 1638 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
1639 | link_clock = 216000; |
1640 | break; | |
71cd8423 | 1641 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
1642 | link_clock = 270000; |
1643 | break; | |
1644 | default: | |
1645 | WARN(1, "Unsupported link rate\n"); | |
1646 | break; | |
1647 | } | |
1648 | link_clock *= 2; | |
1649 | } | |
1650 | ||
1651 | pipe_config->port_clock = link_clock; | |
1652 | ||
398a017e | 1653 | ddi_dotclock_get(pipe_config); |
540e732c S |
1654 | } |
1655 | ||
3d51278a | 1656 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1657 | struct intel_crtc_state *pipe_config) |
11578553 | 1658 | { |
fac5e23e | 1659 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
11578553 JB |
1660 | int link_clock = 0; |
1661 | u32 val, pll; | |
1662 | ||
c856052a | 1663 | val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); |
11578553 JB |
1664 | switch (val & PORT_CLK_SEL_MASK) { |
1665 | case PORT_CLK_SEL_LCPLL_810: | |
1666 | link_clock = 81000; | |
1667 | break; | |
1668 | case PORT_CLK_SEL_LCPLL_1350: | |
1669 | link_clock = 135000; | |
1670 | break; | |
1671 | case PORT_CLK_SEL_LCPLL_2700: | |
1672 | link_clock = 270000; | |
1673 | break; | |
1674 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 1675 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
1676 | break; |
1677 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 1678 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
1679 | break; |
1680 | case PORT_CLK_SEL_SPLL: | |
4a95e36f VS |
1681 | pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; |
1682 | if (pll == SPLL_FREQ_810MHz) | |
11578553 | 1683 | link_clock = 81000; |
4a95e36f | 1684 | else if (pll == SPLL_FREQ_1350MHz) |
11578553 | 1685 | link_clock = 135000; |
4a95e36f | 1686 | else if (pll == SPLL_FREQ_2700MHz) |
11578553 JB |
1687 | link_clock = 270000; |
1688 | else { | |
1689 | WARN(1, "bad spll freq\n"); | |
1690 | return; | |
1691 | } | |
1692 | break; | |
1693 | default: | |
1694 | WARN(1, "bad port clock sel\n"); | |
1695 | return; | |
1696 | } | |
1697 | ||
1698 | pipe_config->port_clock = link_clock * 2; | |
1699 | ||
398a017e | 1700 | ddi_dotclock_get(pipe_config); |
11578553 JB |
1701 | } |
1702 | ||
47c9877e | 1703 | static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) |
977bb38d | 1704 | { |
9e2c8475 | 1705 | struct dpll clock; |
aa610dcb | 1706 | |
aa610dcb | 1707 | clock.m1 = 2; |
47c9877e LDM |
1708 | clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; |
1709 | if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
1710 | clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
1711 | clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
1712 | clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
1713 | clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
aa610dcb ID |
1714 | |
1715 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
1716 | } |
1717 | ||
1718 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
bb911536 | 1719 | struct intel_crtc_state *pipe_config) |
977bb38d | 1720 | { |
47c9877e LDM |
1721 | pipe_config->port_clock = |
1722 | bxt_calc_pll_link(&pipe_config->dpll_hw_state); | |
977bb38d | 1723 | |
398a017e | 1724 | ddi_dotclock_get(pipe_config); |
977bb38d S |
1725 | } |
1726 | ||
35686a44 VS |
1727 | static void intel_ddi_clock_get(struct intel_encoder *encoder, |
1728 | struct intel_crtc_state *pipe_config) | |
3d51278a | 1729 | { |
0853723b | 1730 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22606a18 | 1731 | |
2dd24a9c | 1732 | if (INTEL_GEN(dev_priv) >= 11) |
fdec4df4 | 1733 | icl_ddi_clock_get(encoder, pipe_config); |
a9701a89 RV |
1734 | else if (IS_CANNONLAKE(dev_priv)) |
1735 | cnl_ddi_clock_get(encoder, pipe_config); | |
fdec4df4 RV |
1736 | else if (IS_GEN9_LP(dev_priv)) |
1737 | bxt_ddi_clock_get(encoder, pipe_config); | |
1738 | else if (IS_GEN9_BC(dev_priv)) | |
1739 | skl_ddi_clock_get(encoder, pipe_config); | |
1740 | else if (INTEL_GEN(dev_priv) <= 8) | |
1741 | hsw_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
1742 | } |
1743 | ||
0c06fa15 GM |
1744 | void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, |
1745 | const struct drm_connector_state *conn_state) | |
dae84799 | 1746 | { |
3dc38eea | 1747 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 1748 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
3dc38eea | 1749 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
5448f53f | 1750 | u32 temp; |
dae84799 | 1751 | |
5448f53f VS |
1752 | if (!intel_crtc_has_dp_encoder(crtc_state)) |
1753 | return; | |
4d1de975 | 1754 | |
5448f53f VS |
1755 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
1756 | ||
3e706dff | 1757 | temp = DP_MSA_MISC_SYNC_CLOCK; |
dc5977da | 1758 | |
5448f53f VS |
1759 | switch (crtc_state->pipe_bpp) { |
1760 | case 18: | |
3e706dff | 1761 | temp |= DP_MSA_MISC_6_BPC; |
5448f53f VS |
1762 | break; |
1763 | case 24: | |
3e706dff | 1764 | temp |= DP_MSA_MISC_8_BPC; |
5448f53f VS |
1765 | break; |
1766 | case 30: | |
3e706dff | 1767 | temp |= DP_MSA_MISC_10_BPC; |
5448f53f VS |
1768 | break; |
1769 | case 36: | |
3e706dff | 1770 | temp |= DP_MSA_MISC_12_BPC; |
5448f53f VS |
1771 | break; |
1772 | default: | |
1773 | MISSING_CASE(crtc_state->pipe_bpp); | |
1774 | break; | |
dae84799 | 1775 | } |
5448f53f | 1776 | |
cae154fc VS |
1777 | /* nonsense combination */ |
1778 | WARN_ON(crtc_state->limited_color_range && | |
1779 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); | |
1780 | ||
1781 | if (crtc_state->limited_color_range) | |
3e706dff | 1782 | temp |= DP_MSA_MISC_COLOR_CEA_RGB; |
cae154fc | 1783 | |
668b6c17 SS |
1784 | /* |
1785 | * As per DP 1.2 spec section 2.3.4.3 while sending | |
1786 | * YCBCR 444 signals we should program MSA MISC1/0 fields with | |
646d3dc8 | 1787 | * colorspace information. |
668b6c17 SS |
1788 | */ |
1789 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) | |
3e706dff | 1790 | temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; |
646d3dc8 | 1791 | |
ec4401d3 GM |
1792 | /* |
1793 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication | |
1794 | * of Color Encoding Format and Content Color Gamut] while sending | |
0c06fa15 GM |
1795 | * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields |
1796 | * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. | |
d4a415dc VS |
1797 | * |
1798 | * FIXME MST doesn't pass in the conn_state | |
ec4401d3 | 1799 | */ |
d4a415dc | 1800 | if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) |
3e706dff | 1801 | temp |= DP_MSA_MISC_COLOR_VSC_SDP; |
0c06fa15 | 1802 | |
5448f53f | 1803 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1804 | } |
1805 | ||
3dc38eea ACO |
1806 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1807 | bool state) | |
0e32b39c | 1808 | { |
3dc38eea | 1809 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 1810 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
3dc38eea | 1811 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
3d0c5005 | 1812 | u32 temp; |
7e732cac | 1813 | |
0e32b39c DA |
1814 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1815 | if (state == true) | |
1816 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1817 | else | |
1818 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1819 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1820 | } | |
1821 | ||
99389390 JRS |
1822 | /* |
1823 | * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. | |
1824 | * | |
1825 | * Only intended to be used by intel_ddi_enable_transcoder_func() and | |
1826 | * intel_ddi_config_transcoder_func(). | |
1827 | */ | |
1828 | static u32 | |
1829 | intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) | |
8d9ddbcb | 1830 | { |
3dc38eea | 1831 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
1524e93e | 1832 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
e9ce1a62 ACO |
1833 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1834 | enum pipe pipe = crtc->pipe; | |
3dc38eea | 1835 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
0fce04c8 | 1836 | enum port port = encoder->port; |
3d0c5005 | 1837 | u32 temp; |
8d9ddbcb | 1838 | |
ad80a810 PZ |
1839 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1840 | temp = TRANS_DDI_FUNC_ENABLE; | |
df16b636 MK |
1841 | if (INTEL_GEN(dev_priv) >= 12) |
1842 | temp |= TGL_TRANS_DDI_SELECT_PORT(port); | |
1843 | else | |
1844 | temp |= TRANS_DDI_SELECT_PORT(port); | |
dfcef252 | 1845 | |
3dc38eea | 1846 | switch (crtc_state->pipe_bpp) { |
dfcef252 | 1847 | case 18: |
ad80a810 | 1848 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1849 | break; |
1850 | case 24: | |
ad80a810 | 1851 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1852 | break; |
1853 | case 30: | |
ad80a810 | 1854 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1855 | break; |
1856 | case 36: | |
ad80a810 | 1857 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1858 | break; |
1859 | default: | |
4e53c2e0 | 1860 | BUG(); |
dfcef252 | 1861 | } |
72662e10 | 1862 | |
3dc38eea | 1863 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1864 | temp |= TRANS_DDI_PVSYNC; |
3dc38eea | 1865 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1866 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1867 | |
e6f0bfc4 PZ |
1868 | if (cpu_transcoder == TRANSCODER_EDP) { |
1869 | switch (pipe) { | |
1870 | case PIPE_A: | |
c7670b10 PZ |
1871 | /* On Haswell, can only use the always-on power well for |
1872 | * eDP when not using the panel fitter, and when not | |
1873 | * using motion blur mitigation (which we don't | |
1874 | * support). */ | |
dc0c0bfe | 1875 | if (crtc_state->pch_pfit.force_thru) |
d6dd9eb1 DV |
1876 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1877 | else | |
1878 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1879 | break; |
1880 | case PIPE_B: | |
1881 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1882 | break; | |
1883 | case PIPE_C: | |
1884 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1885 | break; | |
1886 | default: | |
1887 | BUG(); | |
1888 | break; | |
1889 | } | |
1890 | } | |
1891 | ||
742745f1 | 1892 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
3dc38eea | 1893 | if (crtc_state->has_hdmi_sink) |
ad80a810 | 1894 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1895 | else |
ad80a810 | 1896 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
15953637 SS |
1897 | |
1898 | if (crtc_state->hdmi_scrambling) | |
ab2cb2cb | 1899 | temp |= TRANS_DDI_HDMI_SCRAMBLING; |
15953637 SS |
1900 | if (crtc_state->hdmi_high_tmds_clock_ratio) |
1901 | temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; | |
742745f1 | 1902 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
ad80a810 | 1903 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
3dc38eea | 1904 | temp |= (crtc_state->fdi_lanes - 1) << 1; |
742745f1 | 1905 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { |
64ee2fd2 | 1906 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
3dc38eea | 1907 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); |
8d9ddbcb | 1908 | } else { |
742745f1 VS |
1909 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
1910 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); | |
8d9ddbcb PZ |
1911 | } |
1912 | ||
99389390 JRS |
1913 | return temp; |
1914 | } | |
1915 | ||
1916 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) | |
1917 | { | |
1918 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1919 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1920 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
1921 | u32 temp; | |
1922 | ||
1923 | temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); | |
1924 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1925 | } | |
1926 | ||
1927 | /* | |
1928 | * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable | |
1929 | * bit. | |
1930 | */ | |
1931 | static void | |
1932 | intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) | |
1933 | { | |
1934 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1935 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1936 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
1937 | u32 temp; | |
1938 | ||
1939 | temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); | |
1940 | temp &= ~TRANS_DDI_FUNC_ENABLE; | |
ad80a810 | 1941 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1942 | } |
72662e10 | 1943 | |
90c3e219 | 1944 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) |
8d9ddbcb | 1945 | { |
90c3e219 CT |
1946 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
1947 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1948 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
f0f59a00 | 1949 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
3d0c5005 | 1950 | u32 val = I915_READ(reg); |
8d9ddbcb | 1951 | |
df16b636 MK |
1952 | if (INTEL_GEN(dev_priv) >= 12) { |
1953 | val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | | |
1954 | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); | |
1955 | } else { | |
1956 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | | |
1957 | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); | |
1958 | } | |
8d9ddbcb | 1959 | I915_WRITE(reg, val); |
90c3e219 CT |
1960 | |
1961 | if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && | |
1962 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { | |
1963 | DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); | |
1964 | /* Quirk time at 100ms for reliable operation */ | |
1965 | msleep(100); | |
1966 | } | |
72662e10 ED |
1967 | } |
1968 | ||
2320175f SP |
1969 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, |
1970 | bool enable) | |
1971 | { | |
1972 | struct drm_device *dev = intel_encoder->base.dev; | |
1973 | struct drm_i915_private *dev_priv = to_i915(dev); | |
0e6e0be4 | 1974 | intel_wakeref_t wakeref; |
2320175f SP |
1975 | enum pipe pipe = 0; |
1976 | int ret = 0; | |
3d0c5005 | 1977 | u32 tmp; |
2320175f | 1978 | |
0e6e0be4 CW |
1979 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1980 | intel_encoder->power_domain); | |
1981 | if (WARN_ON(!wakeref)) | |
2320175f SP |
1982 | return -ENXIO; |
1983 | ||
1984 | if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { | |
1985 | ret = -EIO; | |
1986 | goto out; | |
1987 | } | |
1988 | ||
1989 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); | |
1990 | if (enable) | |
1991 | tmp |= TRANS_DDI_HDCP_SIGNALLING; | |
1992 | else | |
1993 | tmp &= ~TRANS_DDI_HDCP_SIGNALLING; | |
1994 | I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); | |
1995 | out: | |
0e6e0be4 | 1996 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
2320175f SP |
1997 | return ret; |
1998 | } | |
1999 | ||
bcbc889b PZ |
2000 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
2001 | { | |
2002 | struct drm_device *dev = intel_connector->base.dev; | |
fac5e23e | 2003 | struct drm_i915_private *dev_priv = to_i915(dev); |
1524e93e | 2004 | struct intel_encoder *encoder = intel_connector->encoder; |
bcbc889b | 2005 | int type = intel_connector->base.connector_type; |
0fce04c8 | 2006 | enum port port = encoder->port; |
bcbc889b | 2007 | enum transcoder cpu_transcoder; |
0e6e0be4 CW |
2008 | intel_wakeref_t wakeref; |
2009 | enum pipe pipe = 0; | |
3d0c5005 | 2010 | u32 tmp; |
e27daab4 | 2011 | bool ret; |
bcbc889b | 2012 | |
0e6e0be4 CW |
2013 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
2014 | encoder->power_domain); | |
2015 | if (!wakeref) | |
882244a3 PZ |
2016 | return false; |
2017 | ||
1524e93e | 2018 | if (!encoder->get_hw_state(encoder, &pipe)) { |
e27daab4 ID |
2019 | ret = false; |
2020 | goto out; | |
2021 | } | |
bcbc889b | 2022 | |
bc7e3525 | 2023 | if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) |
bcbc889b PZ |
2024 | cpu_transcoder = TRANSCODER_EDP; |
2025 | else | |
1a240d4d | 2026 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
2027 | |
2028 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
2029 | ||
2030 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
2031 | case TRANS_DDI_MODE_SELECT_HDMI: | |
2032 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
2033 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
2034 | break; | |
bcbc889b PZ |
2035 | |
2036 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
2037 | ret = type == DRM_MODE_CONNECTOR_eDP || |
2038 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
2039 | break; | |
2040 | ||
0e32b39c DA |
2041 | case TRANS_DDI_MODE_SELECT_DP_MST: |
2042 | /* if the transcoder is in MST state then | |
2043 | * connector isn't connected */ | |
e27daab4 ID |
2044 | ret = false; |
2045 | break; | |
bcbc889b PZ |
2046 | |
2047 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
2048 | ret = type == DRM_MODE_CONNECTOR_VGA; |
2049 | break; | |
bcbc889b PZ |
2050 | |
2051 | default: | |
e27daab4 ID |
2052 | ret = false; |
2053 | break; | |
bcbc889b | 2054 | } |
e27daab4 ID |
2055 | |
2056 | out: | |
0e6e0be4 | 2057 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
e27daab4 ID |
2058 | |
2059 | return ret; | |
bcbc889b PZ |
2060 | } |
2061 | ||
9199c322 ID |
2062 | static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, |
2063 | u8 *pipe_mask, bool *is_dp_mst) | |
85234cdc DV |
2064 | { |
2065 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2066 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fce04c8 | 2067 | enum port port = encoder->port; |
0e6e0be4 | 2068 | intel_wakeref_t wakeref; |
3657e927 | 2069 | enum pipe p; |
85234cdc | 2070 | u32 tmp; |
9199c322 ID |
2071 | u8 mst_pipe_mask; |
2072 | ||
2073 | *pipe_mask = 0; | |
2074 | *is_dp_mst = false; | |
85234cdc | 2075 | |
0e6e0be4 CW |
2076 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
2077 | encoder->power_domain); | |
2078 | if (!wakeref) | |
9199c322 | 2079 | return; |
e27daab4 | 2080 | |
fe43d3f5 | 2081 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc | 2082 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
e27daab4 | 2083 | goto out; |
85234cdc | 2084 | |
bc7e3525 | 2085 | if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { |
ad80a810 | 2086 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
85234cdc | 2087 | |
ad80a810 | 2088 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
9199c322 ID |
2089 | default: |
2090 | MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); | |
2091 | /* fallthrough */ | |
ad80a810 PZ |
2092 | case TRANS_DDI_EDP_INPUT_A_ON: |
2093 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9199c322 | 2094 | *pipe_mask = BIT(PIPE_A); |
ad80a810 PZ |
2095 | break; |
2096 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9199c322 | 2097 | *pipe_mask = BIT(PIPE_B); |
ad80a810 PZ |
2098 | break; |
2099 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9199c322 | 2100 | *pipe_mask = BIT(PIPE_C); |
ad80a810 PZ |
2101 | break; |
2102 | } | |
2103 | ||
e27daab4 ID |
2104 | goto out; |
2105 | } | |
0e32b39c | 2106 | |
9199c322 | 2107 | mst_pipe_mask = 0; |
3657e927 | 2108 | for_each_pipe(dev_priv, p) { |
9199c322 | 2109 | enum transcoder cpu_transcoder = (enum transcoder)p; |
df16b636 | 2110 | unsigned int port_mask, ddi_select; |
6aa3bef1 JRS |
2111 | intel_wakeref_t trans_wakeref; |
2112 | ||
2113 | trans_wakeref = intel_display_power_get_if_enabled(dev_priv, | |
2114 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); | |
2115 | if (!trans_wakeref) | |
2116 | continue; | |
df16b636 MK |
2117 | |
2118 | if (INTEL_GEN(dev_priv) >= 12) { | |
2119 | port_mask = TGL_TRANS_DDI_PORT_MASK; | |
2120 | ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); | |
2121 | } else { | |
2122 | port_mask = TRANS_DDI_PORT_MASK; | |
2123 | ddi_select = TRANS_DDI_SELECT_PORT(port); | |
2124 | } | |
3657e927 MK |
2125 | |
2126 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
6aa3bef1 JRS |
2127 | intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), |
2128 | trans_wakeref); | |
e27daab4 | 2129 | |
df16b636 | 2130 | if ((tmp & port_mask) != ddi_select) |
9199c322 | 2131 | continue; |
e27daab4 | 2132 | |
9199c322 ID |
2133 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == |
2134 | TRANS_DDI_MODE_SELECT_DP_MST) | |
2135 | mst_pipe_mask |= BIT(p); | |
e27daab4 | 2136 | |
9199c322 | 2137 | *pipe_mask |= BIT(p); |
85234cdc DV |
2138 | } |
2139 | ||
9199c322 | 2140 | if (!*pipe_mask) |
66a990dd VS |
2141 | DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", |
2142 | encoder->base.base.id, encoder->base.name); | |
9199c322 ID |
2143 | |
2144 | if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { | |
66a990dd VS |
2145 | DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", |
2146 | encoder->base.base.id, encoder->base.name, | |
2147 | *pipe_mask); | |
9199c322 ID |
2148 | *pipe_mask = BIT(ffs(*pipe_mask) - 1); |
2149 | } | |
2150 | ||
2151 | if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) | |
66a990dd VS |
2152 | DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", |
2153 | encoder->base.base.id, encoder->base.name, | |
2154 | *pipe_mask, mst_pipe_mask); | |
9199c322 ID |
2155 | else |
2156 | *is_dp_mst = mst_pipe_mask; | |
85234cdc | 2157 | |
e27daab4 | 2158 | out: |
9199c322 | 2159 | if (*pipe_mask && IS_GEN9_LP(dev_priv)) { |
e93da0a0 | 2160 | tmp = I915_READ(BXT_PHY_CTL(port)); |
e19c1eb8 ID |
2161 | if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | |
2162 | BXT_PHY_LANE_POWERDOWN_ACK | | |
e93da0a0 | 2163 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) |
66a990dd VS |
2164 | DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " |
2165 | "(PHY_CTL %08x)\n", encoder->base.base.id, | |
2166 | encoder->base.name, tmp); | |
e93da0a0 ID |
2167 | } |
2168 | ||
0e6e0be4 | 2169 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
9199c322 | 2170 | } |
e27daab4 | 2171 | |
9199c322 ID |
2172 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
2173 | enum pipe *pipe) | |
2174 | { | |
2175 | u8 pipe_mask; | |
2176 | bool is_mst; | |
2177 | ||
2178 | intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); | |
2179 | ||
2180 | if (is_mst || !pipe_mask) | |
2181 | return false; | |
2182 | ||
2183 | *pipe = ffs(pipe_mask) - 1; | |
2184 | ||
2185 | return true; | |
85234cdc DV |
2186 | } |
2187 | ||
52528055 | 2188 | static inline enum intel_display_power_domain |
bdaa29b6 | 2189 | intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) |
52528055 | 2190 | { |
9e3b5ce9 | 2191 | /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with |
52528055 ID |
2192 | * DC states enabled at the same time, while for driver initiated AUX |
2193 | * transfers we need the same AUX IOs to be powered but with DC states | |
2194 | * disabled. Accordingly use the AUX power domain here which leaves DC | |
2195 | * states enabled. | |
2196 | * However, for non-A AUX ports the corresponding non-EDP transcoders | |
2197 | * would have already enabled power well 2 and DC_OFF. This means we can | |
2198 | * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a | |
2199 | * specific AUX_IO reference without powering up any extra wells. | |
2200 | * Note that PSR is enabled only on Port A even though this function | |
2201 | * returns the correct domain for other ports too. | |
2202 | */ | |
563d22a0 | 2203 | return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : |
337837ac | 2204 | intel_aux_power_domain(dig_port); |
52528055 ID |
2205 | } |
2206 | ||
3a52fb7e ID |
2207 | static void intel_ddi_get_power_domains(struct intel_encoder *encoder, |
2208 | struct intel_crtc_state *crtc_state) | |
62b69566 | 2209 | { |
8e4a3ad9 | 2210 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b79ebe74 | 2211 | struct intel_digital_port *dig_port; |
d8fe2ab6 | 2212 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
62b69566 | 2213 | |
52528055 ID |
2214 | /* |
2215 | * TODO: Add support for MST encoders. Atm, the following should never | |
b79ebe74 ID |
2216 | * happen since fake-MST encoders don't set their get_power_domains() |
2217 | * hook. | |
52528055 ID |
2218 | */ |
2219 | if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) | |
3a52fb7e | 2220 | return; |
b79ebe74 ID |
2221 | |
2222 | dig_port = enc_to_dig_port(&encoder->base); | |
3a52fb7e | 2223 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); |
52528055 | 2224 | |
8e4a3ad9 ID |
2225 | /* |
2226 | * AUX power is only needed for (e)DP mode, and for HDMI mode on TC | |
2227 | * ports. | |
2228 | */ | |
2229 | if (intel_crtc_has_dp_encoder(crtc_state) || | |
d8fe2ab6 | 2230 | intel_phy_is_tc(dev_priv, phy)) |
3a52fb7e ID |
2231 | intel_display_power_get(dev_priv, |
2232 | intel_ddi_main_link_aux_domain(dig_port)); | |
52528055 | 2233 | |
a24c62f9 MN |
2234 | /* |
2235 | * VDSC power is needed when DSC is enabled | |
2236 | */ | |
010663a6 | 2237 | if (crtc_state->dsc.compression_enable) |
3a52fb7e ID |
2238 | intel_display_power_get(dev_priv, |
2239 | intel_dsc_power_domain(crtc_state)); | |
62b69566 ACO |
2240 | } |
2241 | ||
3dc38eea | 2242 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) |
fc914639 | 2243 | { |
3dc38eea | 2244 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 2245 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1524e93e | 2246 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
0fce04c8 | 2247 | enum port port = encoder->port; |
3dc38eea | 2248 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc914639 | 2249 | |
df16b636 MK |
2250 | if (cpu_transcoder != TRANSCODER_EDP) { |
2251 | if (INTEL_GEN(dev_priv) >= 12) | |
2252 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2253 | TGL_TRANS_CLK_SEL_PORT(port)); | |
2254 | else | |
2255 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2256 | TRANS_CLK_SEL_PORT(port)); | |
2257 | } | |
fc914639 PZ |
2258 | } |
2259 | ||
3dc38eea | 2260 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) |
fc914639 | 2261 | { |
3dc38eea ACO |
2262 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
2263 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
fc914639 | 2264 | |
df16b636 MK |
2265 | if (cpu_transcoder != TRANSCODER_EDP) { |
2266 | if (INTEL_GEN(dev_priv) >= 12) | |
2267 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2268 | TGL_TRANS_CLK_SEL_DISABLED); | |
2269 | else | |
2270 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2271 | TRANS_CLK_SEL_DISABLED); | |
2272 | } | |
fc914639 PZ |
2273 | } |
2274 | ||
a7d8dbc0 | 2275 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
3d0c5005 | 2276 | enum port port, u8 iboost) |
f8896f5d | 2277 | { |
a7d8dbc0 VS |
2278 | u32 tmp; |
2279 | ||
2280 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
2281 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); | |
2282 | if (iboost) | |
2283 | tmp |= iboost << BALANCE_LEG_SHIFT(port); | |
2284 | else | |
2285 | tmp |= BALANCE_LEG_DISABLE(port); | |
2286 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); | |
2287 | } | |
2288 | ||
081dfcfa VS |
2289 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, |
2290 | int level, enum intel_output_type type) | |
a7d8dbc0 VS |
2291 | { |
2292 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
8f4f2797 VS |
2293 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2294 | enum port port = encoder->port; | |
3d0c5005 | 2295 | u8 iboost; |
f8896f5d | 2296 | |
081dfcfa VS |
2297 | if (type == INTEL_OUTPUT_HDMI) |
2298 | iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
2299 | else | |
2300 | iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
75067dde | 2301 | |
081dfcfa VS |
2302 | if (iboost == 0) { |
2303 | const struct ddi_buf_trans *ddi_translations; | |
2304 | int n_entries; | |
2305 | ||
2306 | if (type == INTEL_OUTPUT_HDMI) | |
2307 | ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); | |
2308 | else if (type == INTEL_OUTPUT_EDP) | |
edba48fd | 2309 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); |
081dfcfa | 2310 | else |
edba48fd | 2311 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); |
10afa0b6 | 2312 | |
21b39d2a VS |
2313 | if (WARN_ON_ONCE(!ddi_translations)) |
2314 | return; | |
2315 | if (WARN_ON_ONCE(level >= n_entries)) | |
2316 | level = n_entries - 1; | |
2317 | ||
081dfcfa | 2318 | iboost = ddi_translations[level].i_boost; |
f8896f5d DW |
2319 | } |
2320 | ||
2321 | /* Make sure that the requested I_boost is valid */ | |
2322 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
2323 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
2324 | return; | |
2325 | } | |
2326 | ||
a7d8dbc0 | 2327 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
f8896f5d | 2328 | |
a7d8dbc0 VS |
2329 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
2330 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); | |
f8896f5d DW |
2331 | } |
2332 | ||
7d4f37b5 VS |
2333 | static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, |
2334 | int level, enum intel_output_type type) | |
96fb9f9b | 2335 | { |
7d4f37b5 | 2336 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
96fb9f9b | 2337 | const struct bxt_ddi_buf_trans *ddi_translations; |
7d4f37b5 | 2338 | enum port port = encoder->port; |
043eaf36 | 2339 | int n_entries; |
7d4f37b5 VS |
2340 | |
2341 | if (type == INTEL_OUTPUT_HDMI) | |
2342 | ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); | |
2343 | else if (type == INTEL_OUTPUT_EDP) | |
2344 | ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); | |
2345 | else | |
2346 | ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); | |
96fb9f9b | 2347 | |
21b39d2a VS |
2348 | if (WARN_ON_ONCE(!ddi_translations)) |
2349 | return; | |
2350 | if (WARN_ON_ONCE(level >= n_entries)) | |
2351 | level = n_entries - 1; | |
2352 | ||
b6e08203 ACO |
2353 | bxt_ddi_phy_set_signal_level(dev_priv, port, |
2354 | ddi_translations[level].margin, | |
2355 | ddi_translations[level].scale, | |
2356 | ddi_translations[level].enable, | |
2357 | ddi_translations[level].deemphasis); | |
96fb9f9b VK |
2358 | } |
2359 | ||
ffe5111e VS |
2360 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) |
2361 | { | |
2362 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b265a2a6 | 2363 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
edba48fd | 2364 | enum port port = encoder->port; |
d8fe2ab6 | 2365 | enum phy phy = intel_port_to_phy(dev_priv, port); |
ffe5111e VS |
2366 | int n_entries; |
2367 | ||
978c3e53 CT |
2368 | if (INTEL_GEN(dev_priv) >= 12) { |
2369 | if (intel_phy_is_combo(dev_priv, phy)) | |
2370 | icl_get_combo_buf_trans(dev_priv, encoder->type, | |
2371 | intel_dp->link_rate, &n_entries); | |
2372 | else | |
2373 | n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); | |
2374 | } else if (INTEL_GEN(dev_priv) == 11) { | |
d8fe2ab6 | 2375 | if (intel_phy_is_combo(dev_priv, phy)) |
4a8134d5 | 2376 | icl_get_combo_buf_trans(dev_priv, encoder->type, |
b265a2a6 | 2377 | intel_dp->link_rate, &n_entries); |
36cf89f5 MN |
2378 | else |
2379 | n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); | |
2380 | } else if (IS_CANNONLAKE(dev_priv)) { | |
5fcf34b1 RV |
2381 | if (encoder->type == INTEL_OUTPUT_EDP) |
2382 | cnl_get_buf_trans_edp(dev_priv, &n_entries); | |
2383 | else | |
2384 | cnl_get_buf_trans_dp(dev_priv, &n_entries); | |
7d4f37b5 VS |
2385 | } else if (IS_GEN9_LP(dev_priv)) { |
2386 | if (encoder->type == INTEL_OUTPUT_EDP) | |
2387 | bxt_get_buf_trans_edp(dev_priv, &n_entries); | |
2388 | else | |
2389 | bxt_get_buf_trans_dp(dev_priv, &n_entries); | |
5fcf34b1 RV |
2390 | } else { |
2391 | if (encoder->type == INTEL_OUTPUT_EDP) | |
edba48fd | 2392 | intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); |
5fcf34b1 | 2393 | else |
edba48fd | 2394 | intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); |
5fcf34b1 | 2395 | } |
ffe5111e VS |
2396 | |
2397 | if (WARN_ON(n_entries < 1)) | |
2398 | n_entries = 1; | |
2399 | if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) | |
2400 | n_entries = ARRAY_SIZE(index_to_dp_signal_levels); | |
2401 | ||
2402 | return index_to_dp_signal_levels[n_entries - 1] & | |
2403 | DP_TRAIN_VOLTAGE_SWING_MASK; | |
2404 | } | |
2405 | ||
4718a365 VS |
2406 | /* |
2407 | * We assume that the full set of pre-emphasis values can be | |
2408 | * used on all DDI platforms. Should that change we need to | |
2409 | * rethink this code. | |
2410 | */ | |
2411 | u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) | |
2412 | { | |
2413 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2414 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
2415 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2416 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2417 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2418 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2419 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2420 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
2421 | default: | |
2422 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
2423 | } | |
2424 | } | |
2425 | ||
f3cf4ba4 VS |
2426 | static void cnl_ddi_vswing_program(struct intel_encoder *encoder, |
2427 | int level, enum intel_output_type type) | |
cf54ca8b | 2428 | { |
f3cf4ba4 | 2429 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
f3cf4ba4 | 2430 | const struct cnl_ddi_buf_trans *ddi_translations; |
0fce04c8 | 2431 | enum port port = encoder->port; |
f3cf4ba4 VS |
2432 | int n_entries, ln; |
2433 | u32 val; | |
cf54ca8b | 2434 | |
f3cf4ba4 | 2435 | if (type == INTEL_OUTPUT_HDMI) |
cc9cabfd | 2436 | ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); |
f3cf4ba4 | 2437 | else if (type == INTEL_OUTPUT_EDP) |
cc9cabfd | 2438 | ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); |
f3cf4ba4 VS |
2439 | else |
2440 | ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); | |
cf54ca8b | 2441 | |
21b39d2a | 2442 | if (WARN_ON_ONCE(!ddi_translations)) |
cf54ca8b | 2443 | return; |
21b39d2a | 2444 | if (WARN_ON_ONCE(level >= n_entries)) |
cf54ca8b | 2445 | level = n_entries - 1; |
cf54ca8b RV |
2446 | |
2447 | /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ | |
2448 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
1f588aeb | 2449 | val &= ~SCALING_MODE_SEL_MASK; |
cf54ca8b RV |
2450 | val |= SCALING_MODE_SEL(2); |
2451 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2452 | ||
2453 | /* Program PORT_TX_DW2 */ | |
2454 | val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); | |
1f588aeb RV |
2455 | val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | |
2456 | RCOMP_SCALAR_MASK); | |
cf54ca8b RV |
2457 | val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); |
2458 | val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); | |
2459 | /* Rcomp scalar is fixed as 0x98 for every table entry */ | |
2460 | val |= RCOMP_SCALAR(0x98); | |
2461 | I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); | |
2462 | ||
20303eb4 | 2463 | /* Program PORT_TX_DW4 */ |
cf54ca8b RV |
2464 | /* We cannot write to GRP. It would overrite individual loadgen */ |
2465 | for (ln = 0; ln < 4; ln++) { | |
9194e42a | 2466 | val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); |
1f588aeb RV |
2467 | val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | |
2468 | CURSOR_COEFF_MASK); | |
cf54ca8b RV |
2469 | val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); |
2470 | val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); | |
2471 | val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); | |
9194e42a | 2472 | I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); |
cf54ca8b RV |
2473 | } |
2474 | ||
20303eb4 | 2475 | /* Program PORT_TX_DW5 */ |
cf54ca8b RV |
2476 | /* All DW5 values are fixed for every table entry */ |
2477 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
1f588aeb | 2478 | val &= ~RTERM_SELECT_MASK; |
cf54ca8b RV |
2479 | val |= RTERM_SELECT(6); |
2480 | val |= TAP3_DISABLE; | |
2481 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2482 | ||
20303eb4 | 2483 | /* Program PORT_TX_DW7 */ |
cf54ca8b | 2484 | val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); |
1f588aeb | 2485 | val &= ~N_SCALAR_MASK; |
cf54ca8b RV |
2486 | val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); |
2487 | I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); | |
2488 | } | |
2489 | ||
f3cf4ba4 VS |
2490 | static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, |
2491 | int level, enum intel_output_type type) | |
cf54ca8b | 2492 | { |
0091abc3 | 2493 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0fce04c8 | 2494 | enum port port = encoder->port; |
f3cf4ba4 | 2495 | int width, rate, ln; |
cf54ca8b | 2496 | u32 val; |
0091abc3 | 2497 | |
f3cf4ba4 | 2498 | if (type == INTEL_OUTPUT_HDMI) { |
0091abc3 | 2499 | width = 4; |
f3cf4ba4 | 2500 | rate = 0; /* Rate is always < than 6GHz for HDMI */ |
61f3e770 | 2501 | } else { |
f3cf4ba4 VS |
2502 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2503 | ||
2504 | width = intel_dp->lane_count; | |
2505 | rate = intel_dp->link_rate; | |
0091abc3 | 2506 | } |
cf54ca8b RV |
2507 | |
2508 | /* | |
2509 | * 1. If port type is eDP or DP, | |
2510 | * set PORT_PCS_DW1 cmnkeeper_enable to 1b, | |
2511 | * else clear to 0b. | |
2512 | */ | |
2513 | val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); | |
f3cf4ba4 | 2514 | if (type != INTEL_OUTPUT_HDMI) |
cf54ca8b RV |
2515 | val |= COMMON_KEEPER_EN; |
2516 | else | |
2517 | val &= ~COMMON_KEEPER_EN; | |
2518 | I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); | |
2519 | ||
2520 | /* 2. Program loadgen select */ | |
2521 | /* | |
0091abc3 CT |
2522 | * Program PORT_TX_DW4_LN depending on Bit rate and used lanes |
2523 | * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) | |
2524 | * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) | |
2525 | * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) | |
cf54ca8b | 2526 | */ |
0091abc3 | 2527 | for (ln = 0; ln <= 3; ln++) { |
9194e42a | 2528 | val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); |
0091abc3 CT |
2529 | val &= ~LOADGEN_SELECT; |
2530 | ||
a8e45a1c NM |
2531 | if ((rate <= 600000 && width == 4 && ln >= 1) || |
2532 | (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { | |
0091abc3 CT |
2533 | val |= LOADGEN_SELECT; |
2534 | } | |
9194e42a | 2535 | I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); |
0091abc3 | 2536 | } |
cf54ca8b RV |
2537 | |
2538 | /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ | |
2539 | val = I915_READ(CNL_PORT_CL1CM_DW5); | |
2540 | val |= SUS_CLOCK_CONFIG; | |
2541 | I915_WRITE(CNL_PORT_CL1CM_DW5, val); | |
2542 | ||
2543 | /* 4. Clear training enable to change swing values */ | |
2544 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
2545 | val &= ~TX_TRAINING_EN; | |
2546 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2547 | ||
2548 | /* 5. Program swing and de-emphasis */ | |
f3cf4ba4 | 2549 | cnl_ddi_vswing_program(encoder, level, type); |
cf54ca8b RV |
2550 | |
2551 | /* 6. Set training enable to trigger update */ | |
2552 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
2553 | val |= TX_TRAINING_EN; | |
2554 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2555 | } | |
2556 | ||
fb5c8e9d | 2557 | static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, |
dc867bc7 | 2558 | u32 level, enum phy phy, int type, |
b265a2a6 | 2559 | int rate) |
fb5c8e9d | 2560 | { |
b265a2a6 | 2561 | const struct cnl_ddi_buf_trans *ddi_translations = NULL; |
fb5c8e9d MN |
2562 | u32 n_entries, val; |
2563 | int ln; | |
2564 | ||
4a8134d5 MR |
2565 | ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, |
2566 | &n_entries); | |
fb5c8e9d MN |
2567 | if (!ddi_translations) |
2568 | return; | |
2569 | ||
2570 | if (level >= n_entries) { | |
2571 | DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); | |
2572 | level = n_entries - 1; | |
2573 | } | |
2574 | ||
b265a2a6 | 2575 | /* Set PORT_TX_DW5 */ |
dc867bc7 | 2576 | val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); |
b265a2a6 CT |
2577 | val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | |
2578 | TAP2_DISABLE | TAP3_DISABLE); | |
2579 | val |= SCALING_MODE_SEL(0x2); | |
fb5c8e9d | 2580 | val |= RTERM_SELECT(0x6); |
b265a2a6 | 2581 | val |= TAP3_DISABLE; |
dc867bc7 | 2582 | I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); |
fb5c8e9d MN |
2583 | |
2584 | /* Program PORT_TX_DW2 */ | |
dc867bc7 | 2585 | val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); |
fb5c8e9d MN |
2586 | val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | |
2587 | RCOMP_SCALAR_MASK); | |
b265a2a6 CT |
2588 | val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); |
2589 | val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); | |
fb5c8e9d | 2590 | /* Program Rcomp scalar for every table entry */ |
b265a2a6 | 2591 | val |= RCOMP_SCALAR(0x98); |
dc867bc7 | 2592 | I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); |
fb5c8e9d MN |
2593 | |
2594 | /* Program PORT_TX_DW4 */ | |
2595 | /* We cannot write to GRP. It would overwrite individual loadgen. */ | |
2596 | for (ln = 0; ln <= 3; ln++) { | |
dc867bc7 | 2597 | val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); |
fb5c8e9d MN |
2598 | val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | |
2599 | CURSOR_COEFF_MASK); | |
b265a2a6 CT |
2600 | val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); |
2601 | val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); | |
2602 | val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); | |
dc867bc7 | 2603 | I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); |
fb5c8e9d | 2604 | } |
b265a2a6 CT |
2605 | |
2606 | /* Program PORT_TX_DW7 */ | |
dc867bc7 | 2607 | val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); |
b265a2a6 CT |
2608 | val &= ~N_SCALAR_MASK; |
2609 | val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); | |
dc867bc7 | 2610 | I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); |
fb5c8e9d MN |
2611 | } |
2612 | ||
2613 | static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, | |
2614 | u32 level, | |
2615 | enum intel_output_type type) | |
2616 | { | |
2617 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
dc867bc7 | 2618 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
fb5c8e9d MN |
2619 | int width = 0; |
2620 | int rate = 0; | |
2621 | u32 val; | |
2622 | int ln = 0; | |
2623 | ||
2624 | if (type == INTEL_OUTPUT_HDMI) { | |
2625 | width = 4; | |
2626 | /* Rate is always < than 6GHz for HDMI */ | |
2627 | } else { | |
2628 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2629 | ||
2630 | width = intel_dp->lane_count; | |
2631 | rate = intel_dp->link_rate; | |
2632 | } | |
2633 | ||
2634 | /* | |
2635 | * 1. If port type is eDP or DP, | |
2636 | * set PORT_PCS_DW1 cmnkeeper_enable to 1b, | |
2637 | * else clear to 0b. | |
2638 | */ | |
dc867bc7 | 2639 | val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); |
fb5c8e9d MN |
2640 | if (type == INTEL_OUTPUT_HDMI) |
2641 | val &= ~COMMON_KEEPER_EN; | |
2642 | else | |
2643 | val |= COMMON_KEEPER_EN; | |
dc867bc7 | 2644 | I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); |
fb5c8e9d MN |
2645 | |
2646 | /* 2. Program loadgen select */ | |
2647 | /* | |
2648 | * Program PORT_TX_DW4_LN depending on Bit rate and used lanes | |
2649 | * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) | |
2650 | * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) | |
2651 | * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) | |
2652 | */ | |
2653 | for (ln = 0; ln <= 3; ln++) { | |
dc867bc7 | 2654 | val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); |
fb5c8e9d MN |
2655 | val &= ~LOADGEN_SELECT; |
2656 | ||
2657 | if ((rate <= 600000 && width == 4 && ln >= 1) || | |
2658 | (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { | |
2659 | val |= LOADGEN_SELECT; | |
2660 | } | |
dc867bc7 | 2661 | I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); |
fb5c8e9d MN |
2662 | } |
2663 | ||
2664 | /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ | |
dc867bc7 | 2665 | val = I915_READ(ICL_PORT_CL_DW5(phy)); |
fb5c8e9d | 2666 | val |= SUS_CLOCK_CONFIG; |
dc867bc7 | 2667 | I915_WRITE(ICL_PORT_CL_DW5(phy), val); |
fb5c8e9d MN |
2668 | |
2669 | /* 4. Clear training enable to change swing values */ | |
dc867bc7 | 2670 | val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); |
fb5c8e9d | 2671 | val &= ~TX_TRAINING_EN; |
dc867bc7 | 2672 | I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); |
fb5c8e9d MN |
2673 | |
2674 | /* 5. Program swing and de-emphasis */ | |
dc867bc7 | 2675 | icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); |
fb5c8e9d MN |
2676 | |
2677 | /* 6. Set training enable to trigger update */ | |
dc867bc7 | 2678 | val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); |
fb5c8e9d | 2679 | val |= TX_TRAINING_EN; |
dc867bc7 | 2680 | I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); |
fb5c8e9d MN |
2681 | } |
2682 | ||
07685c82 MN |
2683 | static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, |
2684 | int link_clock, | |
2685 | u32 level) | |
2686 | { | |
2687 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
f21e8b80 | 2688 | enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); |
07685c82 MN |
2689 | const struct icl_mg_phy_ddi_buf_trans *ddi_translations; |
2690 | u32 n_entries, val; | |
2691 | int ln; | |
2692 | ||
2693 | n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); | |
2694 | ddi_translations = icl_mg_phy_ddi_translations; | |
2695 | /* The table does not have values for level 3 and level 9. */ | |
2696 | if (level >= n_entries || level == 3 || level == 9) { | |
2697 | DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", | |
2698 | level, n_entries - 2); | |
2699 | level = n_entries - 2; | |
2700 | } | |
2701 | ||
2702 | /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ | |
2703 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2704 | val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port)); |
07685c82 | 2705 | val &= ~CRI_USE_FS32; |
f21e8b80 | 2706 | I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val); |
07685c82 | 2707 | |
f21e8b80 | 2708 | val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port)); |
07685c82 | 2709 | val &= ~CRI_USE_FS32; |
f21e8b80 | 2710 | I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val); |
07685c82 MN |
2711 | } |
2712 | ||
2713 | /* Program MG_TX_SWINGCTRL with values from vswing table */ | |
2714 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2715 | val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port)); |
07685c82 MN |
2716 | val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; |
2717 | val |= CRI_TXDEEMPH_OVERRIDE_17_12( | |
2718 | ddi_translations[level].cri_txdeemph_override_17_12); | |
f21e8b80 | 2719 | I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val); |
07685c82 | 2720 | |
f21e8b80 | 2721 | val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port)); |
07685c82 MN |
2722 | val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; |
2723 | val |= CRI_TXDEEMPH_OVERRIDE_17_12( | |
2724 | ddi_translations[level].cri_txdeemph_override_17_12); | |
f21e8b80 | 2725 | I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val); |
07685c82 MN |
2726 | } |
2727 | ||
2728 | /* Program MG_TX_DRVCTRL with values from vswing table */ | |
2729 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2730 | val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port)); |
07685c82 MN |
2731 | val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | |
2732 | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); | |
2733 | val |= CRI_TXDEEMPH_OVERRIDE_5_0( | |
2734 | ddi_translations[level].cri_txdeemph_override_5_0) | | |
2735 | CRI_TXDEEMPH_OVERRIDE_11_6( | |
2736 | ddi_translations[level].cri_txdeemph_override_11_6) | | |
2737 | CRI_TXDEEMPH_OVERRIDE_EN; | |
f21e8b80 | 2738 | I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val); |
07685c82 | 2739 | |
f21e8b80 | 2740 | val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port)); |
07685c82 MN |
2741 | val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | |
2742 | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); | |
2743 | val |= CRI_TXDEEMPH_OVERRIDE_5_0( | |
2744 | ddi_translations[level].cri_txdeemph_override_5_0) | | |
2745 | CRI_TXDEEMPH_OVERRIDE_11_6( | |
2746 | ddi_translations[level].cri_txdeemph_override_11_6) | | |
2747 | CRI_TXDEEMPH_OVERRIDE_EN; | |
f21e8b80 | 2748 | I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val); |
07685c82 MN |
2749 | |
2750 | /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ | |
2751 | } | |
2752 | ||
2753 | /* | |
2754 | * Program MG_CLKHUB<LN, port being used> with value from frequency table | |
2755 | * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the | |
2756 | * values from table for which TX1 and TX2 enabled. | |
2757 | */ | |
2758 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2759 | val = I915_READ(MG_CLKHUB(ln, tc_port)); |
07685c82 MN |
2760 | if (link_clock < 300000) |
2761 | val |= CFG_LOW_RATE_LKREN_EN; | |
2762 | else | |
2763 | val &= ~CFG_LOW_RATE_LKREN_EN; | |
f21e8b80 | 2764 | I915_WRITE(MG_CLKHUB(ln, tc_port), val); |
07685c82 MN |
2765 | } |
2766 | ||
2767 | /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ | |
2768 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2769 | val = I915_READ(MG_TX1_DCC(ln, tc_port)); |
07685c82 MN |
2770 | val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; |
2771 | if (link_clock <= 500000) { | |
2772 | val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; | |
2773 | } else { | |
2774 | val |= CFG_AMI_CK_DIV_OVERRIDE_EN | | |
2775 | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); | |
2776 | } | |
f21e8b80 | 2777 | I915_WRITE(MG_TX1_DCC(ln, tc_port), val); |
07685c82 | 2778 | |
f21e8b80 | 2779 | val = I915_READ(MG_TX2_DCC(ln, tc_port)); |
07685c82 MN |
2780 | val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; |
2781 | if (link_clock <= 500000) { | |
2782 | val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; | |
2783 | } else { | |
2784 | val |= CFG_AMI_CK_DIV_OVERRIDE_EN | | |
2785 | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); | |
2786 | } | |
f21e8b80 | 2787 | I915_WRITE(MG_TX2_DCC(ln, tc_port), val); |
07685c82 MN |
2788 | } |
2789 | ||
2790 | /* Program MG_TX_PISO_READLOAD with values from vswing table */ | |
2791 | for (ln = 0; ln < 2; ln++) { | |
f21e8b80 | 2792 | val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port)); |
07685c82 | 2793 | val |= CRI_CALCINIT; |
f21e8b80 | 2794 | I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val); |
07685c82 | 2795 | |
f21e8b80 | 2796 | val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port)); |
07685c82 | 2797 | val |= CRI_CALCINIT; |
f21e8b80 | 2798 | I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val); |
07685c82 MN |
2799 | } |
2800 | } | |
2801 | ||
2802 | static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, | |
2803 | int link_clock, | |
2804 | u32 level, | |
fb5c8e9d MN |
2805 | enum intel_output_type type) |
2806 | { | |
176597a1 | 2807 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d8fe2ab6 | 2808 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
fb5c8e9d | 2809 | |
d8fe2ab6 | 2810 | if (intel_phy_is_combo(dev_priv, phy)) |
fb5c8e9d MN |
2811 | icl_combo_phy_ddi_vswing_sequence(encoder, level, type); |
2812 | else | |
07685c82 | 2813 | icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); |
fb5c8e9d MN |
2814 | } |
2815 | ||
978c3e53 CT |
2816 | static void |
2817 | tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, | |
2818 | u32 level) | |
2819 | { | |
2820 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2821 | enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); | |
2822 | const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; | |
2823 | u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; | |
2824 | ||
2825 | n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); | |
2826 | ddi_translations = tgl_dkl_phy_ddi_translations; | |
2827 | ||
2828 | if (level >= n_entries) | |
2829 | level = n_entries - 1; | |
2830 | ||
2831 | dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | | |
2832 | DKL_TX_DE_EMPAHSIS_COEFF_MASK | | |
2833 | DKL_TX_VSWING_CONTROL_MASK); | |
2834 | dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); | |
2835 | dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); | |
2836 | dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); | |
2837 | ||
2838 | for (ln = 0; ln < 2; ln++) { | |
2839 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); | |
2840 | ||
2841 | /* All the registers are RMW */ | |
2842 | val = I915_READ(DKL_TX_DPCNTL0(tc_port)); | |
2843 | val &= ~dpcnt_mask; | |
2844 | val |= dpcnt_val; | |
2845 | I915_WRITE(DKL_TX_DPCNTL0(tc_port), val); | |
2846 | ||
2847 | val = I915_READ(DKL_TX_DPCNTL1(tc_port)); | |
2848 | val &= ~dpcnt_mask; | |
2849 | val |= dpcnt_val; | |
2850 | I915_WRITE(DKL_TX_DPCNTL1(tc_port), val); | |
2851 | ||
2852 | val = I915_READ(DKL_TX_DPCNTL2(tc_port)); | |
2853 | val &= ~DKL_TX_DP20BITMODE; | |
2854 | I915_WRITE(DKL_TX_DPCNTL2(tc_port), val); | |
2855 | } | |
2856 | } | |
2857 | ||
2858 | static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, | |
2859 | int link_clock, | |
2860 | u32 level, | |
2861 | enum intel_output_type type) | |
2862 | { | |
2863 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2864 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); | |
2865 | ||
2866 | if (intel_phy_is_combo(dev_priv, phy)) | |
2867 | icl_combo_phy_ddi_vswing_sequence(encoder, level, type); | |
2868 | else | |
2869 | tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); | |
2870 | } | |
2871 | ||
3d0c5005 | 2872 | static u32 translate_signal_level(int signal_levels) |
f8896f5d | 2873 | { |
97eeb872 | 2874 | int i; |
f8896f5d | 2875 | |
97eeb872 VS |
2876 | for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { |
2877 | if (index_to_dp_signal_levels[i] == signal_levels) | |
2878 | return i; | |
f8896f5d DW |
2879 | } |
2880 | ||
97eeb872 VS |
2881 | WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
2882 | signal_levels); | |
2883 | ||
2884 | return 0; | |
f8896f5d DW |
2885 | } |
2886 | ||
3d0c5005 | 2887 | static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) |
1b6e2fd2 | 2888 | { |
3d0c5005 | 2889 | u8 train_set = intel_dp->train_set[0]; |
1b6e2fd2 RV |
2890 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2891 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2892 | ||
2893 | return translate_signal_level(signal_levels); | |
2894 | } | |
2895 | ||
d509af6c | 2896 | u32 bxt_signal_levels(struct intel_dp *intel_dp) |
f8896f5d DW |
2897 | { |
2898 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 2899 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d | 2900 | struct intel_encoder *encoder = &dport->base; |
d02ace87 | 2901 | int level = intel_ddi_dp_level(intel_dp); |
d509af6c | 2902 | |
978c3e53 CT |
2903 | if (INTEL_GEN(dev_priv) >= 12) |
2904 | tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, | |
2905 | level, encoder->type); | |
2906 | else if (INTEL_GEN(dev_priv) >= 11) | |
07685c82 MN |
2907 | icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, |
2908 | level, encoder->type); | |
fb5c8e9d | 2909 | else if (IS_CANNONLAKE(dev_priv)) |
f3cf4ba4 | 2910 | cnl_ddi_vswing_sequence(encoder, level, encoder->type); |
d509af6c | 2911 | else |
7d4f37b5 | 2912 | bxt_ddi_vswing_sequence(encoder, level, encoder->type); |
d509af6c RV |
2913 | |
2914 | return 0; | |
2915 | } | |
2916 | ||
3d0c5005 | 2917 | u32 ddi_signal_levels(struct intel_dp *intel_dp) |
d509af6c RV |
2918 | { |
2919 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2920 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
2921 | struct intel_encoder *encoder = &dport->base; | |
d02ace87 | 2922 | int level = intel_ddi_dp_level(intel_dp); |
f8896f5d | 2923 | |
b976dc53 | 2924 | if (IS_GEN9_BC(dev_priv)) |
081dfcfa | 2925 | skl_ddi_set_iboost(encoder, level, encoder->type); |
d509af6c | 2926 | |
f8896f5d DW |
2927 | return DDI_BUF_TRANS_SELECT(level); |
2928 | } | |
2929 | ||
bb1c7edc | 2930 | static inline |
3d0c5005 | 2931 | u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, |
befa372b | 2932 | enum phy phy) |
bb1c7edc | 2933 | { |
befa372b MR |
2934 | if (intel_phy_is_combo(dev_priv, phy)) { |
2935 | return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); | |
2936 | } else if (intel_phy_is_tc(dev_priv, phy)) { | |
2937 | enum tc_port tc_port = intel_port_to_tc(dev_priv, | |
2938 | (enum port)phy); | |
bb1c7edc MK |
2939 | |
2940 | return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); | |
2941 | } | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | ||
3b8c0d5b JN |
2946 | static void icl_map_plls_to_ports(struct intel_encoder *encoder, |
2947 | const struct intel_crtc_state *crtc_state) | |
c27e917e | 2948 | { |
3b8c0d5b | 2949 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c27e917e | 2950 | struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
befa372b | 2951 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
3b8c0d5b | 2952 | u32 val; |
c27e917e | 2953 | |
3b8c0d5b | 2954 | mutex_lock(&dev_priv->dpll_lock); |
c27e917e | 2955 | |
befa372b MR |
2956 | val = I915_READ(ICL_DPCLKA_CFGCR0); |
2957 | WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); | |
c27e917e | 2958 | |
befa372b MR |
2959 | if (intel_phy_is_combo(dev_priv, phy)) { |
2960 | /* | |
2961 | * Even though this register references DDIs, note that we | |
2962 | * want to pass the PHY rather than the port (DDI). For | |
2963 | * ICL, port=phy in all cases so it doesn't matter, but for | |
2964 | * EHL the bspec notes the following: | |
2965 | * | |
2966 | * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA | |
2967 | * Clock Select chooses the PLL for both DDIA and DDID and | |
2968 | * drives port A in all cases." | |
2969 | */ | |
2970 | val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
2971 | val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); | |
2972 | I915_WRITE(ICL_DPCLKA_CFGCR0, val); | |
2973 | POSTING_READ(ICL_DPCLKA_CFGCR0); | |
c27e917e | 2974 | } |
3b8c0d5b | 2975 | |
befa372b MR |
2976 | val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); |
2977 | I915_WRITE(ICL_DPCLKA_CFGCR0, val); | |
3b8c0d5b JN |
2978 | |
2979 | mutex_unlock(&dev_priv->dpll_lock); | |
c27e917e PZ |
2980 | } |
2981 | ||
3b8c0d5b | 2982 | static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) |
c27e917e | 2983 | { |
3b8c0d5b | 2984 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
befa372b | 2985 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
3b8c0d5b | 2986 | u32 val; |
c27e917e | 2987 | |
3b8c0d5b | 2988 | mutex_lock(&dev_priv->dpll_lock); |
c27e917e | 2989 | |
befa372b MR |
2990 | val = I915_READ(ICL_DPCLKA_CFGCR0); |
2991 | val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); | |
2992 | I915_WRITE(ICL_DPCLKA_CFGCR0, val); | |
c27e917e | 2993 | |
3b8c0d5b | 2994 | mutex_unlock(&dev_priv->dpll_lock); |
c27e917e PZ |
2995 | } |
2996 | ||
70332ac5 ID |
2997 | void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) |
2998 | { | |
2999 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
30f5ccfa | 3000 | u32 val; |
1dd07e56 ID |
3001 | enum port port; |
3002 | u32 port_mask; | |
3003 | bool ddi_clk_needed; | |
30f5ccfa ID |
3004 | |
3005 | /* | |
3006 | * In case of DP MST, we sanitize the primary encoder only, not the | |
3007 | * virtual ones. | |
3008 | */ | |
3009 | if (encoder->type == INTEL_OUTPUT_DP_MST) | |
3010 | return; | |
3011 | ||
30f5ccfa ID |
3012 | if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { |
3013 | u8 pipe_mask; | |
3014 | bool is_mst; | |
3015 | ||
3016 | intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); | |
3017 | /* | |
3018 | * In the unlikely case that BIOS enables DP in MST mode, just | |
3019 | * warn since our MST HW readout is incomplete. | |
3020 | */ | |
3021 | if (WARN_ON(is_mst)) | |
3022 | return; | |
3023 | } | |
70332ac5 | 3024 | |
1dd07e56 ID |
3025 | port_mask = BIT(encoder->port); |
3026 | ddi_clk_needed = encoder->base.crtc; | |
70332ac5 | 3027 | |
1dd07e56 ID |
3028 | if (encoder->type == INTEL_OUTPUT_DSI) { |
3029 | struct intel_encoder *other_encoder; | |
70332ac5 | 3030 | |
1dd07e56 ID |
3031 | port_mask = intel_dsi_encoder_ports(encoder); |
3032 | /* | |
3033 | * Sanity check that we haven't incorrectly registered another | |
3034 | * encoder using any of the ports of this DSI encoder. | |
3035 | */ | |
3036 | for_each_intel_encoder(&dev_priv->drm, other_encoder) { | |
3037 | if (other_encoder == encoder) | |
3038 | continue; | |
3039 | ||
3040 | if (WARN_ON(port_mask & BIT(other_encoder->port))) | |
3041 | return; | |
3042 | } | |
3043 | /* | |
942d1cf4 VK |
3044 | * For DSI we keep the ddi clocks gated |
3045 | * except during enable/disable sequence. | |
1dd07e56 | 3046 | */ |
942d1cf4 | 3047 | ddi_clk_needed = false; |
1dd07e56 ID |
3048 | } |
3049 | ||
befa372b | 3050 | val = I915_READ(ICL_DPCLKA_CFGCR0); |
1dd07e56 | 3051 | for_each_port_masked(port, port_mask) { |
befa372b MR |
3052 | enum phy phy = intel_port_to_phy(dev_priv, port); |
3053 | ||
1dd07e56 ID |
3054 | bool ddi_clk_ungated = !(val & |
3055 | icl_dpclka_cfgcr0_clk_off(dev_priv, | |
befa372b | 3056 | phy)); |
1dd07e56 ID |
3057 | |
3058 | if (ddi_clk_needed == ddi_clk_ungated) | |
3059 | continue; | |
3060 | ||
3061 | /* | |
3062 | * Punt on the case now where clock is gated, but it would | |
3063 | * be needed by the port. Something else is really broken then. | |
3064 | */ | |
3065 | if (WARN_ON(ddi_clk_needed)) | |
3066 | continue; | |
3067 | ||
befa372b MR |
3068 | DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", |
3069 | phy_name(port)); | |
3070 | val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); | |
3071 | I915_WRITE(ICL_DPCLKA_CFGCR0, val); | |
1dd07e56 | 3072 | } |
70332ac5 ID |
3073 | } |
3074 | ||
d7c530b2 | 3075 | static void intel_ddi_clk_select(struct intel_encoder *encoder, |
0e5fa646 | 3076 | const struct intel_crtc_state *crtc_state) |
6441ab5f | 3077 | { |
e404ba8d | 3078 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0fce04c8 | 3079 | enum port port = encoder->port; |
d8fe2ab6 | 3080 | enum phy phy = intel_port_to_phy(dev_priv, port); |
3d0c5005 | 3081 | u32 val; |
0e5fa646 | 3082 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
6441ab5f | 3083 | |
c856052a ACO |
3084 | if (WARN_ON(!pll)) |
3085 | return; | |
3086 | ||
04bf68bb | 3087 | mutex_lock(&dev_priv->dpll_lock); |
8edcda12 | 3088 | |
2dd24a9c | 3089 | if (INTEL_GEN(dev_priv) >= 11) { |
d8fe2ab6 | 3090 | if (!intel_phy_is_combo(dev_priv, phy)) |
c27e917e | 3091 | I915_WRITE(DDI_CLK_SEL(port), |
20fd2ab7 | 3092 | icl_pll_to_ddi_clk_sel(encoder, crtc_state)); |
c2052d6e JRS |
3093 | else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) |
3094 | /* | |
3095 | * MG does not exist but the programming is required | |
3096 | * to ungate DDIC and DDID | |
3097 | */ | |
3098 | I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG); | |
c27e917e | 3099 | } else if (IS_CANNONLAKE(dev_priv)) { |
555e38d2 RV |
3100 | /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ |
3101 | val = I915_READ(DPCLKA_CFGCR0); | |
23a7068e | 3102 | val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); |
0823eb9c | 3103 | val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); |
555e38d2 | 3104 | I915_WRITE(DPCLKA_CFGCR0, val); |
efa80add | 3105 | |
555e38d2 RV |
3106 | /* |
3107 | * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. | |
3108 | * This step and the step before must be done with separate | |
3109 | * register writes. | |
3110 | */ | |
3111 | val = I915_READ(DPCLKA_CFGCR0); | |
87145d95 | 3112 | val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); |
555e38d2 RV |
3113 | I915_WRITE(DPCLKA_CFGCR0, val); |
3114 | } else if (IS_GEN9_BC(dev_priv)) { | |
5416d871 | 3115 | /* DDI -> PLL mapping */ |
efa80add S |
3116 | val = I915_READ(DPLL_CTRL2); |
3117 | ||
3118 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
04bf68bb | 3119 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); |
0823eb9c | 3120 | val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | |
efa80add S |
3121 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
3122 | ||
3123 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 3124 | |
c56b89f1 | 3125 | } else if (INTEL_GEN(dev_priv) < 9) { |
c856052a | 3126 | I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); |
efa80add | 3127 | } |
8edcda12 RV |
3128 | |
3129 | mutex_unlock(&dev_priv->dpll_lock); | |
e404ba8d VS |
3130 | } |
3131 | ||
6b8506d5 VS |
3132 | static void intel_ddi_clk_disable(struct intel_encoder *encoder) |
3133 | { | |
3134 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
0fce04c8 | 3135 | enum port port = encoder->port; |
d8fe2ab6 | 3136 | enum phy phy = intel_port_to_phy(dev_priv, port); |
6b8506d5 | 3137 | |
2dd24a9c | 3138 | if (INTEL_GEN(dev_priv) >= 11) { |
c2052d6e JRS |
3139 | if (!intel_phy_is_combo(dev_priv, phy) || |
3140 | (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) | |
c27e917e PZ |
3141 | I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); |
3142 | } else if (IS_CANNONLAKE(dev_priv)) { | |
6b8506d5 VS |
3143 | I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | |
3144 | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); | |
c27e917e | 3145 | } else if (IS_GEN9_BC(dev_priv)) { |
6b8506d5 VS |
3146 | I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | |
3147 | DPLL_CTRL2_DDI_CLK_OFF(port)); | |
c27e917e | 3148 | } else if (INTEL_GEN(dev_priv) < 9) { |
6b8506d5 | 3149 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
c27e917e | 3150 | } |
6b8506d5 VS |
3151 | } |
3152 | ||
8aaf5cbd JRS |
3153 | static void |
3154 | icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) | |
cb9ff519 ID |
3155 | { |
3156 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
f21e8b80 | 3157 | enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); |
8aaf5cbd | 3158 | u32 val, bits; |
9c11b121 | 3159 | int ln; |
cb9ff519 ID |
3160 | |
3161 | if (tc_port == PORT_TC_NONE) | |
3162 | return; | |
3163 | ||
8aaf5cbd JRS |
3164 | bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | |
3165 | MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | | |
3166 | MG_DP_MODE_CFG_GAONPWR_GATING; | |
cb9ff519 | 3167 | |
9c11b121 | 3168 | for (ln = 0; ln < 2; ln++) { |
978c3e53 CT |
3169 | if (INTEL_GEN(dev_priv) >= 12) { |
3170 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); | |
3171 | val = I915_READ(DKL_DP_MODE(tc_port)); | |
3172 | } else { | |
f21e8b80 | 3173 | val = I915_READ(MG_DP_MODE(ln, tc_port)); |
978c3e53 CT |
3174 | } |
3175 | ||
8aaf5cbd JRS |
3176 | if (enable) |
3177 | val |= bits; | |
3178 | else | |
3179 | val &= ~bits; | |
978c3e53 CT |
3180 | |
3181 | if (INTEL_GEN(dev_priv) >= 12) | |
3182 | I915_WRITE(DKL_DP_MODE(tc_port), val); | |
3183 | else | |
f21e8b80 | 3184 | I915_WRITE(MG_DP_MODE(ln, tc_port), val); |
cb9ff519 ID |
3185 | } |
3186 | ||
978c3e53 CT |
3187 | if (INTEL_GEN(dev_priv) == 11) { |
3188 | bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | | |
3189 | MG_MISC_SUS0_CFG_CL2PWR_GATING | | |
3190 | MG_MISC_SUS0_CFG_GAONPWR_GATING | | |
3191 | MG_MISC_SUS0_CFG_TRPWR_GATING | | |
3192 | MG_MISC_SUS0_CFG_CL1PWR_GATING | | |
3193 | MG_MISC_SUS0_CFG_DGPWR_GATING; | |
8aaf5cbd | 3194 | |
978c3e53 CT |
3195 | val = I915_READ(MG_MISC_SUS0(tc_port)); |
3196 | if (enable) | |
3197 | val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); | |
3198 | else | |
3199 | val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); | |
3200 | I915_WRITE(MG_MISC_SUS0(tc_port), val); | |
3201 | } | |
cb9ff519 ID |
3202 | } |
3203 | ||
3b51be4e CT |
3204 | static void |
3205 | icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, | |
3206 | const struct intel_crtc_state *crtc_state) | |
93b662d3 ID |
3207 | { |
3208 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
f21e8b80 | 3209 | enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); |
3b51be4e CT |
3210 | u32 ln0, ln1, pin_assignment; |
3211 | u8 width; | |
93b662d3 | 3212 | |
e9b7e142 | 3213 | if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) |
93b662d3 ID |
3214 | return; |
3215 | ||
978c3e53 CT |
3216 | if (INTEL_GEN(dev_priv) >= 12) { |
3217 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); | |
3218 | ln0 = I915_READ(DKL_DP_MODE(tc_port)); | |
3219 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); | |
3220 | ln1 = I915_READ(DKL_DP_MODE(tc_port)); | |
3221 | } else { | |
f21e8b80 JRS |
3222 | ln0 = I915_READ(MG_DP_MODE(0, tc_port)); |
3223 | ln1 = I915_READ(MG_DP_MODE(1, tc_port)); | |
978c3e53 | 3224 | } |
93b662d3 | 3225 | |
3b51be4e CT |
3226 | ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); |
3227 | ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); | |
93b662d3 | 3228 | |
3b51be4e CT |
3229 | /* DPPATC */ |
3230 | pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); | |
3231 | width = crtc_state->lane_count; | |
93b662d3 | 3232 | |
3b51be4e CT |
3233 | switch (pin_assignment) { |
3234 | case 0x0: | |
3235 | WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); | |
3236 | if (width == 1) { | |
3237 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; | |
3238 | } else { | |
3239 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3240 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3241 | } | |
3242 | break; | |
3243 | case 0x1: | |
3244 | if (width == 4) { | |
3245 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3246 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3247 | } | |
3248 | break; | |
3249 | case 0x2: | |
3250 | if (width == 2) { | |
3251 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3252 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3253 | } | |
3254 | break; | |
3255 | case 0x3: | |
3256 | case 0x5: | |
3257 | if (width == 1) { | |
93b662d3 | 3258 | ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; |
93b662d3 | 3259 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; |
3b51be4e CT |
3260 | } else { |
3261 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3262 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
93b662d3 ID |
3263 | } |
3264 | break; | |
3b51be4e CT |
3265 | case 0x4: |
3266 | case 0x6: | |
3267 | if (width == 1) { | |
3268 | ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; | |
3269 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; | |
3270 | } else { | |
3271 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3272 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; | |
3273 | } | |
93b662d3 | 3274 | break; |
93b662d3 | 3275 | default: |
3b51be4e | 3276 | MISSING_CASE(pin_assignment); |
93b662d3 ID |
3277 | } |
3278 | ||
978c3e53 CT |
3279 | if (INTEL_GEN(dev_priv) >= 12) { |
3280 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); | |
3281 | I915_WRITE(DKL_DP_MODE(tc_port), ln0); | |
3282 | I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); | |
3283 | I915_WRITE(DKL_DP_MODE(tc_port), ln1); | |
3284 | } else { | |
f21e8b80 JRS |
3285 | I915_WRITE(MG_DP_MODE(0, tc_port), ln0); |
3286 | I915_WRITE(MG_DP_MODE(1, tc_port), ln1); | |
978c3e53 | 3287 | } |
93b662d3 ID |
3288 | } |
3289 | ||
a322b975 AS |
3290 | static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, |
3291 | const struct intel_crtc_state *crtc_state) | |
3292 | { | |
3293 | if (!crtc_state->fec_enable) | |
3294 | return; | |
3295 | ||
3296 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) | |
3297 | DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); | |
3298 | } | |
3299 | ||
5c44b938 AS |
3300 | static void intel_ddi_enable_fec(struct intel_encoder *encoder, |
3301 | const struct intel_crtc_state *crtc_state) | |
3302 | { | |
3303 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4444df6e | 3304 | struct intel_dp *intel_dp; |
5c44b938 AS |
3305 | u32 val; |
3306 | ||
3307 | if (!crtc_state->fec_enable) | |
3308 | return; | |
3309 | ||
4444df6e LDM |
3310 | intel_dp = enc_to_intel_dp(&encoder->base); |
3311 | val = I915_READ(intel_dp->regs.dp_tp_ctl); | |
5c44b938 | 3312 | val |= DP_TP_CTL_FEC_ENABLE; |
4444df6e | 3313 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
5c44b938 | 3314 | |
4444df6e | 3315 | if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, |
4cb3b44d | 3316 | DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) |
5c44b938 AS |
3317 | DRM_ERROR("Timed out waiting for FEC Enable Status\n"); |
3318 | } | |
3319 | ||
d6a09cee AS |
3320 | static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, |
3321 | const struct intel_crtc_state *crtc_state) | |
3322 | { | |
3323 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4444df6e | 3324 | struct intel_dp *intel_dp; |
d6a09cee AS |
3325 | u32 val; |
3326 | ||
3327 | if (!crtc_state->fec_enable) | |
3328 | return; | |
3329 | ||
4444df6e LDM |
3330 | intel_dp = enc_to_intel_dp(&encoder->base); |
3331 | val = I915_READ(intel_dp->regs.dp_tp_ctl); | |
d6a09cee | 3332 | val &= ~DP_TP_CTL_FEC_ENABLE; |
4444df6e LDM |
3333 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
3334 | POSTING_READ(intel_dp->regs.dp_tp_ctl); | |
d6a09cee AS |
3335 | } |
3336 | ||
bdacf087 AG |
3337 | static void |
3338 | tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) | |
3339 | { | |
3340 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
3341 | u32 val; | |
3342 | ||
3343 | if (!cstate->dc3co_exitline) | |
3344 | return; | |
3345 | ||
3346 | val = I915_READ(EXITLINE(cstate->cpu_transcoder)); | |
3347 | val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); | |
3348 | I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); | |
3349 | } | |
3350 | ||
3351 | static void | |
3352 | tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) | |
3353 | { | |
3354 | u32 val, exit_scanlines; | |
3355 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
3356 | ||
3357 | if (!cstate->dc3co_exitline) | |
3358 | return; | |
3359 | ||
3360 | exit_scanlines = cstate->dc3co_exitline; | |
3361 | exit_scanlines <<= EXITLINE_SHIFT; | |
3362 | val = I915_READ(EXITLINE(cstate->cpu_transcoder)); | |
3363 | val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); | |
3364 | val |= exit_scanlines; | |
3365 | val |= EXITLINE_ENABLE; | |
3366 | I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); | |
3367 | } | |
3368 | ||
3369 | static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, | |
3370 | struct intel_crtc_state *cstate) | |
3371 | { | |
3372 | u32 exit_scanlines; | |
3373 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
3374 | u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay; | |
3375 | ||
3376 | cstate->dc3co_exitline = 0; | |
3377 | ||
3378 | if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) | |
3379 | return; | |
3380 | ||
3381 | /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ | |
3382 | if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A || | |
3383 | encoder->port != PORT_A) | |
3384 | return; | |
3385 | ||
3386 | if (!cstate->has_psr2 || !cstate->base.active) | |
3387 | return; | |
3388 | ||
3389 | /* | |
3390 | * DC3CO Exit time 200us B.Spec 49196 | |
3391 | * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 | |
3392 | */ | |
3393 | exit_scanlines = | |
3394 | intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1; | |
3395 | ||
3396 | if (WARN_ON(exit_scanlines > crtc_vdisplay)) | |
3397 | return; | |
3398 | ||
3399 | cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; | |
3400 | DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); | |
3401 | } | |
3402 | ||
3403 | static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) | |
3404 | { | |
3405 | u32 val; | |
3406 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
3407 | ||
3408 | if (INTEL_GEN(dev_priv) < 12) | |
3409 | return; | |
3410 | ||
3411 | val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); | |
3412 | ||
3413 | if (val & EXITLINE_ENABLE) | |
3414 | crtc_state->dc3co_exitline = val & EXITLINE_MASK; | |
3415 | } | |
3416 | ||
99389390 JRS |
3417 | static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, |
3418 | const struct intel_crtc_state *crtc_state, | |
3419 | const struct drm_connector_state *conn_state) | |
3420 | { | |
3421 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
3422 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3423 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); | |
3424 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
3425 | bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); | |
3426 | int level = intel_ddi_dp_level(intel_dp); | |
4444df6e | 3427 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
99389390 | 3428 | |
bdacf087 | 3429 | tgl_set_psr2_transcoder_exitline(crtc_state); |
99389390 JRS |
3430 | intel_dp_set_link_params(intel_dp, crtc_state->port_clock, |
3431 | crtc_state->lane_count, is_mst); | |
3432 | ||
4444df6e LDM |
3433 | intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); |
3434 | intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); | |
3435 | ||
99389390 JRS |
3436 | /* 1.a got on intel_atomic_commit_tail() */ |
3437 | ||
3438 | /* 2. */ | |
3439 | intel_edp_panel_on(intel_dp); | |
3440 | ||
3441 | /* | |
6171e58b | 3442 | * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by: |
99389390 JRS |
3443 | * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and |
3444 | * haswell_crtc_enable()->intel_enable_shared_dpll() | |
3445 | */ | |
3446 | ||
6171e58b CT |
3447 | /* 4.b */ |
3448 | intel_ddi_clk_select(encoder, crtc_state); | |
3449 | ||
99389390 JRS |
3450 | /* 5. */ |
3451 | if (!intel_phy_is_tc(dev_priv, phy) || | |
3452 | dig_port->tc_mode != TC_PORT_TBT_ALT) | |
3453 | intel_display_power_get(dev_priv, | |
3454 | dig_port->ddi_io_power_domain); | |
3455 | ||
3456 | /* 6. */ | |
3b51be4e | 3457 | icl_program_mg_dp_mode(dig_port, crtc_state); |
99389390 JRS |
3458 | |
3459 | /* | |
3460 | * 7.a - Steps in this function should only be executed over MST | |
3461 | * master, what will be taken in care by MST hook | |
3462 | * intel_mst_pre_enable_dp() | |
3463 | */ | |
3464 | intel_ddi_enable_pipe_clock(crtc_state); | |
3465 | ||
3466 | /* 7.b */ | |
3467 | intel_ddi_config_transcoder_func(crtc_state); | |
3468 | ||
3469 | /* 7.d */ | |
8aaf5cbd | 3470 | icl_phy_set_clock_gating(dig_port, false); |
99389390 JRS |
3471 | |
3472 | /* 7.e */ | |
978c3e53 | 3473 | tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, |
99389390 JRS |
3474 | encoder->type); |
3475 | ||
3476 | /* 7.f */ | |
3477 | if (intel_phy_is_combo(dev_priv, phy)) { | |
3478 | bool lane_reversal = | |
3479 | dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; | |
3480 | ||
3481 | intel_combo_phy_power_up_lanes(dev_priv, phy, false, | |
3482 | crtc_state->lane_count, | |
3483 | lane_reversal); | |
3484 | } | |
3485 | ||
3486 | /* 7.g */ | |
3487 | intel_ddi_init_dp_buf_reg(encoder); | |
3488 | ||
3489 | if (!is_mst) | |
3490 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
3491 | ||
3492 | intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); | |
3493 | /* | |
3494 | * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit | |
3495 | * in the FEC_CONFIGURATION register to 1 before initiating link | |
3496 | * training | |
3497 | */ | |
3498 | intel_dp_sink_set_fec_ready(intel_dp, crtc_state); | |
3499 | /* 7.c, 7.h, 7.i, 7.j */ | |
3500 | intel_dp_start_link_train(intel_dp); | |
3501 | ||
3502 | /* 7.k */ | |
eadf6f91 MN |
3503 | if (!is_trans_port_sync_mode(crtc_state)) |
3504 | intel_dp_stop_link_train(intel_dp); | |
99389390 | 3505 | |
978c3e53 CT |
3506 | /* |
3507 | * TODO: enable clock gating | |
3508 | * | |
3509 | * It is not written in DP enabling sequence but "PHY Clockgating | |
3510 | * programming" states that clock gating should be enabled after the | |
3511 | * link training but doing so causes all the following trainings to fail | |
3512 | * so not enabling it for now. | |
3513 | */ | |
3514 | ||
99389390 JRS |
3515 | /* 7.l */ |
3516 | intel_ddi_enable_fec(encoder, crtc_state); | |
3517 | intel_dsc_enable(encoder, crtc_state); | |
3518 | } | |
3519 | ||
3520 | static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, | |
3521 | const struct intel_crtc_state *crtc_state, | |
3522 | const struct drm_connector_state *conn_state) | |
e404ba8d | 3523 | { |
ba88d153 MN |
3524 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
3525 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
0fce04c8 | 3526 | enum port port = encoder->port; |
dc867bc7 | 3527 | enum phy phy = intel_port_to_phy(dev_priv, port); |
62b69566 | 3528 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
45e0327e | 3529 | bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); |
d02ace87 | 3530 | int level = intel_ddi_dp_level(intel_dp); |
b2ccb822 | 3531 | |
45e0327e | 3532 | WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); |
e081c846 | 3533 | |
45e0327e VS |
3534 | intel_dp_set_link_params(intel_dp, crtc_state->port_clock, |
3535 | crtc_state->lane_count, is_mst); | |
680b71c2 | 3536 | |
4444df6e LDM |
3537 | intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); |
3538 | intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); | |
3539 | ||
680b71c2 | 3540 | intel_edp_panel_on(intel_dp); |
32bdc400 | 3541 | |
0e5fa646 | 3542 | intel_ddi_clk_select(encoder, crtc_state); |
62b69566 | 3543 | |
d8fe2ab6 | 3544 | if (!intel_phy_is_tc(dev_priv, phy) || |
3b2ed431 ID |
3545 | dig_port->tc_mode != TC_PORT_TBT_ALT) |
3546 | intel_display_power_get(dev_priv, | |
3547 | dig_port->ddi_io_power_domain); | |
62b69566 | 3548 | |
3b51be4e | 3549 | icl_program_mg_dp_mode(dig_port, crtc_state); |
8aaf5cbd | 3550 | icl_phy_set_clock_gating(dig_port, false); |
340a44be | 3551 | |
2dd24a9c | 3552 | if (INTEL_GEN(dev_priv) >= 11) |
07685c82 MN |
3553 | icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, |
3554 | level, encoder->type); | |
fb5c8e9d | 3555 | else if (IS_CANNONLAKE(dev_priv)) |
f3cf4ba4 | 3556 | cnl_ddi_vswing_sequence(encoder, level, encoder->type); |
381f9570 | 3557 | else if (IS_GEN9_LP(dev_priv)) |
7d4f37b5 | 3558 | bxt_ddi_vswing_sequence(encoder, level, encoder->type); |
381f9570 | 3559 | else |
3a6d84e6 | 3560 | intel_prepare_dp_ddi_buffers(encoder, crtc_state); |
2f7460a7 | 3561 | |
d8fe2ab6 | 3562 | if (intel_phy_is_combo(dev_priv, phy)) { |
cfda08cd ID |
3563 | bool lane_reversal = |
3564 | dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; | |
3565 | ||
dc867bc7 | 3566 | intel_combo_phy_power_up_lanes(dev_priv, phy, false, |
cfda08cd ID |
3567 | crtc_state->lane_count, |
3568 | lane_reversal); | |
3569 | } | |
3570 | ||
ba88d153 | 3571 | intel_ddi_init_dp_buf_reg(encoder); |
be1c63c8 LP |
3572 | if (!is_mst) |
3573 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
2279298d GS |
3574 | intel_dp_sink_set_decompression_state(intel_dp, crtc_state, |
3575 | true); | |
a322b975 | 3576 | intel_dp_sink_set_fec_ready(intel_dp, crtc_state); |
ba88d153 | 3577 | intel_dp_start_link_train(intel_dp); |
eadf6f91 MN |
3578 | if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && |
3579 | !is_trans_port_sync_mode(crtc_state)) | |
ba88d153 | 3580 | intel_dp_stop_link_train(intel_dp); |
afb2c443 | 3581 | |
5c44b938 AS |
3582 | intel_ddi_enable_fec(encoder, crtc_state); |
3583 | ||
8aaf5cbd | 3584 | icl_phy_set_clock_gating(dig_port, true); |
bc334d91 | 3585 | |
2b5cf4ef ID |
3586 | if (!is_mst) |
3587 | intel_ddi_enable_pipe_clock(crtc_state); | |
7182414e MN |
3588 | |
3589 | intel_dsc_enable(encoder, crtc_state); | |
ba88d153 | 3590 | } |
901c2daf | 3591 | |
99389390 JRS |
3592 | static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, |
3593 | const struct intel_crtc_state *crtc_state, | |
3594 | const struct drm_connector_state *conn_state) | |
3595 | { | |
3596 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3597 | ||
3598 | if (INTEL_GEN(dev_priv) >= 12) | |
3599 | tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); | |
3600 | else | |
3601 | hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); | |
0c06fa15 GM |
3602 | |
3603 | intel_ddi_set_dp_msa(crtc_state, conn_state); | |
99389390 JRS |
3604 | } |
3605 | ||
ba88d153 | 3606 | static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, |
ac240288 | 3607 | const struct intel_crtc_state *crtc_state, |
45e0327e | 3608 | const struct drm_connector_state *conn_state) |
ba88d153 | 3609 | { |
f99be1b3 VS |
3610 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
3611 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
ba88d153 | 3612 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0fce04c8 | 3613 | enum port port = encoder->port; |
ba88d153 | 3614 | int level = intel_ddi_hdmi_level(dev_priv, port); |
62b69566 | 3615 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
c19b0669 | 3616 | |
ba88d153 | 3617 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
0e5fa646 | 3618 | intel_ddi_clk_select(encoder, crtc_state); |
62b69566 ACO |
3619 | |
3620 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); | |
3621 | ||
3b51be4e | 3622 | icl_program_mg_dp_mode(dig_port, crtc_state); |
8aaf5cbd | 3623 | icl_phy_set_clock_gating(dig_port, false); |
cb9ff519 | 3624 | |
978c3e53 CT |
3625 | if (INTEL_GEN(dev_priv) >= 12) |
3626 | tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, | |
3627 | level, INTEL_OUTPUT_HDMI); | |
3628 | else if (INTEL_GEN(dev_priv) == 11) | |
07685c82 MN |
3629 | icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, |
3630 | level, INTEL_OUTPUT_HDMI); | |
fb5c8e9d | 3631 | else if (IS_CANNONLAKE(dev_priv)) |
f3cf4ba4 | 3632 | cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); |
cc3f90f0 | 3633 | else if (IS_GEN9_LP(dev_priv)) |
7d4f37b5 | 3634 | bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); |
2f7460a7 | 3635 | else |
7ea79333 | 3636 | intel_prepare_hdmi_ddi_buffers(encoder, level); |
2f7460a7 | 3637 | |
8aaf5cbd | 3638 | icl_phy_set_clock_gating(dig_port, true); |
cb9ff519 | 3639 | |
2f7460a7 | 3640 | if (IS_GEN9_BC(dev_priv)) |
081dfcfa | 3641 | skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); |
8d8bb85e | 3642 | |
c7373764 ID |
3643 | intel_ddi_enable_pipe_clock(crtc_state); |
3644 | ||
790ea70c | 3645 | intel_dig_port->set_infoframes(encoder, |
45e0327e | 3646 | crtc_state->has_infoframe, |
f99be1b3 | 3647 | crtc_state, conn_state); |
ba88d153 | 3648 | } |
32bdc400 | 3649 | |
1524e93e | 3650 | static void intel_ddi_pre_enable(struct intel_encoder *encoder, |
45e0327e | 3651 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 3652 | const struct drm_connector_state *conn_state) |
ba88d153 | 3653 | { |
45e0327e VS |
3654 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
3655 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3656 | enum pipe pipe = crtc->pipe; | |
30cf6db8 | 3657 | |
1939ba51 VS |
3658 | /* |
3659 | * When called from DP MST code: | |
3660 | * - conn_state will be NULL | |
3661 | * - encoder will be the main encoder (ie. mst->primary) | |
3662 | * - the main connector associated with this port | |
3663 | * won't be active or linked to a crtc | |
3664 | * - crtc_state will be the state of the first stream to | |
3665 | * be activated on this port, and it may not be the same | |
3666 | * stream that will be deactivated last, but each stream | |
3667 | * should have a state that is identical when it comes to | |
3668 | * the DP link parameteres | |
3669 | */ | |
3670 | ||
45e0327e | 3671 | WARN_ON(crtc_state->has_pch_encoder); |
364a3fe1 | 3672 | |
3b8c0d5b JN |
3673 | if (INTEL_GEN(dev_priv) >= 11) |
3674 | icl_map_plls_to_ports(encoder, crtc_state); | |
3675 | ||
364a3fe1 JN |
3676 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
3677 | ||
06c812d7 | 3678 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
45e0327e | 3679 | intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); |
06c812d7 SS |
3680 | } else { |
3681 | struct intel_lspcon *lspcon = | |
3682 | enc_to_intel_lspcon(&encoder->base); | |
3683 | ||
45e0327e | 3684 | intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); |
06c812d7 SS |
3685 | if (lspcon->active) { |
3686 | struct intel_digital_port *dig_port = | |
3687 | enc_to_dig_port(&encoder->base); | |
3688 | ||
3689 | dig_port->set_infoframes(encoder, | |
3690 | crtc_state->has_infoframe, | |
3691 | crtc_state, conn_state); | |
3692 | } | |
3693 | } | |
6441ab5f PZ |
3694 | } |
3695 | ||
d6a09cee AS |
3696 | static void intel_disable_ddi_buf(struct intel_encoder *encoder, |
3697 | const struct intel_crtc_state *crtc_state) | |
e725f645 VS |
3698 | { |
3699 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
0fce04c8 | 3700 | enum port port = encoder->port; |
e725f645 VS |
3701 | bool wait = false; |
3702 | u32 val; | |
3703 | ||
3704 | val = I915_READ(DDI_BUF_CTL(port)); | |
3705 | if (val & DDI_BUF_CTL_ENABLE) { | |
3706 | val &= ~DDI_BUF_CTL_ENABLE; | |
3707 | I915_WRITE(DDI_BUF_CTL(port), val); | |
3708 | wait = true; | |
3709 | } | |
3710 | ||
e468ff06 | 3711 | if (intel_crtc_has_dp_encoder(crtc_state)) { |
4444df6e LDM |
3712 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
3713 | ||
3714 | val = I915_READ(intel_dp->regs.dp_tp_ctl); | |
e468ff06 LDM |
3715 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
3716 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
4444df6e | 3717 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
e468ff06 | 3718 | } |
e725f645 | 3719 | |
d6a09cee AS |
3720 | /* Disable FEC in DP Sink */ |
3721 | intel_ddi_disable_fec_state(encoder, crtc_state); | |
3722 | ||
e725f645 VS |
3723 | if (wait) |
3724 | intel_wait_ddi_buf_idle(dev_priv, port); | |
3725 | } | |
3726 | ||
f45f3da7 VS |
3727 | static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, |
3728 | const struct intel_crtc_state *old_crtc_state, | |
3729 | const struct drm_connector_state *old_conn_state) | |
6441ab5f | 3730 | { |
f45f3da7 VS |
3731 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3732 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
3733 | struct intel_dp *intel_dp = &dig_port->dp; | |
be1c63c8 LP |
3734 | bool is_mst = intel_crtc_has_type(old_crtc_state, |
3735 | INTEL_OUTPUT_DP_MST); | |
d8fe2ab6 | 3736 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
2886e93f | 3737 | |
2b5cf4ef ID |
3738 | if (!is_mst) { |
3739 | intel_ddi_disable_pipe_clock(old_crtc_state); | |
3740 | /* | |
3741 | * Power down sink before disabling the port, otherwise we end | |
3742 | * up getting interrupts from the sink on detecting link loss. | |
3743 | */ | |
be1c63c8 | 3744 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2b5cf4ef | 3745 | } |
c5f93fcf | 3746 | |
d6a09cee | 3747 | intel_disable_ddi_buf(encoder, old_crtc_state); |
7618138d | 3748 | |
f45f3da7 VS |
3749 | intel_edp_panel_vdd_on(intel_dp); |
3750 | intel_edp_panel_off(intel_dp); | |
a836bdf9 | 3751 | |
d8fe2ab6 | 3752 | if (!intel_phy_is_tc(dev_priv, phy) || |
3b2ed431 ID |
3753 | dig_port->tc_mode != TC_PORT_TBT_ALT) |
3754 | intel_display_power_put_unchecked(dev_priv, | |
3755 | dig_port->ddi_io_power_domain); | |
c5f93fcf | 3756 | |
f45f3da7 | 3757 | intel_ddi_clk_disable(encoder); |
bdacf087 | 3758 | tgl_clear_psr2_transcoder_exitline(old_crtc_state); |
f45f3da7 | 3759 | } |
c5f93fcf | 3760 | |
f45f3da7 VS |
3761 | static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, |
3762 | const struct intel_crtc_state *old_crtc_state, | |
3763 | const struct drm_connector_state *old_conn_state) | |
3764 | { | |
3765 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3766 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
3767 | struct intel_hdmi *intel_hdmi = &dig_port->hdmi; | |
82a4d9c0 | 3768 | |
790ea70c | 3769 | dig_port->set_infoframes(encoder, false, |
c7373764 ID |
3770 | old_crtc_state, old_conn_state); |
3771 | ||
afb2c443 ID |
3772 | intel_ddi_disable_pipe_clock(old_crtc_state); |
3773 | ||
d6a09cee | 3774 | intel_disable_ddi_buf(encoder, old_crtc_state); |
62b69566 | 3775 | |
0e6e0be4 CW |
3776 | intel_display_power_put_unchecked(dev_priv, |
3777 | dig_port->ddi_io_power_domain); | |
b2ccb822 | 3778 | |
f45f3da7 VS |
3779 | intel_ddi_clk_disable(encoder); |
3780 | ||
3781 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
3782 | } | |
3783 | ||
3784 | static void intel_ddi_post_disable(struct intel_encoder *encoder, | |
3785 | const struct intel_crtc_state *old_crtc_state, | |
3786 | const struct drm_connector_state *old_conn_state) | |
3787 | { | |
3b8c0d5b JN |
3788 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3789 | ||
f45f3da7 | 3790 | /* |
1939ba51 VS |
3791 | * When called from DP MST code: |
3792 | * - old_conn_state will be NULL | |
3793 | * - encoder will be the main encoder (ie. mst->primary) | |
3794 | * - the main connector associated with this port | |
3795 | * won't be active or linked to a crtc | |
3796 | * - old_crtc_state will be the state of the last stream to | |
3797 | * be deactivated on this port, and it may not be the same | |
3798 | * stream that was activated last, but each stream | |
3799 | * should have a state that is identical when it comes to | |
3800 | * the DP link parameteres | |
f45f3da7 | 3801 | */ |
1939ba51 VS |
3802 | |
3803 | if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) | |
f45f3da7 VS |
3804 | intel_ddi_post_disable_hdmi(encoder, |
3805 | old_crtc_state, old_conn_state); | |
3806 | else | |
3807 | intel_ddi_post_disable_dp(encoder, | |
3808 | old_crtc_state, old_conn_state); | |
3b8c0d5b JN |
3809 | |
3810 | if (INTEL_GEN(dev_priv) >= 11) | |
3811 | icl_unmap_plls_to_ports(encoder); | |
6441ab5f PZ |
3812 | } |
3813 | ||
1524e93e | 3814 | void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3815 | const struct intel_crtc_state *old_crtc_state, |
3816 | const struct drm_connector_state *old_conn_state) | |
b7076546 | 3817 | { |
1524e93e | 3818 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3d0c5005 | 3819 | u32 val; |
b7076546 ML |
3820 | |
3821 | /* | |
3822 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) | |
3823 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, | |
3824 | * step 13 is the correct place for it. Step 18 is where it was | |
3825 | * originally before the BUN. | |
3826 | */ | |
3827 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
3828 | val &= ~FDI_RX_ENABLE; | |
3829 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
3830 | ||
d6a09cee | 3831 | intel_disable_ddi_buf(encoder, old_crtc_state); |
fb0bd3bd | 3832 | intel_ddi_clk_disable(encoder); |
b7076546 ML |
3833 | |
3834 | val = I915_READ(FDI_RX_MISC(PIPE_A)); | |
3835 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
3836 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
3837 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); | |
3838 | ||
3839 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
3840 | val &= ~FDI_PCDCLK; | |
3841 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
3842 | ||
3843 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
3844 | val &= ~FDI_RX_PLL_ENABLE; | |
3845 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
3846 | } | |
3847 | ||
15d05f0e VS |
3848 | static void intel_enable_ddi_dp(struct intel_encoder *encoder, |
3849 | const struct intel_crtc_state *crtc_state, | |
3850 | const struct drm_connector_state *conn_state) | |
72662e10 | 3851 | { |
15d05f0e VS |
3852 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3853 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
0fce04c8 | 3854 | enum port port = encoder->port; |
72662e10 | 3855 | |
15d05f0e VS |
3856 | if (port == PORT_A && INTEL_GEN(dev_priv) < 9) |
3857 | intel_dp_stop_link_train(intel_dp); | |
d6c50ff8 | 3858 | |
15d05f0e VS |
3859 | intel_edp_backlight_on(crtc_state, conn_state); |
3860 | intel_psr_enable(intel_dp, crtc_state); | |
bb71fb00 | 3861 | intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); |
b246cf21 | 3862 | intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); |
15d05f0e | 3863 | intel_edp_drrs_enable(intel_dp, crtc_state); |
3ab9c637 | 3864 | |
15d05f0e VS |
3865 | if (crtc_state->has_audio) |
3866 | intel_audio_codec_enable(encoder, crtc_state, conn_state); | |
3867 | } | |
3868 | ||
8f19b401 ID |
3869 | static i915_reg_t |
3870 | gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, | |
3871 | enum port port) | |
3872 | { | |
3873 | static const i915_reg_t regs[] = { | |
3874 | [PORT_A] = CHICKEN_TRANS_EDP, | |
3875 | [PORT_B] = CHICKEN_TRANS_A, | |
3876 | [PORT_C] = CHICKEN_TRANS_B, | |
3877 | [PORT_D] = CHICKEN_TRANS_C, | |
3878 | [PORT_E] = CHICKEN_TRANS_A, | |
3879 | }; | |
3880 | ||
3881 | WARN_ON(INTEL_GEN(dev_priv) < 9); | |
3882 | ||
3883 | if (WARN_ON(port < PORT_A || port > PORT_E)) | |
3884 | port = PORT_A; | |
3885 | ||
3886 | return regs[port]; | |
3887 | } | |
3888 | ||
15d05f0e VS |
3889 | static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, |
3890 | const struct intel_crtc_state *crtc_state, | |
3891 | const struct drm_connector_state *conn_state) | |
3892 | { | |
3893 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3894 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
277ab5ab | 3895 | struct drm_connector *connector = conn_state->connector; |
0fce04c8 | 3896 | enum port port = encoder->port; |
15d05f0e | 3897 | |
277ab5ab VS |
3898 | if (!intel_hdmi_handle_sink_scrambling(encoder, connector, |
3899 | crtc_state->hdmi_high_tmds_clock_ratio, | |
3900 | crtc_state->hdmi_scrambling)) | |
3901 | DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", | |
3902 | connector->base.id, connector->name); | |
15d05f0e | 3903 | |
0519c102 VS |
3904 | /* Display WA #1143: skl,kbl,cfl */ |
3905 | if (IS_GEN9_BC(dev_priv)) { | |
3906 | /* | |
3907 | * For some reason these chicken bits have been | |
3908 | * stuffed into a transcoder register, event though | |
3909 | * the bits affect a specific DDI port rather than | |
3910 | * a specific transcoder. | |
3911 | */ | |
8f19b401 | 3912 | i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); |
0519c102 VS |
3913 | u32 val; |
3914 | ||
8f19b401 | 3915 | val = I915_READ(reg); |
0519c102 VS |
3916 | |
3917 | if (port == PORT_E) | |
3918 | val |= DDIE_TRAINING_OVERRIDE_ENABLE | | |
3919 | DDIE_TRAINING_OVERRIDE_VALUE; | |
3920 | else | |
3921 | val |= DDI_TRAINING_OVERRIDE_ENABLE | | |
3922 | DDI_TRAINING_OVERRIDE_VALUE; | |
3923 | ||
8f19b401 ID |
3924 | I915_WRITE(reg, val); |
3925 | POSTING_READ(reg); | |
0519c102 VS |
3926 | |
3927 | udelay(1); | |
3928 | ||
3929 | if (port == PORT_E) | |
3930 | val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | | |
3931 | DDIE_TRAINING_OVERRIDE_VALUE); | |
3932 | else | |
3933 | val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | | |
3934 | DDI_TRAINING_OVERRIDE_VALUE); | |
3935 | ||
8f19b401 | 3936 | I915_WRITE(reg, val); |
0519c102 VS |
3937 | } |
3938 | ||
15d05f0e VS |
3939 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
3940 | * are ignored so nothing special needs to be done besides | |
3941 | * enabling the port. | |
3942 | */ | |
3943 | I915_WRITE(DDI_BUF_CTL(port), | |
3944 | dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); | |
7b9f35a6 | 3945 | |
15d05f0e VS |
3946 | if (crtc_state->has_audio) |
3947 | intel_audio_codec_enable(encoder, crtc_state, conn_state); | |
3948 | } | |
3949 | ||
3950 | static void intel_enable_ddi(struct intel_encoder *encoder, | |
3951 | const struct intel_crtc_state *crtc_state, | |
3952 | const struct drm_connector_state *conn_state) | |
3953 | { | |
3954 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
3955 | intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); | |
3956 | else | |
3957 | intel_enable_ddi_dp(encoder, crtc_state, conn_state); | |
ee5e5e7a SP |
3958 | |
3959 | /* Enable hdcp if it's desired */ | |
3960 | if (conn_state->content_protection == | |
3961 | DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
d456512c R |
3962 | intel_hdcp_enable(to_intel_connector(conn_state->connector), |
3963 | (u8)conn_state->hdcp_content_type); | |
5ab432ef DV |
3964 | } |
3965 | ||
33f083f0 VS |
3966 | static void intel_disable_ddi_dp(struct intel_encoder *encoder, |
3967 | const struct intel_crtc_state *old_crtc_state, | |
3968 | const struct drm_connector_state *old_conn_state) | |
5ab432ef | 3969 | { |
33f083f0 | 3970 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
d6c50ff8 | 3971 | |
edb2e530 VS |
3972 | intel_dp->link_trained = false; |
3973 | ||
37255d8d | 3974 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
3975 | intel_audio_codec_disable(encoder, |
3976 | old_crtc_state, old_conn_state); | |
2831d842 | 3977 | |
33f083f0 VS |
3978 | intel_edp_drrs_disable(intel_dp, old_crtc_state); |
3979 | intel_psr_disable(intel_dp, old_crtc_state); | |
3980 | intel_edp_backlight_off(old_conn_state); | |
2279298d GS |
3981 | /* Disable the decompression in DP Sink */ |
3982 | intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, | |
3983 | false); | |
33f083f0 | 3984 | } |
15953637 | 3985 | |
33f083f0 VS |
3986 | static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, |
3987 | const struct intel_crtc_state *old_crtc_state, | |
3988 | const struct drm_connector_state *old_conn_state) | |
3989 | { | |
277ab5ab VS |
3990 | struct drm_connector *connector = old_conn_state->connector; |
3991 | ||
33f083f0 | 3992 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
3993 | intel_audio_codec_disable(encoder, |
3994 | old_crtc_state, old_conn_state); | |
d6c50ff8 | 3995 | |
277ab5ab VS |
3996 | if (!intel_hdmi_handle_sink_scrambling(encoder, connector, |
3997 | false, false)) | |
3998 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", | |
3999 | connector->base.id, connector->name); | |
33f083f0 VS |
4000 | } |
4001 | ||
4002 | static void intel_disable_ddi(struct intel_encoder *encoder, | |
4003 | const struct intel_crtc_state *old_crtc_state, | |
4004 | const struct drm_connector_state *old_conn_state) | |
4005 | { | |
ee5e5e7a SP |
4006 | intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); |
4007 | ||
33f083f0 VS |
4008 | if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) |
4009 | intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); | |
4010 | else | |
4011 | intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); | |
72662e10 | 4012 | } |
79f689aa | 4013 | |
2ef82327 HG |
4014 | static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, |
4015 | const struct intel_crtc_state *crtc_state, | |
4016 | const struct drm_connector_state *conn_state) | |
4017 | { | |
4018 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
4019 | ||
0c06fa15 | 4020 | intel_ddi_set_dp_msa(crtc_state, conn_state); |
5aa2c9ae | 4021 | |
23ec9f52 | 4022 | intel_psr_update(intel_dp, crtc_state); |
2ef82327 | 4023 | intel_edp_drrs_enable(intel_dp, crtc_state); |
63a23d24 ML |
4024 | |
4025 | intel_panel_update_backlight(encoder, crtc_state, conn_state); | |
2ef82327 HG |
4026 | } |
4027 | ||
4028 | static void intel_ddi_update_pipe(struct intel_encoder *encoder, | |
4029 | const struct intel_crtc_state *crtc_state, | |
4030 | const struct drm_connector_state *conn_state) | |
4031 | { | |
d456512c R |
4032 | struct intel_connector *connector = |
4033 | to_intel_connector(conn_state->connector); | |
4034 | struct intel_hdcp *hdcp = &connector->hdcp; | |
4035 | bool content_protection_type_changed = | |
4036 | (conn_state->hdcp_content_type != hdcp->content_type && | |
4037 | conn_state->content_protection != | |
4038 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED); | |
4039 | ||
2ef82327 HG |
4040 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
4041 | intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); | |
634852d1 | 4042 | |
d456512c R |
4043 | /* |
4044 | * During the HDCP encryption session if Type change is requested, | |
4045 | * disable the HDCP and reenable it with new TYPE value. | |
4046 | */ | |
634852d1 | 4047 | if (conn_state->content_protection == |
d456512c R |
4048 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED || |
4049 | content_protection_type_changed) | |
4050 | intel_hdcp_disable(connector); | |
4051 | ||
4052 | /* | |
4053 | * Mark the hdcp state as DESIRED after the hdcp disable of type | |
4054 | * change procedure. | |
4055 | */ | |
4056 | if (content_protection_type_changed) { | |
4057 | mutex_lock(&hdcp->mutex); | |
4058 | hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
4059 | schedule_work(&hdcp->prop_work); | |
4060 | mutex_unlock(&hdcp->mutex); | |
4061 | } | |
4062 | ||
4063 | if (conn_state->content_protection == | |
4064 | DRM_MODE_CONTENT_PROTECTION_DESIRED || | |
4065 | content_protection_type_changed) | |
4066 | intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type); | |
2ef82327 HG |
4067 | } |
4068 | ||
24a7bfe0 ID |
4069 | static void |
4070 | intel_ddi_update_prepare(struct intel_atomic_state *state, | |
4071 | struct intel_encoder *encoder, | |
4072 | struct intel_crtc *crtc) | |
4073 | { | |
4074 | struct intel_crtc_state *crtc_state = | |
4075 | crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; | |
4076 | int required_lanes = crtc_state ? crtc_state->lane_count : 1; | |
4077 | ||
4078 | WARN_ON(crtc && crtc->active); | |
4079 | ||
4080 | intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); | |
4081 | if (crtc_state && crtc_state->base.active) | |
4082 | intel_update_active_dpll(state, crtc, encoder); | |
4083 | } | |
4084 | ||
4085 | static void | |
4086 | intel_ddi_update_complete(struct intel_atomic_state *state, | |
4087 | struct intel_encoder *encoder, | |
4088 | struct intel_crtc *crtc) | |
4089 | { | |
4090 | intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); | |
4091 | } | |
4092 | ||
bdaa29b6 ID |
4093 | static void |
4094 | intel_ddi_pre_pll_enable(struct intel_encoder *encoder, | |
4095 | const struct intel_crtc_state *crtc_state, | |
4096 | const struct drm_connector_state *conn_state) | |
03ad7d88 | 4097 | { |
bdaa29b6 | 4098 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
03ad7d88 | 4099 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
d8fe2ab6 MR |
4100 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
4101 | bool is_tc_port = intel_phy_is_tc(dev_priv, phy); | |
bdaa29b6 | 4102 | |
24a7bfe0 ID |
4103 | if (is_tc_port) |
4104 | intel_tc_port_get_link(dig_port, crtc_state->lane_count); | |
4105 | ||
4106 | if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) | |
bdaa29b6 ID |
4107 | intel_display_power_get(dev_priv, |
4108 | intel_ddi_main_link_aux_domain(dig_port)); | |
4109 | ||
9d44dcb9 LDM |
4110 | if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) |
4111 | /* | |
4112 | * Program the lane count for static/dynamic connections on | |
4113 | * Type-C ports. Skip this step for TBT. | |
4114 | */ | |
4115 | intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); | |
4116 | else if (IS_GEN9_LP(dev_priv)) | |
bdaa29b6 ID |
4117 | bxt_ddi_phy_set_lane_optim_mask(encoder, |
4118 | crtc_state->lane_lat_optim_mask); | |
bdaa29b6 ID |
4119 | } |
4120 | ||
4121 | static void | |
4122 | intel_ddi_post_pll_disable(struct intel_encoder *encoder, | |
4123 | const struct intel_crtc_state *crtc_state, | |
4124 | const struct drm_connector_state *conn_state) | |
4125 | { | |
4126 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4127 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
d8fe2ab6 MR |
4128 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
4129 | bool is_tc_port = intel_phy_is_tc(dev_priv, phy); | |
bdaa29b6 | 4130 | |
24a7bfe0 | 4131 | if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) |
0e6e0be4 CW |
4132 | intel_display_power_put_unchecked(dev_priv, |
4133 | intel_ddi_main_link_aux_domain(dig_port)); | |
24a7bfe0 ID |
4134 | |
4135 | if (is_tc_port) | |
4136 | intel_tc_port_put_link(dig_port); | |
03ad7d88 MN |
4137 | } |
4138 | ||
97068c1b | 4139 | static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 4140 | { |
ad64217b ACO |
4141 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4142 | struct drm_i915_private *dev_priv = | |
4143 | to_i915(intel_dig_port->base.base.dev); | |
8f4f2797 | 4144 | enum port port = intel_dig_port->base.port; |
3d0c5005 | 4145 | u32 val; |
f3e227df | 4146 | bool wait = false; |
c19b0669 | 4147 | |
4444df6e | 4148 | if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) { |
c19b0669 PZ |
4149 | val = I915_READ(DDI_BUF_CTL(port)); |
4150 | if (val & DDI_BUF_CTL_ENABLE) { | |
4151 | val &= ~DDI_BUF_CTL_ENABLE; | |
4152 | I915_WRITE(DDI_BUF_CTL(port), val); | |
4153 | wait = true; | |
4154 | } | |
4155 | ||
4444df6e | 4156 | val = I915_READ(intel_dp->regs.dp_tp_ctl); |
c19b0669 PZ |
4157 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
4158 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
4444df6e LDM |
4159 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
4160 | POSTING_READ(intel_dp->regs.dp_tp_ctl); | |
c19b0669 PZ |
4161 | |
4162 | if (wait) | |
4163 | intel_wait_ddi_buf_idle(dev_priv, port); | |
4164 | } | |
4165 | ||
0e32b39c | 4166 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 4167 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
64ee2fd2 | 4168 | if (intel_dp->link_mst) |
0e32b39c DA |
4169 | val |= DP_TP_CTL_MODE_MST; |
4170 | else { | |
4171 | val |= DP_TP_CTL_MODE_SST; | |
4172 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
4173 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
4174 | } | |
4444df6e LDM |
4175 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
4176 | POSTING_READ(intel_dp->regs.dp_tp_ctl); | |
c19b0669 PZ |
4177 | |
4178 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
4179 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
4180 | POSTING_READ(DDI_BUF_CTL(port)); | |
4181 | ||
4182 | udelay(600); | |
4183 | } | |
00c09d70 | 4184 | |
2085cc5d VS |
4185 | static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
4186 | enum transcoder cpu_transcoder) | |
9935f7fa | 4187 | { |
2085cc5d VS |
4188 | if (cpu_transcoder == TRANSCODER_EDP) |
4189 | return false; | |
9935f7fa | 4190 | |
2085cc5d VS |
4191 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) |
4192 | return false; | |
4193 | ||
4194 | return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & | |
4195 | AUDIO_OUTPUT_ENABLE(cpu_transcoder); | |
9935f7fa LY |
4196 | } |
4197 | ||
53e9bf5e VS |
4198 | void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, |
4199 | struct intel_crtc_state *crtc_state) | |
4200 | { | |
2dd24a9c | 4201 | if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) |
9378985e | 4202 | crtc_state->min_voltage_level = 1; |
36c1f028 RV |
4203 | else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) |
4204 | crtc_state->min_voltage_level = 2; | |
53e9bf5e VS |
4205 | } |
4206 | ||
6801c18c | 4207 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 4208 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 4209 | { |
fac5e23e | 4210 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
35686a44 | 4211 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
0cb09a97 | 4212 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
045ac3b5 JB |
4213 | u32 temp, flags = 0; |
4214 | ||
4d1de975 JN |
4215 | /* XXX: DSI transcoder paranoia */ |
4216 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) | |
4217 | return; | |
4218 | ||
045ac3b5 JB |
4219 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
4220 | if (temp & TRANS_DDI_PHSYNC) | |
4221 | flags |= DRM_MODE_FLAG_PHSYNC; | |
4222 | else | |
4223 | flags |= DRM_MODE_FLAG_NHSYNC; | |
4224 | if (temp & TRANS_DDI_PVSYNC) | |
4225 | flags |= DRM_MODE_FLAG_PVSYNC; | |
4226 | else | |
4227 | flags |= DRM_MODE_FLAG_NVSYNC; | |
4228 | ||
2d112de7 | 4229 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
4230 | |
4231 | switch (temp & TRANS_DDI_BPC_MASK) { | |
4232 | case TRANS_DDI_BPC_6: | |
4233 | pipe_config->pipe_bpp = 18; | |
4234 | break; | |
4235 | case TRANS_DDI_BPC_8: | |
4236 | pipe_config->pipe_bpp = 24; | |
4237 | break; | |
4238 | case TRANS_DDI_BPC_10: | |
4239 | pipe_config->pipe_bpp = 30; | |
4240 | break; | |
4241 | case TRANS_DDI_BPC_12: | |
4242 | pipe_config->pipe_bpp = 36; | |
4243 | break; | |
4244 | default: | |
4245 | break; | |
4246 | } | |
eb14cb74 VS |
4247 | |
4248 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
4249 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 4250 | pipe_config->has_hdmi_sink = true; |
bbd440fb | 4251 | |
e5e70d4a VS |
4252 | pipe_config->infoframes.enable |= |
4253 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
4254 | ||
4255 | if (pipe_config->infoframes.enable) | |
bbd440fb | 4256 | pipe_config->has_infoframe = true; |
15953637 | 4257 | |
ab2cb2cb | 4258 | if (temp & TRANS_DDI_HDMI_SCRAMBLING) |
15953637 SS |
4259 | pipe_config->hdmi_scrambling = true; |
4260 | if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) | |
4261 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
d4d6279a | 4262 | /* fall through */ |
eb14cb74 | 4263 | case TRANS_DDI_MODE_SELECT_DVI: |
e1214b95 | 4264 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
d4d6279a ACO |
4265 | pipe_config->lane_count = 4; |
4266 | break; | |
eb14cb74 | 4267 | case TRANS_DDI_MODE_SELECT_FDI: |
e1214b95 | 4268 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
eb14cb74 VS |
4269 | break; |
4270 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e1214b95 VS |
4271 | if (encoder->type == INTEL_OUTPUT_EDP) |
4272 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); | |
4273 | else | |
4274 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); | |
4275 | pipe_config->lane_count = | |
4276 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
4277 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
8aa940c8 ML |
4278 | |
4279 | if (INTEL_GEN(dev_priv) >= 11) { | |
4280 | i915_reg_t dp_tp_ctl; | |
4281 | ||
4282 | if (IS_GEN(dev_priv, 11)) | |
4283 | dp_tp_ctl = DP_TP_CTL(encoder->port); | |
4284 | else | |
4285 | dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); | |
4286 | ||
4287 | pipe_config->fec_enable = | |
4288 | I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; | |
4289 | ||
4290 | DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", | |
4291 | encoder->base.base.id, encoder->base.name, | |
4292 | pipe_config->fec_enable); | |
4293 | } | |
4294 | ||
e1214b95 | 4295 | break; |
eb14cb74 | 4296 | case TRANS_DDI_MODE_SELECT_DP_MST: |
e1214b95 | 4297 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); |
90a6b7b0 VS |
4298 | pipe_config->lane_count = |
4299 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
4300 | intel_dp_get_m_n(intel_crtc, pipe_config); |
4301 | break; | |
4302 | default: | |
4303 | break; | |
4304 | } | |
10214420 | 4305 | |
bdacf087 AG |
4306 | if (encoder->type == INTEL_OUTPUT_EDP) |
4307 | tgl_dc3co_exitline_get_config(pipe_config); | |
4308 | ||
9935f7fa | 4309 | pipe_config->has_audio = |
2085cc5d | 4310 | intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); |
9ed109a7 | 4311 | |
6aa23e65 JN |
4312 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
4313 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
10214420 DV |
4314 | /* |
4315 | * This is a big fat ugly hack. | |
4316 | * | |
4317 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
4318 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
4319 | * unknown we fail to light up. Yet the same BIOS boots up with | |
4320 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
4321 | * max, not what it tells us to use. | |
4322 | * | |
4323 | * Note: This will still be broken if the eDP panel is not lit | |
4324 | * up by the BIOS, and thus we can't get the mode at module | |
4325 | * load. | |
4326 | */ | |
4327 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
4328 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
4329 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
10214420 | 4330 | } |
11578553 | 4331 | |
22606a18 | 4332 | intel_ddi_clock_get(encoder, pipe_config); |
95a7a2ae | 4333 | |
cc3f90f0 | 4334 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae ID |
4335 | pipe_config->lane_lat_optim_mask = |
4336 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); | |
53e9bf5e VS |
4337 | |
4338 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); | |
f2a10d61 VS |
4339 | |
4340 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
4341 | ||
4342 | intel_read_infoframe(encoder, pipe_config, | |
4343 | HDMI_INFOFRAME_TYPE_AVI, | |
4344 | &pipe_config->infoframes.avi); | |
4345 | intel_read_infoframe(encoder, pipe_config, | |
4346 | HDMI_INFOFRAME_TYPE_SPD, | |
4347 | &pipe_config->infoframes.spd); | |
4348 | intel_read_infoframe(encoder, pipe_config, | |
4349 | HDMI_INFOFRAME_TYPE_VENDOR, | |
4350 | &pipe_config->infoframes.hdmi); | |
b37f588e US |
4351 | intel_read_infoframe(encoder, pipe_config, |
4352 | HDMI_INFOFRAME_TYPE_DRM, | |
4353 | &pipe_config->infoframes.drm); | |
045ac3b5 JB |
4354 | } |
4355 | ||
7e732cac VS |
4356 | static enum intel_output_type |
4357 | intel_ddi_compute_output_type(struct intel_encoder *encoder, | |
4358 | struct intel_crtc_state *crtc_state, | |
4359 | struct drm_connector_state *conn_state) | |
4360 | { | |
4361 | switch (conn_state->connector->connector_type) { | |
4362 | case DRM_MODE_CONNECTOR_HDMIA: | |
4363 | return INTEL_OUTPUT_HDMI; | |
4364 | case DRM_MODE_CONNECTOR_eDP: | |
4365 | return INTEL_OUTPUT_EDP; | |
4366 | case DRM_MODE_CONNECTOR_DisplayPort: | |
4367 | return INTEL_OUTPUT_DP; | |
4368 | default: | |
4369 | MISSING_CASE(conn_state->connector->connector_type); | |
4370 | return INTEL_OUTPUT_UNUSED; | |
4371 | } | |
4372 | } | |
4373 | ||
204474a6 LP |
4374 | static int intel_ddi_compute_config(struct intel_encoder *encoder, |
4375 | struct intel_crtc_state *pipe_config, | |
4376 | struct drm_connector_state *conn_state) | |
00c09d70 | 4377 | { |
dc0c0bfe | 4378 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
fac5e23e | 4379 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0fce04c8 | 4380 | enum port port = encoder->port; |
95a7a2ae | 4381 | int ret; |
00c09d70 | 4382 | |
bc7e3525 | 4383 | if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) |
eccb140b DV |
4384 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
4385 | ||
bdacf087 | 4386 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { |
0a478c27 | 4387 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
bdacf087 | 4388 | } else { |
0a478c27 | 4389 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
bdacf087 AG |
4390 | tgl_dc3co_exitline_compute_config(encoder, pipe_config); |
4391 | } | |
4392 | ||
7a412b8f VS |
4393 | if (ret) |
4394 | return ret; | |
95a7a2ae | 4395 | |
dc0c0bfe VS |
4396 | if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && |
4397 | pipe_config->cpu_transcoder == TRANSCODER_EDP) | |
4398 | pipe_config->pch_pfit.force_thru = | |
4399 | pipe_config->pch_pfit.enabled || | |
4400 | pipe_config->crc_enabled; | |
4401 | ||
7a412b8f | 4402 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae | 4403 | pipe_config->lane_lat_optim_mask = |
5161d058 | 4404 | bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); |
95a7a2ae | 4405 | |
53e9bf5e VS |
4406 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |
4407 | ||
7a412b8f | 4408 | return 0; |
00c09d70 PZ |
4409 | } |
4410 | ||
f6bff60e ID |
4411 | static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) |
4412 | { | |
4413 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
f6bff60e ID |
4414 | |
4415 | intel_dp_encoder_flush_work(encoder); | |
4416 | ||
f6bff60e ID |
4417 | drm_encoder_cleanup(encoder); |
4418 | kfree(dig_port); | |
4419 | } | |
4420 | ||
00c09d70 | 4421 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
32691b58 | 4422 | .reset = intel_dp_encoder_reset, |
f6bff60e | 4423 | .destroy = intel_ddi_encoder_destroy, |
00c09d70 PZ |
4424 | }; |
4425 | ||
4a28ae58 PZ |
4426 | static struct intel_connector * |
4427 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
4428 | { | |
4429 | struct intel_connector *connector; | |
8f4f2797 | 4430 | enum port port = intel_dig_port->base.port; |
4a28ae58 | 4431 | |
9bdbd0b9 | 4432 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
4433 | if (!connector) |
4434 | return NULL; | |
4435 | ||
4436 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
97068c1b VS |
4437 | intel_dig_port->dp.prepare_link_retrain = |
4438 | intel_ddi_prepare_link_retrain; | |
4439 | ||
4a28ae58 PZ |
4440 | if (!intel_dp_init_connector(intel_dig_port, connector)) { |
4441 | kfree(connector); | |
4442 | return NULL; | |
4443 | } | |
4444 | ||
4445 | return connector; | |
4446 | } | |
4447 | ||
dba14b27 VS |
4448 | static int modeset_pipe(struct drm_crtc *crtc, |
4449 | struct drm_modeset_acquire_ctx *ctx) | |
4450 | { | |
4451 | struct drm_atomic_state *state; | |
4452 | struct drm_crtc_state *crtc_state; | |
4453 | int ret; | |
4454 | ||
4455 | state = drm_atomic_state_alloc(crtc->dev); | |
4456 | if (!state) | |
4457 | return -ENOMEM; | |
4458 | ||
4459 | state->acquire_ctx = ctx; | |
4460 | ||
4461 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
4462 | if (IS_ERR(crtc_state)) { | |
4463 | ret = PTR_ERR(crtc_state); | |
4464 | goto out; | |
4465 | } | |
4466 | ||
b8fe992a | 4467 | crtc_state->connectors_changed = true; |
dba14b27 | 4468 | |
dba14b27 | 4469 | ret = drm_atomic_commit(state); |
a551cd66 | 4470 | out: |
dba14b27 VS |
4471 | drm_atomic_state_put(state); |
4472 | ||
4473 | return ret; | |
4474 | } | |
4475 | ||
4476 | static int intel_hdmi_reset_link(struct intel_encoder *encoder, | |
4477 | struct drm_modeset_acquire_ctx *ctx) | |
4478 | { | |
4479 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4480 | struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); | |
4481 | struct intel_connector *connector = hdmi->attached_connector; | |
4482 | struct i2c_adapter *adapter = | |
4483 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
4484 | struct drm_connector_state *conn_state; | |
4485 | struct intel_crtc_state *crtc_state; | |
4486 | struct intel_crtc *crtc; | |
4487 | u8 config; | |
4488 | int ret; | |
4489 | ||
4490 | if (!connector || connector->base.status != connector_status_connected) | |
4491 | return 0; | |
4492 | ||
4493 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
4494 | ctx); | |
4495 | if (ret) | |
4496 | return ret; | |
4497 | ||
4498 | conn_state = connector->base.state; | |
4499 | ||
4500 | crtc = to_intel_crtc(conn_state->crtc); | |
4501 | if (!crtc) | |
4502 | return 0; | |
4503 | ||
4504 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
4505 | if (ret) | |
4506 | return ret; | |
4507 | ||
4508 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
4509 | ||
4510 | WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); | |
4511 | ||
4512 | if (!crtc_state->base.active) | |
4513 | return 0; | |
4514 | ||
4515 | if (!crtc_state->hdmi_high_tmds_clock_ratio && | |
4516 | !crtc_state->hdmi_scrambling) | |
4517 | return 0; | |
4518 | ||
4519 | if (conn_state->commit && | |
4520 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
4521 | return 0; | |
4522 | ||
4523 | ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); | |
4524 | if (ret < 0) { | |
4525 | DRM_ERROR("Failed to read TMDS config: %d\n", ret); | |
4526 | return 0; | |
4527 | } | |
4528 | ||
4529 | if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == | |
4530 | crtc_state->hdmi_high_tmds_clock_ratio && | |
4531 | !!(config & SCDC_SCRAMBLING_ENABLE) == | |
4532 | crtc_state->hdmi_scrambling) | |
4533 | return 0; | |
4534 | ||
4535 | /* | |
4536 | * HDMI 2.0 says that one should not send scrambled data | |
4537 | * prior to configuring the sink scrambling, and that | |
4538 | * TMDS clock/data transmission should be suspended when | |
4539 | * changing the TMDS clock rate in the sink. So let's | |
4540 | * just do a full modeset here, even though some sinks | |
4541 | * would be perfectly happy if were to just reconfigure | |
4542 | * the SCDC settings on the fly. | |
4543 | */ | |
4544 | return modeset_pipe(&crtc->base, ctx); | |
4545 | } | |
4546 | ||
3944709d ID |
4547 | static enum intel_hotplug_state |
4548 | intel_ddi_hotplug(struct intel_encoder *encoder, | |
4549 | struct intel_connector *connector, | |
4550 | bool irq_received) | |
dba14b27 | 4551 | { |
bb80c925 | 4552 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
dba14b27 | 4553 | struct drm_modeset_acquire_ctx ctx; |
3944709d | 4554 | enum intel_hotplug_state state; |
dba14b27 VS |
4555 | int ret; |
4556 | ||
3944709d | 4557 | state = intel_encoder_hotplug(encoder, connector, irq_received); |
dba14b27 VS |
4558 | |
4559 | drm_modeset_acquire_init(&ctx, 0); | |
4560 | ||
4561 | for (;;) { | |
c85d200e VS |
4562 | if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) |
4563 | ret = intel_hdmi_reset_link(encoder, &ctx); | |
4564 | else | |
4565 | ret = intel_dp_retrain_link(encoder, &ctx); | |
dba14b27 VS |
4566 | |
4567 | if (ret == -EDEADLK) { | |
4568 | drm_modeset_backoff(&ctx); | |
4569 | continue; | |
4570 | } | |
4571 | ||
4572 | break; | |
4573 | } | |
4574 | ||
4575 | drm_modeset_drop_locks(&ctx); | |
4576 | drm_modeset_acquire_fini(&ctx); | |
4577 | WARN(ret, "Acquiring modeset locks failed with %i\n", ret); | |
4578 | ||
bb80c925 JRS |
4579 | /* |
4580 | * Unpowered type-c dongles can take some time to boot and be | |
4581 | * responsible, so here giving some time to those dongles to power up | |
4582 | * and then retrying the probe. | |
4583 | * | |
4584 | * On many platforms the HDMI live state signal is known to be | |
4585 | * unreliable, so we can't use it to detect if a sink is connected or | |
4586 | * not. Instead we detect if it's connected based on whether we can | |
4587 | * read the EDID or not. That in turn has a problem during disconnect, | |
4588 | * since the HPD interrupt may be raised before the DDC lines get | |
4589 | * disconnected (due to how the required length of DDC vs. HPD | |
4590 | * connector pins are specified) and so we'll still be able to get a | |
4591 | * valid EDID. To solve this schedule another detection cycle if this | |
4592 | * time around we didn't detect any change in the sink's connection | |
4593 | * status. | |
4594 | */ | |
4595 | if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && | |
4596 | !dig_port->dp.is_mst) | |
4597 | state = INTEL_HOTPLUG_RETRY; | |
4598 | ||
3944709d | 4599 | return state; |
dba14b27 VS |
4600 | } |
4601 | ||
4a28ae58 PZ |
4602 | static struct intel_connector * |
4603 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
4604 | { | |
4605 | struct intel_connector *connector; | |
8f4f2797 | 4606 | enum port port = intel_dig_port->base.port; |
4a28ae58 | 4607 | |
9bdbd0b9 | 4608 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
4609 | if (!connector) |
4610 | return NULL; | |
4611 | ||
4612 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
4613 | intel_hdmi_init_connector(intel_dig_port, connector); | |
4614 | ||
4615 | return connector; | |
4616 | } | |
4617 | ||
436009b5 RV |
4618 | static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) |
4619 | { | |
4620 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
4621 | ||
8f4f2797 | 4622 | if (dport->base.port != PORT_A) |
436009b5 RV |
4623 | return false; |
4624 | ||
4625 | if (dport->saved_port_bits & DDI_A_4_LANES) | |
4626 | return false; | |
4627 | ||
4628 | /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only | |
4629 | * supported configuration | |
4630 | */ | |
4631 | if (IS_GEN9_LP(dev_priv)) | |
4632 | return true; | |
4633 | ||
4634 | /* Cannonlake: Most of SKUs don't support DDI_E, and the only | |
4635 | * one who does also have a full A/E split called | |
4636 | * DDI_F what makes DDI_E useless. However for this | |
4637 | * case let's trust VBT info. | |
4638 | */ | |
4639 | if (IS_CANNONLAKE(dev_priv) && | |
4640 | !intel_bios_is_port_present(dev_priv, PORT_E)) | |
4641 | return true; | |
4642 | ||
4643 | return false; | |
4644 | } | |
4645 | ||
3d2011cf MK |
4646 | static int |
4647 | intel_ddi_max_lanes(struct intel_digital_port *intel_dport) | |
4648 | { | |
4649 | struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); | |
4650 | enum port port = intel_dport->base.port; | |
4651 | int max_lanes = 4; | |
4652 | ||
4653 | if (INTEL_GEN(dev_priv) >= 11) | |
4654 | return max_lanes; | |
4655 | ||
4656 | if (port == PORT_A || port == PORT_E) { | |
4657 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
4658 | max_lanes = port == PORT_A ? 4 : 0; | |
4659 | else | |
4660 | /* Both A and E share 2 lanes */ | |
4661 | max_lanes = 2; | |
4662 | } | |
4663 | ||
4664 | /* | |
4665 | * Some BIOS might fail to set this bit on port A if eDP | |
4666 | * wasn't lit up at boot. Force this bit set when needed | |
4667 | * so we use the proper lane count for our calculations. | |
4668 | */ | |
4669 | if (intel_ddi_a_force_4_lanes(intel_dport)) { | |
4670 | DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); | |
4671 | intel_dport->saved_port_bits |= DDI_A_4_LANES; | |
4672 | max_lanes = 4; | |
4673 | } | |
4674 | ||
4675 | return max_lanes; | |
4676 | } | |
4677 | ||
c39055b0 | 4678 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) |
00c09d70 | 4679 | { |
f6bff60e ID |
4680 | struct ddi_vbt_port_info *port_info = |
4681 | &dev_priv->vbt.ddi_port_info[port]; | |
00c09d70 PZ |
4682 | struct intel_digital_port *intel_dig_port; |
4683 | struct intel_encoder *intel_encoder; | |
4684 | struct drm_encoder *encoder; | |
ff662124 | 4685 | bool init_hdmi, init_dp, init_lspcon = false; |
570b16b5 | 4686 | enum pipe pipe; |
d8fe2ab6 | 4687 | enum phy phy = intel_port_to_phy(dev_priv, port); |
10e7bec3 | 4688 | |
f6bff60e ID |
4689 | init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; |
4690 | init_dp = port_info->supports_dp; | |
ff662124 SS |
4691 | |
4692 | if (intel_bios_is_lspcon_present(dev_priv, port)) { | |
4693 | /* | |
4694 | * Lspcon device needs to be driven with DP connector | |
4695 | * with special detection sequence. So make sure DP | |
4696 | * is initialized before lspcon. | |
4697 | */ | |
4698 | init_dp = true; | |
4699 | init_lspcon = true; | |
4700 | init_hdmi = false; | |
4701 | DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); | |
4702 | } | |
4703 | ||
311a2094 | 4704 | if (!init_dp && !init_hdmi) { |
500ea70d | 4705 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 4706 | port_name(port)); |
500ea70d | 4707 | return; |
311a2094 | 4708 | } |
00c09d70 | 4709 | |
b14c5679 | 4710 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
4711 | if (!intel_dig_port) |
4712 | return; | |
4713 | ||
00c09d70 PZ |
4714 | intel_encoder = &intel_dig_port->base; |
4715 | encoder = &intel_encoder->base; | |
4716 | ||
c39055b0 | 4717 | drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, |
580d8ed5 | 4718 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
00c09d70 | 4719 | |
c85d200e | 4720 | intel_encoder->hotplug = intel_ddi_hotplug; |
7e732cac | 4721 | intel_encoder->compute_output_type = intel_ddi_compute_output_type; |
5bfe2ac0 | 4722 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 | 4723 | intel_encoder->enable = intel_enable_ddi; |
bdaa29b6 ID |
4724 | intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable; |
4725 | intel_encoder->post_pll_disable = intel_ddi_post_pll_disable; | |
00c09d70 PZ |
4726 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
4727 | intel_encoder->disable = intel_disable_ddi; | |
4728 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2ef82327 | 4729 | intel_encoder->update_pipe = intel_ddi_update_pipe; |
00c09d70 | 4730 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
045ac3b5 | 4731 | intel_encoder->get_config = intel_ddi_get_config; |
a171f8e7 | 4732 | intel_encoder->suspend = intel_dp_encoder_suspend; |
62b69566 | 4733 | intel_encoder->get_power_domains = intel_ddi_get_power_domains; |
3d2011cf MK |
4734 | intel_encoder->type = INTEL_OUTPUT_DDI; |
4735 | intel_encoder->power_domain = intel_port_to_power_domain(port); | |
4736 | intel_encoder->port = port; | |
3d2011cf | 4737 | intel_encoder->cloneable = 0; |
570b16b5 MK |
4738 | for_each_pipe(dev_priv, pipe) |
4739 | intel_encoder->crtc_mask |= BIT(pipe); | |
00c09d70 | 4740 | |
1e6aa7e5 JN |
4741 | if (INTEL_GEN(dev_priv) >= 11) |
4742 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & | |
4743 | DDI_BUF_PORT_REVERSAL; | |
4744 | else | |
4745 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & | |
4746 | (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); | |
3d2011cf MK |
4747 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
4748 | intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); | |
39053089 | 4749 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
00c09d70 | 4750 | |
d8fe2ab6 | 4751 | if (intel_phy_is_tc(dev_priv, phy)) { |
ab7bc4e1 ID |
4752 | bool is_legacy = !port_info->supports_typec_usb && |
4753 | !port_info->supports_tbt; | |
4754 | ||
4755 | intel_tc_port_init(intel_dig_port, is_legacy); | |
24a7bfe0 ID |
4756 | |
4757 | intel_encoder->update_prepare = intel_ddi_update_prepare; | |
4758 | intel_encoder->update_complete = intel_ddi_update_complete; | |
ab7bc4e1 | 4759 | } |
f6bff60e | 4760 | |
327f8d8c LDM |
4761 | WARN_ON(port > PORT_I); |
4762 | intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + | |
4763 | port - PORT_A; | |
62b69566 | 4764 | |
f68d697e CW |
4765 | if (init_dp) { |
4766 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
4767 | goto err; | |
13cf5504 | 4768 | |
f68d697e | 4769 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
f68d697e | 4770 | } |
21a8e6a4 | 4771 | |
311a2094 PZ |
4772 | /* In theory we don't need the encoder->type check, but leave it just in |
4773 | * case we have some really bad VBTs... */ | |
f68d697e CW |
4774 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
4775 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
4776 | goto err; | |
21a8e6a4 | 4777 | } |
f68d697e | 4778 | |
ff662124 SS |
4779 | if (init_lspcon) { |
4780 | if (lspcon_init(intel_dig_port)) | |
4781 | /* TODO: handle hdmi info frame part */ | |
4782 | DRM_DEBUG_KMS("LSPCON init success on port %c\n", | |
4783 | port_name(port)); | |
4784 | else | |
4785 | /* | |
4786 | * LSPCON init faied, but DP init was success, so | |
4787 | * lets try to drive as DP++ port. | |
4788 | */ | |
4789 | DRM_ERROR("LSPCON init failed on port %c\n", | |
4790 | port_name(port)); | |
4791 | } | |
4792 | ||
06c812d7 | 4793 | intel_infoframe_init(intel_dig_port); |
f6bff60e | 4794 | |
f68d697e CW |
4795 | return; |
4796 | ||
4797 | err: | |
4798 | drm_encoder_cleanup(encoder); | |
4799 | kfree(intel_dig_port); | |
00c09d70 | 4800 | } |