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drm/i915/guc: Avoid reclaim locks during reset
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / display / intel_ddi.c
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45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
dba14b27 28#include <drm/drm_scdc_helper.h>
331c201a 29
45244b87 30#include "i915_drv.h"
331c201a 31#include "intel_audio.h"
cfda08cd 32#include "intel_combo_phy.h"
ec7f29ff 33#include "intel_connector.h"
fdc24cf3 34#include "intel_ddi.h"
27fec1f9 35#include "intel_dp.h"
e075094f 36#include "intel_dp_link_training.h"
b1ad4c39 37#include "intel_dpio_phy.h"
45244b87 38#include "intel_drv.h"
1dd07e56 39#include "intel_dsi.h"
8834e365 40#include "intel_fifo_underrun.h"
3ce2ea65 41#include "intel_gmbus.h"
408bd917 42#include "intel_hdcp.h"
0550691d 43#include "intel_hdmi.h"
dbeb38d9 44#include "intel_hotplug.h"
f3e18947 45#include "intel_lspcon.h"
44c1220a 46#include "intel_panel.h"
55367a27 47#include "intel_psr.h"
bc85328f 48#include "intel_tc.h"
b375d0ef 49#include "intel_vdsc.h"
45244b87 50
10122051
JN		 51struct ddi_buf_trans {
52 u32 trans1; /* balance leg enable, de-emph level */
53 u32 trans2; /* vref sel, vswing */
f8896f5d 54 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 55};
56
97eeb872
VS		 57static const u8 index_to_dp_signal_levels[] = {
58 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
59 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
60 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
61 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
62 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
63 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
64 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
65 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
68};
69
45244b87
ED		 70/* HDMI/DVI modes ignore everything but the last 2 items. So we share
71 * them for both DP and FDI transports, allowing those ports to
72 * automatically adapt to HDMI connections as well
73 */
10122051 74static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 75 { 0x00FFFFFF, 0x0006000E, 0x0 },
76 { 0x00D75FFF, 0x0005000A, 0x0 },
77 { 0x00C30FFF, 0x00040006, 0x0 },
78 { 0x80AAAFFF, 0x000B0000, 0x0 },
79 { 0x00FFFFFF, 0x0005000A, 0x0 },
80 { 0x00D75FFF, 0x000C0004, 0x0 },
81 { 0x80C30FFF, 0x000B0000, 0x0 },
82 { 0x00FFFFFF, 0x00040006, 0x0 },
83 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 84};
85
10122051 86static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 87 { 0x00FFFFFF, 0x0007000E, 0x0 },
88 { 0x00D75FFF, 0x000F000A, 0x0 },
89 { 0x00C30FFF, 0x00060006, 0x0 },
90 { 0x00AAAFFF, 0x001E0000, 0x0 },
91 { 0x00FFFFFF, 0x000F000A, 0x0 },
92 { 0x00D75FFF, 0x00160004, 0x0 },
93 { 0x00C30FFF, 0x001E0000, 0x0 },
94 { 0x00FFFFFF, 0x00060006, 0x0 },
95 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 96};
97
10122051
JN		 98static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
99 /* Idx NT mV d T mV d db */
f8896f5d
DW		 100 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
101 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
102 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
103 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
104 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
105 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
106 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
107 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
108 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
109 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
110 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
111 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 112};
113
10122051 114static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 115 { 0x00FFFFFF, 0x00000012, 0x0 },
116 { 0x00EBAFFF, 0x00020011, 0x0 },
117 { 0x00C71FFF, 0x0006000F, 0x0 },
118 { 0x00AAAFFF, 0x000E000A, 0x0 },
119 { 0x00FFFFFF, 0x00020011, 0x0 },
120 { 0x00DB6FFF, 0x0005000F, 0x0 },
121 { 0x00BEEFFF, 0x000A000C, 0x0 },
122 { 0x00FFFFFF, 0x0005000F, 0x0 },
123 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 124};
125
10122051 126static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 127 { 0x00FFFFFF, 0x0007000E, 0x0 },
128 { 0x00D75FFF, 0x000E000A, 0x0 },
129 { 0x00BEFFFF, 0x00140006, 0x0 },
130 { 0x80B2CFFF, 0x001B0002, 0x0 },
131 { 0x00FFFFFF, 0x000E000A, 0x0 },
132 { 0x00DB6FFF, 0x00160005, 0x0 },
133 { 0x80C71FFF, 0x001A0002, 0x0 },
134 { 0x00F7DFFF, 0x00180004, 0x0 },
135 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 136};
137
10122051 138static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 139 { 0x00FFFFFF, 0x0001000E, 0x0 },
140 { 0x00D75FFF, 0x0004000A, 0x0 },
141 { 0x00C30FFF, 0x00070006, 0x0 },
142 { 0x00AAAFFF, 0x000C0000, 0x0 },
143 { 0x00FFFFFF, 0x0004000A, 0x0 },
144 { 0x00D75FFF, 0x00090004, 0x0 },
145 { 0x00C30FFF, 0x000C0000, 0x0 },
146 { 0x00FFFFFF, 0x00070006, 0x0 },
147 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 148};
149
10122051
JN		 150static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
151 /* Idx NT mV d T mV df db */
f8896f5d
DW		 152 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
153 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
154 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
155 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
156 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
157 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
158 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
159 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
160 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
161 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 162};
163
5f8b2531 164/* Skylake H and S */
7f88e3af 165static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 166 { 0x00002016, 0x000000A0, 0x0 },
167 { 0x00005012, 0x0000009B, 0x0 },
168 { 0x00007011, 0x00000088, 0x0 },
d7097cff 169 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 170 { 0x00002016, 0x0000009B, 0x0 },
171 { 0x00005012, 0x00000088, 0x0 },
d7097cff 172 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 173 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 174 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 175};
176
f8896f5d
DW		 177/* Skylake U */
178static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 179 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 180 { 0x00005012, 0x00000088, 0x0 },
5ac90567 181 { 0x80007011, 0x000000CD, 0x1 },
d7097cff 182 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 183 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 184 { 0x80005012, 0x000000C0, 0x1 },
185 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 186 { 0x00002016, 0x00000088, 0x0 },
d7097cff 187 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 188};
189
5f8b2531
RV		 190/* Skylake Y */
191static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 192 { 0x00000018, 0x000000A2, 0x0 },
193 { 0x00005012, 0x00000088, 0x0 },
5ac90567 194 { 0x80007011, 0x000000CD, 0x3 },
d7097cff 195 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 196 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 197 { 0x80005012, 0x000000C0, 0x3 },
198 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 199 { 0x00000018, 0x00000088, 0x0 },
d7097cff 200 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 201};
202
0fdd4918
RV		 203/* Kabylake H and S */
204static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
205 { 0x00002016, 0x000000A0, 0x0 },
206 { 0x00005012, 0x0000009B, 0x0 },
207 { 0x00007011, 0x00000088, 0x0 },
208 { 0x80009010, 0x000000C0, 0x1 },
209 { 0x00002016, 0x0000009B, 0x0 },
210 { 0x00005012, 0x00000088, 0x0 },
211 { 0x80007011, 0x000000C0, 0x1 },
212 { 0x00002016, 0x00000097, 0x0 },
213 { 0x80005012, 0x000000C0, 0x1 },
214};
215
216/* Kabylake U */
217static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
218 { 0x0000201B, 0x000000A1, 0x0 },
219 { 0x00005012, 0x00000088, 0x0 },
220 { 0x80007011, 0x000000CD, 0x3 },
221 { 0x80009010, 0x000000C0, 0x3 },
222 { 0x0000201B, 0x0000009D, 0x0 },
223 { 0x80005012, 0x000000C0, 0x3 },
224 { 0x80007011, 0x000000C0, 0x3 },
225 { 0x00002016, 0x0000004F, 0x0 },
226 { 0x80005012, 0x000000C0, 0x3 },
227};
228
229/* Kabylake Y */
230static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
231 { 0x00001017, 0x000000A1, 0x0 },
232 { 0x00005012, 0x00000088, 0x0 },
233 { 0x80007011, 0x000000CD, 0x3 },
234 { 0x8000800F, 0x000000C0, 0x3 },
235 { 0x00001017, 0x0000009D, 0x0 },
236 { 0x80005012, 0x000000C0, 0x3 },
237 { 0x80007011, 0x000000C0, 0x3 },
238 { 0x00001017, 0x0000004C, 0x0 },
239 { 0x80005012, 0x000000C0, 0x3 },
240};
241
f8896f5d 242/*
0fdd4918 243 * Skylake/Kabylake H and S
f8896f5d
DW		 244 * eDP 1.4 low vswing translation parameters
245 */
7ad14a29 246static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 247 { 0x00000018, 0x000000A8, 0x0 },
248 { 0x00004013, 0x000000A9, 0x0 },
249 { 0x00007011, 0x000000A2, 0x0 },
250 { 0x00009010, 0x0000009C, 0x0 },
251 { 0x00000018, 0x000000A9, 0x0 },
252 { 0x00006013, 0x000000A2, 0x0 },
253 { 0x00007011, 0x000000A6, 0x0 },
254 { 0x00000018, 0x000000AB, 0x0 },
255 { 0x00007013, 0x0000009F, 0x0 },
256 { 0x00000018, 0x000000DF, 0x0 },
257};
258
259/*
0fdd4918 260 * Skylake/Kabylake U
f8896f5d
DW		 261 * eDP 1.4 low vswing translation parameters
262 */
263static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
264 { 0x00000018, 0x000000A8, 0x0 },
265 { 0x00004013, 0x000000A9, 0x0 },
266 { 0x00007011, 0x000000A2, 0x0 },
267 { 0x00009010, 0x0000009C, 0x0 },
268 { 0x00000018, 0x000000A9, 0x0 },
269 { 0x00006013, 0x000000A2, 0x0 },
270 { 0x00007011, 0x000000A6, 0x0 },
271 { 0x00002016, 0x000000AB, 0x0 },
272 { 0x00005013, 0x0000009F, 0x0 },
273 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 274};
275
f8896f5d 276/*
0fdd4918 277 * Skylake/Kabylake Y
f8896f5d
DW		 278 * eDP 1.4 low vswing translation parameters
279 */
5f8b2531 280static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 281 { 0x00000018, 0x000000A8, 0x0 },
282 { 0x00004013, 0x000000AB, 0x0 },
283 { 0x00007011, 0x000000A4, 0x0 },
284 { 0x00009010, 0x000000DF, 0x0 },
285 { 0x00000018, 0x000000AA, 0x0 },
286 { 0x00006013, 0x000000A4, 0x0 },
287 { 0x00007011, 0x0000009D, 0x0 },
288 { 0x00000018, 0x000000A0, 0x0 },
289 { 0x00006012, 0x000000DF, 0x0 },
290 { 0x00000018, 0x0000008A, 0x0 },
291};
7ad14a29 292
0fdd4918 293/* Skylake/Kabylake U, H and S */
7f88e3af 294static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 295 { 0x00000018, 0x000000AC, 0x0 },
296 { 0x00005012, 0x0000009D, 0x0 },
297 { 0x00007011, 0x00000088, 0x0 },
298 { 0x00000018, 0x000000A1, 0x0 },
299 { 0x00000018, 0x00000098, 0x0 },
300 { 0x00004013, 0x00000088, 0x0 },
2e78416e 301 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 302 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 303 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
304 { 0x80003015, 0x000000C0, 0x1 },
305 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 306};
307
0fdd4918 308/* Skylake/Kabylake Y */
5f8b2531 309static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 310 { 0x00000018, 0x000000A1, 0x0 },
311 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 312 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 313 { 0x00000018, 0x000000A4, 0x0 },
314 { 0x00000018, 0x0000009D, 0x0 },
315 { 0x00004013, 0x00000080, 0x0 },
2e78416e 316 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 317 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 318 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
319 { 0x80003015, 0x000000C0, 0x3 },
320 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 321};
322
96fb9f9b 323struct bxt_ddi_buf_trans {
ac3ad6c6
VS		 324 u8 margin; /* swing value */
325 u8 scale; /* scale value */
326 u8 enable; /* scale enable */
327 u8 deemphasis;
96fb9f9b
VK		 328};
329
96fb9f9b
VK		 330static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
331 /* Idx NT mV diff db */
043eaf36
VS		 332 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
333 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
334 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
335 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
336 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
337 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
338 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
339 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
340 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
341 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 342};
343
d9d7000d
SJ		 344static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
345 /* Idx NT mV diff db */
043eaf36
VS		 346 { 26, 0, 0, 128, }, /* 0: 200 0 */
347 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
348 { 48, 0, 0, 96, }, /* 2: 200 4 */
349 { 54, 0, 0, 69, }, /* 3: 200 6 */
350 { 32, 0, 0, 128, }, /* 4: 250 0 */
351 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
352 { 54, 0, 0, 85, }, /* 6: 250 4 */
353 { 43, 0, 0, 128, }, /* 7: 300 0 */
354 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
355 { 48, 0, 0, 128, }, /* 9: 300 0 */
d9d7000d
SJ		 356};
357
96fb9f9b
VK		 358/* BSpec has 2 recommended values - entries 0 and 8.
359 * Using the entry with higher vswing.
360 */
361static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
362 /* Idx NT mV diff db */
043eaf36
VS		 363 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
364 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
365 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
366 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
367 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
368 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
369 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
370 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
371 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
372 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
96fb9f9b
VK		 373};
374
83fb7ab4 375struct cnl_ddi_buf_trans {
fb5f4e96
VS		 376 u8 dw2_swing_sel;
377 u8 dw7_n_scalar;
378 u8 dw4_cursor_coeff;
379 u8 dw4_post_cursor_2;
380 u8 dw4_post_cursor_1;
83fb7ab4
RV		 381};
382
383/* Voltage Swing Programming for VccIO 0.85V for DP */
384static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
385 /* NT mV Trans mV db */
386 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
387 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
388 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
389 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
390 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
391 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
392 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
393 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
394 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
395 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
396};
397
398/* Voltage Swing Programming for VccIO 0.85V for HDMI */
399static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
400 /* NT mV Trans mV db */
401 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
402 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
403 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
404 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
405 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
406 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
407 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
408};
409
410/* Voltage Swing Programming for VccIO 0.85V for eDP */
411static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
412 /* NT mV Trans mV db */
413 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
414 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
415 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
416 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
417 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
418 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
419 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
420 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
421 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
422};
423
424/* Voltage Swing Programming for VccIO 0.95V for DP */
425static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
426 /* NT mV Trans mV db */
427 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
428 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
429 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
430 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
431 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
432 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
433 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
434 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
435 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
436 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
437};
438
439/* Voltage Swing Programming for VccIO 0.95V for HDMI */
440static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
441 /* NT mV Trans mV db */
442 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
443 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
444 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
445 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
446 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
447 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
448 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
449 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
450 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
451 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
452 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
453};
454
455/* Voltage Swing Programming for VccIO 0.95V for eDP */
456static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
457 /* NT mV Trans mV db */
458 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
459 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
461 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
462 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
463 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
464 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
465 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
466 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
467 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
468};
469
470/* Voltage Swing Programming for VccIO 1.05V for DP */
471static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
472 /* NT mV Trans mV db */
473 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
474 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
475 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
476 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
477 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
478 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
479 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
480 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
481 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
483};
484
485/* Voltage Swing Programming for VccIO 1.05V for HDMI */
486static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
487 /* NT mV Trans mV db */
488 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
489 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
490 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
491 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
492 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
493 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
494 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
495 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
496 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
497 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
498 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
499};
500
501/* Voltage Swing Programming for VccIO 1.05V for eDP */
502static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
503 /* NT mV Trans mV db */
504 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
505 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
506 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
507 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
508 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
509 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
510 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
511 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
512 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
513};
514
b265a2a6
CT		 515/* icl_combo_phy_ddi_translations */
516static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
517 /* NT mV Trans mV db */
518 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
519 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
520 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
521 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
522 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
523 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
524 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
525 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
526 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
527 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 528};
529
b265a2a6
CT		 530static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
531 /* NT mV Trans mV db */
532 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
533 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
534 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
535 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
536 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
537 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
538 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
539 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
540 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
541 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
19b904f8
MN		 542};
543
b265a2a6
CT		 544static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
545 /* NT mV Trans mV db */
546 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
547 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
548 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
549 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
550 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
551 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
552 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
553 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
554 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
555 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
19b904f8
MN		 556};
557
b265a2a6
CT		 558static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
559 /* NT mV Trans mV db */
560 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
561 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
562 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
563 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
564 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
565 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
566 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
19b904f8
MN		 567};
568
cd96bea7
MN		 569struct icl_mg_phy_ddi_buf_trans {
570 u32 cri_txdeemph_override_5_0;
571 u32 cri_txdeemph_override_11_6;
572 u32 cri_txdeemph_override_17_12;
573};
574
575static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
576 /* Voltage swing pre-emphasis */
577 { 0x0, 0x1B, 0x00 }, /* 0 0 */
578 { 0x0, 0x23, 0x08 }, /* 0 1 */
579 { 0x0, 0x2D, 0x12 }, /* 0 2 */
580 { 0x0, 0x00, 0x00 }, /* 0 3 */
581 { 0x0, 0x23, 0x00 }, /* 1 0 */
582 { 0x0, 0x2B, 0x09 }, /* 1 1 */
583 { 0x0, 0x2E, 0x11 }, /* 1 2 */
584 { 0x0, 0x2F, 0x00 }, /* 2 0 */
585 { 0x0, 0x33, 0x0C }, /* 2 1 */
586 { 0x0, 0x00, 0x00 }, /* 3 0 */
587};
588
a930acd9
VS		 589static const struct ddi_buf_trans *
590bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
591{
592 if (dev_priv->vbt.edp.low_vswing) {
593 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
594 return bdw_ddi_translations_edp;
595 } else {
596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 return bdw_ddi_translations_dp;
598 }
599}
600
acee2998 601static const struct ddi_buf_trans *
78ab0bae 602skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 603{
0fdd4918 604 if (IS_SKL_ULX(dev_priv)) {
5f8b2531 605 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 606 return skl_y_ddi_translations_dp;
0fdd4918 607 } else if (IS_SKL_ULT(dev_priv)) {
f8896f5d 608 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 609 return skl_u_ddi_translations_dp;
f8896f5d 610 } else {
f8896f5d 611 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 612 return skl_ddi_translations_dp;
f8896f5d 613 }
f8896f5d
DW		 614}
615
0fdd4918
RV		 616static const struct ddi_buf_trans *
617kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
618{
6ce1c33d 619 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
0fdd4918
RV		 620 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
621 return kbl_y_ddi_translations_dp;
da411a48 622 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
0fdd4918
RV		 623 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
624 return kbl_u_ddi_translations_dp;
625 } else {
626 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
627 return kbl_ddi_translations_dp;
628 }
629}
630
acee2998 631static const struct ddi_buf_trans *
78ab0bae 632skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 633{
06411f08 634 if (dev_priv->vbt.edp.low_vswing) {
6ce1c33d
VS		 635 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
636 IS_CFL_ULX(dev_priv)) {
5f8b2531 637 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 638 return skl_y_ddi_translations_edp;
da411a48
RV		 639 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
640 IS_CFL_ULT(dev_priv)) {
f8896f5d 641 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 642 return skl_u_ddi_translations_edp;
f8896f5d 643 } else {
f8896f5d 644 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 645 return skl_ddi_translations_edp;
f8896f5d
DW		 646 }
647 }
cd1101cb 648
da411a48 649 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
0fdd4918
RV		 650 return kbl_get_buf_trans_dp(dev_priv, n_entries);
651 else
652 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 653}
654
655static const struct ddi_buf_trans *
78ab0bae 656skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 657{
6ce1c33d
VS		 658 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
659 IS_CFL_ULX(dev_priv)) {
5f8b2531 660 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 661 return skl_y_ddi_translations_hdmi;
f8896f5d 662 } else {
f8896f5d 663 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 664 return skl_ddi_translations_hdmi;
f8896f5d 665 }
f8896f5d
DW		 666}
667
edba48fd
VS		 668static int skl_buf_trans_num_entries(enum port port, int n_entries)
669{
670 /* Only DDIA and DDIE can select the 10th register with DP */
671 if (port == PORT_A || port == PORT_E)
672 return min(n_entries, 10);
673 else
674 return min(n_entries, 9);
675}
676
d8fe2c7f
VS		 677static const struct ddi_buf_trans *
678intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
edba48fd 679 enum port port, int *n_entries)
d8fe2c7f
VS		 680{
681 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
edba48fd
VS		 682 const struct ddi_buf_trans *ddi_translations =
683 kbl_get_buf_trans_dp(dev_priv, n_entries);
684 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
685 return ddi_translations;
d8fe2c7f 686 } else if (IS_SKYLAKE(dev_priv)) {
edba48fd
VS		 687 const struct ddi_buf_trans *ddi_translations =
688 skl_get_buf_trans_dp(dev_priv, n_entries);
689 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
690 return ddi_translations;
d8fe2c7f
VS		 691 } else if (IS_BROADWELL(dev_priv)) {
692 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
693 return bdw_ddi_translations_dp;
694 } else if (IS_HASWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 return hsw_ddi_translations_dp;
697 }
698
699 *n_entries = 0;
700 return NULL;
701}
702
703static const struct ddi_buf_trans *
704intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
edba48fd 705 enum port port, int *n_entries)
d8fe2c7f
VS		 706{
707 if (IS_GEN9_BC(dev_priv)) {
edba48fd
VS		 708 const struct ddi_buf_trans *ddi_translations =
709 skl_get_buf_trans_edp(dev_priv, n_entries);
710 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
711 return ddi_translations;
d8fe2c7f
VS		 712 } else if (IS_BROADWELL(dev_priv)) {
713 return bdw_get_buf_trans_edp(dev_priv, n_entries);
714 } else if (IS_HASWELL(dev_priv)) {
715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
716 return hsw_ddi_translations_dp;
717 }
718
719 *n_entries = 0;
720 return NULL;
721}
722
723static const struct ddi_buf_trans *
724intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
725 int *n_entries)
726{
727 if (IS_BROADWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
729 return bdw_ddi_translations_fdi;
730 } else if (IS_HASWELL(dev_priv)) {
731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 return hsw_ddi_translations_fdi;
733 }
734
735 *n_entries = 0;
736 return NULL;
737}
738
975786ee
VS		 739static const struct ddi_buf_trans *
740intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
741 int *n_entries)
742{
743 if (IS_GEN9_BC(dev_priv)) {
744 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
745 } else if (IS_BROADWELL(dev_priv)) {
746 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
747 return bdw_ddi_translations_hdmi;
748 } else if (IS_HASWELL(dev_priv)) {
749 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
750 return hsw_ddi_translations_hdmi;
751 }
752
753 *n_entries = 0;
754 return NULL;
755}
756
7d4f37b5
VS		 757static const struct bxt_ddi_buf_trans *
758bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
759{
760 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
761 return bxt_ddi_translations_dp;
762}
763
764static const struct bxt_ddi_buf_trans *
765bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
766{
767 if (dev_priv->vbt.edp.low_vswing) {
768 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
769 return bxt_ddi_translations_edp;
770 }
771
772 return bxt_get_buf_trans_dp(dev_priv, n_entries);
773}
774
775static const struct bxt_ddi_buf_trans *
776bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
777{
778 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
779 return bxt_ddi_translations_hdmi;
780}
781
cf3e0fb4
RV		 782static const struct cnl_ddi_buf_trans *
783cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
784{
785 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
786
787 if (voltage == VOLTAGE_INFO_0_85V) {
788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
789 return cnl_ddi_translations_hdmi_0_85V;
790 } else if (voltage == VOLTAGE_INFO_0_95V) {
791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
792 return cnl_ddi_translations_hdmi_0_95V;
793 } else if (voltage == VOLTAGE_INFO_1_05V) {
794 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
795 return cnl_ddi_translations_hdmi_1_05V;
83482ca3
AB		 796 } else {
797 *n_entries = 1; /* shut up gcc */
cf3e0fb4 798 MISSING_CASE(voltage);
83482ca3 799 }
cf3e0fb4
RV		 800 return NULL;
801}
802
803static const struct cnl_ddi_buf_trans *
804cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
805{
806 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
807
808 if (voltage == VOLTAGE_INFO_0_85V) {
809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
810 return cnl_ddi_translations_dp_0_85V;
811 } else if (voltage == VOLTAGE_INFO_0_95V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
813 return cnl_ddi_translations_dp_0_95V;
814 } else if (voltage == VOLTAGE_INFO_1_05V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
816 return cnl_ddi_translations_dp_1_05V;
83482ca3
AB		 817 } else {
818 *n_entries = 1; /* shut up gcc */
cf3e0fb4 819 MISSING_CASE(voltage);
83482ca3 820 }
cf3e0fb4
RV		 821 return NULL;
822}
823
824static const struct cnl_ddi_buf_trans *
825cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
826{
827 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
828
829 if (dev_priv->vbt.edp.low_vswing) {
830 if (voltage == VOLTAGE_INFO_0_85V) {
831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
832 return cnl_ddi_translations_edp_0_85V;
833 } else if (voltage == VOLTAGE_INFO_0_95V) {
834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
835 return cnl_ddi_translations_edp_0_95V;
836 } else if (voltage == VOLTAGE_INFO_1_05V) {
837 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
838 return cnl_ddi_translations_edp_1_05V;
83482ca3
AB		 839 } else {
840 *n_entries = 1; /* shut up gcc */
cf3e0fb4 841 MISSING_CASE(voltage);
83482ca3 842 }
cf3e0fb4
RV		 843 return NULL;
844 } else {
845 return cnl_get_buf_trans_dp(dev_priv, n_entries);
846 }
847}
848
b265a2a6 849static const struct cnl_ddi_buf_trans *
fb5c8e9d 850icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
b265a2a6 851 int type, int rate, int *n_entries)
fb5c8e9d 852{
b265a2a6
CT		 853 if (type == INTEL_OUTPUT_HDMI) {
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
855 return icl_combo_phy_ddi_translations_hdmi;
856 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
858 return icl_combo_phy_ddi_translations_edp_hbr3;
859 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
860 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
861 return icl_combo_phy_ddi_translations_edp_hbr2;
fb5c8e9d 862 }
b265a2a6
CT		 863
864 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
865 return icl_combo_phy_ddi_translations_dp_hbr2;
fb5c8e9d
MN		 866}
867
8d8bb85e
VS		 868static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
869{
d02ace87 870 int n_entries, level, default_entry;
8d8bb85e 871
d02ace87 872 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
8d8bb85e 873
2dd24a9c 874 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 875 if (intel_port_is_combophy(dev_priv, port))
b265a2a6
CT		 876 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
877 0, &n_entries);
dccc7228
MN		 878 else
879 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
880 default_entry = n_entries - 1;
881 } else if (IS_CANNONLAKE(dev_priv)) {
d02ace87
VS		 882 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
883 default_entry = n_entries - 1;
043eaf36 884 } else if (IS_GEN9_LP(dev_priv)) {
d02ace87
VS		 885 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
886 default_entry = n_entries - 1;
bf503556 887 } else if (IS_GEN9_BC(dev_priv)) {
d02ace87
VS		 888 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
889 default_entry = 8;
8d8bb85e 890 } else if (IS_BROADWELL(dev_priv)) {
d02ace87
VS		 891 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
892 default_entry = 7;
8d8bb85e 893 } else if (IS_HASWELL(dev_priv)) {
d02ace87
VS		 894 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
895 default_entry = 6;
8d8bb85e
VS		 896 } else {
897 WARN(1, "ddi translation table missing\n");
975786ee 898 return 0;
8d8bb85e
VS		 899 }
900
901 /* Choose a good default if VBT is badly populated */
d02ace87
VS		 902 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
903 level = default_entry;
8d8bb85e 904
d02ace87 905 if (WARN_ON_ONCE(n_entries == 0))
21b39d2a 906 return 0;
d02ace87
VS		 907 if (WARN_ON_ONCE(level >= n_entries))
908 level = n_entries - 1;
21b39d2a 909
d02ace87 910 return level;
8d8bb85e
VS		 911}
912
e58623cb
AR		 913/*
914 * Starting with Haswell, DDI port buffers must be programmed with correct
32bdc400
VS		 915 * values in advance. This function programs the correct values for
916 * DP/eDP/FDI use cases.
45244b87 917 */
3a6d84e6
VS		 918static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
919 const struct intel_crtc_state *crtc_state)
45244b87 920{
6a7e4f99 921 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 922 u32 iboost_bit = 0;
7d1c42e6 923 int i, n_entries;
0fce04c8 924 enum port port = encoder->port;
10122051 925 const struct ddi_buf_trans *ddi_translations;
e58623cb 926
3a6d84e6
VS		 927 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
928 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
929 &n_entries);
930 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
edba48fd 931 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
7d1c42e6 932 &n_entries);
3a6d84e6 933 else
edba48fd 934 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
7d1c42e6 935 &n_entries);
e58623cb 936
edba48fd
VS		 937 /* If we're boosting the current, set bit 31 of trans1 */
938 if (IS_GEN9_BC(dev_priv) &&
939 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
940 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
45244b87 941
7d1c42e6 942 for (i = 0; i < n_entries; i++) {
9712e688
VS		 943 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
944 ddi_translations[i].trans1 | iboost_bit);
945 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
946 ddi_translations[i].trans2);
45244b87 947 }
32bdc400
VS		 948}
949
950/*
951 * Starting with Haswell, DDI port buffers must be programmed with correct
952 * values in advance. This function programs the correct values for
953 * HDMI/DVI use cases.
954 */
7ea79333 955static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
d02ace87 956 int level)
32bdc400
VS		 957{
958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
959 u32 iboost_bit = 0;
d02ace87 960 int n_entries;
0fce04c8 961 enum port port = encoder->port;
d02ace87 962 const struct ddi_buf_trans *ddi_translations;
ce4dd49e 963
d02ace87 964 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1edaaa2f 965
d02ace87 966 if (WARN_ON_ONCE(!ddi_translations))
21b39d2a 967 return;
d02ace87
VS		 968 if (WARN_ON_ONCE(level >= n_entries))
969 level = n_entries - 1;
21b39d2a 970
975786ee
VS		 971 /* If we're boosting the current, set bit 31 of trans1 */
972 if (IS_GEN9_BC(dev_priv) &&
973 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
974 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
32bdc400 975
6acab15a 976 /* Entry 9 is for HDMI: */
ed9c77d2 977 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
d02ace87 978 ddi_translations[level].trans1 | iboost_bit);
ed9c77d2 979 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
d02ace87 980 ddi_translations[level].trans2);
45244b87
ED		 981}
982
248138b5
PZ		 983static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
984 enum port port)
985{
f0f59a00 986 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 987 int i;
988
3449ca85 989 for (i = 0; i < 16; i++) {
248138b5
PZ		 990 udelay(1);
991 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
992 return;
993 }
994 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
995}
c82e4d26 996
3d0c5005 997static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
c856052a 998{
0823eb9c 999 switch (pll->info->id) {
c856052a
ACO		 1000 case DPLL_ID_WRPLL1:
1001 return PORT_CLK_SEL_WRPLL1;
1002 case DPLL_ID_WRPLL2:
1003 return PORT_CLK_SEL_WRPLL2;
1004 case DPLL_ID_SPLL:
1005 return PORT_CLK_SEL_SPLL;
1006 case DPLL_ID_LCPLL_810:
1007 return PORT_CLK_SEL_LCPLL_810;
1008 case DPLL_ID_LCPLL_1350:
1009 return PORT_CLK_SEL_LCPLL_1350;
1010 case DPLL_ID_LCPLL_2700:
1011 return PORT_CLK_SEL_LCPLL_2700;
1012 default:
0823eb9c 1013 MISSING_CASE(pll->info->id);
c856052a
ACO		 1014 return PORT_CLK_SEL_NONE;
1015 }
1016}
1017
20fd2ab7 1018static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
3d0c5005 1019 const struct intel_crtc_state *crtc_state)
c27e917e 1020{
0e5fa646
ML		 1021 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1022 int clock = crtc_state->port_clock;
c27e917e
PZ		 1023 const enum intel_dpll_id id = pll->info->id;
1024
1025 switch (id) {
1026 default:
20fd2ab7
LDM		 1027 /*
1028 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1029 * here, so do warn if this get passed in
1030 */
c27e917e 1031 MISSING_CASE(id);
c27e917e 1032 return DDI_CLK_SEL_NONE;
1fa11ee2
PZ		 1033 case DPLL_ID_ICL_TBTPLL:
1034 switch (clock) {
1035 case 162000:
1036 return DDI_CLK_SEL_TBT_162;
1037 case 270000:
1038 return DDI_CLK_SEL_TBT_270;
1039 case 540000:
1040 return DDI_CLK_SEL_TBT_540;
1041 case 810000:
1042 return DDI_CLK_SEL_TBT_810;
1043 default:
1044 MISSING_CASE(clock);
7a61a6de 1045 return DDI_CLK_SEL_NONE;
1fa11ee2 1046 }
c27e917e
PZ		 1047 case DPLL_ID_ICL_MGPLL1:
1048 case DPLL_ID_ICL_MGPLL2:
1049 case DPLL_ID_ICL_MGPLL3:
1050 case DPLL_ID_ICL_MGPLL4:
1051 return DDI_CLK_SEL_MG;
1052 }
1053}
1054
c82e4d26
ED		 1055/* Starting with Haswell, different DDI ports can work in FDI mode for
1056 * connection to the PCH-located connectors. For this, it is necessary to train
1057 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1058 *
1059 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1060 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1061 * DDI A (which is used for eDP)
1062 */
1063
dc4a1094
ACO		 1064void hsw_fdi_link_train(struct intel_crtc *crtc,
1065 const struct intel_crtc_state *crtc_state)
c82e4d26 1066{
4cbe4b2b 1067 struct drm_device *dev = crtc->base.dev;
fac5e23e 1068 struct drm_i915_private *dev_priv = to_i915(dev);
6a7e4f99 1069 struct intel_encoder *encoder;
c856052a 1070 u32 temp, i, rx_ctl_val, ddi_pll_sel;
c82e4d26 1071
4cbe4b2b 1072 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6a7e4f99 1073 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
3a6d84e6 1074 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
6a7e4f99
VS		 1075 }
1076
04945641
PZ		 1077 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1078 * mode set "sequence for CRT port" document:
1079 * - TP1 to TP2 time with the default value
1080 * - FDI delay to 90h
8693a824
DL		 1081 *
1082 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 1083 */
eede3b53 1084 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 1085 FDI_RX_PWRDN_LANE0_VAL(2) |
1086 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1087
1088 /* Enable the PCH Receiver FDI PLL */
3e68320e 1089 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 1090 FDI_RX_PLL_ENABLE |
dc4a1094 1091 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
eede3b53
VS		 1092 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1093 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1094 udelay(220);
1095
1096 /* Switch from Rawclk to PCDclk */
1097 rx_ctl_val |= FDI_PCDCLK;
eede3b53 1098 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 1099
1100 /* Configure Port Clock Select */
dc4a1094 1101 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
c856052a
ACO		 1102 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1103 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 1104
1105 /* Start the training iterating through available voltages and emphasis,
1106 * testing each value twice. */
10122051 1107 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 1108 /* Configure DP_TP_CTL with auto-training */
1109 I915_WRITE(DP_TP_CTL(PORT_E),
1110 DP_TP_CTL_FDI_AUTOTRAIN |
1111 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1112 DP_TP_CTL_LINK_TRAIN_PAT1 |
1113 DP_TP_CTL_ENABLE);
1114
876a8cdf
DL		 1115 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1116 * DDI E does not support port reversal, the functionality is
1117 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1118 * port reversal bit */
c82e4d26 1119 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 1120 DDI_BUF_CTL_ENABLE |
dc4a1094 1121 ((crtc_state->fdi_lanes - 1) << 1) |
c5fe6a06 1122 DDI_BUF_TRANS_SELECT(i / 2));
04945641 1123 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 1124
1125 udelay(600);
1126
04945641 1127 /* Program PCH FDI Receiver TU */
eede3b53 1128 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 1129
1130 /* Enable PCH FDI Receiver with auto-training */
1131 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 1132 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1133 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 1134
1135 /* Wait for FDI receiver lane calibration */
1136 udelay(30);
1137
1138 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 1139 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 1140 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 1141 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1142 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1143
1144 /* Wait for FDI auto training time */
1145 udelay(5);
c82e4d26
ED		 1146
1147 temp = I915_READ(DP_TP_STATUS(PORT_E));
1148 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 1149 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 1150 break;
1151 }
c82e4d26 1152
a308ccb3
VS		 1153 /*
1154 * Leave things enabled even if we failed to train FDI.
1155 * Results in less fireworks from the state checker.
1156 */
1157 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1158 DRM_ERROR("FDI link training failed!\n");
1159 break;
c82e4d26 1160 }
04945641 1161
5b421c57
VS		 1162 rx_ctl_val &= ~FDI_RX_ENABLE;
1163 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1164 POSTING_READ(FDI_RX_CTL(PIPE_A));
1165
248138b5
PZ		 1166 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1167 temp &= ~DDI_BUF_CTL_ENABLE;
1168 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1169 POSTING_READ(DDI_BUF_CTL(PORT_E));
1170
04945641 1171 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 1172 temp = I915_READ(DP_TP_CTL(PORT_E));
1173 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1174 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1175 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1176 POSTING_READ(DP_TP_CTL(PORT_E));
1177
1178 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 1179
04945641 1180 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 1181 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 1182 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1183 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 1186 }
1187
a308ccb3
VS		 1188 /* Enable normal pixel sending for FDI */
1189 I915_WRITE(DP_TP_CTL(PORT_E),
1190 DP_TP_CTL_FDI_AUTOTRAIN |
1191 DP_TP_CTL_LINK_TRAIN_NORMAL |
1192 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1193 DP_TP_CTL_ENABLE);
c82e4d26 1194}
0e72a5b5 1195
d7c530b2 1196static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
44905a27
DA		 1197{
1198 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1199 struct intel_digital_port *intel_dig_port =
1200 enc_to_dig_port(&encoder->base);
1201
1202 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 1203 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 1204 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 1205}
1206
8d9ddbcb 1207static struct intel_encoder *
e9ce1a62 1208intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
8d9ddbcb 1209{
e9ce1a62 1210 struct drm_device *dev = crtc->base.dev;
1524e93e 1211 struct intel_encoder *encoder, *ret = NULL;
8d9ddbcb
PZ		 1212 int num_encoders = 0;
1213
1524e93e
SS		 1214 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1215 ret = encoder;
8d9ddbcb
PZ		 1216 num_encoders++;
1217 }
1218
1219 if (num_encoders != 1)
84f44ce7 1220 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
e9ce1a62 1221 pipe_name(crtc->pipe));
8d9ddbcb
PZ		 1222
1223 BUG_ON(ret == NULL);
1224 return ret;
1225}
1226
f0f59a00
VS		 1227static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1228 i915_reg_t reg)
11578553 1229{
0f52c097 1230 int refclk;
11578553
JB		 1231 int n, p, r;
1232 u32 wrpll;
1233
1234 wrpll = I915_READ(reg);
4a95e36f
VS		 1235 switch (wrpll & WRPLL_REF_MASK) {
1236 case WRPLL_REF_SPECIAL_HSW:
86761789
VS		 1237 /*
1238 * muxed-SSC for BDW.
1239 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1240 * for the non-SSC reference frequency.
1241 */
1242 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1243 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1244 refclk = 24;
1245 else
1246 refclk = 135;
1247 break;
1248 }
1249 /* fall through */
4a95e36f 1250 case WRPLL_REF_PCH_SSC:
11578553
JB		 1251 /*
1252 * We could calculate spread here, but our checking
1253 * code only cares about 5% accuracy, and spread is a max of
1254 * 0.5% downspread.
1255 */
1256 refclk = 135;
1257 break;
4a95e36f 1258 case WRPLL_REF_LCPLL:
0f52c097 1259 refclk = 2700;
11578553
JB		 1260 break;
1261 default:
86761789 1262 MISSING_CASE(wrpll);
11578553
JB		 1263 return 0;
1264 }
1265
1266 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1267 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1268 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1269
20f0ec16
JB		 1270 /* Convert to KHz, p & r have a fixed point portion */
1271 return (refclk * n * 100) / (p * r);
11578553
JB		 1272}
1273
947f4417 1274static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
540e732c 1275{
3d0c5005 1276 u32 p0, p1, p2, dco_freq;
540e732c 1277
947f4417
LDM		 1278 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1279 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
540e732c 1280
947f4417
LDM		 1281 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1282 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
540e732c
S		 1283 else
1284 p1 = 1;
1285
1286
1287 switch (p0) {
1288 case DPLL_CFGCR2_PDIV_1:
1289 p0 = 1;
1290 break;
1291 case DPLL_CFGCR2_PDIV_2:
1292 p0 = 2;
1293 break;
1294 case DPLL_CFGCR2_PDIV_3:
1295 p0 = 3;
1296 break;
1297 case DPLL_CFGCR2_PDIV_7:
1298 p0 = 7;
1299 break;
1300 }
1301
1302 switch (p2) {
1303 case DPLL_CFGCR2_KDIV_5:
1304 p2 = 5;
1305 break;
1306 case DPLL_CFGCR2_KDIV_2:
1307 p2 = 2;
1308 break;
1309 case DPLL_CFGCR2_KDIV_3:
1310 p2 = 3;
1311 break;
1312 case DPLL_CFGCR2_KDIV_1:
1313 p2 = 1;
1314 break;
1315 }
1316
947f4417
LDM		 1317 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1318 * 24 * 1000;
540e732c 1319
947f4417
LDM		 1320 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1321 * 24 * 1000) / 0x8000;
540e732c 1322
b8449c43
YX		 1323 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1324 return 0;
1325
540e732c
S		 1326 return dco_freq / (p0 * p1 * p2 * 5);
1327}
1328
8327af28 1329int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
5e65216d 1330 struct intel_dpll_hw_state *pll_state)
a9701a89 1331{
3d0c5005 1332 u32 p0, p1, p2, dco_freq, ref_clock;
a9701a89 1333
5e65216d
LDM		 1334 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1335 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
a9701a89 1336
5e65216d
LDM		 1337 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1338 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
a9701a89
RV		 1339 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1340 else
1341 p1 = 1;
1342
1343
1344 switch (p0) {
1345 case DPLL_CFGCR1_PDIV_2:
1346 p0 = 2;
1347 break;
1348 case DPLL_CFGCR1_PDIV_3:
1349 p0 = 3;
1350 break;
1351 case DPLL_CFGCR1_PDIV_5:
1352 p0 = 5;
1353 break;
1354 case DPLL_CFGCR1_PDIV_7:
1355 p0 = 7;
1356 break;
1357 }
1358
1359 switch (p2) {
1360 case DPLL_CFGCR1_KDIV_1:
1361 p2 = 1;
1362 break;
1363 case DPLL_CFGCR1_KDIV_2:
1364 p2 = 2;
1365 break;
2ee7fd1e
VS		 1366 case DPLL_CFGCR1_KDIV_3:
1367 p2 = 3;
a9701a89
RV		 1368 break;
1369 }
1370
9f9d594d 1371 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
a9701a89 1372
5e65216d
LDM		 1373 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1374 * ref_clock;
a9701a89 1375
5e65216d 1376 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
442aa277 1377 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
a9701a89 1378
0e005888
PZ		 1379 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1380 return 0;
1381
a9701a89
RV		 1382 return dco_freq / (p0 * p1 * p2 * 5);
1383}
1384
7b19f544
MN		 1385static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1386 enum port port)
1387{
1388 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1389
1390 switch (val) {
1391 case DDI_CLK_SEL_NONE:
1392 return 0;
1393 case DDI_CLK_SEL_TBT_162:
1394 return 162000;
1395 case DDI_CLK_SEL_TBT_270:
1396 return 270000;
1397 case DDI_CLK_SEL_TBT_540:
1398 return 540000;
1399 case DDI_CLK_SEL_TBT_810:
1400 return 810000;
1401 default:
1402 MISSING_CASE(val);
1403 return 0;
1404 }
1405}
1406
1407static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
02c99d26 1408 const struct intel_dpll_hw_state *pll_state)
7b19f544 1409{
02c99d26 1410 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
7b19f544
MN		 1411 u64 tmp;
1412
02c99d26 1413 ref_clock = dev_priv->cdclk.hw.ref;
7b19f544 1414
02c99d26
LDM		 1415 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1416 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1417 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1418 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1419 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
7b19f544 1420
02c99d26
LDM		 1421 switch (pll_state->mg_clktop2_hsclkctl &
1422 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
7b19f544
MN		 1423 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1424 div1 = 2;
1425 break;
1426 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1427 div1 = 3;
1428 break;
1429 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1430 div1 = 5;
1431 break;
1432 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1433 div1 = 7;
1434 break;
1435 default:
02c99d26 1436 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
7b19f544
MN		 1437 return 0;
1438 }
1439
02c99d26
LDM		 1440 div2 = (pll_state->mg_clktop2_hsclkctl &
1441 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
7b19f544 1442 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
02c99d26 1443
7b19f544
MN		 1444 /* div2 value of 0 is same as 1 means no div */
1445 if (div2 == 0)
1446 div2 = 1;
1447
1448 /*
1449 * Adjust the original formula to delay the division by 2^22 in order to
1450 * minimize possible rounding errors.
1451 */
02c99d26
LDM		 1452 tmp = (u64)m1 * m2_int * ref_clock +
1453 (((u64)m1 * m2_frac * ref_clock) >> 22);
7b19f544
MN		 1454 tmp = div_u64(tmp, 5 * div1 * div2);
1455
1456 return tmp;
1457}
1458
398a017e
VS		 1459static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1460{
1461 int dotclock;
1462
1463 if (pipe_config->has_pch_encoder)
1464 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1465 &pipe_config->fdi_m_n);
37a5650b 1466 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 1467 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1468 &pipe_config->dp_m_n);
1469 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1470 dotclock = pipe_config->port_clock * 2 / 3;
1471 else
1472 dotclock = pipe_config->port_clock;
1473
16668f48
GM		 1474 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1475 !intel_crtc_has_dp_encoder(pipe_config))
b22ca995
SS		 1476 dotclock *= 2;
1477
398a017e
VS		 1478 if (pipe_config->pixel_multiplier)
1479 dotclock /= pipe_config->pixel_multiplier;
1480
1481 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1482}
540e732c 1483
51c83cfa
MN		 1484static void icl_ddi_clock_get(struct intel_encoder *encoder,
1485 struct intel_crtc_state *pipe_config)
1486{
1487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d 1488 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
51c83cfa 1489 enum port port = encoder->port;
5e65216d 1490 int link_clock;
51c83cfa 1491
176597a1 1492 if (intel_port_is_combophy(dev_priv, port)) {
5e65216d 1493 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
51c83cfa 1494 } else {
077973c8
LDM		 1495 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1496 pipe_config->shared_dpll);
1497
7b19f544
MN		 1498 if (pll_id == DPLL_ID_ICL_TBTPLL)
1499 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1500 else
02c99d26 1501 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
51c83cfa
MN		 1502 }
1503
1504 pipe_config->port_clock = link_clock;
02c99d26 1505
51c83cfa
MN		 1506 ddi_dotclock_get(pipe_config);
1507}
1508
a9701a89
RV		 1509static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1510 struct intel_crtc_state *pipe_config)
1511{
1512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5e65216d
LDM		 1513 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1514 int link_clock;
a9701a89 1515
5e65216d
LDM		 1516 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1517 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
a9701a89 1518 } else {
5e65216d 1519 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
a9701a89
RV		 1520
1521 switch (link_clock) {
1522 case DPLL_CFGCR0_LINK_RATE_810:
1523 link_clock = 81000;
1524 break;
1525 case DPLL_CFGCR0_LINK_RATE_1080:
1526 link_clock = 108000;
1527 break;
1528 case DPLL_CFGCR0_LINK_RATE_1350:
1529 link_clock = 135000;
1530 break;
1531 case DPLL_CFGCR0_LINK_RATE_1620:
1532 link_clock = 162000;
1533 break;
1534 case DPLL_CFGCR0_LINK_RATE_2160:
1535 link_clock = 216000;
1536 break;
1537 case DPLL_CFGCR0_LINK_RATE_2700:
1538 link_clock = 270000;
1539 break;
1540 case DPLL_CFGCR0_LINK_RATE_3240:
1541 link_clock = 324000;
1542 break;
1543 case DPLL_CFGCR0_LINK_RATE_4050:
1544 link_clock = 405000;
1545 break;
1546 default:
1547 WARN(1, "Unsupported link rate\n");
1548 break;
1549 }
1550 link_clock *= 2;
1551 }
1552
1553 pipe_config->port_clock = link_clock;
1554
1555 ddi_dotclock_get(pipe_config);
1556}
1557
540e732c 1558static void skl_ddi_clock_get(struct intel_encoder *encoder,
947f4417 1559 struct intel_crtc_state *pipe_config)
540e732c 1560{
947f4417
LDM		 1561 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1562 int link_clock;
540e732c 1563
947f4417
LDM		 1564 /*
1565 * ctrl1 register is already shifted for each pll, just use 0 to get
1566 * the internal shift for each field
1567 */
1568 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1569 link_clock = skl_calc_wrpll_link(pll_state);
540e732c 1570 } else {
947f4417
LDM		 1571 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1572 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
540e732c
S		 1573
1574 switch (link_clock) {
71cd8423 1575 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1576 link_clock = 81000;
1577 break;
71cd8423 1578 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1579 link_clock = 108000;
1580 break;
71cd8423 1581 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1582 link_clock = 135000;
1583 break;
71cd8423 1584 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1585 link_clock = 162000;
1586 break;
71cd8423 1587 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1588 link_clock = 216000;
1589 break;
71cd8423 1590 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1591 link_clock = 270000;
1592 break;
1593 default:
1594 WARN(1, "Unsupported link rate\n");
1595 break;
1596 }
1597 link_clock *= 2;
1598 }
1599
1600 pipe_config->port_clock = link_clock;
1601
398a017e 1602 ddi_dotclock_get(pipe_config);
540e732c
S		 1603}
1604
3d51278a 1605static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1606 struct intel_crtc_state *pipe_config)
11578553 1607{
fac5e23e 1608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 1609 int link_clock = 0;
1610 u32 val, pll;
1611
c856052a 1612 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
11578553
JB		 1613 switch (val & PORT_CLK_SEL_MASK) {
1614 case PORT_CLK_SEL_LCPLL_810:
1615 link_clock = 81000;
1616 break;
1617 case PORT_CLK_SEL_LCPLL_1350:
1618 link_clock = 135000;
1619 break;
1620 case PORT_CLK_SEL_LCPLL_2700:
1621 link_clock = 270000;
1622 break;
1623 case PORT_CLK_SEL_WRPLL1:
01403de3 1624 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1625 break;
1626 case PORT_CLK_SEL_WRPLL2:
01403de3 1627 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1628 break;
1629 case PORT_CLK_SEL_SPLL:
4a95e36f
VS		 1630 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1631 if (pll == SPLL_FREQ_810MHz)
11578553 1632 link_clock = 81000;
4a95e36f 1633 else if (pll == SPLL_FREQ_1350MHz)
11578553 1634 link_clock = 135000;
4a95e36f 1635 else if (pll == SPLL_FREQ_2700MHz)
11578553
JB		 1636 link_clock = 270000;
1637 else {
1638 WARN(1, "bad spll freq\n");
1639 return;
1640 }
1641 break;
1642 default:
1643 WARN(1, "bad port clock sel\n");
1644 return;
1645 }
1646
1647 pipe_config->port_clock = link_clock * 2;
1648
398a017e 1649 ddi_dotclock_get(pipe_config);
11578553
JB		 1650}
1651
47c9877e 1652static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
977bb38d 1653{
9e2c8475 1654 struct dpll clock;
aa610dcb 1655
aa610dcb 1656 clock.m1 = 2;
47c9877e
LDM		 1657 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1658 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1659 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1660 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1661 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1662 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
aa610dcb
ID		 1663
1664 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1665}
1666
1667static void bxt_ddi_clock_get(struct intel_encoder *encoder,
bb911536 1668 struct intel_crtc_state *pipe_config)
977bb38d 1669{
47c9877e
LDM		 1670 pipe_config->port_clock =
1671 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
977bb38d 1672
398a017e 1673 ddi_dotclock_get(pipe_config);
977bb38d
S		 1674}
1675
35686a44
VS		 1676static void intel_ddi_clock_get(struct intel_encoder *encoder,
1677 struct intel_crtc_state *pipe_config)
3d51278a 1678{
0853723b 1679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22606a18 1680
2dd24a9c 1681 if (INTEL_GEN(dev_priv) >= 11)
fdec4df4 1682 icl_ddi_clock_get(encoder, pipe_config);
a9701a89
RV		 1683 else if (IS_CANNONLAKE(dev_priv))
1684 cnl_ddi_clock_get(encoder, pipe_config);
fdec4df4
RV		 1685 else if (IS_GEN9_LP(dev_priv))
1686 bxt_ddi_clock_get(encoder, pipe_config);
1687 else if (IS_GEN9_BC(dev_priv))
1688 skl_ddi_clock_get(encoder, pipe_config);
1689 else if (INTEL_GEN(dev_priv) <= 8)
1690 hsw_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1691}
1692
3dc38eea 1693void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
dae84799 1694{
3dc38eea 1695 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1696 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1697 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5448f53f 1698 u32 temp;
dae84799 1699
5448f53f
VS		 1700 if (!intel_crtc_has_dp_encoder(crtc_state))
1701 return;
4d1de975 1702
5448f53f
VS		 1703 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1704
1705 temp = TRANS_MSA_SYNC_CLK;
dc5977da
JN		 1706
1707 if (crtc_state->limited_color_range)
1708 temp |= TRANS_MSA_CEA_RANGE;
1709
5448f53f
VS		 1710 switch (crtc_state->pipe_bpp) {
1711 case 18:
1712 temp |= TRANS_MSA_6_BPC;
1713 break;
1714 case 24:
1715 temp |= TRANS_MSA_8_BPC;
1716 break;
1717 case 30:
1718 temp |= TRANS_MSA_10_BPC;
1719 break;
1720 case 36:
1721 temp |= TRANS_MSA_12_BPC;
1722 break;
1723 default:
1724 MISSING_CASE(crtc_state->pipe_bpp);
1725 break;
dae84799 1726 }
5448f53f 1727
668b6c17
SS		 1728 /*
1729 * As per DP 1.2 spec section 2.3.4.3 while sending
1730 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1731 * colorspace information. The output colorspace encoding is BT601.
1732 */
1733 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1734 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
ec4401d3
GM		 1735 /*
1736 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1737 * of Color Encoding Format and Content Color Gamut] while sending
1738 * YCBCR 420 signals we should program MSA MISC1 fields which
1739 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1740 */
1741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1742 temp |= TRANS_MSA_USE_VSC_SDP;
5448f53f 1743 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1744}
1745
3dc38eea
ACO		 1746void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1747 bool state)
0e32b39c 1748{
3dc38eea 1749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 1750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3dc38eea 1751 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3d0c5005 1752 u32 temp;
7e732cac 1753
0e32b39c
DA		 1754 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1755 if (state == true)
1756 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1757 else
1758 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1759 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1760}
1761
3dc38eea 1762void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1763{
3dc38eea 1764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524e93e 1765 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
e9ce1a62
ACO		 1766 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1767 enum pipe pipe = crtc->pipe;
3dc38eea 1768 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
0fce04c8 1769 enum port port = encoder->port;
3d0c5005 1770 u32 temp;
8d9ddbcb 1771
ad80a810
PZ		 1772 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1773 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1774 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1775
3dc38eea 1776 switch (crtc_state->pipe_bpp) {
dfcef252 1777 case 18:
ad80a810 1778 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1779 break;
1780 case 24:
ad80a810 1781 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1782 break;
1783 case 30:
ad80a810 1784 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1785 break;
1786 case 36:
ad80a810 1787 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1788 break;
1789 default:
4e53c2e0 1790 BUG();
dfcef252 1791 }
72662e10 1792
3dc38eea 1793 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1794 temp |= TRANS_DDI_PVSYNC;
3dc38eea 1795 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1796 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1797
e6f0bfc4
PZ		 1798 if (cpu_transcoder == TRANSCODER_EDP) {
1799 switch (pipe) {
1800 case PIPE_A:
c7670b10
PZ		 1801 /* On Haswell, can only use the always-on power well for
1802 * eDP when not using the panel fitter, and when not
1803 * using motion blur mitigation (which we don't
1804 * support). */
dc0c0bfe 1805 if (crtc_state->pch_pfit.force_thru)
d6dd9eb1
DV		 1806 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1807 else
1808 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1809 break;
1810 case PIPE_B:
1811 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1812 break;
1813 case PIPE_C:
1814 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1815 break;
1816 default:
1817 BUG();
1818 break;
1819 }
1820 }
1821
742745f1 1822 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3dc38eea 1823 if (crtc_state->has_hdmi_sink)
ad80a810 1824 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1825 else
ad80a810 1826 temp |= TRANS_DDI_MODE_SELECT_DVI;
15953637
SS		 1827
1828 if (crtc_state->hdmi_scrambling)
ab2cb2cb 1829 temp |= TRANS_DDI_HDMI_SCRAMBLING;
15953637
SS		 1830 if (crtc_state->hdmi_high_tmds_clock_ratio)
1831 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
742745f1 1832 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
ad80a810 1833 temp |= TRANS_DDI_MODE_SELECT_FDI;
3dc38eea 1834 temp |= (crtc_state->fdi_lanes - 1) << 1;
742745f1 1835 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
64ee2fd2 1836 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
3dc38eea 1837 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb 1838 } else {
742745f1
VS		 1839 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1840 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
8d9ddbcb
PZ		 1841 }
1842
ad80a810 1843 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1844}
72662e10 1845
90c3e219 1846void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
8d9ddbcb 1847{
90c3e219
CT		 1848 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 1851 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
3d0c5005 1852 u32 val = I915_READ(reg);
8d9ddbcb 1853
0e32b39c 1854 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1855 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1856 I915_WRITE(reg, val);
90c3e219
CT		 1857
1858 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1859 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1860 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1861 /* Quirk time at 100ms for reliable operation */
1862 msleep(100);
1863 }
72662e10
ED		 1864}
1865
2320175f
SP		 1866int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1867 bool enable)
1868{
1869 struct drm_device *dev = intel_encoder->base.dev;
1870 struct drm_i915_private *dev_priv = to_i915(dev);
0e6e0be4 1871 intel_wakeref_t wakeref;
2320175f
SP		 1872 enum pipe pipe = 0;
1873 int ret = 0;
3d0c5005 1874 u32 tmp;
2320175f 1875
0e6e0be4
CW		 1876 wakeref = intel_display_power_get_if_enabled(dev_priv,
1877 intel_encoder->power_domain);
1878 if (WARN_ON(!wakeref))
2320175f
SP		 1879 return -ENXIO;
1880
1881 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1882 ret = -EIO;
1883 goto out;
1884 }
1885
1886 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1887 if (enable)
1888 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1889 else
1890 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1891 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1892out:
0e6e0be4 1893 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2320175f
SP		 1894 return ret;
1895}
1896
bcbc889b
PZ		 1897bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1898{
1899 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1900 struct drm_i915_private *dev_priv = to_i915(dev);
1524e93e 1901 struct intel_encoder *encoder = intel_connector->encoder;
bcbc889b 1902 int type = intel_connector->base.connector_type;
0fce04c8 1903 enum port port = encoder->port;
bcbc889b 1904 enum transcoder cpu_transcoder;
0e6e0be4
CW		 1905 intel_wakeref_t wakeref;
1906 enum pipe pipe = 0;
3d0c5005 1907 u32 tmp;
e27daab4 1908 bool ret;
bcbc889b 1909
0e6e0be4
CW		 1910 wakeref = intel_display_power_get_if_enabled(dev_priv,
1911 encoder->power_domain);
1912 if (!wakeref)
882244a3
PZ		 1913 return false;
1914
1524e93e 1915 if (!encoder->get_hw_state(encoder, &pipe)) {
e27daab4
ID		 1916 ret = false;
1917 goto out;
1918 }
bcbc889b 1919
bc7e3525 1920 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
bcbc889b
PZ		 1921 cpu_transcoder = TRANSCODER_EDP;
1922 else
1a240d4d 1923 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1924
1925 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1926
1927 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1928 case TRANS_DDI_MODE_SELECT_HDMI:
1929 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1930 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1931 break;
bcbc889b
PZ		 1932
1933 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1934 ret = type == DRM_MODE_CONNECTOR_eDP ||
1935 type == DRM_MODE_CONNECTOR_DisplayPort;
1936 break;
1937
0e32b39c
DA		 1938 case TRANS_DDI_MODE_SELECT_DP_MST:
1939 /* if the transcoder is in MST state then
1940 * connector isn't connected */
e27daab4
ID		 1941 ret = false;
1942 break;
bcbc889b
PZ		 1943
1944 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1945 ret = type == DRM_MODE_CONNECTOR_VGA;
1946 break;
bcbc889b
PZ		 1947
1948 default:
e27daab4
ID		 1949 ret = false;
1950 break;
bcbc889b 1951 }
e27daab4
ID		 1952
1953out:
0e6e0be4 1954 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
e27daab4
ID		 1955
1956 return ret;
bcbc889b
PZ		 1957}
1958
9199c322
ID		 1959static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1960 u8 *pipe_mask, bool *is_dp_mst)
85234cdc
DV		 1961{
1962 struct drm_device *dev = encoder->base.dev;
fac5e23e 1963 struct drm_i915_private *dev_priv = to_i915(dev);
0fce04c8 1964 enum port port = encoder->port;
0e6e0be4 1965 intel_wakeref_t wakeref;
3657e927 1966 enum pipe p;
85234cdc 1967 u32 tmp;
9199c322
ID		 1968 u8 mst_pipe_mask;
1969
1970 *pipe_mask = 0;
1971 *is_dp_mst = false;
85234cdc 1972
0e6e0be4
CW		 1973 wakeref = intel_display_power_get_if_enabled(dev_priv,
1974 encoder->power_domain);
1975 if (!wakeref)
9199c322 1976 return;
e27daab4 1977
fe43d3f5 1978 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc 1979 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1980 goto out;
85234cdc 1981
bc7e3525 1982 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
ad80a810 1983 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1984
ad80a810 1985 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199c322
ID		 1986 default:
1987 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1988 /* fallthrough */
ad80a810
PZ		 1989 case TRANS_DDI_EDP_INPUT_A_ON:
1990 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9199c322 1991 *pipe_mask = BIT(PIPE_A);
ad80a810
PZ		 1992 break;
1993 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9199c322 1994 *pipe_mask = BIT(PIPE_B);
ad80a810
PZ		 1995 break;
1996 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9199c322 1997 *pipe_mask = BIT(PIPE_C);
ad80a810
PZ		 1998 break;
1999 }
2000
e27daab4
ID		 2001 goto out;
2002 }
0e32b39c 2003
9199c322 2004 mst_pipe_mask = 0;
3657e927 2005 for_each_pipe(dev_priv, p) {
9199c322 2006 enum transcoder cpu_transcoder = (enum transcoder)p;
3657e927
MK		 2007
2008 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
e27daab4 2009
9199c322
ID		 2010 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2011 continue;
e27daab4 2012
9199c322
ID		 2013 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2014 TRANS_DDI_MODE_SELECT_DP_MST)
2015 mst_pipe_mask |= BIT(p);
e27daab4 2016
9199c322 2017 *pipe_mask |= BIT(p);
85234cdc
DV		 2018 }
2019
9199c322
ID		 2020 if (!*pipe_mask)
2021 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2022 port_name(port));
2023
2024 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2025 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2026 port_name(port), *pipe_mask);
2027 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2028 }
2029
2030 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2031 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2032 port_name(port), *pipe_mask, mst_pipe_mask);
2033 else
2034 *is_dp_mst = mst_pipe_mask;
85234cdc 2035
e27daab4 2036out:
9199c322 2037 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
e93da0a0 2038 tmp = I915_READ(BXT_PHY_CTL(port));
e19c1eb8
ID		 2039 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2040 BXT_PHY_LANE_POWERDOWN_ACK |
e93da0a0
ID		 2041 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2042 DRM_ERROR("Port %c enabled but PHY powered down? "
2043 "(PHY_CTL %08x)\n", port_name(port), tmp);
2044 }
2045
0e6e0be4 2046 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
9199c322 2047}
e27daab4 2048
9199c322
ID		 2049bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2050 enum pipe *pipe)
2051{
2052 u8 pipe_mask;
2053 bool is_mst;
2054
2055 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2056
2057 if (is_mst || !pipe_mask)
2058 return false;
2059
2060 *pipe = ffs(pipe_mask) - 1;
2061
2062 return true;
85234cdc
DV		 2063}
2064
52528055 2065static inline enum intel_display_power_domain
bdaa29b6 2066intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
52528055 2067{
9e3b5ce9 2068 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
52528055
ID		 2069 * DC states enabled at the same time, while for driver initiated AUX
2070 * transfers we need the same AUX IOs to be powered but with DC states
2071 * disabled. Accordingly use the AUX power domain here which leaves DC
2072 * states enabled.
2073 * However, for non-A AUX ports the corresponding non-EDP transcoders
2074 * would have already enabled power well 2 and DC_OFF. This means we can
2075 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2076 * specific AUX_IO reference without powering up any extra wells.
2077 * Note that PSR is enabled only on Port A even though this function
2078 * returns the correct domain for other ports too.
2079 */
563d22a0 2080 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
337837ac 2081 intel_aux_power_domain(dig_port);
52528055
ID		 2082}
2083
3a52fb7e
ID		 2084static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2085 struct intel_crtc_state *crtc_state)
62b69566 2086{
8e4a3ad9 2087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b79ebe74 2088 struct intel_digital_port *dig_port;
62b69566 2089
52528055
ID		 2090 /*
2091 * TODO: Add support for MST encoders. Atm, the following should never
b79ebe74
ID		 2092 * happen since fake-MST encoders don't set their get_power_domains()
2093 * hook.
52528055
ID		 2094 */
2095 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
3a52fb7e 2096 return;
b79ebe74
ID		 2097
2098 dig_port = enc_to_dig_port(&encoder->base);
3a52fb7e 2099 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
52528055 2100
8e4a3ad9
ID		 2101 /*
2102 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2103 * ports.
2104 */
2105 if (intel_crtc_has_dp_encoder(crtc_state) ||
2106 intel_port_is_tc(dev_priv, encoder->port))
3a52fb7e
ID		 2107 intel_display_power_get(dev_priv,
2108 intel_ddi_main_link_aux_domain(dig_port));
52528055 2109
a24c62f9
MN		 2110 /*
2111 * VDSC power is needed when DSC is enabled
2112 */
2113 if (crtc_state->dsc_params.compression_enable)
3a52fb7e
ID		 2114 intel_display_power_get(dev_priv,
2115 intel_dsc_power_domain(crtc_state));
62b69566
ACO		 2116}
2117
3dc38eea 2118void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2119{
3dc38eea 2120 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
e9ce1a62 2121 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524e93e 2122 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
0fce04c8 2123 enum port port = encoder->port;
3dc38eea 2124 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2125
bb523fc0
PZ		 2126 if (cpu_transcoder != TRANSCODER_EDP)
2127 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2128 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2129}
2130
3dc38eea 2131void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
fc914639 2132{
3dc38eea
ACO		 2133 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2134 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
fc914639 2135
bb523fc0
PZ		 2136 if (cpu_transcoder != TRANSCODER_EDP)
2137 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2138 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2139}
2140
a7d8dbc0 2141static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
3d0c5005 2142 enum port port, u8 iboost)
f8896f5d 2143{
a7d8dbc0
VS		 2144 u32 tmp;
2145
2146 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2147 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2148 if (iboost)
2149 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2150 else
2151 tmp |= BALANCE_LEG_DISABLE(port);
2152 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2153}
2154
081dfcfa
VS		 2155static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2156 int level, enum intel_output_type type)
a7d8dbc0
VS		 2157{
2158 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
8f4f2797
VS		 2159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2160 enum port port = encoder->port;
3d0c5005 2161 u8 iboost;
f8896f5d 2162
081dfcfa
VS		 2163 if (type == INTEL_OUTPUT_HDMI)
2164 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2165 else
2166 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
75067dde 2167
081dfcfa
VS		 2168 if (iboost == 0) {
2169 const struct ddi_buf_trans *ddi_translations;
2170 int n_entries;
2171
2172 if (type == INTEL_OUTPUT_HDMI)
2173 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2174 else if (type == INTEL_OUTPUT_EDP)
edba48fd 2175 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
081dfcfa 2176 else
edba48fd 2177 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
10afa0b6 2178
21b39d2a
VS		 2179 if (WARN_ON_ONCE(!ddi_translations))
2180 return;
2181 if (WARN_ON_ONCE(level >= n_entries))
2182 level = n_entries - 1;
2183
081dfcfa 2184 iboost = ddi_translations[level].i_boost;
f8896f5d
DW		 2185 }
2186
2187 /* Make sure that the requested I_boost is valid */
2188 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2189 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2190 return;
2191 }
2192
a7d8dbc0 2193 _skl_ddi_set_iboost(dev_priv, port, iboost);
f8896f5d 2194
a7d8dbc0
VS		 2195 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2196 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
f8896f5d
DW		 2197}
2198
7d4f37b5
VS		 2199static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2200 int level, enum intel_output_type type)
96fb9f9b 2201{
7d4f37b5 2202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96fb9f9b 2203 const struct bxt_ddi_buf_trans *ddi_translations;
7d4f37b5 2204 enum port port = encoder->port;
043eaf36 2205 int n_entries;
7d4f37b5
VS		 2206
2207 if (type == INTEL_OUTPUT_HDMI)
2208 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2209 else if (type == INTEL_OUTPUT_EDP)
2210 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2211 else
2212 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
96fb9f9b 2213
21b39d2a
VS		 2214 if (WARN_ON_ONCE(!ddi_translations))
2215 return;
2216 if (WARN_ON_ONCE(level >= n_entries))
2217 level = n_entries - 1;
2218
b6e08203
ACO		 2219 bxt_ddi_phy_set_signal_level(dev_priv, port,
2220 ddi_translations[level].margin,
2221 ddi_translations[level].scale,
2222 ddi_translations[level].enable,
2223 ddi_translations[level].deemphasis);
96fb9f9b
VK		 2224}
2225
ffe5111e
VS		 2226u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2227{
2228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b265a2a6 2229 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
edba48fd 2230 enum port port = encoder->port;
ffe5111e
VS		 2231 int n_entries;
2232
2dd24a9c 2233 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2234 if (intel_port_is_combophy(dev_priv, port))
36cf89f5 2235 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
b265a2a6 2236 intel_dp->link_rate, &n_entries);
36cf89f5
MN		 2237 else
2238 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2239 } else if (IS_CANNONLAKE(dev_priv)) {
5fcf34b1
RV		 2240 if (encoder->type == INTEL_OUTPUT_EDP)
2241 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2242 else
2243 cnl_get_buf_trans_dp(dev_priv, &n_entries);
7d4f37b5
VS		 2244 } else if (IS_GEN9_LP(dev_priv)) {
2245 if (encoder->type == INTEL_OUTPUT_EDP)
2246 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2247 else
2248 bxt_get_buf_trans_dp(dev_priv, &n_entries);
5fcf34b1
RV		 2249 } else {
2250 if (encoder->type == INTEL_OUTPUT_EDP)
edba48fd 2251 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
5fcf34b1 2252 else
edba48fd 2253 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
5fcf34b1 2254 }
ffe5111e
VS		 2255
2256 if (WARN_ON(n_entries < 1))
2257 n_entries = 1;
2258 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2259 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2260
2261 return index_to_dp_signal_levels[n_entries - 1] &
2262 DP_TRAIN_VOLTAGE_SWING_MASK;
2263}
2264
4718a365
VS		 2265/*
2266 * We assume that the full set of pre-emphasis values can be
2267 * used on all DDI platforms. Should that change we need to
2268 * rethink this code.
2269 */
2270u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2271{
2272 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2274 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2276 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2278 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2280 default:
2281 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2282 }
2283}
2284
f3cf4ba4
VS		 2285static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2286 int level, enum intel_output_type type)
cf54ca8b 2287{
f3cf4ba4 2288 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f3cf4ba4 2289 const struct cnl_ddi_buf_trans *ddi_translations;
0fce04c8 2290 enum port port = encoder->port;
f3cf4ba4
VS		 2291 int n_entries, ln;
2292 u32 val;
cf54ca8b 2293
f3cf4ba4 2294 if (type == INTEL_OUTPUT_HDMI)
cc9cabfd 2295 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
f3cf4ba4 2296 else if (type == INTEL_OUTPUT_EDP)
cc9cabfd 2297 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
f3cf4ba4
VS		 2298 else
2299 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
cf54ca8b 2300
21b39d2a 2301 if (WARN_ON_ONCE(!ddi_translations))
cf54ca8b 2302 return;
21b39d2a 2303 if (WARN_ON_ONCE(level >= n_entries))
cf54ca8b 2304 level = n_entries - 1;
cf54ca8b
RV		 2305
2306 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2307 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2308 val &= ~SCALING_MODE_SEL_MASK;
cf54ca8b
RV		 2309 val |= SCALING_MODE_SEL(2);
2310 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2311
2312 /* Program PORT_TX_DW2 */
2313 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1f588aeb
RV		 2314 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2315 RCOMP_SCALAR_MASK);
cf54ca8b
RV		 2316 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2317 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2318 /* Rcomp scalar is fixed as 0x98 for every table entry */
2319 val |= RCOMP_SCALAR(0x98);
2320 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2321
20303eb4 2322 /* Program PORT_TX_DW4 */
cf54ca8b
RV		 2323 /* We cannot write to GRP. It would overrite individual loadgen */
2324 for (ln = 0; ln < 4; ln++) {
9194e42a 2325 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
1f588aeb
RV		 2326 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2327 CURSOR_COEFF_MASK);
cf54ca8b
RV		 2328 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2329 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2330 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2331 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
cf54ca8b
RV		 2332 }
2333
20303eb4 2334 /* Program PORT_TX_DW5 */
cf54ca8b
RV		 2335 /* All DW5 values are fixed for every table entry */
2336 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1f588aeb 2337 val &= ~RTERM_SELECT_MASK;
cf54ca8b
RV		 2338 val |= RTERM_SELECT(6);
2339 val |= TAP3_DISABLE;
2340 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2341
20303eb4 2342 /* Program PORT_TX_DW7 */
cf54ca8b 2343 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1f588aeb 2344 val &= ~N_SCALAR_MASK;
cf54ca8b
RV		 2345 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2346 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2347}
2348
f3cf4ba4
VS		 2349static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2350 int level, enum intel_output_type type)
cf54ca8b 2351{
0091abc3 2352 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2353 enum port port = encoder->port;
f3cf4ba4 2354 int width, rate, ln;
cf54ca8b 2355 u32 val;
0091abc3 2356
f3cf4ba4 2357 if (type == INTEL_OUTPUT_HDMI) {
0091abc3 2358 width = 4;
f3cf4ba4 2359 rate = 0; /* Rate is always < than 6GHz for HDMI */
61f3e770 2360 } else {
f3cf4ba4
VS		 2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2362
2363 width = intel_dp->lane_count;
2364 rate = intel_dp->link_rate;
0091abc3 2365 }
cf54ca8b
RV		 2366
2367 /*
2368 * 1. If port type is eDP or DP,
2369 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2370 * else clear to 0b.
2371 */
2372 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
f3cf4ba4 2373 if (type != INTEL_OUTPUT_HDMI)
cf54ca8b
RV		 2374 val |= COMMON_KEEPER_EN;
2375 else
2376 val &= ~COMMON_KEEPER_EN;
2377 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2378
2379 /* 2. Program loadgen select */
2380 /*
0091abc3
CT		 2381 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2382 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2383 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2384 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
cf54ca8b 2385 */
0091abc3 2386 for (ln = 0; ln <= 3; ln++) {
9194e42a 2387 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
0091abc3
CT		 2388 val &= ~LOADGEN_SELECT;
2389
a8e45a1c
NM		 2390 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2391 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
0091abc3
CT		 2392 val |= LOADGEN_SELECT;
2393 }
9194e42a 2394 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
0091abc3 2395 }
cf54ca8b
RV		 2396
2397 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2398 val = I915_READ(CNL_PORT_CL1CM_DW5);
2399 val |= SUS_CLOCK_CONFIG;
2400 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2401
2402 /* 4. Clear training enable to change swing values */
2403 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2404 val &= ~TX_TRAINING_EN;
2405 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2406
2407 /* 5. Program swing and de-emphasis */
f3cf4ba4 2408 cnl_ddi_vswing_program(encoder, level, type);
cf54ca8b
RV		 2409
2410 /* 6. Set training enable to trigger update */
2411 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2412 val |= TX_TRAINING_EN;
2413 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2414}
2415
fb5c8e9d 2416static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
b265a2a6
CT		 2417 u32 level, enum port port, int type,
2418 int rate)
fb5c8e9d 2419{
b265a2a6 2420 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
fb5c8e9d
MN		 2421 u32 n_entries, val;
2422 int ln;
2423
2424 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
b265a2a6 2425 rate, &n_entries);
fb5c8e9d
MN		 2426 if (!ddi_translations)
2427 return;
2428
2429 if (level >= n_entries) {
2430 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2431 level = n_entries - 1;
2432 }
2433
b265a2a6 2434 /* Set PORT_TX_DW5 */
fb5c8e9d 2435 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
b265a2a6
CT		 2436 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2437 TAP2_DISABLE | TAP3_DISABLE);
2438 val |= SCALING_MODE_SEL(0x2);
fb5c8e9d 2439 val |= RTERM_SELECT(0x6);
b265a2a6 2440 val |= TAP3_DISABLE;
fb5c8e9d
MN		 2441 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2442
2443 /* Program PORT_TX_DW2 */
2444 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2445 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2446 RCOMP_SCALAR_MASK);
b265a2a6
CT		 2447 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2448 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
fb5c8e9d 2449 /* Program Rcomp scalar for every table entry */
b265a2a6 2450 val |= RCOMP_SCALAR(0x98);
fb5c8e9d
MN		 2451 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2452
2453 /* Program PORT_TX_DW4 */
2454 /* We cannot write to GRP. It would overwrite individual loadgen. */
2455 for (ln = 0; ln <= 3; ln++) {
9194e42a 2456 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2457 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2458 CURSOR_COEFF_MASK);
b265a2a6
CT		 2459 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2460 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2461 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
9194e42a 2462 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d 2463 }
b265a2a6
CT		 2464
2465 /* Program PORT_TX_DW7 */
2466 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2467 val &= ~N_SCALAR_MASK;
2468 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2469 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
fb5c8e9d
MN		 2470}
2471
2472static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2473 u32 level,
2474 enum intel_output_type type)
2475{
2476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2477 enum port port = encoder->port;
2478 int width = 0;
2479 int rate = 0;
2480 u32 val;
2481 int ln = 0;
2482
2483 if (type == INTEL_OUTPUT_HDMI) {
2484 width = 4;
2485 /* Rate is always < than 6GHz for HDMI */
2486 } else {
2487 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2488
2489 width = intel_dp->lane_count;
2490 rate = intel_dp->link_rate;
2491 }
2492
2493 /*
2494 * 1. If port type is eDP or DP,
2495 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2496 * else clear to 0b.
2497 */
2498 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2499 if (type == INTEL_OUTPUT_HDMI)
2500 val &= ~COMMON_KEEPER_EN;
2501 else
2502 val |= COMMON_KEEPER_EN;
2503 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2504
2505 /* 2. Program loadgen select */
2506 /*
2507 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2508 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2509 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2510 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2511 */
2512 for (ln = 0; ln <= 3; ln++) {
9194e42a 2513 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
fb5c8e9d
MN		 2514 val &= ~LOADGEN_SELECT;
2515
2516 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2517 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2518 val |= LOADGEN_SELECT;
2519 }
9194e42a 2520 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
fb5c8e9d
MN		 2521 }
2522
2523 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2524 val = I915_READ(ICL_PORT_CL_DW5(port));
2525 val |= SUS_CLOCK_CONFIG;
2526 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2527
2528 /* 4. Clear training enable to change swing values */
2529 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2530 val &= ~TX_TRAINING_EN;
2531 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2532
2533 /* 5. Program swing and de-emphasis */
b265a2a6 2534 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
fb5c8e9d
MN		 2535
2536 /* 6. Set training enable to trigger update */
2537 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2538 val |= TX_TRAINING_EN;
2539 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2540}
2541
07685c82
MN		 2542static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2543 int link_clock,
2544 u32 level)
2545{
2546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2547 enum port port = encoder->port;
2548 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2549 u32 n_entries, val;
2550 int ln;
2551
2552 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2553 ddi_translations = icl_mg_phy_ddi_translations;
2554 /* The table does not have values for level 3 and level 9. */
2555 if (level >= n_entries || level == 3 || level == 9) {
2556 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2557 level, n_entries - 2);
2558 level = n_entries - 2;
2559 }
2560
2561 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2562 for (ln = 0; ln < 2; ln++) {
58106b7d 2563 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
07685c82 2564 val &= ~CRI_USE_FS32;
58106b7d 2565 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
07685c82 2566
58106b7d 2567 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
07685c82 2568 val &= ~CRI_USE_FS32;
58106b7d 2569 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
07685c82
MN		 2570 }
2571
2572 /* Program MG_TX_SWINGCTRL with values from vswing table */
2573 for (ln = 0; ln < 2; ln++) {
58106b7d 2574 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
07685c82
MN		 2575 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2576 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2577 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2578 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
07685c82 2579
58106b7d 2580 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
07685c82
MN		 2581 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583 ddi_translations[level].cri_txdeemph_override_17_12);
58106b7d 2584 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
07685c82
MN		 2585 }
2586
2587 /* Program MG_TX_DRVCTRL with values from vswing table */
2588 for (ln = 0; ln < 2; ln++) {
58106b7d 2589 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
07685c82
MN		 2590 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2591 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2592 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2593 ddi_translations[level].cri_txdeemph_override_5_0) |
2594 CRI_TXDEEMPH_OVERRIDE_11_6(
2595 ddi_translations[level].cri_txdeemph_override_11_6) |
2596 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2597 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
07685c82 2598
58106b7d 2599 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
07685c82
MN		 2600 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2601 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2602 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2603 ddi_translations[level].cri_txdeemph_override_5_0) |
2604 CRI_TXDEEMPH_OVERRIDE_11_6(
2605 ddi_translations[level].cri_txdeemph_override_11_6) |
2606 CRI_TXDEEMPH_OVERRIDE_EN;
58106b7d 2607 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
07685c82
MN		 2608
2609 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2610 }
2611
2612 /*
2613 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2614 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2615 * values from table for which TX1 and TX2 enabled.
2616 */
2617 for (ln = 0; ln < 2; ln++) {
58106b7d 2618 val = I915_READ(MG_CLKHUB(ln, port));
07685c82
MN		 2619 if (link_clock < 300000)
2620 val |= CFG_LOW_RATE_LKREN_EN;
2621 else
2622 val &= ~CFG_LOW_RATE_LKREN_EN;
58106b7d 2623 I915_WRITE(MG_CLKHUB(ln, port), val);
07685c82
MN		 2624 }
2625
2626 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2627 for (ln = 0; ln < 2; ln++) {
58106b7d 2628 val = I915_READ(MG_TX1_DCC(ln, port));
07685c82
MN		 2629 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2630 if (link_clock <= 500000) {
2631 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2632 } else {
2633 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2634 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2635 }
58106b7d 2636 I915_WRITE(MG_TX1_DCC(ln, port), val);
07685c82 2637
58106b7d 2638 val = I915_READ(MG_TX2_DCC(ln, port));
07685c82
MN		 2639 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2640 if (link_clock <= 500000) {
2641 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2642 } else {
2643 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2644 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2645 }
58106b7d 2646 I915_WRITE(MG_TX2_DCC(ln, port), val);
07685c82
MN		 2647 }
2648
2649 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2650 for (ln = 0; ln < 2; ln++) {
58106b7d 2651 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
07685c82 2652 val |= CRI_CALCINIT;
58106b7d 2653 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
07685c82 2654
58106b7d 2655 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
07685c82 2656 val |= CRI_CALCINIT;
58106b7d 2657 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
07685c82
MN		 2658 }
2659}
2660
2661static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2662 int link_clock,
2663 u32 level,
fb5c8e9d
MN		 2664 enum intel_output_type type)
2665{
176597a1 2666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fb5c8e9d
MN		 2667 enum port port = encoder->port;
2668
176597a1 2669 if (intel_port_is_combophy(dev_priv, port))
fb5c8e9d
MN		 2670 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2671 else
07685c82 2672 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
fb5c8e9d
MN		 2673}
2674
3d0c5005 2675static u32 translate_signal_level(int signal_levels)
f8896f5d 2676{
97eeb872 2677 int i;
f8896f5d 2678
97eeb872
VS		 2679 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2680 if (index_to_dp_signal_levels[i] == signal_levels)
2681 return i;
f8896f5d
DW		 2682 }
2683
97eeb872
VS		 2684 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2685 signal_levels);
2686
2687 return 0;
f8896f5d
DW		 2688}
2689
3d0c5005 2690static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
1b6e2fd2 2691{
3d0c5005 2692 u8 train_set = intel_dp->train_set[0];
1b6e2fd2
RV		 2693 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2694 DP_TRAIN_PRE_EMPHASIS_MASK);
2695
2696 return translate_signal_level(signal_levels);
2697}
2698
d509af6c 2699u32 bxt_signal_levels(struct intel_dp *intel_dp)
f8896f5d
DW		 2700{
2701 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2702 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d 2703 struct intel_encoder *encoder = &dport->base;
d02ace87 2704 int level = intel_ddi_dp_level(intel_dp);
d509af6c 2705
2dd24a9c 2706 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 2707 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2708 level, encoder->type);
fb5c8e9d 2709 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 2710 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c 2711 else
7d4f37b5 2712 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
d509af6c
RV		 2713
2714 return 0;
2715}
2716
3d0c5005 2717u32 ddi_signal_levels(struct intel_dp *intel_dp)
d509af6c
RV		 2718{
2719 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2720 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2721 struct intel_encoder *encoder = &dport->base;
d02ace87 2722 int level = intel_ddi_dp_level(intel_dp);
f8896f5d 2723
b976dc53 2724 if (IS_GEN9_BC(dev_priv))
081dfcfa 2725 skl_ddi_set_iboost(encoder, level, encoder->type);
d509af6c 2726
f8896f5d
DW		 2727 return DDI_BUF_TRANS_SELECT(level);
2728}
2729
bb1c7edc 2730static inline
3d0c5005
JN		 2731u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2732 enum port port)
bb1c7edc
MK		 2733{
2734 if (intel_port_is_combophy(dev_priv, port)) {
2735 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2736 } else if (intel_port_is_tc(dev_priv, port)) {
2737 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2738
2739 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2740 }
2741
2742 return 0;
2743}
2744
3b8c0d5b
JN		 2745static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2746 const struct intel_crtc_state *crtc_state)
c27e917e 2747{
3b8c0d5b 2748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c27e917e 2749 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3b8c0d5b
JN		 2750 enum port port = encoder->port;
2751 u32 val;
c27e917e 2752
3b8c0d5b 2753 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2754
3b8c0d5b
JN		 2755 val = I915_READ(DPCLKA_CFGCR0_ICL);
2756 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
c27e917e 2757
3b8c0d5b
JN		 2758 if (intel_port_is_combophy(dev_priv, port)) {
2759 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2760 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
c27e917e 2761 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
3b8c0d5b 2762 POSTING_READ(DPCLKA_CFGCR0_ICL);
c27e917e 2763 }
3b8c0d5b
JN		 2764
2765 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2766 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2767
2768 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2769}
2770
3b8c0d5b 2771static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
c27e917e 2772{
3b8c0d5b
JN		 2773 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2774 enum port port = encoder->port;
2775 u32 val;
c27e917e 2776
3b8c0d5b 2777 mutex_lock(&dev_priv->dpll_lock);
c27e917e 2778
3b8c0d5b
JN		 2779 val = I915_READ(DPCLKA_CFGCR0_ICL);
2780 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2781 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
c27e917e 2782
3b8c0d5b 2783 mutex_unlock(&dev_priv->dpll_lock);
c27e917e
PZ		 2784}
2785
70332ac5
ID		 2786void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2787{
2788 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
30f5ccfa 2789 u32 val;
1dd07e56
ID		 2790 enum port port;
2791 u32 port_mask;
2792 bool ddi_clk_needed;
30f5ccfa
ID		 2793
2794 /*
2795 * In case of DP MST, we sanitize the primary encoder only, not the
2796 * virtual ones.
2797 */
2798 if (encoder->type == INTEL_OUTPUT_DP_MST)
2799 return;
2800
30f5ccfa
ID		 2801 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2802 u8 pipe_mask;
2803 bool is_mst;
2804
2805 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2806 /*
2807 * In the unlikely case that BIOS enables DP in MST mode, just
2808 * warn since our MST HW readout is incomplete.
2809 */
2810 if (WARN_ON(is_mst))
2811 return;
2812 }
70332ac5 2813
1dd07e56
ID		 2814 port_mask = BIT(encoder->port);
2815 ddi_clk_needed = encoder->base.crtc;
70332ac5 2816
1dd07e56
ID		 2817 if (encoder->type == INTEL_OUTPUT_DSI) {
2818 struct intel_encoder *other_encoder;
70332ac5 2819
1dd07e56
ID		 2820 port_mask = intel_dsi_encoder_ports(encoder);
2821 /*
2822 * Sanity check that we haven't incorrectly registered another
2823 * encoder using any of the ports of this DSI encoder.
2824 */
2825 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2826 if (other_encoder == encoder)
2827 continue;
2828
2829 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2830 return;
2831 }
2832 /*
942d1cf4
VK		 2833 * For DSI we keep the ddi clocks gated
2834 * except during enable/disable sequence.
1dd07e56 2835 */
942d1cf4 2836 ddi_clk_needed = false;
1dd07e56
ID		 2837 }
2838
2839 val = I915_READ(DPCLKA_CFGCR0_ICL);
2840 for_each_port_masked(port, port_mask) {
2841 bool ddi_clk_ungated = !(val &
2842 icl_dpclka_cfgcr0_clk_off(dev_priv,
2843 port));
2844
2845 if (ddi_clk_needed == ddi_clk_ungated)
2846 continue;
2847
2848 /*
2849 * Punt on the case now where clock is gated, but it would
2850 * be needed by the port. Something else is really broken then.
2851 */
2852 if (WARN_ON(ddi_clk_needed))
2853 continue;
2854
2855 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2856 port_name(port));
2857 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2858 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2859 }
70332ac5
ID		 2860}
2861
d7c530b2 2862static void intel_ddi_clk_select(struct intel_encoder *encoder,
0e5fa646 2863 const struct intel_crtc_state *crtc_state)
6441ab5f 2864{
e404ba8d 2865 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2866 enum port port = encoder->port;
3d0c5005 2867 u32 val;
0e5fa646 2868 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
6441ab5f 2869
c856052a
ACO		 2870 if (WARN_ON(!pll))
2871 return;
2872
04bf68bb 2873 mutex_lock(&dev_priv->dpll_lock);
8edcda12 2874
2dd24a9c 2875 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2876 if (!intel_port_is_combophy(dev_priv, port))
c27e917e 2877 I915_WRITE(DDI_CLK_SEL(port),
20fd2ab7 2878 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
c27e917e 2879 } else if (IS_CANNONLAKE(dev_priv)) {
555e38d2
RV		 2880 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2881 val = I915_READ(DPCLKA_CFGCR0);
23a7068e 2882 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
0823eb9c 2883 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
555e38d2 2884 I915_WRITE(DPCLKA_CFGCR0, val);
efa80add 2885
555e38d2
RV		 2886 /*
2887 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2888 * This step and the step before must be done with separate
2889 * register writes.
2890 */
2891 val = I915_READ(DPCLKA_CFGCR0);
87145d95 2892 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
555e38d2
RV		 2893 I915_WRITE(DPCLKA_CFGCR0, val);
2894 } else if (IS_GEN9_BC(dev_priv)) {
5416d871 2895 /* DDI -> PLL mapping */
efa80add
S		 2896 val = I915_READ(DPLL_CTRL2);
2897
2898 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
04bf68bb 2899 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
0823eb9c 2900 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
efa80add
S		 2901 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2902
2903 I915_WRITE(DPLL_CTRL2, val);
5416d871 2904
c56b89f1 2905 } else if (INTEL_GEN(dev_priv) < 9) {
c856052a 2906 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
efa80add 2907 }
8edcda12
RV		 2908
2909 mutex_unlock(&dev_priv->dpll_lock);
e404ba8d
VS		 2910}
2911
6b8506d5
VS		 2912static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2913{
2914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 2915 enum port port = encoder->port;
6b8506d5 2916
2dd24a9c 2917 if (INTEL_GEN(dev_priv) >= 11) {
176597a1 2918 if (!intel_port_is_combophy(dev_priv, port))
c27e917e
PZ		 2919 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2920 } else if (IS_CANNONLAKE(dev_priv)) {
6b8506d5
VS		 2921 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2922 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
c27e917e 2923 } else if (IS_GEN9_BC(dev_priv)) {
6b8506d5
VS		 2924 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2925 DPLL_CTRL2_DDI_CLK_OFF(port));
c27e917e 2926 } else if (INTEL_GEN(dev_priv) < 9) {
6b8506d5 2927 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
c27e917e 2928 }
6b8506d5
VS		 2929}
2930
cb9ff519
ID		 2931static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2932{
2933 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2934 enum port port = dig_port->base.port;
2935 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2936 u32 val;
9c11b121 2937 int ln;
cb9ff519
ID		 2938
2939 if (tc_port == PORT_TC_NONE)
2940 return;
2941
9c11b121
ID		 2942 for (ln = 0; ln < 2; ln++) {
2943 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2944 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2945 MG_DP_MODE_CFG_TRPWR_GATING |
2946 MG_DP_MODE_CFG_CLNPWR_GATING |
2947 MG_DP_MODE_CFG_DIGPWR_GATING |
2948 MG_DP_MODE_CFG_GAONPWR_GATING;
9c11b121 2949 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2950 }
2951
2952 val = I915_READ(MG_MISC_SUS0(tc_port));
2953 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2954 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2955 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2956 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2957 MG_MISC_SUS0_CFG_TRPWR_GATING |
2958 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2959 MG_MISC_SUS0_CFG_DGPWR_GATING;
2960 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2961}
2962
2963static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2964{
2965 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2966 enum port port = dig_port->base.port;
2967 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
cb9ff519 2968 u32 val;
9c11b121 2969 int ln;
cb9ff519
ID		 2970
2971 if (tc_port == PORT_TC_NONE)
2972 return;
2973
9c11b121
ID		 2974 for (ln = 0; ln < 2; ln++) {
2975 val = I915_READ(MG_DP_MODE(ln, port));
cb9ff519
ID		 2976 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2977 MG_DP_MODE_CFG_TRPWR_GATING |
2978 MG_DP_MODE_CFG_CLNPWR_GATING |
2979 MG_DP_MODE_CFG_DIGPWR_GATING |
2980 MG_DP_MODE_CFG_GAONPWR_GATING);
9c11b121 2981 I915_WRITE(MG_DP_MODE(ln, port), val);
cb9ff519
ID		 2982 }
2983
2984 val = I915_READ(MG_MISC_SUS0(tc_port));
2985 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2986 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2987 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2988 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2989 MG_MISC_SUS0_CFG_TRPWR_GATING |
2990 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2991 MG_MISC_SUS0_CFG_DGPWR_GATING);
2992 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2993}
2994
93b662d3
ID		 2995static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2996{
2997 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2998 enum port port = intel_dig_port->base.port;
c905eb28 2999 u32 ln0, ln1, lane_mask;
93b662d3 3000
e9b7e142 3001 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
93b662d3
ID		 3002 return;
3003
37fc7845
JRS		 3004 ln0 = I915_READ(MG_DP_MODE(0, port));
3005 ln1 = I915_READ(MG_DP_MODE(1, port));
93b662d3 3006
e9b7e142
ID		 3007 switch (intel_dig_port->tc_mode) {
3008 case TC_PORT_DP_ALT:
93b662d3
ID		 3009 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3010 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3011
c905eb28 3012 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
93b662d3 3013
c905eb28 3014 switch (lane_mask) {
93b662d3
ID		 3015 case 0x1:
3016 case 0x4:
3017 break;
3018 case 0x2:
3019 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3020 break;
3021 case 0x3:
3022 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3023 MG_DP_MODE_CFG_DP_X2_MODE;
3024 break;
3025 case 0x8:
3026 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3027 break;
3028 case 0xC:
3029 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3030 MG_DP_MODE_CFG_DP_X2_MODE;
3031 break;
3032 case 0xF:
3033 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3034 MG_DP_MODE_CFG_DP_X2_MODE;
3035 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3036 MG_DP_MODE_CFG_DP_X2_MODE;
3037 break;
3038 default:
c905eb28 3039 MISSING_CASE(lane_mask);
93b662d3
ID		 3040 }
3041 break;
3042
3043 case TC_PORT_LEGACY:
3044 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3045 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3046 break;
3047
3048 default:
e9b7e142 3049 MISSING_CASE(intel_dig_port->tc_mode);
93b662d3
ID		 3050 return;
3051 }
3052
37fc7845
JRS		 3053 I915_WRITE(MG_DP_MODE(0, port), ln0);
3054 I915_WRITE(MG_DP_MODE(1, port), ln1);
93b662d3
ID		 3055}
3056
a322b975
AS		 3057static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3058 const struct intel_crtc_state *crtc_state)
3059{
3060 if (!crtc_state->fec_enable)
3061 return;
3062
3063 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3064 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3065}
3066
5c44b938
AS		 3067static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3068 const struct intel_crtc_state *crtc_state)
3069{
3070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3071 enum port port = encoder->port;
3072 u32 val;
3073
3074 if (!crtc_state->fec_enable)
3075 return;
3076
3077 val = I915_READ(DP_TP_CTL(port));
3078 val |= DP_TP_CTL_FEC_ENABLE;
3079 I915_WRITE(DP_TP_CTL(port), val);
3080
97a04e0d 3081 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
5c44b938
AS		 3082 DP_TP_STATUS_FEC_ENABLE_LIVE,
3083 DP_TP_STATUS_FEC_ENABLE_LIVE,
3084 1))
3085 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3086}
3087
d6a09cee
AS		 3088static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3089 const struct intel_crtc_state *crtc_state)
3090{
3091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3092 enum port port = encoder->port;
3093 u32 val;
3094
3095 if (!crtc_state->fec_enable)
3096 return;
3097
3098 val = I915_READ(DP_TP_CTL(port));
3099 val &= ~DP_TP_CTL_FEC_ENABLE;
3100 I915_WRITE(DP_TP_CTL(port), val);
3101 POSTING_READ(DP_TP_CTL(port));
3102}
3103
ba88d153 3104static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
45e0327e
VS		 3105 const struct intel_crtc_state *crtc_state,
3106 const struct drm_connector_state *conn_state)
e404ba8d 3107{
ba88d153
MN		 3108 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3110 enum port port = encoder->port;
62b69566 3111 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
45e0327e 3112 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
d02ace87 3113 int level = intel_ddi_dp_level(intel_dp);
b2ccb822 3114
45e0327e 3115 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
e081c846 3116
45e0327e
VS		 3117 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3118 crtc_state->lane_count, is_mst);
680b71c2
VS		 3119
3120 intel_edp_panel_on(intel_dp);
32bdc400 3121
0e5fa646 3122 intel_ddi_clk_select(encoder, crtc_state);
62b69566 3123
3b2ed431
ID		 3124 if (!intel_port_is_tc(dev_priv, port) ||
3125 dig_port->tc_mode != TC_PORT_TBT_ALT)
3126 intel_display_power_get(dev_priv,
3127 dig_port->ddi_io_power_domain);
62b69566 3128
93b662d3 3129 icl_program_mg_dp_mode(dig_port);
bc334d91 3130 icl_disable_phy_clock_gating(dig_port);
340a44be 3131
2dd24a9c 3132 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3133 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3134 level, encoder->type);
fb5c8e9d 3135 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3136 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3137 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3138 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
381f9570 3139 else
3a6d84e6 3140 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2f7460a7 3141
cfda08cd
ID		 3142 if (intel_port_is_combophy(dev_priv, port)) {
3143 bool lane_reversal =
3144 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3145
3146 intel_combo_phy_power_up_lanes(dev_priv, port, false,
3147 crtc_state->lane_count,
3148 lane_reversal);
3149 }
3150
ba88d153 3151 intel_ddi_init_dp_buf_reg(encoder);
be1c63c8
LP		 3152 if (!is_mst)
3153 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2279298d
GS		 3154 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3155 true);
a322b975 3156 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
ba88d153
MN		 3157 intel_dp_start_link_train(intel_dp);
3158 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3159 intel_dp_stop_link_train(intel_dp);
afb2c443 3160
5c44b938
AS		 3161 intel_ddi_enable_fec(encoder, crtc_state);
3162
bc334d91
PZ		 3163 icl_enable_phy_clock_gating(dig_port);
3164
2b5cf4ef
ID		 3165 if (!is_mst)
3166 intel_ddi_enable_pipe_clock(crtc_state);
7182414e
MN		 3167
3168 intel_dsc_enable(encoder, crtc_state);
ba88d153 3169}
901c2daf 3170
ba88d153 3171static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
ac240288 3172 const struct intel_crtc_state *crtc_state,
45e0327e 3173 const struct drm_connector_state *conn_state)
ba88d153 3174{
f99be1b3
VS		 3175 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3176 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
ba88d153 3177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3178 enum port port = encoder->port;
ba88d153 3179 int level = intel_ddi_hdmi_level(dev_priv, port);
62b69566 3180 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
c19b0669 3181
ba88d153 3182 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
0e5fa646 3183 intel_ddi_clk_select(encoder, crtc_state);
62b69566
ACO		 3184
3185 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3186
93b662d3 3187 icl_program_mg_dp_mode(dig_port);
cb9ff519
ID		 3188 icl_disable_phy_clock_gating(dig_port);
3189
2dd24a9c 3190 if (INTEL_GEN(dev_priv) >= 11)
07685c82
MN		 3191 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3192 level, INTEL_OUTPUT_HDMI);
fb5c8e9d 3193 else if (IS_CANNONLAKE(dev_priv))
f3cf4ba4 3194 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
cc3f90f0 3195 else if (IS_GEN9_LP(dev_priv))
7d4f37b5 3196 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2f7460a7 3197 else
7ea79333 3198 intel_prepare_hdmi_ddi_buffers(encoder, level);
2f7460a7 3199
cb9ff519
ID		 3200 icl_enable_phy_clock_gating(dig_port);
3201
2f7460a7 3202 if (IS_GEN9_BC(dev_priv))
081dfcfa 3203 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
8d8bb85e 3204
c7373764
ID		 3205 intel_ddi_enable_pipe_clock(crtc_state);
3206
790ea70c 3207 intel_dig_port->set_infoframes(encoder,
45e0327e 3208 crtc_state->has_infoframe,
f99be1b3 3209 crtc_state, conn_state);
ba88d153 3210}
32bdc400 3211
1524e93e 3212static void intel_ddi_pre_enable(struct intel_encoder *encoder,
45e0327e 3213 const struct intel_crtc_state *crtc_state,
5f88a9c6 3214 const struct drm_connector_state *conn_state)
ba88d153 3215{
45e0327e
VS		 3216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3218 enum pipe pipe = crtc->pipe;
30cf6db8 3219
1939ba51
VS		 3220 /*
3221 * When called from DP MST code:
3222 * - conn_state will be NULL
3223 * - encoder will be the main encoder (ie. mst->primary)
3224 * - the main connector associated with this port
3225 * won't be active or linked to a crtc
3226 * - crtc_state will be the state of the first stream to
3227 * be activated on this port, and it may not be the same
3228 * stream that will be deactivated last, but each stream
3229 * should have a state that is identical when it comes to
3230 * the DP link parameteres
3231 */
3232
45e0327e 3233 WARN_ON(crtc_state->has_pch_encoder);
364a3fe1 3234
3b8c0d5b
JN		 3235 if (INTEL_GEN(dev_priv) >= 11)
3236 icl_map_plls_to_ports(encoder, crtc_state);
3237
364a3fe1
JN		 3238 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3239
06c812d7 3240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
45e0327e 3241 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
06c812d7
SS		 3242 } else {
3243 struct intel_lspcon *lspcon =
3244 enc_to_intel_lspcon(&encoder->base);
3245
45e0327e 3246 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
06c812d7
SS		 3247 if (lspcon->active) {
3248 struct intel_digital_port *dig_port =
3249 enc_to_dig_port(&encoder->base);
3250
3251 dig_port->set_infoframes(encoder,
3252 crtc_state->has_infoframe,
3253 crtc_state, conn_state);
3254 }
3255 }
6441ab5f
PZ		 3256}
3257
d6a09cee
AS		 3258static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3259 const struct intel_crtc_state *crtc_state)
e725f645
VS		 3260{
3261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3262 enum port port = encoder->port;
e725f645
VS		 3263 bool wait = false;
3264 u32 val;
3265
3266 val = I915_READ(DDI_BUF_CTL(port));
3267 if (val & DDI_BUF_CTL_ENABLE) {
3268 val &= ~DDI_BUF_CTL_ENABLE;
3269 I915_WRITE(DDI_BUF_CTL(port), val);
3270 wait = true;
3271 }
3272
3273 val = I915_READ(DP_TP_CTL(port));
3274 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3275 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3276 I915_WRITE(DP_TP_CTL(port), val);
3277
d6a09cee
AS		 3278 /* Disable FEC in DP Sink */
3279 intel_ddi_disable_fec_state(encoder, crtc_state);
3280
e725f645
VS		 3281 if (wait)
3282 intel_wait_ddi_buf_idle(dev_priv, port);
3283}
3284
f45f3da7
VS		 3285static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3286 const struct intel_crtc_state *old_crtc_state,
3287 const struct drm_connector_state *old_conn_state)
6441ab5f 3288{
f45f3da7
VS		 3289 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3290 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3291 struct intel_dp *intel_dp = &dig_port->dp;
be1c63c8
LP		 3292 bool is_mst = intel_crtc_has_type(old_crtc_state,
3293 INTEL_OUTPUT_DP_MST);
2886e93f 3294
2b5cf4ef
ID		 3295 if (!is_mst) {
3296 intel_ddi_disable_pipe_clock(old_crtc_state);
3297 /*
3298 * Power down sink before disabling the port, otherwise we end
3299 * up getting interrupts from the sink on detecting link loss.
3300 */
be1c63c8 3301 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2b5cf4ef 3302 }
c5f93fcf 3303
d6a09cee 3304 intel_disable_ddi_buf(encoder, old_crtc_state);
7618138d 3305
f45f3da7
VS		 3306 intel_edp_panel_vdd_on(intel_dp);
3307 intel_edp_panel_off(intel_dp);
a836bdf9 3308
3b2ed431
ID		 3309 if (!intel_port_is_tc(dev_priv, encoder->port) ||
3310 dig_port->tc_mode != TC_PORT_TBT_ALT)
3311 intel_display_power_put_unchecked(dev_priv,
3312 dig_port->ddi_io_power_domain);
c5f93fcf 3313
f45f3da7
VS		 3314 intel_ddi_clk_disable(encoder);
3315}
c5f93fcf 3316
f45f3da7
VS		 3317static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3318 const struct intel_crtc_state *old_crtc_state,
3319 const struct drm_connector_state *old_conn_state)
3320{
3321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3322 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3323 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
82a4d9c0 3324
790ea70c 3325 dig_port->set_infoframes(encoder, false,
c7373764
ID		 3326 old_crtc_state, old_conn_state);
3327
afb2c443
ID		 3328 intel_ddi_disable_pipe_clock(old_crtc_state);
3329
d6a09cee 3330 intel_disable_ddi_buf(encoder, old_crtc_state);
62b69566 3331
0e6e0be4
CW		 3332 intel_display_power_put_unchecked(dev_priv,
3333 dig_port->ddi_io_power_domain);
b2ccb822 3334
f45f3da7
VS		 3335 intel_ddi_clk_disable(encoder);
3336
3337 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3338}
3339
3340static void intel_ddi_post_disable(struct intel_encoder *encoder,
3341 const struct intel_crtc_state *old_crtc_state,
3342 const struct drm_connector_state *old_conn_state)
3343{
3b8c0d5b
JN		 3344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3345
f45f3da7 3346 /*
1939ba51
VS		 3347 * When called from DP MST code:
3348 * - old_conn_state will be NULL
3349 * - encoder will be the main encoder (ie. mst->primary)
3350 * - the main connector associated with this port
3351 * won't be active or linked to a crtc
3352 * - old_crtc_state will be the state of the last stream to
3353 * be deactivated on this port, and it may not be the same
3354 * stream that was activated last, but each stream
3355 * should have a state that is identical when it comes to
3356 * the DP link parameteres
f45f3da7 3357 */
1939ba51
VS		 3358
3359 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
f45f3da7
VS		 3360 intel_ddi_post_disable_hdmi(encoder,
3361 old_crtc_state, old_conn_state);
3362 else
3363 intel_ddi_post_disable_dp(encoder,
3364 old_crtc_state, old_conn_state);
3b8c0d5b
JN		 3365
3366 if (INTEL_GEN(dev_priv) >= 11)
3367 icl_unmap_plls_to_ports(encoder);
6441ab5f
PZ		 3368}
3369
1524e93e 3370void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 3371 const struct intel_crtc_state *old_crtc_state,
3372 const struct drm_connector_state *old_conn_state)
b7076546 3373{
1524e93e 3374 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3d0c5005 3375 u32 val;
b7076546
ML		 3376
3377 /*
3378 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3379 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3380 * step 13 is the correct place for it. Step 18 is where it was
3381 * originally before the BUN.
3382 */
3383 val = I915_READ(FDI_RX_CTL(PIPE_A));
3384 val &= ~FDI_RX_ENABLE;
3385 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3386
d6a09cee 3387 intel_disable_ddi_buf(encoder, old_crtc_state);
fb0bd3bd 3388 intel_ddi_clk_disable(encoder);
b7076546
ML		 3389
3390 val = I915_READ(FDI_RX_MISC(PIPE_A));
3391 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3392 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3393 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3394
3395 val = I915_READ(FDI_RX_CTL(PIPE_A));
3396 val &= ~FDI_PCDCLK;
3397 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3398
3399 val = I915_READ(FDI_RX_CTL(PIPE_A));
3400 val &= ~FDI_RX_PLL_ENABLE;
3401 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3402}
3403
15d05f0e
VS		 3404static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3405 const struct intel_crtc_state *crtc_state,
3406 const struct drm_connector_state *conn_state)
72662e10 3407{
15d05f0e
VS		 3408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3409 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0fce04c8 3410 enum port port = encoder->port;
72662e10 3411
15d05f0e
VS		 3412 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3413 intel_dp_stop_link_train(intel_dp);
d6c50ff8 3414
15d05f0e
VS		 3415 intel_edp_backlight_on(crtc_state, conn_state);
3416 intel_psr_enable(intel_dp, crtc_state);
3c053a96 3417 intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
15d05f0e 3418 intel_edp_drrs_enable(intel_dp, crtc_state);
3ab9c637 3419
15d05f0e
VS		 3420 if (crtc_state->has_audio)
3421 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3422}
3423
8f19b401
ID		 3424static i915_reg_t
3425gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3426 enum port port)
3427{
3428 static const i915_reg_t regs[] = {
3429 [PORT_A] = CHICKEN_TRANS_EDP,
3430 [PORT_B] = CHICKEN_TRANS_A,
3431 [PORT_C] = CHICKEN_TRANS_B,
3432 [PORT_D] = CHICKEN_TRANS_C,
3433 [PORT_E] = CHICKEN_TRANS_A,
3434 };
3435
3436 WARN_ON(INTEL_GEN(dev_priv) < 9);
3437
3438 if (WARN_ON(port < PORT_A || port > PORT_E))
3439 port = PORT_A;
3440
3441 return regs[port];
3442}
3443
15d05f0e
VS		 3444static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3445 const struct intel_crtc_state *crtc_state,
3446 const struct drm_connector_state *conn_state)
3447{
3448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3449 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
277ab5ab 3450 struct drm_connector *connector = conn_state->connector;
0fce04c8 3451 enum port port = encoder->port;
15d05f0e 3452
277ab5ab
VS		 3453 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3454 crtc_state->hdmi_high_tmds_clock_ratio,
3455 crtc_state->hdmi_scrambling))
3456 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3457 connector->base.id, connector->name);
15d05f0e 3458
0519c102
VS		 3459 /* Display WA #1143: skl,kbl,cfl */
3460 if (IS_GEN9_BC(dev_priv)) {
3461 /*
3462 * For some reason these chicken bits have been
3463 * stuffed into a transcoder register, event though
3464 * the bits affect a specific DDI port rather than
3465 * a specific transcoder.
3466 */
8f19b401 3467 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
0519c102
VS		 3468 u32 val;
3469
8f19b401 3470 val = I915_READ(reg);
0519c102
VS		 3471
3472 if (port == PORT_E)
3473 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3474 DDIE_TRAINING_OVERRIDE_VALUE;
3475 else
3476 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3477 DDI_TRAINING_OVERRIDE_VALUE;
3478
8f19b401
ID		 3479 I915_WRITE(reg, val);
3480 POSTING_READ(reg);
0519c102
VS		 3481
3482 udelay(1);
3483
3484 if (port == PORT_E)
3485 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3486 DDIE_TRAINING_OVERRIDE_VALUE);
3487 else
3488 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3489 DDI_TRAINING_OVERRIDE_VALUE);
3490
8f19b401 3491 I915_WRITE(reg, val);
0519c102
VS		 3492 }
3493
15d05f0e
VS		 3494 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3495 * are ignored so nothing special needs to be done besides
3496 * enabling the port.
3497 */
3498 I915_WRITE(DDI_BUF_CTL(port),
3499 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
7b9f35a6 3500
15d05f0e
VS		 3501 if (crtc_state->has_audio)
3502 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3503}
3504
3505static void intel_enable_ddi(struct intel_encoder *encoder,
3506 const struct intel_crtc_state *crtc_state,
3507 const struct drm_connector_state *conn_state)
3508{
3509 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3510 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3511 else
3512 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
ee5e5e7a
SP		 3513
3514 /* Enable hdcp if it's desired */
3515 if (conn_state->content_protection ==
3516 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3517 intel_hdcp_enable(to_intel_connector(conn_state->connector));
5ab432ef
DV		 3518}
3519
33f083f0
VS		 3520static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3521 const struct intel_crtc_state *old_crtc_state,
3522 const struct drm_connector_state *old_conn_state)
5ab432ef 3523{
33f083f0 3524 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6c50ff8 3525
edb2e530
VS		 3526 intel_dp->link_trained = false;
3527
37255d8d 3528 if (old_crtc_state->has_audio)
8ec47de2
VS		 3529 intel_audio_codec_disable(encoder,
3530 old_crtc_state, old_conn_state);
2831d842 3531
33f083f0
VS		 3532 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3533 intel_psr_disable(intel_dp, old_crtc_state);
3534 intel_edp_backlight_off(old_conn_state);
2279298d
GS		 3535 /* Disable the decompression in DP Sink */
3536 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3537 false);
33f083f0 3538}
15953637 3539
33f083f0
VS		 3540static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *old_crtc_state,
3542 const struct drm_connector_state *old_conn_state)
3543{
277ab5ab
VS		 3544 struct drm_connector *connector = old_conn_state->connector;
3545
33f083f0 3546 if (old_crtc_state->has_audio)
8ec47de2
VS		 3547 intel_audio_codec_disable(encoder,
3548 old_crtc_state, old_conn_state);
d6c50ff8 3549
277ab5ab
VS		 3550 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3551 false, false))
3552 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3553 connector->base.id, connector->name);
33f083f0
VS		 3554}
3555
3556static void intel_disable_ddi(struct intel_encoder *encoder,
3557 const struct intel_crtc_state *old_crtc_state,
3558 const struct drm_connector_state *old_conn_state)
3559{
ee5e5e7a
SP		 3560 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3561
33f083f0
VS		 3562 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3563 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3564 else
3565 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
72662e10 3566}
79f689aa 3567
2ef82327
HG		 3568static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3569 const struct intel_crtc_state *crtc_state,
3570 const struct drm_connector_state *conn_state)
3571{
3572 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3573
5aa2c9ae
VS		 3574 intel_ddi_set_pipe_settings(crtc_state);
3575
23ec9f52 3576 intel_psr_update(intel_dp, crtc_state);
2ef82327 3577 intel_edp_drrs_enable(intel_dp, crtc_state);
63a23d24
ML		 3578
3579 intel_panel_update_backlight(encoder, crtc_state, conn_state);
2ef82327
HG		 3580}
3581
3582static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3583 const struct intel_crtc_state *crtc_state,
3584 const struct drm_connector_state *conn_state)
3585{
3586 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3587 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
634852d1
R		 3588
3589 if (conn_state->content_protection ==
3590 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3591 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3592 else if (conn_state->content_protection ==
3593 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3594 intel_hdcp_disable(to_intel_connector(conn_state->connector));
2ef82327
HG		 3595}
3596
03ad7d88
MN		 3597static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3598 const struct intel_crtc_state *pipe_config,
3599 enum port port)
3600{
3601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3602 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3603 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3604 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3605 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3606
3ee2771e
ID		 3607 WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
3608
03ad7d88
MN		 3609 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3610 switch (pipe_config->lane_count) {
3611 case 1:
3612 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3613 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3614 break;
3615 case 2:
3616 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3617 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3618 break;
3619 case 4:
3620 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3621 break;
3622 default:
3623 MISSING_CASE(pipe_config->lane_count);
3624 }
3625 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3626}
3627
24a7bfe0
ID		 3628static void
3629intel_ddi_update_prepare(struct intel_atomic_state *state,
3630 struct intel_encoder *encoder,
3631 struct intel_crtc *crtc)
3632{
3633 struct intel_crtc_state *crtc_state =
3634 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3635 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3636
3637 WARN_ON(crtc && crtc->active);
3638
3639 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3640 if (crtc_state && crtc_state->base.active)
3641 intel_update_active_dpll(state, crtc, encoder);
3642}
3643
3644static void
3645intel_ddi_update_complete(struct intel_atomic_state *state,
3646 struct intel_encoder *encoder,
3647 struct intel_crtc *crtc)
3648{
3649 intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3650}
3651
bdaa29b6
ID		 3652static void
3653intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3654 const struct intel_crtc_state *crtc_state,
3655 const struct drm_connector_state *conn_state)
03ad7d88 3656{
bdaa29b6 3657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03ad7d88 3658 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
24a7bfe0 3659 bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
bdaa29b6
ID		 3660 enum port port = encoder->port;
3661
24a7bfe0
ID		 3662 if (is_tc_port)
3663 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3664
3665 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
bdaa29b6
ID		 3666 intel_display_power_get(dev_priv,
3667 intel_ddi_main_link_aux_domain(dig_port));
3668
3669 if (IS_GEN9_LP(dev_priv))
3670 bxt_ddi_phy_set_lane_optim_mask(encoder,
3671 crtc_state->lane_lat_optim_mask);
03ad7d88
MN		 3672
3673 /*
3674 * Program the lane count for static/dynamic connections on Type-C ports.
3675 * Skip this step for TBT.
3676 */
e9b7e142 3677 if (dig_port->tc_mode == TC_PORT_TBT_ALT)
03ad7d88
MN		 3678 return;
3679
bdaa29b6
ID		 3680 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3681}
3682
3683static void
3684intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3685 const struct intel_crtc_state *crtc_state,
3686 const struct drm_connector_state *conn_state)
3687{
3688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3689 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
24a7bfe0 3690 bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
bdaa29b6 3691
24a7bfe0 3692 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
0e6e0be4
CW		 3693 intel_display_power_put_unchecked(dev_priv,
3694 intel_ddi_main_link_aux_domain(dig_port));
24a7bfe0
ID		 3695
3696 if (is_tc_port)
3697 intel_tc_port_put_link(dig_port);
03ad7d88
MN		 3698}
3699
97068c1b 3700static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3701{
ad64217b
ACO		 3702 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3703 struct drm_i915_private *dev_priv =
3704 to_i915(intel_dig_port->base.base.dev);
8f4f2797 3705 enum port port = intel_dig_port->base.port;
3d0c5005 3706 u32 val;
f3e227df 3707 bool wait = false;
c19b0669
PZ		 3708
3709 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3710 val = I915_READ(DDI_BUF_CTL(port));
3711 if (val & DDI_BUF_CTL_ENABLE) {
3712 val &= ~DDI_BUF_CTL_ENABLE;
3713 I915_WRITE(DDI_BUF_CTL(port), val);
3714 wait = true;
3715 }
3716
3717 val = I915_READ(DP_TP_CTL(port));
3718 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3719 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3720 I915_WRITE(DP_TP_CTL(port), val);
3721 POSTING_READ(DP_TP_CTL(port));
3722
3723 if (wait)
3724 intel_wait_ddi_buf_idle(dev_priv, port);
3725 }
3726
0e32b39c 3727 val = DP_TP_CTL_ENABLE |
c19b0669 3728 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
64ee2fd2 3729 if (intel_dp->link_mst)
0e32b39c
DA		 3730 val |= DP_TP_CTL_MODE_MST;
3731 else {
3732 val |= DP_TP_CTL_MODE_SST;
3733 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3734 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3735 }
c19b0669
PZ		 3736 I915_WRITE(DP_TP_CTL(port), val);
3737 POSTING_READ(DP_TP_CTL(port));
3738
3739 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3740 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3741 POSTING_READ(DDI_BUF_CTL(port));
3742
3743 udelay(600);
3744}
00c09d70 3745
2085cc5d
VS		 3746static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3747 enum transcoder cpu_transcoder)
9935f7fa 3748{
2085cc5d
VS		 3749 if (cpu_transcoder == TRANSCODER_EDP)
3750 return false;
9935f7fa 3751
2085cc5d
VS		 3752 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3753 return false;
3754
3755 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3756 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
9935f7fa
LY		 3757}
3758
53e9bf5e
VS		 3759void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3760 struct intel_crtc_state *crtc_state)
3761{
2dd24a9c 3762 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
9378985e 3763 crtc_state->min_voltage_level = 1;
36c1f028
RV		 3764 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3765 crtc_state->min_voltage_level = 2;
53e9bf5e
VS		 3766}
3767
6801c18c 3768void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3769 struct intel_crtc_state *pipe_config)
045ac3b5 3770{
fac5e23e 3771 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
35686a44 3772 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
0cb09a97 3773 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
f99be1b3 3774 struct intel_digital_port *intel_dig_port;
045ac3b5
JB		 3775 u32 temp, flags = 0;
3776
4d1de975
JN		 3777 /* XXX: DSI transcoder paranoia */
3778 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3779 return;
3780
045ac3b5
JB		 3781 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3782 if (temp & TRANS_DDI_PHSYNC)
3783 flags |= DRM_MODE_FLAG_PHSYNC;
3784 else
3785 flags |= DRM_MODE_FLAG_NHSYNC;
3786 if (temp & TRANS_DDI_PVSYNC)
3787 flags |= DRM_MODE_FLAG_PVSYNC;
3788 else
3789 flags |= DRM_MODE_FLAG_NVSYNC;
3790
2d112de7 3791 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3792
3793 switch (temp & TRANS_DDI_BPC_MASK) {
3794 case TRANS_DDI_BPC_6:
3795 pipe_config->pipe_bpp = 18;
3796 break;
3797 case TRANS_DDI_BPC_8:
3798 pipe_config->pipe_bpp = 24;
3799 break;
3800 case TRANS_DDI_BPC_10:
3801 pipe_config->pipe_bpp = 30;
3802 break;
3803 case TRANS_DDI_BPC_12:
3804 pipe_config->pipe_bpp = 36;
3805 break;
3806 default:
3807 break;
3808 }
eb14cb74
VS		 3809
3810 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3811 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3812 pipe_config->has_hdmi_sink = true;
f99be1b3 3813 intel_dig_port = enc_to_dig_port(&encoder->base);
bbd440fb 3814
e5e70d4a
VS		 3815 pipe_config->infoframes.enable |=
3816 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3817
3818 if (pipe_config->infoframes.enable)
bbd440fb 3819 pipe_config->has_infoframe = true;
15953637 3820
ab2cb2cb 3821 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
15953637
SS		 3822 pipe_config->hdmi_scrambling = true;
3823 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3824 pipe_config->hdmi_high_tmds_clock_ratio = true;
d4d6279a 3825 /* fall through */
eb14cb74 3826 case TRANS_DDI_MODE_SELECT_DVI:
e1214b95 3827 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
d4d6279a
ACO		 3828 pipe_config->lane_count = 4;
3829 break;
eb14cb74 3830 case TRANS_DDI_MODE_SELECT_FDI:
e1214b95 3831 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
eb14cb74
VS		 3832 break;
3833 case TRANS_DDI_MODE_SELECT_DP_SST:
e1214b95
VS		 3834 if (encoder->type == INTEL_OUTPUT_EDP)
3835 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3836 else
3837 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3838 pipe_config->lane_count =
3839 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3840 intel_dp_get_m_n(intel_crtc, pipe_config);
3841 break;
eb14cb74 3842 case TRANS_DDI_MODE_SELECT_DP_MST:
e1214b95 3843 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
90a6b7b0
VS		 3844 pipe_config->lane_count =
3845 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3846 intel_dp_get_m_n(intel_crtc, pipe_config);
3847 break;
3848 default:
3849 break;
3850 }
10214420 3851
9935f7fa 3852 pipe_config->has_audio =
2085cc5d 3853 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
9ed109a7 3854
6aa23e65
JN		 3855 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3856 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 3857 /*
3858 * This is a big fat ugly hack.
3859 *
3860 * Some machines in UEFI boot mode provide us a VBT that has 18
3861 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3862 * unknown we fail to light up. Yet the same BIOS boots up with
3863 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3864 * max, not what it tells us to use.
3865 *
3866 * Note: This will still be broken if the eDP panel is not lit
3867 * up by the BIOS, and thus we can't get the mode at module
3868 * load.
3869 */
3870 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 3871 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3872 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 3873 }
11578553 3874
22606a18 3875 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae 3876
cc3f90f0 3877 if (IS_GEN9_LP(dev_priv))
95a7a2ae
ID		 3878 pipe_config->lane_lat_optim_mask =
3879 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
53e9bf5e
VS		 3880
3881 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
f2a10d61
VS		 3882
3883 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3884
3885 intel_read_infoframe(encoder, pipe_config,
3886 HDMI_INFOFRAME_TYPE_AVI,
3887 &pipe_config->infoframes.avi);
3888 intel_read_infoframe(encoder, pipe_config,
3889 HDMI_INFOFRAME_TYPE_SPD,
3890 &pipe_config->infoframes.spd);
3891 intel_read_infoframe(encoder, pipe_config,
3892 HDMI_INFOFRAME_TYPE_VENDOR,
3893 &pipe_config->infoframes.hdmi);
b37f588e
US		 3894 intel_read_infoframe(encoder, pipe_config,
3895 HDMI_INFOFRAME_TYPE_DRM,
3896 &pipe_config->infoframes.drm);
045ac3b5
JB		 3897}
3898
7e732cac
VS		 3899static enum intel_output_type
3900intel_ddi_compute_output_type(struct intel_encoder *encoder,
3901 struct intel_crtc_state *crtc_state,
3902 struct drm_connector_state *conn_state)
3903{
3904 switch (conn_state->connector->connector_type) {
3905 case DRM_MODE_CONNECTOR_HDMIA:
3906 return INTEL_OUTPUT_HDMI;
3907 case DRM_MODE_CONNECTOR_eDP:
3908 return INTEL_OUTPUT_EDP;
3909 case DRM_MODE_CONNECTOR_DisplayPort:
3910 return INTEL_OUTPUT_DP;
3911 default:
3912 MISSING_CASE(conn_state->connector->connector_type);
3913 return INTEL_OUTPUT_UNUSED;
3914 }
3915}
3916
204474a6
LP		 3917static int intel_ddi_compute_config(struct intel_encoder *encoder,
3918 struct intel_crtc_state *pipe_config,
3919 struct drm_connector_state *conn_state)
00c09d70 3920{
dc0c0bfe 3921 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
fac5e23e 3922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0fce04c8 3923 enum port port = encoder->port;
95a7a2ae 3924 int ret;
00c09d70 3925
bc7e3525 3926 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
eccb140b
DV		 3927 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3928
7e732cac 3929 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
0a478c27 3930 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
00c09d70 3931 else
0a478c27 3932 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
7a412b8f
VS		 3933 if (ret)
3934 return ret;
95a7a2ae 3935
dc0c0bfe
VS		 3936 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3937 pipe_config->cpu_transcoder == TRANSCODER_EDP)
3938 pipe_config->pch_pfit.force_thru =
3939 pipe_config->pch_pfit.enabled ||
3940 pipe_config->crc_enabled;
3941
7a412b8f 3942 if (IS_GEN9_LP(dev_priv))
95a7a2ae 3943 pipe_config->lane_lat_optim_mask =
5161d058 3944 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
95a7a2ae 3945
53e9bf5e
VS		 3946 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3947
7a412b8f 3948 return 0;
00c09d70
PZ		 3949}
3950
f6bff60e
ID		 3951static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3952{
3953 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
f6bff60e
ID		 3954
3955 intel_dp_encoder_flush_work(encoder);
3956
f6bff60e
ID		 3957 drm_encoder_cleanup(encoder);
3958 kfree(dig_port);
3959}
3960
00c09d70 3961static const struct drm_encoder_funcs intel_ddi_funcs = {
32691b58 3962 .reset = intel_dp_encoder_reset,
f6bff60e 3963 .destroy = intel_ddi_encoder_destroy,
00c09d70
PZ		 3964};
3965
4a28ae58
PZ		 3966static struct intel_connector *
3967intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3968{
3969 struct intel_connector *connector;
8f4f2797 3970 enum port port = intel_dig_port->base.port;
4a28ae58 3971
9bdbd0b9 3972 connector = intel_connector_alloc();
4a28ae58
PZ		 3973 if (!connector)
3974 return NULL;
3975
3976 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
97068c1b
VS		 3977 intel_dig_port->dp.prepare_link_retrain =
3978 intel_ddi_prepare_link_retrain;
3979
4a28ae58
PZ		 3980 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3981 kfree(connector);
3982 return NULL;
3983 }
3984
3985 return connector;
3986}
3987
dba14b27
VS		 3988static int modeset_pipe(struct drm_crtc *crtc,
3989 struct drm_modeset_acquire_ctx *ctx)
3990{
3991 struct drm_atomic_state *state;
3992 struct drm_crtc_state *crtc_state;
3993 int ret;
3994
3995 state = drm_atomic_state_alloc(crtc->dev);
3996 if (!state)
3997 return -ENOMEM;
3998
3999 state->acquire_ctx = ctx;
4000
4001 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4002 if (IS_ERR(crtc_state)) {
4003 ret = PTR_ERR(crtc_state);
4004 goto out;
4005 }
4006
b8fe992a 4007 crtc_state->connectors_changed = true;
dba14b27 4008
dba14b27 4009 ret = drm_atomic_commit(state);
a551cd66 4010out:
dba14b27
VS		 4011 drm_atomic_state_put(state);
4012
4013 return ret;
4014}
4015
4016static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4017 struct drm_modeset_acquire_ctx *ctx)
4018{
4019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4020 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4021 struct intel_connector *connector = hdmi->attached_connector;
4022 struct i2c_adapter *adapter =
4023 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4024 struct drm_connector_state *conn_state;
4025 struct intel_crtc_state *crtc_state;
4026 struct intel_crtc *crtc;
4027 u8 config;
4028 int ret;
4029
4030 if (!connector || connector->base.status != connector_status_connected)
4031 return 0;
4032
4033 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4034 ctx);
4035 if (ret)
4036 return ret;
4037
4038 conn_state = connector->base.state;
4039
4040 crtc = to_intel_crtc(conn_state->crtc);
4041 if (!crtc)
4042 return 0;
4043
4044 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4045 if (ret)
4046 return ret;
4047
4048 crtc_state = to_intel_crtc_state(crtc->base.state);
4049
4050 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4051
4052 if (!crtc_state->base.active)
4053 return 0;
4054
4055 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4056 !crtc_state->hdmi_scrambling)
4057 return 0;
4058
4059 if (conn_state->commit &&
4060 !try_wait_for_completion(&conn_state->commit->hw_done))
4061 return 0;
4062
4063 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4064 if (ret < 0) {
4065 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4066 return 0;
4067 }
4068
4069 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4070 crtc_state->hdmi_high_tmds_clock_ratio &&
4071 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4072 crtc_state->hdmi_scrambling)
4073 return 0;
4074
4075 /*
4076 * HDMI 2.0 says that one should not send scrambled data
4077 * prior to configuring the sink scrambling, and that
4078 * TMDS clock/data transmission should be suspended when
4079 * changing the TMDS clock rate in the sink. So let's
4080 * just do a full modeset here, even though some sinks
4081 * would be perfectly happy if were to just reconfigure
4082 * the SCDC settings on the fly.
4083 */
4084 return modeset_pipe(&crtc->base, ctx);
4085}
4086
4087static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4088 struct intel_connector *connector)
4089{
4090 struct drm_modeset_acquire_ctx ctx;
4091 bool changed;
4092 int ret;
4093
4094 changed = intel_encoder_hotplug(encoder, connector);
4095
4096 drm_modeset_acquire_init(&ctx, 0);
4097
4098 for (;;) {
c85d200e
VS		 4099 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4100 ret = intel_hdmi_reset_link(encoder, &ctx);
4101 else
4102 ret = intel_dp_retrain_link(encoder, &ctx);
dba14b27
VS		 4103
4104 if (ret == -EDEADLK) {
4105 drm_modeset_backoff(&ctx);
4106 continue;
4107 }
4108
4109 break;
4110 }
4111
4112 drm_modeset_drop_locks(&ctx);
4113 drm_modeset_acquire_fini(&ctx);
4114 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4115
4116 return changed;
4117}
4118
4a28ae58
PZ		 4119static struct intel_connector *
4120intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4121{
4122 struct intel_connector *connector;
8f4f2797 4123 enum port port = intel_dig_port->base.port;
4a28ae58 4124
9bdbd0b9 4125 connector = intel_connector_alloc();
4a28ae58
PZ		 4126 if (!connector)
4127 return NULL;
4128
4129 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4130 intel_hdmi_init_connector(intel_dig_port, connector);
4131
4132 return connector;
4133}
4134
436009b5
RV		 4135static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4136{
4137 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4138
8f4f2797 4139 if (dport->base.port != PORT_A)
436009b5
RV		 4140 return false;
4141
4142 if (dport->saved_port_bits & DDI_A_4_LANES)
4143 return false;
4144
4145 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4146 * supported configuration
4147 */
4148 if (IS_GEN9_LP(dev_priv))
4149 return true;
4150
4151 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4152 * one who does also have a full A/E split called
4153 * DDI_F what makes DDI_E useless. However for this
4154 * case let's trust VBT info.
4155 */
4156 if (IS_CANNONLAKE(dev_priv) &&
4157 !intel_bios_is_port_present(dev_priv, PORT_E))
4158 return true;
4159
4160 return false;
4161}
4162
3d2011cf
MK		 4163static int
4164intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4165{
4166 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4167 enum port port = intel_dport->base.port;
4168 int max_lanes = 4;
4169
4170 if (INTEL_GEN(dev_priv) >= 11)
4171 return max_lanes;
4172
4173 if (port == PORT_A || port == PORT_E) {
4174 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4175 max_lanes = port == PORT_A ? 4 : 0;
4176 else
4177 /* Both A and E share 2 lanes */
4178 max_lanes = 2;
4179 }
4180
4181 /*
4182 * Some BIOS might fail to set this bit on port A if eDP
4183 * wasn't lit up at boot. Force this bit set when needed
4184 * so we use the proper lane count for our calculations.
4185 */
4186 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4187 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4188 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4189 max_lanes = 4;
4190 }
4191
4192 return max_lanes;
4193}
4194
c39055b0 4195void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
00c09d70 4196{
f6bff60e
ID		 4197 struct ddi_vbt_port_info *port_info =
4198 &dev_priv->vbt.ddi_port_info[port];
00c09d70
PZ		 4199 struct intel_digital_port *intel_dig_port;
4200 struct intel_encoder *intel_encoder;
4201 struct drm_encoder *encoder;
ff662124 4202 bool init_hdmi, init_dp, init_lspcon = false;
570b16b5 4203 enum pipe pipe;
10e7bec3 4204
f6bff60e
ID		 4205 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4206 init_dp = port_info->supports_dp;
ff662124
SS		 4207
4208 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4209 /*
4210 * Lspcon device needs to be driven with DP connector
4211 * with special detection sequence. So make sure DP
4212 * is initialized before lspcon.
4213 */
4214 init_dp = true;
4215 init_lspcon = true;
4216 init_hdmi = false;
4217 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4218 }
4219
311a2094 4220 if (!init_dp && !init_hdmi) {
500ea70d 4221 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 4222 port_name(port));
500ea70d 4223 return;
311a2094 4224 }
00c09d70 4225
b14c5679 4226 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 4227 if (!intel_dig_port)
4228 return;
4229
00c09d70
PZ		 4230 intel_encoder = &intel_dig_port->base;
4231 encoder = &intel_encoder->base;
4232
c39055b0 4233 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
580d8ed5 4234 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 4235
c85d200e 4236 intel_encoder->hotplug = intel_ddi_hotplug;
7e732cac 4237 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
5bfe2ac0 4238 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 4239 intel_encoder->enable = intel_enable_ddi;
bdaa29b6
ID		 4240 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4241 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
00c09d70
PZ		 4242 intel_encoder->pre_enable = intel_ddi_pre_enable;
4243 intel_encoder->disable = intel_disable_ddi;
4244 intel_encoder->post_disable = intel_ddi_post_disable;
2ef82327 4245 intel_encoder->update_pipe = intel_ddi_update_pipe;
00c09d70 4246 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 4247 intel_encoder->get_config = intel_ddi_get_config;
a171f8e7 4248 intel_encoder->suspend = intel_dp_encoder_suspend;
62b69566 4249 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3d2011cf
MK		 4250 intel_encoder->type = INTEL_OUTPUT_DDI;
4251 intel_encoder->power_domain = intel_port_to_power_domain(port);
4252 intel_encoder->port = port;
3d2011cf 4253 intel_encoder->cloneable = 0;
570b16b5
MK		 4254 for_each_pipe(dev_priv, pipe)
4255 intel_encoder->crtc_mask |= BIT(pipe);
00c09d70 4256
1e6aa7e5
JN		 4257 if (INTEL_GEN(dev_priv) >= 11)
4258 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4259 DDI_BUF_PORT_REVERSAL;
4260 else
4261 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4262 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3d2011cf
MK		 4263 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4264 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
39053089 4265 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
00c09d70 4266
ab7bc4e1
ID		 4267 if (intel_port_is_tc(dev_priv, port)) {
4268 bool is_legacy = !port_info->supports_typec_usb &&
4269 !port_info->supports_tbt;
4270
4271 intel_tc_port_init(intel_dig_port, is_legacy);
24a7bfe0
ID		 4272
4273 intel_encoder->update_prepare = intel_ddi_update_prepare;
4274 intel_encoder->update_complete = intel_ddi_update_complete;
ab7bc4e1 4275 }
f6bff60e 4276
62b69566
ACO		 4277 switch (port) {
4278 case PORT_A:
4279 intel_dig_port->ddi_io_power_domain =
4280 POWER_DOMAIN_PORT_DDI_A_IO;
4281 break;
4282 case PORT_B:
4283 intel_dig_port->ddi_io_power_domain =
4284 POWER_DOMAIN_PORT_DDI_B_IO;
4285 break;
4286 case PORT_C:
4287 intel_dig_port->ddi_io_power_domain =
4288 POWER_DOMAIN_PORT_DDI_C_IO;
4289 break;
4290 case PORT_D:
4291 intel_dig_port->ddi_io_power_domain =
4292 POWER_DOMAIN_PORT_DDI_D_IO;
4293 break;
4294 case PORT_E:
4295 intel_dig_port->ddi_io_power_domain =
4296 POWER_DOMAIN_PORT_DDI_E_IO;
4297 break;
9787e835
RV		 4298 case PORT_F:
4299 intel_dig_port->ddi_io_power_domain =
4300 POWER_DOMAIN_PORT_DDI_F_IO;
4301 break;
62b69566
ACO		 4302 default:
4303 MISSING_CASE(port);
4304 }
4305
f68d697e
CW		 4306 if (init_dp) {
4307 if (!intel_ddi_init_dp_connector(intel_dig_port))
4308 goto err;
13cf5504 4309
f68d697e 4310 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
f68d697e 4311 }
21a8e6a4 4312
311a2094
PZ		 4313 /* In theory we don't need the encoder->type check, but leave it just in
4314 * case we have some really bad VBTs... */
f68d697e
CW		 4315 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4316 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4317 goto err;
21a8e6a4 4318 }
f68d697e 4319
ff662124
SS		 4320 if (init_lspcon) {
4321 if (lspcon_init(intel_dig_port))
4322 /* TODO: handle hdmi info frame part */
4323 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4324 port_name(port));
4325 else
4326 /*
4327 * LSPCON init faied, but DP init was success, so
4328 * lets try to drive as DP++ port.
4329 */
4330 DRM_ERROR("LSPCON init failed on port %c\n",
4331 port_name(port));
4332 }
4333
06c812d7 4334 intel_infoframe_init(intel_dig_port);
f6bff60e 4335
f68d697e
CW		 4336 return;
4337
4338err:
4339 drm_encoder_cleanup(encoder);
4340 kfree(intel_dig_port);
00c09d70 4341}
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