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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
d0e93599 SR |
28 | #include <linux/input.h> |
29 | #include <linux/intel-iommu.h> | |
7662c8bd | 30 | #include <linux/kernel.h> |
d0e93599 | 31 | #include <linux/module.h> |
52791eee | 32 | #include <linux/dma-resv.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
d0e93599 | 34 | |
319c1d42 | 35 | #include <drm/drm_atomic.h> |
c196e1d6 | 36 | #include <drm/drm_atomic_helper.h> |
d0e93599 | 37 | #include <drm/drm_atomic_uapi.h> |
093a3a30 | 38 | #include <drm/drm_damage_helper.h> |
760285e7 | 39 | #include <drm/drm_dp_helper.h> |
d0e93599 SR |
40 | #include <drm/drm_edid.h> |
41 | #include <drm/drm_fourcc.h> | |
465c120c | 42 | #include <drm/drm_plane_helper.h> |
fcd70cd3 | 43 | #include <drm/drm_probe_helper.h> |
465c120c | 44 | #include <drm/drm_rect.h> |
d0e93599 | 45 | |
379bc100 JN |
46 | #include "display/intel_crt.h" |
47 | #include "display/intel_ddi.h" | |
48 | #include "display/intel_dp.h" | |
6671c367 | 49 | #include "display/intel_dp_mst.h" |
ddff9a60 | 50 | #include "display/intel_dpll_mgr.h" |
379bc100 JN |
51 | #include "display/intel_dsi.h" |
52 | #include "display/intel_dvo.h" | |
53 | #include "display/intel_gmbus.h" | |
54 | #include "display/intel_hdmi.h" | |
55 | #include "display/intel_lvds.h" | |
56 | #include "display/intel_sdvo.h" | |
57 | #include "display/intel_tv.h" | |
58 | #include "display/intel_vdsc.h" | |
59 | ||
3e7abf81 AS |
60 | #include "gt/intel_rps.h" |
61 | ||
d0e93599 | 62 | #include "i915_drv.h" |
d0e93599 | 63 | #include "i915_trace.h" |
4e49d35c | 64 | #include "intel_acpi.h" |
12392a74 | 65 | #include "intel_atomic.h" |
56dabc93 | 66 | #include "intel_atomic_plane.h" |
c457d9cf | 67 | #include "intel_bw.h" |
e7674ef6 | 68 | #include "intel_cdclk.h" |
1d455f8d | 69 | #include "intel_color.h" |
24d98a54 | 70 | #include "intel_csr.h" |
1d455f8d | 71 | #include "intel_display_types.h" |
3c954c41 | 72 | #include "intel_dp_link_training.h" |
98afa316 | 73 | #include "intel_fbc.h" |
6dfccb95 | 74 | #include "intel_fbdev.h" |
8834e365 | 75 | #include "intel_fifo_underrun.h" |
d0e93599 | 76 | #include "intel_frontbuffer.h" |
408bd917 | 77 | #include "intel_hdcp.h" |
dbeb38d9 | 78 | #include "intel_hotplug.h" |
05ca9306 | 79 | #include "intel_overlay.h" |
c6a35b9c | 80 | #include "intel_pipe_crc.h" |
696173b0 | 81 | #include "intel_pm.h" |
55367a27 | 82 | #include "intel_psr.h" |
220b92bf | 83 | #include "intel_quirks.h" |
56c5098f | 84 | #include "intel_sideband.h" |
f9a79f9a | 85 | #include "intel_sprite.h" |
32691b58 | 86 | #include "intel_tc.h" |
4fb87831 | 87 | #include "intel_vga.h" |
79e53945 | 88 | |
465c120c | 89 | /* Primary plane formats for gen <= 3 */ |
ba3f4d0a | 90 | static const u32 i8xx_primary_formats[] = { |
67fe7dc5 | 91 | DRM_FORMAT_C8, |
465c120c | 92 | DRM_FORMAT_XRGB1555, |
12fef149 | 93 | DRM_FORMAT_RGB565, |
67fe7dc5 | 94 | DRM_FORMAT_XRGB8888, |
465c120c MR |
95 | }; |
96 | ||
03b0ce95 VS |
97 | /* Primary plane formats for ivb (no fp16 due to hw issue) */ |
98 | static const u32 ivb_primary_formats[] = { | |
99 | DRM_FORMAT_C8, | |
100 | DRM_FORMAT_RGB565, | |
101 | DRM_FORMAT_XRGB8888, | |
102 | DRM_FORMAT_XBGR8888, | |
103 | DRM_FORMAT_XRGB2101010, | |
104 | DRM_FORMAT_XBGR2101010, | |
105 | }; | |
106 | ||
107 | /* Primary plane formats for gen >= 4, except ivb */ | |
ba3f4d0a | 108 | static const u32 i965_primary_formats[] = { |
6c0fd451 DL |
109 | DRM_FORMAT_C8, |
110 | DRM_FORMAT_RGB565, | |
111 | DRM_FORMAT_XRGB8888, | |
112 | DRM_FORMAT_XBGR8888, | |
113 | DRM_FORMAT_XRGB2101010, | |
114 | DRM_FORMAT_XBGR2101010, | |
03b0ce95 | 115 | DRM_FORMAT_XBGR16161616F, |
6c0fd451 DL |
116 | }; |
117 | ||
73263cb6 VS |
118 | /* Primary plane formats for vlv/chv */ |
119 | static const u32 vlv_primary_formats[] = { | |
120 | DRM_FORMAT_C8, | |
121 | DRM_FORMAT_RGB565, | |
122 | DRM_FORMAT_XRGB8888, | |
123 | DRM_FORMAT_XBGR8888, | |
124 | DRM_FORMAT_ARGB8888, | |
125 | DRM_FORMAT_ABGR8888, | |
126 | DRM_FORMAT_XRGB2101010, | |
127 | DRM_FORMAT_XBGR2101010, | |
128 | DRM_FORMAT_ARGB2101010, | |
129 | DRM_FORMAT_ABGR2101010, | |
130 | DRM_FORMAT_XBGR16161616F, | |
131 | }; | |
132 | ||
ba3f4d0a | 133 | static const u64 i9xx_format_modifiers[] = { |
714244e2 BW |
134 | I915_FORMAT_MOD_X_TILED, |
135 | DRM_FORMAT_MOD_LINEAR, | |
136 | DRM_FORMAT_MOD_INVALID | |
137 | }; | |
138 | ||
3d7d6510 | 139 | /* Cursor formats */ |
ba3f4d0a | 140 | static const u32 intel_cursor_formats[] = { |
3d7d6510 MR |
141 | DRM_FORMAT_ARGB8888, |
142 | }; | |
143 | ||
ba3f4d0a | 144 | static const u64 cursor_format_modifiers[] = { |
714244e2 BW |
145 | DRM_FORMAT_MOD_LINEAR, |
146 | DRM_FORMAT_MOD_INVALID | |
147 | }; | |
148 | ||
f1f644dc | 149 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 150 | struct intel_crtc_state *pipe_config); |
9eae5e27 LDM |
151 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
152 | struct intel_crtc_state *pipe_config); | |
f1f644dc | 153 | |
24dbf51a CW |
154 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
155 | struct drm_i915_gem_object *obj, | |
156 | struct drm_mode_fb_cmd2 *mode_cmd); | |
e7fc3f90 | 157 | static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); |
44fe7f35 | 158 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); |
4c354754 ML |
159 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
160 | const struct intel_link_m_n *m_n, | |
161 | const struct intel_link_m_n *m2_n2); | |
fdf73510 | 162 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); |
9eae5e27 | 163 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); |
1e98f88c | 164 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state); |
9b11215e | 165 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); |
d288f65f | 166 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 167 | const struct intel_crtc_state *pipe_config); |
d288f65f | 168 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 169 | const struct intel_crtc_state *pipe_config); |
f6df4d46 | 170 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state); |
9eae5e27 | 171 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); |
aecd36b8 VS |
172 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
173 | struct drm_modeset_acquire_ctx *ctx); | |
216383e9 | 174 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); |
e7457a9a | 175 | |
d4906093 | 176 | struct intel_limit { |
4c5def93 ACO |
177 | struct { |
178 | int min, max; | |
179 | } dot, vco, n, m, m1, m2, p, p1; | |
180 | ||
181 | struct { | |
182 | int dot_limit; | |
183 | int p2_slow, p2_fast; | |
184 | } p2; | |
d4906093 | 185 | }; |
79e53945 | 186 | |
bfa7df01 | 187 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 188 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
189 | { |
190 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
191 | ||
192 | /* Obtain SKU information */ | |
bfa7df01 VS |
193 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
194 | CCK_FUSE_HPLL_FREQ_MASK; | |
bfa7df01 VS |
195 | |
196 | return vco_freq[hpll_freq] * 1000; | |
197 | } | |
198 | ||
c30fec65 VS |
199 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
200 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
201 | { |
202 | u32 val; | |
203 | int divider; | |
204 | ||
bfa7df01 | 205 | val = vlv_cck_read(dev_priv, reg); |
bfa7df01 VS |
206 | divider = val & CCK_FREQUENCY_VALUES; |
207 | ||
e57291c2 PB |
208 | drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != |
209 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
210 | "%s change in progress\n", name); | |
bfa7df01 | 211 | |
c30fec65 VS |
212 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
213 | } | |
214 | ||
7ff89ca2 VS |
215 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
216 | const char *name, u32 reg) | |
c30fec65 | 217 | { |
337fa6e0 CW |
218 | int hpll; |
219 | ||
220 | vlv_cck_get(dev_priv); | |
221 | ||
c30fec65 | 222 | if (dev_priv->hpll_freq == 0) |
49cd97a3 | 223 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 | 224 | |
337fa6e0 CW |
225 | hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); |
226 | ||
227 | vlv_cck_put(dev_priv); | |
228 | ||
229 | return hpll; | |
bfa7df01 VS |
230 | } |
231 | ||
bfa7df01 VS |
232 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
233 | { | |
666a4537 | 234 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
235 | return; |
236 | ||
237 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
238 | CCK_CZ_CLOCK_CONTROL); | |
239 | ||
cd49f818 WK |
240 | drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", |
241 | dev_priv->czclk_freq); | |
bfa7df01 VS |
242 | } |
243 | ||
81b55ef1 JN |
244 | /* units of 100MHz */ |
245 | static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv, | |
246 | const struct intel_crtc_state *pipe_config) | |
021357ac | 247 | { |
21a727b3 VS |
248 | if (HAS_DDI(dev_priv)) |
249 | return pipe_config->port_clock; /* SPLL */ | |
e3b247da | 250 | else |
58ecd9d5 | 251 | return dev_priv->fdi_pll_freq; |
021357ac CW |
252 | } |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
265 | }; |
266 | ||
1b6f4958 | 267 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 268 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 269 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 270 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
271 | .m = { .min = 96, .max = 140 }, |
272 | .m1 = { .min = 18, .max = 26 }, | |
273 | .m2 = { .min = 6, .max = 16 }, | |
274 | .p = { .min = 4, .max = 128 }, | |
275 | .p1 = { .min = 2, .max = 33 }, | |
276 | .p2 = { .dot_limit = 165000, | |
277 | .p2_slow = 4, .p2_fast = 4 }, | |
278 | }; | |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 281 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 282 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 283 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
284 | .m = { .min = 96, .max = 140 }, |
285 | .m1 = { .min = 18, .max = 26 }, | |
286 | .m2 = { .min = 6, .max = 16 }, | |
287 | .p = { .min = 4, .max = 128 }, | |
288 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 165000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 291 | }; |
273e27ca | 292 | |
1b6f4958 | 293 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
294 | .dot = { .min = 20000, .max = 400000 }, |
295 | .vco = { .min = 1400000, .max = 2800000 }, | |
296 | .n = { .min = 1, .max = 6 }, | |
297 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
298 | .m1 = { .min = 8, .max = 18 }, |
299 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
300 | .p = { .min = 5, .max = 80 }, |
301 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
302 | .p2 = { .dot_limit = 200000, |
303 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
304 | }; |
305 | ||
1b6f4958 | 306 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
307 | .dot = { .min = 20000, .max = 400000 }, |
308 | .vco = { .min = 1400000, .max = 2800000 }, | |
309 | .n = { .min = 1, .max = 6 }, | |
310 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
311 | .m1 = { .min = 8, .max = 18 }, |
312 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
313 | .p = { .min = 7, .max = 98 }, |
314 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
315 | .p2 = { .dot_limit = 112000, |
316 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
317 | }; |
318 | ||
273e27ca | 319 | |
1b6f4958 | 320 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 270000 }, |
322 | .vco = { .min = 1750000, .max = 3500000}, | |
323 | .n = { .min = 1, .max = 4 }, | |
324 | .m = { .min = 104, .max = 138 }, | |
325 | .m1 = { .min = 17, .max = 23 }, | |
326 | .m2 = { .min = 5, .max = 11 }, | |
327 | .p = { .min = 10, .max = 30 }, | |
328 | .p1 = { .min = 1, .max = 3}, | |
329 | .p2 = { .dot_limit = 270000, | |
330 | .p2_slow = 10, | |
331 | .p2_fast = 10 | |
044c7c41 | 332 | }, |
e4b36699 KP |
333 | }; |
334 | ||
1b6f4958 | 335 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
336 | .dot = { .min = 22000, .max = 400000 }, |
337 | .vco = { .min = 1750000, .max = 3500000}, | |
338 | .n = { .min = 1, .max = 4 }, | |
339 | .m = { .min = 104, .max = 138 }, | |
340 | .m1 = { .min = 16, .max = 23 }, | |
341 | .m2 = { .min = 5, .max = 11 }, | |
342 | .p = { .min = 5, .max = 80 }, | |
343 | .p1 = { .min = 1, .max = 8}, | |
344 | .p2 = { .dot_limit = 165000, | |
345 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
346 | }; |
347 | ||
1b6f4958 | 348 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
349 | .dot = { .min = 20000, .max = 115000 }, |
350 | .vco = { .min = 1750000, .max = 3500000 }, | |
351 | .n = { .min = 1, .max = 3 }, | |
352 | .m = { .min = 104, .max = 138 }, | |
353 | .m1 = { .min = 17, .max = 23 }, | |
354 | .m2 = { .min = 5, .max = 11 }, | |
355 | .p = { .min = 28, .max = 112 }, | |
356 | .p1 = { .min = 2, .max = 8 }, | |
357 | .p2 = { .dot_limit = 0, | |
358 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 359 | }, |
e4b36699 KP |
360 | }; |
361 | ||
1b6f4958 | 362 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
363 | .dot = { .min = 80000, .max = 224000 }, |
364 | .vco = { .min = 1750000, .max = 3500000 }, | |
365 | .n = { .min = 1, .max = 3 }, | |
366 | .m = { .min = 104, .max = 138 }, | |
367 | .m1 = { .min = 17, .max = 23 }, | |
368 | .m2 = { .min = 5, .max = 11 }, | |
369 | .p = { .min = 14, .max = 42 }, | |
370 | .p1 = { .min = 2, .max = 6 }, | |
371 | .p2 = { .dot_limit = 0, | |
372 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 373 | }, |
e4b36699 KP |
374 | }; |
375 | ||
1d218220 | 376 | static const struct intel_limit pnv_limits_sdvo = { |
0206e353 AJ |
377 | .dot = { .min = 20000, .max = 400000}, |
378 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 379 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
380 | .n = { .min = 3, .max = 6 }, |
381 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 382 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
383 | .m1 = { .min = 0, .max = 0 }, |
384 | .m2 = { .min = 0, .max = 254 }, | |
385 | .p = { .min = 5, .max = 80 }, | |
386 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
387 | .p2 = { .dot_limit = 200000, |
388 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
389 | }; |
390 | ||
1d218220 | 391 | static const struct intel_limit pnv_limits_lvds = { |
0206e353 AJ |
392 | .dot = { .min = 20000, .max = 400000 }, |
393 | .vco = { .min = 1700000, .max = 3500000 }, | |
394 | .n = { .min = 3, .max = 6 }, | |
395 | .m = { .min = 2, .max = 256 }, | |
396 | .m1 = { .min = 0, .max = 0 }, | |
397 | .m2 = { .min = 0, .max = 254 }, | |
398 | .p = { .min = 7, .max = 112 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
400 | .p2 = { .dot_limit = 112000, |
401 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
402 | }; |
403 | ||
273e27ca EA |
404 | /* Ironlake / Sandybridge |
405 | * | |
406 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
407 | * the range value for them is (actual_value - 2). | |
408 | */ | |
9eae5e27 | 409 | static const struct intel_limit ilk_limits_dac = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 5 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 5, .max = 80 }, | |
417 | .p1 = { .min = 1, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
420 | }; |
421 | ||
9eae5e27 | 422 | static const struct intel_limit ilk_limits_single_lvds = { |
273e27ca EA |
423 | .dot = { .min = 25000, .max = 350000 }, |
424 | .vco = { .min = 1760000, .max = 3510000 }, | |
425 | .n = { .min = 1, .max = 3 }, | |
426 | .m = { .min = 79, .max = 118 }, | |
427 | .m1 = { .min = 12, .max = 22 }, | |
428 | .m2 = { .min = 5, .max = 9 }, | |
429 | .p = { .min = 28, .max = 112 }, | |
430 | .p1 = { .min = 2, .max = 8 }, | |
431 | .p2 = { .dot_limit = 225000, | |
432 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
433 | }; |
434 | ||
9eae5e27 | 435 | static const struct intel_limit ilk_limits_dual_lvds = { |
273e27ca EA |
436 | .dot = { .min = 25000, .max = 350000 }, |
437 | .vco = { .min = 1760000, .max = 3510000 }, | |
438 | .n = { .min = 1, .max = 3 }, | |
439 | .m = { .min = 79, .max = 127 }, | |
440 | .m1 = { .min = 12, .max = 22 }, | |
441 | .m2 = { .min = 5, .max = 9 }, | |
442 | .p = { .min = 14, .max = 56 }, | |
443 | .p1 = { .min = 2, .max = 8 }, | |
444 | .p2 = { .dot_limit = 225000, | |
445 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
446 | }; |
447 | ||
273e27ca | 448 | /* LVDS 100mhz refclk limits. */ |
9eae5e27 | 449 | static const struct intel_limit ilk_limits_single_lvds_100m = { |
273e27ca EA |
450 | .dot = { .min = 25000, .max = 350000 }, |
451 | .vco = { .min = 1760000, .max = 3510000 }, | |
452 | .n = { .min = 1, .max = 2 }, | |
453 | .m = { .min = 79, .max = 126 }, | |
454 | .m1 = { .min = 12, .max = 22 }, | |
455 | .m2 = { .min = 5, .max = 9 }, | |
456 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 457 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
458 | .p2 = { .dot_limit = 225000, |
459 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
460 | }; |
461 | ||
9eae5e27 | 462 | static const struct intel_limit ilk_limits_dual_lvds_100m = { |
273e27ca EA |
463 | .dot = { .min = 25000, .max = 350000 }, |
464 | .vco = { .min = 1760000, .max = 3510000 }, | |
465 | .n = { .min = 1, .max = 3 }, | |
466 | .m = { .min = 79, .max = 126 }, | |
467 | .m1 = { .min = 12, .max = 22 }, | |
468 | .m2 = { .min = 5, .max = 9 }, | |
469 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 470 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
471 | .p2 = { .dot_limit = 225000, |
472 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
473 | }; |
474 | ||
1b6f4958 | 475 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
476 | /* |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 483 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 484 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
485 | .m1 = { .min = 2, .max = 3 }, |
486 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 487 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 488 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
489 | }; |
490 | ||
1b6f4958 | 491 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
492 | /* |
493 | * These are the data rate limits (measured in fast clocks) | |
494 | * since those are the strictest limits we have. The fast | |
495 | * clock and actual rate limits are more relaxed, so checking | |
496 | * them would make no difference. | |
497 | */ | |
498 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 499 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
500 | .n = { .min = 1, .max = 1 }, |
501 | .m1 = { .min = 2, .max = 2 }, | |
502 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
503 | .p1 = { .min = 2, .max = 4 }, | |
504 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
505 | }; | |
506 | ||
1b6f4958 | 507 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
508 | /* FIXME: find real dot limits */ |
509 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 510 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
511 | .n = { .min = 1, .max = 1 }, |
512 | .m1 = { .min = 2, .max = 2 }, | |
513 | /* FIXME: find real m2 limits */ | |
514 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
515 | .p1 = { .min = 2, .max = 4 }, | |
516 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
517 | }; | |
518 | ||
51eb1a1d | 519 | /* WA Display #0827: Gen9:all */ |
c4a4efa9 | 520 | static void |
d048a268 | 521 | skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) |
c4a4efa9 | 522 | { |
c4a4efa9 | 523 | if (enable) |
dc008bf0 JN |
524 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
525 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); | |
c4a4efa9 | 526 | else |
dc008bf0 JN |
527 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
528 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); | |
c4a4efa9 VS |
529 | } |
530 | ||
f96198ab | 531 | /* Wa_2006604312:icl,ehl */ |
51eb1a1d RS |
532 | static void |
533 | icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, | |
534 | bool enable) | |
535 | { | |
536 | if (enable) | |
dc008bf0 JN |
537 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
538 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); | |
51eb1a1d | 539 | else |
dc008bf0 JN |
540 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
541 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); | |
51eb1a1d RS |
542 | } |
543 | ||
cdba954e | 544 | static bool |
69f786ae | 545 | needs_modeset(const struct intel_crtc_state *state) |
cdba954e | 546 | { |
2225f3c6 | 547 | return drm_atomic_crtc_needs_modeset(&state->uapi); |
cdba954e ACO |
548 | } |
549 | ||
d82a855a VS |
550 | static bool |
551 | is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) | |
bfb926e3 | 552 | { |
d82a855a | 553 | return crtc_state->master_transcoder != INVALID_TRANSCODER; |
bfb926e3 MN |
554 | } |
555 | ||
ad457191 | 556 | static bool |
d82a855a | 557 | is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) |
ad457191 | 558 | { |
d82a855a VS |
559 | return crtc_state->sync_mode_slaves_mask != 0; |
560 | } | |
561 | ||
562 | bool | |
563 | is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) | |
564 | { | |
565 | return is_trans_port_sync_master(crtc_state) || | |
566 | is_trans_port_sync_slave(crtc_state); | |
ad457191 JRS |
567 | } |
568 | ||
dccbea3b ID |
569 | /* |
570 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
571 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
572 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
573 | * The helpers' return value is the rate of the clock that is fed to the | |
574 | * display engine's pipe which can be the above fast dot clock rate or a | |
575 | * divided-down version of it. | |
576 | */ | |
f2b115e6 | 577 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 578 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 579 | { |
2177832f SL |
580 | clock->m = clock->m2 + 2; |
581 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 582 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 583 | return 0; |
fb03ac01 VS |
584 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
585 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
586 | |
587 | return clock->dot; | |
2177832f SL |
588 | } |
589 | ||
ba3f4d0a | 590 | static u32 i9xx_dpll_compute_m(struct dpll *dpll) |
7429e9d4 DV |
591 | { |
592 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
593 | } | |
594 | ||
9e2c8475 | 595 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 596 | { |
7429e9d4 | 597 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 598 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 599 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 600 | return 0; |
fb03ac01 VS |
601 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
602 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
603 | |
604 | return clock->dot; | |
79e53945 JB |
605 | } |
606 | ||
9e2c8475 | 607 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
608 | { |
609 | clock->m = clock->m1 * clock->m2; | |
610 | clock->p = clock->p1 * clock->p2; | |
611 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 612 | return 0; |
589eca67 ID |
613 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
614 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
615 | |
616 | return clock->dot / 5; | |
589eca67 ID |
617 | } |
618 | ||
9e2c8475 | 619 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
620 | { |
621 | clock->m = clock->m1 * clock->m2; | |
622 | clock->p = clock->p1 * clock->p2; | |
623 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 624 | return 0; |
d492a29d | 625 | clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), |
ba3f4d0a | 626 | clock->n << 22); |
ef9348c8 | 627 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
dccbea3b ID |
628 | |
629 | return clock->dot / 5; | |
ef9348c8 CML |
630 | } |
631 | ||
c38c1455 | 632 | /* |
79e53945 JB |
633 | * Returns whether the given set of divisors are valid for a given refclk with |
634 | * the given connectors. | |
635 | */ | |
4fb5eec9 | 636 | static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 637 | const struct intel_limit *limit, |
9e2c8475 | 638 | const struct dpll *clock) |
79e53945 | 639 | { |
4fb5eec9 JN |
640 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
641 | return false; | |
642 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
643 | return false; | |
644 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
645 | return false; | |
646 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
647 | return false; | |
f01b7962 | 648 | |
e2d214ae | 649 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 650 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 | 651 | if (clock->m1 <= clock->m2) |
4fb5eec9 | 652 | return false; |
f01b7962 | 653 | |
e2d214ae | 654 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 655 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 | 656 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
4fb5eec9 | 657 | return false; |
f01b7962 | 658 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
4fb5eec9 | 659 | return false; |
f01b7962 VS |
660 | } |
661 | ||
79e53945 | 662 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
4fb5eec9 | 663 | return false; |
79e53945 JB |
664 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
665 | * connector, etc., rather than just a single range. | |
666 | */ | |
667 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
4fb5eec9 | 668 | return false; |
79e53945 JB |
669 | |
670 | return true; | |
671 | } | |
672 | ||
3b1429d9 | 673 | static int |
1b6f4958 | 674 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
675 | const struct intel_crtc_state *crtc_state, |
676 | int target) | |
79e53945 | 677 | { |
2225f3c6 | 678 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
79e53945 | 679 | |
2d84d2b3 | 680 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 681 | /* |
a210b028 DV |
682 | * For LVDS just rely on its current settings for dual-channel. |
683 | * We haven't figured out how to reliably set up different | |
684 | * single/dual channel state, if we even can. | |
79e53945 | 685 | */ |
d2daff2c | 686 | if (intel_is_dual_link_lvds(dev_priv)) |
3b1429d9 | 687 | return limit->p2.p2_fast; |
79e53945 | 688 | else |
3b1429d9 | 689 | return limit->p2.p2_slow; |
79e53945 JB |
690 | } else { |
691 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 692 | return limit->p2.p2_slow; |
79e53945 | 693 | else |
3b1429d9 | 694 | return limit->p2.p2_fast; |
79e53945 | 695 | } |
3b1429d9 VS |
696 | } |
697 | ||
70e8aa21 ACO |
698 | /* |
699 | * Returns a set of divisors for the desired target clock with the given | |
700 | * refclk, or FALSE. The returned values represent the clock equation: | |
701 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
702 | * | |
703 | * Target and reference clocks are specified in kHz. | |
704 | * | |
705 | * If match_clock is provided, then best_clock P divider must match the P | |
706 | * divider from @match_clock used for LVDS downclocking. | |
707 | */ | |
3b1429d9 | 708 | static bool |
1b6f4958 | 709 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 710 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
711 | int target, int refclk, struct dpll *match_clock, |
712 | struct dpll *best_clock) | |
3b1429d9 | 713 | { |
2225f3c6 | 714 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 715 | struct dpll clock; |
3b1429d9 | 716 | int err = target; |
79e53945 | 717 | |
0206e353 | 718 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 719 | |
3b1429d9 VS |
720 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
721 | ||
42158660 ZY |
722 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
723 | clock.m1++) { | |
724 | for (clock.m2 = limit->m2.min; | |
725 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 726 | if (clock.m2 >= clock.m1) |
42158660 ZY |
727 | break; |
728 | for (clock.n = limit->n.min; | |
729 | clock.n <= limit->n.max; clock.n++) { | |
730 | for (clock.p1 = limit->p1.min; | |
731 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
732 | int this_err; |
733 | ||
dccbea3b | 734 | i9xx_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 735 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 736 | limit, |
ac58c3f0 DV |
737 | &clock)) |
738 | continue; | |
739 | if (match_clock && | |
740 | clock.p != match_clock->p) | |
741 | continue; | |
742 | ||
743 | this_err = abs(clock.dot - target); | |
744 | if (this_err < err) { | |
745 | *best_clock = clock; | |
746 | err = this_err; | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
751 | } | |
752 | ||
753 | return (err != target); | |
754 | } | |
755 | ||
70e8aa21 ACO |
756 | /* |
757 | * Returns a set of divisors for the desired target clock with the given | |
758 | * refclk, or FALSE. The returned values represent the clock equation: | |
759 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
760 | * | |
761 | * Target and reference clocks are specified in kHz. | |
762 | * | |
763 | * If match_clock is provided, then best_clock P divider must match the P | |
764 | * divider from @match_clock used for LVDS downclocking. | |
765 | */ | |
ac58c3f0 | 766 | static bool |
1b6f4958 | 767 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 768 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
769 | int target, int refclk, struct dpll *match_clock, |
770 | struct dpll *best_clock) | |
79e53945 | 771 | { |
2225f3c6 | 772 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 773 | struct dpll clock; |
79e53945 JB |
774 | int err = target; |
775 | ||
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
784 | for (clock.n = limit->n.min; |
785 | clock.n <= limit->n.max; clock.n++) { | |
786 | for (clock.p1 = limit->p1.min; | |
787 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
788 | int this_err; |
789 | ||
dccbea3b | 790 | pnv_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 791 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 792 | limit, |
1b894b59 | 793 | &clock)) |
79e53945 | 794 | continue; |
cec2f356 SP |
795 | if (match_clock && |
796 | clock.p != match_clock->p) | |
797 | continue; | |
79e53945 JB |
798 | |
799 | this_err = abs(clock.dot - target); | |
800 | if (this_err < err) { | |
801 | *best_clock = clock; | |
802 | err = this_err; | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
809 | return (err != target); | |
810 | } | |
811 | ||
997c030c ACO |
812 | /* |
813 | * Returns a set of divisors for the desired target clock with the given | |
814 | * refclk, or FALSE. The returned values represent the clock equation: | |
815 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
816 | * |
817 | * Target and reference clocks are specified in kHz. | |
818 | * | |
819 | * If match_clock is provided, then best_clock P divider must match the P | |
820 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 821 | */ |
d4906093 | 822 | static bool |
1b6f4958 | 823 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 824 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
825 | int target, int refclk, struct dpll *match_clock, |
826 | struct dpll *best_clock) | |
d4906093 | 827 | { |
2225f3c6 | 828 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 829 | struct dpll clock; |
d4906093 | 830 | int max_n; |
3b1429d9 | 831 | bool found = false; |
6ba770dc AJ |
832 | /* approximately equals target * 0.00585 */ |
833 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
834 | |
835 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
836 | |
837 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
838 | ||
d4906093 | 839 | max_n = limit->n.max; |
f77f13e2 | 840 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 841 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 842 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
843 | for (clock.m1 = limit->m1.max; |
844 | clock.m1 >= limit->m1.min; clock.m1--) { | |
845 | for (clock.m2 = limit->m2.max; | |
846 | clock.m2 >= limit->m2.min; clock.m2--) { | |
847 | for (clock.p1 = limit->p1.max; | |
848 | clock.p1 >= limit->p1.min; clock.p1--) { | |
849 | int this_err; | |
850 | ||
dccbea3b | 851 | i9xx_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 852 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 853 | limit, |
1b894b59 | 854 | &clock)) |
d4906093 | 855 | continue; |
1b894b59 CW |
856 | |
857 | this_err = abs(clock.dot - target); | |
d4906093 ML |
858 | if (this_err < err_most) { |
859 | *best_clock = clock; | |
860 | err_most = this_err; | |
861 | max_n = clock.n; | |
862 | found = true; | |
863 | } | |
864 | } | |
865 | } | |
866 | } | |
867 | } | |
2c07245f ZW |
868 | return found; |
869 | } | |
870 | ||
d5dd62bd ID |
871 | /* |
872 | * Check if the calculated PLL configuration is more optimal compared to the | |
873 | * best configuration and error found so far. Return the calculated error. | |
874 | */ | |
875 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
876 | const struct dpll *calculated_clock, |
877 | const struct dpll *best_clock, | |
d5dd62bd ID |
878 | unsigned int best_error_ppm, |
879 | unsigned int *error_ppm) | |
880 | { | |
9ca3ba01 ID |
881 | /* |
882 | * For CHV ignore the error and consider only the P value. | |
883 | * Prefer a bigger P value based on HW requirements. | |
884 | */ | |
920a14b2 | 885 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
886 | *error_ppm = 0; |
887 | ||
888 | return calculated_clock->p > best_clock->p; | |
889 | } | |
890 | ||
e57291c2 | 891 | if (drm_WARN_ON_ONCE(dev, !target_freq)) |
24be4e46 ID |
892 | return false; |
893 | ||
d5dd62bd ID |
894 | *error_ppm = div_u64(1000000ULL * |
895 | abs(target_freq - calculated_clock->dot), | |
896 | target_freq); | |
897 | /* | |
898 | * Prefer a better P value over a better (smaller) error if the error | |
899 | * is small. Ensure this preference for future configurations too by | |
900 | * setting the error to 0. | |
901 | */ | |
902 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
903 | *error_ppm = 0; | |
904 | ||
905 | return true; | |
906 | } | |
907 | ||
908 | return *error_ppm + 10 < best_error_ppm; | |
909 | } | |
910 | ||
65b3d6a9 ACO |
911 | /* |
912 | * Returns a set of divisors for the desired target clock with the given | |
913 | * refclk, or FALSE. The returned values represent the clock equation: | |
914 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
915 | */ | |
a0c4da24 | 916 | static bool |
1b6f4958 | 917 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 918 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
919 | int target, int refclk, struct dpll *match_clock, |
920 | struct dpll *best_clock) | |
a0c4da24 | 921 | { |
2225f3c6 | 922 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a919ff14 | 923 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 924 | struct dpll clock; |
69e4f900 | 925 | unsigned int bestppm = 1000000; |
27e639bf VS |
926 | /* min update 19.2 MHz */ |
927 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 928 | bool found = false; |
a0c4da24 | 929 | |
6b4bf1c4 VS |
930 | target *= 5; /* fast clock */ |
931 | ||
932 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
933 | |
934 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 935 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 936 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 937 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 938 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 939 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 940 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 941 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 942 | unsigned int ppm; |
69e4f900 | 943 | |
6b4bf1c4 VS |
944 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
945 | refclk * clock.m1); | |
946 | ||
dccbea3b | 947 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 948 | |
4fb5eec9 | 949 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 950 | limit, |
f01b7962 | 951 | &clock)) |
43b0ac53 VS |
952 | continue; |
953 | ||
d5dd62bd ID |
954 | if (!vlv_PLL_is_optimal(dev, target, |
955 | &clock, | |
956 | best_clock, | |
957 | bestppm, &ppm)) | |
958 | continue; | |
6b4bf1c4 | 959 | |
d5dd62bd ID |
960 | *best_clock = clock; |
961 | bestppm = ppm; | |
962 | found = true; | |
a0c4da24 JB |
963 | } |
964 | } | |
965 | } | |
966 | } | |
a0c4da24 | 967 | |
49e497ef | 968 | return found; |
a0c4da24 | 969 | } |
a4fc5ed6 | 970 | |
65b3d6a9 ACO |
971 | /* |
972 | * Returns a set of divisors for the desired target clock with the given | |
973 | * refclk, or FALSE. The returned values represent the clock equation: | |
974 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
975 | */ | |
ef9348c8 | 976 | static bool |
1b6f4958 | 977 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 978 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
979 | int target, int refclk, struct dpll *match_clock, |
980 | struct dpll *best_clock) | |
ef9348c8 | 981 | { |
2225f3c6 | 982 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a919ff14 | 983 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 984 | unsigned int best_error_ppm; |
9e2c8475 | 985 | struct dpll clock; |
ba3f4d0a | 986 | u64 m2; |
ef9348c8 CML |
987 | int found = false; |
988 | ||
989 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 990 | best_error_ppm = 1000000; |
ef9348c8 CML |
991 | |
992 | /* | |
993 | * Based on hardware doc, the n always set to 1, and m1 always | |
994 | * set to 2. If requires to support 200Mhz refclk, we need to | |
995 | * revisit this because n may not 1 anymore. | |
996 | */ | |
997 | clock.n = 1, clock.m1 = 2; | |
998 | target *= 5; /* fast clock */ | |
999 | ||
1000 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1001 | for (clock.p2 = limit->p2.p2_fast; | |
1002 | clock.p2 >= limit->p2.p2_slow; | |
1003 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1004 | unsigned int error_ppm; |
ef9348c8 CML |
1005 | |
1006 | clock.p = clock.p1 * clock.p2; | |
1007 | ||
d492a29d VS |
1008 | m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, |
1009 | refclk * clock.m1); | |
ef9348c8 CML |
1010 | |
1011 | if (m2 > INT_MAX/clock.m1) | |
1012 | continue; | |
1013 | ||
1014 | clock.m2 = m2; | |
1015 | ||
dccbea3b | 1016 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 1017 | |
4fb5eec9 | 1018 | if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
1019 | continue; |
1020 | ||
9ca3ba01 ID |
1021 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1022 | best_error_ppm, &error_ppm)) | |
1023 | continue; | |
1024 | ||
1025 | *best_clock = clock; | |
1026 | best_error_ppm = error_ppm; | |
1027 | found = true; | |
ef9348c8 CML |
1028 | } |
1029 | } | |
1030 | ||
1031 | return found; | |
1032 | } | |
1033 | ||
e40396d0 | 1034 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
9e2c8475 | 1035 | struct dpll *best_clock) |
5ab7b0b7 | 1036 | { |
65b3d6a9 | 1037 | int refclk = 100000; |
1b6f4958 | 1038 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1039 | |
65b3d6a9 | 1040 | return chv_find_best_dpll(limit, crtc_state, |
e40396d0 VS |
1041 | crtc_state->port_clock, refclk, |
1042 | NULL, best_clock); | |
5ab7b0b7 ID |
1043 | } |
1044 | ||
8fedd64d VS |
1045 | static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe) | |
fbf49ea2 | 1047 | { |
f0f59a00 | 1048 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1049 | u32 line1, line2; |
1050 | u32 line_mask; | |
1051 | ||
cf819eff | 1052 | if (IS_GEN(dev_priv, 2)) |
fbf49ea2 VS |
1053 | line_mask = DSL_LINEMASK_GEN2; |
1054 | else | |
1055 | line_mask = DSL_LINEMASK_GEN3; | |
1056 | ||
dc008bf0 | 1057 | line1 = intel_de_read(dev_priv, reg) & line_mask; |
6adfb1ef | 1058 | msleep(5); |
dc008bf0 | 1059 | line2 = intel_de_read(dev_priv, reg) & line_mask; |
fbf49ea2 | 1060 | |
8fedd64d VS |
1061 | return line1 != line2; |
1062 | } | |
1063 | ||
1064 | static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) | |
1065 | { | |
1066 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1067 | enum pipe pipe = crtc->pipe; | |
1068 | ||
1069 | /* Wait for the display line to settle/start moving */ | |
1070 | if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) | |
cd49f818 WK |
1071 | drm_err(&dev_priv->drm, |
1072 | "pipe %c scanline %s wait timed out\n", | |
1073 | pipe_name(pipe), onoff(state)); | |
8fedd64d VS |
1074 | } |
1075 | ||
1076 | static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) | |
1077 | { | |
1078 | wait_for_pipe_scanline_moving(crtc, false); | |
1079 | } | |
1080 | ||
1081 | static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) | |
1082 | { | |
1083 | wait_for_pipe_scanline_moving(crtc, true); | |
fbf49ea2 VS |
1084 | } |
1085 | ||
4972f70a VS |
1086 | static void |
1087 | intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) | |
9d0498a2 | 1088 | { |
2225f3c6 | 1089 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
6315b5d3 | 1090 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab7ad7f6 | 1091 | |
6315b5d3 | 1092 | if (INTEL_GEN(dev_priv) >= 4) { |
4972f70a | 1093 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
f0f59a00 | 1094 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1095 | |
1096 | /* Wait for the Pipe State to go off */ | |
4cb3b44d DCS |
1097 | if (intel_de_wait_for_clear(dev_priv, reg, |
1098 | I965_PIPECONF_ACTIVE, 100)) | |
e57291c2 PB |
1099 | drm_WARN(&dev_priv->drm, 1, |
1100 | "pipe_off wait timed out\n"); | |
ab7ad7f6 | 1101 | } else { |
8fedd64d | 1102 | intel_wait_for_pipe_scanline_stopped(crtc); |
ab7ad7f6 | 1103 | } |
79e53945 JB |
1104 | } |
1105 | ||
b24e7179 | 1106 | /* Only for pre-ILK configs */ |
55607e8a DV |
1107 | void assert_pll(struct drm_i915_private *dev_priv, |
1108 | enum pipe pipe, bool state) | |
b24e7179 | 1109 | { |
b24e7179 JB |
1110 | u32 val; |
1111 | bool cur_state; | |
1112 | ||
dc008bf0 | 1113 | val = intel_de_read(dev_priv, DPLL(pipe)); |
b24e7179 | 1114 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1115 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1116 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1117 | onoff(state), onoff(cur_state)); |
b24e7179 | 1118 | } |
b24e7179 | 1119 | |
23538ef1 | 1120 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1121 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1122 | { |
1123 | u32 val; | |
1124 | bool cur_state; | |
1125 | ||
221c7862 | 1126 | vlv_cck_get(dev_priv); |
23538ef1 | 1127 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
221c7862 | 1128 | vlv_cck_put(dev_priv); |
23538ef1 JN |
1129 | |
1130 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1131 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1132 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1133 | onoff(state), onoff(cur_state)); |
23538ef1 | 1134 | } |
23538ef1 | 1135 | |
040484af JB |
1136 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1137 | enum pipe pipe, bool state) | |
1138 | { | |
040484af JB |
1139 | bool cur_state; |
1140 | ||
2d1fe073 | 1141 | if (HAS_DDI(dev_priv)) { |
a722146b VS |
1142 | /* |
1143 | * DDI does not have a specific FDI_TX register. | |
1144 | * | |
1145 | * FDI is never fed from EDP transcoder | |
1146 | * so pipe->transcoder cast is fine here. | |
1147 | */ | |
1148 | enum transcoder cpu_transcoder = (enum transcoder)pipe; | |
dc008bf0 JN |
1149 | u32 val = intel_de_read(dev_priv, |
1150 | TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
ad80a810 | 1151 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1152 | } else { |
dc008bf0 | 1153 | u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1154 | cur_state = !!(val & FDI_TX_ENABLE); |
1155 | } | |
e2c719b7 | 1156 | I915_STATE_WARN(cur_state != state, |
040484af | 1157 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1158 | onoff(state), onoff(cur_state)); |
040484af JB |
1159 | } |
1160 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1161 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1162 | ||
1163 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1164 | enum pipe pipe, bool state) | |
1165 | { | |
040484af JB |
1166 | u32 val; |
1167 | bool cur_state; | |
1168 | ||
dc008bf0 | 1169 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); |
d63fa0dc | 1170 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1171 | I915_STATE_WARN(cur_state != state, |
040484af | 1172 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1173 | onoff(state), onoff(cur_state)); |
040484af JB |
1174 | } |
1175 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1176 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1177 | ||
1178 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1179 | enum pipe pipe) | |
1180 | { | |
040484af JB |
1181 | u32 val; |
1182 | ||
1183 | /* ILK FDI PLL is always enabled */ | |
cf819eff | 1184 | if (IS_GEN(dev_priv, 5)) |
040484af JB |
1185 | return; |
1186 | ||
bf507ef7 | 1187 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1188 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1189 | return; |
1190 | ||
dc008bf0 | 1191 | val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); |
e2c719b7 | 1192 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1193 | } |
1194 | ||
55607e8a DV |
1195 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
040484af | 1197 | { |
040484af | 1198 | u32 val; |
55607e8a | 1199 | bool cur_state; |
040484af | 1200 | |
dc008bf0 | 1201 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); |
55607e8a | 1202 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1203 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1204 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1205 | onoff(state), onoff(cur_state)); |
040484af JB |
1206 | } |
1207 | ||
4f8036a2 | 1208 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1209 | { |
f0f59a00 | 1210 | i915_reg_t pp_reg; |
ea0760cf | 1211 | u32 val; |
10ed55e4 | 1212 | enum pipe panel_pipe = INVALID_PIPE; |
0de3b485 | 1213 | bool locked = true; |
ea0760cf | 1214 | |
e57291c2 | 1215 | if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) |
bedd4dba JN |
1216 | return; |
1217 | ||
4f8036a2 | 1218 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1219 | u32 port_sel; |
1220 | ||
44cb734c | 1221 | pp_reg = PP_CONTROL(0); |
dc008bf0 | 1222 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; |
bedd4dba | 1223 | |
4c23dea4 VS |
1224 | switch (port_sel) { |
1225 | case PANEL_PORT_SELECT_LVDS: | |
a44628b9 | 1226 | intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe); |
4c23dea4 VS |
1227 | break; |
1228 | case PANEL_PORT_SELECT_DPA: | |
1229 | intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe); | |
1230 | break; | |
1231 | case PANEL_PORT_SELECT_DPC: | |
1232 | intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe); | |
1233 | break; | |
1234 | case PANEL_PORT_SELECT_DPD: | |
1235 | intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe); | |
1236 | break; | |
1237 | default: | |
1238 | MISSING_CASE(port_sel); | |
1239 | break; | |
1240 | } | |
4f8036a2 | 1241 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1242 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1243 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1244 | panel_pipe = pipe; |
ea0760cf | 1245 | } else { |
f0d2b758 VS |
1246 | u32 port_sel; |
1247 | ||
44cb734c | 1248 | pp_reg = PP_CONTROL(0); |
dc008bf0 | 1249 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; |
f0d2b758 | 1250 | |
e57291c2 PB |
1251 | drm_WARN_ON(&dev_priv->drm, |
1252 | port_sel != PANEL_PORT_SELECT_LVDS); | |
a44628b9 | 1253 | intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); |
ea0760cf JB |
1254 | } |
1255 | ||
dc008bf0 | 1256 | val = intel_de_read(dev_priv, pp_reg); |
ea0760cf | 1257 | if (!(val & PANEL_POWER_ON) || |
ec49ba2d | 1258 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1259 | locked = false; |
1260 | ||
e2c719b7 | 1261 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1262 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1263 | pipe_name(pipe)); |
ea0760cf JB |
1264 | } |
1265 | ||
b840d907 | 1266 | void assert_pipe(struct drm_i915_private *dev_priv, |
b104e8b2 | 1267 | enum transcoder cpu_transcoder, bool state) |
b24e7179 | 1268 | { |
63d7bbe9 | 1269 | bool cur_state; |
4feed0eb | 1270 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 1271 | intel_wakeref_t wakeref; |
b24e7179 | 1272 | |
e56134bc VS |
1273 | /* we keep both pipes enabled on 830 */ |
1274 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1275 | state = true; |
1276 | ||
4feed0eb | 1277 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
0e6e0be4 CW |
1278 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
1279 | if (wakeref) { | |
dc008bf0 | 1280 | u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); |
69310161 | 1281 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb | 1282 | |
0e6e0be4 | 1283 | intel_display_power_put(dev_priv, power_domain, wakeref); |
4feed0eb ID |
1284 | } else { |
1285 | cur_state = false; | |
69310161 PZ |
1286 | } |
1287 | ||
e2c719b7 | 1288 | I915_STATE_WARN(cur_state != state, |
b104e8b2 VS |
1289 | "transcoder %s assertion failure (expected %s, current %s)\n", |
1290 | transcoder_name(cpu_transcoder), | |
1291 | onoff(state), onoff(cur_state)); | |
b24e7179 JB |
1292 | } |
1293 | ||
51f5a096 | 1294 | static void assert_plane(struct intel_plane *plane, bool state) |
b24e7179 | 1295 | { |
eade6c89 VS |
1296 | enum pipe pipe; |
1297 | bool cur_state; | |
1298 | ||
1299 | cur_state = plane->get_hw_state(plane, &pipe); | |
b24e7179 | 1300 | |
e2c719b7 | 1301 | I915_STATE_WARN(cur_state != state, |
51f5a096 VS |
1302 | "%s assertion failure (expected %s, current %s)\n", |
1303 | plane->base.name, onoff(state), onoff(cur_state)); | |
b24e7179 JB |
1304 | } |
1305 | ||
51f5a096 VS |
1306 | #define assert_plane_enabled(p) assert_plane(p, true) |
1307 | #define assert_plane_disabled(p) assert_plane(p, false) | |
931872fc | 1308 | |
51f5a096 | 1309 | static void assert_planes_disabled(struct intel_crtc *crtc) |
b24e7179 | 1310 | { |
51f5a096 VS |
1311 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1312 | struct intel_plane *plane; | |
19332d7a | 1313 | |
51f5a096 VS |
1314 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) |
1315 | assert_plane_disabled(plane); | |
19332d7a JB |
1316 | } |
1317 | ||
08c71e5e VS |
1318 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1319 | { | |
e2c719b7 | 1320 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1321 | drm_crtc_vblank_put(crtc); |
1322 | } | |
1323 | ||
7abd4b35 ACO |
1324 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1325 | enum pipe pipe) | |
92f2584a | 1326 | { |
92f2584a JB |
1327 | u32 val; |
1328 | bool enabled; | |
1329 | ||
dc008bf0 | 1330 | val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); |
92f2584a | 1331 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1332 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1333 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1334 | pipe_name(pipe)); | |
92f2584a JB |
1335 | } |
1336 | ||
59b74c49 VS |
1337 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1338 | enum pipe pipe, enum port port, | |
1339 | i915_reg_t dp_reg) | |
f0575e92 | 1340 | { |
59b74c49 VS |
1341 | enum pipe port_pipe; |
1342 | bool state; | |
f0575e92 | 1343 | |
59b74c49 | 1344 | state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); |
f0575e92 | 1345 | |
59b74c49 VS |
1346 | I915_STATE_WARN(state && port_pipe == pipe, |
1347 | "PCH DP %c enabled on transcoder %c, should be disabled\n", | |
1348 | port_name(port), pipe_name(pipe)); | |
1349 | ||
1350 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, | |
1351 | "IBX PCH DP %c still using transcoder B\n", | |
1352 | port_name(port)); | |
291906f1 JB |
1353 | } |
1354 | ||
1355 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
76203467 VS |
1356 | enum pipe pipe, enum port port, |
1357 | i915_reg_t hdmi_reg) | |
291906f1 | 1358 | { |
76203467 VS |
1359 | enum pipe port_pipe; |
1360 | bool state; | |
1361 | ||
1362 | state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); | |
1363 | ||
1364 | I915_STATE_WARN(state && port_pipe == pipe, | |
1365 | "PCH HDMI %c enabled on transcoder %c, should be disabled\n", | |
1366 | port_name(port), pipe_name(pipe)); | |
de9a35ab | 1367 | |
76203467 VS |
1368 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, |
1369 | "IBX PCH HDMI %c still using transcoder B\n", | |
1370 | port_name(port)); | |
291906f1 JB |
1371 | } |
1372 | ||
1373 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1374 | enum pipe pipe) | |
1375 | { | |
6102a8ee | 1376 | enum pipe port_pipe; |
291906f1 | 1377 | |
59b74c49 VS |
1378 | assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); |
1379 | assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); | |
1380 | assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); | |
291906f1 | 1381 | |
6102a8ee VS |
1382 | I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && |
1383 | port_pipe == pipe, | |
1384 | "PCH VGA enabled on transcoder %c, should be disabled\n", | |
1385 | pipe_name(pipe)); | |
291906f1 | 1386 | |
a44628b9 VS |
1387 | I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && |
1388 | port_pipe == pipe, | |
1389 | "PCH LVDS enabled on transcoder %c, should be disabled\n", | |
1390 | pipe_name(pipe)); | |
291906f1 | 1391 | |
3aefb67f | 1392 | /* PCH SDVOB multiplex with HDMIB */ |
76203467 VS |
1393 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); |
1394 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); | |
1395 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); | |
291906f1 JB |
1396 | } |
1397 | ||
cd2d34d9 VS |
1398 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1399 | const struct intel_crtc_state *pipe_config) | |
1400 | { | |
1401 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1402 | enum pipe pipe = crtc->pipe; | |
1403 | ||
dc008bf0 JN |
1404 | intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
1405 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
cd2d34d9 VS |
1406 | udelay(150); |
1407 | ||
4cb3b44d | 1408 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) |
cd49f818 | 1409 | drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1410 | } |
1411 | ||
d288f65f | 1412 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1413 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1414 | { |
cd2d34d9 | 1415 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1416 | enum pipe pipe = crtc->pipe; |
87442f73 | 1417 | |
b104e8b2 | 1418 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
87442f73 | 1419 | |
87442f73 | 1420 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1421 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1422 | |
cd2d34d9 VS |
1423 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1424 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1425 | |
dc008bf0 JN |
1426 | intel_de_write(dev_priv, DPLL_MD(pipe), |
1427 | pipe_config->dpll_hw_state.dpll_md); | |
1428 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)); | |
87442f73 DV |
1429 | } |
1430 | ||
cd2d34d9 VS |
1431 | |
1432 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1433 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1434 | { |
cd2d34d9 | 1435 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1436 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1437 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1438 | u32 tmp; |
1439 | ||
221c7862 | 1440 | vlv_dpio_get(dev_priv); |
9d556c99 CML |
1441 | |
1442 | /* Enable back the 10bit clock to display controller */ | |
1443 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1444 | tmp |= DPIO_DCLKP_EN; | |
1445 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1446 | ||
221c7862 | 1447 | vlv_dpio_put(dev_priv); |
54433e91 | 1448 | |
9d556c99 CML |
1449 | /* |
1450 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1451 | */ | |
1452 | udelay(1); | |
1453 | ||
1454 | /* Enable PLL */ | |
dc008bf0 | 1455 | intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1456 | |
1457 | /* Check PLL is locked */ | |
4cb3b44d | 1458 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) |
cd49f818 | 1459 | drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1460 | } |
1461 | ||
1462 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1463 | const struct intel_crtc_state *pipe_config) | |
1464 | { | |
1465 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1466 | enum pipe pipe = crtc->pipe; | |
1467 | ||
b104e8b2 | 1468 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
cd2d34d9 VS |
1469 | |
1470 | /* PLL is protected by panel, make sure we can write it */ | |
1471 | assert_panel_unlocked(dev_priv, pipe); | |
1472 | ||
1473 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1474 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1475 | |
c231775c VS |
1476 | if (pipe != PIPE_A) { |
1477 | /* | |
1478 | * WaPixelRepeatModeFixForC0:chv | |
1479 | * | |
1480 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1481 | * the value from DPLLBMD to either pipe B or C. | |
1482 | */ | |
dc008bf0 JN |
1483 | intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); |
1484 | intel_de_write(dev_priv, DPLL_MD(PIPE_B), | |
1485 | pipe_config->dpll_hw_state.dpll_md); | |
1486 | intel_de_write(dev_priv, CBR4_VLV, 0); | |
c231775c VS |
1487 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; |
1488 | ||
1489 | /* | |
1490 | * DPLLB VGA mode also seems to cause problems. | |
1491 | * We should always have it disabled. | |
1492 | */ | |
e57291c2 PB |
1493 | drm_WARN_ON(&dev_priv->drm, |
1494 | (intel_de_read(dev_priv, DPLL(PIPE_B)) & | |
1495 | DPLL_VGA_MODE_DIS) == 0); | |
c231775c | 1496 | } else { |
dc008bf0 JN |
1497 | intel_de_write(dev_priv, DPLL_MD(pipe), |
1498 | pipe_config->dpll_hw_state.dpll_md); | |
1499 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)); | |
c231775c | 1500 | } |
9d556c99 CML |
1501 | } |
1502 | ||
9e7d5699 VS |
1503 | static bool i9xx_has_pps(struct drm_i915_private *dev_priv) |
1504 | { | |
1505 | if (IS_I830(dev_priv)) | |
1506 | return false; | |
1507 | ||
1508 | return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); | |
1509 | } | |
1510 | ||
939994da VS |
1511 | static void i9xx_enable_pll(struct intel_crtc *crtc, |
1512 | const struct intel_crtc_state *crtc_state) | |
63d7bbe9 | 1513 | { |
6315b5d3 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1515 | i915_reg_t reg = DPLL(crtc->pipe); |
939994da | 1516 | u32 dpll = crtc_state->dpll_hw_state.dpll; |
bb408dd2 | 1517 | int i; |
63d7bbe9 | 1518 | |
b104e8b2 | 1519 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
58c6eaa2 | 1520 | |
63d7bbe9 | 1521 | /* PLL is protected by panel, make sure we can write it */ |
9e7d5699 | 1522 | if (i9xx_has_pps(dev_priv)) |
66e3d5c0 | 1523 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1524 | |
c2b63374 VS |
1525 | /* |
1526 | * Apparently we need to have VGA mode enabled prior to changing | |
1527 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1528 | * dividers, even though the register value does change. | |
1529 | */ | |
dc008bf0 JN |
1530 | intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); |
1531 | intel_de_write(dev_priv, reg, dpll); | |
8e7a65aa | 1532 | |
66e3d5c0 | 1533 | /* Wait for the clocks to stabilize. */ |
dc008bf0 | 1534 | intel_de_posting_read(dev_priv, reg); |
66e3d5c0 DV |
1535 | udelay(150); |
1536 | ||
6315b5d3 | 1537 | if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
1538 | intel_de_write(dev_priv, DPLL_MD(crtc->pipe), |
1539 | crtc_state->dpll_hw_state.dpll_md); | |
66e3d5c0 DV |
1540 | } else { |
1541 | /* The pixel multiplier can only be updated once the | |
1542 | * DPLL is enabled and the clocks are stable. | |
1543 | * | |
1544 | * So write it again. | |
1545 | */ | |
dc008bf0 | 1546 | intel_de_write(dev_priv, reg, dpll); |
66e3d5c0 | 1547 | } |
63d7bbe9 JB |
1548 | |
1549 | /* We do this three times for luck */ | |
bb408dd2 | 1550 | for (i = 0; i < 3; i++) { |
dc008bf0 JN |
1551 | intel_de_write(dev_priv, reg, dpll); |
1552 | intel_de_posting_read(dev_priv, reg); | |
bb408dd2 VS |
1553 | udelay(150); /* wait for warmup */ |
1554 | } | |
63d7bbe9 JB |
1555 | } |
1556 | ||
b2354c78 | 1557 | static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) |
63d7bbe9 | 1558 | { |
2225f3c6 | 1559 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 1560 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1561 | enum pipe pipe = crtc->pipe; |
1562 | ||
b6b5d049 | 1563 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1564 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1565 | return; |
1566 | ||
1567 | /* Make sure the pipe isn't still relying on us */ | |
b104e8b2 | 1568 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
63d7bbe9 | 1569 | |
dc008bf0 JN |
1570 | intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); |
1571 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
63d7bbe9 JB |
1572 | } |
1573 | ||
f6071166 JB |
1574 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1575 | { | |
b8afb911 | 1576 | u32 val; |
f6071166 JB |
1577 | |
1578 | /* Make sure the pipe isn't still relying on us */ | |
b104e8b2 | 1579 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe); |
f6071166 | 1580 | |
03ed5cbf VS |
1581 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1582 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1583 | if (pipe != PIPE_A) | |
1584 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1585 | ||
dc008bf0 JN |
1586 | intel_de_write(dev_priv, DPLL(pipe), val); |
1587 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
076ed3b2 CML |
1588 | } |
1589 | ||
1590 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1591 | { | |
d752048d | 1592 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1593 | u32 val; |
1594 | ||
a11b0703 | 1595 | /* Make sure the pipe isn't still relying on us */ |
b104e8b2 | 1596 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe); |
076ed3b2 | 1597 | |
60bfe44f VS |
1598 | val = DPLL_SSC_REF_CLK_CHV | |
1599 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1600 | if (pipe != PIPE_A) |
1601 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1602 | |
dc008bf0 JN |
1603 | intel_de_write(dev_priv, DPLL(pipe), val); |
1604 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
d752048d | 1605 | |
221c7862 | 1606 | vlv_dpio_get(dev_priv); |
d752048d VS |
1607 | |
1608 | /* Disable 10bit clock to display controller */ | |
1609 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1610 | val &= ~DPIO_DCLKP_EN; | |
1611 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1612 | ||
221c7862 | 1613 | vlv_dpio_put(dev_priv); |
f6071166 JB |
1614 | } |
1615 | ||
e4607fcf | 1616 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
7801f3b7 | 1617 | struct intel_digital_port *dig_port, |
9b6de0a1 | 1618 | unsigned int expected_mask) |
89b667f8 JB |
1619 | { |
1620 | u32 port_mask; | |
f0f59a00 | 1621 | i915_reg_t dpll_reg; |
89b667f8 | 1622 | |
7801f3b7 | 1623 | switch (dig_port->base.port) { |
e4607fcf | 1624 | case PORT_B: |
89b667f8 | 1625 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1626 | dpll_reg = DPLL(0); |
e4607fcf CML |
1627 | break; |
1628 | case PORT_C: | |
89b667f8 | 1629 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1630 | dpll_reg = DPLL(0); |
9b6de0a1 | 1631 | expected_mask <<= 4; |
00fc31b7 CML |
1632 | break; |
1633 | case PORT_D: | |
1634 | port_mask = DPLL_PORTD_READY_MASK; | |
1635 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1636 | break; |
1637 | default: | |
1638 | BUG(); | |
1639 | } | |
89b667f8 | 1640 | |
4cb3b44d DCS |
1641 | if (intel_de_wait_for_register(dev_priv, dpll_reg, |
1642 | port_mask, expected_mask, 1000)) | |
e57291c2 PB |
1643 | drm_WARN(&dev_priv->drm, 1, |
1644 | "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", | |
7801f3b7 | 1645 | dig_port->base.base.base.id, dig_port->base.base.name, |
e57291c2 PB |
1646 | intel_de_read(dev_priv, dpll_reg) & port_mask, |
1647 | expected_mask); | |
89b667f8 JB |
1648 | } |
1649 | ||
9eae5e27 | 1650 | static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) |
040484af | 1651 | { |
2225f3c6 | 1652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7efd90fb ML |
1653 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1654 | enum pipe pipe = crtc->pipe; | |
f0f59a00 | 1655 | i915_reg_t reg; |
ba3f4d0a | 1656 | u32 val, pipeconf_val; |
040484af | 1657 | |
040484af | 1658 | /* Make sure PCH DPLL is enabled */ |
7efd90fb | 1659 | assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); |
040484af JB |
1660 | |
1661 | /* FDI must be feeding us bits for PCH ports */ | |
1662 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1663 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1664 | ||
6e266956 | 1665 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 | 1666 | reg = TRANS_CHICKEN2(pipe); |
dc008bf0 | 1667 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
1668 | /* |
1669 | * Workaround: Set the timing override bit | |
1670 | * before enabling the pch transcoder. | |
1671 | */ | |
23670b32 | 1672 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
cc7a4cff VS |
1673 | /* Configure frame start delay to match the CPU */ |
1674 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; | |
1675 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 1676 | intel_de_write(dev_priv, reg, val); |
59c859d6 | 1677 | } |
23670b32 | 1678 | |
ab9412ba | 1679 | reg = PCH_TRANSCONF(pipe); |
dc008bf0 JN |
1680 | val = intel_de_read(dev_priv, reg); |
1681 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); | |
e9bcff5c | 1682 | |
2d1fe073 | 1683 | if (HAS_PCH_IBX(dev_priv)) { |
cc7a4cff VS |
1684 | /* Configure frame start delay to match the CPU */ |
1685 | val &= ~TRANS_FRAME_START_DELAY_MASK; | |
1686 | val |= TRANS_FRAME_START_DELAY(0); | |
1687 | ||
e9bcff5c | 1688 | /* |
c5de7c6f VS |
1689 | * Make the BPC in transcoder be consistent with |
1690 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1691 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1692 | */ |
dfd07d72 | 1693 | val &= ~PIPECONF_BPC_MASK; |
7efd90fb | 1694 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1695 | val |= PIPECONF_8BPC; |
1696 | else | |
1697 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1698 | } |
5f7f726d PZ |
1699 | |
1700 | val &= ~TRANS_INTERLACE_MASK; | |
27b680f9 | 1701 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) { |
2d1fe073 | 1702 | if (HAS_PCH_IBX(dev_priv) && |
7efd90fb | 1703 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1704 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1705 | else | |
1706 | val |= TRANS_INTERLACED; | |
27b680f9 | 1707 | } else { |
5f7f726d | 1708 | val |= TRANS_PROGRESSIVE; |
27b680f9 | 1709 | } |
5f7f726d | 1710 | |
dc008bf0 | 1711 | intel_de_write(dev_priv, reg, val | TRANS_ENABLE); |
4cb3b44d | 1712 | if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) |
cd49f818 WK |
1713 | drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", |
1714 | pipe_name(pipe)); | |
040484af JB |
1715 | } |
1716 | ||
8fb033d7 | 1717 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1718 | enum transcoder cpu_transcoder) |
040484af | 1719 | { |
8fb033d7 | 1720 | u32 val, pipeconf_val; |
8fb033d7 | 1721 | |
8fb033d7 | 1722 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1723 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1724 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1725 | |
dc008bf0 | 1726 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); |
cc7a4cff | 1727 | /* Workaround: set timing override bit. */ |
23670b32 | 1728 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
cc7a4cff VS |
1729 | /* Configure frame start delay to match the CPU */ |
1730 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; | |
1731 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 1732 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1733 | |
25f3ef11 | 1734 | val = TRANS_ENABLE; |
dc008bf0 | 1735 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); |
8fb033d7 | 1736 | |
9a76b1c6 PZ |
1737 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1738 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1739 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1740 | else |
1741 | val |= TRANS_PROGRESSIVE; | |
1742 | ||
dc008bf0 | 1743 | intel_de_write(dev_priv, LPT_TRANSCONF, val); |
4cb3b44d DCS |
1744 | if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, |
1745 | TRANS_STATE_ENABLE, 100)) | |
cd49f818 | 1746 | drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1747 | } |
1748 | ||
9eae5e27 LDM |
1749 | static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1750 | enum pipe pipe) | |
040484af | 1751 | { |
f0f59a00 | 1752 | i915_reg_t reg; |
ba3f4d0a | 1753 | u32 val; |
040484af JB |
1754 | |
1755 | /* FDI relies on the transcoder */ | |
1756 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1757 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1758 | ||
291906f1 JB |
1759 | /* Ports must be off as well */ |
1760 | assert_pch_ports_disabled(dev_priv, pipe); | |
1761 | ||
ab9412ba | 1762 | reg = PCH_TRANSCONF(pipe); |
dc008bf0 | 1763 | val = intel_de_read(dev_priv, reg); |
040484af | 1764 | val &= ~TRANS_ENABLE; |
dc008bf0 | 1765 | intel_de_write(dev_priv, reg, val); |
040484af | 1766 | /* wait for PCH transcoder off, transcoder state */ |
4cb3b44d | 1767 | if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) |
cd49f818 WK |
1768 | drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", |
1769 | pipe_name(pipe)); | |
23670b32 | 1770 | |
6e266956 | 1771 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1772 | /* Workaround: Clear the timing override chicken bit again. */ |
1773 | reg = TRANS_CHICKEN2(pipe); | |
dc008bf0 | 1774 | val = intel_de_read(dev_priv, reg); |
23670b32 | 1775 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
dc008bf0 | 1776 | intel_de_write(dev_priv, reg, val); |
23670b32 | 1777 | } |
040484af JB |
1778 | } |
1779 | ||
b7076546 | 1780 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1781 | { |
8fb033d7 PZ |
1782 | u32 val; |
1783 | ||
dc008bf0 | 1784 | val = intel_de_read(dev_priv, LPT_TRANSCONF); |
8fb033d7 | 1785 | val &= ~TRANS_ENABLE; |
dc008bf0 | 1786 | intel_de_write(dev_priv, LPT_TRANSCONF, val); |
8fb033d7 | 1787 | /* wait for PCH transcoder off, transcoder state */ |
4cb3b44d DCS |
1788 | if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, |
1789 | TRANS_STATE_ENABLE, 50)) | |
cd49f818 | 1790 | drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1791 | |
1792 | /* Workaround: clear timing override bit. */ | |
dc008bf0 | 1793 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1794 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
dc008bf0 | 1795 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1796 | } |
1797 | ||
a2196033 | 1798 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1799 | { |
1800 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1801 | ||
65f2130c | 1802 | if (HAS_PCH_LPT(dev_priv)) |
a2196033 | 1803 | return PIPE_A; |
65f2130c | 1804 | else |
a2196033 | 1805 | return crtc->pipe; |
65f2130c VS |
1806 | } |
1807 | ||
32db0b65 VS |
1808 | static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) |
1809 | { | |
2225f3c6 | 1810 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
33267703 VK |
1811 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1812 | u32 mode_flags = crtc->mode_flags; | |
1813 | ||
1814 | /* | |
1815 | * From Gen 11, In case of dsi cmd mode, frame counter wouldnt | |
1816 | * have updated at the beginning of TE, if we want to use | |
1817 | * the hw counter, then we would find it updated in only | |
1818 | * the next TE, hence switching to sw counter. | |
1819 | */ | |
1820 | if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1)) | |
1821 | return 0; | |
32db0b65 VS |
1822 | |
1823 | /* | |
1824 | * On i965gm the hardware frame counter reads | |
1825 | * zero when the TV encoder is enabled :( | |
1826 | */ | |
1827 | if (IS_I965GM(dev_priv) && | |
1828 | (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) | |
1829 | return 0; | |
1830 | ||
1831 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
1832 | return 0xffffffff; /* full 32 bit counter */ | |
1833 | else if (INTEL_GEN(dev_priv) >= 3) | |
1834 | return 0xffffff; /* only 24 bits of frame count */ | |
1835 | else | |
1836 | return 0; /* Gen2 doesn't have a hardware frame counter */ | |
1837 | } | |
1838 | ||
21fd23ac | 1839 | void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) |
32db0b65 | 1840 | { |
2225f3c6 | 1841 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
32db0b65 | 1842 | |
407b9405 | 1843 | assert_vblank_disabled(&crtc->base); |
32db0b65 VS |
1844 | drm_crtc_set_max_vblank_count(&crtc->base, |
1845 | intel_crtc_max_vblank_count(crtc_state)); | |
1846 | drm_crtc_vblank_on(&crtc->base); | |
1847 | } | |
1848 | ||
773b4b54 | 1849 | void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) |
d18b6bb8 | 1850 | { |
f5271ee5 VS |
1851 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1852 | ||
d18b6bb8 VS |
1853 | drm_crtc_vblank_off(&crtc->base); |
1854 | assert_vblank_disabled(&crtc->base); | |
1855 | } | |
1856 | ||
21fd23ac | 1857 | void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) |
b24e7179 | 1858 | { |
2225f3c6 | 1859 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
4972f70a VS |
1860 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1861 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; | |
0372264a | 1862 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1863 | i915_reg_t reg; |
b24e7179 JB |
1864 | u32 val; |
1865 | ||
cd49f818 | 1866 | drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); |
9e2ee2dd | 1867 | |
51f5a096 | 1868 | assert_planes_disabled(crtc); |
58c6eaa2 | 1869 | |
b24e7179 JB |
1870 | /* |
1871 | * A pipe without a PLL won't actually be able to drive bits from | |
1872 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1873 | * need the check. | |
1874 | */ | |
b2ae318a | 1875 | if (HAS_GMCH(dev_priv)) { |
4972f70a | 1876 | if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1877 | assert_dsi_pll_enabled(dev_priv); |
1878 | else | |
1879 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1880 | } else { |
4972f70a | 1881 | if (new_crtc_state->has_pch_encoder) { |
040484af | 1882 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1883 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1884 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1885 | assert_fdi_tx_pll_enabled(dev_priv, |
1886 | (enum pipe) cpu_transcoder); | |
040484af JB |
1887 | } |
1888 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1889 | } | |
b24e7179 | 1890 | |
4c888e7b | 1891 | trace_intel_pipe_enable(crtc); |
0b2599a4 | 1892 | |
702e7a56 | 1893 | reg = PIPECONF(cpu_transcoder); |
dc008bf0 | 1894 | val = intel_de_read(dev_priv, reg); |
7ad25d48 | 1895 | if (val & PIPECONF_ENABLE) { |
e56134bc | 1896 | /* we keep both pipes enabled on 830 */ |
e57291c2 | 1897 | drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); |
00d70b15 | 1898 | return; |
7ad25d48 | 1899 | } |
00d70b15 | 1900 | |
dc008bf0 JN |
1901 | intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); |
1902 | intel_de_posting_read(dev_priv, reg); | |
b7792d8b VS |
1903 | |
1904 | /* | |
8fedd64d VS |
1905 | * Until the pipe starts PIPEDSL reads will return a stale value, |
1906 | * which causes an apparent vblank timestamp jump when PIPEDSL | |
1907 | * resets to its proper value. That also messes up the frame count | |
1908 | * when it's derived from the timestamps. So let's wait for the | |
1909 | * pipe to start properly before we call drm_crtc_vblank_on() | |
b7792d8b | 1910 | */ |
32db0b65 | 1911 | if (intel_crtc_max_vblank_count(new_crtc_state) == 0) |
8fedd64d | 1912 | intel_wait_for_pipe_scanline_moving(crtc); |
b24e7179 JB |
1913 | } |
1914 | ||
773b4b54 | 1915 | void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) |
b24e7179 | 1916 | { |
2225f3c6 | 1917 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
fac5e23e | 1918 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4972f70a | 1919 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
575f7ab7 | 1920 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1921 | i915_reg_t reg; |
b24e7179 JB |
1922 | u32 val; |
1923 | ||
cd49f818 | 1924 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); |
9e2ee2dd | 1925 | |
b24e7179 JB |
1926 | /* |
1927 | * Make sure planes won't keep trying to pump pixels to us, | |
1928 | * or we might hang the display. | |
1929 | */ | |
51f5a096 | 1930 | assert_planes_disabled(crtc); |
b24e7179 | 1931 | |
4c888e7b | 1932 | trace_intel_pipe_disable(crtc); |
0b2599a4 | 1933 | |
702e7a56 | 1934 | reg = PIPECONF(cpu_transcoder); |
dc008bf0 | 1935 | val = intel_de_read(dev_priv, reg); |
00d70b15 CW |
1936 | if ((val & PIPECONF_ENABLE) == 0) |
1937 | return; | |
1938 | ||
67adc644 VS |
1939 | /* |
1940 | * Double wide has implications for planes | |
1941 | * so best keep it disabled when not needed. | |
1942 | */ | |
4972f70a | 1943 | if (old_crtc_state->double_wide) |
67adc644 VS |
1944 | val &= ~PIPECONF_DOUBLE_WIDE; |
1945 | ||
1946 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1947 | if (!IS_I830(dev_priv)) |
67adc644 VS |
1948 | val &= ~PIPECONF_ENABLE; |
1949 | ||
dc008bf0 | 1950 | intel_de_write(dev_priv, reg, val); |
67adc644 | 1951 | if ((val & PIPECONF_ENABLE) == 0) |
4972f70a | 1952 | intel_wait_for_pipe_off(old_crtc_state); |
b24e7179 JB |
1953 | } |
1954 | ||
832be82f VS |
1955 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1956 | { | |
cf819eff | 1957 | return IS_GEN(dev_priv, 2) ? 2048 : 4096; |
832be82f VS |
1958 | } |
1959 | ||
e7af9094 ID |
1960 | static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) |
1961 | { | |
1962 | if (!is_ccs_modifier(fb->modifier)) | |
1963 | return false; | |
1964 | ||
1965 | return plane >= fb->format->num_planes / 2; | |
1966 | } | |
1967 | ||
b3e57bcc DP |
1968 | static bool is_gen12_ccs_modifier(u64 modifier) |
1969 | { | |
2dfbf9d2 DP |
1970 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || |
1971 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; | |
1972 | ||
b3e57bcc DP |
1973 | } |
1974 | ||
1975 | static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) | |
1976 | { | |
1977 | return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); | |
1978 | } | |
1979 | ||
e7af9094 ID |
1980 | static bool is_aux_plane(const struct drm_framebuffer *fb, int plane) |
1981 | { | |
1982 | if (is_ccs_modifier(fb->modifier)) | |
1983 | return is_ccs_plane(fb, plane); | |
1984 | ||
1985 | return plane == 1; | |
1986 | } | |
1987 | ||
1988 | static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) | |
1989 | { | |
ce04ecd9 PB |
1990 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || |
1991 | (main_plane && main_plane >= fb->format->num_planes / 2)); | |
e7af9094 ID |
1992 | |
1993 | return fb->format->num_planes / 2 + main_plane; | |
1994 | } | |
1995 | ||
b3e57bcc DP |
1996 | static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) |
1997 | { | |
ce04ecd9 PB |
1998 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || |
1999 | ccs_plane < fb->format->num_planes / 2); | |
b3e57bcc DP |
2000 | |
2001 | return ccs_plane - fb->format->num_planes / 2; | |
2002 | } | |
2003 | ||
2dfbf9d2 | 2004 | int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) |
e7af9094 | 2005 | { |
a007138e VS |
2006 | struct drm_i915_private *i915 = to_i915(fb->dev); |
2007 | ||
e7af9094 ID |
2008 | if (is_ccs_modifier(fb->modifier)) |
2009 | return main_to_ccs_plane(fb, main_plane); | |
a007138e VS |
2010 | else if (INTEL_GEN(i915) < 11 && |
2011 | intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) | |
2012 | return 1; | |
2013 | else | |
2014 | return 0; | |
e7af9094 ID |
2015 | } |
2016 | ||
4941f35b ID |
2017 | bool |
2018 | intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, | |
2019 | uint64_t modifier) | |
2020 | { | |
2021 | return info->is_yuv && | |
2022 | info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2); | |
2023 | } | |
2024 | ||
d156135e ID |
2025 | static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, |
2026 | int color_plane) | |
2027 | { | |
2028 | return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && | |
2029 | color_plane == 1; | |
2030 | } | |
2031 | ||
d88c4afd | 2032 | static unsigned int |
5d2a1950 | 2033 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) |
7b49f948 | 2034 | { |
d88c4afd | 2035 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
5d2a1950 | 2036 | unsigned int cpp = fb->format->cpp[color_plane]; |
d88c4afd VS |
2037 | |
2038 | switch (fb->modifier) { | |
2f075565 | 2039 | case DRM_FORMAT_MOD_LINEAR: |
54d4d719 | 2040 | return intel_tile_size(dev_priv); |
7b49f948 | 2041 | case I915_FORMAT_MOD_X_TILED: |
cf819eff | 2042 | if (IS_GEN(dev_priv, 2)) |
7b49f948 VS |
2043 | return 128; |
2044 | else | |
2045 | return 512; | |
2e2adb05 | 2046 | case I915_FORMAT_MOD_Y_TILED_CCS: |
e7af9094 | 2047 | if (is_ccs_plane(fb, color_plane)) |
2e2adb05 | 2048 | return 128; |
df561f66 | 2049 | fallthrough; |
b3e57bcc | 2050 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2dfbf9d2 | 2051 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
b3e57bcc DP |
2052 | if (is_ccs_plane(fb, color_plane)) |
2053 | return 64; | |
df561f66 | 2054 | fallthrough; |
7b49f948 | 2055 | case I915_FORMAT_MOD_Y_TILED: |
cf819eff | 2056 | if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) |
7b49f948 VS |
2057 | return 128; |
2058 | else | |
2059 | return 512; | |
2e2adb05 | 2060 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
e7af9094 | 2061 | if (is_ccs_plane(fb, color_plane)) |
2e2adb05 | 2062 | return 128; |
df561f66 | 2063 | fallthrough; |
7b49f948 VS |
2064 | case I915_FORMAT_MOD_Yf_TILED: |
2065 | switch (cpp) { | |
2066 | case 1: | |
2067 | return 64; | |
2068 | case 2: | |
2069 | case 4: | |
2070 | return 128; | |
2071 | case 8: | |
2072 | case 16: | |
2073 | return 256; | |
2074 | default: | |
2075 | MISSING_CASE(cpp); | |
2076 | return cpp; | |
2077 | } | |
2078 | break; | |
2079 | default: | |
d88c4afd | 2080 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2081 | return cpp; |
2082 | } | |
2083 | } | |
2084 | ||
d88c4afd | 2085 | static unsigned int |
5d2a1950 | 2086 | intel_tile_height(const struct drm_framebuffer *fb, int color_plane) |
a57ce0b2 | 2087 | { |
b3e57bcc DP |
2088 | if (is_gen12_ccs_plane(fb, color_plane)) |
2089 | return 1; | |
2090 | ||
54d4d719 VS |
2091 | return intel_tile_size(to_i915(fb->dev)) / |
2092 | intel_tile_width_bytes(fb, color_plane); | |
6761dd31 TU |
2093 | } |
2094 | ||
8d0deca8 | 2095 | /* Return the tile dimensions in pixel units */ |
5d2a1950 | 2096 | static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, |
8d0deca8 | 2097 | unsigned int *tile_width, |
d88c4afd | 2098 | unsigned int *tile_height) |
8d0deca8 | 2099 | { |
5d2a1950 VS |
2100 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); |
2101 | unsigned int cpp = fb->format->cpp[color_plane]; | |
8d0deca8 VS |
2102 | |
2103 | *tile_width = tile_width_bytes / cpp; | |
021a4116 | 2104 | *tile_height = intel_tile_height(fb, color_plane); |
8d0deca8 VS |
2105 | } |
2106 | ||
d156135e ID |
2107 | static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, |
2108 | int color_plane) | |
2109 | { | |
2110 | unsigned int tile_width, tile_height; | |
2111 | ||
2112 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); | |
2113 | ||
2114 | return fb->pitches[color_plane] * tile_height; | |
2115 | } | |
2116 | ||
6761dd31 | 2117 | unsigned int |
d88c4afd | 2118 | intel_fb_align_height(const struct drm_framebuffer *fb, |
5d2a1950 | 2119 | int color_plane, unsigned int height) |
6761dd31 | 2120 | { |
5d2a1950 | 2121 | unsigned int tile_height = intel_tile_height(fb, color_plane); |
832be82f VS |
2122 | |
2123 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2124 | } |
2125 | ||
1663b9d6 VS |
2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2127 | { | |
2128 | unsigned int size = 0; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2133 | ||
2134 | return size; | |
2135 | } | |
2136 | ||
1a74fc0b VS |
2137 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) |
2138 | { | |
2139 | unsigned int size = 0; | |
2140 | int i; | |
2141 | ||
2142 | for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) | |
2143 | size += rem_info->plane[i].width * rem_info->plane[i].height; | |
2144 | ||
2145 | return size; | |
2146 | } | |
2147 | ||
75c82a53 | 2148 | static void |
3465c580 VS |
2149 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2150 | const struct drm_framebuffer *fb, | |
2151 | unsigned int rotation) | |
f64b98cd | 2152 | { |
7b92c047 | 2153 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2154 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2155 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2156 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2157 | } |
2158 | } | |
50470bb0 | 2159 | |
fabac484 VS |
2160 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2161 | { | |
2162 | if (IS_I830(dev_priv)) | |
2163 | return 16 * 1024; | |
2164 | else if (IS_I85X(dev_priv)) | |
2165 | return 256; | |
d9e1551e VS |
2166 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2167 | return 32; | |
fabac484 VS |
2168 | else |
2169 | return 4 * 1024; | |
2170 | } | |
2171 | ||
603525d7 | 2172 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 | 2173 | { |
c56b89f1 | 2174 | if (INTEL_GEN(dev_priv) >= 9) |
4e9a86b6 | 2175 | return 256 * 1024; |
c0f86832 | 2176 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2177 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 | 2178 | return 128 * 1024; |
c56b89f1 | 2179 | else if (INTEL_GEN(dev_priv) >= 4) |
4e9a86b6 VS |
2180 | return 4 * 1024; |
2181 | else | |
44c5905e | 2182 | return 0; |
4e9a86b6 VS |
2183 | } |
2184 | ||
d88c4afd | 2185 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
5d2a1950 | 2186 | int color_plane) |
603525d7 | 2187 | { |
d88c4afd VS |
2188 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2189 | ||
b90c1ee1 | 2190 | /* AUX_DIST needs only 4K alignment */ |
d156135e ID |
2191 | if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) || |
2192 | is_ccs_plane(fb, color_plane)) | |
b90c1ee1 VS |
2193 | return 4096; |
2194 | ||
d88c4afd | 2195 | switch (fb->modifier) { |
2f075565 | 2196 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2197 | return intel_linear_alignment(dev_priv); |
2198 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2199 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2200 | return 256 * 1024; |
2201 | return 0; | |
2dfbf9d2 DP |
2202 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
2203 | if (is_semiplanar_uv_plane(fb, color_plane)) | |
2204 | return intel_tile_row_size(fb, color_plane); | |
df561f66 | 2205 | fallthrough; |
b3e57bcc DP |
2206 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2207 | return 16 * 1024; | |
2e2adb05 VS |
2208 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2209 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 | 2210 | case I915_FORMAT_MOD_Y_TILED: |
d156135e ID |
2211 | if (INTEL_GEN(dev_priv) >= 12 && |
2212 | is_semiplanar_uv_plane(fb, color_plane)) | |
2213 | return intel_tile_row_size(fb, color_plane); | |
df561f66 | 2214 | fallthrough; |
603525d7 VS |
2215 | case I915_FORMAT_MOD_Yf_TILED: |
2216 | return 1 * 1024 * 1024; | |
2217 | default: | |
d88c4afd | 2218 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2219 | return 0; |
2220 | } | |
2221 | } | |
2222 | ||
f7a02ad7 VS |
2223 | static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) |
2224 | { | |
f90a85e7 | 2225 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
f7a02ad7 VS |
2226 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2227 | ||
bb211c3d VS |
2228 | return INTEL_GEN(dev_priv) < 4 || |
2229 | (plane->has_fbc && | |
2230 | plane_state->view.type == I915_GGTT_VIEW_NORMAL); | |
f7a02ad7 VS |
2231 | } |
2232 | ||
058d88c4 | 2233 | struct i915_vma * |
5935485f | 2234 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
f5929c53 | 2235 | const struct i915_ggtt_view *view, |
f7a02ad7 | 2236 | bool uses_fence, |
5935485f | 2237 | unsigned long *out_flags) |
6b95a207 | 2238 | { |
850c4cdc | 2239 | struct drm_device *dev = fb->dev; |
fac5e23e | 2240 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2241 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1d264d91 | 2242 | intel_wakeref_t wakeref; |
058d88c4 | 2243 | struct i915_vma *vma; |
5935485f | 2244 | unsigned int pinctl; |
6b95a207 | 2245 | u32 alignment; |
6b95a207 | 2246 | |
e57291c2 | 2247 | if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) |
5a90606d | 2248 | return ERR_PTR(-EINVAL); |
ebcdd39e | 2249 | |
d88c4afd | 2250 | alignment = intel_surf_alignment(fb, 0); |
e57291c2 | 2251 | if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) |
7361bdb2 | 2252 | return ERR_PTR(-EINVAL); |
6b95a207 | 2253 | |
693db184 CW |
2254 | /* Note that the w/a also requires 64 PTE of padding following the |
2255 | * bo. We currently fill all unused PTE with the shadow page and so | |
2256 | * we should always have valid PTE following the scanout preventing | |
2257 | * the VT-d warning. | |
2258 | */ | |
48f112fe | 2259 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2260 | alignment = 256 * 1024; |
2261 | ||
d6dd6843 PZ |
2262 | /* |
2263 | * Global gtt pte registers are special registers which actually forward | |
2264 | * writes to a chunk of system memory. Which means that there is no risk | |
2265 | * that the register values disappear as soon as we call | |
2266 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2267 | * pin/unpin/fence and not more. | |
2268 | */ | |
d858d569 | 2269 | wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
d6dd6843 | 2270 | |
9db529aa DV |
2271 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
2272 | ||
8b1c78e0 CW |
2273 | /* |
2274 | * Valleyview is definitely limited to scanning out the first | |
5935485f CW |
2275 | * 512MiB. Lets presume this behaviour was inherited from the |
2276 | * g4x display engine and that all earlier gen are similarly | |
2277 | * limited. Testing suggests that it is a little more | |
2278 | * complicated than this. For example, Cherryview appears quite | |
2279 | * happy to scanout from anywhere within its global aperture. | |
2280 | */ | |
8b1c78e0 | 2281 | pinctl = 0; |
b2ae318a | 2282 | if (HAS_GMCH(dev_priv)) |
5935485f CW |
2283 | pinctl |= PIN_MAPPABLE; |
2284 | ||
2285 | vma = i915_gem_object_pin_to_display_plane(obj, | |
f5929c53 | 2286 | alignment, view, pinctl); |
49ef5294 CW |
2287 | if (IS_ERR(vma)) |
2288 | goto err; | |
6b95a207 | 2289 | |
f7a02ad7 | 2290 | if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { |
85798ac9 VS |
2291 | int ret; |
2292 | ||
8b1c78e0 CW |
2293 | /* |
2294 | * Install a fence for tiled scan-out. Pre-i965 always needs a | |
49ef5294 CW |
2295 | * fence, whereas 965+ only requires a fence if using |
2296 | * framebuffer compression. For simplicity, we always, when | |
2297 | * possible, install a fence as the cost is not that onerous. | |
2298 | * | |
2299 | * If we fail to fence the tiled scanout, then either the | |
2300 | * modeset will reject the change (which is highly unlikely as | |
2301 | * the affected systems, all but one, do not have unmappable | |
2302 | * space) or we will not be able to enable full powersaving | |
2303 | * techniques (also likely not to apply due to various limits | |
2304 | * FBC and the like impose on the size of the buffer, which | |
2305 | * presumably we violated anyway with this unmappable buffer). | |
2306 | * Anyway, it is presumably better to stumble onwards with | |
2307 | * something and try to run the system in a "less than optimal" | |
2308 | * mode that matches the user configuration. | |
2309 | */ | |
85798ac9 VS |
2310 | ret = i915_vma_pin_fence(vma); |
2311 | if (ret != 0 && INTEL_GEN(dev_priv) < 4) { | |
7509702b | 2312 | i915_gem_object_unpin_from_display_plane(vma); |
85798ac9 VS |
2313 | vma = ERR_PTR(ret); |
2314 | goto err; | |
2315 | } | |
2316 | ||
2317 | if (ret == 0 && vma->fence) | |
5935485f | 2318 | *out_flags |= PLANE_HAS_FENCE; |
9807216f | 2319 | } |
6b95a207 | 2320 | |
be1e3415 | 2321 | i915_vma_get(vma); |
49ef5294 | 2322 | err: |
9db529aa | 2323 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); |
d858d569 | 2324 | intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); |
058d88c4 | 2325 | return vma; |
6b95a207 KH |
2326 | } |
2327 | ||
5935485f | 2328 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) |
1690e1eb | 2329 | { |
80f0b679 | 2330 | i915_gem_object_lock(vma->obj, NULL); |
5935485f CW |
2331 | if (flags & PLANE_HAS_FENCE) |
2332 | i915_vma_unpin_fence(vma); | |
058d88c4 | 2333 | i915_gem_object_unpin_from_display_plane(vma); |
6951e589 CW |
2334 | i915_gem_object_unlock(vma->obj); |
2335 | ||
be1e3415 | 2336 | i915_vma_put(vma); |
1690e1eb CW |
2337 | } |
2338 | ||
5d2a1950 | 2339 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane, |
ef78ec94 VS |
2340 | unsigned int rotation) |
2341 | { | |
bd2ef25d | 2342 | if (drm_rotation_90_or_270(rotation)) |
5d2a1950 | 2343 | return to_intel_framebuffer(fb)->rotated[color_plane].pitch; |
ef78ec94 | 2344 | else |
5d2a1950 | 2345 | return fb->pitches[color_plane]; |
ef78ec94 VS |
2346 | } |
2347 | ||
6687c906 VS |
2348 | /* |
2349 | * Convert the x/y offsets into a linear offset. | |
2350 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2351 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2352 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2353 | */ | |
2354 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c | 2355 | const struct intel_plane_state *state, |
5d2a1950 | 2356 | int color_plane) |
6687c906 | 2357 | { |
7b3cb17a | 2358 | const struct drm_framebuffer *fb = state->hw.fb; |
5d2a1950 VS |
2359 | unsigned int cpp = fb->format->cpp[color_plane]; |
2360 | unsigned int pitch = state->color_plane[color_plane].stride; | |
6687c906 VS |
2361 | |
2362 | return y * pitch + x * cpp; | |
2363 | } | |
2364 | ||
2365 | /* | |
2366 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2367 | * specified plane src x/y offsets. The resulting x/y offsets | |
2368 | * specify the start of scanout from the beginning of the gtt mapping. | |
2369 | */ | |
2370 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c | 2371 | const struct intel_plane_state *state, |
5d2a1950 | 2372 | int color_plane) |
6687c906 VS |
2373 | |
2374 | { | |
54d4d719 VS |
2375 | *x += state->color_plane[color_plane].x; |
2376 | *y += state->color_plane[color_plane].y; | |
6687c906 VS |
2377 | } |
2378 | ||
6d19a44c VS |
2379 | static u32 intel_adjust_tile_offset(int *x, int *y, |
2380 | unsigned int tile_width, | |
2381 | unsigned int tile_height, | |
2382 | unsigned int tile_size, | |
2383 | unsigned int pitch_tiles, | |
2384 | u32 old_offset, | |
2385 | u32 new_offset) | |
29cf9491 | 2386 | { |
b9b24038 | 2387 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2388 | unsigned int tiles; |
2389 | ||
2390 | WARN_ON(old_offset & (tile_size - 1)); | |
2391 | WARN_ON(new_offset & (tile_size - 1)); | |
2392 | WARN_ON(new_offset > old_offset); | |
2393 | ||
2394 | tiles = (old_offset - new_offset) / tile_size; | |
2395 | ||
2396 | *y += tiles / pitch_tiles * tile_height; | |
2397 | *x += tiles % pitch_tiles * tile_width; | |
2398 | ||
b9b24038 VS |
2399 | /* minimize x in case it got needlessly big */ |
2400 | *y += *x / pitch_pixels * tile_height; | |
2401 | *x %= pitch_pixels; | |
2402 | ||
29cf9491 VS |
2403 | return new_offset; |
2404 | } | |
2405 | ||
b3e57bcc | 2406 | static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) |
2a11b1b4 | 2407 | { |
b3e57bcc DP |
2408 | return fb->modifier == DRM_FORMAT_MOD_LINEAR || |
2409 | is_gen12_ccs_plane(fb, color_plane); | |
2a11b1b4 DP |
2410 | } |
2411 | ||
6d19a44c | 2412 | static u32 intel_adjust_aligned_offset(int *x, int *y, |
5d2a1950 VS |
2413 | const struct drm_framebuffer *fb, |
2414 | int color_plane, | |
6d19a44c | 2415 | unsigned int rotation, |
df79cf44 | 2416 | unsigned int pitch, |
6d19a44c | 2417 | u32 old_offset, u32 new_offset) |
66a2d927 | 2418 | { |
6d19a44c | 2419 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
5d2a1950 | 2420 | unsigned int cpp = fb->format->cpp[color_plane]; |
66a2d927 | 2421 | |
e57291c2 | 2422 | drm_WARN_ON(&dev_priv->drm, new_offset > old_offset); |
66a2d927 | 2423 | |
b3e57bcc | 2424 | if (!is_surface_linear(fb, color_plane)) { |
66a2d927 VS |
2425 | unsigned int tile_size, tile_width, tile_height; |
2426 | unsigned int pitch_tiles; | |
2427 | ||
2428 | tile_size = intel_tile_size(dev_priv); | |
5d2a1950 | 2429 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
66a2d927 | 2430 | |
bd2ef25d | 2431 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2432 | pitch_tiles = pitch / tile_height; |
2433 | swap(tile_width, tile_height); | |
2434 | } else { | |
2435 | pitch_tiles = pitch / (tile_width * cpp); | |
2436 | } | |
2437 | ||
6d19a44c VS |
2438 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2439 | tile_size, pitch_tiles, | |
2440 | old_offset, new_offset); | |
66a2d927 VS |
2441 | } else { |
2442 | old_offset += *y * pitch + *x * cpp; | |
2443 | ||
2444 | *y = (old_offset - new_offset) / pitch; | |
2445 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2446 | } | |
2447 | ||
2448 | return new_offset; | |
2449 | } | |
2450 | ||
303ba695 VS |
2451 | /* |
2452 | * Adjust the tile offset by moving the difference into | |
2453 | * the x/y offsets. | |
2454 | */ | |
6d19a44c VS |
2455 | static u32 intel_plane_adjust_aligned_offset(int *x, int *y, |
2456 | const struct intel_plane_state *state, | |
5d2a1950 | 2457 | int color_plane, |
6d19a44c | 2458 | u32 old_offset, u32 new_offset) |
303ba695 | 2459 | { |
7b3cb17a ML |
2460 | return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, |
2461 | state->hw.rotation, | |
5d2a1950 | 2462 | state->color_plane[color_plane].stride, |
6d19a44c | 2463 | old_offset, new_offset); |
303ba695 VS |
2464 | } |
2465 | ||
8d0deca8 | 2466 | /* |
6d19a44c | 2467 | * Computes the aligned offset to the base tile and adjusts |
8d0deca8 VS |
2468 | * x, y. bytes per pixel is assumed to be a power-of-two. |
2469 | * | |
2470 | * In the 90/270 rotated case, x and y are assumed | |
2471 | * to be already rotated to match the rotated GTT view, and | |
2472 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2473 | * |
2474 | * This function is used when computing the derived information | |
2475 | * under intel_framebuffer, so using any of that information | |
2476 | * here is not allowed. Anything under drm_framebuffer can be | |
2477 | * used. This is why the user has to pass in the pitch since it | |
2478 | * is specified in the rotated orientation. | |
8d0deca8 | 2479 | */ |
6d19a44c VS |
2480 | static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv, |
2481 | int *x, int *y, | |
5d2a1950 VS |
2482 | const struct drm_framebuffer *fb, |
2483 | int color_plane, | |
6d19a44c VS |
2484 | unsigned int pitch, |
2485 | unsigned int rotation, | |
2486 | u32 alignment) | |
c2c75131 | 2487 | { |
5d2a1950 | 2488 | unsigned int cpp = fb->format->cpp[color_plane]; |
6687c906 | 2489 | u32 offset, offset_aligned; |
29cf9491 | 2490 | |
b3e57bcc | 2491 | if (!is_surface_linear(fb, color_plane)) { |
8d0deca8 VS |
2492 | unsigned int tile_size, tile_width, tile_height; |
2493 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2494 | |
d843310d | 2495 | tile_size = intel_tile_size(dev_priv); |
5d2a1950 | 2496 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
8d0deca8 | 2497 | |
bd2ef25d | 2498 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2499 | pitch_tiles = pitch / tile_height; |
2500 | swap(tile_width, tile_height); | |
2501 | } else { | |
2502 | pitch_tiles = pitch / (tile_width * cpp); | |
2503 | } | |
d843310d VS |
2504 | |
2505 | tile_rows = *y / tile_height; | |
2506 | *y %= tile_height; | |
c2c75131 | 2507 | |
8d0deca8 VS |
2508 | tiles = *x / tile_width; |
2509 | *x %= tile_width; | |
bc752862 | 2510 | |
29cf9491 | 2511 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
7361bdb2 ID |
2512 | |
2513 | offset_aligned = offset; | |
2514 | if (alignment) | |
2515 | offset_aligned = rounddown(offset_aligned, alignment); | |
bc752862 | 2516 | |
6d19a44c VS |
2517 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2518 | tile_size, pitch_tiles, | |
2519 | offset, offset_aligned); | |
29cf9491 | 2520 | } else { |
bc752862 | 2521 | offset = *y * pitch + *x * cpp; |
7361bdb2 ID |
2522 | offset_aligned = offset; |
2523 | if (alignment) { | |
2524 | offset_aligned = rounddown(offset_aligned, alignment); | |
2525 | *y = (offset % alignment) / pitch; | |
2526 | *x = ((offset % alignment) - *y * pitch) / cpp; | |
2527 | } else { | |
2528 | *y = *x = 0; | |
2529 | } | |
bc752862 | 2530 | } |
29cf9491 VS |
2531 | |
2532 | return offset_aligned; | |
c2c75131 DV |
2533 | } |
2534 | ||
6d19a44c VS |
2535 | static u32 intel_plane_compute_aligned_offset(int *x, int *y, |
2536 | const struct intel_plane_state *state, | |
5d2a1950 | 2537 | int color_plane) |
6687c906 | 2538 | { |
f90a85e7 | 2539 | struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); |
1e7b4fd8 | 2540 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
7b3cb17a ML |
2541 | const struct drm_framebuffer *fb = state->hw.fb; |
2542 | unsigned int rotation = state->hw.rotation; | |
5d2a1950 | 2543 | int pitch = state->color_plane[color_plane].stride; |
1e7b4fd8 VS |
2544 | u32 alignment; |
2545 | ||
2546 | if (intel_plane->id == PLANE_CURSOR) | |
2547 | alignment = intel_cursor_alignment(dev_priv); | |
2548 | else | |
5d2a1950 | 2549 | alignment = intel_surf_alignment(fb, color_plane); |
6687c906 | 2550 | |
5d2a1950 | 2551 | return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane, |
6d19a44c | 2552 | pitch, rotation, alignment); |
6687c906 VS |
2553 | } |
2554 | ||
303ba695 VS |
2555 | /* Convert the fb->offset[] into x/y offsets */ |
2556 | static int intel_fb_offset_to_xy(int *x, int *y, | |
5d2a1950 VS |
2557 | const struct drm_framebuffer *fb, |
2558 | int color_plane) | |
6687c906 | 2559 | { |
303ba695 | 2560 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
70bbe53c | 2561 | unsigned int height; |
d156135e ID |
2562 | u32 alignment; |
2563 | ||
2564 | if (INTEL_GEN(dev_priv) >= 12 && | |
2565 | is_semiplanar_uv_plane(fb, color_plane)) | |
2566 | alignment = intel_tile_row_size(fb, color_plane); | |
2567 | else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) | |
2568 | alignment = intel_tile_size(dev_priv); | |
2569 | else | |
2570 | alignment = 0; | |
6687c906 | 2571 | |
d156135e | 2572 | if (alignment != 0 && fb->offsets[color_plane] % alignment) { |
cd49f818 WK |
2573 | drm_dbg_kms(&dev_priv->drm, |
2574 | "Misaligned offset 0x%08x for color plane %d\n", | |
2575 | fb->offsets[color_plane], color_plane); | |
303ba695 | 2576 | return -EINVAL; |
70bbe53c VS |
2577 | } |
2578 | ||
2579 | height = drm_framebuffer_plane_height(fb->height, fb, color_plane); | |
2580 | height = ALIGN(height, intel_tile_height(fb, color_plane)); | |
2581 | ||
2582 | /* Catch potential overflows early */ | |
2583 | if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), | |
2584 | fb->offsets[color_plane])) { | |
cd49f818 WK |
2585 | drm_dbg_kms(&dev_priv->drm, |
2586 | "Bad offset 0x%08x or pitch %d for color plane %d\n", | |
2587 | fb->offsets[color_plane], fb->pitches[color_plane], | |
2588 | color_plane); | |
70bbe53c VS |
2589 | return -ERANGE; |
2590 | } | |
303ba695 VS |
2591 | |
2592 | *x = 0; | |
2593 | *y = 0; | |
2594 | ||
6d19a44c | 2595 | intel_adjust_aligned_offset(x, y, |
5d2a1950 VS |
2596 | fb, color_plane, DRM_MODE_ROTATE_0, |
2597 | fb->pitches[color_plane], | |
2598 | fb->offsets[color_plane], 0); | |
303ba695 VS |
2599 | |
2600 | return 0; | |
6687c906 VS |
2601 | } |
2602 | ||
ba3f4d0a | 2603 | static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) |
72618ebf VS |
2604 | { |
2605 | switch (fb_modifier) { | |
2606 | case I915_FORMAT_MOD_X_TILED: | |
2607 | return I915_TILING_X; | |
2608 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2609 | case I915_FORMAT_MOD_Y_TILED_CCS: |
b3e57bcc | 2610 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2dfbf9d2 | 2611 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
72618ebf VS |
2612 | return I915_TILING_Y; |
2613 | default: | |
2614 | return I915_TILING_NONE; | |
2615 | } | |
2616 | } | |
2617 | ||
16af25fa VS |
2618 | /* |
2619 | * From the Sky Lake PRM: | |
2620 | * "The Color Control Surface (CCS) contains the compression status of | |
2621 | * the cache-line pairs. The compression state of the cache-line pair | |
2622 | * is specified by 2 bits in the CCS. Each CCS cache-line represents | |
2623 | * an area on the main surface of 16 x16 sets of 128 byte Y-tiled | |
2624 | * cache-line-pairs. CCS is always Y tiled." | |
2625 | * | |
2626 | * Since cache line pairs refers to horizontally adjacent cache lines, | |
2627 | * each cache line in the CCS corresponds to an area of 32x16 cache | |
2628 | * lines on the main surface. Since each pixel is 4 bytes, this gives | |
2629 | * us a ratio of one byte in the CCS for each 8x16 pixels in the | |
2630 | * main surface. | |
2631 | */ | |
b3e57bcc | 2632 | static const struct drm_format_info skl_ccs_formats[] = { |
38f30041 VS |
2633 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, |
2634 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2635 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, | |
2636 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2637 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, | |
2638 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, | |
2639 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, | |
2640 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, | |
bbfb6ce8 VS |
2641 | }; |
2642 | ||
b3e57bcc DP |
2643 | /* |
2644 | * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the | |
2645 | * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles | |
2646 | * in the main surface. With 4 byte pixels and each Y-tile having dimensions of | |
2647 | * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in | |
2648 | * the main surface. | |
2649 | */ | |
2650 | static const struct drm_format_info gen12_ccs_formats[] = { | |
2651 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, | |
2652 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2653 | .hsub = 1, .vsub = 1, }, | |
2654 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, | |
2655 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2656 | .hsub = 1, .vsub = 1, }, | |
2657 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, | |
2658 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2659 | .hsub = 1, .vsub = 1, .has_alpha = true }, | |
2660 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, | |
2661 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2662 | .hsub = 1, .vsub = 1, .has_alpha = true }, | |
2dfbf9d2 DP |
2663 | { .format = DRM_FORMAT_YUYV, .num_planes = 2, |
2664 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2665 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2666 | { .format = DRM_FORMAT_YVYU, .num_planes = 2, | |
2667 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2668 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2669 | { .format = DRM_FORMAT_UYVY, .num_planes = 2, | |
2670 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2671 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2672 | { .format = DRM_FORMAT_VYUY, .num_planes = 2, | |
2673 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2674 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2675 | { .format = DRM_FORMAT_NV12, .num_planes = 4, | |
2676 | .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, | |
2677 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2678 | { .format = DRM_FORMAT_P010, .num_planes = 4, | |
2679 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2680 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2681 | { .format = DRM_FORMAT_P012, .num_planes = 4, | |
2682 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2683 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2684 | { .format = DRM_FORMAT_P016, .num_planes = 4, | |
2685 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2686 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
b3e57bcc DP |
2687 | }; |
2688 | ||
bbfb6ce8 VS |
2689 | static const struct drm_format_info * |
2690 | lookup_format_info(const struct drm_format_info formats[], | |
2691 | int num_formats, u32 format) | |
2692 | { | |
2693 | int i; | |
2694 | ||
2695 | for (i = 0; i < num_formats; i++) { | |
2696 | if (formats[i].format == format) | |
2697 | return &formats[i]; | |
2698 | } | |
2699 | ||
2700 | return NULL; | |
2701 | } | |
2702 | ||
2703 | static const struct drm_format_info * | |
2704 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2705 | { | |
2706 | switch (cmd->modifier[0]) { | |
2707 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2708 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
b3e57bcc DP |
2709 | return lookup_format_info(skl_ccs_formats, |
2710 | ARRAY_SIZE(skl_ccs_formats), | |
2711 | cmd->pixel_format); | |
2712 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: | |
2dfbf9d2 | 2713 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
b3e57bcc DP |
2714 | return lookup_format_info(gen12_ccs_formats, |
2715 | ARRAY_SIZE(gen12_ccs_formats), | |
bbfb6ce8 VS |
2716 | cmd->pixel_format); |
2717 | default: | |
2718 | return NULL; | |
2719 | } | |
2720 | } | |
2721 | ||
63eaf9ac DP |
2722 | bool is_ccs_modifier(u64 modifier) |
2723 | { | |
b3e57bcc | 2724 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || |
2dfbf9d2 | 2725 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || |
b3e57bcc | 2726 | modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
63eaf9ac DP |
2727 | modifier == I915_FORMAT_MOD_Yf_TILED_CCS; |
2728 | } | |
2729 | ||
71df86f0 ID |
2730 | static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane) |
2731 | { | |
2732 | return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], | |
2733 | 512) * 64; | |
2734 | } | |
2735 | ||
54d4d719 VS |
2736 | u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, |
2737 | u32 pixel_format, u64 modifier) | |
a88c40eb VS |
2738 | { |
2739 | struct intel_crtc *crtc; | |
2740 | struct intel_plane *plane; | |
2741 | ||
2742 | /* | |
2743 | * We assume the primary plane for pipe A has | |
eae3da27 AG |
2744 | * the highest stride limits of them all, |
2745 | * if in case pipe A is disabled, use the first pipe from pipe_mask. | |
a88c40eb | 2746 | */ |
eae3da27 | 2747 | crtc = intel_get_first_crtc(dev_priv); |
baea9ffe VS |
2748 | if (!crtc) |
2749 | return 0; | |
2750 | ||
a88c40eb VS |
2751 | plane = to_intel_plane(crtc->base.primary); |
2752 | ||
2753 | return plane->max_stride(plane, pixel_format, modifier, | |
2754 | DRM_MODE_ROTATE_0); | |
2755 | } | |
2756 | ||
54d4d719 VS |
2757 | static |
2758 | u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, | |
2759 | u32 pixel_format, u64 modifier) | |
2760 | { | |
20330129 VS |
2761 | /* |
2762 | * Arbitrary limit for gen4+ chosen to match the | |
2763 | * render engine max stride. | |
2764 | * | |
2765 | * The new CCS hash mode makes remapping impossible | |
2766 | */ | |
2767 | if (!is_ccs_modifier(modifier)) { | |
2768 | if (INTEL_GEN(dev_priv) >= 7) | |
2769 | return 256*1024; | |
2770 | else if (INTEL_GEN(dev_priv) >= 4) | |
2771 | return 128*1024; | |
2772 | } | |
2773 | ||
54d4d719 VS |
2774 | return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); |
2775 | } | |
2776 | ||
a88c40eb VS |
2777 | static u32 |
2778 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) | |
2779 | { | |
54d4d719 | 2780 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
b3e57bcc | 2781 | u32 tile_width; |
54d4d719 | 2782 | |
b3e57bcc | 2783 | if (is_surface_linear(fb, color_plane)) { |
54d4d719 VS |
2784 | u32 max_stride = intel_plane_fb_max_stride(dev_priv, |
2785 | fb->format->format, | |
2786 | fb->modifier); | |
2787 | ||
2788 | /* | |
2789 | * To make remapping with linear generally feasible | |
2790 | * we need the stride to be page aligned. | |
2791 | */ | |
b3e57bcc DP |
2792 | if (fb->pitches[color_plane] > max_stride && |
2793 | !is_ccs_modifier(fb->modifier)) | |
54d4d719 VS |
2794 | return intel_tile_size(dev_priv); |
2795 | else | |
2796 | return 64; | |
b3e57bcc | 2797 | } |
86f236bb | 2798 | |
b3e57bcc | 2799 | tile_width = intel_tile_width_bytes(fb, color_plane); |
2dfbf9d2 | 2800 | if (is_ccs_modifier(fb->modifier)) { |
86f236bb DP |
2801 | /* |
2802 | * Display WA #0531: skl,bxt,kbl,glk | |
2803 | * | |
2804 | * Render decompression and plane width > 3840 | |
2805 | * combined with horizontal panning requires the | |
2806 | * plane stride to be a multiple of 4. We'll just | |
2807 | * require the entire fb to accommodate that to avoid | |
2808 | * potential runtime errors at plane configuration time. | |
2809 | */ | |
2dfbf9d2 | 2810 | if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840) |
b3e57bcc DP |
2811 | tile_width *= 4; |
2812 | /* | |
2813 | * The main surface pitch must be padded to a multiple of four | |
2814 | * tile widths. | |
2815 | */ | |
2816 | else if (INTEL_GEN(dev_priv) >= 12) | |
86f236bb | 2817 | tile_width *= 4; |
54d4d719 | 2818 | } |
b3e57bcc | 2819 | return tile_width; |
54d4d719 VS |
2820 | } |
2821 | ||
2822 | bool intel_plane_can_remap(const struct intel_plane_state *plane_state) | |
2823 | { | |
f90a85e7 | 2824 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
54d4d719 | 2825 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 2826 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
54d4d719 VS |
2827 | int i; |
2828 | ||
2829 | /* We don't want to deal with remapping with cursors */ | |
2830 | if (plane->id == PLANE_CURSOR) | |
2831 | return false; | |
2832 | ||
2833 | /* | |
2834 | * The display engine limits already match/exceed the | |
2835 | * render engine limits, so not much point in remapping. | |
2836 | * Would also need to deal with the fence POT alignment | |
2837 | * and gen2 2KiB GTT tile size. | |
2838 | */ | |
2839 | if (INTEL_GEN(dev_priv) < 4) | |
2840 | return false; | |
2841 | ||
2842 | /* | |
2843 | * The new CCS hash mode isn't compatible with remapping as | |
2844 | * the virtual address of the pages affects the compressed data. | |
2845 | */ | |
2846 | if (is_ccs_modifier(fb->modifier)) | |
2847 | return false; | |
2848 | ||
2849 | /* Linear needs a page aligned stride for remapping */ | |
2850 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { | |
2851 | unsigned int alignment = intel_tile_size(dev_priv) - 1; | |
2852 | ||
2853 | for (i = 0; i < fb->format->num_planes; i++) { | |
2854 | if (fb->pitches[i] & alignment) | |
2855 | return false; | |
2856 | } | |
2857 | } | |
2858 | ||
2859 | return true; | |
2860 | } | |
2861 | ||
2862 | static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) | |
2863 | { | |
f90a85e7 | 2864 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
7b3cb17a ML |
2865 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
2866 | unsigned int rotation = plane_state->hw.rotation; | |
54d4d719 VS |
2867 | u32 stride, max_stride; |
2868 | ||
2869 | /* | |
2870 | * No remapping for invisible planes since we don't have | |
2871 | * an actual source viewport to remap. | |
2872 | */ | |
f90a85e7 | 2873 | if (!plane_state->uapi.visible) |
54d4d719 VS |
2874 | return false; |
2875 | ||
2876 | if (!intel_plane_can_remap(plane_state)) | |
2877 | return false; | |
2878 | ||
2879 | /* | |
2880 | * FIXME: aux plane limits on gen9+ are | |
2881 | * unclear in Bspec, for now no checking. | |
2882 | */ | |
2883 | stride = intel_fb_pitch(fb, 0, rotation); | |
2884 | max_stride = plane->max_stride(plane, fb->format->format, | |
2885 | fb->modifier, rotation); | |
2886 | ||
2887 | return stride > max_stride; | |
a88c40eb VS |
2888 | } |
2889 | ||
b3e57bcc DP |
2890 | static void |
2891 | intel_fb_plane_get_subsampling(int *hsub, int *vsub, | |
2892 | const struct drm_framebuffer *fb, | |
2893 | int color_plane) | |
2894 | { | |
2895 | int main_plane; | |
2896 | ||
2897 | if (color_plane == 0) { | |
2898 | *hsub = 1; | |
2899 | *vsub = 1; | |
2900 | ||
2901 | return; | |
2902 | } | |
2903 | ||
2904 | /* | |
2905 | * TODO: Deduct the subsampling from the char block for all CCS | |
2906 | * formats and planes. | |
2907 | */ | |
2908 | if (!is_gen12_ccs_plane(fb, color_plane)) { | |
2909 | *hsub = fb->format->hsub; | |
2910 | *vsub = fb->format->vsub; | |
2911 | ||
2912 | return; | |
2913 | } | |
2914 | ||
2915 | main_plane = ccs_to_main_plane(fb, color_plane); | |
2916 | *hsub = drm_format_info_block_width(fb->format, color_plane) / | |
2917 | drm_format_info_block_width(fb->format, main_plane); | |
2918 | ||
2919 | /* | |
2920 | * The min stride check in the core framebuffer_check() function | |
2921 | * assumes that format->hsub applies to every plane except for the | |
2922 | * first plane. That's incorrect for the CCS AUX plane of the first | |
2923 | * plane, but for the above check to pass we must define the block | |
2924 | * width with that subsampling applied to it. Adjust the width here | |
2925 | * accordingly, so we can calculate the actual subsampling factor. | |
2926 | */ | |
2927 | if (main_plane == 0) | |
2928 | *hsub *= fb->format->hsub; | |
2929 | ||
2930 | *vsub = 32; | |
2931 | } | |
13f2cb9a DP |
2932 | static int |
2933 | intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y) | |
2934 | { | |
3dfd8d71 | 2935 | struct drm_i915_private *i915 = to_i915(fb->dev); |
13f2cb9a | 2936 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
b3e57bcc DP |
2937 | int main_plane; |
2938 | int hsub, vsub; | |
13f2cb9a DP |
2939 | int tile_width, tile_height; |
2940 | int ccs_x, ccs_y; | |
2941 | int main_x, main_y; | |
2942 | ||
b3e57bcc | 2943 | if (!is_ccs_plane(fb, ccs_plane)) |
13f2cb9a DP |
2944 | return 0; |
2945 | ||
b3e57bcc DP |
2946 | intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height); |
2947 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); | |
13f2cb9a DP |
2948 | |
2949 | tile_width *= hsub; | |
2950 | tile_height *= vsub; | |
2951 | ||
2952 | ccs_x = (x * hsub) % tile_width; | |
2953 | ccs_y = (y * vsub) % tile_height; | |
b3e57bcc DP |
2954 | |
2955 | main_plane = ccs_to_main_plane(fb, ccs_plane); | |
2956 | main_x = intel_fb->normal[main_plane].x % tile_width; | |
2957 | main_y = intel_fb->normal[main_plane].y % tile_height; | |
13f2cb9a DP |
2958 | |
2959 | /* | |
2960 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2961 | * x/y offsets must match between CCS and the main surface. | |
2962 | */ | |
2963 | if (main_x != ccs_x || main_y != ccs_y) { | |
3dfd8d71 JN |
2964 | drm_dbg_kms(&i915->drm, |
2965 | "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
13f2cb9a DP |
2966 | main_x, main_y, |
2967 | ccs_x, ccs_y, | |
b3e57bcc DP |
2968 | intel_fb->normal[main_plane].x, |
2969 | intel_fb->normal[main_plane].y, | |
13f2cb9a DP |
2970 | x, y); |
2971 | return -EINVAL; | |
2972 | } | |
2973 | ||
2974 | return 0; | |
2975 | } | |
2976 | ||
b3e57bcc DP |
2977 | static void |
2978 | intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane) | |
2979 | { | |
577687bf ID |
2980 | int main_plane = is_ccs_plane(fb, color_plane) ? |
2981 | ccs_to_main_plane(fb, color_plane) : 0; | |
2982 | int main_hsub, main_vsub; | |
b3e57bcc DP |
2983 | int hsub, vsub; |
2984 | ||
577687bf | 2985 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane); |
b3e57bcc | 2986 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane); |
577687bf ID |
2987 | *w = fb->width / main_hsub / hsub; |
2988 | *h = fb->height / main_vsub / vsub; | |
b3e57bcc DP |
2989 | } |
2990 | ||
931cd348 DP |
2991 | /* |
2992 | * Setup the rotated view for an FB plane and return the size the GTT mapping | |
2993 | * requires for this view. | |
2994 | */ | |
2995 | static u32 | |
2996 | setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info, | |
2997 | u32 gtt_offset_rotated, int x, int y, | |
2998 | unsigned int width, unsigned int height, | |
2999 | unsigned int tile_size, | |
3000 | unsigned int tile_width, unsigned int tile_height, | |
3001 | struct drm_framebuffer *fb) | |
3002 | { | |
3003 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
3004 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
3005 | unsigned int pitch_tiles; | |
3006 | struct drm_rect r; | |
3007 | ||
3008 | /* Y or Yf modifiers required for 90/270 rotation */ | |
3009 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && | |
3010 | fb->modifier != I915_FORMAT_MOD_Yf_TILED) | |
3011 | return 0; | |
3012 | ||
ce04ecd9 | 3013 | if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane))) |
931cd348 DP |
3014 | return 0; |
3015 | ||
3016 | rot_info->plane[plane] = *plane_info; | |
3017 | ||
3018 | intel_fb->rotated[plane].pitch = plane_info->height * tile_height; | |
3019 | ||
3020 | /* rotate the x/y offsets to match the GTT view */ | |
3021 | drm_rect_init(&r, x, y, width, height); | |
3022 | drm_rect_rotate(&r, | |
3023 | plane_info->width * tile_width, | |
3024 | plane_info->height * tile_height, | |
3025 | DRM_MODE_ROTATE_270); | |
3026 | x = r.x1; | |
3027 | y = r.y1; | |
3028 | ||
3029 | /* rotate the tile dimensions to match the GTT view */ | |
3030 | pitch_tiles = intel_fb->rotated[plane].pitch / tile_height; | |
3031 | swap(tile_width, tile_height); | |
3032 | ||
3033 | /* | |
3034 | * We only keep the x/y offsets, so push all of the | |
3035 | * gtt offset into the x/y offsets. | |
3036 | */ | |
3037 | intel_adjust_tile_offset(&x, &y, | |
3038 | tile_width, tile_height, | |
3039 | tile_size, pitch_tiles, | |
3040 | gtt_offset_rotated * tile_size, 0); | |
3041 | ||
3042 | /* | |
3043 | * First pixel of the framebuffer from | |
3044 | * the start of the rotated gtt mapping. | |
3045 | */ | |
3046 | intel_fb->rotated[plane].x = x; | |
3047 | intel_fb->rotated[plane].y = y; | |
3048 | ||
3049 | return plane_info->width * plane_info->height; | |
3050 | } | |
3051 | ||
6687c906 VS |
3052 | static int |
3053 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
3054 | struct drm_framebuffer *fb) | |
3055 | { | |
3056 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
a5ff7a45 | 3057 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6687c906 VS |
3058 | u32 gtt_offset_rotated = 0; |
3059 | unsigned int max_size = 0; | |
bcb0b461 | 3060 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
3061 | unsigned int tile_size = intel_tile_size(dev_priv); |
3062 | ||
3063 | for (i = 0; i < num_planes; i++) { | |
3064 | unsigned int width, height; | |
3065 | unsigned int cpp, size; | |
3066 | u32 offset; | |
3067 | int x, y; | |
303ba695 | 3068 | int ret; |
6687c906 | 3069 | |
353c8598 | 3070 | cpp = fb->format->cpp[i]; |
b3e57bcc | 3071 | intel_fb_plane_dims(&width, &height, fb, i); |
6687c906 | 3072 | |
303ba695 VS |
3073 | ret = intel_fb_offset_to_xy(&x, &y, fb, i); |
3074 | if (ret) { | |
cd49f818 WK |
3075 | drm_dbg_kms(&dev_priv->drm, |
3076 | "bad fb plane %d offset: 0x%x\n", | |
3077 | i, fb->offsets[i]); | |
303ba695 VS |
3078 | return ret; |
3079 | } | |
6687c906 | 3080 | |
13f2cb9a DP |
3081 | ret = intel_fb_check_ccs_xy(fb, i, x, y); |
3082 | if (ret) | |
3083 | return ret; | |
2e2adb05 | 3084 | |
60d5f2a4 VS |
3085 | /* |
3086 | * The fence (if used) is aligned to the start of the object | |
3087 | * so having the framebuffer wrap around across the edge of the | |
3088 | * fenced region doesn't really work. We have no API to configure | |
3089 | * the fence start offset within the object (nor could we probably | |
3090 | * on gen2/3). So it's just easier if we just require that the | |
3091 | * fb layout agrees with the fence layout. We already check that the | |
3092 | * fb stride matches the fence stride elsewhere. | |
3093 | */ | |
a5ff7a45 | 3094 | if (i == 0 && i915_gem_object_is_tiled(obj) && |
60d5f2a4 | 3095 | (x + width) * cpp > fb->pitches[i]) { |
cd49f818 WK |
3096 | drm_dbg_kms(&dev_priv->drm, |
3097 | "bad fb plane %d offset: 0x%x\n", | |
3098 | i, fb->offsets[i]); | |
60d5f2a4 VS |
3099 | return -EINVAL; |
3100 | } | |
3101 | ||
6687c906 VS |
3102 | /* |
3103 | * First pixel of the framebuffer from | |
3104 | * the start of the normal gtt mapping. | |
3105 | */ | |
3106 | intel_fb->normal[i].x = x; | |
3107 | intel_fb->normal[i].y = y; | |
3108 | ||
6d19a44c VS |
3109 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i, |
3110 | fb->pitches[i], | |
3111 | DRM_MODE_ROTATE_0, | |
3112 | tile_size); | |
6687c906 VS |
3113 | offset /= tile_size; |
3114 | ||
b3e57bcc | 3115 | if (!is_surface_linear(fb, i)) { |
931cd348 | 3116 | struct intel_remapped_plane_info plane_info; |
6687c906 | 3117 | unsigned int tile_width, tile_height; |
6687c906 | 3118 | |
d88c4afd | 3119 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 | 3120 | |
931cd348 DP |
3121 | plane_info.offset = offset; |
3122 | plane_info.stride = DIV_ROUND_UP(fb->pitches[i], | |
3123 | tile_width * cpp); | |
3124 | plane_info.width = DIV_ROUND_UP(x + width, tile_width); | |
3125 | plane_info.height = DIV_ROUND_UP(y + height, | |
3126 | tile_height); | |
6687c906 VS |
3127 | |
3128 | /* how many tiles does this plane need */ | |
931cd348 | 3129 | size = plane_info.stride * plane_info.height; |
6687c906 VS |
3130 | /* |
3131 | * If the plane isn't horizontally tile aligned, | |
3132 | * we need one more tile. | |
3133 | */ | |
3134 | if (x != 0) | |
3135 | size++; | |
3136 | ||
931cd348 DP |
3137 | gtt_offset_rotated += |
3138 | setup_fb_rotation(i, &plane_info, | |
3139 | gtt_offset_rotated, | |
3140 | x, y, width, height, | |
3141 | tile_size, | |
3142 | tile_width, tile_height, | |
3143 | fb); | |
6687c906 VS |
3144 | } else { |
3145 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
3146 | x * cpp, tile_size); | |
3147 | } | |
3148 | ||
3149 | /* how many tiles in total needed in the bo */ | |
3150 | max_size = max(max_size, offset + size); | |
3151 | } | |
3152 | ||
4e05047d | 3153 | if (mul_u32_u32(max_size, tile_size) > obj->base.size) { |
cd49f818 WK |
3154 | drm_dbg_kms(&dev_priv->drm, |
3155 | "fb too big for bo (need %llu bytes, have %zu bytes)\n", | |
3156 | mul_u32_u32(max_size, tile_size), obj->base.size); | |
6687c906 VS |
3157 | return -EINVAL; |
3158 | } | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
54d4d719 VS |
3163 | static void |
3164 | intel_plane_remap_gtt(struct intel_plane_state *plane_state) | |
3165 | { | |
3166 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 3167 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 3168 | struct drm_framebuffer *fb = plane_state->hw.fb; |
54d4d719 VS |
3169 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
3170 | struct intel_rotation_info *info = &plane_state->view.rotated; | |
7b3cb17a | 3171 | unsigned int rotation = plane_state->hw.rotation; |
54d4d719 VS |
3172 | int i, num_planes = fb->format->num_planes; |
3173 | unsigned int tile_size = intel_tile_size(dev_priv); | |
3174 | unsigned int src_x, src_y; | |
3175 | unsigned int src_w, src_h; | |
3176 | u32 gtt_offset = 0; | |
3177 | ||
3178 | memset(&plane_state->view, 0, sizeof(plane_state->view)); | |
3179 | plane_state->view.type = drm_rotation_90_or_270(rotation) ? | |
3180 | I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED; | |
3181 | ||
f90a85e7 ML |
3182 | src_x = plane_state->uapi.src.x1 >> 16; |
3183 | src_y = plane_state->uapi.src.y1 >> 16; | |
3184 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; | |
3185 | src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
54d4d719 | 3186 | |
e57291c2 | 3187 | drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier)); |
54d4d719 VS |
3188 | |
3189 | /* Make src coordinates relative to the viewport */ | |
f90a85e7 | 3190 | drm_rect_translate(&plane_state->uapi.src, |
54d4d719 VS |
3191 | -(src_x << 16), -(src_y << 16)); |
3192 | ||
3193 | /* Rotate src coordinates to match rotated GTT view */ | |
3194 | if (drm_rotation_90_or_270(rotation)) | |
f90a85e7 | 3195 | drm_rect_rotate(&plane_state->uapi.src, |
54d4d719 VS |
3196 | src_w << 16, src_h << 16, |
3197 | DRM_MODE_ROTATE_270); | |
3198 | ||
3199 | for (i = 0; i < num_planes; i++) { | |
3200 | unsigned int hsub = i ? fb->format->hsub : 1; | |
3201 | unsigned int vsub = i ? fb->format->vsub : 1; | |
3202 | unsigned int cpp = fb->format->cpp[i]; | |
3203 | unsigned int tile_width, tile_height; | |
3204 | unsigned int width, height; | |
3205 | unsigned int pitch_tiles; | |
3206 | unsigned int x, y; | |
3207 | u32 offset; | |
3208 | ||
3209 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
3210 | ||
3211 | x = src_x / hsub; | |
3212 | y = src_y / vsub; | |
3213 | width = src_w / hsub; | |
3214 | height = src_h / vsub; | |
3215 | ||
3216 | /* | |
3217 | * First pixel of the src viewport from the | |
3218 | * start of the normal gtt mapping. | |
3219 | */ | |
3220 | x += intel_fb->normal[i].x; | |
3221 | y += intel_fb->normal[i].y; | |
3222 | ||
3223 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, | |
3224 | fb, i, fb->pitches[i], | |
3225 | DRM_MODE_ROTATE_0, tile_size); | |
3226 | offset /= tile_size; | |
3227 | ||
e57291c2 | 3228 | drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane)); |
54d4d719 VS |
3229 | info->plane[i].offset = offset; |
3230 | info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], | |
3231 | tile_width * cpp); | |
3232 | info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
3233 | info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
3234 | ||
3235 | if (drm_rotation_90_or_270(rotation)) { | |
3236 | struct drm_rect r; | |
3237 | ||
3238 | /* rotate the x/y offsets to match the GTT view */ | |
fc1a0fb5 | 3239 | drm_rect_init(&r, x, y, width, height); |
54d4d719 VS |
3240 | drm_rect_rotate(&r, |
3241 | info->plane[i].width * tile_width, | |
3242 | info->plane[i].height * tile_height, | |
3243 | DRM_MODE_ROTATE_270); | |
3244 | x = r.x1; | |
3245 | y = r.y1; | |
3246 | ||
3247 | pitch_tiles = info->plane[i].height; | |
3248 | plane_state->color_plane[i].stride = pitch_tiles * tile_height; | |
3249 | ||
3250 | /* rotate the tile dimensions to match the GTT view */ | |
3251 | swap(tile_width, tile_height); | |
3252 | } else { | |
3253 | pitch_tiles = info->plane[i].width; | |
3254 | plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp; | |
3255 | } | |
3256 | ||
3257 | /* | |
3258 | * We only keep the x/y offsets, so push all of the | |
3259 | * gtt offset into the x/y offsets. | |
3260 | */ | |
3261 | intel_adjust_tile_offset(&x, &y, | |
3262 | tile_width, tile_height, | |
3263 | tile_size, pitch_tiles, | |
3264 | gtt_offset * tile_size, 0); | |
3265 | ||
3266 | gtt_offset += info->plane[i].width * info->plane[i].height; | |
3267 | ||
3268 | plane_state->color_plane[i].offset = 0; | |
3269 | plane_state->color_plane[i].x = x; | |
3270 | plane_state->color_plane[i].y = y; | |
3271 | } | |
3272 | } | |
3273 | ||
3274 | static int | |
3275 | intel_plane_compute_gtt(struct intel_plane_state *plane_state) | |
3276 | { | |
3277 | const struct intel_framebuffer *fb = | |
7b3cb17a ML |
3278 | to_intel_framebuffer(plane_state->hw.fb); |
3279 | unsigned int rotation = plane_state->hw.rotation; | |
54d4d719 VS |
3280 | int i, num_planes; |
3281 | ||
3282 | if (!fb) | |
3283 | return 0; | |
3284 | ||
3285 | num_planes = fb->base.format->num_planes; | |
3286 | ||
3287 | if (intel_plane_needs_remap(plane_state)) { | |
3288 | intel_plane_remap_gtt(plane_state); | |
3289 | ||
3290 | /* | |
3291 | * Sometimes even remapping can't overcome | |
3292 | * the stride limitations :( Can happen with | |
3293 | * big plane sizes and suitably misaligned | |
3294 | * offsets. | |
3295 | */ | |
3296 | return intel_plane_check_stride(plane_state); | |
3297 | } | |
3298 | ||
3299 | intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation); | |
3300 | ||
3301 | for (i = 0; i < num_planes; i++) { | |
3302 | plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation); | |
3303 | plane_state->color_plane[i].offset = 0; | |
3304 | ||
3305 | if (drm_rotation_90_or_270(rotation)) { | |
3306 | plane_state->color_plane[i].x = fb->rotated[i].x; | |
3307 | plane_state->color_plane[i].y = fb->rotated[i].y; | |
3308 | } else { | |
3309 | plane_state->color_plane[i].x = fb->normal[i].x; | |
3310 | plane_state->color_plane[i].y = fb->normal[i].y; | |
3311 | } | |
3312 | } | |
3313 | ||
3314 | /* Rotate src coordinates to match rotated GTT view */ | |
3315 | if (drm_rotation_90_or_270(rotation)) | |
f90a85e7 | 3316 | drm_rect_rotate(&plane_state->uapi.src, |
54d4d719 VS |
3317 | fb->base.width << 16, fb->base.height << 16, |
3318 | DRM_MODE_ROTATE_270); | |
3319 | ||
3320 | return intel_plane_check_stride(plane_state); | |
3321 | } | |
3322 | ||
b35d63fa | 3323 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
3324 | { |
3325 | switch (format) { | |
3326 | case DISPPLANE_8BPP: | |
3327 | return DRM_FORMAT_C8; | |
73263cb6 VS |
3328 | case DISPPLANE_BGRA555: |
3329 | return DRM_FORMAT_ARGB1555; | |
46f297fb JB |
3330 | case DISPPLANE_BGRX555: |
3331 | return DRM_FORMAT_XRGB1555; | |
3332 | case DISPPLANE_BGRX565: | |
3333 | return DRM_FORMAT_RGB565; | |
3334 | default: | |
3335 | case DISPPLANE_BGRX888: | |
3336 | return DRM_FORMAT_XRGB8888; | |
3337 | case DISPPLANE_RGBX888: | |
3338 | return DRM_FORMAT_XBGR8888; | |
73263cb6 VS |
3339 | case DISPPLANE_BGRA888: |
3340 | return DRM_FORMAT_ARGB8888; | |
3341 | case DISPPLANE_RGBA888: | |
3342 | return DRM_FORMAT_ABGR8888; | |
46f297fb JB |
3343 | case DISPPLANE_BGRX101010: |
3344 | return DRM_FORMAT_XRGB2101010; | |
3345 | case DISPPLANE_RGBX101010: | |
3346 | return DRM_FORMAT_XBGR2101010; | |
73263cb6 VS |
3347 | case DISPPLANE_BGRA101010: |
3348 | return DRM_FORMAT_ARGB2101010; | |
3349 | case DISPPLANE_RGBA101010: | |
3350 | return DRM_FORMAT_ABGR2101010; | |
03b0ce95 VS |
3351 | case DISPPLANE_RGBX161616: |
3352 | return DRM_FORMAT_XBGR16161616F; | |
46f297fb JB |
3353 | } |
3354 | } | |
3355 | ||
ddf34319 | 3356 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
bc8d7dff DL |
3357 | { |
3358 | switch (format) { | |
3359 | case PLANE_CTL_FORMAT_RGB_565: | |
3360 | return DRM_FORMAT_RGB565; | |
f34a291c MK |
3361 | case PLANE_CTL_FORMAT_NV12: |
3362 | return DRM_FORMAT_NV12; | |
da904174 SL |
3363 | case PLANE_CTL_FORMAT_XYUV: |
3364 | return DRM_FORMAT_XYUV8888; | |
df7d4156 JPH |
3365 | case PLANE_CTL_FORMAT_P010: |
3366 | return DRM_FORMAT_P010; | |
3367 | case PLANE_CTL_FORMAT_P012: | |
3368 | return DRM_FORMAT_P012; | |
3369 | case PLANE_CTL_FORMAT_P016: | |
3370 | return DRM_FORMAT_P016; | |
296e9b19 SS |
3371 | case PLANE_CTL_FORMAT_Y210: |
3372 | return DRM_FORMAT_Y210; | |
3373 | case PLANE_CTL_FORMAT_Y212: | |
3374 | return DRM_FORMAT_Y212; | |
3375 | case PLANE_CTL_FORMAT_Y216: | |
3376 | return DRM_FORMAT_Y216; | |
3377 | case PLANE_CTL_FORMAT_Y410: | |
ff01e697 | 3378 | return DRM_FORMAT_XVYU2101010; |
296e9b19 | 3379 | case PLANE_CTL_FORMAT_Y412: |
ff01e697 | 3380 | return DRM_FORMAT_XVYU12_16161616; |
296e9b19 | 3381 | case PLANE_CTL_FORMAT_Y416: |
ff01e697 | 3382 | return DRM_FORMAT_XVYU16161616; |
bc8d7dff DL |
3383 | default: |
3384 | case PLANE_CTL_FORMAT_XRGB_8888: | |
3385 | if (rgb_order) { | |
3386 | if (alpha) | |
3387 | return DRM_FORMAT_ABGR8888; | |
3388 | else | |
3389 | return DRM_FORMAT_XBGR8888; | |
3390 | } else { | |
3391 | if (alpha) | |
3392 | return DRM_FORMAT_ARGB8888; | |
3393 | else | |
3394 | return DRM_FORMAT_XRGB8888; | |
3395 | } | |
3396 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
f9c43a31 VS |
3397 | if (rgb_order) { |
3398 | if (alpha) | |
3399 | return DRM_FORMAT_ABGR2101010; | |
3400 | else | |
3401 | return DRM_FORMAT_XBGR2101010; | |
3402 | } else { | |
3403 | if (alpha) | |
3404 | return DRM_FORMAT_ARGB2101010; | |
3405 | else | |
3406 | return DRM_FORMAT_XRGB2101010; | |
3407 | } | |
a94bed60 KS |
3408 | case PLANE_CTL_FORMAT_XRGB_16161616F: |
3409 | if (rgb_order) { | |
3410 | if (alpha) | |
3411 | return DRM_FORMAT_ABGR16161616F; | |
3412 | else | |
3413 | return DRM_FORMAT_XBGR16161616F; | |
3414 | } else { | |
3415 | if (alpha) | |
3416 | return DRM_FORMAT_ARGB16161616F; | |
3417 | else | |
3418 | return DRM_FORMAT_XRGB16161616F; | |
3419 | } | |
bc8d7dff DL |
3420 | } |
3421 | } | |
3422 | ||
9c4ce97d CW |
3423 | static struct i915_vma * |
3424 | initial_plane_vma(struct drm_i915_private *i915, | |
3425 | struct intel_initial_plane_config *plane_config) | |
3426 | { | |
3427 | struct drm_i915_gem_object *obj; | |
3428 | struct i915_vma *vma; | |
3429 | u32 base, size; | |
3430 | ||
3431 | if (plane_config->size == 0) | |
3432 | return NULL; | |
3433 | ||
3434 | base = round_down(plane_config->base, | |
3435 | I915_GTT_MIN_ALIGNMENT); | |
3436 | size = round_up(plane_config->base + plane_config->size, | |
3437 | I915_GTT_MIN_ALIGNMENT); | |
3438 | size -= base; | |
3439 | ||
3440 | /* | |
3441 | * If the FB is too big, just don't use it since fbdev is not very | |
3442 | * important and we should probably use that space with FBC or other | |
3443 | * features. | |
3444 | */ | |
3445 | if (size * 2 > i915->stolen_usable_size) | |
3446 | return NULL; | |
3447 | ||
3448 | obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size); | |
3449 | if (IS_ERR(obj)) | |
3450 | return NULL; | |
3451 | ||
2c1e63ba VS |
3452 | /* |
3453 | * Mark it WT ahead of time to avoid changing the | |
3454 | * cache_level during fbdev initialization. The | |
3455 | * unbind there would get stuck waiting for rcu. | |
3456 | */ | |
3457 | i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? | |
3458 | I915_CACHE_WT : I915_CACHE_NONE); | |
3459 | ||
9c4ce97d CW |
3460 | switch (plane_config->tiling) { |
3461 | case I915_TILING_NONE: | |
3462 | break; | |
3463 | case I915_TILING_X: | |
3464 | case I915_TILING_Y: | |
3465 | obj->tiling_and_stride = | |
3466 | plane_config->fb->base.pitches[0] | | |
3467 | plane_config->tiling; | |
3468 | break; | |
3469 | default: | |
3470 | MISSING_CASE(plane_config->tiling); | |
3471 | goto err_obj; | |
3472 | } | |
3473 | ||
3474 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); | |
3475 | if (IS_ERR(vma)) | |
3476 | goto err_obj; | |
3477 | ||
47b08693 | 3478 | if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) |
9c4ce97d CW |
3479 | goto err_obj; |
3480 | ||
3481 | if (i915_gem_object_is_tiled(obj) && | |
3482 | !i915_vma_is_map_and_fenceable(vma)) | |
3483 | goto err_obj; | |
3484 | ||
3485 | return vma; | |
3486 | ||
3487 | err_obj: | |
3488 | i915_gem_object_put(obj); | |
3489 | return NULL; | |
3490 | } | |
3491 | ||
5724dbd1 | 3492 | static bool |
f6936e29 DV |
3493 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
3494 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
3495 | { |
3496 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 3497 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb | 3498 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
2d14030b | 3499 | struct drm_framebuffer *fb = &plane_config->fb->base; |
9c4ce97d | 3500 | struct i915_vma *vma; |
3badb49f | 3501 | |
914a4fd8 ID |
3502 | switch (fb->modifier) { |
3503 | case DRM_FORMAT_MOD_LINEAR: | |
3504 | case I915_FORMAT_MOD_X_TILED: | |
3505 | case I915_FORMAT_MOD_Y_TILED: | |
3506 | break; | |
3507 | default: | |
cd49f818 WK |
3508 | drm_dbg(&dev_priv->drm, |
3509 | "Unsupported modifier for initial FB: 0x%llx\n", | |
3510 | fb->modifier); | |
914a4fd8 ID |
3511 | return false; |
3512 | } | |
3513 | ||
9c4ce97d CW |
3514 | vma = initial_plane_vma(dev_priv, plane_config); |
3515 | if (!vma) | |
484b41dd | 3516 | return false; |
46f297fb | 3517 | |
438b74a5 | 3518 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
3519 | mode_cmd.width = fb->width; |
3520 | mode_cmd.height = fb->height; | |
3521 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 3522 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 3523 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 3524 | |
9c4ce97d CW |
3525 | if (intel_framebuffer_init(to_intel_framebuffer(fb), |
3526 | vma->obj, &mode_cmd)) { | |
cd49f818 | 3527 | drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); |
9c4ce97d | 3528 | goto err_vma; |
46f297fb | 3529 | } |
12c83d99 | 3530 | |
9c4ce97d CW |
3531 | plane_config->vma = vma; |
3532 | return true; | |
484b41dd | 3533 | |
9c4ce97d CW |
3534 | err_vma: |
3535 | i915_vma_put(vma); | |
3536 | return false; | |
484b41dd JB |
3537 | } |
3538 | ||
e9728bd8 VS |
3539 | static void |
3540 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
3541 | struct intel_plane_state *plane_state, | |
3542 | bool visible) | |
3543 | { | |
f90a85e7 | 3544 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
e9728bd8 | 3545 | |
f90a85e7 | 3546 | plane_state->uapi.visible = visible; |
e9728bd8 | 3547 | |
62358aa4 | 3548 | if (visible) |
2225f3c6 | 3549 | crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); |
62358aa4 | 3550 | else |
2225f3c6 | 3551 | crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); |
e9728bd8 VS |
3552 | } |
3553 | ||
62358aa4 VS |
3554 | static void fixup_active_planes(struct intel_crtc_state *crtc_state) |
3555 | { | |
2225f3c6 | 3556 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
62358aa4 VS |
3557 | struct drm_plane *plane; |
3558 | ||
3559 | /* | |
3560 | * Active_planes aliases if multiple "primary" or cursor planes | |
3561 | * have been used on the same (or wrong) pipe. plane_mask uses | |
3562 | * unique ids, hence we can use that to reconstruct active_planes. | |
3563 | */ | |
3564 | crtc_state->active_planes = 0; | |
3565 | ||
3566 | drm_for_each_plane_mask(plane, &dev_priv->drm, | |
2225f3c6 | 3567 | crtc_state->uapi.plane_mask) |
62358aa4 VS |
3568 | crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); |
3569 | } | |
3570 | ||
b1e01595 VS |
3571 | static void intel_plane_disable_noatomic(struct intel_crtc *crtc, |
3572 | struct intel_plane *plane) | |
3573 | { | |
23526249 | 3574 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b1e01595 VS |
3575 | struct intel_crtc_state *crtc_state = |
3576 | to_intel_crtc_state(crtc->base.state); | |
3577 | struct intel_plane_state *plane_state = | |
3578 | to_intel_plane_state(plane->base.state); | |
3579 | ||
cd49f818 WK |
3580 | drm_dbg_kms(&dev_priv->drm, |
3581 | "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", | |
3582 | plane->base.base.id, plane->base.name, | |
3583 | crtc->base.base.id, crtc->base.name); | |
7a4a2a46 | 3584 | |
b1e01595 | 3585 | intel_set_plane_visible(crtc_state, plane_state, false); |
62358aa4 | 3586 | fixup_active_planes(crtc_state); |
c457d9cf | 3587 | crtc_state->data_rate[plane->id] = 0; |
bb6ae9e6 | 3588 | crtc_state->min_cdclk[plane->id] = 0; |
b1e01595 VS |
3589 | |
3590 | if (plane->id == PLANE_PRIMARY) | |
23526249 VS |
3591 | hsw_disable_ips(crtc_state); |
3592 | ||
3593 | /* | |
3594 | * Vblank time updates from the shadow to live plane control register | |
3595 | * are blocked if the memory self-refresh mode is active at that | |
3596 | * moment. So to make sure the plane gets truly disabled, disable | |
3597 | * first the self-refresh mode. The self-refresh enable bit in turn | |
3598 | * will be checked/applied by the HW only at the next frame start | |
3599 | * event which is after the vblank start event, so we need to have a | |
3600 | * wait-for-vblank between disabling the plane and the pipe. | |
3601 | */ | |
3602 | if (HAS_GMCH(dev_priv) && | |
3603 | intel_set_memory_cxsr(dev_priv, false)) | |
3604 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
3605 | ||
3606 | /* | |
3607 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
3608 | * So disable underrun reporting before all the planes get disabled. | |
3609 | */ | |
3610 | if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes) | |
3611 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
b1e01595 | 3612 | |
c48b86f9 | 3613 | intel_disable_plane(plane, crtc_state); |
b1e01595 VS |
3614 | } |
3615 | ||
8e7cb179 CW |
3616 | static struct intel_frontbuffer * |
3617 | to_intel_frontbuffer(struct drm_framebuffer *fb) | |
3618 | { | |
3619 | return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; | |
3620 | } | |
3621 | ||
5724dbd1 | 3622 | static void |
f6936e29 DV |
3623 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
3624 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
3625 | { |
3626 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3627 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 3628 | struct drm_crtc *c; |
88595ac9 | 3629 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 3630 | struct drm_plane_state *plane_state = primary->state; |
200757f5 | 3631 | struct intel_plane *intel_plane = to_intel_plane(primary); |
0a8d8a86 MR |
3632 | struct intel_plane_state *intel_state = |
3633 | to_intel_plane_state(plane_state); | |
88595ac9 | 3634 | struct drm_framebuffer *fb; |
9c4ce97d | 3635 | struct i915_vma *vma; |
484b41dd | 3636 | |
2d14030b | 3637 | if (!plane_config->fb) |
484b41dd JB |
3638 | return; |
3639 | ||
f6936e29 | 3640 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 | 3641 | fb = &plane_config->fb->base; |
9c4ce97d | 3642 | vma = plane_config->vma; |
88595ac9 | 3643 | goto valid_fb; |
f55548b5 | 3644 | } |
484b41dd | 3645 | |
484b41dd JB |
3646 | /* |
3647 | * Failed to alloc the obj, check to see if we should share | |
3648 | * an fb with another CRTC instead | |
3649 | */ | |
70e1e0ec | 3650 | for_each_crtc(dev, c) { |
be1e3415 | 3651 | struct intel_plane_state *state; |
484b41dd JB |
3652 | |
3653 | if (c == &intel_crtc->base) | |
3654 | continue; | |
3655 | ||
be1e3415 | 3656 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
3657 | continue; |
3658 | ||
be1e3415 CW |
3659 | state = to_intel_plane_state(c->primary->state); |
3660 | if (!state->vma) | |
484b41dd JB |
3661 | continue; |
3662 | ||
be1e3415 | 3663 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
7b3cb17a | 3664 | fb = state->hw.fb; |
9c4ce97d | 3665 | vma = state->vma; |
88595ac9 | 3666 | goto valid_fb; |
484b41dd JB |
3667 | } |
3668 | } | |
88595ac9 | 3669 | |
200757f5 MR |
3670 | /* |
3671 | * We've failed to reconstruct the BIOS FB. Current display state | |
3672 | * indicates that the primary plane is visible, but has a NULL FB, | |
3673 | * which will lead to problems later if we don't fix it up. The | |
3674 | * simplest solution is to just disable the primary plane now and | |
3675 | * pretend the BIOS never had it enabled. | |
3676 | */ | |
b1e01595 | 3677 | intel_plane_disable_noatomic(intel_crtc, intel_plane); |
200757f5 | 3678 | |
88595ac9 DV |
3679 | return; |
3680 | ||
3681 | valid_fb: | |
7b3cb17a | 3682 | intel_state->hw.rotation = plane_config->rotation; |
f5929c53 | 3683 | intel_fill_fb_ggtt_view(&intel_state->view, fb, |
7b3cb17a | 3684 | intel_state->hw.rotation); |
df79cf44 | 3685 | intel_state->color_plane[0].stride = |
7b3cb17a | 3686 | intel_fb_pitch(fb, 0, intel_state->hw.rotation); |
df79cf44 | 3687 | |
9c4ce97d CW |
3688 | __i915_vma_pin(vma); |
3689 | intel_state->vma = i915_vma_get(vma); | |
3690 | if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0) | |
3691 | if (vma->fence) | |
3692 | intel_state->flags |= PLANE_HAS_FENCE; | |
07bcd99b | 3693 | |
f44e2659 VS |
3694 | plane_state->src_x = 0; |
3695 | plane_state->src_y = 0; | |
be5651f2 ML |
3696 | plane_state->src_w = fb->width << 16; |
3697 | plane_state->src_h = fb->height << 16; | |
3698 | ||
f44e2659 VS |
3699 | plane_state->crtc_x = 0; |
3700 | plane_state->crtc_y = 0; | |
be5651f2 ML |
3701 | plane_state->crtc_w = fb->width; |
3702 | plane_state->crtc_h = fb->height; | |
3703 | ||
f90a85e7 ML |
3704 | intel_state->uapi.src = drm_plane_state_src(plane_state); |
3705 | intel_state->uapi.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 3706 | |
8e7cb179 | 3707 | if (plane_config->tiling) |
88595ac9 DV |
3708 | dev_priv->preserve_bios_swizzle = true; |
3709 | ||
cd30fbca | 3710 | plane_state->fb = fb; |
1586f620 CW |
3711 | drm_framebuffer_get(fb); |
3712 | ||
cd30fbca | 3713 | plane_state->crtc = &intel_crtc->base; |
380015bf | 3714 | intel_plane_copy_uapi_to_hw_state(intel_state, intel_state); |
e9728bd8 | 3715 | |
9c4ce97d CW |
3716 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
3717 | ||
faf5bf0a | 3718 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
8e7cb179 | 3719 | &to_intel_frontbuffer(fb)->bits); |
46f297fb JB |
3720 | } |
3721 | ||
e91c8a29 | 3722 | |
2dfbf9d2 DP |
3723 | static bool |
3724 | skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, | |
3725 | int main_x, int main_y, u32 main_offset, | |
3726 | int ccs_plane) | |
2e2adb05 | 3727 | { |
7b3cb17a | 3728 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
e7af9094 ID |
3729 | int aux_x = plane_state->color_plane[ccs_plane].x; |
3730 | int aux_y = plane_state->color_plane[ccs_plane].y; | |
3731 | u32 aux_offset = plane_state->color_plane[ccs_plane].offset; | |
3732 | u32 alignment = intel_surf_alignment(fb, ccs_plane); | |
b3e57bcc DP |
3733 | int hsub; |
3734 | int vsub; | |
2e2adb05 | 3735 | |
b3e57bcc | 3736 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
2e2adb05 VS |
3737 | while (aux_offset >= main_offset && aux_y <= main_y) { |
3738 | int x, y; | |
3739 | ||
3740 | if (aux_x == main_x && aux_y == main_y) | |
3741 | break; | |
3742 | ||
3743 | if (aux_offset == 0) | |
3744 | break; | |
3745 | ||
3746 | x = aux_x / hsub; | |
3747 | y = aux_y / vsub; | |
e7af9094 ID |
3748 | aux_offset = intel_plane_adjust_aligned_offset(&x, &y, |
3749 | plane_state, | |
3750 | ccs_plane, | |
3751 | aux_offset, | |
3752 | aux_offset - | |
3753 | alignment); | |
2e2adb05 VS |
3754 | aux_x = x * hsub + aux_x % hsub; |
3755 | aux_y = y * vsub + aux_y % vsub; | |
3756 | } | |
3757 | ||
3758 | if (aux_x != main_x || aux_y != main_y) | |
3759 | return false; | |
3760 | ||
e7af9094 ID |
3761 | plane_state->color_plane[ccs_plane].offset = aux_offset; |
3762 | plane_state->color_plane[ccs_plane].x = aux_x; | |
3763 | plane_state->color_plane[ccs_plane].y = aux_y; | |
2e2adb05 VS |
3764 | |
3765 | return true; | |
3766 | } | |
3767 | ||
5331889b VS |
3768 | unsigned int |
3769 | intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) | |
3770 | { | |
3771 | int x = 0, y = 0; | |
3772 | ||
3773 | intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, | |
3774 | plane_state->color_plane[0].offset, 0); | |
3775 | ||
3776 | return y; | |
3777 | } | |
3778 | ||
230edf78 VS |
3779 | static int intel_plane_min_width(struct intel_plane *plane, |
3780 | const struct drm_framebuffer *fb, | |
3781 | int color_plane, | |
3782 | unsigned int rotation) | |
3783 | { | |
3784 | if (plane->min_width) | |
3785 | return plane->min_width(fb, color_plane, rotation); | |
3786 | else | |
3787 | return 1; | |
3788 | } | |
3789 | ||
3790 | static int intel_plane_max_width(struct intel_plane *plane, | |
3791 | const struct drm_framebuffer *fb, | |
3792 | int color_plane, | |
3793 | unsigned int rotation) | |
3794 | { | |
3795 | if (plane->max_width) | |
3796 | return plane->max_width(fb, color_plane, rotation); | |
3797 | else | |
3798 | return INT_MAX; | |
3799 | } | |
3800 | ||
3801 | static int intel_plane_max_height(struct intel_plane *plane, | |
3802 | const struct drm_framebuffer *fb, | |
3803 | int color_plane, | |
3804 | unsigned int rotation) | |
3805 | { | |
3806 | if (plane->max_height) | |
3807 | return plane->max_height(fb, color_plane, rotation); | |
3808 | else | |
3809 | return INT_MAX; | |
3810 | } | |
3811 | ||
73266595 | 3812 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
b63a16f6 | 3813 | { |
230edf78 VS |
3814 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
3815 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
7b3cb17a ML |
3816 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
3817 | unsigned int rotation = plane_state->hw.rotation; | |
f90a85e7 ML |
3818 | int x = plane_state->uapi.src.x1 >> 16; |
3819 | int y = plane_state->uapi.src.y1 >> 16; | |
3820 | int w = drm_rect_width(&plane_state->uapi.src) >> 16; | |
3821 | int h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
230edf78 VS |
3822 | int min_width = intel_plane_min_width(plane, fb, 0, rotation); |
3823 | int max_width = intel_plane_max_width(plane, fb, 0, rotation); | |
3824 | int max_height = intel_plane_max_height(plane, fb, 0, rotation); | |
e7af9094 ID |
3825 | int aux_plane = intel_main_to_aux_plane(fb, 0); |
3826 | u32 aux_offset = plane_state->color_plane[aux_plane].offset; | |
230edf78 | 3827 | u32 alignment, offset; |
e91c8a29 | 3828 | |
d24f1341 | 3829 | if (w > max_width || w < min_width || h > max_height) { |
cd49f818 | 3830 | drm_dbg_kms(&dev_priv->drm, |
d24f1341 MA |
3831 | "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", |
3832 | w, h, min_width, max_width, max_height); | |
b63a16f6 VS |
3833 | return -EINVAL; |
3834 | } | |
3835 | ||
3836 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
6d19a44c | 3837 | offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); |
d88c4afd | 3838 | alignment = intel_surf_alignment(fb, 0); |
e57291c2 | 3839 | if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) |
7361bdb2 | 3840 | return -EINVAL; |
b63a16f6 | 3841 | |
8d970654 VS |
3842 | /* |
3843 | * AUX surface offset is specified as the distance from the | |
3844 | * main surface offset, and it must be non-negative. Make | |
3845 | * sure that is what we will get. | |
3846 | */ | |
a007138e | 3847 | if (aux_plane && offset > aux_offset) |
6d19a44c VS |
3848 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3849 | offset, aux_offset & ~(alignment - 1)); | |
8d970654 | 3850 | |
b63a16f6 VS |
3851 | /* |
3852 | * When using an X-tiled surface, the plane blows up | |
3853 | * if the x offset + width exceed the stride. | |
3854 | * | |
3855 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3856 | */ | |
bae781b2 | 3857 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3858 | int cpp = fb->format->cpp[0]; |
b63a16f6 | 3859 | |
df79cf44 | 3860 | while ((x + w) * cpp > plane_state->color_plane[0].stride) { |
b63a16f6 | 3861 | if (offset == 0) { |
cd49f818 WK |
3862 | drm_dbg_kms(&dev_priv->drm, |
3863 | "Unable to find suitable display surface offset due to X-tiling\n"); | |
b63a16f6 VS |
3864 | return -EINVAL; |
3865 | } | |
3866 | ||
6d19a44c VS |
3867 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3868 | offset, offset - alignment); | |
b63a16f6 VS |
3869 | } |
3870 | } | |
3871 | ||
2e2adb05 VS |
3872 | /* |
3873 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3874 | * they match with the main surface x/y offsets. | |
3875 | */ | |
63eaf9ac | 3876 | if (is_ccs_modifier(fb->modifier)) { |
2dfbf9d2 DP |
3877 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, |
3878 | offset, aux_plane)) { | |
2e2adb05 VS |
3879 | if (offset == 0) |
3880 | break; | |
3881 | ||
6d19a44c VS |
3882 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3883 | offset, offset - alignment); | |
2e2adb05 VS |
3884 | } |
3885 | ||
e7af9094 ID |
3886 | if (x != plane_state->color_plane[aux_plane].x || |
3887 | y != plane_state->color_plane[aux_plane].y) { | |
cd49f818 WK |
3888 | drm_dbg_kms(&dev_priv->drm, |
3889 | "Unable to find suitable display surface offset due to CCS\n"); | |
2e2adb05 VS |
3890 | return -EINVAL; |
3891 | } | |
3892 | } | |
3893 | ||
c11ada07 VS |
3894 | plane_state->color_plane[0].offset = offset; |
3895 | plane_state->color_plane[0].x = x; | |
3896 | plane_state->color_plane[0].y = y; | |
b63a16f6 | 3897 | |
54d4d719 VS |
3898 | /* |
3899 | * Put the final coordinates back so that the src | |
3900 | * coordinate checks will see the right values. | |
3901 | */ | |
f90a85e7 | 3902 | drm_rect_translate_to(&plane_state->uapi.src, |
dcdef1ab | 3903 | x << 16, y << 16); |
54d4d719 | 3904 | |
b63a16f6 VS |
3905 | return 0; |
3906 | } | |
3907 | ||
8d970654 VS |
3908 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3909 | { | |
230edf78 VS |
3910 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
3911 | struct drm_i915_private *i915 = to_i915(plane->base.dev); | |
7b3cb17a ML |
3912 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
3913 | unsigned int rotation = plane_state->hw.rotation; | |
2dfbf9d2 | 3914 | int uv_plane = 1; |
230edf78 VS |
3915 | int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); |
3916 | int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); | |
f90a85e7 ML |
3917 | int x = plane_state->uapi.src.x1 >> 17; |
3918 | int y = plane_state->uapi.src.y1 >> 17; | |
3919 | int w = drm_rect_width(&plane_state->uapi.src) >> 17; | |
3920 | int h = drm_rect_height(&plane_state->uapi.src) >> 17; | |
8d970654 VS |
3921 | u32 offset; |
3922 | ||
8d970654 VS |
3923 | /* FIXME not quite sure how/if these apply to the chroma plane */ |
3924 | if (w > max_width || h > max_height) { | |
cd49f818 WK |
3925 | drm_dbg_kms(&i915->drm, |
3926 | "CbCr source size %dx%d too big (limit %dx%d)\n", | |
3927 | w, h, max_width, max_height); | |
8d970654 VS |
3928 | return -EINVAL; |
3929 | } | |
3930 | ||
230edf78 VS |
3931 | intel_add_fb_offsets(&x, &y, plane_state, uv_plane); |
3932 | offset = intel_plane_compute_aligned_offset(&x, &y, | |
3933 | plane_state, uv_plane); | |
3934 | ||
2dfbf9d2 DP |
3935 | if (is_ccs_modifier(fb->modifier)) { |
3936 | int ccs_plane = main_to_ccs_plane(fb, uv_plane); | |
63b9d9aa VS |
3937 | u32 aux_offset = plane_state->color_plane[ccs_plane].offset; |
3938 | u32 alignment = intel_surf_alignment(fb, uv_plane); | |
2dfbf9d2 DP |
3939 | |
3940 | if (offset > aux_offset) | |
3941 | offset = intel_plane_adjust_aligned_offset(&x, &y, | |
3942 | plane_state, | |
3943 | uv_plane, | |
3944 | offset, | |
3945 | aux_offset & ~(alignment - 1)); | |
3946 | ||
3947 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, | |
3948 | offset, ccs_plane)) { | |
3949 | if (offset == 0) | |
3950 | break; | |
3951 | ||
3952 | offset = intel_plane_adjust_aligned_offset(&x, &y, | |
3953 | plane_state, | |
3954 | uv_plane, | |
3955 | offset, offset - alignment); | |
3956 | } | |
3957 | ||
3958 | if (x != plane_state->color_plane[ccs_plane].x || | |
3959 | y != plane_state->color_plane[ccs_plane].y) { | |
cd49f818 WK |
3960 | drm_dbg_kms(&i915->drm, |
3961 | "Unable to find suitable display surface offset due to CCS\n"); | |
2dfbf9d2 DP |
3962 | return -EINVAL; |
3963 | } | |
3964 | } | |
3965 | ||
3966 | plane_state->color_plane[uv_plane].offset = offset; | |
3967 | plane_state->color_plane[uv_plane].x = x; | |
3968 | plane_state->color_plane[uv_plane].y = y; | |
8d970654 VS |
3969 | |
3970 | return 0; | |
3971 | } | |
3972 | ||
2e2adb05 VS |
3973 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3974 | { | |
7b3cb17a | 3975 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 ML |
3976 | int src_x = plane_state->uapi.src.x1 >> 16; |
3977 | int src_y = plane_state->uapi.src.y1 >> 16; | |
2e2adb05 | 3978 | u32 offset; |
2dfbf9d2 | 3979 | int ccs_plane; |
2e2adb05 | 3980 | |
2dfbf9d2 DP |
3981 | for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { |
3982 | int main_hsub, main_vsub; | |
3983 | int hsub, vsub; | |
3984 | int x, y; | |
2e2adb05 | 3985 | |
2dfbf9d2 DP |
3986 | if (!is_ccs_plane(fb, ccs_plane)) |
3987 | continue; | |
3988 | ||
3989 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, | |
3990 | ccs_to_main_plane(fb, ccs_plane)); | |
3991 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); | |
3992 | ||
3993 | hsub *= main_hsub; | |
3994 | vsub *= main_vsub; | |
3995 | x = src_x / hsub; | |
3996 | y = src_y / vsub; | |
3997 | ||
3998 | intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); | |
3999 | ||
4000 | offset = intel_plane_compute_aligned_offset(&x, &y, | |
4001 | plane_state, | |
4002 | ccs_plane); | |
4003 | ||
4004 | plane_state->color_plane[ccs_plane].offset = offset; | |
4005 | plane_state->color_plane[ccs_plane].x = (x * hsub + | |
4006 | src_x % hsub) / | |
4007 | main_hsub; | |
4008 | plane_state->color_plane[ccs_plane].y = (y * vsub + | |
4009 | src_y % vsub) / | |
4010 | main_vsub; | |
4011 | } | |
2e2adb05 VS |
4012 | |
4013 | return 0; | |
4014 | } | |
4015 | ||
73266595 | 4016 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
b63a16f6 | 4017 | { |
7b3cb17a | 4018 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
79148ce4 | 4019 | int ret, i; |
b63a16f6 | 4020 | |
54d4d719 | 4021 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
4022 | if (ret) |
4023 | return ret; | |
4024 | ||
f90a85e7 | 4025 | if (!plane_state->uapi.visible) |
a5e4c7d0 VS |
4026 | return 0; |
4027 | ||
8d970654 | 4028 | /* |
2dfbf9d2 DP |
4029 | * Handle the AUX surface first since the main surface setup depends on |
4030 | * it. | |
8d970654 | 4031 | */ |
2dfbf9d2 | 4032 | if (is_ccs_modifier(fb->modifier)) { |
2dfbf9d2 DP |
4033 | ret = skl_check_ccs_aux_surface(plane_state); |
4034 | if (ret) | |
4035 | return ret; | |
4036 | } | |
4037 | ||
4941f35b ID |
4038 | if (intel_format_info_is_yuv_semiplanar(fb->format, |
4039 | fb->modifier)) { | |
8d970654 VS |
4040 | ret = skl_check_nv12_aux_surface(plane_state); |
4041 | if (ret) | |
4042 | return ret; | |
2dfbf9d2 DP |
4043 | } |
4044 | ||
79148ce4 | 4045 | for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) { |
a007138e | 4046 | plane_state->color_plane[i].offset = 0; |
79148ce4 VS |
4047 | plane_state->color_plane[i].x = 0; |
4048 | plane_state->color_plane[i].y = 0; | |
8d970654 VS |
4049 | } |
4050 | ||
73266595 | 4051 | ret = skl_check_main_surface(plane_state); |
b63a16f6 VS |
4052 | if (ret) |
4053 | return ret; | |
4054 | ||
4055 | return 0; | |
4056 | } | |
4057 | ||
bb6ae9e6 VS |
4058 | static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, |
4059 | const struct intel_plane_state *plane_state, | |
4060 | unsigned int *num, unsigned int *den) | |
4061 | { | |
7b3cb17a | 4062 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
bb6ae9e6 VS |
4063 | unsigned int cpp = fb->format->cpp[0]; |
4064 | ||
4065 | /* | |
4066 | * g4x bspec says 64bpp pixel rate can't exceed 80% | |
4067 | * of cdclk when the sprite plane is enabled on the | |
4068 | * same pipe. ilk/snb bspec says 64bpp pixel rate is | |
4069 | * never allowed to exceed 80% of cdclk. Let's just go | |
4070 | * with the ilk/snb limit always. | |
4071 | */ | |
4072 | if (cpp == 8) { | |
4073 | *num = 10; | |
4074 | *den = 8; | |
4075 | } else { | |
4076 | *num = 1; | |
4077 | *den = 1; | |
4078 | } | |
4079 | } | |
4080 | ||
4081 | static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, | |
4082 | const struct intel_plane_state *plane_state) | |
4083 | { | |
4084 | unsigned int pixel_rate; | |
4085 | unsigned int num, den; | |
4086 | ||
4087 | /* | |
4088 | * Note that crtc_state->pixel_rate accounts for both | |
4089 | * horizontal and vertical panel fitter downscaling factors. | |
4090 | * Pre-HSW bspec tells us to only consider the horizontal | |
4091 | * downscaling factor here. We ignore that and just consider | |
4092 | * both for simplicity. | |
4093 | */ | |
4094 | pixel_rate = crtc_state->pixel_rate; | |
4095 | ||
4096 | i9xx_plane_ratio(crtc_state, plane_state, &num, &den); | |
4097 | ||
4098 | /* two pixels per clock with double wide pipe */ | |
4099 | if (crtc_state->double_wide) | |
4100 | den *= 2; | |
4101 | ||
4102 | return DIV_ROUND_UP(pixel_rate * num, den); | |
4103 | } | |
4104 | ||
ddd5713d VS |
4105 | unsigned int |
4106 | i9xx_plane_max_stride(struct intel_plane *plane, | |
4107 | u32 pixel_format, u64 modifier, | |
4108 | unsigned int rotation) | |
4109 | { | |
4110 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
4111 | ||
b2ae318a | 4112 | if (!HAS_GMCH(dev_priv)) { |
ddd5713d VS |
4113 | return 32*1024; |
4114 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
4115 | if (modifier == I915_FORMAT_MOD_X_TILED) | |
4116 | return 16*1024; | |
4117 | else | |
4118 | return 32*1024; | |
4119 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
4120 | if (modifier == I915_FORMAT_MOD_X_TILED) | |
4121 | return 8*1024; | |
4122 | else | |
4123 | return 16*1024; | |
4124 | } else { | |
4125 | if (plane->i9xx_plane == PLANE_C) | |
4126 | return 4*1024; | |
4127 | else | |
4128 | return 8*1024; | |
4129 | } | |
4130 | } | |
4131 | ||
7eb31a0b VS |
4132 | static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4133 | { | |
2225f3c6 | 4134 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7eb31a0b VS |
4135 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4136 | u32 dspcntr = 0; | |
4137 | ||
5f29ab23 VS |
4138 | if (crtc_state->gamma_enable) |
4139 | dspcntr |= DISPPLANE_GAMMA_ENABLE; | |
7eb31a0b | 4140 | |
8271b2ef | 4141 | if (crtc_state->csc_enable) |
7eb31a0b VS |
4142 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
4143 | ||
4144 | if (INTEL_GEN(dev_priv) < 5) | |
4145 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
4146 | ||
4147 | return dspcntr; | |
4148 | } | |
4149 | ||
7145f60a VS |
4150 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
4151 | const struct intel_plane_state *plane_state) | |
81255565 | 4152 | { |
7145f60a | 4153 | struct drm_i915_private *dev_priv = |
f90a85e7 | 4154 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
4155 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4156 | unsigned int rotation = plane_state->hw.rotation; | |
7145f60a | 4157 | u32 dspcntr; |
c9ba6fad | 4158 | |
7eb31a0b | 4159 | dspcntr = DISPLAY_PLANE_ENABLE; |
f45651ba | 4160 | |
cf819eff LDM |
4161 | if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || |
4162 | IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 4163 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 4164 | |
438b74a5 | 4165 | switch (fb->format->format) { |
57779d06 | 4166 | case DRM_FORMAT_C8: |
81255565 JB |
4167 | dspcntr |= DISPPLANE_8BPP; |
4168 | break; | |
57779d06 | 4169 | case DRM_FORMAT_XRGB1555: |
57779d06 | 4170 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 4171 | break; |
73263cb6 VS |
4172 | case DRM_FORMAT_ARGB1555: |
4173 | dspcntr |= DISPPLANE_BGRA555; | |
4174 | break; | |
57779d06 VS |
4175 | case DRM_FORMAT_RGB565: |
4176 | dspcntr |= DISPPLANE_BGRX565; | |
4177 | break; | |
4178 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
4179 | dspcntr |= DISPPLANE_BGRX888; |
4180 | break; | |
4181 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
4182 | dspcntr |= DISPPLANE_RGBX888; |
4183 | break; | |
73263cb6 VS |
4184 | case DRM_FORMAT_ARGB8888: |
4185 | dspcntr |= DISPPLANE_BGRA888; | |
4186 | break; | |
4187 | case DRM_FORMAT_ABGR8888: | |
4188 | dspcntr |= DISPPLANE_RGBA888; | |
4189 | break; | |
57779d06 | 4190 | case DRM_FORMAT_XRGB2101010: |
57779d06 VS |
4191 | dspcntr |= DISPPLANE_BGRX101010; |
4192 | break; | |
4193 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 4194 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 | 4195 | break; |
73263cb6 VS |
4196 | case DRM_FORMAT_ARGB2101010: |
4197 | dspcntr |= DISPPLANE_BGRA101010; | |
4198 | break; | |
4199 | case DRM_FORMAT_ABGR2101010: | |
4200 | dspcntr |= DISPPLANE_RGBA101010; | |
4201 | break; | |
03b0ce95 VS |
4202 | case DRM_FORMAT_XBGR16161616F: |
4203 | dspcntr |= DISPPLANE_RGBX161616; | |
4204 | break; | |
81255565 | 4205 | default: |
7145f60a VS |
4206 | MISSING_CASE(fb->format->format); |
4207 | return 0; | |
81255565 | 4208 | } |
57779d06 | 4209 | |
72618ebf | 4210 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 4211 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 4212 | dspcntr |= DISPPLANE_TILED; |
81255565 | 4213 | |
c2c446ad | 4214 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
4215 | dspcntr |= DISPPLANE_ROTATE_180; |
4216 | ||
c2c446ad | 4217 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
4218 | dspcntr |= DISPPLANE_MIRROR; |
4219 | ||
7145f60a VS |
4220 | return dspcntr; |
4221 | } | |
de1aa629 | 4222 | |
f9407ae1 | 4223 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
4224 | { |
4225 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 4226 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 4227 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
03b0ce95 | 4228 | int src_x, src_y, src_w; |
5b7fcc44 | 4229 | u32 offset; |
fc3fed5d | 4230 | int ret; |
81255565 | 4231 | |
54d4d719 | 4232 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
4233 | if (ret) |
4234 | return ret; | |
4235 | ||
f90a85e7 | 4236 | if (!plane_state->uapi.visible) |
54d4d719 VS |
4237 | return 0; |
4238 | ||
f90a85e7 ML |
4239 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
4240 | src_x = plane_state->uapi.src.x1 >> 16; | |
4241 | src_y = plane_state->uapi.src.y1 >> 16; | |
54d4d719 | 4242 | |
03b0ce95 VS |
4243 | /* Undocumented hardware limit on i965/g4x/vlv/chv */ |
4244 | if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) | |
4245 | return -EINVAL; | |
4246 | ||
5b7fcc44 | 4247 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 4248 | |
5b7fcc44 | 4249 | if (INTEL_GEN(dev_priv) >= 4) |
6d19a44c VS |
4250 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, |
4251 | plane_state, 0); | |
5b7fcc44 VS |
4252 | else |
4253 | offset = 0; | |
4254 | ||
54d4d719 VS |
4255 | /* |
4256 | * Put the final coordinates back so that the src | |
4257 | * coordinate checks will see the right values. | |
4258 | */ | |
f90a85e7 | 4259 | drm_rect_translate_to(&plane_state->uapi.src, |
dcdef1ab | 4260 | src_x << 16, src_y << 16); |
54d4d719 | 4261 | |
5b7fcc44 VS |
4262 | /* HSW/BDW do this automagically in hardware */ |
4263 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
7b3cb17a | 4264 | unsigned int rotation = plane_state->hw.rotation; |
f90a85e7 ML |
4265 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
4266 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
5b7fcc44 | 4267 | |
c2c446ad | 4268 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
4269 | src_x += src_w - 1; |
4270 | src_y += src_h - 1; | |
c2c446ad | 4271 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
4272 | src_x += src_w - 1; |
4273 | } | |
48404c1e SJ |
4274 | } |
4275 | ||
c11ada07 VS |
4276 | plane_state->color_plane[0].offset = offset; |
4277 | plane_state->color_plane[0].x = src_x; | |
4278 | plane_state->color_plane[0].y = src_y; | |
5b7fcc44 VS |
4279 | |
4280 | return 0; | |
4281 | } | |
4282 | ||
26443a4b VS |
4283 | static bool i9xx_plane_has_windowing(struct intel_plane *plane) |
4284 | { | |
4285 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
4286 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
4287 | ||
4288 | if (IS_CHERRYVIEW(dev_priv)) | |
4289 | return i9xx_plane == PLANE_B; | |
4290 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
4291 | return false; | |
4292 | else if (IS_GEN(dev_priv, 4)) | |
4293 | return i9xx_plane == PLANE_C; | |
4294 | else | |
4295 | return i9xx_plane == PLANE_B || | |
4296 | i9xx_plane == PLANE_C; | |
4297 | } | |
4298 | ||
4e0b83a5 VS |
4299 | static int |
4300 | i9xx_plane_check(struct intel_crtc_state *crtc_state, | |
4301 | struct intel_plane_state *plane_state) | |
4302 | { | |
f90a85e7 | 4303 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4e0b83a5 VS |
4304 | int ret; |
4305 | ||
25721f82 VS |
4306 | ret = chv_plane_check_rotation(plane_state); |
4307 | if (ret) | |
4308 | return ret; | |
4309 | ||
f90a85e7 | 4310 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
2225f3c6 | 4311 | &crtc_state->uapi, |
4e0b83a5 VS |
4312 | DRM_PLANE_HELPER_NO_SCALING, |
4313 | DRM_PLANE_HELPER_NO_SCALING, | |
26443a4b VS |
4314 | i9xx_plane_has_windowing(plane), |
4315 | true); | |
4e0b83a5 VS |
4316 | if (ret) |
4317 | return ret; | |
4318 | ||
54d4d719 VS |
4319 | ret = i9xx_check_plane_surface(plane_state); |
4320 | if (ret) | |
4321 | return ret; | |
4322 | ||
f90a85e7 | 4323 | if (!plane_state->uapi.visible) |
4e0b83a5 VS |
4324 | return 0; |
4325 | ||
4326 | ret = intel_plane_check_src_coordinates(plane_state); | |
4327 | if (ret) | |
4328 | return ret; | |
4329 | ||
4e0b83a5 VS |
4330 | plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); |
4331 | ||
4332 | return 0; | |
4333 | } | |
4334 | ||
ed15030d VS |
4335 | static void i9xx_update_plane(struct intel_plane *plane, |
4336 | const struct intel_crtc_state *crtc_state, | |
4337 | const struct intel_plane_state *plane_state) | |
7145f60a | 4338 | { |
ed15030d | 4339 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
ed15030d | 4340 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
7145f60a | 4341 | u32 linear_offset; |
c11ada07 VS |
4342 | int x = plane_state->color_plane[0].x; |
4343 | int y = plane_state->color_plane[0].y; | |
f90a85e7 ML |
4344 | int crtc_x = plane_state->uapi.dst.x1; |
4345 | int crtc_y = plane_state->uapi.dst.y1; | |
4346 | int crtc_w = drm_rect_width(&plane_state->uapi.dst); | |
4347 | int crtc_h = drm_rect_height(&plane_state->uapi.dst); | |
7145f60a | 4348 | unsigned long irqflags; |
e288881b | 4349 | u32 dspaddr_offset; |
7eb31a0b VS |
4350 | u32 dspcntr; |
4351 | ||
4352 | dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); | |
7145f60a | 4353 | |
2949056c | 4354 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 4355 | |
5b7fcc44 | 4356 | if (INTEL_GEN(dev_priv) >= 4) |
c11ada07 | 4357 | dspaddr_offset = plane_state->color_plane[0].offset; |
5b7fcc44 | 4358 | else |
e288881b | 4359 | dspaddr_offset = linear_offset; |
6687c906 | 4360 | |
dd584fc0 VS |
4361 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4362 | ||
dc008bf0 JN |
4363 | intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), |
4364 | plane_state->color_plane[0].stride); | |
83234d13 | 4365 | |
78587de2 | 4366 | if (INTEL_GEN(dev_priv) < 4) { |
26443a4b VS |
4367 | /* |
4368 | * PLANE_A doesn't actually have a full window | |
4369 | * generator but let's assume we still need to | |
4370 | * program whatever is there. | |
78587de2 | 4371 | */ |
dc008bf0 JN |
4372 | intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), |
4373 | (crtc_y << 16) | crtc_x); | |
4374 | intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), | |
4375 | ((crtc_h - 1) << 16) | (crtc_w - 1)); | |
ed15030d | 4376 | } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { |
dc008bf0 JN |
4377 | intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), |
4378 | (crtc_y << 16) | crtc_x); | |
4379 | intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), | |
4380 | ((crtc_h - 1) << 16) | (crtc_w - 1)); | |
4381 | intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); | |
78587de2 VS |
4382 | } |
4383 | ||
3ba35e53 | 4384 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
dc008bf0 JN |
4385 | intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), |
4386 | (y << 16) | x); | |
3ba35e53 | 4387 | } else if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
4388 | intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), |
4389 | linear_offset); | |
4390 | intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), | |
4391 | (y << 16) | x); | |
83234d13 VS |
4392 | } |
4393 | ||
4394 | /* | |
4395 | * The control register self-arms if the plane was previously | |
4396 | * disabled. Try to make the plane enable atomic by writing | |
4397 | * the control register just before the surface register. | |
4398 | */ | |
dc008bf0 | 4399 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); |
83234d13 | 4400 | if (INTEL_GEN(dev_priv) >= 4) |
dc008bf0 JN |
4401 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), |
4402 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); | |
83234d13 | 4403 | else |
dc008bf0 JN |
4404 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), |
4405 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); | |
dd584fc0 VS |
4406 | |
4407 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
4408 | } |
4409 | ||
ed15030d | 4410 | static void i9xx_disable_plane(struct intel_plane *plane, |
0dd14be3 | 4411 | const struct intel_crtc_state *crtc_state) |
17638cd6 | 4412 | { |
ed15030d VS |
4413 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
4414 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
dd584fc0 | 4415 | unsigned long irqflags; |
7eb31a0b VS |
4416 | u32 dspcntr; |
4417 | ||
4418 | /* | |
4419 | * DSPCNTR pipe gamma enable on g4x+ and pipe csc | |
4420 | * enable on ilk+ affect the pipe bottom color as | |
4421 | * well, so we must configure them even if the plane | |
4422 | * is disabled. | |
4423 | * | |
4424 | * On pre-g4x there is no way to gamma correct the | |
4425 | * pipe bottom color but we'll keep on doing this | |
9d5441de | 4426 | * anyway so that the crtc state readout works correctly. |
7eb31a0b VS |
4427 | */ |
4428 | dspcntr = i9xx_plane_ctl_crtc(crtc_state); | |
dd584fc0 VS |
4429 | |
4430 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 4431 | |
dc008bf0 | 4432 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); |
ed15030d | 4433 | if (INTEL_GEN(dev_priv) >= 4) |
dc008bf0 | 4434 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); |
a8d201af | 4435 | else |
dc008bf0 | 4436 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); |
dd584fc0 VS |
4437 | |
4438 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 4439 | } |
c9ba6fad | 4440 | |
eade6c89 VS |
4441 | static bool i9xx_plane_get_hw_state(struct intel_plane *plane, |
4442 | enum pipe *pipe) | |
51f5a096 | 4443 | { |
ed15030d | 4444 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
51f5a096 | 4445 | enum intel_display_power_domain power_domain; |
ed15030d | 4446 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
0e6e0be4 | 4447 | intel_wakeref_t wakeref; |
51f5a096 | 4448 | bool ret; |
eade6c89 | 4449 | u32 val; |
51f5a096 VS |
4450 | |
4451 | /* | |
4452 | * Not 100% correct for planes that can move between pipes, | |
4453 | * but that's only the case for gen2-4 which don't have any | |
4454 | * display power wells. | |
4455 | */ | |
eade6c89 | 4456 | power_domain = POWER_DOMAIN_PIPE(plane->pipe); |
0e6e0be4 CW |
4457 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
4458 | if (!wakeref) | |
51f5a096 VS |
4459 | return false; |
4460 | ||
dc008bf0 | 4461 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
eade6c89 VS |
4462 | |
4463 | ret = val & DISPLAY_PLANE_ENABLE; | |
4464 | ||
4465 | if (INTEL_GEN(dev_priv) >= 5) | |
4466 | *pipe = plane->pipe; | |
4467 | else | |
4468 | *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
4469 | DISPPLANE_SEL_PIPE_SHIFT; | |
51f5a096 | 4470 | |
0e6e0be4 | 4471 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
4472 | |
4473 | return ret; | |
4474 | } | |
4475 | ||
e435d6e5 ML |
4476 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
4477 | { | |
4478 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4479 | struct drm_i915_private *dev_priv = to_i915(dev); |
f986ef2e VS |
4480 | unsigned long irqflags; |
4481 | ||
4482 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
4483 | ||
4484 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
4485 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
4486 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 | 4487 | |
f986ef2e | 4488 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
e435d6e5 ML |
4489 | } |
4490 | ||
a1b2278e CK |
4491 | /* |
4492 | * This function detaches (aka. unbinds) unused scalers in hardware | |
4493 | */ | |
15cbe5d0 | 4494 | static void skl_detach_scalers(const struct intel_crtc_state *crtc_state) |
a1b2278e | 4495 | { |
2225f3c6 | 4496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
15cbe5d0 ML |
4497 | const struct intel_crtc_scaler_state *scaler_state = |
4498 | &crtc_state->scaler_state; | |
a1b2278e CK |
4499 | int i; |
4500 | ||
a1b2278e CK |
4501 | /* loop through and disable scalers that aren't in use */ |
4502 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
4503 | if (!scaler_state->scalers[i].in_use) |
4504 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
4505 | } |
4506 | } | |
4507 | ||
b3cf5c06 VS |
4508 | static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, |
4509 | int color_plane, unsigned int rotation) | |
4510 | { | |
4511 | /* | |
4512 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
4513 | * linear buffers or in number of tiles for tiled buffers. | |
4514 | */ | |
b3e57bcc | 4515 | if (is_surface_linear(fb, color_plane)) |
b3cf5c06 VS |
4516 | return 64; |
4517 | else if (drm_rotation_90_or_270(rotation)) | |
4518 | return intel_tile_height(fb, color_plane); | |
4519 | else | |
4520 | return intel_tile_width_bytes(fb, color_plane); | |
4521 | } | |
4522 | ||
df79cf44 | 4523 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
5d2a1950 | 4524 | int color_plane) |
d2196774 | 4525 | { |
7b3cb17a ML |
4526 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4527 | unsigned int rotation = plane_state->hw.rotation; | |
5d2a1950 | 4528 | u32 stride = plane_state->color_plane[color_plane].stride; |
1b500535 | 4529 | |
5d2a1950 | 4530 | if (color_plane >= fb->format->num_planes) |
1b500535 VS |
4531 | return 0; |
4532 | ||
b3cf5c06 | 4533 | return stride / skl_plane_stride_mult(fb, color_plane, rotation); |
d2196774 VS |
4534 | } |
4535 | ||
ba3f4d0a | 4536 | static u32 skl_plane_ctl_format(u32 pixel_format) |
70d21f0e | 4537 | { |
6156a456 | 4538 | switch (pixel_format) { |
d161cf7a | 4539 | case DRM_FORMAT_C8: |
c34ce3d1 | 4540 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 4541 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 4542 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 4543 | case DRM_FORMAT_XBGR8888: |
4036c78c | 4544 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 4545 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 4546 | case DRM_FORMAT_XRGB8888: |
6156a456 | 4547 | case DRM_FORMAT_ARGB8888: |
4036c78c | 4548 | return PLANE_CTL_FORMAT_XRGB_8888; |
94e35ce2 | 4549 | case DRM_FORMAT_XBGR2101010: |
f9c43a31 | 4550 | case DRM_FORMAT_ABGR2101010: |
94e35ce2 | 4551 | return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; |
70d21f0e | 4552 | case DRM_FORMAT_XRGB2101010: |
f9c43a31 | 4553 | case DRM_FORMAT_ARGB2101010: |
c34ce3d1 | 4554 | return PLANE_CTL_FORMAT_XRGB_2101010; |
a94bed60 KS |
4555 | case DRM_FORMAT_XBGR16161616F: |
4556 | case DRM_FORMAT_ABGR16161616F: | |
4557 | return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; | |
4558 | case DRM_FORMAT_XRGB16161616F: | |
4559 | case DRM_FORMAT_ARGB16161616F: | |
4560 | return PLANE_CTL_FORMAT_XRGB_16161616F; | |
da904174 SL |
4561 | case DRM_FORMAT_XYUV8888: |
4562 | return PLANE_CTL_FORMAT_XYUV; | |
6156a456 | 4563 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 4564 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 4565 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 4566 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 4567 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 4568 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 4569 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 4570 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
77224cd5 CK |
4571 | case DRM_FORMAT_NV12: |
4572 | return PLANE_CTL_FORMAT_NV12; | |
df7d4156 JPH |
4573 | case DRM_FORMAT_P010: |
4574 | return PLANE_CTL_FORMAT_P010; | |
4575 | case DRM_FORMAT_P012: | |
4576 | return PLANE_CTL_FORMAT_P012; | |
4577 | case DRM_FORMAT_P016: | |
4578 | return PLANE_CTL_FORMAT_P016; | |
296e9b19 SS |
4579 | case DRM_FORMAT_Y210: |
4580 | return PLANE_CTL_FORMAT_Y210; | |
4581 | case DRM_FORMAT_Y212: | |
4582 | return PLANE_CTL_FORMAT_Y212; | |
4583 | case DRM_FORMAT_Y216: | |
4584 | return PLANE_CTL_FORMAT_Y216; | |
ff01e697 | 4585 | case DRM_FORMAT_XVYU2101010: |
296e9b19 | 4586 | return PLANE_CTL_FORMAT_Y410; |
ff01e697 | 4587 | case DRM_FORMAT_XVYU12_16161616: |
296e9b19 | 4588 | return PLANE_CTL_FORMAT_Y412; |
ff01e697 | 4589 | case DRM_FORMAT_XVYU16161616: |
296e9b19 | 4590 | return PLANE_CTL_FORMAT_Y416; |
70d21f0e | 4591 | default: |
4249eeef | 4592 | MISSING_CASE(pixel_format); |
70d21f0e | 4593 | } |
8cfcba41 | 4594 | |
c34ce3d1 | 4595 | return 0; |
6156a456 | 4596 | } |
70d21f0e | 4597 | |
b2081525 | 4598 | static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) |
4036c78c | 4599 | { |
7b3cb17a | 4600 | if (!plane_state->hw.fb->format->has_alpha) |
b2081525 ML |
4601 | return PLANE_CTL_ALPHA_DISABLE; |
4602 | ||
7b3cb17a | 4603 | switch (plane_state->hw.pixel_blend_mode) { |
b2081525 ML |
4604 | case DRM_MODE_BLEND_PIXEL_NONE: |
4605 | return PLANE_CTL_ALPHA_DISABLE; | |
4606 | case DRM_MODE_BLEND_PREMULTI: | |
4036c78c | 4607 | return PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
b2081525 ML |
4608 | case DRM_MODE_BLEND_COVERAGE: |
4609 | return PLANE_CTL_ALPHA_HW_PREMULTIPLY; | |
4036c78c | 4610 | default: |
7b3cb17a | 4611 | MISSING_CASE(plane_state->hw.pixel_blend_mode); |
4036c78c JA |
4612 | return PLANE_CTL_ALPHA_DISABLE; |
4613 | } | |
4614 | } | |
4615 | ||
b2081525 | 4616 | static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) |
4036c78c | 4617 | { |
7b3cb17a | 4618 | if (!plane_state->hw.fb->format->has_alpha) |
b2081525 ML |
4619 | return PLANE_COLOR_ALPHA_DISABLE; |
4620 | ||
7b3cb17a | 4621 | switch (plane_state->hw.pixel_blend_mode) { |
b2081525 ML |
4622 | case DRM_MODE_BLEND_PIXEL_NONE: |
4623 | return PLANE_COLOR_ALPHA_DISABLE; | |
4624 | case DRM_MODE_BLEND_PREMULTI: | |
4036c78c | 4625 | return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; |
b2081525 ML |
4626 | case DRM_MODE_BLEND_COVERAGE: |
4627 | return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; | |
4036c78c | 4628 | default: |
7b3cb17a | 4629 | MISSING_CASE(plane_state->hw.pixel_blend_mode); |
4036c78c JA |
4630 | return PLANE_COLOR_ALPHA_DISABLE; |
4631 | } | |
4632 | } | |
4633 | ||
ba3f4d0a | 4634 | static u32 skl_plane_ctl_tiling(u64 fb_modifier) |
6156a456 | 4635 | { |
6156a456 | 4636 | switch (fb_modifier) { |
2f075565 | 4637 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 4638 | break; |
30af77c4 | 4639 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 4640 | return PLANE_CTL_TILED_X; |
b321803d | 4641 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 4642 | return PLANE_CTL_TILED_Y; |
2e2adb05 | 4643 | case I915_FORMAT_MOD_Y_TILED_CCS: |
53867b46 | 4644 | return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; |
b3e57bcc DP |
4645 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
4646 | return PLANE_CTL_TILED_Y | | |
4647 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | | |
4648 | PLANE_CTL_CLEAR_COLOR_DISABLE; | |
2dfbf9d2 DP |
4649 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
4650 | return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; | |
b321803d | 4651 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 4652 | return PLANE_CTL_TILED_YF; |
2e2adb05 | 4653 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
53867b46 | 4654 | return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; |
70d21f0e | 4655 | default: |
6156a456 | 4656 | MISSING_CASE(fb_modifier); |
70d21f0e | 4657 | } |
8cfcba41 | 4658 | |
c34ce3d1 | 4659 | return 0; |
6156a456 | 4660 | } |
70d21f0e | 4661 | |
5f8e3f57 | 4662 | static u32 skl_plane_ctl_rotate(unsigned int rotate) |
6156a456 | 4663 | { |
5f8e3f57 | 4664 | switch (rotate) { |
c2c446ad | 4665 | case DRM_MODE_ROTATE_0: |
6156a456 | 4666 | break; |
1e8df167 | 4667 | /* |
c2c446ad | 4668 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
4669 | * while i915 HW rotation is clockwise, thats why this swapping. |
4670 | */ | |
c2c446ad | 4671 | case DRM_MODE_ROTATE_90: |
1e8df167 | 4672 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 4673 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 4674 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 4675 | case DRM_MODE_ROTATE_270: |
1e8df167 | 4676 | return PLANE_CTL_ROTATE_90; |
6156a456 | 4677 | default: |
5f8e3f57 JL |
4678 | MISSING_CASE(rotate); |
4679 | } | |
4680 | ||
4681 | return 0; | |
4682 | } | |
4683 | ||
4684 | static u32 cnl_plane_ctl_flip(unsigned int reflect) | |
4685 | { | |
4686 | switch (reflect) { | |
4687 | case 0: | |
4688 | break; | |
4689 | case DRM_MODE_REFLECT_X: | |
4690 | return PLANE_CTL_FLIP_HORIZONTAL; | |
4691 | case DRM_MODE_REFLECT_Y: | |
4692 | default: | |
4693 | MISSING_CASE(reflect); | |
6156a456 CK |
4694 | } |
4695 | ||
c34ce3d1 | 4696 | return 0; |
6156a456 CK |
4697 | } |
4698 | ||
7eb31a0b VS |
4699 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4700 | { | |
2225f3c6 | 4701 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7eb31a0b VS |
4702 | u32 plane_ctl = 0; |
4703 | ||
c5e07e00 K |
4704 | if (crtc_state->uapi.async_flip) |
4705 | plane_ctl |= PLANE_CTL_ASYNC_FLIP; | |
4706 | ||
7eb31a0b VS |
4707 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
4708 | return plane_ctl; | |
4709 | ||
5f29ab23 VS |
4710 | if (crtc_state->gamma_enable) |
4711 | plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; | |
4712 | ||
8271b2ef VS |
4713 | if (crtc_state->csc_enable) |
4714 | plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; | |
7eb31a0b VS |
4715 | |
4716 | return plane_ctl; | |
4717 | } | |
4718 | ||
2e881264 VS |
4719 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
4720 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
4721 | { |
4722 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 4723 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
4724 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4725 | unsigned int rotation = plane_state->hw.rotation; | |
2e881264 | 4726 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
4727 | u32 plane_ctl; |
4728 | ||
4729 | plane_ctl = PLANE_CTL_ENABLE; | |
4730 | ||
4036c78c | 4731 | if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { |
b2081525 | 4732 | plane_ctl |= skl_plane_ctl_alpha(plane_state); |
7eb31a0b | 4733 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
b0f5c0ba | 4734 | |
7b3cb17a | 4735 | if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) |
b0f5c0ba | 4736 | plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; |
c8624ede | 4737 | |
7b3cb17a | 4738 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
c8624ede | 4739 | plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; |
46f788ba VS |
4740 | } |
4741 | ||
4742 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
4743 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
5f8e3f57 JL |
4744 | plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); |
4745 | ||
4746 | if (INTEL_GEN(dev_priv) >= 10) | |
4747 | plane_ctl |= cnl_plane_ctl_flip(rotation & | |
4748 | DRM_MODE_REFLECT_MASK); | |
46f788ba | 4749 | |
2e881264 VS |
4750 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
4751 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
4752 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
4753 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
4754 | ||
46f788ba VS |
4755 | return plane_ctl; |
4756 | } | |
4757 | ||
7eb31a0b VS |
4758 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4759 | { | |
2225f3c6 | 4760 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7eb31a0b VS |
4761 | u32 plane_color_ctl = 0; |
4762 | ||
4763 | if (INTEL_GEN(dev_priv) >= 11) | |
4764 | return plane_color_ctl; | |
4765 | ||
5f29ab23 VS |
4766 | if (crtc_state->gamma_enable) |
4767 | plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; | |
4768 | ||
8271b2ef VS |
4769 | if (crtc_state->csc_enable) |
4770 | plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; | |
7eb31a0b VS |
4771 | |
4772 | return plane_color_ctl; | |
4773 | } | |
4774 | ||
4036c78c JA |
4775 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
4776 | const struct intel_plane_state *plane_state) | |
4777 | { | |
42fd20ed | 4778 | struct drm_i915_private *dev_priv = |
f90a85e7 | 4779 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 4780 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 | 4781 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4036c78c JA |
4782 | u32 plane_color_ctl = 0; |
4783 | ||
4036c78c | 4784 | plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; |
b2081525 | 4785 | plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); |
4036c78c | 4786 | |
42fd20ed | 4787 | if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { |
a0196dd6 KK |
4788 | switch (plane_state->hw.color_encoding) { |
4789 | case DRM_COLOR_YCBCR_BT709: | |
b0f5c0ba | 4790 | plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; |
a0196dd6 KK |
4791 | break; |
4792 | case DRM_COLOR_YCBCR_BT2020: | |
4793 | plane_color_ctl |= | |
4794 | PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; | |
4795 | break; | |
4796 | default: | |
4797 | plane_color_ctl |= | |
4798 | PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; | |
4799 | } | |
7b3cb17a | 4800 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
c8624ede | 4801 | plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; |
bfe60a02 US |
4802 | } else if (fb->format->is_yuv) { |
4803 | plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; | |
b0f5c0ba | 4804 | } |
012d79e6 | 4805 | |
4036c78c JA |
4806 | return plane_color_ctl; |
4807 | } | |
4808 | ||
73974893 ML |
4809 | static int |
4810 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
4811 | struct drm_atomic_state *state, |
4812 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
4813 | { |
4814 | struct drm_crtc_state *crtc_state; | |
4815 | struct drm_crtc *crtc; | |
4816 | int i, ret; | |
11c22da6 | 4817 | |
aecd36b8 | 4818 | intel_modeset_setup_hw_state(dev, ctx); |
4fb87831 | 4819 | intel_vga_redisable(to_i915(dev)); |
73974893 ML |
4820 | |
4821 | if (!state) | |
4822 | return 0; | |
4823 | ||
aa5e9b47 ML |
4824 | /* |
4825 | * We've duplicated the state, pointers to the old state are invalid. | |
4826 | * | |
4827 | * Don't attempt to use the old state until we commit the duplicated state. | |
4828 | */ | |
4829 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
4830 | /* |
4831 | * Force recalculation even if we restore | |
4832 | * current state. With fast modeset this may not result | |
4833 | * in a modeset when the state is compatible. | |
4834 | */ | |
4835 | crtc_state->mode_changed = true; | |
96a02917 | 4836 | } |
73974893 ML |
4837 | |
4838 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
b2ae318a | 4839 | if (!HAS_GMCH(to_i915(dev))) |
602ae835 | 4840 | to_intel_atomic_state(state)->skip_intermediate_wm = true; |
73974893 | 4841 | |
581e49fe | 4842 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 | 4843 | |
e57291c2 | 4844 | drm_WARN_ON(dev, ret == -EDEADLK); |
73974893 | 4845 | return ret; |
96a02917 VS |
4846 | } |
4847 | ||
4ac2ba2f VS |
4848 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
4849 | { | |
55277e1f | 4850 | return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && |
260e6b71 | 4851 | intel_has_gpu_reset(&dev_priv->gt)); |
4ac2ba2f VS |
4852 | } |
4853 | ||
87ebfaab | 4854 | void intel_display_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 4855 | { |
73974893 ML |
4856 | struct drm_device *dev = &dev_priv->drm; |
4857 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
4858 | struct drm_atomic_state *state; | |
4859 | int ret; | |
4860 | ||
2c568805 JRS |
4861 | if (!HAS_DISPLAY(dev_priv)) |
4862 | return; | |
4863 | ||
ce87ea15 | 4864 | /* reset doesn't touch the display */ |
8a25c4be | 4865 | if (!dev_priv->params.force_reset_modeset_test && |
ce87ea15 DV |
4866 | !gpu_reset_clobbers_display(dev_priv)) |
4867 | return; | |
4868 | ||
9db529aa | 4869 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
cb823ed9 CW |
4870 | set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags); |
4871 | smp_mb__after_atomic(); | |
4872 | wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET); | |
9db529aa DV |
4873 | |
4874 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { | |
cd49f818 WK |
4875 | drm_dbg_kms(&dev_priv->drm, |
4876 | "Modeset potentially stuck, unbreaking through wedging\n"); | |
cb823ed9 | 4877 | intel_gt_set_wedged(&dev_priv->gt); |
9db529aa | 4878 | } |
97154ec2 | 4879 | |
73974893 ML |
4880 | /* |
4881 | * Need mode_config.mutex so that we don't | |
4882 | * trample ongoing ->detect() and whatnot. | |
4883 | */ | |
4884 | mutex_lock(&dev->mode_config.mutex); | |
4885 | drm_modeset_acquire_init(ctx, 0); | |
4886 | while (1) { | |
4887 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
4888 | if (ret != -EDEADLK) | |
4889 | break; | |
4890 | ||
4891 | drm_modeset_backoff(ctx); | |
4892 | } | |
f98ce92f VS |
4893 | /* |
4894 | * Disabling the crtcs gracefully seems nicer. Also the | |
4895 | * g33 docs say we should at least disable all the planes. | |
4896 | */ | |
73974893 ML |
4897 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
4898 | if (IS_ERR(state)) { | |
4899 | ret = PTR_ERR(state); | |
cd49f818 WK |
4900 | drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", |
4901 | ret); | |
1e5a15d6 | 4902 | return; |
73974893 ML |
4903 | } |
4904 | ||
4905 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
4906 | if (ret) { | |
cd49f818 WK |
4907 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", |
4908 | ret); | |
1e5a15d6 ACO |
4909 | drm_atomic_state_put(state); |
4910 | return; | |
73974893 ML |
4911 | } |
4912 | ||
4913 | dev_priv->modeset_restore_state = state; | |
4914 | state->acquire_ctx = ctx; | |
7514747d VS |
4915 | } |
4916 | ||
e669ad6f | 4917 | void intel_display_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 4918 | { |
73974893 ML |
4919 | struct drm_device *dev = &dev_priv->drm; |
4920 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
40da1d31 | 4921 | struct drm_atomic_state *state; |
73974893 ML |
4922 | int ret; |
4923 | ||
2c568805 JRS |
4924 | if (!HAS_DISPLAY(dev_priv)) |
4925 | return; | |
4926 | ||
ce87ea15 | 4927 | /* reset doesn't touch the display */ |
cb823ed9 | 4928 | if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) |
ce87ea15 DV |
4929 | return; |
4930 | ||
40da1d31 | 4931 | state = fetch_and_zero(&dev_priv->modeset_restore_state); |
ce87ea15 DV |
4932 | if (!state) |
4933 | goto unlock; | |
4934 | ||
7514747d | 4935 | /* reset doesn't touch the display */ |
4ac2ba2f | 4936 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
4937 | /* for testing only restore the display */ |
4938 | ret = __intel_display_resume(dev, state, ctx); | |
942d5d0d | 4939 | if (ret) |
cd49f818 WK |
4940 | drm_err(&dev_priv->drm, |
4941 | "Restoring old state failed with %i\n", ret); | |
73974893 ML |
4942 | } else { |
4943 | /* | |
4944 | * The display has been reset as well, | |
4945 | * so need a full re-initialization. | |
4946 | */ | |
51f59205 | 4947 | intel_pps_unlock_regs_wa(dev_priv); |
6cd02e77 | 4948 | intel_modeset_init_hw(dev_priv); |
f72b84c6 | 4949 | intel_init_clock_gating(dev_priv); |
4c8d4651 | 4950 | intel_hpd_init(dev_priv); |
7514747d | 4951 | |
581e49fe | 4952 | ret = __intel_display_resume(dev, state, ctx); |
73974893 | 4953 | if (ret) |
cd49f818 WK |
4954 | drm_err(&dev_priv->drm, |
4955 | "Restoring old state failed with %i\n", ret); | |
7514747d | 4956 | |
4c8d4651 | 4957 | intel_hpd_poll_disable(dev_priv); |
73974893 | 4958 | } |
7514747d | 4959 | |
ce87ea15 DV |
4960 | drm_atomic_state_put(state); |
4961 | unlock: | |
73974893 ML |
4962 | drm_modeset_drop_locks(ctx); |
4963 | drm_modeset_acquire_fini(ctx); | |
4964 | mutex_unlock(&dev->mode_config.mutex); | |
9db529aa | 4965 | |
cb823ed9 | 4966 | clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags); |
7514747d VS |
4967 | } |
4968 | ||
d1622119 VS |
4969 | static void icl_set_pipe_chicken(struct intel_crtc *crtc) |
4970 | { | |
4971 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
4972 | enum pipe pipe = crtc->pipe; | |
4973 | u32 tmp; | |
4974 | ||
dc008bf0 | 4975 | tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); |
d1622119 VS |
4976 | |
4977 | /* | |
4978 | * Display WA #1153: icl | |
4979 | * enable hardware to bypass the alpha math | |
4980 | * and rounding for per-pixel values 00 and 0xff | |
4981 | */ | |
4982 | tmp |= PER_PIXEL_ALPHA_BYPASS_EN; | |
26eeea15 AS |
4983 | /* |
4984 | * Display WA # 1605353570: icl | |
4985 | * Set the pixel rounding bit to 1 for allowing | |
4986 | * passthrough of Frame buffer pixels unmodified | |
4987 | * across pipe | |
4988 | */ | |
4989 | tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; | |
dc008bf0 | 4990 | intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); |
d1622119 VS |
4991 | } |
4992 | ||
4cbe4b2b | 4993 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 4994 | { |
4cbe4b2b | 4995 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4996 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 4997 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
4998 | i915_reg_t reg; |
4999 | u32 temp; | |
5e84e1a4 ZW |
5000 | |
5001 | /* enable normal train */ | |
5002 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5003 | temp = intel_de_read(dev_priv, reg); |
fd6b8f43 | 5004 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
5005 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
5006 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
5007 | } else { |
5008 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5009 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 5010 | } |
dc008bf0 | 5011 | intel_de_write(dev_priv, reg, temp); |
5e84e1a4 ZW |
5012 | |
5013 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5014 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5015 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
5016 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5017 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
5018 | } else { | |
5019 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5020 | temp |= FDI_LINK_TRAIN_NONE; | |
5021 | } | |
dc008bf0 | 5022 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
5e84e1a4 ZW |
5023 | |
5024 | /* wait one idle pattern time */ | |
dc008bf0 | 5025 | intel_de_posting_read(dev_priv, reg); |
5e84e1a4 | 5026 | udelay(1000); |
357555c0 JB |
5027 | |
5028 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 5029 | if (IS_IVYBRIDGE(dev_priv)) |
dc008bf0 JN |
5030 | intel_de_write(dev_priv, reg, |
5031 | intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
5032 | } |
5033 | ||
8db9d77b | 5034 | /* The FDI link training functions for ILK/Ibexpeak. */ |
9eae5e27 LDM |
5035 | static void ilk_fdi_link_train(struct intel_crtc *crtc, |
5036 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 5037 | { |
4cbe4b2b | 5038 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5039 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5040 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5041 | i915_reg_t reg; |
5042 | u32 temp, tries; | |
8db9d77b | 5043 | |
1c8562f6 | 5044 | /* FDI needs bits from pipe first */ |
b104e8b2 | 5045 | assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder); |
0fc932b8 | 5046 | |
e1a44743 AJ |
5047 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
5048 | for train result */ | |
5eddb70b | 5049 | reg = FDI_RX_IMR(pipe); |
dc008bf0 | 5050 | temp = intel_de_read(dev_priv, reg); |
e1a44743 AJ |
5051 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5052 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 JN |
5053 | intel_de_write(dev_priv, reg, temp); |
5054 | intel_de_read(dev_priv, reg); | |
e1a44743 AJ |
5055 | udelay(150); |
5056 | ||
8db9d77b | 5057 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b | 5058 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5059 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5060 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5061 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
5062 | temp &= ~FDI_LINK_TRAIN_NONE; |
5063 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5064 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
8db9d77b | 5065 | |
5eddb70b | 5066 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5067 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5068 | temp &= ~FDI_LINK_TRAIN_NONE; |
5069 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5070 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
5eddb70b | 5071 | |
dc008bf0 | 5072 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5073 | udelay(150); |
5074 | ||
5b2adf89 | 5075 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
dc008bf0 JN |
5076 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), |
5077 | FDI_RX_PHASE_SYNC_POINTER_OVR); | |
5078 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), | |
5079 | FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 5080 | |
5eddb70b | 5081 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 5082 | for (tries = 0; tries < 5; tries++) { |
dc008bf0 | 5083 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5084 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
8db9d77b ZW |
5085 | |
5086 | if ((temp & FDI_RX_BIT_LOCK)) { | |
cd49f818 | 5087 | drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); |
dc008bf0 | 5088 | intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
5089 | break; |
5090 | } | |
8db9d77b | 5091 | } |
e1a44743 | 5092 | if (tries == 5) |
cd49f818 | 5093 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); |
8db9d77b ZW |
5094 | |
5095 | /* Train 2 */ | |
5eddb70b | 5096 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5097 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5098 | temp &= ~FDI_LINK_TRAIN_NONE; |
5099 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
dc008bf0 | 5100 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5101 | |
5eddb70b | 5102 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5103 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5104 | temp &= ~FDI_LINK_TRAIN_NONE; |
5105 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
dc008bf0 | 5106 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5107 | |
dc008bf0 | 5108 | intel_de_posting_read(dev_priv, reg); |
5eddb70b | 5109 | udelay(150); |
8db9d77b | 5110 | |
5eddb70b | 5111 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 5112 | for (tries = 0; tries < 5; tries++) { |
dc008bf0 | 5113 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5114 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
8db9d77b ZW |
5115 | |
5116 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
dc008bf0 JN |
5117 | intel_de_write(dev_priv, reg, |
5118 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 | 5119 | drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); |
8db9d77b ZW |
5120 | break; |
5121 | } | |
8db9d77b | 5122 | } |
e1a44743 | 5123 | if (tries == 5) |
cd49f818 | 5124 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); |
8db9d77b | 5125 | |
cd49f818 | 5126 | drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); |
5c5313c8 | 5127 | |
8db9d77b ZW |
5128 | } |
5129 | ||
0206e353 | 5130 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
5131 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
5132 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
5133 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
5134 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
5135 | }; | |
5136 | ||
5137 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
5138 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
5139 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 5140 | { |
4cbe4b2b | 5141 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5142 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5143 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5144 | i915_reg_t reg; |
5145 | u32 temp, i, retry; | |
8db9d77b | 5146 | |
e1a44743 AJ |
5147 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
5148 | for train result */ | |
5eddb70b | 5149 | reg = FDI_RX_IMR(pipe); |
dc008bf0 | 5150 | temp = intel_de_read(dev_priv, reg); |
e1a44743 AJ |
5151 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5152 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 | 5153 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5154 | |
dc008bf0 | 5155 | intel_de_posting_read(dev_priv, reg); |
e1a44743 AJ |
5156 | udelay(150); |
5157 | ||
8db9d77b | 5158 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b | 5159 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5160 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5161 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5162 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
5163 | temp &= ~FDI_LINK_TRAIN_NONE; |
5164 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5165 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
5166 | /* SNB-B */ | |
5167 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
dc008bf0 | 5168 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
8db9d77b | 5169 | |
dc008bf0 JN |
5170 | intel_de_write(dev_priv, FDI_RX_MISC(pipe), |
5171 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
d74cf324 | 5172 | |
5eddb70b | 5173 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5174 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5175 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
5176 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5177 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
5178 | } else { | |
5179 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5180 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5181 | } | |
dc008bf0 | 5182 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
5eddb70b | 5183 | |
dc008bf0 | 5184 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5185 | udelay(150); |
5186 | ||
0206e353 | 5187 | for (i = 0; i < 4; i++) { |
5eddb70b | 5188 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5189 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5190 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5191 | temp |= snb_b_fdi_train_param[i]; | |
dc008bf0 | 5192 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5193 | |
dc008bf0 | 5194 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5195 | udelay(500); |
5196 | ||
fa37d39e SP |
5197 | for (retry = 0; retry < 5; retry++) { |
5198 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5199 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5200 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
fa37d39e | 5201 | if (temp & FDI_RX_BIT_LOCK) { |
dc008bf0 JN |
5202 | intel_de_write(dev_priv, reg, |
5203 | temp | FDI_RX_BIT_LOCK); | |
cd49f818 WK |
5204 | drm_dbg_kms(&dev_priv->drm, |
5205 | "FDI train 1 done.\n"); | |
fa37d39e SP |
5206 | break; |
5207 | } | |
5208 | udelay(50); | |
8db9d77b | 5209 | } |
fa37d39e SP |
5210 | if (retry < 5) |
5211 | break; | |
8db9d77b ZW |
5212 | } |
5213 | if (i == 4) | |
cd49f818 | 5214 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); |
8db9d77b ZW |
5215 | |
5216 | /* Train 2 */ | |
5eddb70b | 5217 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5218 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5219 | temp &= ~FDI_LINK_TRAIN_NONE; |
5220 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
cf819eff | 5221 | if (IS_GEN(dev_priv, 6)) { |
8db9d77b ZW |
5222 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5223 | /* SNB-B */ | |
5224 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5225 | } | |
dc008bf0 | 5226 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5227 | |
5eddb70b | 5228 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5229 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5230 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
5231 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5232 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
5233 | } else { | |
5234 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5235 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5236 | } | |
dc008bf0 | 5237 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5238 | |
dc008bf0 | 5239 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5240 | udelay(150); |
5241 | ||
0206e353 | 5242 | for (i = 0; i < 4; i++) { |
5eddb70b | 5243 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5244 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5245 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5246 | temp |= snb_b_fdi_train_param[i]; | |
dc008bf0 | 5247 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5248 | |
dc008bf0 | 5249 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5250 | udelay(500); |
5251 | ||
fa37d39e SP |
5252 | for (retry = 0; retry < 5; retry++) { |
5253 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5254 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5255 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
fa37d39e | 5256 | if (temp & FDI_RX_SYMBOL_LOCK) { |
dc008bf0 JN |
5257 | intel_de_write(dev_priv, reg, |
5258 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 WK |
5259 | drm_dbg_kms(&dev_priv->drm, |
5260 | "FDI train 2 done.\n"); | |
fa37d39e SP |
5261 | break; |
5262 | } | |
5263 | udelay(50); | |
8db9d77b | 5264 | } |
fa37d39e SP |
5265 | if (retry < 5) |
5266 | break; | |
8db9d77b ZW |
5267 | } |
5268 | if (i == 4) | |
cd49f818 | 5269 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); |
8db9d77b | 5270 | |
cd49f818 | 5271 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); |
8db9d77b ZW |
5272 | } |
5273 | ||
357555c0 | 5274 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
5275 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
5276 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 5277 | { |
4cbe4b2b | 5278 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5279 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5280 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5281 | i915_reg_t reg; |
5282 | u32 temp, i, j; | |
357555c0 JB |
5283 | |
5284 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
5285 | for train result */ | |
5286 | reg = FDI_RX_IMR(pipe); | |
dc008bf0 | 5287 | temp = intel_de_read(dev_priv, reg); |
357555c0 JB |
5288 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5289 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 | 5290 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5291 | |
dc008bf0 | 5292 | intel_de_posting_read(dev_priv, reg); |
357555c0 JB |
5293 | udelay(150); |
5294 | ||
cd49f818 | 5295 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", |
dc008bf0 | 5296 | intel_de_read(dev_priv, FDI_RX_IIR(pipe))); |
01a415fd | 5297 | |
139ccd3f JB |
5298 | /* Try each vswing and preemphasis setting twice before moving on */ |
5299 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
5300 | /* disable first in case we need to retry */ | |
5301 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5302 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5303 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
5304 | temp &= ~FDI_TX_ENABLE; | |
dc008bf0 | 5305 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5306 | |
139ccd3f | 5307 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5308 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5309 | temp &= ~FDI_LINK_TRAIN_AUTO; |
5310 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
5311 | temp &= ~FDI_RX_ENABLE; | |
dc008bf0 | 5312 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5313 | |
139ccd3f | 5314 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 | 5315 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5316 | temp = intel_de_read(dev_priv, reg); |
139ccd3f | 5317 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5318 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 5319 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 5320 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
5321 | temp |= snb_b_fdi_train_param[j/2]; |
5322 | temp |= FDI_COMPOSITE_SYNC; | |
dc008bf0 | 5323 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
357555c0 | 5324 | |
dc008bf0 JN |
5325 | intel_de_write(dev_priv, FDI_RX_MISC(pipe), |
5326 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 5327 | |
139ccd3f | 5328 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5329 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5330 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
5331 | temp |= FDI_COMPOSITE_SYNC; | |
dc008bf0 | 5332 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
357555c0 | 5333 | |
dc008bf0 | 5334 | intel_de_posting_read(dev_priv, reg); |
139ccd3f | 5335 | udelay(1); /* should be 0.5us */ |
357555c0 | 5336 | |
139ccd3f JB |
5337 | for (i = 0; i < 4; i++) { |
5338 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5339 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5340 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
357555c0 | 5341 | |
139ccd3f | 5342 | if (temp & FDI_RX_BIT_LOCK || |
dc008bf0 JN |
5343 | (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { |
5344 | intel_de_write(dev_priv, reg, | |
5345 | temp | FDI_RX_BIT_LOCK); | |
cd49f818 WK |
5346 | drm_dbg_kms(&dev_priv->drm, |
5347 | "FDI train 1 done, level %i.\n", | |
5348 | i); | |
139ccd3f JB |
5349 | break; |
5350 | } | |
5351 | udelay(1); /* should be 0.5us */ | |
5352 | } | |
5353 | if (i == 4) { | |
cd49f818 WK |
5354 | drm_dbg_kms(&dev_priv->drm, |
5355 | "FDI train 1 fail on vswing %d\n", j / 2); | |
139ccd3f JB |
5356 | continue; |
5357 | } | |
357555c0 | 5358 | |
139ccd3f | 5359 | /* Train 2 */ |
357555c0 | 5360 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5361 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5362 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
5363 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
dc008bf0 | 5364 | intel_de_write(dev_priv, reg, temp); |
139ccd3f JB |
5365 | |
5366 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5367 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5368 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5369 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
dc008bf0 | 5370 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5371 | |
dc008bf0 | 5372 | intel_de_posting_read(dev_priv, reg); |
139ccd3f | 5373 | udelay(2); /* should be 1.5us */ |
357555c0 | 5374 | |
139ccd3f JB |
5375 | for (i = 0; i < 4; i++) { |
5376 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5377 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5378 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
357555c0 | 5379 | |
139ccd3f | 5380 | if (temp & FDI_RX_SYMBOL_LOCK || |
dc008bf0 JN |
5381 | (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { |
5382 | intel_de_write(dev_priv, reg, | |
5383 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 WK |
5384 | drm_dbg_kms(&dev_priv->drm, |
5385 | "FDI train 2 done, level %i.\n", | |
5386 | i); | |
139ccd3f JB |
5387 | goto train_done; |
5388 | } | |
5389 | udelay(2); /* should be 1.5us */ | |
357555c0 | 5390 | } |
139ccd3f | 5391 | if (i == 4) |
cd49f818 WK |
5392 | drm_dbg_kms(&dev_priv->drm, |
5393 | "FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 5394 | } |
357555c0 | 5395 | |
139ccd3f | 5396 | train_done: |
cd49f818 | 5397 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); |
357555c0 JB |
5398 | } |
5399 | ||
9eae5e27 | 5400 | static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) |
2c07245f | 5401 | { |
2225f3c6 | 5402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2354c78 | 5403 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
d048a268 | 5404 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 VS |
5405 | i915_reg_t reg; |
5406 | u32 temp; | |
c64e311e | 5407 | |
c98e9dcf | 5408 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b | 5409 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5410 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5411 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
b2354c78 | 5412 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
dc008bf0 JN |
5413 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5414 | intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); | |
5eddb70b | 5415 | |
dc008bf0 | 5416 | intel_de_posting_read(dev_priv, reg); |
c98e9dcf JB |
5417 | udelay(200); |
5418 | ||
5419 | /* Switch from Rawclk to PCDclk */ | |
dc008bf0 JN |
5420 | temp = intel_de_read(dev_priv, reg); |
5421 | intel_de_write(dev_priv, reg, temp | FDI_PCDCLK); | |
5eddb70b | 5422 | |
dc008bf0 | 5423 | intel_de_posting_read(dev_priv, reg); |
c98e9dcf JB |
5424 | udelay(200); |
5425 | ||
20749730 PZ |
5426 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
5427 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5428 | temp = intel_de_read(dev_priv, reg); |
20749730 | 5429 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
dc008bf0 | 5430 | intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); |
5eddb70b | 5431 | |
dc008bf0 | 5432 | intel_de_posting_read(dev_priv, reg); |
20749730 | 5433 | udelay(100); |
6be4a607 | 5434 | } |
0e23b99d JB |
5435 | } |
5436 | ||
9eae5e27 | 5437 | static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc) |
88cefb6c DV |
5438 | { |
5439 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 5440 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5441 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 VS |
5442 | i915_reg_t reg; |
5443 | u32 temp; | |
88cefb6c DV |
5444 | |
5445 | /* Switch from PCDclk to Rawclk */ | |
5446 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 JN |
5447 | temp = intel_de_read(dev_priv, reg); |
5448 | intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK); | |
88cefb6c DV |
5449 | |
5450 | /* Disable CPU FDI TX PLL */ | |
5451 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 JN |
5452 | temp = intel_de_read(dev_priv, reg); |
5453 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE); | |
88cefb6c | 5454 | |
dc008bf0 | 5455 | intel_de_posting_read(dev_priv, reg); |
88cefb6c DV |
5456 | udelay(100); |
5457 | ||
5458 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 JN |
5459 | temp = intel_de_read(dev_priv, reg); |
5460 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE); | |
88cefb6c DV |
5461 | |
5462 | /* Wait for the clocks to turn off. */ | |
dc008bf0 | 5463 | intel_de_posting_read(dev_priv, reg); |
88cefb6c DV |
5464 | udelay(100); |
5465 | } | |
5466 | ||
9eae5e27 | 5467 | static void ilk_fdi_disable(struct intel_crtc *crtc) |
0fc932b8 | 5468 | { |
5b4f4e94 VS |
5469 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5470 | enum pipe pipe = crtc->pipe; | |
f0f59a00 VS |
5471 | i915_reg_t reg; |
5472 | u32 temp; | |
0fc932b8 JB |
5473 | |
5474 | /* disable CPU FDI tx and PCH FDI rx */ | |
5475 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 JN |
5476 | temp = intel_de_read(dev_priv, reg); |
5477 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE); | |
5478 | intel_de_posting_read(dev_priv, reg); | |
0fc932b8 JB |
5479 | |
5480 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5481 | temp = intel_de_read(dev_priv, reg); |
0fc932b8 | 5482 | temp &= ~(0x7 << 16); |
dc008bf0 JN |
5483 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5484 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); | |
0fc932b8 | 5485 | |
dc008bf0 | 5486 | intel_de_posting_read(dev_priv, reg); |
0fc932b8 JB |
5487 | udelay(100); |
5488 | ||
5489 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 5490 | if (HAS_PCH_IBX(dev_priv)) |
dc008bf0 JN |
5491 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), |
5492 | FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
5493 | |
5494 | /* still set train pattern 1 */ | |
5495 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5496 | temp = intel_de_read(dev_priv, reg); |
0fc932b8 JB |
5497 | temp &= ~FDI_LINK_TRAIN_NONE; |
5498 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5499 | intel_de_write(dev_priv, reg, temp); |
0fc932b8 JB |
5500 | |
5501 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5502 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5503 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
5504 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5505 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
5506 | } else { | |
5507 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5508 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5509 | } | |
5510 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
5511 | temp &= ~(0x07 << 16); | |
dc008bf0 JN |
5512 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5513 | intel_de_write(dev_priv, reg, temp); | |
0fc932b8 | 5514 | |
dc008bf0 | 5515 | intel_de_posting_read(dev_priv, reg); |
0fc932b8 JB |
5516 | udelay(100); |
5517 | } | |
5518 | ||
49d73912 | 5519 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 5520 | { |
fa05887a DV |
5521 | struct drm_crtc *crtc; |
5522 | bool cleanup_done; | |
5523 | ||
5524 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
5525 | struct drm_crtc_commit *commit; | |
5526 | spin_lock(&crtc->commit_lock); | |
5527 | commit = list_first_entry_or_null(&crtc->commit_list, | |
5528 | struct drm_crtc_commit, commit_entry); | |
5529 | cleanup_done = commit ? | |
5530 | try_wait_for_completion(&commit->cleanup_done) : true; | |
5531 | spin_unlock(&crtc->commit_lock); | |
5532 | ||
5533 | if (cleanup_done) | |
5dce5b93 CW |
5534 | continue; |
5535 | ||
fa05887a | 5536 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
5537 | |
5538 | return true; | |
5539 | } | |
5540 | ||
5541 | return false; | |
5542 | } | |
5543 | ||
b7076546 | 5544 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
5545 | { |
5546 | u32 temp; | |
5547 | ||
dc008bf0 | 5548 | intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); |
060f02d8 VS |
5549 | |
5550 | mutex_lock(&dev_priv->sb_lock); | |
5551 | ||
5552 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
5553 | temp |= SBI_SSCCTL_DISABLE; | |
5554 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
5555 | ||
5556 | mutex_unlock(&dev_priv->sb_lock); | |
5557 | } | |
5558 | ||
e615efe4 | 5559 | /* Program iCLKIP clock to the desired frequency */ |
c5b36fac | 5560 | static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) |
e615efe4 | 5561 | { |
2225f3c6 | 5562 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
0dcdc382 | 5563 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1326a92c | 5564 | int clock = crtc_state->hw.adjusted_mode.crtc_clock; |
e615efe4 ED |
5565 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
5566 | u32 temp; | |
5567 | ||
060f02d8 | 5568 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 5569 | |
64b46a06 VS |
5570 | /* The iCLK virtual clock root frequency is in MHz, |
5571 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
5572 | * divisors, it is necessary to divide one by another, so we | |
5573 | * convert the virtual clock precision to KHz here for higher | |
5574 | * precision. | |
5575 | */ | |
5576 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
5577 | u32 iclk_virtual_root_freq = 172800 * 1000; |
5578 | u32 iclk_pi_range = 64; | |
64b46a06 | 5579 | u32 desired_divisor; |
e615efe4 | 5580 | |
64b46a06 VS |
5581 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
5582 | clock << auxdiv); | |
5583 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
5584 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 5585 | |
64b46a06 VS |
5586 | /* |
5587 | * Near 20MHz is a corner case which is | |
5588 | * out of range for the 7-bit divisor | |
5589 | */ | |
5590 | if (divsel <= 0x7f) | |
5591 | break; | |
e615efe4 ED |
5592 | } |
5593 | ||
5594 | /* This should not happen with any sane values */ | |
e57291c2 PB |
5595 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
5596 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
5597 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
5598 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
e615efe4 | 5599 | |
cd49f818 WK |
5600 | drm_dbg_kms(&dev_priv->drm, |
5601 | "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
5602 | clock, auxdiv, divsel, phasedir, phaseinc); | |
e615efe4 | 5603 | |
060f02d8 VS |
5604 | mutex_lock(&dev_priv->sb_lock); |
5605 | ||
e615efe4 | 5606 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 5607 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
5608 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
5609 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
5610 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
5611 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
5612 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
5613 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 5614 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
5615 | |
5616 | /* Program SSCAUXDIV */ | |
988d6ee8 | 5617 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
5618 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
5619 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 5620 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
5621 | |
5622 | /* Enable modulator and associated divider */ | |
988d6ee8 | 5623 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 5624 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 5625 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 5626 | |
060f02d8 VS |
5627 | mutex_unlock(&dev_priv->sb_lock); |
5628 | ||
e615efe4 ED |
5629 | /* Wait for initialization time */ |
5630 | udelay(24); | |
5631 | ||
dc008bf0 | 5632 | intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
e615efe4 ED |
5633 | } |
5634 | ||
8802e5b6 VS |
5635 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
5636 | { | |
5637 | u32 divsel, phaseinc, auxdiv; | |
5638 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
5639 | u32 iclk_pi_range = 64; | |
5640 | u32 desired_divisor; | |
5641 | u32 temp; | |
5642 | ||
dc008bf0 | 5643 | if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) |
8802e5b6 VS |
5644 | return 0; |
5645 | ||
5646 | mutex_lock(&dev_priv->sb_lock); | |
5647 | ||
5648 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
5649 | if (temp & SBI_SSCCTL_DISABLE) { | |
5650 | mutex_unlock(&dev_priv->sb_lock); | |
5651 | return 0; | |
5652 | } | |
5653 | ||
5654 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
5655 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
5656 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
5657 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
5658 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
5659 | ||
5660 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
5661 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
5662 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
5663 | ||
5664 | mutex_unlock(&dev_priv->sb_lock); | |
5665 | ||
5666 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
5667 | ||
5668 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
5669 | desired_divisor << auxdiv); | |
5670 | } | |
5671 | ||
9eae5e27 LDM |
5672 | static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, |
5673 | enum pipe pch_transcoder) | |
275f01b2 | 5674 | { |
2225f3c6 | 5675 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
5e1cdf54 ML |
5676 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5677 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
275f01b2 | 5678 | |
dc008bf0 JN |
5679 | intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), |
5680 | intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); | |
5681 | intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), | |
5682 | intel_de_read(dev_priv, HBLANK(cpu_transcoder))); | |
5683 | intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), | |
5684 | intel_de_read(dev_priv, HSYNC(cpu_transcoder))); | |
275f01b2 | 5685 | |
dc008bf0 JN |
5686 | intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), |
5687 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); | |
5688 | intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), | |
5689 | intel_de_read(dev_priv, VBLANK(cpu_transcoder))); | |
5690 | intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), | |
5691 | intel_de_read(dev_priv, VSYNC(cpu_transcoder))); | |
5692 | intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
5693 | intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); | |
275f01b2 DV |
5694 | } |
5695 | ||
b0b62d84 | 5696 | static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) |
1fbc0d78 | 5697 | { |
ba3f4d0a | 5698 | u32 temp; |
1fbc0d78 | 5699 | |
dc008bf0 | 5700 | temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); |
003632d9 | 5701 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
5702 | return; |
5703 | ||
e57291c2 PB |
5704 | drm_WARN_ON(&dev_priv->drm, |
5705 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & | |
5706 | FDI_RX_ENABLE); | |
5707 | drm_WARN_ON(&dev_priv->drm, | |
5708 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & | |
5709 | FDI_RX_ENABLE); | |
1fbc0d78 | 5710 | |
003632d9 ACO |
5711 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
5712 | if (enable) | |
5713 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5714 | ||
cd49f818 WK |
5715 | drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", |
5716 | enable ? "en" : "dis"); | |
dc008bf0 JN |
5717 | intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); |
5718 | intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); | |
1fbc0d78 DV |
5719 | } |
5720 | ||
74bb98ba | 5721 | static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) |
1fbc0d78 | 5722 | { |
2225f3c6 | 5723 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b0b62d84 | 5724 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1fbc0d78 | 5725 | |
b0b62d84 | 5726 | switch (crtc->pipe) { |
1fbc0d78 DV |
5727 | case PIPE_A: |
5728 | break; | |
5729 | case PIPE_B: | |
b0b62d84 ML |
5730 | if (crtc_state->fdi_lanes > 2) |
5731 | cpt_set_fdi_bc_bifurcation(dev_priv, false); | |
1fbc0d78 | 5732 | else |
b0b62d84 | 5733 | cpt_set_fdi_bc_bifurcation(dev_priv, true); |
1fbc0d78 DV |
5734 | |
5735 | break; | |
5736 | case PIPE_C: | |
b0b62d84 | 5737 | cpt_set_fdi_bc_bifurcation(dev_priv, true); |
1fbc0d78 DV |
5738 | |
5739 | break; | |
5740 | default: | |
5741 | BUG(); | |
5742 | } | |
5743 | } | |
5744 | ||
f606bc6d VS |
5745 | /* |
5746 | * Finds the encoder associated with the given CRTC. This can only be | |
5747 | * used when we know that the CRTC isn't feeding multiple encoders! | |
5748 | */ | |
5749 | static struct intel_encoder * | |
5a0b385e VS |
5750 | intel_get_crtc_new_encoder(const struct intel_atomic_state *state, |
5751 | const struct intel_crtc_state *crtc_state) | |
f606bc6d | 5752 | { |
2225f3c6 | 5753 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f606bc6d VS |
5754 | const struct drm_connector_state *connector_state; |
5755 | const struct drm_connector *connector; | |
5756 | struct intel_encoder *encoder = NULL; | |
5757 | int num_encoders = 0; | |
5758 | int i; | |
5759 | ||
5a0b385e | 5760 | for_each_new_connector_in_state(&state->base, connector, connector_state, i) { |
f606bc6d VS |
5761 | if (connector_state->crtc != &crtc->base) |
5762 | continue; | |
5763 | ||
5764 | encoder = to_intel_encoder(connector_state->best_encoder); | |
5765 | num_encoders++; | |
5766 | } | |
5767 | ||
3a47ae20 PB |
5768 | drm_WARN(encoder->base.dev, num_encoders != 1, |
5769 | "%d encoders for pipe %c\n", | |
5770 | num_encoders, pipe_name(crtc->pipe)); | |
f606bc6d VS |
5771 | |
5772 | return encoder; | |
5773 | } | |
5774 | ||
f67a559d JB |
5775 | /* |
5776 | * Enable PCH resources required for PCH ports: | |
5777 | * - PCH PLLs | |
5778 | * - FDI training & RX/TX | |
5779 | * - update transcoder timings | |
5780 | * - DP transcoding bits | |
5781 | * - transcoder | |
5782 | */ | |
9eae5e27 LDM |
5783 | static void ilk_pch_enable(const struct intel_atomic_state *state, |
5784 | const struct intel_crtc_state *crtc_state) | |
0e23b99d | 5785 | { |
2225f3c6 | 5786 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4cbe4b2b | 5787 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5788 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5789 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 5790 | u32 temp; |
2c07245f | 5791 | |
ab9412ba | 5792 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 5793 | |
fd6b8f43 | 5794 | if (IS_IVYBRIDGE(dev_priv)) |
74bb98ba | 5795 | ivb_update_fdi_bc_bifurcation(crtc_state); |
1fbc0d78 | 5796 | |
cd986abb DV |
5797 | /* Write the TU size bits before fdi link training, so that error |
5798 | * detection works. */ | |
dc008bf0 JN |
5799 | intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), |
5800 | intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
cd986abb | 5801 | |
c98e9dcf | 5802 | /* For PCH output, training FDI link */ |
dc4a1094 | 5803 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 5804 | |
3ad8a208 DV |
5805 | /* We need to program the right clock selection before writing the pixel |
5806 | * mutliplier into the DPLL. */ | |
6e266956 | 5807 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 5808 | u32 sel; |
4b645f14 | 5809 | |
dc008bf0 | 5810 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
11887397 DV |
5811 | temp |= TRANS_DPLL_ENABLE(pipe); |
5812 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 5813 | if (crtc_state->shared_dpll == |
8106ddbd | 5814 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
5815 | temp |= sel; |
5816 | else | |
5817 | temp &= ~sel; | |
dc008bf0 | 5818 | intel_de_write(dev_priv, PCH_DPLL_SEL, temp); |
c98e9dcf | 5819 | } |
5eddb70b | 5820 | |
3ad8a208 DV |
5821 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
5822 | * transcoder, and we actually should do this to not upset any PCH | |
5823 | * transcoder that already use the clock when we share it. | |
5824 | * | |
5825 | * Note that enable_shared_dpll tries to do the right thing, but | |
5826 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
5827 | * the right LVDS enable sequence. */ | |
65c307fd | 5828 | intel_enable_shared_dpll(crtc_state); |
3ad8a208 | 5829 | |
d9b6cb56 JB |
5830 | /* set transcoder timing, panel must allow it */ |
5831 | assert_panel_unlocked(dev_priv, pipe); | |
9eae5e27 | 5832 | ilk_pch_transcoder_set_timings(crtc_state, pipe); |
8db9d77b | 5833 | |
303b81e0 | 5834 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 5835 | |
c98e9dcf | 5836 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 5837 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 5838 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 5839 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 5840 | &crtc_state->hw.adjusted_mode; |
dc008bf0 | 5841 | u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 5842 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
f67dc6d8 VS |
5843 | enum port port; |
5844 | ||
dc008bf0 | 5845 | temp = intel_de_read(dev_priv, reg); |
5eddb70b | 5846 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
220cad3c EA |
5847 | TRANS_DP_SYNC_MASK | |
5848 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 5849 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 5850 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 5851 | |
9c4edaee | 5852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 5853 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 5854 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 5855 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf | 5856 | |
5a0b385e | 5857 | port = intel_get_crtc_new_encoder(state, crtc_state)->port; |
e57291c2 | 5858 | drm_WARN_ON(dev, port < PORT_B || port > PORT_D); |
f67dc6d8 | 5859 | temp |= TRANS_DP_PORT_SEL(port); |
2c07245f | 5860 | |
dc008bf0 | 5861 | intel_de_write(dev_priv, reg, temp); |
6be4a607 | 5862 | } |
b52eb4dc | 5863 | |
9eae5e27 | 5864 | ilk_enable_pch_transcoder(crtc_state); |
f67a559d JB |
5865 | } |
5866 | ||
21fd23ac | 5867 | void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 5868 | { |
2225f3c6 | 5869 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
0dcdc382 | 5870 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 5871 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 5872 | |
a2196033 | 5873 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 5874 | |
c5b36fac | 5875 | lpt_program_iclkip(crtc_state); |
1507e5bd | 5876 | |
0540e488 | 5877 | /* Set transcoder timing. */ |
9eae5e27 | 5878 | ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); |
1507e5bd | 5879 | |
937bb610 | 5880 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
5881 | } |
5882 | ||
c684fb44 VS |
5883 | static void cpt_verify_modeset(struct drm_i915_private *dev_priv, |
5884 | enum pipe pipe) | |
d4270e57 | 5885 | { |
f0f59a00 | 5886 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
5887 | u32 temp; |
5888 | ||
dc008bf0 | 5889 | temp = intel_de_read(dev_priv, dslreg); |
d4270e57 | 5890 | udelay(500); |
dc008bf0 JN |
5891 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { |
5892 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) | |
cd49f818 WK |
5893 | drm_err(&dev_priv->drm, |
5894 | "mode set failed: pipe %c stuck\n", | |
5895 | pipe_name(pipe)); | |
d4270e57 JB |
5896 | } |
5897 | } | |
5898 | ||
0a59952b VS |
5899 | /* |
5900 | * The hardware phase 0.0 refers to the center of the pixel. | |
5901 | * We want to start from the top/left edge which is phase | |
5902 | * -0.5. That matches how the hardware calculates the scaling | |
5903 | * factors (from top-left of the first pixel to bottom-right | |
5904 | * of the last pixel, as opposed to the pixel centers). | |
5905 | * | |
5906 | * For 4:2:0 subsampled chroma planes we obviously have to | |
5907 | * adjust that so that the chroma sample position lands in | |
5908 | * the right spot. | |
5909 | * | |
5910 | * Note that for packed YCbCr 4:2:2 formats there is no way to | |
5911 | * control chroma siting. The hardware simply replicates the | |
5912 | * chroma samples for both of the luma samples, and thus we don't | |
5913 | * actually get the expected MPEG2 chroma siting convention :( | |
5914 | * The same behaviour is observed on pre-SKL platforms as well. | |
e7a278a3 VS |
5915 | * |
5916 | * Theory behind the formula (note that we ignore sub-pixel | |
5917 | * source coordinates): | |
5918 | * s = source sample position | |
5919 | * d = destination sample position | |
5920 | * | |
5921 | * Downscaling 4:1: | |
5922 | * -0.5 | |
5923 | * | 0.0 | |
5924 | * | | 1.5 (initial phase) | |
5925 | * | | | | |
5926 | * v v v | |
5927 | * | s | s | s | s | | |
5928 | * | d | | |
5929 | * | |
5930 | * Upscaling 1:4: | |
5931 | * -0.5 | |
5932 | * | -0.375 (initial phase) | |
5933 | * | | 0.0 | |
5934 | * | | | | |
5935 | * v v v | |
5936 | * | s | | |
5937 | * | d | d | d | d | | |
0a59952b | 5938 | */ |
e7a278a3 | 5939 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) |
0a59952b VS |
5940 | { |
5941 | int phase = -0x8000; | |
5942 | u16 trip = 0; | |
5943 | ||
5944 | if (chroma_cosited) | |
5945 | phase += (sub - 1) * 0x8000 / sub; | |
5946 | ||
e7a278a3 VS |
5947 | phase += scale / (2 * sub); |
5948 | ||
5949 | /* | |
5950 | * Hardware initial phase limited to [-0.5:1.5]. | |
5951 | * Since the max hardware scale factor is 3.0, we | |
5952 | * should never actually excdeed 1.0 here. | |
5953 | */ | |
5954 | WARN_ON(phase < -0x8000 || phase > 0x18000); | |
5955 | ||
0a59952b VS |
5956 | if (phase < 0) |
5957 | phase = 0x10000 + phase; | |
5958 | else | |
5959 | trip = PS_PHASE_TRIP; | |
5960 | ||
5961 | return ((phase >> 2) & PS_PHASE_MASK) | trip; | |
5962 | } | |
5963 | ||
69f44d3b JN |
5964 | #define SKL_MIN_SRC_W 8 |
5965 | #define SKL_MAX_SRC_W 4096 | |
5966 | #define SKL_MIN_SRC_H 8 | |
5967 | #define SKL_MAX_SRC_H 4096 | |
5968 | #define SKL_MIN_DST_W 8 | |
5969 | #define SKL_MAX_DST_W 4096 | |
5970 | #define SKL_MIN_DST_H 8 | |
5971 | #define SKL_MAX_DST_H 4096 | |
5972 | #define ICL_MAX_SRC_W 5120 | |
5973 | #define ICL_MAX_SRC_H 4096 | |
5974 | #define ICL_MAX_DST_W 5120 | |
5975 | #define ICL_MAX_DST_H 4096 | |
5976 | #define SKL_MIN_YUV_420_SRC_W 16 | |
5977 | #define SKL_MIN_YUV_420_SRC_H 16 | |
5978 | ||
86adf9d7 ML |
5979 | static int |
5980 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 5981 | unsigned int scaler_user, int *scaler_id, |
77224cd5 | 5982 | int src_w, int src_h, int dst_w, int dst_h, |
4941f35b ID |
5983 | const struct drm_format_info *format, |
5984 | u64 modifier, bool need_scaler) | |
a1b2278e | 5985 | { |
86adf9d7 ML |
5986 | struct intel_crtc_scaler_state *scaler_state = |
5987 | &crtc_state->scaler_state; | |
5988 | struct intel_crtc *intel_crtc = | |
2225f3c6 | 5989 | to_intel_crtc(crtc_state->uapi.crtc); |
7f58cbb1 MK |
5990 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
5991 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 5992 | &crtc_state->hw.adjusted_mode; |
6156a456 | 5993 | |
d96a7d2a VS |
5994 | /* |
5995 | * Src coordinates are already rotated by 270 degrees for | |
5996 | * the 90/270 degree plane rotation cases (to match the | |
5997 | * GTT mapping), hence no need to account for rotation here. | |
5998 | */ | |
b1554e23 ML |
5999 | if (src_w != dst_w || src_h != dst_h) |
6000 | need_scaler = true; | |
e5c05931 | 6001 | |
7f58cbb1 MK |
6002 | /* |
6003 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
6004 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
6005 | * Once NV12 is enabled, handle it here while allocating scaler | |
6006 | * for NV12. | |
6007 | */ | |
1326a92c | 6008 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable && |
b1554e23 | 6009 | need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
cd49f818 WK |
6010 | drm_dbg_kms(&dev_priv->drm, |
6011 | "Pipe/Plane scaling not supported with IF-ID mode\n"); | |
7f58cbb1 MK |
6012 | return -EINVAL; |
6013 | } | |
6014 | ||
a1b2278e CK |
6015 | /* |
6016 | * if plane is being disabled or scaler is no more required or force detach | |
6017 | * - free scaler binded to this plane/crtc | |
6018 | * - in order to do this, update crtc->scaler_usage | |
6019 | * | |
6020 | * Here scaler state in crtc_state is set free so that | |
6021 | * scaler can be assigned to other user. Actual register | |
6022 | * update to free the scaler is done in plane/panel-fit programming. | |
6023 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
6024 | */ | |
b1554e23 | 6025 | if (force_detach || !need_scaler) { |
a1b2278e | 6026 | if (*scaler_id >= 0) { |
86adf9d7 | 6027 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
6028 | scaler_state->scalers[*scaler_id].in_use = 0; |
6029 | ||
cd49f818 WK |
6030 | drm_dbg_kms(&dev_priv->drm, |
6031 | "scaler_user index %u.%u: " | |
6032 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
6033 | intel_crtc->pipe, scaler_user, *scaler_id, | |
6034 | scaler_state->scaler_users); | |
a1b2278e CK |
6035 | *scaler_id = -1; |
6036 | } | |
6037 | return 0; | |
6038 | } | |
6039 | ||
4941f35b | 6040 | if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && |
5d794288 | 6041 | (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { |
cd49f818 WK |
6042 | drm_dbg_kms(&dev_priv->drm, |
6043 | "Planar YUV: src dimensions not met\n"); | |
77224cd5 CK |
6044 | return -EINVAL; |
6045 | } | |
6046 | ||
a1b2278e CK |
6047 | /* range checks */ |
6048 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
323301af | 6049 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
2dd24a9c | 6050 | (INTEL_GEN(dev_priv) >= 11 && |
323301af NM |
6051 | (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || |
6052 | dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || | |
2dd24a9c | 6053 | (INTEL_GEN(dev_priv) < 11 && |
323301af NM |
6054 | (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
6055 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { | |
cd49f818 WK |
6056 | drm_dbg_kms(&dev_priv->drm, |
6057 | "scaler_user index %u.%u: src %ux%u dst %ux%u " | |
6058 | "size is out of scaler range\n", | |
6059 | intel_crtc->pipe, scaler_user, src_w, src_h, | |
6060 | dst_w, dst_h); | |
a1b2278e CK |
6061 | return -EINVAL; |
6062 | } | |
6063 | ||
86adf9d7 ML |
6064 | /* mark this plane as a scaler user in crtc_state */ |
6065 | scaler_state->scaler_users |= (1 << scaler_user); | |
cd49f818 WK |
6066 | drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " |
6067 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
6068 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
6069 | scaler_state->scaler_users); | |
86adf9d7 ML |
6070 | |
6071 | return 0; | |
6072 | } | |
6073 | ||
c5a01ec7 | 6074 | static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) |
86adf9d7 | 6075 | { |
bafcdad6 | 6076 | const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; |
c5a01ec7 | 6077 | int width, height; |
b1554e23 | 6078 | |
c5a01ec7 | 6079 | if (crtc_state->pch_pfit.enabled) { |
35dd95b4 VS |
6080 | width = drm_rect_width(&crtc_state->pch_pfit.dst); |
6081 | height = drm_rect_height(&crtc_state->pch_pfit.dst); | |
c5a01ec7 | 6082 | } else { |
bafcdad6 ML |
6083 | width = pipe_mode->crtc_hdisplay; |
6084 | height = pipe_mode->crtc_vdisplay; | |
c5a01ec7 | 6085 | } |
c5a01ec7 VS |
6086 | return skl_update_scaler(crtc_state, !crtc_state->hw.active, |
6087 | SKL_CRTC_INDEX, | |
6088 | &crtc_state->scaler_state.scaler_id, | |
6089 | crtc_state->pipe_src_w, crtc_state->pipe_src_h, | |
6090 | width, height, NULL, 0, | |
6091 | crtc_state->pch_pfit.enabled); | |
86adf9d7 ML |
6092 | } |
6093 | ||
6094 | /** | |
6095 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
c38c1455 | 6096 | * @crtc_state: crtc's scaler state |
86adf9d7 ML |
6097 | * @plane_state: atomic plane state to update |
6098 | * | |
6099 | * Return | |
6100 | * 0 - scaler_usage updated successfully | |
6101 | * error - requested scaling cannot be supported or other error condition | |
6102 | */ | |
da20eabd ML |
6103 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
6104 | struct intel_plane_state *plane_state) | |
86adf9d7 | 6105 | { |
da20eabd | 6106 | struct intel_plane *intel_plane = |
f90a85e7 | 6107 | to_intel_plane(plane_state->uapi.plane); |
42fd20ed | 6108 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
7b3cb17a | 6109 | struct drm_framebuffer *fb = plane_state->hw.fb; |
86adf9d7 | 6110 | int ret; |
f90a85e7 | 6111 | bool force_detach = !fb || !plane_state->uapi.visible; |
b1554e23 ML |
6112 | bool need_scaler = false; |
6113 | ||
6114 | /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ | |
42fd20ed | 6115 | if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && |
4941f35b | 6116 | fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) |
b1554e23 | 6117 | need_scaler = true; |
86adf9d7 | 6118 | |
86adf9d7 ML |
6119 | ret = skl_update_scaler(crtc_state, force_detach, |
6120 | drm_plane_index(&intel_plane->base), | |
6121 | &plane_state->scaler_id, | |
f90a85e7 ML |
6122 | drm_rect_width(&plane_state->uapi.src) >> 16, |
6123 | drm_rect_height(&plane_state->uapi.src) >> 16, | |
6124 | drm_rect_width(&plane_state->uapi.dst), | |
6125 | drm_rect_height(&plane_state->uapi.dst), | |
4941f35b ID |
6126 | fb ? fb->format : NULL, |
6127 | fb ? fb->modifier : 0, | |
6128 | need_scaler); | |
86adf9d7 ML |
6129 | |
6130 | if (ret || plane_state->scaler_id < 0) | |
6131 | return ret; | |
6132 | ||
a1b2278e | 6133 | /* check colorkey */ |
6ec5bd34 | 6134 | if (plane_state->ckey.flags) { |
cd49f818 WK |
6135 | drm_dbg_kms(&dev_priv->drm, |
6136 | "[PLANE:%d:%s] scaling with color key not allowed", | |
6137 | intel_plane->base.base.id, | |
6138 | intel_plane->base.name); | |
a1b2278e CK |
6139 | return -EINVAL; |
6140 | } | |
6141 | ||
6142 | /* Check src format */ | |
438b74a5 | 6143 | switch (fb->format->format) { |
86adf9d7 ML |
6144 | case DRM_FORMAT_RGB565: |
6145 | case DRM_FORMAT_XBGR8888: | |
6146 | case DRM_FORMAT_XRGB8888: | |
6147 | case DRM_FORMAT_ABGR8888: | |
6148 | case DRM_FORMAT_ARGB8888: | |
6149 | case DRM_FORMAT_XRGB2101010: | |
6150 | case DRM_FORMAT_XBGR2101010: | |
f9c43a31 VS |
6151 | case DRM_FORMAT_ARGB2101010: |
6152 | case DRM_FORMAT_ABGR2101010: | |
86adf9d7 ML |
6153 | case DRM_FORMAT_YUYV: |
6154 | case DRM_FORMAT_YVYU: | |
6155 | case DRM_FORMAT_UYVY: | |
6156 | case DRM_FORMAT_VYUY: | |
77224cd5 | 6157 | case DRM_FORMAT_NV12: |
da904174 | 6158 | case DRM_FORMAT_XYUV8888: |
df7d4156 JPH |
6159 | case DRM_FORMAT_P010: |
6160 | case DRM_FORMAT_P012: | |
6161 | case DRM_FORMAT_P016: | |
296e9b19 SS |
6162 | case DRM_FORMAT_Y210: |
6163 | case DRM_FORMAT_Y212: | |
6164 | case DRM_FORMAT_Y216: | |
ff01e697 ML |
6165 | case DRM_FORMAT_XVYU2101010: |
6166 | case DRM_FORMAT_XVYU12_16161616: | |
6167 | case DRM_FORMAT_XVYU16161616: | |
86adf9d7 | 6168 | break; |
6e6c155d VS |
6169 | case DRM_FORMAT_XBGR16161616F: |
6170 | case DRM_FORMAT_ABGR16161616F: | |
6171 | case DRM_FORMAT_XRGB16161616F: | |
6172 | case DRM_FORMAT_ARGB16161616F: | |
6173 | if (INTEL_GEN(dev_priv) >= 11) | |
6174 | break; | |
df561f66 | 6175 | fallthrough; |
86adf9d7 | 6176 | default: |
cd49f818 WK |
6177 | drm_dbg_kms(&dev_priv->drm, |
6178 | "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", | |
6179 | intel_plane->base.base.id, intel_plane->base.name, | |
6180 | fb->base.id, fb->format->format); | |
86adf9d7 | 6181 | return -EINVAL; |
a1b2278e CK |
6182 | } |
6183 | ||
a1b2278e CK |
6184 | return 0; |
6185 | } | |
6186 | ||
f6df4d46 | 6187 | void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) |
e435d6e5 | 6188 | { |
cfb627c4 | 6189 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
e435d6e5 ML |
6190 | int i; |
6191 | ||
6192 | for (i = 0; i < crtc->num_scalers; i++) | |
6193 | skl_detach_scaler(crtc, i); | |
6194 | } | |
6195 | ||
cc2396ff PB |
6196 | static int cnl_coef_tap(int i) |
6197 | { | |
6198 | return i % 7; | |
6199 | } | |
6200 | ||
6201 | static u16 cnl_nearest_filter_coef(int t) | |
6202 | { | |
6203 | return t == 3 ? 0x0800 : 0x3000; | |
6204 | } | |
6205 | ||
176fd228 | 6206 | /* |
cc2396ff PB |
6207 | * Theory behind setting nearest-neighbor integer scaling: |
6208 | * | |
6209 | * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. | |
6210 | * The letter represents the filter tap (D is the center tap) and the number | |
6211 | * represents the coefficient set for a phase (0-16). | |
6212 | * | |
6213 | * +------------+------------------------+------------------------+ | |
6214 | * |Index value | Data value coeffient 1 | Data value coeffient 2 | | |
6215 | * +------------+------------------------+------------------------+ | |
6216 | * | 00h | B0 | A0 | | |
6217 | * +------------+------------------------+------------------------+ | |
6218 | * | 01h | D0 | C0 | | |
6219 | * +------------+------------------------+------------------------+ | |
6220 | * | 02h | F0 | E0 | | |
6221 | * +------------+------------------------+------------------------+ | |
6222 | * | 03h | A1 | G0 | | |
6223 | * +------------+------------------------+------------------------+ | |
6224 | * | 04h | C1 | B1 | | |
6225 | * +------------+------------------------+------------------------+ | |
6226 | * | ... | ... | ... | | |
6227 | * +------------+------------------------+------------------------+ | |
6228 | * | 38h | B16 | A16 | | |
6229 | * +------------+------------------------+------------------------+ | |
6230 | * | 39h | D16 | C16 | | |
6231 | * +------------+------------------------+------------------------+ | |
6232 | * | 3Ah | F16 | C16 | | |
6233 | * +------------+------------------------+------------------------+ | |
6234 | * | 3Bh | Reserved | G16 | | |
6235 | * +------------+------------------------+------------------------+ | |
6236 | * | |
6237 | * To enable nearest-neighbor scaling: program scaler coefficents with | |
6238 | * the center tap (Dxx) values set to 1 and all other values set to 0 as per | |
6239 | * SCALER_COEFFICIENT_FORMAT | |
6240 | * | |
6241 | */ | |
6242 | ||
6243 | static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv, | |
6244 | enum pipe pipe, int id, int set) | |
6245 | { | |
6246 | int i; | |
6247 | ||
6248 | intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), | |
6249 | PS_COEE_INDEX_AUTO_INC); | |
6250 | ||
6251 | for (i = 0; i < 17 * 7; i += 2) { | |
6252 | u32 tmp; | |
6253 | int t; | |
6254 | ||
6255 | t = cnl_coef_tap(i); | |
6256 | tmp = cnl_nearest_filter_coef(t); | |
6257 | ||
6258 | t = cnl_coef_tap(i + 1); | |
6259 | tmp |= cnl_nearest_filter_coef(t) << 16; | |
6260 | ||
6261 | intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set), | |
6262 | tmp); | |
6263 | } | |
6264 | ||
6265 | intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0); | |
6266 | } | |
6267 | ||
6268 | inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) | |
6269 | { | |
6270 | if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { | |
6271 | return (PS_FILTER_PROGRAMMED | | |
6272 | PS_Y_VERT_FILTER_SELECT(set) | | |
6273 | PS_Y_HORZ_FILTER_SELECT(set) | | |
6274 | PS_UV_VERT_FILTER_SELECT(set) | | |
6275 | PS_UV_HORZ_FILTER_SELECT(set)); | |
6276 | } | |
6277 | ||
6278 | return PS_FILTER_MEDIUM; | |
6279 | } | |
6280 | ||
6281 | void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, | |
6282 | int id, int set, enum drm_scaling_filter filter) | |
6283 | { | |
6284 | switch (filter) { | |
6285 | case DRM_SCALING_FILTER_DEFAULT: | |
6286 | break; | |
6287 | case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: | |
6288 | cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set); | |
6289 | break; | |
6290 | default: | |
6291 | MISSING_CASE(filter); | |
6292 | } | |
6293 | } | |
6294 | ||
f6df4d46 | 6295 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) |
bd2e244f | 6296 | { |
2225f3c6 | 6297 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 6298 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b2562712 ML |
6299 | const struct intel_crtc_scaler_state *scaler_state = |
6300 | &crtc_state->scaler_state; | |
35dd95b4 VS |
6301 | struct drm_rect src = { |
6302 | .x2 = crtc_state->pipe_src_w << 16, | |
6303 | .y2 = crtc_state->pipe_src_h << 16, | |
6304 | }; | |
6305 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; | |
eac9c585 | 6306 | u16 uv_rgb_hphase, uv_rgb_vphase; |
35dd95b4 VS |
6307 | enum pipe pipe = crtc->pipe; |
6308 | int width = drm_rect_width(dst); | |
6309 | int height = drm_rect_height(dst); | |
6310 | int x = dst->x1; | |
6311 | int y = dst->y1; | |
6312 | int hscale, vscale; | |
eac9c585 VS |
6313 | unsigned long irqflags; |
6314 | int id; | |
6d1a2fde | 6315 | u32 ps_ctrl; |
a1b2278e | 6316 | |
eac9c585 VS |
6317 | if (!crtc_state->pch_pfit.enabled) |
6318 | return; | |
a1b2278e | 6319 | |
eac9c585 VS |
6320 | if (drm_WARN_ON(&dev_priv->drm, |
6321 | crtc_state->scaler_state.scaler_id < 0)) | |
6322 | return; | |
a1b2278e | 6323 | |
35dd95b4 VS |
6324 | hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); |
6325 | vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); | |
e7a278a3 | 6326 | |
eac9c585 VS |
6327 | uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); |
6328 | uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); | |
0a59952b | 6329 | |
eac9c585 | 6330 | id = scaler_state->scaler_id; |
f986ef2e | 6331 | |
6d1a2fde PB |
6332 | ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); |
6333 | ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode; | |
6334 | ||
eac9c585 | 6335 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
f986ef2e | 6336 | |
6d1a2fde PB |
6337 | skl_scaler_setup_filter(dev_priv, pipe, id, 0, |
6338 | crtc_state->hw.scaling_filter); | |
6339 | ||
6340 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); | |
6341 | ||
eac9c585 VS |
6342 | intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), |
6343 | PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); | |
6344 | intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), | |
6345 | PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); | |
6346 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), | |
35dd95b4 | 6347 | x << 16 | y); |
eac9c585 | 6348 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), |
35dd95b4 | 6349 | width << 16 | height); |
f986ef2e | 6350 | |
eac9c585 | 6351 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
bd2e244f JB |
6352 | } |
6353 | ||
9eae5e27 | 6354 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) |
b074cec8 | 6355 | { |
2225f3c6 | 6356 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 6357 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
35dd95b4 | 6358 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; |
d048a268 | 6359 | enum pipe pipe = crtc->pipe; |
35dd95b4 VS |
6360 | int width = drm_rect_width(dst); |
6361 | int height = drm_rect_height(dst); | |
6362 | int x = dst->x1; | |
6363 | int y = dst->y1; | |
b074cec8 | 6364 | |
eac9c585 VS |
6365 | if (!crtc_state->pch_pfit.enabled) |
6366 | return; | |
6367 | ||
6368 | /* Force use of hard-coded filter coefficients | |
6369 | * as some pre-programmed values are broken, | |
6370 | * e.g. x201. | |
6371 | */ | |
6372 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) | |
6373 | intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | | |
6374 | PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); | |
6375 | else | |
6376 | intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | | |
6377 | PF_FILTER_MED_3x3); | |
35dd95b4 VS |
6378 | intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y); |
6379 | intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); | |
d4270e57 JB |
6380 | } |
6381 | ||
199ea381 | 6382 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state) |
d77e4531 | 6383 | { |
2225f3c6 | 6384 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
cea165c3 | 6385 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6386 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 6387 | |
24f28450 | 6388 | if (!crtc_state->ips_enabled) |
d77e4531 PZ |
6389 | return; |
6390 | ||
307e4498 ML |
6391 | /* |
6392 | * We can only enable IPS after we enable a plane and wait for a vblank | |
6393 | * This function is called from post_plane_update, which is run after | |
6394 | * a vblank wait. | |
6395 | */ | |
e57291c2 | 6396 | drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); |
51f5a096 | 6397 | |
8652744b | 6398 | if (IS_BROADWELL(dev_priv)) { |
e57291c2 PB |
6399 | drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, |
6400 | IPS_ENABLE | IPS_PCODE_CONTROL)); | |
2a114cc1 BW |
6401 | /* Quoting Art Runyan: "its not safe to expect any particular |
6402 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
6403 | * mailbox." Moreover, the mailbox may return a bogus state, |
6404 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
6405 | */ |
6406 | } else { | |
dc008bf0 | 6407 | intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE); |
2a114cc1 BW |
6408 | /* The bit only becomes 1 in the next vblank, so this wait here |
6409 | * is essentially intel_wait_for_vblank. If we don't have this | |
6410 | * and don't wait for vblanks until the end of crtc_enable, then | |
6411 | * the HW state readout code will complain that the expected | |
6412 | * IPS_CTL value is not the one we read. */ | |
4cb3b44d | 6413 | if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50)) |
cd49f818 WK |
6414 | drm_err(&dev_priv->drm, |
6415 | "Timed out waiting for IPS enable\n"); | |
2a114cc1 | 6416 | } |
d77e4531 PZ |
6417 | } |
6418 | ||
199ea381 | 6419 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state) |
d77e4531 | 6420 | { |
2225f3c6 | 6421 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
d77e4531 | 6422 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6423 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 6424 | |
199ea381 | 6425 | if (!crtc_state->ips_enabled) |
d77e4531 PZ |
6426 | return; |
6427 | ||
8652744b | 6428 | if (IS_BROADWELL(dev_priv)) { |
e57291c2 PB |
6429 | drm_WARN_ON(dev, |
6430 | sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
acb3ef0e ID |
6431 | /* |
6432 | * Wait for PCODE to finish disabling IPS. The BSpec specified | |
6433 | * 42ms timeout value leads to occasional timeouts so use 100ms | |
6434 | * instead. | |
6435 | */ | |
4cb3b44d | 6436 | if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100)) |
cd49f818 WK |
6437 | drm_err(&dev_priv->drm, |
6438 | "Timed out waiting for IPS disable\n"); | |
e59150dc | 6439 | } else { |
dc008bf0 JN |
6440 | intel_de_write(dev_priv, IPS_CTL, 0); |
6441 | intel_de_posting_read(dev_priv, IPS_CTL); | |
e59150dc | 6442 | } |
d77e4531 PZ |
6443 | |
6444 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 6445 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
6446 | } |
6447 | ||
7cac945f | 6448 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 6449 | { |
cb5eb072 | 6450 | if (intel_crtc->overlay) |
d3eedb1a | 6451 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
6452 | |
6453 | /* Let userspace switch the overlay on again. In most cases userspace | |
6454 | * has to recompute where to put it anyway. | |
6455 | */ | |
6456 | } | |
6457 | ||
24f28450 ML |
6458 | static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, |
6459 | const struct intel_crtc_state *new_crtc_state) | |
6460 | { | |
2225f3c6 | 6461 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
051a6d8d VS |
6462 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6463 | ||
24f28450 ML |
6464 | if (!old_crtc_state->ips_enabled) |
6465 | return false; | |
6466 | ||
69f786ae | 6467 | if (needs_modeset(new_crtc_state)) |
24f28450 ML |
6468 | return true; |
6469 | ||
051a6d8d VS |
6470 | /* |
6471 | * Workaround : Do not read or write the pipe palette/gamma data while | |
6472 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6473 | * | |
6474 | * Disable IPS before we program the LUT. | |
6475 | */ | |
6476 | if (IS_HASWELL(dev_priv) && | |
2225f3c6 | 6477 | (new_crtc_state->uapi.color_mgmt_changed || |
051a6d8d VS |
6478 | new_crtc_state->update_pipe) && |
6479 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) | |
6480 | return true; | |
6481 | ||
24f28450 ML |
6482 | return !new_crtc_state->ips_enabled; |
6483 | } | |
6484 | ||
6485 | static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, | |
6486 | const struct intel_crtc_state *new_crtc_state) | |
6487 | { | |
2225f3c6 | 6488 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
051a6d8d VS |
6489 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6490 | ||
24f28450 ML |
6491 | if (!new_crtc_state->ips_enabled) |
6492 | return false; | |
6493 | ||
69f786ae | 6494 | if (needs_modeset(new_crtc_state)) |
24f28450 ML |
6495 | return true; |
6496 | ||
051a6d8d VS |
6497 | /* |
6498 | * Workaround : Do not read or write the pipe palette/gamma data while | |
6499 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6500 | * | |
6501 | * Re-enable IPS after the LUT has been programmed. | |
6502 | */ | |
6503 | if (IS_HASWELL(dev_priv) && | |
2225f3c6 | 6504 | (new_crtc_state->uapi.color_mgmt_changed || |
051a6d8d VS |
6505 | new_crtc_state->update_pipe) && |
6506 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) | |
6507 | return true; | |
6508 | ||
24f28450 ML |
6509 | /* |
6510 | * We can't read out IPS on broadwell, assume the worst and | |
6511 | * forcibly enable IPS on the first fastset. | |
6512 | */ | |
a227569d | 6513 | if (new_crtc_state->update_pipe && old_crtc_state->inherited) |
24f28450 ML |
6514 | return true; |
6515 | ||
6516 | return !old_crtc_state->ips_enabled; | |
6517 | } | |
6518 | ||
d2432796 | 6519 | static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) |
8e021151 | 6520 | { |
d2432796 VS |
6521 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
6522 | ||
8e021151 ML |
6523 | if (!crtc_state->nv12_planes) |
6524 | return false; | |
6525 | ||
1347d3ce | 6526 | /* WA Display #0827: Gen9:all */ |
cf819eff | 6527 | if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) |
8e021151 ML |
6528 | return true; |
6529 | ||
6530 | return false; | |
6531 | } | |
6532 | ||
d2432796 | 6533 | static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) |
51eb1a1d | 6534 | { |
d2432796 VS |
6535 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
6536 | ||
f96198ab MA |
6537 | /* Wa_2006604312:icl,ehl */ |
6538 | if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11)) | |
51eb1a1d RS |
6539 | return true; |
6540 | ||
6541 | return false; | |
6542 | } | |
6543 | ||
7181f5c5 VS |
6544 | static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, |
6545 | const struct intel_crtc_state *new_crtc_state) | |
6546 | { | |
6547 | return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) && | |
6548 | new_crtc_state->active_planes; | |
6549 | } | |
6550 | ||
6551 | static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, | |
6552 | const struct intel_crtc_state *new_crtc_state) | |
6553 | { | |
6554 | return old_crtc_state->active_planes && | |
6555 | (!new_crtc_state->active_planes || needs_modeset(new_crtc_state)); | |
6556 | } | |
6557 | ||
bee43ca4 VS |
6558 | static void intel_post_plane_update(struct intel_atomic_state *state, |
6559 | struct intel_crtc *crtc) | |
5a21b665 | 6560 | { |
bee43ca4 | 6561 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
bee43ca4 VS |
6562 | const struct intel_crtc_state *old_crtc_state = |
6563 | intel_atomic_get_old_crtc_state(state, crtc); | |
6564 | const struct intel_crtc_state *new_crtc_state = | |
6565 | intel_atomic_get_new_crtc_state(state, crtc); | |
7181f5c5 | 6566 | enum pipe pipe = crtc->pipe; |
5a21b665 | 6567 | |
bee43ca4 | 6568 | intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); |
5a21b665 | 6569 | |
0e75fb8c | 6570 | if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) |
432081bc | 6571 | intel_update_watermarks(crtc); |
5a21b665 | 6572 | |
0e75fb8c VS |
6573 | if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state)) |
6574 | hsw_enable_ips(new_crtc_state); | |
24f28450 | 6575 | |
9ecc6eab | 6576 | intel_fbc_post_update(state, crtc); |
5a21b665 | 6577 | |
d2432796 | 6578 | if (needs_nv12_wa(old_crtc_state) && |
0e75fb8c | 6579 | !needs_nv12_wa(new_crtc_state)) |
7181f5c5 | 6580 | skl_wa_827(dev_priv, pipe, false); |
51eb1a1d | 6581 | |
d2432796 | 6582 | if (needs_scalerclk_wa(old_crtc_state) && |
0e75fb8c | 6583 | !needs_scalerclk_wa(new_crtc_state)) |
7181f5c5 | 6584 | icl_wa_scalerclkgating(dev_priv, pipe, false); |
5a21b665 DV |
6585 | } |
6586 | ||
e5cb1afb K |
6587 | static void skl_disable_async_flip_wa(struct intel_atomic_state *state, |
6588 | struct intel_crtc *crtc, | |
6589 | const struct intel_crtc_state *new_crtc_state) | |
6590 | { | |
6591 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
6592 | struct intel_plane *plane; | |
6593 | struct intel_plane_state *new_plane_state; | |
6594 | int i; | |
6595 | ||
6596 | for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { | |
6597 | u32 update_mask = new_crtc_state->update_planes; | |
6598 | u32 plane_ctl, surf_addr; | |
6599 | enum plane_id plane_id; | |
6600 | unsigned long irqflags; | |
6601 | enum pipe pipe; | |
6602 | ||
6603 | if (crtc->pipe != plane->pipe || | |
6604 | !(update_mask & BIT(plane->id))) | |
6605 | continue; | |
6606 | ||
6607 | plane_id = plane->id; | |
6608 | pipe = plane->pipe; | |
6609 | ||
6610 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
6611 | plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id)); | |
6612 | surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); | |
6613 | ||
6614 | plane_ctl &= ~PLANE_CTL_ASYNC_FLIP; | |
6615 | ||
6616 | intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); | |
6617 | intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr); | |
6618 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
6619 | } | |
6620 | ||
6621 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
6622 | } | |
6623 | ||
bee43ca4 VS |
6624 | static void intel_pre_plane_update(struct intel_atomic_state *state, |
6625 | struct intel_crtc *crtc) | |
ac21b225 | 6626 | { |
bee43ca4 | 6627 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
bee43ca4 VS |
6628 | const struct intel_crtc_state *old_crtc_state = |
6629 | intel_atomic_get_old_crtc_state(state, crtc); | |
6630 | const struct intel_crtc_state *new_crtc_state = | |
6631 | intel_atomic_get_new_crtc_state(state, crtc); | |
7181f5c5 | 6632 | enum pipe pipe = crtc->pipe; |
ac21b225 | 6633 | |
0e75fb8c | 6634 | if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state)) |
24f28450 ML |
6635 | hsw_disable_ips(old_crtc_state); |
6636 | ||
9ecc6eab | 6637 | if (intel_fbc_pre_update(state, crtc)) |
07fd0df8 VS |
6638 | intel_wait_for_vblank(dev_priv, pipe); |
6639 | ||
8e021151 | 6640 | /* Display WA 827 */ |
d2432796 | 6641 | if (!needs_nv12_wa(old_crtc_state) && |
0e75fb8c | 6642 | needs_nv12_wa(new_crtc_state)) |
7181f5c5 | 6643 | skl_wa_827(dev_priv, pipe, true); |
51eb1a1d | 6644 | |
f96198ab | 6645 | /* Wa_2006604312:icl,ehl */ |
d2432796 | 6646 | if (!needs_scalerclk_wa(old_crtc_state) && |
0e75fb8c | 6647 | needs_scalerclk_wa(new_crtc_state)) |
7181f5c5 | 6648 | icl_wa_scalerclkgating(dev_priv, pipe, true); |
8e021151 | 6649 | |
5eeb798b VS |
6650 | /* |
6651 | * Vblank time updates from the shadow to live plane control register | |
6652 | * are blocked if the memory self-refresh mode is active at that | |
6653 | * moment. So to make sure the plane gets truly disabled, disable | |
6654 | * first the self-refresh mode. The self-refresh enable bit in turn | |
6655 | * will be checked/applied by the HW only at the next frame start | |
6656 | * event which is after the vblank start event, so we need to have a | |
6657 | * wait-for-vblank between disabling the plane and the pipe. | |
6658 | */ | |
1326a92c | 6659 | if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && |
0e75fb8c | 6660 | new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) |
7181f5c5 | 6661 | intel_wait_for_vblank(dev_priv, pipe); |
92826fcd | 6662 | |
ed4a6a7c MR |
6663 | /* |
6664 | * IVB workaround: must disable low power watermarks for at least | |
6665 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
6666 | * when scaling is disabled. | |
6667 | * | |
6668 | * WaCxSRDisabledForSpriteScaling:ivb | |
6669 | */ | |
0e75fb8c VS |
6670 | if (old_crtc_state->hw.active && |
6671 | new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) | |
7181f5c5 | 6672 | intel_wait_for_vblank(dev_priv, pipe); |
ed4a6a7c MR |
6673 | |
6674 | /* | |
7181f5c5 VS |
6675 | * If we're doing a modeset we don't need to do any |
6676 | * pre-vblank watermark programming here. | |
ed4a6a7c | 6677 | */ |
7181f5c5 VS |
6678 | if (!needs_modeset(new_crtc_state)) { |
6679 | /* | |
6680 | * For platforms that support atomic watermarks, program the | |
6681 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
6682 | * will be the intermediate values that are safe for both pre- and | |
6683 | * post- vblank; when vblank happens, the 'active' values will be set | |
6684 | * to the final 'target' values and we'll do this again to get the | |
6685 | * optimal watermarks. For gen9+ platforms, the values we program here | |
6686 | * will be the final target values which will get automatically latched | |
6687 | * at vblank time; no further programming will be necessary. | |
6688 | * | |
6689 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
6690 | * we'll continue to update watermarks the old way, if flags tell | |
6691 | * us to. | |
6692 | */ | |
6693 | if (dev_priv->display.initial_watermarks) | |
6694 | dev_priv->display.initial_watermarks(state, crtc); | |
6695 | else if (new_crtc_state->update_wm_pre) | |
6696 | intel_update_watermarks(crtc); | |
6697 | } | |
ed4a6a7c MR |
6698 | |
6699 | /* | |
7181f5c5 VS |
6700 | * Gen2 reports pipe underruns whenever all planes are disabled. |
6701 | * So disable underrun reporting before all the planes get disabled. | |
ed4a6a7c | 6702 | * |
7181f5c5 VS |
6703 | * We do this after .initial_watermarks() so that we have a |
6704 | * chance of catching underruns with the intermediate watermarks | |
6705 | * vs. the old plane configuration. | |
ed4a6a7c | 6706 | */ |
7181f5c5 VS |
6707 | if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state)) |
6708 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
e5cb1afb K |
6709 | |
6710 | /* | |
6711 | * WA for platforms where async address update enable bit | |
6712 | * is double buffered and only latched at start of vblank. | |
6713 | */ | |
6714 | if (old_crtc_state->uapi.async_flip && | |
6715 | !new_crtc_state->uapi.async_flip && | |
6716 | IS_GEN_RANGE(dev_priv, 9, 10)) | |
6717 | skl_disable_async_flip_wa(state, crtc, new_crtc_state); | |
ac21b225 ML |
6718 | } |
6719 | ||
0dd14be3 VS |
6720 | static void intel_crtc_disable_planes(struct intel_atomic_state *state, |
6721 | struct intel_crtc *crtc) | |
87d4300a | 6722 | { |
0dd14be3 VS |
6723 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6724 | const struct intel_crtc_state *new_crtc_state = | |
6725 | intel_atomic_get_new_crtc_state(state, crtc); | |
6726 | unsigned int update_mask = new_crtc_state->update_planes; | |
6727 | const struct intel_plane_state *old_plane_state; | |
f59e9701 ML |
6728 | struct intel_plane *plane; |
6729 | unsigned fb_bits = 0; | |
0dd14be3 | 6730 | int i; |
87d4300a | 6731 | |
f59e9701 | 6732 | intel_crtc_dpms_overlay_disable(crtc); |
27321ae8 | 6733 | |
0dd14be3 VS |
6734 | for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { |
6735 | if (crtc->pipe != plane->pipe || | |
6736 | !(update_mask & BIT(plane->id))) | |
6737 | continue; | |
6738 | ||
c48b86f9 | 6739 | intel_disable_plane(plane, new_crtc_state); |
f98551ae | 6740 | |
f90a85e7 | 6741 | if (old_plane_state->uapi.visible) |
f59e9701 | 6742 | fb_bits |= plane->frontbuffer_bit; |
f59e9701 ML |
6743 | } |
6744 | ||
0dd14be3 | 6745 | intel_frontbuffer_flip(dev_priv, fb_bits); |
a5c4d7bc VS |
6746 | } |
6747 | ||
24a7bfe0 ID |
6748 | /* |
6749 | * intel_connector_primary_encoder - get the primary encoder for a connector | |
6750 | * @connector: connector for which to return the encoder | |
6751 | * | |
6752 | * Returns the primary encoder for a connector. There is a 1:1 mapping from | |
6753 | * all connectors to their encoder, except for DP-MST connectors which have | |
6754 | * both a virtual and a primary encoder. These DP-MST primary encoders can be | |
6755 | * pointed to by as many DP-MST connectors as there are pipes. | |
6756 | */ | |
6757 | static struct intel_encoder * | |
6758 | intel_connector_primary_encoder(struct intel_connector *connector) | |
6759 | { | |
6760 | struct intel_encoder *encoder; | |
6761 | ||
6762 | if (connector->mst_port) | |
6763 | return &dp_to_dig_port(connector->mst_port)->base; | |
6764 | ||
43a6d19c | 6765 | encoder = intel_attached_encoder(connector); |
ce04ecd9 | 6766 | drm_WARN_ON(connector->base.dev, !encoder); |
24a7bfe0 ID |
6767 | |
6768 | return encoder; | |
6769 | } | |
6770 | ||
24a7bfe0 ID |
6771 | static void intel_encoders_update_prepare(struct intel_atomic_state *state) |
6772 | { | |
24a7bfe0 | 6773 | struct drm_connector_state *new_conn_state; |
ee36c7c0 | 6774 | struct drm_connector *connector; |
24a7bfe0 ID |
6775 | int i; |
6776 | ||
ee36c7c0 JRS |
6777 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, |
6778 | i) { | |
6779 | struct intel_connector *intel_connector; | |
24a7bfe0 ID |
6780 | struct intel_encoder *encoder; |
6781 | struct intel_crtc *crtc; | |
6782 | ||
ee36c7c0 | 6783 | if (!intel_connector_needs_modeset(state, connector)) |
24a7bfe0 ID |
6784 | continue; |
6785 | ||
ee36c7c0 JRS |
6786 | intel_connector = to_intel_connector(connector); |
6787 | encoder = intel_connector_primary_encoder(intel_connector); | |
24a7bfe0 ID |
6788 | if (!encoder->update_prepare) |
6789 | continue; | |
6790 | ||
6791 | crtc = new_conn_state->crtc ? | |
6792 | to_intel_crtc(new_conn_state->crtc) : NULL; | |
6793 | encoder->update_prepare(state, encoder, crtc); | |
6794 | } | |
6795 | } | |
6796 | ||
6797 | static void intel_encoders_update_complete(struct intel_atomic_state *state) | |
6798 | { | |
24a7bfe0 | 6799 | struct drm_connector_state *new_conn_state; |
ee36c7c0 | 6800 | struct drm_connector *connector; |
24a7bfe0 ID |
6801 | int i; |
6802 | ||
ee36c7c0 JRS |
6803 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, |
6804 | i) { | |
6805 | struct intel_connector *intel_connector; | |
24a7bfe0 ID |
6806 | struct intel_encoder *encoder; |
6807 | struct intel_crtc *crtc; | |
6808 | ||
ee36c7c0 | 6809 | if (!intel_connector_needs_modeset(state, connector)) |
24a7bfe0 ID |
6810 | continue; |
6811 | ||
ee36c7c0 JRS |
6812 | intel_connector = to_intel_connector(connector); |
6813 | encoder = intel_connector_primary_encoder(intel_connector); | |
24a7bfe0 ID |
6814 | if (!encoder->update_complete) |
6815 | continue; | |
6816 | ||
6817 | crtc = new_conn_state->crtc ? | |
6818 | to_intel_crtc(new_conn_state->crtc) : NULL; | |
6819 | encoder->update_complete(state, encoder, crtc); | |
6820 | } | |
6821 | } | |
6822 | ||
021ba100 VS |
6823 | static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, |
6824 | struct intel_crtc *crtc) | |
fb1c98b1 | 6825 | { |
021ba100 VS |
6826 | const struct intel_crtc_state *crtc_state = |
6827 | intel_atomic_get_new_crtc_state(state, crtc); | |
6828 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6829 | struct drm_connector *conn; |
6830 | int i; | |
6831 | ||
855e0d68 | 6832 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6833 | struct intel_encoder *encoder = |
6834 | to_intel_encoder(conn_state->best_encoder); | |
6835 | ||
855e0d68 | 6836 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6837 | continue; |
6838 | ||
6839 | if (encoder->pre_pll_enable) | |
ede9771d VS |
6840 | encoder->pre_pll_enable(state, encoder, |
6841 | crtc_state, conn_state); | |
fb1c98b1 ML |
6842 | } |
6843 | } | |
6844 | ||
021ba100 VS |
6845 | static void intel_encoders_pre_enable(struct intel_atomic_state *state, |
6846 | struct intel_crtc *crtc) | |
fb1c98b1 | 6847 | { |
021ba100 VS |
6848 | const struct intel_crtc_state *crtc_state = |
6849 | intel_atomic_get_new_crtc_state(state, crtc); | |
6850 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6851 | struct drm_connector *conn; |
6852 | int i; | |
6853 | ||
855e0d68 | 6854 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6855 | struct intel_encoder *encoder = |
6856 | to_intel_encoder(conn_state->best_encoder); | |
6857 | ||
855e0d68 | 6858 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6859 | continue; |
6860 | ||
6861 | if (encoder->pre_enable) | |
ede9771d VS |
6862 | encoder->pre_enable(state, encoder, |
6863 | crtc_state, conn_state); | |
fb1c98b1 ML |
6864 | } |
6865 | } | |
6866 | ||
021ba100 VS |
6867 | static void intel_encoders_enable(struct intel_atomic_state *state, |
6868 | struct intel_crtc *crtc) | |
fb1c98b1 | 6869 | { |
021ba100 VS |
6870 | const struct intel_crtc_state *crtc_state = |
6871 | intel_atomic_get_new_crtc_state(state, crtc); | |
6872 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6873 | struct drm_connector *conn; |
6874 | int i; | |
6875 | ||
855e0d68 | 6876 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6877 | struct intel_encoder *encoder = |
6878 | to_intel_encoder(conn_state->best_encoder); | |
6879 | ||
855e0d68 | 6880 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6881 | continue; |
6882 | ||
c84c6fe3 | 6883 | if (encoder->enable) |
ede9771d VS |
6884 | encoder->enable(state, encoder, |
6885 | crtc_state, conn_state); | |
fb1c98b1 ML |
6886 | intel_opregion_notify_encoder(encoder, true); |
6887 | } | |
6888 | } | |
6889 | ||
021ba100 VS |
6890 | static void intel_encoders_disable(struct intel_atomic_state *state, |
6891 | struct intel_crtc *crtc) | |
fb1c98b1 | 6892 | { |
021ba100 VS |
6893 | const struct intel_crtc_state *old_crtc_state = |
6894 | intel_atomic_get_old_crtc_state(state, crtc); | |
6895 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6896 | struct drm_connector *conn; |
6897 | int i; | |
6898 | ||
855e0d68 | 6899 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6900 | struct intel_encoder *encoder = |
6901 | to_intel_encoder(old_conn_state->best_encoder); | |
6902 | ||
855e0d68 | 6903 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6904 | continue; |
6905 | ||
6906 | intel_opregion_notify_encoder(encoder, false); | |
c84c6fe3 | 6907 | if (encoder->disable) |
ede9771d VS |
6908 | encoder->disable(state, encoder, |
6909 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6910 | } |
6911 | } | |
6912 | ||
021ba100 VS |
6913 | static void intel_encoders_post_disable(struct intel_atomic_state *state, |
6914 | struct intel_crtc *crtc) | |
fb1c98b1 | 6915 | { |
021ba100 VS |
6916 | const struct intel_crtc_state *old_crtc_state = |
6917 | intel_atomic_get_old_crtc_state(state, crtc); | |
6918 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6919 | struct drm_connector *conn; |
6920 | int i; | |
6921 | ||
855e0d68 | 6922 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6923 | struct intel_encoder *encoder = |
6924 | to_intel_encoder(old_conn_state->best_encoder); | |
6925 | ||
855e0d68 | 6926 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6927 | continue; |
6928 | ||
6929 | if (encoder->post_disable) | |
ede9771d VS |
6930 | encoder->post_disable(state, encoder, |
6931 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6932 | } |
6933 | } | |
6934 | ||
021ba100 VS |
6935 | static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, |
6936 | struct intel_crtc *crtc) | |
fb1c98b1 | 6937 | { |
021ba100 VS |
6938 | const struct intel_crtc_state *old_crtc_state = |
6939 | intel_atomic_get_old_crtc_state(state, crtc); | |
6940 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6941 | struct drm_connector *conn; |
6942 | int i; | |
6943 | ||
855e0d68 | 6944 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6945 | struct intel_encoder *encoder = |
6946 | to_intel_encoder(old_conn_state->best_encoder); | |
6947 | ||
855e0d68 | 6948 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6949 | continue; |
6950 | ||
6951 | if (encoder->post_pll_disable) | |
ede9771d VS |
6952 | encoder->post_pll_disable(state, encoder, |
6953 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6954 | } |
6955 | } | |
6956 | ||
021ba100 VS |
6957 | static void intel_encoders_update_pipe(struct intel_atomic_state *state, |
6958 | struct intel_crtc *crtc) | |
608ed4ab | 6959 | { |
021ba100 VS |
6960 | const struct intel_crtc_state *crtc_state = |
6961 | intel_atomic_get_new_crtc_state(state, crtc); | |
6962 | const struct drm_connector_state *conn_state; | |
608ed4ab HG |
6963 | struct drm_connector *conn; |
6964 | int i; | |
6965 | ||
855e0d68 | 6966 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
608ed4ab HG |
6967 | struct intel_encoder *encoder = |
6968 | to_intel_encoder(conn_state->best_encoder); | |
6969 | ||
855e0d68 | 6970 | if (conn_state->crtc != &crtc->base) |
608ed4ab HG |
6971 | continue; |
6972 | ||
6973 | if (encoder->update_pipe) | |
ede9771d VS |
6974 | encoder->update_pipe(state, encoder, |
6975 | crtc_state, conn_state); | |
608ed4ab HG |
6976 | } |
6977 | } | |
6978 | ||
73a116be VS |
6979 | static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) |
6980 | { | |
2225f3c6 | 6981 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
73a116be VS |
6982 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
6983 | ||
6984 | plane->disable_plane(plane, crtc_state); | |
6985 | } | |
6986 | ||
9eae5e27 LDM |
6987 | static void ilk_crtc_enable(struct intel_atomic_state *state, |
6988 | struct intel_crtc *crtc) | |
f67a559d | 6989 | { |
7451a074 VS |
6990 | const struct intel_crtc_state *new_crtc_state = |
6991 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
6992 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6993 | enum pipe pipe = crtc->pipe; | |
f67a559d | 6994 | |
e57291c2 | 6995 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
f67a559d JB |
6996 | return; |
6997 | ||
b2c0593a VS |
6998 | /* |
6999 | * Sometimes spurious CPU pipe underruns happen during FDI | |
7000 | * training, at least with VGA+HDMI cloning. Suppress them. | |
7001 | * | |
7002 | * On ILK we get an occasional spurious CPU pipe underruns | |
7003 | * between eDP port A enable and vdd enable. Also PCH port | |
7004 | * enable seems to result in the occasional CPU pipe underrun. | |
7005 | * | |
7006 | * Spurious PCH underruns also occur during PCH enabling. | |
7007 | */ | |
2b5b6312 VS |
7008 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
7009 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca | 7010 | |
502d8714 VS |
7011 | if (new_crtc_state->has_pch_encoder) |
7012 | intel_prepare_shared_dpll(new_crtc_state); | |
b14b1055 | 7013 | |
502d8714 VS |
7014 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
7015 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
29407aab | 7016 | |
e7fc3f90 | 7017 | intel_set_transcoder_timings(new_crtc_state); |
502d8714 | 7018 | intel_set_pipe_src_size(new_crtc_state); |
29407aab | 7019 | |
502d8714 VS |
7020 | if (new_crtc_state->has_pch_encoder) |
7021 | intel_cpu_transcoder_set_m_n(new_crtc_state, | |
7022 | &new_crtc_state->fdi_m_n, NULL); | |
29407aab | 7023 | |
9eae5e27 | 7024 | ilk_set_pipeconf(new_crtc_state); |
29407aab | 7025 | |
e44c84a1 | 7026 | crtc->active = true; |
8664281b | 7027 | |
e44c84a1 | 7028 | intel_encoders_pre_enable(state, crtc); |
f67a559d | 7029 | |
502d8714 | 7030 | if (new_crtc_state->has_pch_encoder) { |
fff367c7 DV |
7031 | /* Note: FDI PLL enabling _must_ be done before we enable the |
7032 | * cpu pipes, hence this is separate from all the other fdi/pch | |
7033 | * enabling. */ | |
9eae5e27 | 7034 | ilk_fdi_pll_enable(new_crtc_state); |
46b6f814 DV |
7035 | } else { |
7036 | assert_fdi_tx_disabled(dev_priv, pipe); | |
7037 | assert_fdi_rx_disabled(dev_priv, pipe); | |
7038 | } | |
f67a559d | 7039 | |
9eae5e27 | 7040 | ilk_pfit_enable(new_crtc_state); |
f67a559d | 7041 | |
9c54c0dd JB |
7042 | /* |
7043 | * On ILK+ LUT must be loaded before the pipe is running but with | |
7044 | * clocks enabled | |
7045 | */ | |
502d8714 VS |
7046 | intel_color_load_luts(new_crtc_state); |
7047 | intel_color_commit(new_crtc_state); | |
73a116be | 7048 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 7049 | intel_disable_primary_plane(new_crtc_state); |
9c54c0dd | 7050 | |
7a8fdb1f | 7051 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 7052 | dev_priv->display.initial_watermarks(state, crtc); |
502d8714 | 7053 | intel_enable_pipe(new_crtc_state); |
f67a559d | 7054 | |
502d8714 | 7055 | if (new_crtc_state->has_pch_encoder) |
9eae5e27 | 7056 | ilk_pch_enable(state, new_crtc_state); |
c98e9dcf | 7057 | |
502d8714 | 7058 | intel_crtc_vblank_on(new_crtc_state); |
f9b61ff6 | 7059 | |
e44c84a1 | 7060 | intel_encoders_enable(state, crtc); |
61b77ddd | 7061 | |
6e266956 | 7062 | if (HAS_PCH_CPT(dev_priv)) |
c684fb44 | 7063 | cpt_verify_modeset(dev_priv, pipe); |
37ca8d4c | 7064 | |
ea80a661 VS |
7065 | /* |
7066 | * Must wait for vblank to avoid spurious PCH FIFO underruns. | |
7067 | * And a second vblank wait is needed at least on ILK with | |
7068 | * some interlaced HDMI modes. Let's do the double wait always | |
7069 | * in case there are more corner cases we don't know about. | |
7070 | */ | |
502d8714 | 7071 | if (new_crtc_state->has_pch_encoder) { |
ea80a661 | 7072 | intel_wait_for_vblank(dev_priv, pipe); |
0f0f74bc | 7073 | intel_wait_for_vblank(dev_priv, pipe); |
ea80a661 | 7074 | } |
b2c0593a | 7075 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 7076 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
7077 | } |
7078 | ||
42db64ef PZ |
7079 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
7080 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
7081 | { | |
50a0bc90 | 7082 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
7083 | } |
7084 | ||
ed69cd40 ID |
7085 | static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, |
7086 | enum pipe pipe, bool apply) | |
7087 | { | |
dc008bf0 | 7088 | u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); |
ed69cd40 ID |
7089 | u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; |
7090 | ||
7091 | if (apply) | |
7092 | val |= mask; | |
7093 | else | |
7094 | val &= ~mask; | |
7095 | ||
dc008bf0 | 7096 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); |
ed69cd40 ID |
7097 | } |
7098 | ||
c3cc39c5 MK |
7099 | static void icl_pipe_mbus_enable(struct intel_crtc *crtc) |
7100 | { | |
7101 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7102 | enum pipe pipe = crtc->pipe; | |
ba3f4d0a | 7103 | u32 val; |
c3cc39c5 | 7104 | |
443d5e39 | 7105 | val = MBUS_DBOX_A_CREDIT(2); |
30fcc338 RV |
7106 | |
7107 | if (INTEL_GEN(dev_priv) >= 12) { | |
7108 | val |= MBUS_DBOX_BW_CREDIT(2); | |
7109 | val |= MBUS_DBOX_B_CREDIT(12); | |
7110 | } else { | |
7111 | val |= MBUS_DBOX_BW_CREDIT(1); | |
7112 | val |= MBUS_DBOX_B_CREDIT(8); | |
7113 | } | |
c3cc39c5 | 7114 | |
dc008bf0 | 7115 | intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); |
c3cc39c5 MK |
7116 | } |
7117 | ||
6dcde047 VS |
7118 | static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) |
7119 | { | |
7120 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
7121 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7122 | ||
7123 | intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), | |
7124 | HSW_LINETIME(crtc_state->linetime) | | |
7125 | HSW_IPS_LINETIME(crtc_state->ips_linetime)); | |
7126 | } | |
7127 | ||
cc7a4cff VS |
7128 | static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) |
7129 | { | |
7130 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
7131 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7132 | i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); | |
7133 | u32 val; | |
7134 | ||
dc008bf0 | 7135 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
7136 | val &= ~HSW_FRAME_START_DELAY_MASK; |
7137 | val |= HSW_FRAME_START_DELAY(0); | |
dc008bf0 | 7138 | intel_de_write(dev_priv, reg, val); |
cc7a4cff VS |
7139 | } |
7140 | ||
1e98f88c LDM |
7141 | static void hsw_crtc_enable(struct intel_atomic_state *state, |
7142 | struct intel_crtc *crtc) | |
4f771f10 | 7143 | { |
7451a074 VS |
7144 | const struct intel_crtc_state *new_crtc_state = |
7145 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7146 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7147 | enum pipe pipe = crtc->pipe, hsw_workaround_pipe; | |
502d8714 | 7148 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; |
ed69cd40 | 7149 | bool psl_clkgate_wa; |
4f771f10 | 7150 | |
e57291c2 | 7151 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
4f771f10 PZ |
7152 | return; |
7153 | ||
e44c84a1 | 7154 | intel_encoders_pre_pll_enable(state, crtc); |
95a7a2ae | 7155 | |
502d8714 VS |
7156 | if (new_crtc_state->shared_dpll) |
7157 | intel_enable_shared_dpll(new_crtc_state); | |
df8ad70c | 7158 | |
e44c84a1 | 7159 | intel_encoders_pre_enable(state, crtc); |
c8af5274 | 7160 | |
d7edc4e5 | 7161 | if (!transcoder_is_dsi(cpu_transcoder)) |
e7fc3f90 | 7162 | intel_set_transcoder_timings(new_crtc_state); |
4d1de975 | 7163 | |
502d8714 | 7164 | intel_set_pipe_src_size(new_crtc_state); |
229fca97 | 7165 | |
4d1de975 | 7166 | if (cpu_transcoder != TRANSCODER_EDP && |
502d8714 | 7167 | !transcoder_is_dsi(cpu_transcoder)) |
dc008bf0 JN |
7168 | intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), |
7169 | new_crtc_state->pixel_multiplier - 1); | |
ebb69c95 | 7170 | |
502d8714 VS |
7171 | if (new_crtc_state->has_pch_encoder) |
7172 | intel_cpu_transcoder_set_m_n(new_crtc_state, | |
7173 | &new_crtc_state->fdi_m_n, NULL); | |
229fca97 | 7174 | |
cc7a4cff | 7175 | if (!transcoder_is_dsi(cpu_transcoder)) { |
502d8714 | 7176 | hsw_set_frame_start_delay(new_crtc_state); |
1e98f88c | 7177 | hsw_set_pipeconf(new_crtc_state); |
cc7a4cff | 7178 | } |
4d1de975 | 7179 | |
9b11215e | 7180 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
502d8714 | 7181 | bdw_set_pipemisc(new_crtc_state); |
229fca97 | 7182 | |
e44c84a1 | 7183 | crtc->active = true; |
8664281b | 7184 | |
ed69cd40 ID |
7185 | /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ |
7186 | psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && | |
502d8714 | 7187 | new_crtc_state->pch_pfit.enabled; |
ed69cd40 ID |
7188 | if (psl_clkgate_wa) |
7189 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); | |
7190 | ||
6315b5d3 | 7191 | if (INTEL_GEN(dev_priv) >= 9) |
f6df4d46 | 7192 | skl_pfit_enable(new_crtc_state); |
ff6d9f55 | 7193 | else |
9eae5e27 | 7194 | ilk_pfit_enable(new_crtc_state); |
4f771f10 PZ |
7195 | |
7196 | /* | |
7197 | * On ILK+ LUT must be loaded before the pipe is running but with | |
7198 | * clocks enabled | |
7199 | */ | |
502d8714 VS |
7200 | intel_color_load_luts(new_crtc_state); |
7201 | intel_color_commit(new_crtc_state); | |
73a116be VS |
7202 | /* update DSPCNTR to configure gamma/csc for pipe bottom color */ |
7203 | if (INTEL_GEN(dev_priv) < 9) | |
502d8714 | 7204 | intel_disable_primary_plane(new_crtc_state); |
4f771f10 | 7205 | |
6dcde047 VS |
7206 | hsw_set_linetime_wm(new_crtc_state); |
7207 | ||
d1622119 | 7208 | if (INTEL_GEN(dev_priv) >= 11) |
e44c84a1 | 7209 | icl_set_pipe_chicken(crtc); |
e16a3750 | 7210 | |
7a8fdb1f | 7211 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 7212 | dev_priv->display.initial_watermarks(state, crtc); |
4d1de975 | 7213 | |
c3cc39c5 | 7214 | if (INTEL_GEN(dev_priv) >= 11) |
e44c84a1 | 7215 | icl_pipe_mbus_enable(crtc); |
c3cc39c5 | 7216 | |
e44c84a1 | 7217 | intel_encoders_enable(state, crtc); |
4f771f10 | 7218 | |
ed69cd40 ID |
7219 | if (psl_clkgate_wa) { |
7220 | intel_wait_for_vblank(dev_priv, pipe); | |
7221 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); | |
7222 | } | |
7223 | ||
e4916946 PZ |
7224 | /* If we change the relative order between pipe/planes enabling, we need |
7225 | * to change the workaround. */ | |
502d8714 | 7226 | hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; |
772c2a51 | 7227 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
7228 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
7229 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 7230 | } |
4f771f10 PZ |
7231 | } |
7232 | ||
9eae5e27 | 7233 | void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
3f8dce3a | 7234 | { |
2225f3c6 | 7235 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
b2562712 ML |
7236 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7237 | enum pipe pipe = crtc->pipe; | |
3f8dce3a DV |
7238 | |
7239 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
7240 | * it's in use. The hw state code will make sure we get this right. */ | |
eac9c585 VS |
7241 | if (!old_crtc_state->pch_pfit.enabled) |
7242 | return; | |
7243 | ||
7244 | intel_de_write(dev_priv, PF_CTL(pipe), 0); | |
7245 | intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); | |
7246 | intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); | |
3f8dce3a DV |
7247 | } |
7248 | ||
9eae5e27 LDM |
7249 | static void ilk_crtc_disable(struct intel_atomic_state *state, |
7250 | struct intel_crtc *crtc) | |
6be4a607 | 7251 | { |
7451a074 VS |
7252 | const struct intel_crtc_state *old_crtc_state = |
7253 | intel_atomic_get_old_crtc_state(state, crtc); | |
e44c84a1 VS |
7254 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7255 | enum pipe pipe = crtc->pipe; | |
b52eb4dc | 7256 | |
b2c0593a VS |
7257 | /* |
7258 | * Sometimes spurious CPU pipe underruns happen when the | |
7259 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
7260 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
7261 | */ | |
2b5b6312 VS |
7262 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
7263 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 7264 | |
e44c84a1 | 7265 | intel_encoders_disable(state, crtc); |
ea9d758d | 7266 | |
f5271ee5 | 7267 | intel_crtc_vblank_off(old_crtc_state); |
f9b61ff6 | 7268 | |
4972f70a | 7269 | intel_disable_pipe(old_crtc_state); |
32f9d658 | 7270 | |
9eae5e27 | 7271 | ilk_pfit_disable(old_crtc_state); |
2c07245f | 7272 | |
6f405638 | 7273 | if (old_crtc_state->has_pch_encoder) |
9eae5e27 | 7274 | ilk_fdi_disable(crtc); |
5a74f70a | 7275 | |
e44c84a1 | 7276 | intel_encoders_post_disable(state, crtc); |
2c07245f | 7277 | |
6f405638 | 7278 | if (old_crtc_state->has_pch_encoder) { |
9eae5e27 | 7279 | ilk_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 7280 | |
6e266956 | 7281 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
7282 | i915_reg_t reg; |
7283 | u32 temp; | |
7284 | ||
d925c59a DV |
7285 | /* disable TRANS_DP_CTL */ |
7286 | reg = TRANS_DP_CTL(pipe); | |
dc008bf0 | 7287 | temp = intel_de_read(dev_priv, reg); |
d925c59a DV |
7288 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
7289 | TRANS_DP_PORT_SEL_MASK); | |
7290 | temp |= TRANS_DP_PORT_SEL_NONE; | |
dc008bf0 | 7291 | intel_de_write(dev_priv, reg, temp); |
d925c59a DV |
7292 | |
7293 | /* disable DPLL_SEL */ | |
dc008bf0 | 7294 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
11887397 | 7295 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
dc008bf0 | 7296 | intel_de_write(dev_priv, PCH_DPLL_SEL, temp); |
9db4a9c7 | 7297 | } |
e3421a18 | 7298 | |
9eae5e27 | 7299 | ilk_fdi_pll_disable(crtc); |
d925c59a | 7300 | } |
81b088ca | 7301 | |
b2c0593a | 7302 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 7303 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 7304 | } |
1b3c7a47 | 7305 | |
1e98f88c LDM |
7306 | static void hsw_crtc_disable(struct intel_atomic_state *state, |
7307 | struct intel_crtc *crtc) | |
ee7b9f93 | 7308 | { |
773b4b54 VS |
7309 | /* |
7310 | * FIXME collapse everything to one hook. | |
7311 | * Need care with mst->ddi interactions. | |
7312 | */ | |
e44c84a1 | 7313 | intel_encoders_disable(state, crtc); |
e44c84a1 | 7314 | intel_encoders_post_disable(state, crtc); |
4f771f10 PZ |
7315 | } |
7316 | ||
b2562712 | 7317 | static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) |
2dd24552 | 7318 | { |
2225f3c6 | 7319 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 7320 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2dd24552 | 7321 | |
b2562712 | 7322 | if (!crtc_state->gmch_pfit.control) |
2dd24552 JB |
7323 | return; |
7324 | ||
2dd24552 | 7325 | /* |
c0b03411 DV |
7326 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
7327 | * according to register description and PRM. | |
2dd24552 | 7328 | */ |
e57291c2 PB |
7329 | drm_WARN_ON(&dev_priv->drm, |
7330 | intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); | |
b104e8b2 | 7331 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
2dd24552 | 7332 | |
dc008bf0 JN |
7333 | intel_de_write(dev_priv, PFIT_PGM_RATIOS, |
7334 | crtc_state->gmch_pfit.pgm_ratios); | |
7335 | intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); | |
5a80c45c DV |
7336 | |
7337 | /* Border color in case we don't scale up to the full screen. Black by | |
7338 | * default, change to something else for debugging. */ | |
dc008bf0 | 7339 | intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); |
2dd24552 JB |
7340 | } |
7341 | ||
358633e7 MR |
7342 | bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) |
7343 | { | |
7344 | if (phy == PHY_NONE) | |
7345 | return false; | |
aefaa1f4 MR |
7346 | else if (IS_ROCKETLAKE(dev_priv)) |
7347 | return phy <= PHY_D; | |
24ea098b | 7348 | else if (IS_JSL_EHL(dev_priv)) |
358633e7 | 7349 | return phy <= PHY_C; |
aefaa1f4 | 7350 | else if (INTEL_GEN(dev_priv) >= 11) |
358633e7 | 7351 | return phy <= PHY_B; |
aefaa1f4 MR |
7352 | else |
7353 | return false; | |
358633e7 MR |
7354 | } |
7355 | ||
358633e7 MR |
7356 | bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) |
7357 | { | |
aefaa1f4 MR |
7358 | if (IS_ROCKETLAKE(dev_priv)) |
7359 | return false; | |
7360 | else if (INTEL_GEN(dev_priv) >= 12) | |
5c719708 | 7361 | return phy >= PHY_D && phy <= PHY_I; |
24ea098b | 7362 | else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv)) |
358633e7 | 7363 | return phy >= PHY_C && phy <= PHY_F; |
aefaa1f4 MR |
7364 | else |
7365 | return false; | |
358633e7 MR |
7366 | } |
7367 | ||
7368 | enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) | |
7369 | { | |
1d8ca002 VS |
7370 | if (IS_ROCKETLAKE(i915) && port >= PORT_TC1) |
7371 | return PHY_C + port - PORT_TC1; | |
24ea098b | 7372 | else if (IS_JSL_EHL(i915) && port == PORT_D) |
358633e7 MR |
7373 | return PHY_A; |
7374 | ||
1d8ca002 | 7375 | return PHY_A + port - PORT_A; |
358633e7 MR |
7376 | } |
7377 | ||
ac213c1b PZ |
7378 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) |
7379 | { | |
358633e7 | 7380 | if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) |
320c670c | 7381 | return TC_PORT_NONE; |
ac213c1b | 7382 | |
6c8337da | 7383 | if (INTEL_GEN(dev_priv) >= 12) |
1d8ca002 VS |
7384 | return TC_PORT_1 + port - PORT_TC1; |
7385 | else | |
7386 | return TC_PORT_1 + port - PORT_C; | |
ac213c1b PZ |
7387 | } |
7388 | ||
79f255a0 | 7389 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
7390 | { |
7391 | switch (port) { | |
7392 | case PORT_A: | |
6331a704 | 7393 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 7394 | case PORT_B: |
6331a704 | 7395 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 7396 | case PORT_C: |
6331a704 | 7397 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 7398 | case PORT_D: |
6331a704 | 7399 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 7400 | case PORT_E: |
6331a704 | 7401 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
9787e835 RV |
7402 | case PORT_F: |
7403 | return POWER_DOMAIN_PORT_DDI_F_LANES; | |
eb8de23c KA |
7404 | case PORT_G: |
7405 | return POWER_DOMAIN_PORT_DDI_G_LANES; | |
07c9b088 VS |
7406 | case PORT_H: |
7407 | return POWER_DOMAIN_PORT_DDI_H_LANES; | |
7408 | case PORT_I: | |
7409 | return POWER_DOMAIN_PORT_DDI_I_LANES; | |
d05410f9 | 7410 | default: |
b9fec167 | 7411 | MISSING_CASE(port); |
d05410f9 DA |
7412 | return POWER_DOMAIN_PORT_OTHER; |
7413 | } | |
7414 | } | |
7415 | ||
337837ac ID |
7416 | enum intel_display_power_domain |
7417 | intel_aux_power_domain(struct intel_digital_port *dig_port) | |
7418 | { | |
dd7239c5 | 7419 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
d8fe2ab6 | 7420 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
dd7239c5 | 7421 | |
d8fe2ab6 | 7422 | if (intel_phy_is_tc(dev_priv, phy) && |
dd7239c5 ID |
7423 | dig_port->tc_mode == TC_PORT_TBT_ALT) { |
7424 | switch (dig_port->aux_ch) { | |
7425 | case AUX_CH_C: | |
8a84bacb | 7426 | return POWER_DOMAIN_AUX_C_TBT; |
dd7239c5 | 7427 | case AUX_CH_D: |
8a84bacb | 7428 | return POWER_DOMAIN_AUX_D_TBT; |
dd7239c5 | 7429 | case AUX_CH_E: |
8a84bacb | 7430 | return POWER_DOMAIN_AUX_E_TBT; |
dd7239c5 | 7431 | case AUX_CH_F: |
8a84bacb | 7432 | return POWER_DOMAIN_AUX_F_TBT; |
eb8de23c KA |
7433 | case AUX_CH_G: |
7434 | return POWER_DOMAIN_AUX_G_TBT; | |
244f2e9c VS |
7435 | case AUX_CH_H: |
7436 | return POWER_DOMAIN_AUX_H_TBT; | |
7437 | case AUX_CH_I: | |
7438 | return POWER_DOMAIN_AUX_I_TBT; | |
dd7239c5 ID |
7439 | default: |
7440 | MISSING_CASE(dig_port->aux_ch); | |
8a84bacb | 7441 | return POWER_DOMAIN_AUX_C_TBT; |
dd7239c5 ID |
7442 | } |
7443 | } | |
7444 | ||
dba6b0b4 JRS |
7445 | return intel_legacy_aux_to_power_domain(dig_port->aux_ch); |
7446 | } | |
7447 | ||
7448 | /* | |
7449 | * Converts aux_ch to power_domain without caring about TBT ports for that use | |
7450 | * intel_aux_power_domain() | |
7451 | */ | |
7452 | enum intel_display_power_domain | |
7453 | intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) | |
7454 | { | |
7455 | switch (aux_ch) { | |
337837ac ID |
7456 | case AUX_CH_A: |
7457 | return POWER_DOMAIN_AUX_A; | |
7458 | case AUX_CH_B: | |
7459 | return POWER_DOMAIN_AUX_B; | |
7460 | case AUX_CH_C: | |
7461 | return POWER_DOMAIN_AUX_C; | |
7462 | case AUX_CH_D: | |
7463 | return POWER_DOMAIN_AUX_D; | |
7464 | case AUX_CH_E: | |
7465 | return POWER_DOMAIN_AUX_E; | |
7466 | case AUX_CH_F: | |
7467 | return POWER_DOMAIN_AUX_F; | |
eb8de23c KA |
7468 | case AUX_CH_G: |
7469 | return POWER_DOMAIN_AUX_G; | |
244f2e9c VS |
7470 | case AUX_CH_H: |
7471 | return POWER_DOMAIN_AUX_H; | |
7472 | case AUX_CH_I: | |
7473 | return POWER_DOMAIN_AUX_I; | |
337837ac | 7474 | default: |
dba6b0b4 | 7475 | MISSING_CASE(aux_ch); |
337837ac ID |
7476 | return POWER_DOMAIN_AUX_A; |
7477 | } | |
7478 | } | |
7479 | ||
afe0c21b | 7480 | static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
77d22dca | 7481 | { |
2225f3c6 | 7482 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
afe0c21b | 7483 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
74bff5f9 | 7484 | struct drm_encoder *encoder; |
855e0d68 | 7485 | enum pipe pipe = crtc->pipe; |
d8fc70b7 | 7486 | u64 mask; |
74bff5f9 | 7487 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 7488 | |
1326a92c | 7489 | if (!crtc_state->hw.active) |
292b990e ML |
7490 | return 0; |
7491 | ||
17bd6e66 ID |
7492 | mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); |
7493 | mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
7494 | if (crtc_state->pch_pfit.enabled || |
7495 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 7496 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 7497 | |
afe0c21b | 7498 | drm_for_each_encoder_mask(encoder, &dev_priv->drm, |
2225f3c6 | 7499 | crtc_state->uapi.encoder_mask) { |
74bff5f9 ML |
7500 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
7501 | ||
79f255a0 | 7502 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 7503 | } |
319be8ae | 7504 | |
37255d8d | 7505 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
17bd6e66 | 7506 | mask |= BIT_ULL(POWER_DOMAIN_AUDIO); |
37255d8d | 7507 | |
15e7ec29 | 7508 | if (crtc_state->shared_dpll) |
08d8e170 | 7509 | mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); |
15e7ec29 | 7510 | |
77d22dca ID |
7511 | return mask; |
7512 | } | |
7513 | ||
d2d15016 | 7514 | static u64 |
afe0c21b | 7515 | modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
77d22dca | 7516 | { |
2225f3c6 | 7517 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
855e0d68 | 7518 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
292b990e | 7519 | enum intel_display_power_domain domain; |
d8fc70b7 | 7520 | u64 domains, new_domains, old_domains; |
77d22dca | 7521 | |
855e0d68 ML |
7522 | old_domains = crtc->enabled_power_domains; |
7523 | crtc->enabled_power_domains = new_domains = | |
afe0c21b | 7524 | get_crtc_power_domains(crtc_state); |
77d22dca | 7525 | |
5a21b665 | 7526 | domains = new_domains & ~old_domains; |
292b990e ML |
7527 | |
7528 | for_each_power_domain(domain, domains) | |
7529 | intel_display_power_get(dev_priv, domain); | |
7530 | ||
5a21b665 | 7531 | return old_domains & ~new_domains; |
292b990e ML |
7532 | } |
7533 | ||
7534 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 7535 | u64 domains) |
292b990e ML |
7536 | { |
7537 | enum intel_display_power_domain domain; | |
7538 | ||
7539 | for_each_power_domain(domain, domains) | |
0e6e0be4 | 7540 | intel_display_power_put_unchecked(dev_priv, domain); |
292b990e | 7541 | } |
77d22dca | 7542 | |
7451a074 VS |
7543 | static void valleyview_crtc_enable(struct intel_atomic_state *state, |
7544 | struct intel_crtc *crtc) | |
adafdc6f | 7545 | { |
7451a074 VS |
7546 | const struct intel_crtc_state *new_crtc_state = |
7547 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7548 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7549 | enum pipe pipe = crtc->pipe; | |
adafdc6f | 7550 | |
e57291c2 | 7551 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
7ff89ca2 | 7552 | return; |
adafdc6f | 7553 | |
502d8714 VS |
7554 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
7555 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
b2045352 | 7556 | |
e7fc3f90 | 7557 | intel_set_transcoder_timings(new_crtc_state); |
502d8714 | 7558 | intel_set_pipe_src_size(new_crtc_state); |
b2045352 | 7559 | |
7ff89ca2 | 7560 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
dc008bf0 JN |
7561 | intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
7562 | intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
7563 | } |
7564 | ||
502d8714 | 7565 | i9xx_set_pipeconf(new_crtc_state); |
560a7ae4 | 7566 | |
e44c84a1 | 7567 | crtc->active = true; |
92891e45 | 7568 | |
7ff89ca2 | 7569 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 7570 | |
e44c84a1 | 7571 | intel_encoders_pre_pll_enable(state, crtc); |
5f199dfa | 7572 | |
7ff89ca2 | 7573 | if (IS_CHERRYVIEW(dev_priv)) { |
502d8714 VS |
7574 | chv_prepare_pll(crtc, new_crtc_state); |
7575 | chv_enable_pll(crtc, new_crtc_state); | |
7ff89ca2 | 7576 | } else { |
502d8714 VS |
7577 | vlv_prepare_pll(crtc, new_crtc_state); |
7578 | vlv_enable_pll(crtc, new_crtc_state); | |
5f199dfa VS |
7579 | } |
7580 | ||
e44c84a1 | 7581 | intel_encoders_pre_enable(state, crtc); |
5f199dfa | 7582 | |
502d8714 | 7583 | i9xx_pfit_enable(new_crtc_state); |
89b3c3c7 | 7584 | |
502d8714 VS |
7585 | intel_color_load_luts(new_crtc_state); |
7586 | intel_color_commit(new_crtc_state); | |
73a116be | 7587 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 7588 | intel_disable_primary_plane(new_crtc_state); |
89b3c3c7 | 7589 | |
e44c84a1 | 7590 | dev_priv->display.initial_watermarks(state, crtc); |
502d8714 | 7591 | intel_enable_pipe(new_crtc_state); |
7ff89ca2 | 7592 | |
502d8714 | 7593 | intel_crtc_vblank_on(new_crtc_state); |
89b3c3c7 | 7594 | |
e44c84a1 | 7595 | intel_encoders_enable(state, crtc); |
89b3c3c7 ACO |
7596 | } |
7597 | ||
b2354c78 | 7598 | static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) |
2b73001e | 7599 | { |
2225f3c6 | 7600 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2354c78 | 7601 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
83d7c81f | 7602 | |
dc008bf0 JN |
7603 | intel_de_write(dev_priv, FP0(crtc->pipe), |
7604 | crtc_state->dpll_hw_state.fp0); | |
7605 | intel_de_write(dev_priv, FP1(crtc->pipe), | |
7606 | crtc_state->dpll_hw_state.fp1); | |
2b73001e VS |
7607 | } |
7608 | ||
7451a074 VS |
7609 | static void i9xx_crtc_enable(struct intel_atomic_state *state, |
7610 | struct intel_crtc *crtc) | |
2b73001e | 7611 | { |
7451a074 VS |
7612 | const struct intel_crtc_state *new_crtc_state = |
7613 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7614 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7615 | enum pipe pipe = crtc->pipe; | |
2b73001e | 7616 | |
e57291c2 | 7617 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
7ff89ca2 | 7618 | return; |
2b73001e | 7619 | |
502d8714 | 7620 | i9xx_set_pll_dividers(new_crtc_state); |
2b73001e | 7621 | |
502d8714 VS |
7622 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
7623 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
83d7c81f | 7624 | |
e7fc3f90 | 7625 | intel_set_transcoder_timings(new_crtc_state); |
502d8714 | 7626 | intel_set_pipe_src_size(new_crtc_state); |
2b73001e | 7627 | |
502d8714 | 7628 | i9xx_set_pipeconf(new_crtc_state); |
f8437dd1 | 7629 | |
e44c84a1 | 7630 | crtc->active = true; |
5f199dfa | 7631 | |
cf819eff | 7632 | if (!IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7633 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 7634 | |
e44c84a1 | 7635 | intel_encoders_pre_enable(state, crtc); |
f8437dd1 | 7636 | |
502d8714 | 7637 | i9xx_enable_pll(crtc, new_crtc_state); |
f8437dd1 | 7638 | |
502d8714 | 7639 | i9xx_pfit_enable(new_crtc_state); |
f8437dd1 | 7640 | |
502d8714 VS |
7641 | intel_color_load_luts(new_crtc_state); |
7642 | intel_color_commit(new_crtc_state); | |
73a116be | 7643 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 7644 | intel_disable_primary_plane(new_crtc_state); |
f8437dd1 | 7645 | |
7a8fdb1f | 7646 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 7647 | dev_priv->display.initial_watermarks(state, crtc); |
04548cba | 7648 | else |
e44c84a1 | 7649 | intel_update_watermarks(crtc); |
502d8714 | 7650 | intel_enable_pipe(new_crtc_state); |
f8437dd1 | 7651 | |
502d8714 | 7652 | intel_crtc_vblank_on(new_crtc_state); |
f8437dd1 | 7653 | |
e44c84a1 | 7654 | intel_encoders_enable(state, crtc); |
f6a7d395 VS |
7655 | |
7656 | /* prevents spurious underruns */ | |
7657 | if (IS_GEN(dev_priv, 2)) | |
7658 | intel_wait_for_vblank(dev_priv, pipe); | |
7ff89ca2 | 7659 | } |
f8437dd1 | 7660 | |
b2562712 | 7661 | static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
7ff89ca2 | 7662 | { |
2225f3c6 | 7663 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
b2562712 | 7664 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f8437dd1 | 7665 | |
b2562712 | 7666 | if (!old_crtc_state->gmch_pfit.control) |
f8437dd1 | 7667 | return; |
f8437dd1 | 7668 | |
b104e8b2 | 7669 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); |
7ff89ca2 | 7670 | |
cd49f818 | 7671 | drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", |
dc008bf0 JN |
7672 | intel_de_read(dev_priv, PFIT_CONTROL)); |
7673 | intel_de_write(dev_priv, PFIT_CONTROL, 0); | |
f8437dd1 VK |
7674 | } |
7675 | ||
7451a074 VS |
7676 | static void i9xx_crtc_disable(struct intel_atomic_state *state, |
7677 | struct intel_crtc *crtc) | |
f8437dd1 | 7678 | { |
7451a074 VS |
7679 | struct intel_crtc_state *old_crtc_state = |
7680 | intel_atomic_get_old_crtc_state(state, crtc); | |
e44c84a1 VS |
7681 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7682 | enum pipe pipe = crtc->pipe; | |
d66a2194 | 7683 | |
d66a2194 | 7684 | /* |
7ff89ca2 VS |
7685 | * On gen2 planes are double buffered but the pipe isn't, so we must |
7686 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 7687 | */ |
cf819eff | 7688 | if (IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7689 | intel_wait_for_vblank(dev_priv, pipe); |
d66a2194 | 7690 | |
e44c84a1 | 7691 | intel_encoders_disable(state, crtc); |
d66a2194 | 7692 | |
f5271ee5 | 7693 | intel_crtc_vblank_off(old_crtc_state); |
d66a2194 | 7694 | |
4972f70a | 7695 | intel_disable_pipe(old_crtc_state); |
d66a2194 | 7696 | |
b2562712 | 7697 | i9xx_pfit_disable(old_crtc_state); |
89b3c3c7 | 7698 | |
e44c84a1 | 7699 | intel_encoders_post_disable(state, crtc); |
d66a2194 | 7700 | |
6f405638 | 7701 | if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { |
7ff89ca2 VS |
7702 | if (IS_CHERRYVIEW(dev_priv)) |
7703 | chv_disable_pll(dev_priv, pipe); | |
7704 | else if (IS_VALLEYVIEW(dev_priv)) | |
7705 | vlv_disable_pll(dev_priv, pipe); | |
7706 | else | |
b2354c78 | 7707 | i9xx_disable_pll(old_crtc_state); |
7ff89ca2 | 7708 | } |
c2e001ef | 7709 | |
e44c84a1 | 7710 | intel_encoders_post_pll_disable(state, crtc); |
89b3c3c7 | 7711 | |
cf819eff | 7712 | if (!IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7713 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
ff32c54e VS |
7714 | |
7715 | if (!dev_priv->display.initial_watermarks) | |
e44c84a1 | 7716 | intel_update_watermarks(crtc); |
2ee0da16 VS |
7717 | |
7718 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
7719 | if (IS_I830(dev_priv)) | |
7720 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
7721 | } |
7722 | ||
56273062 | 7723 | static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, |
da1d0e26 | 7724 | struct drm_modeset_acquire_ctx *ctx) |
f8437dd1 | 7725 | { |
7ff89ca2 | 7726 | struct intel_encoder *encoder; |
56273062 | 7727 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
c457d9cf VS |
7728 | struct intel_bw_state *bw_state = |
7729 | to_intel_bw_state(dev_priv->bw_obj.state); | |
1965de63 | 7730 | struct intel_cdclk_state *cdclk_state = |
28a30b45 | 7731 | to_intel_cdclk_state(dev_priv->cdclk.obj.state); |
3cf43cdc VS |
7732 | struct intel_dbuf_state *dbuf_state = |
7733 | to_intel_dbuf_state(dev_priv->dbuf.obj.state); | |
1e460bf9 | 7734 | struct intel_crtc_state *crtc_state = |
56273062 | 7735 | to_intel_crtc_state(crtc->base.state); |
7ff89ca2 | 7736 | enum intel_display_power_domain domain; |
b1e01595 | 7737 | struct intel_plane *plane; |
7ff89ca2 | 7738 | struct drm_atomic_state *state; |
1e460bf9 | 7739 | struct intel_crtc_state *temp_crtc_state; |
56273062 VS |
7740 | enum pipe pipe = crtc->pipe; |
7741 | u64 domains; | |
7ff89ca2 | 7742 | int ret; |
f8437dd1 | 7743 | |
56273062 | 7744 | if (!crtc_state->hw.active) |
7ff89ca2 | 7745 | return; |
a8ca4934 | 7746 | |
56273062 | 7747 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { |
b1e01595 VS |
7748 | const struct intel_plane_state *plane_state = |
7749 | to_intel_plane_state(plane->base.state); | |
709e05c3 | 7750 | |
f90a85e7 | 7751 | if (plane_state->uapi.visible) |
56273062 | 7752 | intel_plane_disable_noatomic(crtc, plane); |
7ff89ca2 | 7753 | } |
5d96d8af | 7754 | |
56273062 | 7755 | state = drm_atomic_state_alloc(&dev_priv->drm); |
7ff89ca2 | 7756 | if (!state) { |
cd49f818 WK |
7757 | drm_dbg_kms(&dev_priv->drm, |
7758 | "failed to disable [CRTC:%d:%s], out of memory", | |
7759 | crtc->base.base.id, crtc->base.name); | |
1c3f7700 | 7760 | return; |
7ff89ca2 | 7761 | } |
9f7eb31a | 7762 | |
da1d0e26 | 7763 | state->acquire_ctx = ctx; |
ea61791e | 7764 | |
7ff89ca2 | 7765 | /* Everything's already locked, -EDEADLK can't happen. */ |
56273062 VS |
7766 | temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); |
7767 | ret = drm_atomic_add_affected_connectors(state, &crtc->base); | |
9f7eb31a | 7768 | |
e57291c2 | 7769 | drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); |
5d96d8af | 7770 | |
56273062 | 7771 | dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc); |
4a806558 | 7772 | |
0853695c | 7773 | drm_atomic_state_put(state); |
842e0307 | 7774 | |
cd49f818 WK |
7775 | drm_dbg_kms(&dev_priv->drm, |
7776 | "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", | |
7777 | crtc->base.base.id, crtc->base.name); | |
56273062 VS |
7778 | |
7779 | crtc->active = false; | |
7780 | crtc->base.enabled = false; | |
7781 | ||
e57291c2 PB |
7782 | drm_WARN_ON(&dev_priv->drm, |
7783 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); | |
56273062 VS |
7784 | crtc_state->uapi.active = false; |
7785 | crtc_state->uapi.connector_mask = 0; | |
7786 | crtc_state->uapi.encoder_mask = 0; | |
58d124ea ML |
7787 | intel_crtc_free_hw_state(crtc_state); |
7788 | memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); | |
842e0307 | 7789 | |
56273062 | 7790 | for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) |
842e0307 ML |
7791 | encoder->base.crtc = NULL; |
7792 | ||
56273062 VS |
7793 | intel_fbc_disable(crtc); |
7794 | intel_update_watermarks(crtc); | |
7795 | intel_disable_shared_dpll(crtc_state); | |
b17d48e2 | 7796 | |
56273062 | 7797 | domains = crtc->enabled_power_domains; |
b17d48e2 | 7798 | for_each_power_domain(domain, domains) |
0e6e0be4 | 7799 | intel_display_power_put_unchecked(dev_priv, domain); |
56273062 | 7800 | crtc->enabled_power_domains = 0; |
565602d7 | 7801 | |
56273062 | 7802 | dev_priv->active_pipes &= ~BIT(pipe); |
1965de63 VS |
7803 | cdclk_state->min_cdclk[pipe] = 0; |
7804 | cdclk_state->min_voltage_level[pipe] = 0; | |
0c2d5512 | 7805 | cdclk_state->active_pipes &= ~BIT(pipe); |
c457d9cf | 7806 | |
3cf43cdc VS |
7807 | dbuf_state->active_pipes &= ~BIT(pipe); |
7808 | ||
56273062 VS |
7809 | bw_state->data_rate[pipe] = 0; |
7810 | bw_state->num_active_planes[pipe] = 0; | |
b17d48e2 ML |
7811 | } |
7812 | ||
6b72d486 ML |
7813 | /* |
7814 | * turn all crtc's off, but do not adjust state | |
7815 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
7816 | */ | |
70e0bd74 | 7817 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 7818 | { |
e2c8b870 | 7819 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 7820 | struct drm_atomic_state *state; |
e2c8b870 | 7821 | int ret; |
70e0bd74 | 7822 | |
e2c8b870 ML |
7823 | state = drm_atomic_helper_suspend(dev); |
7824 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 | 7825 | if (ret) |
cd49f818 WK |
7826 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", |
7827 | ret); | |
e2c8b870 ML |
7828 | else |
7829 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 7830 | return ret; |
ee7b9f93 JB |
7831 | } |
7832 | ||
ea5b213a | 7833 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 7834 | { |
4ef69c7a | 7835 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 7836 | |
ea5b213a CW |
7837 | drm_encoder_cleanup(encoder); |
7838 | kfree(intel_encoder); | |
7e7d76c3 JB |
7839 | } |
7840 | ||
0a91ca29 DV |
7841 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
7842 | * internal consistency). */ | |
3b4bf24d | 7843 | static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, |
749d98b8 | 7844 | struct drm_connector_state *conn_state) |
79e53945 | 7845 | { |
749d98b8 | 7846 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
cd49f818 | 7847 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
35dd3c64 | 7848 | |
cd49f818 WK |
7849 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", |
7850 | connector->base.base.id, connector->base.name); | |
35dd3c64 | 7851 | |
0a91ca29 | 7852 | if (connector->get_hw_state(connector)) { |
fa7edcd2 | 7853 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
0a91ca29 | 7854 | |
749d98b8 | 7855 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 7856 | "connector enabled without attached crtc\n"); |
0a91ca29 | 7857 | |
749d98b8 | 7858 | if (!crtc_state) |
35dd3c64 ML |
7859 | return; |
7860 | ||
1326a92c ML |
7861 | I915_STATE_WARN(!crtc_state->hw.active, |
7862 | "connector is active, but attached crtc isn't\n"); | |
35dd3c64 | 7863 | |
e85376cb | 7864 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
7865 | return; |
7866 | ||
e85376cb | 7867 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
7868 | "atomic encoder doesn't match attached encoder\n"); |
7869 | ||
e85376cb | 7870 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
7871 | "attached encoder crtc differs from connector crtc\n"); |
7872 | } else { | |
1326a92c ML |
7873 | I915_STATE_WARN(crtc_state && crtc_state->hw.active, |
7874 | "attached crtc is active, but connector isn't\n"); | |
749d98b8 | 7875 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 7876 | "best encoder set without crtc!\n"); |
0a91ca29 | 7877 | } |
79e53945 JB |
7878 | } |
7879 | ||
6d293983 | 7880 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7881 | { |
1326a92c | 7882 | if (crtc_state->hw.enable && crtc_state->has_pch_encoder) |
6d293983 | 7883 | return crtc_state->fdi_lanes; |
d272ddfa VS |
7884 | |
7885 | return 0; | |
7886 | } | |
7887 | ||
9eae5e27 LDM |
7888 | static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
7889 | struct intel_crtc_state *pipe_config) | |
1857e1da | 7890 | { |
8652744b | 7891 | struct drm_i915_private *dev_priv = to_i915(dev); |
2225f3c6 | 7892 | struct drm_atomic_state *state = pipe_config->uapi.state; |
6d293983 ACO |
7893 | struct intel_crtc *other_crtc; |
7894 | struct intel_crtc_state *other_crtc_state; | |
7895 | ||
cd49f818 WK |
7896 | drm_dbg_kms(&dev_priv->drm, |
7897 | "checking fdi config on pipe %c, lanes %i\n", | |
7898 | pipe_name(pipe), pipe_config->fdi_lanes); | |
1857e1da | 7899 | if (pipe_config->fdi_lanes > 4) { |
cd49f818 WK |
7900 | drm_dbg_kms(&dev_priv->drm, |
7901 | "invalid fdi lane config on pipe %c: %i lanes\n", | |
7902 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7903 | return -EINVAL; |
1857e1da DV |
7904 | } |
7905 | ||
8652744b | 7906 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da | 7907 | if (pipe_config->fdi_lanes > 2) { |
cd49f818 WK |
7908 | drm_dbg_kms(&dev_priv->drm, |
7909 | "only 2 lanes on haswell, required: %i lanes\n", | |
7910 | pipe_config->fdi_lanes); | |
6d293983 | 7911 | return -EINVAL; |
1857e1da | 7912 | } else { |
6d293983 | 7913 | return 0; |
1857e1da DV |
7914 | } |
7915 | } | |
7916 | ||
24977870 | 7917 | if (INTEL_NUM_PIPES(dev_priv) == 2) |
6d293983 | 7918 | return 0; |
1857e1da DV |
7919 | |
7920 | /* Ivybridge 3 pipe is really complicated */ | |
7921 | switch (pipe) { | |
7922 | case PIPE_A: | |
6d293983 | 7923 | return 0; |
1857e1da | 7924 | case PIPE_B: |
6d293983 ACO |
7925 | if (pipe_config->fdi_lanes <= 2) |
7926 | return 0; | |
7927 | ||
b91eb5cc | 7928 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7929 | other_crtc_state = |
7930 | intel_atomic_get_crtc_state(state, other_crtc); | |
7931 | if (IS_ERR(other_crtc_state)) | |
7932 | return PTR_ERR(other_crtc_state); | |
7933 | ||
7934 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
cd49f818 WK |
7935 | drm_dbg_kms(&dev_priv->drm, |
7936 | "invalid shared fdi lane config on pipe %c: %i lanes\n", | |
7937 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7938 | return -EINVAL; |
1857e1da | 7939 | } |
6d293983 | 7940 | return 0; |
1857e1da | 7941 | case PIPE_C: |
251cc67c | 7942 | if (pipe_config->fdi_lanes > 2) { |
cd49f818 WK |
7943 | drm_dbg_kms(&dev_priv->drm, |
7944 | "only 2 lanes on pipe %c: required %i lanes\n", | |
7945 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7946 | return -EINVAL; |
251cc67c | 7947 | } |
6d293983 | 7948 | |
b91eb5cc | 7949 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7950 | other_crtc_state = |
7951 | intel_atomic_get_crtc_state(state, other_crtc); | |
7952 | if (IS_ERR(other_crtc_state)) | |
7953 | return PTR_ERR(other_crtc_state); | |
7954 | ||
7955 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
cd49f818 WK |
7956 | drm_dbg_kms(&dev_priv->drm, |
7957 | "fdi link B uses too many lanes to enable link C\n"); | |
6d293983 | 7958 | return -EINVAL; |
1857e1da | 7959 | } |
6d293983 | 7960 | return 0; |
1857e1da DV |
7961 | default: |
7962 | BUG(); | |
7963 | } | |
7964 | } | |
7965 | ||
e29c22c0 | 7966 | #define RETRY 1 |
9eae5e27 LDM |
7967 | static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc, |
7968 | struct intel_crtc_state *pipe_config) | |
877d48d5 | 7969 | { |
1857e1da | 7970 | struct drm_device *dev = intel_crtc->base.dev; |
cd49f818 | 7971 | struct drm_i915_private *i915 = to_i915(dev); |
1326a92c | 7972 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
6d293983 ACO |
7973 | int lane, link_bw, fdi_dotclock, ret; |
7974 | bool needs_recompute = false; | |
877d48d5 | 7975 | |
e29c22c0 | 7976 | retry: |
877d48d5 DV |
7977 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7978 | * each output octet as 10 bits. The actual frequency | |
7979 | * is stored as a divider into a 100MHz clock, and the | |
7980 | * mode pixel clock is stored in units of 1KHz. | |
7981 | * Hence the bw of each lane in terms of the mode signal | |
7982 | * is: | |
7983 | */ | |
cd49f818 | 7984 | link_bw = intel_fdi_link_freq(i915, pipe_config); |
877d48d5 | 7985 | |
241bfc38 | 7986 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7987 | |
9eae5e27 LDM |
7988 | lane = ilk_get_lanes_required(fdi_dotclock, link_bw, |
7989 | pipe_config->pipe_bpp); | |
877d48d5 DV |
7990 | |
7991 | pipe_config->fdi_lanes = lane; | |
7992 | ||
2bd89a07 | 7993 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
ed06efb8 | 7994 | link_bw, &pipe_config->fdi_m_n, false, false); |
1857e1da | 7995 | |
9eae5e27 | 7996 | ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
8e2b4dff VS |
7997 | if (ret == -EDEADLK) |
7998 | return ret; | |
7999 | ||
6d293983 | 8000 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 8001 | pipe_config->pipe_bpp -= 2*3; |
cd49f818 WK |
8002 | drm_dbg_kms(&i915->drm, |
8003 | "fdi link bw constraint, reducing pipe bpp to %i\n", | |
8004 | pipe_config->pipe_bpp); | |
7ff89ca2 VS |
8005 | needs_recompute = true; |
8006 | pipe_config->bw_constrained = true; | |
257a7ffc | 8007 | |
7ff89ca2 | 8008 | goto retry; |
257a7ffc | 8009 | } |
79e53945 | 8010 | |
7ff89ca2 VS |
8011 | if (needs_recompute) |
8012 | return RETRY; | |
e70236a8 | 8013 | |
7ff89ca2 | 8014 | return ret; |
e70236a8 JB |
8015 | } |
8016 | ||
24f28450 | 8017 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) |
e70236a8 | 8018 | { |
2225f3c6 | 8019 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
24f28450 ML |
8020 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8021 | ||
8022 | /* IPS only exists on ULT machines and is tied to pipe A. */ | |
8023 | if (!hsw_crtc_supports_ips(crtc)) | |
6e644626 VS |
8024 | return false; |
8025 | ||
8a25c4be | 8026 | if (!dev_priv->params.enable_ips) |
7ff89ca2 | 8027 | return false; |
e70236a8 | 8028 | |
24f28450 ML |
8029 | if (crtc_state->pipe_bpp > 24) |
8030 | return false; | |
1b1d2716 | 8031 | |
65cd2b3f | 8032 | /* |
7ff89ca2 VS |
8033 | * We compare against max which means we must take |
8034 | * the increased cdclk requirement into account when | |
8035 | * calculating the new cdclk. | |
8036 | * | |
8037 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 8038 | */ |
24f28450 ML |
8039 | if (IS_BROADWELL(dev_priv) && |
8040 | crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) | |
8041 | return false; | |
8042 | ||
8043 | return true; | |
e70236a8 | 8044 | } |
79e53945 | 8045 | |
28a30b45 | 8046 | static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state) |
7ff89ca2 | 8047 | { |
24f28450 | 8048 | struct drm_i915_private *dev_priv = |
2225f3c6 | 8049 | to_i915(crtc_state->uapi.crtc->dev); |
28a30b45 | 8050 | struct intel_atomic_state *state = |
2225f3c6 | 8051 | to_intel_atomic_state(crtc_state->uapi.state); |
28a30b45 VS |
8052 | |
8053 | crtc_state->ips_enabled = false; | |
24f28450 ML |
8054 | |
8055 | if (!hsw_crtc_state_ips_capable(crtc_state)) | |
28a30b45 | 8056 | return 0; |
24f28450 | 8057 | |
a8ebf607 JRS |
8058 | /* |
8059 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
8060 | * enabled and disabled dynamically based on package C states, | |
8061 | * user space can't make reliable use of the CRCs, so let's just | |
8062 | * completely disable it. | |
8063 | */ | |
8064 | if (crtc_state->crc_enabled) | |
28a30b45 | 8065 | return 0; |
24f28450 | 8066 | |
adbe5c5c ML |
8067 | /* IPS should be fine as long as at least one plane is enabled. */ |
8068 | if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) | |
28a30b45 | 8069 | return 0; |
34edce2f | 8070 | |
28a30b45 VS |
8071 | if (IS_BROADWELL(dev_priv)) { |
8072 | const struct intel_cdclk_state *cdclk_state; | |
24f28450 | 8073 | |
28a30b45 VS |
8074 | cdclk_state = intel_atomic_get_cdclk_state(state); |
8075 | if (IS_ERR(cdclk_state)) | |
8076 | return PTR_ERR(cdclk_state); | |
8077 | ||
8078 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
8079 | if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) | |
8080 | return 0; | |
8081 | } | |
8082 | ||
8083 | crtc_state->ips_enabled = true; | |
8084 | ||
8085 | return 0; | |
34edce2f VS |
8086 | } |
8087 | ||
7ff89ca2 | 8088 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 8089 | { |
7ff89ca2 | 8090 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 8091 | |
7ff89ca2 | 8092 | /* GDG double wide on either pipe, otherwise pipe A only */ |
c56b89f1 | 8093 | return INTEL_GEN(dev_priv) < 4 && |
7ff89ca2 | 8094 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
34edce2f VS |
8095 | } |
8096 | ||
eac9c585 | 8097 | static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) |
ceb99320 | 8098 | { |
bafcdad6 | 8099 | u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; |
35dd95b4 | 8100 | unsigned int pipe_w, pipe_h, pfit_w, pfit_h; |
ceb99320 VS |
8101 | |
8102 | /* | |
8103 | * We only use IF-ID interlacing. If we ever use | |
8104 | * PF-ID we'll need to adjust the pixel_rate here. | |
8105 | */ | |
8106 | ||
eac9c585 VS |
8107 | if (!crtc_state->pch_pfit.enabled) |
8108 | return pixel_rate; | |
ceb99320 | 8109 | |
eac9c585 VS |
8110 | pipe_w = crtc_state->pipe_src_w; |
8111 | pipe_h = crtc_state->pipe_src_h; | |
ceb99320 | 8112 | |
35dd95b4 VS |
8113 | pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst); |
8114 | pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst); | |
8115 | ||
eac9c585 VS |
8116 | if (pipe_w < pfit_w) |
8117 | pipe_w = pfit_w; | |
8118 | if (pipe_h < pfit_h) | |
8119 | pipe_h = pfit_h; | |
ceb99320 | 8120 | |
eac9c585 VS |
8121 | if (drm_WARN_ON(crtc_state->uapi.crtc->dev, |
8122 | !pfit_w || !pfit_h)) | |
8123 | return pixel_rate; | |
ceb99320 | 8124 | |
eac9c585 VS |
8125 | return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h), |
8126 | pfit_w * pfit_h); | |
ceb99320 VS |
8127 | } |
8128 | ||
33574ec9 VS |
8129 | static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, |
8130 | const struct drm_display_mode *timings) | |
8131 | { | |
8132 | mode->hdisplay = timings->crtc_hdisplay; | |
8133 | mode->htotal = timings->crtc_htotal; | |
8134 | mode->hsync_start = timings->crtc_hsync_start; | |
8135 | mode->hsync_end = timings->crtc_hsync_end; | |
8136 | ||
8137 | mode->vdisplay = timings->crtc_vdisplay; | |
8138 | mode->vtotal = timings->crtc_vtotal; | |
8139 | mode->vsync_start = timings->crtc_vsync_start; | |
8140 | mode->vsync_end = timings->crtc_vsync_end; | |
8141 | ||
8142 | mode->flags = timings->flags; | |
8143 | mode->type = DRM_MODE_TYPE_DRIVER; | |
8144 | ||
8145 | mode->clock = timings->crtc_clock; | |
8146 | ||
8147 | drm_mode_set_name(mode); | |
8148 | } | |
8149 | ||
7ff89ca2 | 8150 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 8151 | { |
2225f3c6 | 8152 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
34edce2f | 8153 | |
b2ae318a | 8154 | if (HAS_GMCH(dev_priv)) |
7ff89ca2 VS |
8155 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ |
8156 | crtc_state->pixel_rate = | |
bafcdad6 | 8157 | crtc_state->hw.pipe_mode.crtc_clock; |
7ff89ca2 VS |
8158 | else |
8159 | crtc_state->pixel_rate = | |
8160 | ilk_pipe_pixel_rate(crtc_state); | |
8161 | } | |
34edce2f | 8162 | |
c42773b6 VS |
8163 | static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) |
8164 | { | |
8165 | struct drm_display_mode *mode = &crtc_state->hw.mode; | |
bafcdad6 | 8166 | struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; |
c42773b6 VS |
8167 | struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
8168 | ||
bafcdad6 ML |
8169 | drm_mode_copy(pipe_mode, adjusted_mode); |
8170 | ||
8171 | intel_mode_from_crtc_timings(pipe_mode, pipe_mode); | |
c42773b6 VS |
8172 | intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode); |
8173 | ||
8174 | intel_crtc_compute_pixel_rate(crtc_state); | |
8175 | ||
8176 | drm_mode_copy(mode, adjusted_mode); | |
8177 | mode->hdisplay = crtc_state->pipe_src_w; | |
8178 | mode->vdisplay = crtc_state->pipe_src_h; | |
8179 | } | |
8180 | ||
65c1ed30 MN |
8181 | static void intel_encoder_get_config(struct intel_encoder *encoder, |
8182 | struct intel_crtc_state *crtc_state) | |
8183 | { | |
8184 | encoder->get_config(encoder, crtc_state); | |
c42773b6 VS |
8185 | |
8186 | intel_crtc_readout_derived_state(crtc_state); | |
65c1ed30 MN |
8187 | } |
8188 | ||
7ff89ca2 VS |
8189 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
8190 | struct intel_crtc_state *pipe_config) | |
8191 | { | |
d2daff2c | 8192 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bafcdad6 | 8193 | struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode; |
7ff89ca2 | 8194 | int clock_limit = dev_priv->max_dotclk_freq; |
34edce2f | 8195 | |
bafcdad6 ML |
8196 | drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode); |
8197 | intel_mode_from_crtc_timings(pipe_mode, pipe_mode); | |
8198 | ||
7ff89ca2 VS |
8199 | if (INTEL_GEN(dev_priv) < 4) { |
8200 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 8201 | |
7ff89ca2 VS |
8202 | /* |
8203 | * Enable double wide mode when the dot clock | |
8204 | * is > 90% of the (display) core speed. | |
8205 | */ | |
8206 | if (intel_crtc_supports_double_wide(crtc) && | |
bafcdad6 | 8207 | pipe_mode->crtc_clock > clock_limit) { |
7ff89ca2 VS |
8208 | clock_limit = dev_priv->max_dotclk_freq; |
8209 | pipe_config->double_wide = true; | |
8210 | } | |
34edce2f VS |
8211 | } |
8212 | ||
bafcdad6 | 8213 | if (pipe_mode->crtc_clock > clock_limit) { |
cd49f818 WK |
8214 | drm_dbg_kms(&dev_priv->drm, |
8215 | "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
bafcdad6 | 8216 | pipe_mode->crtc_clock, clock_limit, |
cd49f818 | 8217 | yesno(pipe_config->double_wide)); |
7ff89ca2 VS |
8218 | return -EINVAL; |
8219 | } | |
34edce2f | 8220 | |
8c79f844 SS |
8221 | if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
8222 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) && | |
1326a92c | 8223 | pipe_config->hw.ctm) { |
25edf915 SS |
8224 | /* |
8225 | * There is only one pipe CSC unit per pipe, and we need that | |
8226 | * for output conversion from RGB->YCBCR. So if CTM is already | |
8227 | * applied we can't support YCBCR420 output. | |
8228 | */ | |
cd49f818 WK |
8229 | drm_dbg_kms(&dev_priv->drm, |
8230 | "YCBCR420 and CTM together are not possible\n"); | |
25edf915 SS |
8231 | return -EINVAL; |
8232 | } | |
8233 | ||
7ff89ca2 VS |
8234 | /* |
8235 | * Pipe horizontal size must be even in: | |
8236 | * - DVO ganged mode | |
8237 | * - LVDS dual channel mode | |
8238 | * - Double wide pipe | |
8239 | */ | |
0574bd88 VS |
8240 | if (pipe_config->pipe_src_w & 1) { |
8241 | if (pipe_config->double_wide) { | |
cd49f818 WK |
8242 | drm_dbg_kms(&dev_priv->drm, |
8243 | "Odd pipe source width not supported with double wide pipe\n"); | |
0574bd88 VS |
8244 | return -EINVAL; |
8245 | } | |
8246 | ||
8247 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
d2daff2c | 8248 | intel_is_dual_link_lvds(dev_priv)) { |
cd49f818 WK |
8249 | drm_dbg_kms(&dev_priv->drm, |
8250 | "Odd pipe source width not supported with dual link LVDS\n"); | |
0574bd88 VS |
8251 | return -EINVAL; |
8252 | } | |
8253 | } | |
34edce2f | 8254 | |
7ff89ca2 VS |
8255 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
8256 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
8257 | */ | |
8258 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
bafcdad6 | 8259 | pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay) |
7ff89ca2 | 8260 | return -EINVAL; |
34edce2f | 8261 | |
7ff89ca2 | 8262 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 8263 | |
7ff89ca2 | 8264 | if (pipe_config->has_pch_encoder) |
9eae5e27 | 8265 | return ilk_fdi_compute_config(crtc, pipe_config); |
34edce2f | 8266 | |
7ff89ca2 | 8267 | return 0; |
34edce2f VS |
8268 | } |
8269 | ||
2c07245f | 8270 | static void |
ba3f4d0a | 8271 | intel_reduce_m_n_ratio(u32 *num, u32 *den) |
2c07245f | 8272 | { |
a65851af VS |
8273 | while (*num > DATA_LINK_M_N_MASK || |
8274 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
8275 | *num >>= 1; |
8276 | *den >>= 1; | |
8277 | } | |
8278 | } | |
8279 | ||
a65851af | 8280 | static void compute_m_n(unsigned int m, unsigned int n, |
ba3f4d0a | 8281 | u32 *ret_m, u32 *ret_n, |
53ca2edc | 8282 | bool constant_n) |
a65851af | 8283 | { |
9a86cda0 | 8284 | /* |
53ca2edc LS |
8285 | * Several DP dongles in particular seem to be fussy about |
8286 | * too large link M/N values. Give N value as 0x8000 that | |
8287 | * should be acceptable by specific devices. 0x8000 is the | |
8288 | * specified fixed N value for asynchronous clock mode, | |
8289 | * which the devices expect also in synchronous clock mode. | |
9a86cda0 | 8290 | */ |
53ca2edc | 8291 | if (constant_n) |
b22960b8 | 8292 | *ret_n = DP_LINK_CONSTANT_N_VALUE; |
53ca2edc LS |
8293 | else |
8294 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
9a86cda0 | 8295 | |
d492a29d | 8296 | *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); |
a65851af VS |
8297 | intel_reduce_m_n_ratio(ret_m, ret_n); |
8298 | } | |
8299 | ||
e69d0bc1 | 8300 | void |
a4a15777 | 8301 | intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, |
e69d0bc1 | 8302 | int pixel_clock, int link_clock, |
b31e85ed | 8303 | struct intel_link_m_n *m_n, |
ed06efb8 | 8304 | bool constant_n, bool fec_enable) |
2c07245f | 8305 | { |
ed06efb8 ML |
8306 | u32 data_clock = bits_per_pixel * pixel_clock; |
8307 | ||
8308 | if (fec_enable) | |
8309 | data_clock = intel_dp_mode_to_fec_clock(data_clock); | |
a65851af | 8310 | |
ed06efb8 ML |
8311 | m_n->tu = 64; |
8312 | compute_m_n(data_clock, | |
a65851af | 8313 | link_clock * nlanes * 8, |
b31e85ed | 8314 | &m_n->gmch_m, &m_n->gmch_n, |
53ca2edc | 8315 | constant_n); |
a65851af VS |
8316 | |
8317 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed | 8318 | &m_n->link_m, &m_n->link_n, |
53ca2edc | 8319 | constant_n); |
2c07245f ZW |
8320 | } |
8321 | ||
064bd628 JN |
8322 | static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) |
8323 | { | |
8324 | /* | |
8325 | * There may be no VBT; and if the BIOS enabled SSC we can | |
8326 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
8327 | * BIOS isn't using it, don't assume it will work even if the VBT | |
8328 | * indicates as much. | |
8329 | */ | |
8330 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { | |
dc008bf0 JN |
8331 | bool bios_lvds_use_ssc = intel_de_read(dev_priv, |
8332 | PCH_DREF_CONTROL) & | |
064bd628 JN |
8333 | DREF_SSC1_ENABLE; |
8334 | ||
8335 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
cd49f818 WK |
8336 | drm_dbg_kms(&dev_priv->drm, |
8337 | "SSC %s by BIOS, overriding VBT which says %s\n", | |
8338 | enableddisabled(bios_lvds_use_ssc), | |
8339 | enableddisabled(dev_priv->vbt.lvds_use_ssc)); | |
064bd628 JN |
8340 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
8341 | } | |
8342 | } | |
8343 | } | |
8344 | ||
81b55ef1 | 8345 | static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
a7615030 | 8346 | { |
8a25c4be JN |
8347 | if (dev_priv->params.panel_use_ssc >= 0) |
8348 | return dev_priv->params.panel_use_ssc != 0; | |
41aa3448 | 8349 | return dev_priv->vbt.lvds_use_ssc |
435793df | 8350 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
8351 | } |
8352 | ||
ba3f4d0a | 8353 | static u32 pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 8354 | { |
7df00d7a | 8355 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 8356 | } |
f47709a9 | 8357 | |
ba3f4d0a | 8358 | static u32 i9xx_dpll_compute_fp(struct dpll *dpll) |
7429e9d4 DV |
8359 | { |
8360 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
8361 | } |
8362 | ||
f47709a9 | 8363 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 8364 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 8365 | struct dpll *reduced_clock) |
a7516a05 | 8366 | { |
9b1e14f4 | 8367 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
8368 | u32 fp, fp2 = 0; |
8369 | ||
9b1e14f4 | 8370 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 8371 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 8372 | if (reduced_clock) |
7429e9d4 | 8373 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 8374 | } else { |
190f68c5 | 8375 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 8376 | if (reduced_clock) |
7429e9d4 | 8377 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
8378 | } |
8379 | ||
190f68c5 | 8380 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 8381 | |
2d84d2b3 | 8382 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 8383 | reduced_clock) { |
190f68c5 | 8384 | crtc_state->dpll_hw_state.fp1 = fp2; |
a7516a05 | 8385 | } else { |
190f68c5 | 8386 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
8387 | } |
8388 | } | |
8389 | ||
5e69f97f CML |
8390 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
8391 | pipe) | |
89b667f8 JB |
8392 | { |
8393 | u32 reg_val; | |
8394 | ||
8395 | /* | |
8396 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
8397 | * and set it to a reasonable value instead. | |
8398 | */ | |
ab3c759a | 8399 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
8400 | reg_val &= 0xffffff00; |
8401 | reg_val |= 0x00000030; | |
ab3c759a | 8402 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 8403 | |
ab3c759a | 8404 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
8405 | reg_val &= 0x00ffffff; |
8406 | reg_val |= 0x8c000000; | |
ab3c759a | 8407 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 8408 | |
ab3c759a | 8409 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 8410 | reg_val &= 0xffffff00; |
ab3c759a | 8411 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 8412 | |
ab3c759a | 8413 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
8414 | reg_val &= 0x00ffffff; |
8415 | reg_val |= 0xb0000000; | |
ab3c759a | 8416 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
8417 | } |
8418 | ||
4c354754 ML |
8419 | static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
8420 | const struct intel_link_m_n *m_n) | |
b551842d | 8421 | { |
2225f3c6 | 8422 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4c354754 ML |
8423 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8424 | enum pipe pipe = crtc->pipe; | |
b551842d | 8425 | |
dc008bf0 JN |
8426 | intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe), |
8427 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8428 | intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
8429 | intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
8430 | intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
8431 | } |
8432 | ||
4207c8b9 ML |
8433 | static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, |
8434 | enum transcoder transcoder) | |
8435 | { | |
8436 | if (IS_HASWELL(dev_priv)) | |
8437 | return transcoder == TRANSCODER_EDP; | |
8438 | ||
8439 | /* | |
8440 | * Strictly speaking some registers are available before | |
8441 | * gen7, but we only support DRRS on gen7+ | |
8442 | */ | |
cf819eff | 8443 | return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); |
4207c8b9 ML |
8444 | } |
8445 | ||
4c354754 ML |
8446 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
8447 | const struct intel_link_m_n *m_n, | |
8448 | const struct intel_link_m_n *m2_n2) | |
b551842d | 8449 | { |
2225f3c6 | 8450 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 8451 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4c354754 ML |
8452 | enum pipe pipe = crtc->pipe; |
8453 | enum transcoder transcoder = crtc_state->cpu_transcoder; | |
b551842d | 8454 | |
6315b5d3 | 8455 | if (INTEL_GEN(dev_priv) >= 5) { |
dc008bf0 JN |
8456 | intel_de_write(dev_priv, PIPE_DATA_M1(transcoder), |
8457 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8458 | intel_de_write(dev_priv, PIPE_DATA_N1(transcoder), | |
8459 | m_n->gmch_n); | |
8460 | intel_de_write(dev_priv, PIPE_LINK_M1(transcoder), | |
8461 | m_n->link_m); | |
8462 | intel_de_write(dev_priv, PIPE_LINK_N1(transcoder), | |
8463 | m_n->link_n); | |
4207c8b9 ML |
8464 | /* |
8465 | * M2_N2 registers are set only if DRRS is supported | |
8466 | * (to make sure the registers are not unnecessarily accessed). | |
f769cd24 | 8467 | */ |
4207c8b9 ML |
8468 | if (m2_n2 && crtc_state->has_drrs && |
8469 | transcoder_has_m2_n2(dev_priv, transcoder)) { | |
dc008bf0 JN |
8470 | intel_de_write(dev_priv, PIPE_DATA_M2(transcoder), |
8471 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
8472 | intel_de_write(dev_priv, PIPE_DATA_N2(transcoder), | |
8473 | m2_n2->gmch_n); | |
8474 | intel_de_write(dev_priv, PIPE_LINK_M2(transcoder), | |
8475 | m2_n2->link_m); | |
8476 | intel_de_write(dev_priv, PIPE_LINK_N2(transcoder), | |
8477 | m2_n2->link_n); | |
f769cd24 | 8478 | } |
b551842d | 8479 | } else { |
dc008bf0 JN |
8480 | intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe), |
8481 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8482 | intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
8483 | intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
8484 | intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
8485 | } |
8486 | } | |
8487 | ||
4c354754 | 8488 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n) |
03afc4a2 | 8489 | { |
4c354754 | 8490 | const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
cd49f818 | 8491 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
fe3cd48d R |
8492 | |
8493 | if (m_n == M1_N1) { | |
4c354754 ML |
8494 | dp_m_n = &crtc_state->dp_m_n; |
8495 | dp_m2_n2 = &crtc_state->dp_m2_n2; | |
fe3cd48d R |
8496 | } else if (m_n == M2_N2) { |
8497 | ||
8498 | /* | |
8499 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
8500 | * needs to be programmed into M1_N1. | |
8501 | */ | |
4c354754 | 8502 | dp_m_n = &crtc_state->dp_m2_n2; |
fe3cd48d | 8503 | } else { |
cd49f818 | 8504 | drm_err(&i915->drm, "Unsupported divider value\n"); |
fe3cd48d R |
8505 | return; |
8506 | } | |
8507 | ||
4c354754 ML |
8508 | if (crtc_state->has_pch_encoder) |
8509 | intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n); | |
03afc4a2 | 8510 | else |
4c354754 | 8511 | intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
8512 | } |
8513 | ||
251ac862 DV |
8514 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
8515 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 8516 | { |
03ed5cbf | 8517 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 8518 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
8519 | if (crtc->pipe != PIPE_A) |
8520 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 8521 | |
cd2d34d9 | 8522 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 8523 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
8524 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
8525 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
8526 | ||
03ed5cbf VS |
8527 | pipe_config->dpll_hw_state.dpll_md = |
8528 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8529 | } | |
bdd4b6a6 | 8530 | |
03ed5cbf VS |
8531 | static void chv_compute_dpll(struct intel_crtc *crtc, |
8532 | struct intel_crtc_state *pipe_config) | |
8533 | { | |
8534 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 8535 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
8536 | if (crtc->pipe != PIPE_A) |
8537 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
8538 | ||
cd2d34d9 | 8539 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 8540 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
8541 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
8542 | ||
03ed5cbf VS |
8543 | pipe_config->dpll_hw_state.dpll_md = |
8544 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
8545 | } |
8546 | ||
d288f65f | 8547 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 8548 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 8549 | { |
f47709a9 | 8550 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8551 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8552 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 8553 | u32 mdiv; |
a0c4da24 | 8554 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 8555 | u32 coreclk, reg_val; |
a0c4da24 | 8556 | |
cd2d34d9 | 8557 | /* Enable Refclk */ |
dc008bf0 JN |
8558 | intel_de_write(dev_priv, DPLL(pipe), |
8559 | pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
cd2d34d9 VS |
8560 | |
8561 | /* No need to actually set up the DPLL with DSI */ | |
8562 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8563 | return; | |
8564 | ||
221c7862 | 8565 | vlv_dpio_get(dev_priv); |
09153000 | 8566 | |
d288f65f VS |
8567 | bestn = pipe_config->dpll.n; |
8568 | bestm1 = pipe_config->dpll.m1; | |
8569 | bestm2 = pipe_config->dpll.m2; | |
8570 | bestp1 = pipe_config->dpll.p1; | |
8571 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 8572 | |
89b667f8 JB |
8573 | /* See eDP HDMI DPIO driver vbios notes doc */ |
8574 | ||
8575 | /* PLL B needs special handling */ | |
bdd4b6a6 | 8576 | if (pipe == PIPE_B) |
5e69f97f | 8577 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
8578 | |
8579 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 8580 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
8581 | |
8582 | /* Disable target IRef on PLL */ | |
ab3c759a | 8583 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 8584 | reg_val &= 0x00ffffff; |
ab3c759a | 8585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
8586 | |
8587 | /* Disable fast lock */ | |
ab3c759a | 8588 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
8589 | |
8590 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
8591 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
8592 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
8593 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 8594 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
8595 | |
8596 | /* | |
8597 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
8598 | * but we don't support that). | |
8599 | * Note: don't use the DAC post divider as it seems unstable. | |
8600 | */ | |
8601 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 8602 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 8603 | |
a0c4da24 | 8604 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 8605 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 8606 | |
89b667f8 | 8607 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 8608 | if (pipe_config->port_clock == 162000 || |
92d54b07 ML |
8609 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || |
8610 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 8611 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 8612 | 0x009f0003); |
89b667f8 | 8613 | else |
ab3c759a | 8614 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
8615 | 0x00d0000f); |
8616 | ||
37a5650b | 8617 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 8618 | /* Use SSC source */ |
bdd4b6a6 | 8619 | if (pipe == PIPE_A) |
ab3c759a | 8620 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8621 | 0x0df40000); |
8622 | else | |
ab3c759a | 8623 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8624 | 0x0df70000); |
8625 | } else { /* HDMI or VGA */ | |
8626 | /* Use bend source */ | |
bdd4b6a6 | 8627 | if (pipe == PIPE_A) |
ab3c759a | 8628 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8629 | 0x0df70000); |
8630 | else | |
ab3c759a | 8631 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8632 | 0x0df40000); |
8633 | } | |
a0c4da24 | 8634 | |
ab3c759a | 8635 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 8636 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
92d54b07 | 8637 | if (intel_crtc_has_dp_encoder(pipe_config)) |
89b667f8 | 8638 | coreclk |= 0x01000000; |
ab3c759a | 8639 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 8640 | |
ab3c759a | 8641 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
221c7862 CW |
8642 | |
8643 | vlv_dpio_put(dev_priv); | |
a0c4da24 JB |
8644 | } |
8645 | ||
d288f65f | 8646 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 8647 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
8648 | { |
8649 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8650 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8651 | enum pipe pipe = crtc->pipe; |
9d556c99 | 8652 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 8653 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 8654 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 8655 | u32 dpio_val; |
9cbe40c1 | 8656 | int vco; |
9d556c99 | 8657 | |
cd2d34d9 | 8658 | /* Enable Refclk and SSC */ |
dc008bf0 JN |
8659 | intel_de_write(dev_priv, DPLL(pipe), |
8660 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
cd2d34d9 VS |
8661 | |
8662 | /* No need to actually set up the DPLL with DSI */ | |
8663 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8664 | return; | |
8665 | ||
d288f65f VS |
8666 | bestn = pipe_config->dpll.n; |
8667 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
8668 | bestm1 = pipe_config->dpll.m1; | |
8669 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8670 | bestp1 = pipe_config->dpll.p1; | |
8671 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8672 | vco = pipe_config->dpll.vco; |
a945ce7e | 8673 | dpio_val = 0; |
9cbe40c1 | 8674 | loopfilter = 0; |
9d556c99 | 8675 | |
221c7862 | 8676 | vlv_dpio_get(dev_priv); |
9d556c99 | 8677 | |
9d556c99 CML |
8678 | /* p1 and p2 divider */ |
8679 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8680 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8681 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8682 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8683 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8684 | ||
8685 | /* Feedback post-divider - m2 */ | |
8686 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8687 | ||
8688 | /* Feedback refclk divider - n and m1 */ | |
8689 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8690 | DPIO_CHV_M1_DIV_BY_2 | | |
8691 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8692 | ||
8693 | /* M2 fraction division */ | |
25a25dfc | 8694 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8695 | |
8696 | /* M2 fraction division enable */ | |
a945ce7e VP |
8697 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8698 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8699 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8700 | if (bestm2_frac) | |
8701 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8702 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8703 | |
de3a0fde VP |
8704 | /* Program digital lock detect threshold */ |
8705 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8706 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8707 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8708 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8709 | if (!bestm2_frac) | |
8710 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8711 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8712 | ||
9d556c99 | 8713 | /* Loop filter */ |
9cbe40c1 VP |
8714 | if (vco == 5400000) { |
8715 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8716 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8717 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8718 | tribuf_calcntr = 0x9; | |
8719 | } else if (vco <= 6200000) { | |
8720 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8721 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8722 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8723 | tribuf_calcntr = 0x9; | |
8724 | } else if (vco <= 6480000) { | |
8725 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8726 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8727 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8728 | tribuf_calcntr = 0x8; | |
8729 | } else { | |
8730 | /* Not supported. Apply the same limits as in the max case */ | |
8731 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8732 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8733 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8734 | tribuf_calcntr = 0; | |
8735 | } | |
9d556c99 CML |
8736 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8737 | ||
968040b2 | 8738 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8739 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8740 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8741 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8742 | ||
9d556c99 CML |
8743 | /* AFC Recal */ |
8744 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8745 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8746 | DPIO_AFC_RECAL); | |
8747 | ||
221c7862 | 8748 | vlv_dpio_put(dev_priv); |
9d556c99 CML |
8749 | } |
8750 | ||
d288f65f VS |
8751 | /** |
8752 | * vlv_force_pll_on - forcibly enable just the PLL | |
8753 | * @dev_priv: i915 private structure | |
8754 | * @pipe: pipe PLL to enable | |
8755 | * @dpll: PLL configuration | |
8756 | * | |
8757 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8758 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8759 | * be enabled. | |
8760 | */ | |
30ad9814 | 8761 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8762 | const struct dpll *dpll) |
d288f65f | 8763 | { |
b91eb5cc | 8764 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8765 | struct intel_crtc_state *pipe_config; |
8766 | ||
216383e9 | 8767 | pipe_config = intel_crtc_state_alloc(crtc); |
3f36b937 TU |
8768 | if (!pipe_config) |
8769 | return -ENOMEM; | |
8770 | ||
b104e8b2 | 8771 | pipe_config->cpu_transcoder = (enum transcoder)pipe; |
3f36b937 TU |
8772 | pipe_config->pixel_multiplier = 1; |
8773 | pipe_config->dpll = *dpll; | |
d288f65f | 8774 | |
30ad9814 | 8775 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8776 | chv_compute_dpll(crtc, pipe_config); |
8777 | chv_prepare_pll(crtc, pipe_config); | |
8778 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8779 | } else { |
3f36b937 TU |
8780 | vlv_compute_dpll(crtc, pipe_config); |
8781 | vlv_prepare_pll(crtc, pipe_config); | |
8782 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8783 | } |
3f36b937 TU |
8784 | |
8785 | kfree(pipe_config); | |
8786 | ||
8787 | return 0; | |
d288f65f VS |
8788 | } |
8789 | ||
8790 | /** | |
8791 | * vlv_force_pll_off - forcibly disable just the PLL | |
8792 | * @dev_priv: i915 private structure | |
8793 | * @pipe: pipe PLL to disable | |
8794 | * | |
8795 | * Disable the PLL for @pipe. To be used in cases where we need | |
8796 | * the PLL enabled even when @pipe is not going to be enabled. | |
8797 | */ | |
30ad9814 | 8798 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8799 | { |
30ad9814 VS |
8800 | if (IS_CHERRYVIEW(dev_priv)) |
8801 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8802 | else |
30ad9814 | 8803 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8804 | } |
8805 | ||
251ac862 DV |
8806 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8807 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8808 | struct dpll *reduced_clock) |
eb1cbe48 | 8809 | { |
9b1e14f4 | 8810 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8811 | u32 dpll; |
190f68c5 | 8812 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8813 | |
190f68c5 | 8814 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8815 | |
eb1cbe48 DV |
8816 | dpll = DPLL_VGA_MODE_DIS; |
8817 | ||
2d84d2b3 | 8818 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8819 | dpll |= DPLLB_MODE_LVDS; |
8820 | else | |
8821 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8822 | |
73f67aa8 JN |
8823 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8824 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 8825 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8826 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8827 | } |
198a037f | 8828 | |
3d6e9ee0 VS |
8829 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8830 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8831 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8832 | |
37a5650b | 8833 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8834 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8835 | |
8836 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8837 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8838 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8839 | else { | |
8840 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8841 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8842 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8843 | } | |
8844 | switch (clock->p2) { | |
8845 | case 5: | |
8846 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8847 | break; | |
8848 | case 7: | |
8849 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8850 | break; | |
8851 | case 10: | |
8852 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8853 | break; | |
8854 | case 14: | |
8855 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8856 | break; | |
8857 | } | |
9b1e14f4 | 8858 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8859 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8860 | ||
190f68c5 | 8861 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8862 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8863 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8864 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8865 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8866 | else | |
8867 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8868 | ||
8869 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8870 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8871 | |
9b1e14f4 | 8872 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8873 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8874 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8875 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8876 | } |
8877 | } | |
8878 | ||
251ac862 DV |
8879 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8880 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8881 | struct dpll *reduced_clock) |
eb1cbe48 | 8882 | { |
f47709a9 | 8883 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8884 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8885 | u32 dpll; |
190f68c5 | 8886 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8887 | |
190f68c5 | 8888 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8889 | |
eb1cbe48 DV |
8890 | dpll = DPLL_VGA_MODE_DIS; |
8891 | ||
2d84d2b3 | 8892 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8893 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8894 | } else { | |
8895 | if (clock->p1 == 2) | |
8896 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8897 | else | |
8898 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8899 | if (clock->p2 == 4) | |
8900 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8901 | } | |
8902 | ||
171d1562 VS |
8903 | /* |
8904 | * Bspec: | |
8905 | * "[Almador Errata}: For the correct operation of the muxed DVO pins | |
8906 | * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, | |
8907 | * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock | |
8908 | * Enable) must be set to “1” in both the DPLL A Control Register | |
8909 | * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." | |
8910 | * | |
8911 | * For simplicity We simply keep both bits always enabled in | |
8912 | * both DPLLS. The spec says we should disable the DVO 2X clock | |
8913 | * when not needed, but this seems to work fine in practice. | |
8914 | */ | |
8915 | if (IS_I830(dev_priv) || | |
50a0bc90 | 8916 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
8917 | dpll |= DPLL_DVO_2X_MODE; |
8918 | ||
2d84d2b3 | 8919 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8920 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8921 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8922 | else | |
8923 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8924 | ||
8925 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8926 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8927 | } |
8928 | ||
e7fc3f90 | 8929 | static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) |
b0e77b9c | 8930 | { |
2225f3c6 | 8931 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
44fe7f35 ML |
8932 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8933 | enum pipe pipe = crtc->pipe; | |
8934 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
1326a92c | 8935 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
ba3f4d0a | 8936 | u32 crtc_vtotal, crtc_vblank_end; |
1caea6e9 | 8937 | int vsyncshift = 0; |
4d8a62ea DV |
8938 | |
8939 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8940 | * the hw state checker will get angry at the mismatch. */ | |
8941 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8942 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8943 | |
609aeaca | 8944 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8945 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8946 | crtc_vtotal -= 1; |
8947 | crtc_vblank_end -= 1; | |
609aeaca | 8948 | |
44fe7f35 | 8949 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8950 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8951 | else | |
8952 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8953 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8954 | if (vsyncshift < 0) |
8955 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8956 | } |
8957 | ||
6315b5d3 | 8958 | if (INTEL_GEN(dev_priv) > 3) |
dc008bf0 JN |
8959 | intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), |
8960 | vsyncshift); | |
8961 | ||
8962 | intel_de_write(dev_priv, HTOTAL(cpu_transcoder), | |
8963 | (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
8964 | intel_de_write(dev_priv, HBLANK(cpu_transcoder), | |
8965 | (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
8966 | intel_de_write(dev_priv, HSYNC(cpu_transcoder), | |
8967 | (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8968 | ||
8969 | intel_de_write(dev_priv, VTOTAL(cpu_transcoder), | |
8970 | (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); | |
8971 | intel_de_write(dev_priv, VBLANK(cpu_transcoder), | |
8972 | (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); | |
8973 | intel_de_write(dev_priv, VSYNC(cpu_transcoder), | |
8974 | (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
b0e77b9c | 8975 | |
b5e508d4 PZ |
8976 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8977 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8978 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8979 | * bits. */ | |
772c2a51 | 8980 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 | 8981 | (pipe == PIPE_B || pipe == PIPE_C)) |
dc008bf0 JN |
8982 | intel_de_write(dev_priv, VTOTAL(pipe), |
8983 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); | |
b5e508d4 | 8984 | |
bc58be60 JN |
8985 | } |
8986 | ||
44fe7f35 | 8987 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) |
bc58be60 | 8988 | { |
2225f3c6 | 8989 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
44fe7f35 ML |
8990 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8991 | enum pipe pipe = crtc->pipe; | |
bc58be60 | 8992 | |
b0e77b9c PZ |
8993 | /* pipesrc controls the size that is scaled from, which should |
8994 | * always be the user's requested size. | |
8995 | */ | |
dc008bf0 JN |
8996 | intel_de_write(dev_priv, PIPESRC(pipe), |
8997 | ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); | |
b0e77b9c PZ |
8998 | } |
8999 | ||
60a02311 VS |
9000 | static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) |
9001 | { | |
2225f3c6 | 9002 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
60a02311 VS |
9003 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
9004 | ||
9005 | if (IS_GEN(dev_priv, 2)) | |
9006 | return false; | |
9007 | ||
9008 | if (INTEL_GEN(dev_priv) >= 9 || | |
9009 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
dc008bf0 | 9010 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; |
60a02311 | 9011 | else |
dc008bf0 | 9012 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; |
60a02311 VS |
9013 | } |
9014 | ||
e7fc3f90 MN |
9015 | static void intel_get_transcoder_timings(struct intel_crtc *crtc, |
9016 | struct intel_crtc_state *pipe_config) | |
1bd1bd80 DV |
9017 | { |
9018 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9019 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 | 9020 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
ba3f4d0a | 9021 | u32 tmp; |
1bd1bd80 | 9022 | |
dc008bf0 | 9023 | tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); |
1326a92c ML |
9024 | pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
9025 | pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
3c23ed13 VK |
9026 | |
9027 | if (!transcoder_is_dsi(cpu_transcoder)) { | |
dc008bf0 | 9028 | tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); |
1326a92c | 9029 | pipe_config->hw.adjusted_mode.crtc_hblank_start = |
3c23ed13 | 9030 | (tmp & 0xffff) + 1; |
1326a92c | 9031 | pipe_config->hw.adjusted_mode.crtc_hblank_end = |
3c23ed13 VK |
9032 | ((tmp >> 16) & 0xffff) + 1; |
9033 | } | |
dc008bf0 | 9034 | tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); |
1326a92c ML |
9035 | pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
9036 | pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 9037 | |
dc008bf0 | 9038 | tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); |
1326a92c ML |
9039 | pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
9040 | pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
3c23ed13 VK |
9041 | |
9042 | if (!transcoder_is_dsi(cpu_transcoder)) { | |
dc008bf0 | 9043 | tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); |
1326a92c | 9044 | pipe_config->hw.adjusted_mode.crtc_vblank_start = |
3c23ed13 | 9045 | (tmp & 0xffff) + 1; |
1326a92c | 9046 | pipe_config->hw.adjusted_mode.crtc_vblank_end = |
3c23ed13 VK |
9047 | ((tmp >> 16) & 0xffff) + 1; |
9048 | } | |
dc008bf0 | 9049 | tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); |
1326a92c ML |
9050 | pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
9051 | pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 9052 | |
60a02311 | 9053 | if (intel_pipe_is_interlaced(pipe_config)) { |
1326a92c ML |
9054 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
9055 | pipe_config->hw.adjusted_mode.crtc_vtotal += 1; | |
9056 | pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 9057 | } |
bc58be60 JN |
9058 | } |
9059 | ||
9060 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
9061 | struct intel_crtc_state *pipe_config) | |
9062 | { | |
9063 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9064 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 9065 | u32 tmp; |
1bd1bd80 | 9066 | |
dc008bf0 | 9067 | tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); |
37327abd VS |
9068 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
9069 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
9070 | } |
9071 | ||
fdf73510 | 9072 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) |
84b046f3 | 9073 | { |
2225f3c6 | 9074 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 | 9075 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ba3f4d0a | 9076 | u32 pipeconf; |
84b046f3 | 9077 | |
9f11a9e4 | 9078 | pipeconf = 0; |
84b046f3 | 9079 | |
e56134bc VS |
9080 | /* we keep both pipes enabled on 830 */ |
9081 | if (IS_I830(dev_priv)) | |
dc008bf0 | 9082 | pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 9083 | |
fdf73510 | 9084 | if (crtc_state->double_wide) |
cf532bb2 | 9085 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 9086 | |
ff9ce46e | 9087 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
9088 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
9089 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 9090 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
fdf73510 | 9091 | if (crtc_state->dither && crtc_state->pipe_bpp != 30) |
ff9ce46e | 9092 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 9093 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 9094 | |
fdf73510 | 9095 | switch (crtc_state->pipe_bpp) { |
ff9ce46e DV |
9096 | case 18: |
9097 | pipeconf |= PIPECONF_6BPC; | |
9098 | break; | |
9099 | case 24: | |
9100 | pipeconf |= PIPECONF_8BPC; | |
9101 | break; | |
9102 | case 30: | |
9103 | pipeconf |= PIPECONF_10BPC; | |
9104 | break; | |
9105 | default: | |
9106 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
9107 | BUG(); | |
84b046f3 DV |
9108 | } |
9109 | } | |
9110 | ||
1326a92c | 9111 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 9112 | if (INTEL_GEN(dev_priv) < 4 || |
fdf73510 | 9113 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
9114 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
9115 | else | |
9116 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
27b680f9 | 9117 | } else { |
84b046f3 | 9118 | pipeconf |= PIPECONF_PROGRESSIVE; |
27b680f9 | 9119 | } |
84b046f3 | 9120 | |
920a14b2 | 9121 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
fdf73510 | 9122 | crtc_state->limited_color_range) |
9f11a9e4 | 9123 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 9124 | |
9d5441de VS |
9125 | pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); |
9126 | ||
cc7a4cff VS |
9127 | pipeconf |= PIPECONF_FRAME_START_DELAY(0); |
9128 | ||
dc008bf0 JN |
9129 | intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); |
9130 | intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); | |
84b046f3 DV |
9131 | } |
9132 | ||
81c97f52 ACO |
9133 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
9134 | struct intel_crtc_state *crtc_state) | |
9135 | { | |
9136 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9137 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9138 | const struct intel_limit *limit; |
81c97f52 ACO |
9139 | int refclk = 48000; |
9140 | ||
9141 | memset(&crtc_state->dpll_hw_state, 0, | |
9142 | sizeof(crtc_state->dpll_hw_state)); | |
9143 | ||
2d84d2b3 | 9144 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
9145 | if (intel_panel_use_ssc(dev_priv)) { |
9146 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9147 | drm_dbg_kms(&dev_priv->drm, |
9148 | "using SSC reference clock of %d kHz\n", | |
9149 | refclk); | |
81c97f52 ACO |
9150 | } |
9151 | ||
9152 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 9153 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
9154 | limit = &intel_limits_i8xx_dvo; |
9155 | } else { | |
9156 | limit = &intel_limits_i8xx_dac; | |
9157 | } | |
9158 | ||
9159 | if (!crtc_state->clock_set && | |
9160 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9161 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9162 | drm_err(&dev_priv->drm, |
9163 | "Couldn't find PLL settings for mode!\n"); | |
81c97f52 ACO |
9164 | return -EINVAL; |
9165 | } | |
9166 | ||
9167 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
9168 | ||
9169 | return 0; | |
9170 | } | |
9171 | ||
19ec6693 ACO |
9172 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
9173 | struct intel_crtc_state *crtc_state) | |
9174 | { | |
d2daff2c | 9175 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1b6f4958 | 9176 | const struct intel_limit *limit; |
19ec6693 ACO |
9177 | int refclk = 96000; |
9178 | ||
9179 | memset(&crtc_state->dpll_hw_state, 0, | |
9180 | sizeof(crtc_state->dpll_hw_state)); | |
9181 | ||
2d84d2b3 | 9182 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
9183 | if (intel_panel_use_ssc(dev_priv)) { |
9184 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9185 | drm_dbg_kms(&dev_priv->drm, |
9186 | "using SSC reference clock of %d kHz\n", | |
9187 | refclk); | |
19ec6693 ACO |
9188 | } |
9189 | ||
d2daff2c | 9190 | if (intel_is_dual_link_lvds(dev_priv)) |
19ec6693 ACO |
9191 | limit = &intel_limits_g4x_dual_channel_lvds; |
9192 | else | |
9193 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
9194 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
9195 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 9196 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 9197 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
9198 | limit = &intel_limits_g4x_sdvo; |
9199 | } else { | |
9200 | /* The option is for other outputs */ | |
9201 | limit = &intel_limits_i9xx_sdvo; | |
9202 | } | |
9203 | ||
9204 | if (!crtc_state->clock_set && | |
9205 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9206 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9207 | drm_err(&dev_priv->drm, |
9208 | "Couldn't find PLL settings for mode!\n"); | |
19ec6693 ACO |
9209 | return -EINVAL; |
9210 | } | |
9211 | ||
9212 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
9213 | ||
9214 | return 0; | |
9215 | } | |
9216 | ||
70e8aa21 ACO |
9217 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
9218 | struct intel_crtc_state *crtc_state) | |
9219 | { | |
9220 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9221 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9222 | const struct intel_limit *limit; |
70e8aa21 ACO |
9223 | int refclk = 96000; |
9224 | ||
9225 | memset(&crtc_state->dpll_hw_state, 0, | |
9226 | sizeof(crtc_state->dpll_hw_state)); | |
9227 | ||
2d84d2b3 | 9228 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
9229 | if (intel_panel_use_ssc(dev_priv)) { |
9230 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9231 | drm_dbg_kms(&dev_priv->drm, |
9232 | "using SSC reference clock of %d kHz\n", | |
9233 | refclk); | |
70e8aa21 ACO |
9234 | } |
9235 | ||
1d218220 | 9236 | limit = &pnv_limits_lvds; |
70e8aa21 | 9237 | } else { |
1d218220 | 9238 | limit = &pnv_limits_sdvo; |
70e8aa21 ACO |
9239 | } |
9240 | ||
9241 | if (!crtc_state->clock_set && | |
9242 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9243 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9244 | drm_err(&dev_priv->drm, |
9245 | "Couldn't find PLL settings for mode!\n"); | |
70e8aa21 ACO |
9246 | return -EINVAL; |
9247 | } | |
9248 | ||
9249 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
9250 | ||
9251 | return 0; | |
9252 | } | |
9253 | ||
190f68c5 ACO |
9254 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
9255 | struct intel_crtc_state *crtc_state) | |
79e53945 | 9256 | { |
c7653199 | 9257 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9258 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9259 | const struct intel_limit *limit; |
81c97f52 | 9260 | int refclk = 96000; |
79e53945 | 9261 | |
dd3cd74a ACO |
9262 | memset(&crtc_state->dpll_hw_state, 0, |
9263 | sizeof(crtc_state->dpll_hw_state)); | |
9264 | ||
2d84d2b3 | 9265 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
9266 | if (intel_panel_use_ssc(dev_priv)) { |
9267 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9268 | drm_dbg_kms(&dev_priv->drm, |
9269 | "using SSC reference clock of %d kHz\n", | |
9270 | refclk); | |
70e8aa21 | 9271 | } |
43565a06 | 9272 | |
70e8aa21 ACO |
9273 | limit = &intel_limits_i9xx_lvds; |
9274 | } else { | |
9275 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 9276 | } |
79e53945 | 9277 | |
70e8aa21 ACO |
9278 | if (!crtc_state->clock_set && |
9279 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9280 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9281 | drm_err(&dev_priv->drm, |
9282 | "Couldn't find PLL settings for mode!\n"); | |
70e8aa21 | 9283 | return -EINVAL; |
f47709a9 | 9284 | } |
7026d4ac | 9285 | |
81c97f52 | 9286 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 9287 | |
c8f7a0db | 9288 | return 0; |
f564048e EA |
9289 | } |
9290 | ||
65b3d6a9 ACO |
9291 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
9292 | struct intel_crtc_state *crtc_state) | |
9293 | { | |
9294 | int refclk = 100000; | |
1b6f4958 | 9295 | const struct intel_limit *limit = &intel_limits_chv; |
cd49f818 | 9296 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
65b3d6a9 ACO |
9297 | |
9298 | memset(&crtc_state->dpll_hw_state, 0, | |
9299 | sizeof(crtc_state->dpll_hw_state)); | |
9300 | ||
65b3d6a9 ACO |
9301 | if (!crtc_state->clock_set && |
9302 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9303 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 | 9304 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); |
65b3d6a9 ACO |
9305 | return -EINVAL; |
9306 | } | |
9307 | ||
9308 | chv_compute_dpll(crtc, crtc_state); | |
9309 | ||
9310 | return 0; | |
9311 | } | |
9312 | ||
9313 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
9314 | struct intel_crtc_state *crtc_state) | |
9315 | { | |
9316 | int refclk = 100000; | |
1b6f4958 | 9317 | const struct intel_limit *limit = &intel_limits_vlv; |
cd49f818 | 9318 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
65b3d6a9 ACO |
9319 | |
9320 | memset(&crtc_state->dpll_hw_state, 0, | |
9321 | sizeof(crtc_state->dpll_hw_state)); | |
9322 | ||
65b3d6a9 ACO |
9323 | if (!crtc_state->clock_set && |
9324 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9325 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 | 9326 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); |
65b3d6a9 ACO |
9327 | return -EINVAL; |
9328 | } | |
9329 | ||
9330 | vlv_compute_dpll(crtc, crtc_state); | |
9331 | ||
9332 | return 0; | |
9333 | } | |
9334 | ||
b7c8093f VS |
9335 | static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) |
9336 | { | |
9337 | if (IS_I830(dev_priv)) | |
9338 | return false; | |
9339 | ||
9340 | return INTEL_GEN(dev_priv) >= 4 || | |
9341 | IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); | |
9342 | } | |
9343 | ||
eac9c585 | 9344 | static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) |
2fa2fe9a | 9345 | { |
eac9c585 | 9346 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 9347 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ba3f4d0a | 9348 | u32 tmp; |
2fa2fe9a | 9349 | |
b7c8093f | 9350 | if (!i9xx_has_pfit(dev_priv)) |
dc9e7dec VS |
9351 | return; |
9352 | ||
dc008bf0 | 9353 | tmp = intel_de_read(dev_priv, PFIT_CONTROL); |
06922821 DV |
9354 | if (!(tmp & PFIT_ENABLE)) |
9355 | return; | |
2fa2fe9a | 9356 | |
06922821 | 9357 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 9358 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
9359 | if (crtc->pipe != PIPE_B) |
9360 | return; | |
2fa2fe9a DV |
9361 | } else { |
9362 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
9363 | return; | |
9364 | } | |
9365 | ||
eac9c585 VS |
9366 | crtc_state->gmch_pfit.control = tmp; |
9367 | crtc_state->gmch_pfit.pgm_ratios = | |
9368 | intel_de_read(dev_priv, PFIT_PGM_RATIOS); | |
2fa2fe9a DV |
9369 | } |
9370 | ||
acbec814 | 9371 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9372 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
9373 | { |
9374 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9375 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 9376 | enum pipe pipe = crtc->pipe; |
9e2c8475 | 9377 | struct dpll clock; |
acbec814 | 9378 | u32 mdiv; |
662c6ecb | 9379 | int refclk = 100000; |
acbec814 | 9380 | |
b521973b VS |
9381 | /* In case of DSI, DPLL will not be used */ |
9382 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
9383 | return; |
9384 | ||
221c7862 | 9385 | vlv_dpio_get(dev_priv); |
ab3c759a | 9386 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
221c7862 | 9387 | vlv_dpio_put(dev_priv); |
acbec814 JB |
9388 | |
9389 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
9390 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
9391 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
9392 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
9393 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
9394 | ||
dccbea3b | 9395 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
9396 | } |
9397 | ||
5724dbd1 DL |
9398 | static void |
9399 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
9400 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
9401 | { |
9402 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9403 | struct drm_i915_private *dev_priv = to_i915(dev); |
282e83ef VS |
9404 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
9405 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
eade6c89 | 9406 | enum pipe pipe; |
1ad292b5 | 9407 | u32 val, base, offset; |
1ad292b5 | 9408 | int fourcc, pixel_format; |
6761dd31 | 9409 | unsigned int aligned_height; |
b113d5ee | 9410 | struct drm_framebuffer *fb; |
1b842c89 | 9411 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 9412 | |
eade6c89 | 9413 | if (!plane->get_hw_state(plane, &pipe)) |
42a7b088 DL |
9414 | return; |
9415 | ||
e57291c2 | 9416 | drm_WARN_ON(dev, pipe != crtc->pipe); |
eade6c89 | 9417 | |
d9806c9f | 9418 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9419 | if (!intel_fb) { |
cd49f818 | 9420 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); |
1ad292b5 JB |
9421 | return; |
9422 | } | |
9423 | ||
1b842c89 DL |
9424 | fb = &intel_fb->base; |
9425 | ||
d2e9f5fc VS |
9426 | fb->dev = dev; |
9427 | ||
dc008bf0 | 9428 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
2924b8cc | 9429 | |
6315b5d3 | 9430 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 9431 | if (val & DISPPLANE_TILED) { |
49af449b | 9432 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 9433 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e | 9434 | } |
f43348a3 VS |
9435 | |
9436 | if (val & DISPPLANE_ROTATE_180) | |
9437 | plane_config->rotation = DRM_MODE_ROTATE_180; | |
18c5247e | 9438 | } |
1ad292b5 | 9439 | |
f43348a3 VS |
9440 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && |
9441 | val & DISPPLANE_MIRROR) | |
9442 | plane_config->rotation |= DRM_MODE_REFLECT_X; | |
9443 | ||
1ad292b5 | 9444 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
b35d63fa | 9445 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 9446 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 9447 | |
81894b2f | 9448 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
dc008bf0 JN |
9449 | offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); |
9450 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; | |
81894b2f | 9451 | } else if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 9452 | if (plane_config->tiling) |
dc008bf0 JN |
9453 | offset = intel_de_read(dev_priv, |
9454 | DSPTILEOFF(i9xx_plane)); | |
1ad292b5 | 9455 | else |
dc008bf0 JN |
9456 | offset = intel_de_read(dev_priv, |
9457 | DSPLINOFF(i9xx_plane)); | |
9458 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; | |
1ad292b5 | 9459 | } else { |
dc008bf0 | 9460 | base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); |
1ad292b5 JB |
9461 | } |
9462 | plane_config->base = base; | |
9463 | ||
dc008bf0 | 9464 | val = intel_de_read(dev_priv, PIPESRC(pipe)); |
b113d5ee DL |
9465 | fb->width = ((val >> 16) & 0xfff) + 1; |
9466 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 | 9467 | |
dc008bf0 | 9468 | val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); |
b113d5ee | 9469 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 9470 | |
d88c4afd | 9471 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 9472 | |
f37b5c2b | 9473 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 9474 | |
cd49f818 WK |
9475 | drm_dbg_kms(&dev_priv->drm, |
9476 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9477 | crtc->base.name, plane->base.name, fb->width, fb->height, | |
9478 | fb->format->cpp[0] * 8, base, fb->pitches[0], | |
9479 | plane_config->size); | |
1ad292b5 | 9480 | |
2d14030b | 9481 | plane_config->fb = intel_fb; |
1ad292b5 JB |
9482 | } |
9483 | ||
70b23a98 | 9484 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9485 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
9486 | { |
9487 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9488 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 9489 | enum pipe pipe = crtc->pipe; |
70b23a98 | 9490 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9e2c8475 | 9491 | struct dpll clock; |
0d7b6b11 | 9492 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
9493 | int refclk = 100000; |
9494 | ||
b521973b VS |
9495 | /* In case of DSI, DPLL will not be used */ |
9496 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
9497 | return; | |
9498 | ||
221c7862 | 9499 | vlv_dpio_get(dev_priv); |
70b23a98 VS |
9500 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
9501 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
9502 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
9503 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 9504 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
221c7862 | 9505 | vlv_dpio_put(dev_priv); |
70b23a98 VS |
9506 | |
9507 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
9508 | clock.m2 = (pll_dw0 & 0xff) << 22; |
9509 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
9510 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
9511 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
9512 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
9513 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
9514 | ||
dccbea3b | 9515 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
9516 | } |
9517 | ||
b10d1173 VS |
9518 | static enum intel_output_format |
9519 | bdw_get_pipemisc_output_format(struct intel_crtc *crtc) | |
33b7f3ee SS |
9520 | { |
9521 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
b10d1173 VS |
9522 | u32 tmp; |
9523 | ||
dc008bf0 | 9524 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); |
b10d1173 VS |
9525 | |
9526 | if (tmp & PIPEMISC_YUV420_ENABLE) { | |
9527 | /* We support 4:2:0 in full blend mode only */ | |
e57291c2 PB |
9528 | drm_WARN_ON(&dev_priv->drm, |
9529 | (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); | |
33b7f3ee | 9530 | |
b10d1173 VS |
9531 | return INTEL_OUTPUT_FORMAT_YCBCR420; |
9532 | } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { | |
9533 | return INTEL_OUTPUT_FORMAT_YCBCR444; | |
9534 | } else { | |
9535 | return INTEL_OUTPUT_FORMAT_RGB; | |
9536 | } | |
33b7f3ee SS |
9537 | } |
9538 | ||
5f29ab23 VS |
9539 | static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) |
9540 | { | |
2225f3c6 | 9541 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
5f29ab23 VS |
9542 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
9543 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
9544 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
9545 | u32 tmp; | |
9546 | ||
dc008bf0 | 9547 | tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
5f29ab23 VS |
9548 | |
9549 | if (tmp & DISPPLANE_GAMMA_ENABLE) | |
9550 | crtc_state->gamma_enable = true; | |
8271b2ef VS |
9551 | |
9552 | if (!HAS_GMCH(dev_priv) && | |
9553 | tmp & DISPPLANE_PIPE_CSC_ENABLE) | |
9554 | crtc_state->csc_enable = true; | |
5f29ab23 VS |
9555 | } |
9556 | ||
0e8ffe1b | 9557 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9558 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9559 | { |
6315b5d3 | 9560 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9561 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 9562 | intel_wakeref_t wakeref; |
ba3f4d0a | 9563 | u32 tmp; |
1729050e | 9564 | bool ret; |
0e8ffe1b | 9565 | |
1729050e | 9566 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
0e6e0be4 CW |
9567 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
9568 | if (!wakeref) | |
b5482bd0 ID |
9569 | return false; |
9570 | ||
d9facae6 | 9571 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
e143a21c | 9572 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9573 | pipe_config->shared_dpll = NULL; |
eccb140b | 9574 | |
1729050e ID |
9575 | ret = false; |
9576 | ||
dc008bf0 | 9577 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); |
0e8ffe1b | 9578 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 9579 | goto out; |
0e8ffe1b | 9580 | |
9beb5fea TU |
9581 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
9582 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
9583 | switch (tmp & PIPECONF_BPC_MASK) { |
9584 | case PIPECONF_6BPC: | |
9585 | pipe_config->pipe_bpp = 18; | |
9586 | break; | |
9587 | case PIPECONF_8BPC: | |
9588 | pipe_config->pipe_bpp = 24; | |
9589 | break; | |
9590 | case PIPECONF_10BPC: | |
9591 | pipe_config->pipe_bpp = 30; | |
9592 | break; | |
9593 | default: | |
9594 | break; | |
9595 | } | |
9596 | } | |
9597 | ||
920a14b2 | 9598 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 9599 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
9600 | pipe_config->limited_color_range = true; |
9601 | ||
9d5441de VS |
9602 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >> |
9603 | PIPECONF_GAMMA_MODE_SHIFT; | |
9604 | ||
9fdfb8e7 | 9605 | if (IS_CHERRYVIEW(dev_priv)) |
dc008bf0 JN |
9606 | pipe_config->cgm_mode = intel_de_read(dev_priv, |
9607 | CGM_PIPE_MODE(crtc->pipe)); | |
9fdfb8e7 | 9608 | |
5f29ab23 | 9609 | i9xx_get_pipe_color_config(pipe_config); |
3633e511 | 9610 | intel_color_get_config(pipe_config); |
5f29ab23 | 9611 | |
6315b5d3 | 9612 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
9613 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
9614 | ||
e7fc3f90 | 9615 | intel_get_transcoder_timings(crtc, pipe_config); |
bc58be60 | 9616 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9617 | |
eac9c585 | 9618 | i9xx_get_pfit_config(pipe_config); |
2fa2fe9a | 9619 | |
6315b5d3 | 9620 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 9621 | /* No way to read it out on pipes B and C */ |
920a14b2 | 9622 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
9623 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
9624 | else | |
dc008bf0 | 9625 | tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); |
6c49f241 DV |
9626 | pipe_config->pixel_multiplier = |
9627 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
9628 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 9629 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 9630 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 9631 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
dc008bf0 | 9632 | tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); |
6c49f241 DV |
9633 | pipe_config->pixel_multiplier = |
9634 | ((tmp & SDVO_MULTIPLIER_MASK) | |
9635 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
9636 | } else { | |
9637 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
9638 | * port and will be fixed up in the encoder->get_config | |
9639 | * function. */ | |
9640 | pipe_config->pixel_multiplier = 1; | |
9641 | } | |
dc008bf0 JN |
9642 | pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, |
9643 | DPLL(crtc->pipe)); | |
920a14b2 | 9644 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
dc008bf0 JN |
9645 | pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, |
9646 | FP0(crtc->pipe)); | |
9647 | pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, | |
9648 | FP1(crtc->pipe)); | |
165e901c VS |
9649 | } else { |
9650 | /* Mask out read-only status bits. */ | |
9651 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
9652 | DPLL_PORTC_READY_MASK | | |
9653 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 9654 | } |
6c49f241 | 9655 | |
920a14b2 | 9656 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 9657 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 9658 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
9659 | vlv_crtc_clock_get(crtc, pipe_config); |
9660 | else | |
9661 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 9662 | |
0f64614d VS |
9663 | /* |
9664 | * Normally the dotclock is filled in by the encoder .get_config() | |
9665 | * but in case the pipe is enabled w/o any ports we need a sane | |
9666 | * default. | |
9667 | */ | |
1326a92c | 9668 | pipe_config->hw.adjusted_mode.crtc_clock = |
0f64614d VS |
9669 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
9670 | ||
1729050e ID |
9671 | ret = true; |
9672 | ||
9673 | out: | |
0e6e0be4 | 9674 | intel_display_power_put(dev_priv, power_domain, wakeref); |
1729050e ID |
9675 | |
9676 | return ret; | |
0e8ffe1b DV |
9677 | } |
9678 | ||
9eae5e27 | 9679 | static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 9680 | { |
13d83a67 | 9681 | struct intel_encoder *encoder; |
1c1a24d2 | 9682 | int i; |
74cfd7ac | 9683 | u32 val, final; |
13d83a67 | 9684 | bool has_lvds = false; |
199e5d79 | 9685 | bool has_cpu_edp = false; |
199e5d79 | 9686 | bool has_panel = false; |
99eb6a01 KP |
9687 | bool has_ck505 = false; |
9688 | bool can_ssc = false; | |
1c1a24d2 | 9689 | bool using_ssc_source = false; |
13d83a67 JB |
9690 | |
9691 | /* We need to take the global config into account */ | |
c39055b0 | 9692 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
9693 | switch (encoder->type) { |
9694 | case INTEL_OUTPUT_LVDS: | |
9695 | has_panel = true; | |
9696 | has_lvds = true; | |
9697 | break; | |
9698 | case INTEL_OUTPUT_EDP: | |
9699 | has_panel = true; | |
8f4f2797 | 9700 | if (encoder->port == PORT_A) |
199e5d79 KP |
9701 | has_cpu_edp = true; |
9702 | break; | |
6847d71b PZ |
9703 | default: |
9704 | break; | |
13d83a67 JB |
9705 | } |
9706 | } | |
9707 | ||
6e266956 | 9708 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 9709 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
9710 | can_ssc = has_ck505; |
9711 | } else { | |
9712 | has_ck505 = false; | |
9713 | can_ssc = true; | |
9714 | } | |
9715 | ||
1c1a24d2 | 9716 | /* Check if any DPLLs are using the SSC source */ |
353ad959 | 9717 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { |
dc008bf0 | 9718 | u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); |
1c1a24d2 L |
9719 | |
9720 | if (!(temp & DPLL_VCO_ENABLE)) | |
9721 | continue; | |
9722 | ||
9723 | if ((temp & PLL_REF_INPUT_MASK) == | |
9724 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
9725 | using_ssc_source = true; | |
9726 | break; | |
9727 | } | |
9728 | } | |
9729 | ||
cd49f818 WK |
9730 | drm_dbg_kms(&dev_priv->drm, |
9731 | "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
9732 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
9733 | |
9734 | /* Ironlake: try to setup display ref clock before DPLL | |
9735 | * enabling. This is only under driver's control after | |
9736 | * PCH B stepping, previous chipset stepping should be | |
9737 | * ignoring this setting. | |
9738 | */ | |
dc008bf0 | 9739 | val = intel_de_read(dev_priv, PCH_DREF_CONTROL); |
74cfd7ac CW |
9740 | |
9741 | /* As we must carefully and slowly disable/enable each source in turn, | |
9742 | * compute the final state we want first and check if we need to | |
9743 | * make any changes at all. | |
9744 | */ | |
9745 | final = val; | |
9746 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
9747 | if (has_ck505) | |
9748 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
9749 | else | |
9750 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
9751 | ||
8c07eb68 | 9752 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 9753 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 9754 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
9755 | |
9756 | if (has_panel) { | |
9757 | final |= DREF_SSC_SOURCE_ENABLE; | |
9758 | ||
9759 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9760 | final |= DREF_SSC1_ENABLE; | |
9761 | ||
9762 | if (has_cpu_edp) { | |
9763 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9764 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9765 | else | |
9766 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9767 | } else | |
9768 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9769 | } else if (using_ssc_source) { |
9770 | final |= DREF_SSC_SOURCE_ENABLE; | |
9771 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9772 | } |
9773 | ||
9774 | if (final == val) | |
9775 | return; | |
9776 | ||
13d83a67 | 9777 | /* Always enable nonspread source */ |
74cfd7ac | 9778 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9779 | |
99eb6a01 | 9780 | if (has_ck505) |
74cfd7ac | 9781 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9782 | else |
74cfd7ac | 9783 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9784 | |
199e5d79 | 9785 | if (has_panel) { |
74cfd7ac CW |
9786 | val &= ~DREF_SSC_SOURCE_MASK; |
9787 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9788 | |
199e5d79 | 9789 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9790 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
cd49f818 | 9791 | drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n"); |
74cfd7ac | 9792 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9793 | } else |
74cfd7ac | 9794 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9795 | |
9796 | /* Get SSC going before enabling the outputs */ | |
dc008bf0 JN |
9797 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9798 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9799 | udelay(200); |
9800 | ||
74cfd7ac | 9801 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9802 | |
9803 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9804 | if (has_cpu_edp) { |
99eb6a01 | 9805 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
cd49f818 WK |
9806 | drm_dbg_kms(&dev_priv->drm, |
9807 | "Using SSC on eDP\n"); | |
74cfd7ac | 9808 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9809 | } else |
74cfd7ac | 9810 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9811 | } else |
74cfd7ac | 9812 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9813 | |
dc008bf0 JN |
9814 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9815 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9816 | udelay(200); |
9817 | } else { | |
cd49f818 | 9818 | drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); |
199e5d79 | 9819 | |
74cfd7ac | 9820 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9821 | |
9822 | /* Turn off CPU output */ | |
74cfd7ac | 9823 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9824 | |
dc008bf0 JN |
9825 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9826 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9827 | udelay(200); |
9828 | ||
1c1a24d2 | 9829 | if (!using_ssc_source) { |
cd49f818 | 9830 | drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); |
199e5d79 | 9831 | |
1c1a24d2 L |
9832 | /* Turn off the SSC source */ |
9833 | val &= ~DREF_SSC_SOURCE_MASK; | |
9834 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9835 | |
1c1a24d2 L |
9836 | /* Turn off SSC1 */ |
9837 | val &= ~DREF_SSC1_ENABLE; | |
9838 | ||
dc008bf0 JN |
9839 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9840 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
1c1a24d2 L |
9841 | udelay(200); |
9842 | } | |
13d83a67 | 9843 | } |
74cfd7ac CW |
9844 | |
9845 | BUG_ON(val != final); | |
13d83a67 JB |
9846 | } |
9847 | ||
f31f2d55 | 9848 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9849 | { |
ba3f4d0a | 9850 | u32 tmp; |
dde86e2d | 9851 | |
dc008bf0 | 9852 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); |
0ff066a9 | 9853 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
dc008bf0 | 9854 | intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); |
dde86e2d | 9855 | |
dc008bf0 | 9856 | if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & |
cf3598c2 | 9857 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
cd49f818 | 9858 | drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); |
dde86e2d | 9859 | |
dc008bf0 | 9860 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); |
0ff066a9 | 9861 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
dc008bf0 | 9862 | intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); |
dde86e2d | 9863 | |
dc008bf0 | 9864 | if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & |
cf3598c2 | 9865 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
cd49f818 | 9866 | drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9867 | } |
9868 | ||
9869 | /* WaMPhyProgramming:hsw */ | |
9870 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9871 | { | |
ba3f4d0a | 9872 | u32 tmp; |
dde86e2d PZ |
9873 | |
9874 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9875 | tmp &= ~(0xFF << 24); | |
9876 | tmp |= (0x12 << 24); | |
9877 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9878 | ||
dde86e2d PZ |
9879 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9880 | tmp |= (1 << 11); | |
9881 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9882 | ||
9883 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9884 | tmp |= (1 << 11); | |
9885 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9886 | ||
dde86e2d PZ |
9887 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9888 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9889 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9890 | ||
9891 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9892 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9893 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9894 | ||
0ff066a9 PZ |
9895 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9896 | tmp &= ~(7 << 13); | |
9897 | tmp |= (5 << 13); | |
9898 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9899 | |
0ff066a9 PZ |
9900 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9901 | tmp &= ~(7 << 13); | |
9902 | tmp |= (5 << 13); | |
9903 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9904 | |
9905 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9906 | tmp &= ~0xFF; | |
9907 | tmp |= 0x1C; | |
9908 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9909 | ||
9910 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9911 | tmp &= ~0xFF; | |
9912 | tmp |= 0x1C; | |
9913 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9914 | ||
9915 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9916 | tmp &= ~(0xFF << 16); | |
9917 | tmp |= (0x1C << 16); | |
9918 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9919 | ||
9920 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9921 | tmp &= ~(0xFF << 16); | |
9922 | tmp |= (0x1C << 16); | |
9923 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9924 | ||
0ff066a9 PZ |
9925 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9926 | tmp |= (1 << 27); | |
9927 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9928 | |
0ff066a9 PZ |
9929 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9930 | tmp |= (1 << 27); | |
9931 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9932 | |
0ff066a9 PZ |
9933 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9934 | tmp &= ~(0xF << 28); | |
9935 | tmp |= (4 << 28); | |
9936 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9937 | |
0ff066a9 PZ |
9938 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9939 | tmp &= ~(0xF << 28); | |
9940 | tmp |= (4 << 28); | |
9941 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9942 | } |
9943 | ||
2fa86a1f PZ |
9944 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9945 | * Programming" based on the parameters passed: | |
9946 | * - Sequence to enable CLKOUT_DP | |
9947 | * - Sequence to enable CLKOUT_DP without spread | |
9948 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9949 | */ | |
c39055b0 ACO |
9950 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
9951 | bool with_spread, bool with_fdi) | |
f31f2d55 | 9952 | { |
ba3f4d0a | 9953 | u32 reg, tmp; |
2fa86a1f | 9954 | |
e57291c2 PB |
9955 | if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, |
9956 | "FDI requires downspread\n")) | |
2fa86a1f | 9957 | with_spread = true; |
e57291c2 PB |
9958 | if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && |
9959 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9960 | with_fdi = false; |
f31f2d55 | 9961 | |
a580516d | 9962 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9963 | |
9964 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9965 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9966 | tmp |= SBI_SSCCTL_PATHALT; | |
9967 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9968 | ||
9969 | udelay(24); | |
9970 | ||
2fa86a1f PZ |
9971 | if (with_spread) { |
9972 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9973 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9974 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9975 | |
2fa86a1f PZ |
9976 | if (with_fdi) { |
9977 | lpt_reset_fdi_mphy(dev_priv); | |
9978 | lpt_program_fdi_mphy(dev_priv); | |
9979 | } | |
9980 | } | |
dde86e2d | 9981 | |
4f8036a2 | 9982 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9983 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9984 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9985 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9986 | |
a580516d | 9987 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9988 | } |
9989 | ||
47701c3b | 9990 | /* Sequence to disable CLKOUT_DP */ |
46034d2b | 9991 | void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 9992 | { |
ba3f4d0a | 9993 | u32 reg, tmp; |
47701c3b | 9994 | |
a580516d | 9995 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9996 | |
4f8036a2 | 9997 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9998 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9999 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
10000 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
10001 | ||
10002 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
10003 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
10004 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
10005 | tmp |= SBI_SSCCTL_PATHALT; | |
10006 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
10007 | udelay(32); | |
10008 | } | |
10009 | tmp |= SBI_SSCCTL_DISABLE; | |
10010 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
10011 | } | |
10012 | ||
a580516d | 10013 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
10014 | } |
10015 | ||
f7be2c21 VS |
10016 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
10017 | ||
ba3f4d0a | 10018 | static const u16 sscdivintphase[] = { |
f7be2c21 VS |
10019 | [BEND_IDX( 50)] = 0x3B23, |
10020 | [BEND_IDX( 45)] = 0x3B23, | |
10021 | [BEND_IDX( 40)] = 0x3C23, | |
10022 | [BEND_IDX( 35)] = 0x3C23, | |
10023 | [BEND_IDX( 30)] = 0x3D23, | |
10024 | [BEND_IDX( 25)] = 0x3D23, | |
10025 | [BEND_IDX( 20)] = 0x3E23, | |
10026 | [BEND_IDX( 15)] = 0x3E23, | |
10027 | [BEND_IDX( 10)] = 0x3F23, | |
10028 | [BEND_IDX( 5)] = 0x3F23, | |
10029 | [BEND_IDX( 0)] = 0x0025, | |
10030 | [BEND_IDX( -5)] = 0x0025, | |
10031 | [BEND_IDX(-10)] = 0x0125, | |
10032 | [BEND_IDX(-15)] = 0x0125, | |
10033 | [BEND_IDX(-20)] = 0x0225, | |
10034 | [BEND_IDX(-25)] = 0x0225, | |
10035 | [BEND_IDX(-30)] = 0x0325, | |
10036 | [BEND_IDX(-35)] = 0x0325, | |
10037 | [BEND_IDX(-40)] = 0x0425, | |
10038 | [BEND_IDX(-45)] = 0x0425, | |
10039 | [BEND_IDX(-50)] = 0x0525, | |
10040 | }; | |
10041 | ||
10042 | /* | |
10043 | * Bend CLKOUT_DP | |
10044 | * steps -50 to 50 inclusive, in steps of 5 | |
10045 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
10046 | * change in clock period = -(steps / 10) * 5.787 ps | |
10047 | */ | |
10048 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
10049 | { | |
ba3f4d0a | 10050 | u32 tmp; |
f7be2c21 VS |
10051 | int idx = BEND_IDX(steps); |
10052 | ||
e57291c2 | 10053 | if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) |
f7be2c21 VS |
10054 | return; |
10055 | ||
e57291c2 | 10056 | if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) |
f7be2c21 VS |
10057 | return; |
10058 | ||
10059 | mutex_lock(&dev_priv->sb_lock); | |
10060 | ||
10061 | if (steps % 10 != 0) | |
10062 | tmp = 0xAAAAAAAB; | |
10063 | else | |
10064 | tmp = 0x00000000; | |
10065 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
10066 | ||
10067 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
10068 | tmp &= 0xffff0000; | |
10069 | tmp |= sscdivintphase[idx]; | |
10070 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
10071 | ||
10072 | mutex_unlock(&dev_priv->sb_lock); | |
10073 | } | |
10074 | ||
10075 | #undef BEND_IDX | |
10076 | ||
b16c7ed9 VS |
10077 | static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) |
10078 | { | |
dc008bf0 JN |
10079 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
10080 | u32 ctl = intel_de_read(dev_priv, SPLL_CTL); | |
b16c7ed9 VS |
10081 | |
10082 | if ((ctl & SPLL_PLL_ENABLE) == 0) | |
10083 | return false; | |
10084 | ||
4a95e36f | 10085 | if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC && |
b16c7ed9 VS |
10086 | (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) |
10087 | return true; | |
10088 | ||
10089 | if (IS_BROADWELL(dev_priv) && | |
4a95e36f | 10090 | (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW) |
b16c7ed9 VS |
10091 | return true; |
10092 | ||
10093 | return false; | |
10094 | } | |
10095 | ||
10096 | static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, | |
10097 | enum intel_dpll_id id) | |
10098 | { | |
dc008bf0 JN |
10099 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
10100 | u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); | |
b16c7ed9 VS |
10101 | |
10102 | if ((ctl & WRPLL_PLL_ENABLE) == 0) | |
10103 | return false; | |
10104 | ||
4a95e36f | 10105 | if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC) |
b16c7ed9 VS |
10106 | return true; |
10107 | ||
10108 | if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) && | |
4a95e36f | 10109 | (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW && |
b16c7ed9 VS |
10110 | (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) |
10111 | return true; | |
10112 | ||
10113 | return false; | |
10114 | } | |
10115 | ||
c39055b0 | 10116 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 10117 | { |
bf8fa3d3 | 10118 | struct intel_encoder *encoder; |
b16c7ed9 | 10119 | bool has_fdi = false; |
bf8fa3d3 | 10120 | |
c39055b0 | 10121 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
10122 | switch (encoder->type) { |
10123 | case INTEL_OUTPUT_ANALOG: | |
b16c7ed9 | 10124 | has_fdi = true; |
bf8fa3d3 | 10125 | break; |
6847d71b PZ |
10126 | default: |
10127 | break; | |
bf8fa3d3 PZ |
10128 | } |
10129 | } | |
10130 | ||
b16c7ed9 VS |
10131 | /* |
10132 | * The BIOS may have decided to use the PCH SSC | |
10133 | * reference so we must not disable it until the | |
10134 | * relevant PLLs have stopped relying on it. We'll | |
10135 | * just leave the PCH SSC reference enabled in case | |
10136 | * any active PLL is using it. It will get disabled | |
10137 | * after runtime suspend if we don't have FDI. | |
10138 | * | |
10139 | * TODO: Move the whole reference clock handling | |
10140 | * to the modeset sequence proper so that we can | |
10141 | * actually enable/disable/reconfigure these things | |
10142 | * safely. To do that we need to introduce a real | |
10143 | * clock hierarchy. That would also allow us to do | |
10144 | * clock bending finally. | |
10145 | */ | |
dd5279c7 VS |
10146 | dev_priv->pch_ssc_use = 0; |
10147 | ||
b16c7ed9 | 10148 | if (spll_uses_pch_ssc(dev_priv)) { |
cd49f818 | 10149 | drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n"); |
dd5279c7 | 10150 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); |
b16c7ed9 VS |
10151 | } |
10152 | ||
10153 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { | |
cd49f818 | 10154 | drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n"); |
dd5279c7 | 10155 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); |
b16c7ed9 VS |
10156 | } |
10157 | ||
10158 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { | |
cd49f818 | 10159 | drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n"); |
dd5279c7 | 10160 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); |
b16c7ed9 VS |
10161 | } |
10162 | ||
dd5279c7 | 10163 | if (dev_priv->pch_ssc_use) |
b16c7ed9 VS |
10164 | return; |
10165 | ||
10166 | if (has_fdi) { | |
c39055b0 ACO |
10167 | lpt_bend_clkout_dp(dev_priv, 0); |
10168 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 10169 | } else { |
c39055b0 | 10170 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 10171 | } |
bf8fa3d3 PZ |
10172 | } |
10173 | ||
dde86e2d PZ |
10174 | /* |
10175 | * Initialize reference clocks when the driver loads | |
10176 | */ | |
c39055b0 | 10177 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 10178 | { |
6e266956 | 10179 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
9eae5e27 | 10180 | ilk_init_pch_refclk(dev_priv); |
6e266956 | 10181 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 10182 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
10183 | } |
10184 | ||
9eae5e27 | 10185 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) |
79e53945 | 10186 | { |
2225f3c6 | 10187 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 ML |
10188 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10189 | enum pipe pipe = crtc->pipe; | |
ba3f4d0a | 10190 | u32 val; |
c8203565 | 10191 | |
78114071 | 10192 | val = 0; |
c8203565 | 10193 | |
fdf73510 | 10194 | switch (crtc_state->pipe_bpp) { |
c8203565 | 10195 | case 18: |
dfd07d72 | 10196 | val |= PIPECONF_6BPC; |
c8203565 PZ |
10197 | break; |
10198 | case 24: | |
dfd07d72 | 10199 | val |= PIPECONF_8BPC; |
c8203565 PZ |
10200 | break; |
10201 | case 30: | |
dfd07d72 | 10202 | val |= PIPECONF_10BPC; |
c8203565 PZ |
10203 | break; |
10204 | case 36: | |
dfd07d72 | 10205 | val |= PIPECONF_12BPC; |
c8203565 PZ |
10206 | break; |
10207 | default: | |
cc769b62 PZ |
10208 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
10209 | BUG(); | |
c8203565 PZ |
10210 | } |
10211 | ||
fdf73510 | 10212 | if (crtc_state->dither) |
c8203565 PZ |
10213 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
10214 | ||
1326a92c | 10215 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
10216 | val |= PIPECONF_INTERLACED_ILK; |
10217 | else | |
10218 | val |= PIPECONF_PROGRESSIVE; | |
10219 | ||
d1844606 VS |
10220 | /* |
10221 | * This would end up with an odd purple hue over | |
10222 | * the entire display. Make sure we don't do it. | |
10223 | */ | |
e57291c2 PB |
10224 | drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && |
10225 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); | |
d1844606 | 10226 | |
90f8ed85 VS |
10227 | if (crtc_state->limited_color_range && |
10228 | !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) | |
3685a8f3 | 10229 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 10230 | |
d1844606 VS |
10231 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) |
10232 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; | |
10233 | ||
9d5441de VS |
10234 | val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); |
10235 | ||
cc7a4cff VS |
10236 | val |= PIPECONF_FRAME_START_DELAY(0); |
10237 | ||
dc008bf0 JN |
10238 | intel_de_write(dev_priv, PIPECONF(pipe), val); |
10239 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
c8203565 PZ |
10240 | } |
10241 | ||
1e98f88c | 10242 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) |
ee2b0b38 | 10243 | { |
2225f3c6 | 10244 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 ML |
10245 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10246 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
391bf048 | 10247 | u32 val = 0; |
ee2b0b38 | 10248 | |
fdf73510 | 10249 | if (IS_HASWELL(dev_priv) && crtc_state->dither) |
ee2b0b38 PZ |
10250 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
10251 | ||
1326a92c | 10252 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
10253 | val |= PIPECONF_INTERLACED_ILK; |
10254 | else | |
10255 | val |= PIPECONF_PROGRESSIVE; | |
10256 | ||
ac0f01ce VS |
10257 | if (IS_HASWELL(dev_priv) && |
10258 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
10259 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; | |
10260 | ||
dc008bf0 JN |
10261 | intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); |
10262 | intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); | |
391bf048 JN |
10263 | } |
10264 | ||
9b11215e | 10265 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) |
391bf048 | 10266 | { |
2225f3c6 | 10267 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
9b11215e VS |
10268 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10269 | u32 val = 0; | |
756f85cf | 10270 | |
9b11215e VS |
10271 | switch (crtc_state->pipe_bpp) { |
10272 | case 18: | |
10273 | val |= PIPEMISC_DITHER_6_BPC; | |
10274 | break; | |
10275 | case 24: | |
10276 | val |= PIPEMISC_DITHER_8_BPC; | |
10277 | break; | |
10278 | case 30: | |
10279 | val |= PIPEMISC_DITHER_10_BPC; | |
10280 | break; | |
10281 | case 36: | |
10282 | val |= PIPEMISC_DITHER_12_BPC; | |
10283 | break; | |
10284 | default: | |
10285 | MISSING_CASE(crtc_state->pipe_bpp); | |
10286 | break; | |
10287 | } | |
756f85cf | 10288 | |
9b11215e VS |
10289 | if (crtc_state->dither) |
10290 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
756f85cf | 10291 | |
9b11215e VS |
10292 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
10293 | crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) | |
10294 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
8c79f844 | 10295 | |
9b11215e VS |
10296 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
10297 | val |= PIPEMISC_YUV420_ENABLE | | |
10298 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
b22ca995 | 10299 | |
09b25812 | 10300 | if (INTEL_GEN(dev_priv) >= 11 && |
b7ffc4a8 VS |
10301 | (crtc_state->active_planes & ~(icl_hdr_plane_mask() | |
10302 | BIT(PLANE_CURSOR))) == 0) | |
09b25812 VS |
10303 | val |= PIPEMISC_HDR_MODE_PRECISION; |
10304 | ||
041be481 VS |
10305 | if (INTEL_GEN(dev_priv) >= 12) |
10306 | val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; | |
10307 | ||
dc008bf0 | 10308 | intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); |
ee2b0b38 PZ |
10309 | } |
10310 | ||
8ae89743 VK |
10311 | int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) |
10312 | { | |
10313 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10314 | u32 tmp; | |
10315 | ||
dc008bf0 | 10316 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); |
8ae89743 VK |
10317 | |
10318 | switch (tmp & PIPEMISC_DITHER_BPC_MASK) { | |
10319 | case PIPEMISC_DITHER_6_BPC: | |
10320 | return 18; | |
10321 | case PIPEMISC_DITHER_8_BPC: | |
10322 | return 24; | |
10323 | case PIPEMISC_DITHER_10_BPC: | |
10324 | return 30; | |
10325 | case PIPEMISC_DITHER_12_BPC: | |
10326 | return 36; | |
10327 | default: | |
10328 | MISSING_CASE(tmp); | |
10329 | return 0; | |
10330 | } | |
10331 | } | |
10332 | ||
9eae5e27 | 10333 | int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) |
d4b1931c PZ |
10334 | { |
10335 | /* | |
10336 | * Account for spread spectrum to avoid | |
10337 | * oversubscribing the link. Max center spread | |
10338 | * is 2.5%; use 5% for safety's sake. | |
10339 | */ | |
10340 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 10341 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
10342 | } |
10343 | ||
9eae5e27 | 10344 | static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 10345 | { |
7429e9d4 | 10346 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
10347 | } |
10348 | ||
9eae5e27 LDM |
10349 | static void ilk_compute_dpll(struct intel_crtc *crtc, |
10350 | struct intel_crtc_state *crtc_state, | |
10351 | struct dpll *reduced_clock) | |
79e53945 | 10352 | { |
d2daff2c | 10353 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b75ca6f6 | 10354 | u32 dpll, fp, fp2; |
3d6e9ee0 | 10355 | int factor; |
79e53945 | 10356 | |
c1858123 | 10357 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 10358 | factor = 21; |
3d6e9ee0 | 10359 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 10360 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 10361 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
d2daff2c VS |
10362 | (HAS_PCH_IBX(dev_priv) && |
10363 | intel_is_dual_link_lvds(dev_priv))) | |
8febb297 | 10364 | factor = 25; |
27b680f9 | 10365 | } else if (crtc_state->sdvo_tv_clock) { |
8febb297 | 10366 | factor = 20; |
27b680f9 | 10367 | } |
c1858123 | 10368 | |
b75ca6f6 ACO |
10369 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
10370 | ||
9eae5e27 | 10371 | if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
10372 | fp |= FP_CB_TUNE; |
10373 | ||
10374 | if (reduced_clock) { | |
10375 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 10376 | |
b75ca6f6 ACO |
10377 | if (reduced_clock->m < factor * reduced_clock->n) |
10378 | fp2 |= FP_CB_TUNE; | |
10379 | } else { | |
10380 | fp2 = fp; | |
10381 | } | |
9a7c7890 | 10382 | |
5eddb70b | 10383 | dpll = 0; |
2c07245f | 10384 | |
3d6e9ee0 | 10385 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
10386 | dpll |= DPLLB_MODE_LVDS; |
10387 | else | |
10388 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 10389 | |
190f68c5 | 10390 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 10391 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 10392 | |
3d6e9ee0 VS |
10393 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
10394 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 10395 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 10396 | |
37a5650b | 10397 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 10398 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 10399 | |
7d7f8633 VS |
10400 | /* |
10401 | * The high speed IO clock is only really required for | |
10402 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
10403 | * possible to share the DPLL between CRT and HDMI. Enabling | |
10404 | * the clock needlessly does no real harm, except use up a | |
10405 | * bit of power potentially. | |
10406 | * | |
10407 | * We'll limit this to IVB with 3 pipes, since it has only two | |
10408 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
10409 | * driving PCH ports at the same time. On SNB we could do this, | |
10410 | * and potentially avoid enabling the second DPLL, but it's not | |
10411 | * clear if it''s a win or loss power wise. No point in doing | |
10412 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
10413 | */ | |
24977870 | 10414 | if (INTEL_NUM_PIPES(dev_priv) == 3 && |
7d7f8633 VS |
10415 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) |
10416 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
10417 | ||
a07d6787 | 10418 | /* compute bitmask from p1 value */ |
190f68c5 | 10419 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 10420 | /* also FPA1 */ |
190f68c5 | 10421 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 10422 | |
190f68c5 | 10423 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
10424 | case 5: |
10425 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
10426 | break; | |
10427 | case 7: | |
10428 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
10429 | break; | |
10430 | case 10: | |
10431 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
10432 | break; | |
10433 | case 14: | |
10434 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
10435 | break; | |
79e53945 JB |
10436 | } |
10437 | ||
3d6e9ee0 VS |
10438 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
10439 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 10440 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
10441 | else |
10442 | dpll |= PLL_REF_INPUT_DREFCLK; | |
10443 | ||
b75ca6f6 ACO |
10444 | dpll |= DPLL_VCO_ENABLE; |
10445 | ||
10446 | crtc_state->dpll_hw_state.dpll = dpll; | |
10447 | crtc_state->dpll_hw_state.fp0 = fp; | |
10448 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
10449 | } |
10450 | ||
9eae5e27 LDM |
10451 | static int ilk_crtc_compute_clock(struct intel_crtc *crtc, |
10452 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 10453 | { |
d2daff2c | 10454 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
866955fa | 10455 | struct intel_atomic_state *state = |
2225f3c6 | 10456 | to_intel_atomic_state(crtc_state->uapi.state); |
1b6f4958 | 10457 | const struct intel_limit *limit; |
997c030c | 10458 | int refclk = 120000; |
de13a2e3 | 10459 | |
dd3cd74a ACO |
10460 | memset(&crtc_state->dpll_hw_state, 0, |
10461 | sizeof(crtc_state->dpll_hw_state)); | |
10462 | ||
ded220e2 ACO |
10463 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
10464 | if (!crtc_state->has_pch_encoder) | |
10465 | return 0; | |
79e53945 | 10466 | |
2d84d2b3 | 10467 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c | 10468 | if (intel_panel_use_ssc(dev_priv)) { |
cd49f818 WK |
10469 | drm_dbg_kms(&dev_priv->drm, |
10470 | "using SSC reference clock of %d kHz\n", | |
10471 | dev_priv->vbt.lvds_ssc_freq); | |
997c030c ACO |
10472 | refclk = dev_priv->vbt.lvds_ssc_freq; |
10473 | } | |
10474 | ||
d2daff2c | 10475 | if (intel_is_dual_link_lvds(dev_priv)) { |
997c030c | 10476 | if (refclk == 100000) |
9eae5e27 | 10477 | limit = &ilk_limits_dual_lvds_100m; |
997c030c | 10478 | else |
9eae5e27 | 10479 | limit = &ilk_limits_dual_lvds; |
997c030c ACO |
10480 | } else { |
10481 | if (refclk == 100000) | |
9eae5e27 | 10482 | limit = &ilk_limits_single_lvds_100m; |
997c030c | 10483 | else |
9eae5e27 | 10484 | limit = &ilk_limits_single_lvds; |
997c030c ACO |
10485 | } |
10486 | } else { | |
9eae5e27 | 10487 | limit = &ilk_limits_dac; |
997c030c ACO |
10488 | } |
10489 | ||
364ee29d | 10490 | if (!crtc_state->clock_set && |
997c030c ACO |
10491 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
10492 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
10493 | drm_err(&dev_priv->drm, |
10494 | "Couldn't find PLL settings for mode!\n"); | |
364ee29d | 10495 | return -EINVAL; |
f47709a9 | 10496 | } |
79e53945 | 10497 | |
9eae5e27 | 10498 | ilk_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 10499 | |
866955fa | 10500 | if (!intel_reserve_shared_dplls(state, crtc, NULL)) { |
cd49f818 WK |
10501 | drm_dbg_kms(&dev_priv->drm, |
10502 | "failed to find PLL for pipe %c\n", | |
10503 | pipe_name(crtc->pipe)); | |
ded220e2 | 10504 | return -EINVAL; |
3fb37703 | 10505 | } |
79e53945 | 10506 | |
c8f7a0db | 10507 | return 0; |
79e53945 JB |
10508 | } |
10509 | ||
eb14cb74 VS |
10510 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
10511 | struct intel_link_m_n *m_n) | |
10512 | { | |
10513 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10514 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
10515 | enum pipe pipe = crtc->pipe; |
10516 | ||
dc008bf0 JN |
10517 | m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe)); |
10518 | m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe)); | |
10519 | m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) | |
eb14cb74 | 10520 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10521 | m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe)); |
10522 | m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) | |
eb14cb74 VS |
10523 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10524 | } | |
10525 | ||
10526 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
10527 | enum transcoder transcoder, | |
b95af8be VK |
10528 | struct intel_link_m_n *m_n, |
10529 | struct intel_link_m_n *m2_n2) | |
72419203 | 10530 | { |
6315b5d3 | 10531 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 10532 | enum pipe pipe = crtc->pipe; |
72419203 | 10533 | |
6315b5d3 | 10534 | if (INTEL_GEN(dev_priv) >= 5) { |
dc008bf0 JN |
10535 | m_n->link_m = intel_de_read(dev_priv, |
10536 | PIPE_LINK_M1(transcoder)); | |
10537 | m_n->link_n = intel_de_read(dev_priv, | |
10538 | PIPE_LINK_N1(transcoder)); | |
10539 | m_n->gmch_m = intel_de_read(dev_priv, | |
10540 | PIPE_DATA_M1(transcoder)) | |
eb14cb74 | 10541 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10542 | m_n->gmch_n = intel_de_read(dev_priv, |
10543 | PIPE_DATA_N1(transcoder)); | |
10544 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder)) | |
eb14cb74 | 10545 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
4207c8b9 ML |
10546 | |
10547 | if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { | |
dc008bf0 JN |
10548 | m2_n2->link_m = intel_de_read(dev_priv, |
10549 | PIPE_LINK_M2(transcoder)); | |
10550 | m2_n2->link_n = intel_de_read(dev_priv, | |
10551 | PIPE_LINK_N2(transcoder)); | |
10552 | m2_n2->gmch_m = intel_de_read(dev_priv, | |
10553 | PIPE_DATA_M2(transcoder)) | |
b95af8be | 10554 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10555 | m2_n2->gmch_n = intel_de_read(dev_priv, |
10556 | PIPE_DATA_N2(transcoder)); | |
10557 | m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder)) | |
b95af8be VK |
10558 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10559 | } | |
eb14cb74 | 10560 | } else { |
dc008bf0 JN |
10561 | m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe)); |
10562 | m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe)); | |
10563 | m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) | |
eb14cb74 | 10564 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10565 | m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe)); |
10566 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) | |
eb14cb74 VS |
10567 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10568 | } | |
10569 | } | |
10570 | ||
10571 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 10572 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 10573 | { |
681a8504 | 10574 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
10575 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
10576 | else | |
10577 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
10578 | &pipe_config->dp_m_n, |
10579 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 10580 | } |
72419203 | 10581 | |
9eae5e27 LDM |
10582 | static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc, |
10583 | struct intel_crtc_state *pipe_config) | |
eb14cb74 VS |
10584 | { |
10585 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 10586 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
10587 | } |
10588 | ||
35dd95b4 VS |
10589 | static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, |
10590 | u32 pos, u32 size) | |
10591 | { | |
10592 | drm_rect_init(&crtc_state->pch_pfit.dst, | |
10593 | pos >> 16, pos & 0xffff, | |
10594 | size >> 16, size & 0xffff); | |
10595 | } | |
10596 | ||
eac9c585 | 10597 | static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) |
bd2e244f | 10598 | { |
eac9c585 VS |
10599 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
10600 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10601 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
a1b2278e CK |
10602 | int id = -1; |
10603 | int i; | |
bd2e244f | 10604 | |
a1b2278e CK |
10605 | /* find scaler attached to this pipe */ |
10606 | for (i = 0; i < crtc->num_scalers; i++) { | |
35dd95b4 | 10607 | u32 ctl, pos, size; |
eac9c585 | 10608 | |
35dd95b4 VS |
10609 | ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); |
10610 | if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) | |
eac9c585 VS |
10611 | continue; |
10612 | ||
10613 | id = i; | |
10614 | crtc_state->pch_pfit.enabled = true; | |
35dd95b4 VS |
10615 | |
10616 | pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); | |
10617 | size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); | |
10618 | ||
10619 | ilk_get_pfit_pos_size(crtc_state, pos, size); | |
10620 | ||
eac9c585 VS |
10621 | scaler_state->scalers[i].in_use = true; |
10622 | break; | |
a1b2278e | 10623 | } |
bd2e244f | 10624 | |
a1b2278e | 10625 | scaler_state->scaler_id = id; |
eac9c585 | 10626 | if (id >= 0) |
a1b2278e | 10627 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
eac9c585 | 10628 | else |
a1b2278e | 10629 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
bd2e244f JB |
10630 | } |
10631 | ||
5724dbd1 | 10632 | static void |
f6df4d46 LDM |
10633 | skl_get_initial_plane_config(struct intel_crtc *crtc, |
10634 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
10635 | { |
10636 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10637 | struct drm_i915_private *dev_priv = to_i915(dev); |
282e83ef VS |
10638 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
10639 | enum plane_id plane_id = plane->id; | |
eade6c89 | 10640 | enum pipe pipe; |
4036c78c | 10641 | u32 val, base, offset, stride_mult, tiling, alpha; |
bc8d7dff | 10642 | int fourcc, pixel_format; |
6761dd31 | 10643 | unsigned int aligned_height; |
bc8d7dff | 10644 | struct drm_framebuffer *fb; |
1b842c89 | 10645 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 10646 | |
eade6c89 | 10647 | if (!plane->get_hw_state(plane, &pipe)) |
2924b8cc VS |
10648 | return; |
10649 | ||
e57291c2 | 10650 | drm_WARN_ON(dev, pipe != crtc->pipe); |
eade6c89 | 10651 | |
d9806c9f | 10652 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 10653 | if (!intel_fb) { |
cd49f818 | 10654 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); |
bc8d7dff DL |
10655 | return; |
10656 | } | |
10657 | ||
1b842c89 DL |
10658 | fb = &intel_fb->base; |
10659 | ||
d2e9f5fc VS |
10660 | fb->dev = dev; |
10661 | ||
dc008bf0 | 10662 | val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); |
42a7b088 | 10663 | |
b5972776 JA |
10664 | if (INTEL_GEN(dev_priv) >= 11) |
10665 | pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; | |
10666 | else | |
10667 | pixel_format = val & PLANE_CTL_FORMAT_MASK; | |
4036c78c JA |
10668 | |
10669 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { | |
dc008bf0 JN |
10670 | alpha = intel_de_read(dev_priv, |
10671 | PLANE_COLOR_CTL(pipe, plane_id)); | |
4036c78c JA |
10672 | alpha &= PLANE_COLOR_ALPHA_MASK; |
10673 | } else { | |
10674 | alpha = val & PLANE_CTL_ALPHA_MASK; | |
10675 | } | |
10676 | ||
bc8d7dff | 10677 | fourcc = skl_format_to_fourcc(pixel_format, |
4036c78c | 10678 | val & PLANE_CTL_ORDER_RGBX, alpha); |
2f3f4763 | 10679 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 10680 | |
40f46283 DL |
10681 | tiling = val & PLANE_CTL_TILED_MASK; |
10682 | switch (tiling) { | |
10683 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 10684 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
10685 | break; |
10686 | case PLANE_CTL_TILED_X: | |
10687 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 10688 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
10689 | break; |
10690 | case PLANE_CTL_TILED_Y: | |
914a4fd8 | 10691 | plane_config->tiling = I915_TILING_Y; |
53867b46 | 10692 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) |
b3e57bcc DP |
10693 | fb->modifier = INTEL_GEN(dev_priv) >= 12 ? |
10694 | I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : | |
10695 | I915_FORMAT_MOD_Y_TILED_CCS; | |
2dfbf9d2 DP |
10696 | else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) |
10697 | fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; | |
2e2adb05 VS |
10698 | else |
10699 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
10700 | break; |
10701 | case PLANE_CTL_TILED_YF: | |
53867b46 | 10702 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) |
2e2adb05 VS |
10703 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; |
10704 | else | |
10705 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
10706 | break; |
10707 | default: | |
10708 | MISSING_CASE(tiling); | |
10709 | goto error; | |
10710 | } | |
10711 | ||
f43348a3 VS |
10712 | /* |
10713 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
10714 | * while i915 HW rotation is clockwise, thats why this swapping. | |
10715 | */ | |
10716 | switch (val & PLANE_CTL_ROTATE_MASK) { | |
10717 | case PLANE_CTL_ROTATE_0: | |
10718 | plane_config->rotation = DRM_MODE_ROTATE_0; | |
10719 | break; | |
10720 | case PLANE_CTL_ROTATE_90: | |
10721 | plane_config->rotation = DRM_MODE_ROTATE_270; | |
10722 | break; | |
10723 | case PLANE_CTL_ROTATE_180: | |
10724 | plane_config->rotation = DRM_MODE_ROTATE_180; | |
10725 | break; | |
10726 | case PLANE_CTL_ROTATE_270: | |
10727 | plane_config->rotation = DRM_MODE_ROTATE_90; | |
10728 | break; | |
10729 | } | |
10730 | ||
10731 | if (INTEL_GEN(dev_priv) >= 10 && | |
10732 | val & PLANE_CTL_FLIP_HORIZONTAL) | |
10733 | plane_config->rotation |= DRM_MODE_REFLECT_X; | |
10734 | ||
a40a8305 VS |
10735 | /* 90/270 degree rotation would require extra work */ |
10736 | if (drm_rotation_90_or_270(plane_config->rotation)) | |
10737 | goto error; | |
10738 | ||
dc008bf0 | 10739 | base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000; |
bc8d7dff DL |
10740 | plane_config->base = base; |
10741 | ||
dc008bf0 | 10742 | offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); |
bc8d7dff | 10743 | |
dc008bf0 | 10744 | val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); |
e91c8a29 MN |
10745 | fb->height = ((val >> 16) & 0xffff) + 1; |
10746 | fb->width = ((val >> 0) & 0xffff) + 1; | |
bc8d7dff | 10747 | |
dc008bf0 | 10748 | val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); |
b3cf5c06 | 10749 | stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); |
bc8d7dff DL |
10750 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
10751 | ||
d88c4afd | 10752 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 10753 | |
f37b5c2b | 10754 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff | 10755 | |
cd49f818 WK |
10756 | drm_dbg_kms(&dev_priv->drm, |
10757 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
10758 | crtc->base.name, plane->base.name, fb->width, fb->height, | |
10759 | fb->format->cpp[0] * 8, base, fb->pitches[0], | |
10760 | plane_config->size); | |
bc8d7dff | 10761 | |
2d14030b | 10762 | plane_config->fb = intel_fb; |
bc8d7dff DL |
10763 | return; |
10764 | ||
10765 | error: | |
d1a3a036 | 10766 | kfree(intel_fb); |
bc8d7dff DL |
10767 | } |
10768 | ||
eac9c585 | 10769 | static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) |
2fa2fe9a | 10770 | { |
eac9c585 VS |
10771 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
10772 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
35dd95b4 | 10773 | u32 ctl, pos, size; |
2fa2fe9a | 10774 | |
35dd95b4 VS |
10775 | ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); |
10776 | if ((ctl & PF_ENABLE) == 0) | |
eac9c585 | 10777 | return; |
2fa2fe9a | 10778 | |
eac9c585 | 10779 | crtc_state->pch_pfit.enabled = true; |
35dd95b4 VS |
10780 | |
10781 | pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); | |
10782 | size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); | |
10783 | ||
10784 | ilk_get_pfit_pos_size(crtc_state, pos, size); | |
eac9c585 VS |
10785 | |
10786 | /* | |
10787 | * We currently do not free assignements of panel fitters on | |
10788 | * ivb/hsw (since we don't use the higher upscaling modes which | |
10789 | * differentiates them) so just WARN about this case for now. | |
10790 | */ | |
10791 | drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) && | |
35dd95b4 | 10792 | (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); |
79e53945 JB |
10793 | } |
10794 | ||
9eae5e27 LDM |
10795 | static bool ilk_get_pipe_config(struct intel_crtc *crtc, |
10796 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b DV |
10797 | { |
10798 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10799 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 10800 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 10801 | intel_wakeref_t wakeref; |
ba3f4d0a | 10802 | u32 tmp; |
1729050e | 10803 | bool ret; |
0e8ffe1b | 10804 | |
1729050e | 10805 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
0e6e0be4 CW |
10806 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
10807 | if (!wakeref) | |
930e8c9e PZ |
10808 | return false; |
10809 | ||
e143a21c | 10810 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 10811 | pipe_config->shared_dpll = NULL; |
eccb140b | 10812 | |
1729050e | 10813 | ret = false; |
dc008bf0 | 10814 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); |
0e8ffe1b | 10815 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 10816 | goto out; |
0e8ffe1b | 10817 | |
42571aef VS |
10818 | switch (tmp & PIPECONF_BPC_MASK) { |
10819 | case PIPECONF_6BPC: | |
10820 | pipe_config->pipe_bpp = 18; | |
10821 | break; | |
10822 | case PIPECONF_8BPC: | |
10823 | pipe_config->pipe_bpp = 24; | |
10824 | break; | |
10825 | case PIPECONF_10BPC: | |
10826 | pipe_config->pipe_bpp = 30; | |
10827 | break; | |
10828 | case PIPECONF_12BPC: | |
10829 | pipe_config->pipe_bpp = 36; | |
10830 | break; | |
10831 | default: | |
10832 | break; | |
10833 | } | |
10834 | ||
b5a9fa09 DV |
10835 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
10836 | pipe_config->limited_color_range = true; | |
10837 | ||
d1844606 VS |
10838 | switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { |
10839 | case PIPECONF_OUTPUT_COLORSPACE_YUV601: | |
10840 | case PIPECONF_OUTPUT_COLORSPACE_YUV709: | |
10841 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; | |
10842 | break; | |
10843 | default: | |
10844 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | |
10845 | break; | |
10846 | } | |
10847 | ||
9d5441de VS |
10848 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >> |
10849 | PIPECONF_GAMMA_MODE_SHIFT; | |
10850 | ||
dc008bf0 JN |
10851 | pipe_config->csc_mode = intel_de_read(dev_priv, |
10852 | PIPE_CSC_MODE(crtc->pipe)); | |
a1f1e61b | 10853 | |
5f29ab23 | 10854 | i9xx_get_pipe_color_config(pipe_config); |
3633e511 | 10855 | intel_color_get_config(pipe_config); |
5f29ab23 | 10856 | |
dc008bf0 | 10857 | if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 10858 | struct intel_shared_dpll *pll; |
8106ddbd | 10859 | enum intel_dpll_id pll_id; |
fdbc5d68 | 10860 | bool pll_active; |
66e985c0 | 10861 | |
88adfff1 DV |
10862 | pipe_config->has_pch_encoder = true; |
10863 | ||
dc008bf0 | 10864 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe)); |
627eb5a3 DV |
10865 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
10866 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 | 10867 | |
9eae5e27 | 10868 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
6c49f241 | 10869 | |
2d1fe073 | 10870 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
10871 | /* |
10872 | * The pipe->pch transcoder and pch transcoder->pll | |
10873 | * mapping is fixed. | |
10874 | */ | |
8106ddbd | 10875 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 | 10876 | } else { |
dc008bf0 | 10877 | tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
c0d43d62 | 10878 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
8106ddbd | 10879 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 10880 | else |
8106ddbd | 10881 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 10882 | } |
66e985c0 | 10883 | |
8106ddbd ACO |
10884 | pipe_config->shared_dpll = |
10885 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
10886 | pll = pipe_config->shared_dpll; | |
66e985c0 | 10887 | |
fdbc5d68 VS |
10888 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, |
10889 | &pipe_config->dpll_hw_state); | |
10890 | drm_WARN_ON(dev, !pll_active); | |
c93f54cf DV |
10891 | |
10892 | tmp = pipe_config->dpll_hw_state.dpll; | |
10893 | pipe_config->pixel_multiplier = | |
10894 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
10895 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 | 10896 | |
9eae5e27 | 10897 | ilk_pch_clock_get(crtc, pipe_config); |
6c49f241 DV |
10898 | } else { |
10899 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10900 | } |
10901 | ||
e7fc3f90 | 10902 | intel_get_transcoder_timings(crtc, pipe_config); |
bc58be60 | 10903 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10904 | |
eac9c585 | 10905 | ilk_get_pfit_config(pipe_config); |
2fa2fe9a | 10906 | |
1729050e ID |
10907 | ret = true; |
10908 | ||
10909 | out: | |
0e6e0be4 | 10910 | intel_display_power_put(dev_priv, power_domain, wakeref); |
1729050e ID |
10911 | |
10912 | return ret; | |
0e8ffe1b | 10913 | } |
1e98f88c LDM |
10914 | |
10915 | static int hsw_crtc_compute_clock(struct intel_crtc *crtc, | |
10916 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10917 | { |
70a057b7 | 10918 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5a0b385e | 10919 | struct intel_atomic_state *state = |
2225f3c6 | 10920 | to_intel_atomic_state(crtc_state->uapi.state); |
5a0b385e | 10921 | |
70a057b7 | 10922 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || |
2dd24a9c | 10923 | INTEL_GEN(dev_priv) >= 11) { |
44a126ba | 10924 | struct intel_encoder *encoder = |
5a0b385e | 10925 | intel_get_crtc_new_encoder(state, crtc_state); |
44a126ba | 10926 | |
866955fa | 10927 | if (!intel_reserve_shared_dplls(state, crtc, encoder)) { |
cd49f818 WK |
10928 | drm_dbg_kms(&dev_priv->drm, |
10929 | "failed to find PLL for pipe %c\n", | |
10930 | pipe_name(crtc->pipe)); | |
af3997b5 | 10931 | return -EINVAL; |
44a126ba | 10932 | } |
af3997b5 | 10933 | } |
716c2e55 | 10934 | |
c8f7a0db | 10935 | return 0; |
79e53945 JB |
10936 | } |
10937 | ||
11ffe972 LDM |
10938 | static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10939 | struct intel_crtc_state *pipe_config) | |
10940 | { | |
10941 | enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; | |
10942 | enum phy phy = intel_port_to_phy(dev_priv, port); | |
b97fcaee VS |
10943 | struct icl_port_dpll *port_dpll; |
10944 | struct intel_shared_dpll *pll; | |
11ffe972 | 10945 | enum intel_dpll_id id; |
b97fcaee | 10946 | bool pll_active; |
11ffe972 LDM |
10947 | u32 clk_sel; |
10948 | ||
10949 | clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
10950 | id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy); | |
10951 | ||
10952 | if (WARN_ON(id > DPLL_ID_DG1_DPLL3)) | |
10953 | return; | |
10954 | ||
b97fcaee VS |
10955 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
10956 | port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; | |
10957 | ||
10958 | port_dpll->pll = pll; | |
10959 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
10960 | &port_dpll->hw_state); | |
10961 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
11ffe972 LDM |
10962 | |
10963 | icl_set_active_port_dpll(pipe_config, port_dpll_id); | |
10964 | } | |
10965 | ||
8e619820 LDM |
10966 | static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10967 | struct intel_crtc_state *pipe_config) | |
8b0f7e06 | 10968 | { |
b97fcaee | 10969 | struct intel_shared_dpll *pll; |
8b0f7e06 | 10970 | enum intel_dpll_id id; |
b97fcaee | 10971 | bool pll_active; |
8b0f7e06 KM |
10972 | u32 temp; |
10973 | ||
dc008bf0 | 10974 | temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); |
dfbd4508 | 10975 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); |
8b0f7e06 | 10976 | |
e57291c2 | 10977 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) |
8b0f7e06 KM |
10978 | return; |
10979 | ||
b97fcaee VS |
10980 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
10981 | ||
10982 | pipe_config->shared_dpll = pll; | |
10983 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
10984 | &pipe_config->dpll_hw_state); | |
10985 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
8b0f7e06 KM |
10986 | } |
10987 | ||
95be3484 LDM |
10988 | static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10989 | struct intel_crtc_state *pipe_config) | |
970888e7 | 10990 | { |
d8fe2ab6 | 10991 | enum phy phy = intel_port_to_phy(dev_priv, port); |
eea72c4c | 10992 | enum icl_port_dpll_id port_dpll_id; |
b97fcaee VS |
10993 | struct icl_port_dpll *port_dpll; |
10994 | struct intel_shared_dpll *pll; | |
970888e7 | 10995 | enum intel_dpll_id id; |
b97fcaee | 10996 | bool pll_active; |
970888e7 PZ |
10997 | u32 temp; |
10998 | ||
d8fe2ab6 | 10999 | if (intel_phy_is_combo(dev_priv, phy)) { |
cd803bb4 MR |
11000 | u32 mask, shift; |
11001 | ||
11002 | if (IS_ROCKETLAKE(dev_priv)) { | |
11003 | mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
11004 | shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); | |
11005 | } else { | |
11006 | mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
11007 | shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); | |
11008 | } | |
11009 | ||
11010 | temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; | |
11011 | id = temp >> shift; | |
eea72c4c | 11012 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
d8fe2ab6 | 11013 | } else if (intel_phy_is_tc(dev_priv, phy)) { |
dc008bf0 | 11014 | u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; |
39a5883f ID |
11015 | |
11016 | if (clk_sel == DDI_CLK_SEL_MG) { | |
11017 | id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, | |
11018 | port)); | |
eea72c4c | 11019 | port_dpll_id = ICL_PORT_DPLL_MG_PHY; |
39a5883f | 11020 | } else { |
e57291c2 PB |
11021 | drm_WARN_ON(&dev_priv->drm, |
11022 | clk_sel < DDI_CLK_SEL_TBT_162); | |
39a5883f | 11023 | id = DPLL_ID_ICL_TBTPLL; |
eea72c4c | 11024 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
39a5883f | 11025 | } |
8ea59e67 | 11026 | } else { |
e57291c2 | 11027 | drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); |
970888e7 PZ |
11028 | return; |
11029 | } | |
11030 | ||
b97fcaee VS |
11031 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
11032 | port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; | |
11033 | ||
11034 | port_dpll->pll = pll; | |
11035 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
11036 | &port_dpll->hw_state); | |
11037 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
eea72c4c ID |
11038 | |
11039 | icl_set_active_port_dpll(pipe_config, port_dpll_id); | |
970888e7 PZ |
11040 | } |
11041 | ||
3760b59c S |
11042 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
11043 | enum port port, | |
11044 | struct intel_crtc_state *pipe_config) | |
11045 | { | |
b97fcaee | 11046 | struct intel_shared_dpll *pll; |
8106ddbd | 11047 | enum intel_dpll_id id; |
b97fcaee | 11048 | bool pll_active; |
8106ddbd | 11049 | |
3760b59c S |
11050 | switch (port) { |
11051 | case PORT_A: | |
08250c4b | 11052 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
11053 | break; |
11054 | case PORT_B: | |
08250c4b | 11055 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
11056 | break; |
11057 | case PORT_C: | |
08250c4b | 11058 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
11059 | break; |
11060 | default: | |
cd49f818 | 11061 | drm_err(&dev_priv->drm, "Incorrect port type\n"); |
8106ddbd | 11062 | return; |
3760b59c | 11063 | } |
8106ddbd | 11064 | |
b97fcaee VS |
11065 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
11066 | ||
11067 | pipe_config->shared_dpll = pll; | |
11068 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
11069 | &pipe_config->dpll_hw_state); | |
11070 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
3760b59c S |
11071 | } |
11072 | ||
f6df4d46 LDM |
11073 | static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
11074 | struct intel_crtc_state *pipe_config) | |
96b7dfb7 | 11075 | { |
b97fcaee | 11076 | struct intel_shared_dpll *pll; |
8106ddbd | 11077 | enum intel_dpll_id id; |
b97fcaee | 11078 | bool pll_active; |
a3c988ea | 11079 | u32 temp; |
96b7dfb7 | 11080 | |
dc008bf0 | 11081 | temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
c856052a | 11082 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 11083 | |
e57291c2 | 11084 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 11085 | return; |
8106ddbd | 11086 | |
b97fcaee VS |
11087 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
11088 | ||
11089 | pipe_config->shared_dpll = pll; | |
11090 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
11091 | &pipe_config->dpll_hw_state); | |
11092 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
96b7dfb7 S |
11093 | } |
11094 | ||
1e98f88c LDM |
11095 | static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
11096 | struct intel_crtc_state *pipe_config) | |
7d2c8175 | 11097 | { |
b97fcaee | 11098 | struct intel_shared_dpll *pll; |
8106ddbd | 11099 | enum intel_dpll_id id; |
dc008bf0 | 11100 | u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)); |
b97fcaee | 11101 | bool pll_active; |
8106ddbd | 11102 | |
c856052a | 11103 | switch (ddi_pll_sel) { |
7d2c8175 | 11104 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 11105 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
11106 | break; |
11107 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 11108 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 11109 | break; |
00490c22 | 11110 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 11111 | id = DPLL_ID_SPLL; |
79bd23da | 11112 | break; |
9d16da65 ACO |
11113 | case PORT_CLK_SEL_LCPLL_810: |
11114 | id = DPLL_ID_LCPLL_810; | |
11115 | break; | |
11116 | case PORT_CLK_SEL_LCPLL_1350: | |
11117 | id = DPLL_ID_LCPLL_1350; | |
11118 | break; | |
11119 | case PORT_CLK_SEL_LCPLL_2700: | |
11120 | id = DPLL_ID_LCPLL_2700; | |
11121 | break; | |
8106ddbd | 11122 | default: |
c856052a | 11123 | MISSING_CASE(ddi_pll_sel); |
df561f66 | 11124 | fallthrough; |
8106ddbd | 11125 | case PORT_CLK_SEL_NONE: |
8106ddbd | 11126 | return; |
7d2c8175 | 11127 | } |
8106ddbd | 11128 | |
b97fcaee VS |
11129 | pll = intel_get_shared_dpll_by_id(dev_priv, id); |
11130 | ||
11131 | pipe_config->shared_dpll = pll; | |
11132 | pll_active = intel_dpll_get_hw_state(dev_priv, pll, | |
11133 | &pipe_config->dpll_hw_state); | |
11134 | drm_WARN_ON(&dev_priv->drm, !pll_active); | |
7d2c8175 DL |
11135 | } |
11136 | ||
cf30429e JN |
11137 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
11138 | struct intel_crtc_state *pipe_config, | |
513a4c55 CW |
11139 | u64 *power_domain_mask, |
11140 | intel_wakeref_t *wakerefs) | |
cf30429e JN |
11141 | { |
11142 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11143 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e | 11144 | enum intel_display_power_domain power_domain; |
617458cd | 11145 | unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP); |
0716931a JN |
11146 | unsigned long enabled_panel_transcoders = 0; |
11147 | enum transcoder panel_transcoder; | |
513a4c55 | 11148 | intel_wakeref_t wf; |
cf30429e | 11149 | u32 tmp; |
0716931a | 11150 | |
2dd24a9c | 11151 | if (INTEL_GEN(dev_priv) >= 11) |
0716931a JN |
11152 | panel_transcoder_mask |= |
11153 | BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); | |
cf30429e | 11154 | |
d9a7bc67 ID |
11155 | /* |
11156 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
0716931a | 11157 | * and DSI transcoders handled below. |
d9a7bc67 | 11158 | */ |
cf30429e JN |
11159 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
11160 | ||
11161 | /* | |
11162 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
11163 | * consistency and less surprising code; it's in always on power). | |
11164 | */ | |
617458cd AS |
11165 | for_each_cpu_transcoder_masked(dev_priv, panel_transcoder, |
11166 | panel_transcoder_mask) { | |
dc0c0bfe | 11167 | bool force_thru = false; |
0716931a | 11168 | enum pipe trans_pipe; |
2ca711ca | 11169 | |
dc008bf0 JN |
11170 | tmp = intel_de_read(dev_priv, |
11171 | TRANS_DDI_FUNC_CTL(panel_transcoder)); | |
0716931a JN |
11172 | if (!(tmp & TRANS_DDI_FUNC_ENABLE)) |
11173 | continue; | |
2ca711ca | 11174 | |
0716931a JN |
11175 | /* |
11176 | * Log all enabled ones, only use the first one. | |
11177 | * | |
11178 | * FIXME: This won't work for two separate DSI displays. | |
11179 | */ | |
11180 | enabled_panel_transcoders |= BIT(panel_transcoder); | |
11181 | if (enabled_panel_transcoders != BIT(panel_transcoder)) | |
11182 | continue; | |
2ca711ca | 11183 | |
cf30429e JN |
11184 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
11185 | default: | |
e57291c2 PB |
11186 | drm_WARN(dev, 1, |
11187 | "unknown pipe linked to transcoder %s\n", | |
11188 | transcoder_name(panel_transcoder)); | |
df561f66 | 11189 | fallthrough; |
cf30429e | 11190 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
dc0c0bfe | 11191 | force_thru = true; |
df561f66 | 11192 | fallthrough; |
cf30429e | 11193 | case TRANS_DDI_EDP_INPUT_A_ON: |
2ca711ca | 11194 | trans_pipe = PIPE_A; |
cf30429e JN |
11195 | break; |
11196 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
2ca711ca | 11197 | trans_pipe = PIPE_B; |
cf30429e JN |
11198 | break; |
11199 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
2ca711ca | 11200 | trans_pipe = PIPE_C; |
cf30429e | 11201 | break; |
9c569784 JN |
11202 | case TRANS_DDI_EDP_INPUT_D_ONOFF: |
11203 | trans_pipe = PIPE_D; | |
11204 | break; | |
cf30429e JN |
11205 | } |
11206 | ||
dc0c0bfe | 11207 | if (trans_pipe == crtc->pipe) { |
0716931a | 11208 | pipe_config->cpu_transcoder = panel_transcoder; |
dc0c0bfe VS |
11209 | pipe_config->pch_pfit.force_thru = force_thru; |
11210 | } | |
cf30429e JN |
11211 | } |
11212 | ||
0716931a JN |
11213 | /* |
11214 | * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1 | |
11215 | */ | |
e57291c2 PB |
11216 | drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && |
11217 | enabled_panel_transcoders != BIT(TRANSCODER_EDP)); | |
0716931a | 11218 | |
cf30429e | 11219 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
e57291c2 | 11220 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11221 | |
11222 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11223 | if (!wf) | |
cf30429e | 11224 | return false; |
04161d64 | 11225 | |
513a4c55 | 11226 | wakerefs[power_domain] = wf; |
d8fc70b7 | 11227 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e | 11228 | |
dc008bf0 | 11229 | tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); |
cf30429e JN |
11230 | |
11231 | return tmp & PIPECONF_ENABLE; | |
11232 | } | |
11233 | ||
4d1de975 JN |
11234 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
11235 | struct intel_crtc_state *pipe_config, | |
513a4c55 CW |
11236 | u64 *power_domain_mask, |
11237 | intel_wakeref_t *wakerefs) | |
4d1de975 JN |
11238 | { |
11239 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11240 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 11241 | enum intel_display_power_domain power_domain; |
4d1de975 | 11242 | enum transcoder cpu_transcoder; |
513a4c55 CW |
11243 | intel_wakeref_t wf; |
11244 | enum port port; | |
4d1de975 JN |
11245 | u32 tmp; |
11246 | ||
4d1de975 JN |
11247 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
11248 | if (port == PORT_A) | |
11249 | cpu_transcoder = TRANSCODER_DSI_A; | |
11250 | else | |
11251 | cpu_transcoder = TRANSCODER_DSI_C; | |
11252 | ||
11253 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
e57291c2 | 11254 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11255 | |
11256 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11257 | if (!wf) | |
4d1de975 | 11258 | continue; |
04161d64 | 11259 | |
513a4c55 | 11260 | wakerefs[power_domain] = wf; |
d8fc70b7 | 11261 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 11262 | |
db18b6a6 ID |
11263 | /* |
11264 | * The PLL needs to be enabled with a valid divider | |
11265 | * configuration, otherwise accessing DSI registers will hang | |
11266 | * the machine. See BSpec North Display Engine | |
11267 | * registers/MIPI[BXT]. We can break out here early, since we | |
11268 | * need the same DSI PLL to be enabled for both DSI ports. | |
11269 | */ | |
e518634b | 11270 | if (!bxt_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
11271 | break; |
11272 | ||
4d1de975 | 11273 | /* XXX: this works for video mode only */ |
dc008bf0 | 11274 | tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); |
4d1de975 JN |
11275 | if (!(tmp & DPI_ENABLE)) |
11276 | continue; | |
11277 | ||
dc008bf0 | 11278 | tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); |
4d1de975 JN |
11279 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) |
11280 | continue; | |
11281 | ||
11282 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
11283 | break; |
11284 | } | |
11285 | ||
d7edc4e5 | 11286 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
11287 | } |
11288 | ||
1e98f88c LDM |
11289 | static void hsw_get_ddi_port_state(struct intel_crtc *crtc, |
11290 | struct intel_crtc_state *pipe_config) | |
26804afd | 11291 | { |
6315b5d3 | 11292 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6d73af27 | 11293 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
26804afd | 11294 | enum port port; |
ba3f4d0a | 11295 | u32 tmp; |
26804afd | 11296 | |
6d73af27 VK |
11297 | if (transcoder_is_dsi(cpu_transcoder)) { |
11298 | port = (cpu_transcoder == TRANSCODER_DSI_A) ? | |
11299 | PORT_A : PORT_B; | |
11300 | } else { | |
dc008bf0 JN |
11301 | tmp = intel_de_read(dev_priv, |
11302 | TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
6d73af27 VK |
11303 | if (INTEL_GEN(dev_priv) >= 12) |
11304 | port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); | |
11305 | else | |
11306 | port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); | |
11307 | } | |
26804afd | 11308 | |
11ffe972 LDM |
11309 | if (IS_DG1(dev_priv)) |
11310 | dg1_get_ddi_pll(dev_priv, port, pipe_config); | |
11311 | else if (INTEL_GEN(dev_priv) >= 11) | |
95be3484 | 11312 | icl_get_ddi_pll(dev_priv, port, pipe_config); |
970888e7 | 11313 | else if (IS_CANNONLAKE(dev_priv)) |
8e619820 | 11314 | cnl_get_ddi_pll(dev_priv, port, pipe_config); |
8b0f7e06 | 11315 | else if (IS_GEN9_BC(dev_priv)) |
f6df4d46 | 11316 | skl_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 11317 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 11318 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 | 11319 | else |
1e98f88c | 11320 | hsw_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 11321 | |
26804afd DV |
11322 | /* |
11323 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
11324 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
11325 | * the PCH transcoder is on. | |
11326 | */ | |
6315b5d3 | 11327 | if (INTEL_GEN(dev_priv) < 9 && |
dc008bf0 | 11328 | (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
11329 | pipe_config->has_pch_encoder = true; |
11330 | ||
dc008bf0 | 11331 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); |
26804afd DV |
11332 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
11333 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
11334 | ||
9eae5e27 | 11335 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
26804afd DV |
11336 | } |
11337 | } | |
11338 | ||
1e98f88c LDM |
11339 | static bool hsw_get_pipe_config(struct intel_crtc *crtc, |
11340 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11341 | { |
6315b5d3 | 11342 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
513a4c55 | 11343 | intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; |
1729050e | 11344 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 11345 | u64 power_domain_mask; |
cf30429e | 11346 | bool active; |
6dcde047 | 11347 | u32 tmp; |
0e8ffe1b | 11348 | |
ba5f1ae9 MN |
11349 | pipe_config->master_transcoder = INVALID_TRANSCODER; |
11350 | ||
1729050e | 11351 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
513a4c55 CW |
11352 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
11353 | if (!wf) | |
b5482bd0 | 11354 | return false; |
513a4c55 CW |
11355 | |
11356 | wakerefs[power_domain] = wf; | |
d8fc70b7 | 11357 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 11358 | |
8106ddbd | 11359 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 11360 | |
513a4c55 CW |
11361 | active = hsw_get_transcoder_state(crtc, pipe_config, |
11362 | &power_domain_mask, wakerefs); | |
eccb140b | 11363 | |
cc3f90f0 | 11364 | if (IS_GEN9_LP(dev_priv) && |
513a4c55 CW |
11365 | bxt_get_dsi_transcoder_state(crtc, pipe_config, |
11366 | &power_domain_mask, wakerefs)) { | |
e57291c2 | 11367 | drm_WARN_ON(&dev_priv->drm, active); |
d7edc4e5 | 11368 | active = true; |
4d1de975 JN |
11369 | } |
11370 | ||
cf30429e | 11371 | if (!active) |
1729050e | 11372 | goto out; |
0e8ffe1b | 11373 | |
2eae5d6b | 11374 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || |
2dd24a9c | 11375 | INTEL_GEN(dev_priv) >= 11) { |
1e98f88c | 11376 | hsw_get_ddi_port_state(crtc, pipe_config); |
e7fc3f90 | 11377 | intel_get_transcoder_timings(crtc, pipe_config); |
4d1de975 | 11378 | } |
627eb5a3 | 11379 | |
bc58be60 | 11380 | intel_get_pipe_src_size(crtc, pipe_config); |
b10d1173 | 11381 | |
ac0f01ce | 11382 | if (IS_HASWELL(dev_priv)) { |
dc008bf0 JN |
11383 | u32 tmp = intel_de_read(dev_priv, |
11384 | PIPECONF(pipe_config->cpu_transcoder)); | |
ac0f01ce VS |
11385 | |
11386 | if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) | |
11387 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; | |
11388 | else | |
11389 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | |
11390 | } else { | |
b10d1173 VS |
11391 | pipe_config->output_format = |
11392 | bdw_get_pipemisc_output_format(crtc); | |
b10d1173 | 11393 | } |
1bd1bd80 | 11394 | |
dc008bf0 JN |
11395 | pipe_config->gamma_mode = intel_de_read(dev_priv, |
11396 | GAMMA_MODE(crtc->pipe)); | |
05dc698c | 11397 | |
dc008bf0 JN |
11398 | pipe_config->csc_mode = intel_de_read(dev_priv, |
11399 | PIPE_CSC_MODE(crtc->pipe)); | |
a1f1e61b | 11400 | |
5f29ab23 | 11401 | if (INTEL_GEN(dev_priv) >= 9) { |
6dcde047 | 11402 | tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); |
5f29ab23 VS |
11403 | |
11404 | if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) | |
11405 | pipe_config->gamma_enable = true; | |
8271b2ef VS |
11406 | |
11407 | if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) | |
11408 | pipe_config->csc_enable = true; | |
5f29ab23 VS |
11409 | } else { |
11410 | i9xx_get_pipe_color_config(pipe_config); | |
11411 | } | |
11412 | ||
3633e511 SS |
11413 | intel_color_get_config(pipe_config); |
11414 | ||
6dcde047 VS |
11415 | tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); |
11416 | pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); | |
11417 | if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
11418 | pipe_config->ips_linetime = | |
11419 | REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); | |
11420 | ||
1729050e | 11421 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
e57291c2 | 11422 | drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11423 | |
11424 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11425 | if (wf) { | |
11426 | wakerefs[power_domain] = wf; | |
d8fc70b7 | 11427 | power_domain_mask |= BIT_ULL(power_domain); |
04161d64 | 11428 | |
6315b5d3 | 11429 | if (INTEL_GEN(dev_priv) >= 9) |
eac9c585 | 11430 | skl_get_pfit_config(pipe_config); |
ff6d9f55 | 11431 | else |
eac9c585 | 11432 | ilk_get_pfit_config(pipe_config); |
bd2e244f | 11433 | } |
88adfff1 | 11434 | |
24f28450 ML |
11435 | if (hsw_crtc_supports_ips(crtc)) { |
11436 | if (IS_HASWELL(dev_priv)) | |
dc008bf0 JN |
11437 | pipe_config->ips_enabled = intel_de_read(dev_priv, |
11438 | IPS_CTL) & IPS_ENABLE; | |
24f28450 ML |
11439 | else { |
11440 | /* | |
11441 | * We cannot readout IPS state on broadwell, set to | |
11442 | * true so we can set it to a defined state on first | |
11443 | * commit. | |
11444 | */ | |
11445 | pipe_config->ips_enabled = true; | |
11446 | } | |
11447 | } | |
11448 | ||
4d1de975 JN |
11449 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
11450 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 | 11451 | pipe_config->pixel_multiplier = |
dc008bf0 JN |
11452 | intel_de_read(dev_priv, |
11453 | PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
ebb69c95 CT |
11454 | } else { |
11455 | pipe_config->pixel_multiplier = 1; | |
11456 | } | |
6c49f241 | 11457 | |
1729050e ID |
11458 | out: |
11459 | for_each_power_domain(power_domain, power_domain_mask) | |
513a4c55 CW |
11460 | intel_display_power_put(dev_priv, |
11461 | power_domain, wakerefs[power_domain]); | |
1729050e | 11462 | |
cf30429e | 11463 | return active; |
0e8ffe1b DV |
11464 | } |
11465 | ||
11f9af16 MN |
11466 | static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) |
11467 | { | |
11468 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
11469 | struct drm_i915_private *i915 = to_i915(crtc->base.dev); | |
11470 | ||
291106cb VS |
11471 | if (!i915->display.get_pipe_config(crtc, crtc_state)) |
11472 | return false; | |
11473 | ||
11474 | crtc_state->hw.active = true; | |
11475 | ||
c42773b6 VS |
11476 | intel_crtc_readout_derived_state(crtc_state); |
11477 | ||
291106cb | 11478 | return true; |
11f9af16 MN |
11479 | } |
11480 | ||
cd5dcbf1 | 11481 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
11482 | { |
11483 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 11484 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 11485 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
1cecc830 VS |
11486 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11487 | u32 base; | |
11488 | ||
d53db442 | 11489 | if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) |
c6790dc2 | 11490 | base = sg_dma_address(obj->mm.pages->sgl); |
1cecc830 VS |
11491 | else |
11492 | base = intel_plane_ggtt_offset(plane_state); | |
11493 | ||
30a027dc | 11494 | return base + plane_state->color_plane[0].offset; |
1cecc830 VS |
11495 | } |
11496 | ||
ed270223 VS |
11497 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
11498 | { | |
f90a85e7 ML |
11499 | int x = plane_state->uapi.dst.x1; |
11500 | int y = plane_state->uapi.dst.y1; | |
ed270223 VS |
11501 | u32 pos = 0; |
11502 | ||
11503 | if (x < 0) { | |
11504 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
11505 | x = -x; | |
11506 | } | |
11507 | pos |= x << CURSOR_X_SHIFT; | |
11508 | ||
11509 | if (y < 0) { | |
11510 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
11511 | y = -y; | |
11512 | } | |
11513 | pos |= y << CURSOR_Y_SHIFT; | |
11514 | ||
11515 | return pos; | |
11516 | } | |
11517 | ||
3637ecf0 VS |
11518 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
11519 | { | |
11520 | const struct drm_mode_config *config = | |
f90a85e7 ML |
11521 | &plane_state->uapi.plane->dev->mode_config; |
11522 | int width = drm_rect_width(&plane_state->uapi.dst); | |
11523 | int height = drm_rect_height(&plane_state->uapi.dst); | |
3637ecf0 VS |
11524 | |
11525 | return width > 0 && width <= config->cursor_width && | |
11526 | height > 0 && height <= config->cursor_height; | |
11527 | } | |
11528 | ||
fce8d235 | 11529 | static int intel_cursor_check_surface(struct intel_plane_state *plane_state) |
659056f2 | 11530 | { |
30a027dc | 11531 | struct drm_i915_private *dev_priv = |
f90a85e7 | 11532 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 11533 | unsigned int rotation = plane_state->hw.rotation; |
1e7b4fd8 VS |
11534 | int src_x, src_y; |
11535 | u32 offset; | |
fc3fed5d | 11536 | int ret; |
fce8d235 | 11537 | |
54d4d719 | 11538 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
11539 | if (ret) |
11540 | return ret; | |
11541 | ||
f90a85e7 | 11542 | if (!plane_state->uapi.visible) |
54d4d719 VS |
11543 | return 0; |
11544 | ||
f90a85e7 ML |
11545 | src_x = plane_state->uapi.src.x1 >> 16; |
11546 | src_y = plane_state->uapi.src.y1 >> 16; | |
fce8d235 VS |
11547 | |
11548 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
11549 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, | |
11550 | plane_state, 0); | |
11551 | ||
11552 | if (src_x != 0 || src_y != 0) { | |
cd49f818 WK |
11553 | drm_dbg_kms(&dev_priv->drm, |
11554 | "Arbitrary cursor panning not supported\n"); | |
fce8d235 VS |
11555 | return -EINVAL; |
11556 | } | |
11557 | ||
30a027dc VS |
11558 | /* |
11559 | * Put the final coordinates back so that the src | |
11560 | * coordinate checks will see the right values. | |
11561 | */ | |
f90a85e7 | 11562 | drm_rect_translate_to(&plane_state->uapi.src, |
30a027dc VS |
11563 | src_x << 16, src_y << 16); |
11564 | ||
11565 | /* ILK+ do this automagically in hardware */ | |
11566 | if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { | |
7b3cb17a | 11567 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 ML |
11568 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
11569 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
30a027dc VS |
11570 | |
11571 | offset += (src_h * src_w - 1) * fb->format->cpp[0]; | |
11572 | } | |
11573 | ||
fce8d235 | 11574 | plane_state->color_plane[0].offset = offset; |
30a027dc VS |
11575 | plane_state->color_plane[0].x = src_x; |
11576 | plane_state->color_plane[0].y = src_y; | |
fce8d235 VS |
11577 | |
11578 | return 0; | |
11579 | } | |
11580 | ||
11581 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, | |
11582 | struct intel_plane_state *plane_state) | |
11583 | { | |
7b3cb17a | 11584 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
cd49f818 | 11585 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); |
659056f2 VS |
11586 | int ret; |
11587 | ||
4e0b83a5 | 11588 | if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
cd49f818 | 11589 | drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); |
4e0b83a5 VS |
11590 | return -EINVAL; |
11591 | } | |
11592 | ||
f90a85e7 | 11593 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
2225f3c6 | 11594 | &crtc_state->uapi, |
a01cb8ba VS |
11595 | DRM_PLANE_HELPER_NO_SCALING, |
11596 | DRM_PLANE_HELPER_NO_SCALING, | |
11597 | true, true); | |
659056f2 VS |
11598 | if (ret) |
11599 | return ret; | |
11600 | ||
3a612765 | 11601 | /* Use the unclipped src/dst rectangles, which we program to hw */ |
f90a85e7 ML |
11602 | plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi); |
11603 | plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi); | |
3a612765 | 11604 | |
54d4d719 VS |
11605 | ret = intel_cursor_check_surface(plane_state); |
11606 | if (ret) | |
11607 | return ret; | |
11608 | ||
f90a85e7 | 11609 | if (!plane_state->uapi.visible) |
659056f2 VS |
11610 | return 0; |
11611 | ||
4e0b83a5 VS |
11612 | ret = intel_plane_check_src_coordinates(plane_state); |
11613 | if (ret) | |
11614 | return ret; | |
659056f2 VS |
11615 | |
11616 | return 0; | |
11617 | } | |
11618 | ||
ddd5713d VS |
11619 | static unsigned int |
11620 | i845_cursor_max_stride(struct intel_plane *plane, | |
11621 | u32 pixel_format, u64 modifier, | |
11622 | unsigned int rotation) | |
11623 | { | |
11624 | return 2048; | |
11625 | } | |
11626 | ||
7eb31a0b VS |
11627 | static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
11628 | { | |
5f29ab23 VS |
11629 | u32 cntl = 0; |
11630 | ||
11631 | if (crtc_state->gamma_enable) | |
11632 | cntl |= CURSOR_GAMMA_ENABLE; | |
11633 | ||
11634 | return cntl; | |
7eb31a0b VS |
11635 | } |
11636 | ||
292889e1 VS |
11637 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
11638 | const struct intel_plane_state *plane_state) | |
11639 | { | |
292889e1 | 11640 | return CURSOR_ENABLE | |
292889e1 | 11641 | CURSOR_FORMAT_ARGB | |
df79cf44 | 11642 | CURSOR_STRIDE(plane_state->color_plane[0].stride); |
292889e1 VS |
11643 | } |
11644 | ||
659056f2 VS |
11645 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
11646 | { | |
f90a85e7 | 11647 | int width = drm_rect_width(&plane_state->uapi.dst); |
659056f2 VS |
11648 | |
11649 | /* | |
11650 | * 845g/865g are only limited by the width of their cursors, | |
11651 | * the height is arbitrary up to the precision of the register. | |
11652 | */ | |
3637ecf0 | 11653 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
11654 | } |
11655 | ||
eb0f5044 | 11656 | static int i845_check_cursor(struct intel_crtc_state *crtc_state, |
659056f2 VS |
11657 | struct intel_plane_state *plane_state) |
11658 | { | |
7b3cb17a | 11659 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
cd49f818 | 11660 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); |
659056f2 VS |
11661 | int ret; |
11662 | ||
11663 | ret = intel_check_cursor(crtc_state, plane_state); | |
11664 | if (ret) | |
11665 | return ret; | |
11666 | ||
11667 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 11668 | if (!fb) |
659056f2 VS |
11669 | return 0; |
11670 | ||
11671 | /* Check for which cursor types we support */ | |
11672 | if (!i845_cursor_size_ok(plane_state)) { | |
cd49f818 WK |
11673 | drm_dbg_kms(&i915->drm, |
11674 | "Cursor dimension %dx%d not supported\n", | |
11675 | drm_rect_width(&plane_state->uapi.dst), | |
11676 | drm_rect_height(&plane_state->uapi.dst)); | |
659056f2 VS |
11677 | return -EINVAL; |
11678 | } | |
11679 | ||
e57291c2 PB |
11680 | drm_WARN_ON(&i915->drm, plane_state->uapi.visible && |
11681 | plane_state->color_plane[0].stride != fb->pitches[0]); | |
df79cf44 | 11682 | |
1e1bb871 | 11683 | switch (fb->pitches[0]) { |
292889e1 VS |
11684 | case 256: |
11685 | case 512: | |
11686 | case 1024: | |
11687 | case 2048: | |
11688 | break; | |
1e1bb871 | 11689 | default: |
cd49f818 WK |
11690 | drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", |
11691 | fb->pitches[0]); | |
1e1bb871 | 11692 | return -EINVAL; |
292889e1 VS |
11693 | } |
11694 | ||
659056f2 VS |
11695 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
11696 | ||
11697 | return 0; | |
292889e1 VS |
11698 | } |
11699 | ||
b2d03b0d VS |
11700 | static void i845_update_cursor(struct intel_plane *plane, |
11701 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 11702 | const struct intel_plane_state *plane_state) |
560b85bb | 11703 | { |
cd5dcbf1 | 11704 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
11705 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
11706 | unsigned long irqflags; | |
560b85bb | 11707 | |
f90a85e7 ML |
11708 | if (plane_state && plane_state->uapi.visible) { |
11709 | unsigned int width = drm_rect_width(&plane_state->uapi.dst); | |
11710 | unsigned int height = drm_rect_height(&plane_state->uapi.dst); | |
dc41c154 | 11711 | |
7eb31a0b VS |
11712 | cntl = plane_state->ctl | |
11713 | i845_cursor_ctl_crtc(crtc_state); | |
11714 | ||
dc41c154 | 11715 | size = (height << 12) | width; |
560b85bb | 11716 | |
b2d03b0d VS |
11717 | base = intel_cursor_base(plane_state); |
11718 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 11719 | } |
560b85bb | 11720 | |
b2d03b0d | 11721 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 11722 | |
e11ffddb VS |
11723 | /* On these chipsets we can only modify the base/size/stride |
11724 | * whilst the cursor is disabled. | |
11725 | */ | |
11726 | if (plane->cursor.base != base || | |
11727 | plane->cursor.size != size || | |
11728 | plane->cursor.cntl != cntl) { | |
dc008bf0 JN |
11729 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); |
11730 | intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); | |
11731 | intel_de_write_fw(dev_priv, CURSIZE, size); | |
11732 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); | |
11733 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); | |
75343a44 | 11734 | |
e11ffddb VS |
11735 | plane->cursor.base = base; |
11736 | plane->cursor.size = size; | |
11737 | plane->cursor.cntl = cntl; | |
11738 | } else { | |
dc008bf0 | 11739 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); |
560b85bb | 11740 | } |
e11ffddb | 11741 | |
b2d03b0d VS |
11742 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
11743 | } | |
11744 | ||
11745 | static void i845_disable_cursor(struct intel_plane *plane, | |
0dd14be3 | 11746 | const struct intel_crtc_state *crtc_state) |
b2d03b0d | 11747 | { |
0dd14be3 | 11748 | i845_update_cursor(plane, crtc_state, NULL); |
560b85bb CW |
11749 | } |
11750 | ||
eade6c89 VS |
11751 | static bool i845_cursor_get_hw_state(struct intel_plane *plane, |
11752 | enum pipe *pipe) | |
51f5a096 VS |
11753 | { |
11754 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
11755 | enum intel_display_power_domain power_domain; | |
0e6e0be4 | 11756 | intel_wakeref_t wakeref; |
51f5a096 VS |
11757 | bool ret; |
11758 | ||
11759 | power_domain = POWER_DOMAIN_PIPE(PIPE_A); | |
0e6e0be4 CW |
11760 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
11761 | if (!wakeref) | |
51f5a096 VS |
11762 | return false; |
11763 | ||
dc008bf0 | 11764 | ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
51f5a096 | 11765 | |
eade6c89 VS |
11766 | *pipe = PIPE_A; |
11767 | ||
0e6e0be4 | 11768 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
11769 | |
11770 | return ret; | |
11771 | } | |
11772 | ||
ddd5713d VS |
11773 | static unsigned int |
11774 | i9xx_cursor_max_stride(struct intel_plane *plane, | |
11775 | u32 pixel_format, u64 modifier, | |
11776 | unsigned int rotation) | |
11777 | { | |
11778 | return plane->base.dev->mode_config.cursor_width * 4; | |
11779 | } | |
11780 | ||
7eb31a0b | 11781 | static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
292889e1 | 11782 | { |
2225f3c6 | 11783 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7eb31a0b | 11784 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
c894d63c | 11785 | u32 cntl = 0; |
292889e1 | 11786 | |
7eb31a0b VS |
11787 | if (INTEL_GEN(dev_priv) >= 11) |
11788 | return cntl; | |
e876b78c | 11789 | |
5f29ab23 VS |
11790 | if (crtc_state->gamma_enable) |
11791 | cntl = MCURSOR_GAMMA_ENABLE; | |
292889e1 | 11792 | |
8271b2ef | 11793 | if (crtc_state->csc_enable) |
7eb31a0b | 11794 | cntl |= MCURSOR_PIPE_CSC_ENABLE; |
292889e1 | 11795 | |
32ea06b6 VS |
11796 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
11797 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); | |
292889e1 | 11798 | |
7eb31a0b VS |
11799 | return cntl; |
11800 | } | |
11801 | ||
11802 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, | |
11803 | const struct intel_plane_state *plane_state) | |
11804 | { | |
11805 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 11806 | to_i915(plane_state->uapi.plane->dev); |
7eb31a0b VS |
11807 | u32 cntl = 0; |
11808 | ||
11809 | if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) | |
11810 | cntl |= MCURSOR_TRICKLE_FEED_DISABLE; | |
11811 | ||
f90a85e7 | 11812 | switch (drm_rect_width(&plane_state->uapi.dst)) { |
292889e1 | 11813 | case 64: |
b99b9ec1 | 11814 | cntl |= MCURSOR_MODE_64_ARGB_AX; |
292889e1 VS |
11815 | break; |
11816 | case 128: | |
b99b9ec1 | 11817 | cntl |= MCURSOR_MODE_128_ARGB_AX; |
292889e1 VS |
11818 | break; |
11819 | case 256: | |
b99b9ec1 | 11820 | cntl |= MCURSOR_MODE_256_ARGB_AX; |
292889e1 VS |
11821 | break; |
11822 | default: | |
f90a85e7 | 11823 | MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); |
292889e1 VS |
11824 | return 0; |
11825 | } | |
11826 | ||
7b3cb17a | 11827 | if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) |
b99b9ec1 | 11828 | cntl |= MCURSOR_ROTATE_180; |
292889e1 VS |
11829 | |
11830 | return cntl; | |
11831 | } | |
11832 | ||
659056f2 | 11833 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 11834 | { |
024faac7 | 11835 | struct drm_i915_private *dev_priv = |
f90a85e7 ML |
11836 | to_i915(plane_state->uapi.plane->dev); |
11837 | int width = drm_rect_width(&plane_state->uapi.dst); | |
11838 | int height = drm_rect_height(&plane_state->uapi.dst); | |
4b0e333e | 11839 | |
3637ecf0 | 11840 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 11841 | return false; |
4398ad45 | 11842 | |
024faac7 VS |
11843 | /* Cursor width is limited to a few power-of-two sizes */ |
11844 | switch (width) { | |
659056f2 VS |
11845 | case 256: |
11846 | case 128: | |
659056f2 VS |
11847 | case 64: |
11848 | break; | |
11849 | default: | |
11850 | return false; | |
65a21cd6 | 11851 | } |
4b0e333e | 11852 | |
024faac7 VS |
11853 | /* |
11854 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
11855 | * height from 8 lines up to the cursor width, when the | |
11856 | * cursor is not rotated. Everything else requires square | |
11857 | * cursors. | |
11858 | */ | |
11859 | if (HAS_CUR_FBC(dev_priv) && | |
7b3cb17a | 11860 | plane_state->hw.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
11861 | if (height < 8 || height > width) |
11862 | return false; | |
11863 | } else { | |
11864 | if (height != width) | |
11865 | return false; | |
11866 | } | |
99d1f387 | 11867 | |
659056f2 | 11868 | return true; |
65a21cd6 JB |
11869 | } |
11870 | ||
eb0f5044 | 11871 | static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, |
659056f2 | 11872 | struct intel_plane_state *plane_state) |
cda4b7d3 | 11873 | { |
f90a85e7 | 11874 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
659056f2 | 11875 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 11876 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
659056f2 | 11877 | enum pipe pipe = plane->pipe; |
659056f2 | 11878 | int ret; |
cda4b7d3 | 11879 | |
659056f2 VS |
11880 | ret = intel_check_cursor(crtc_state, plane_state); |
11881 | if (ret) | |
11882 | return ret; | |
cda4b7d3 | 11883 | |
659056f2 | 11884 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 11885 | if (!fb) |
659056f2 | 11886 | return 0; |
55a08b3f | 11887 | |
659056f2 VS |
11888 | /* Check for which cursor types we support */ |
11889 | if (!i9xx_cursor_size_ok(plane_state)) { | |
cd49f818 WK |
11890 | drm_dbg(&dev_priv->drm, |
11891 | "Cursor dimension %dx%d not supported\n", | |
11892 | drm_rect_width(&plane_state->uapi.dst), | |
11893 | drm_rect_height(&plane_state->uapi.dst)); | |
659056f2 | 11894 | return -EINVAL; |
cda4b7d3 | 11895 | } |
cda4b7d3 | 11896 | |
e57291c2 PB |
11897 | drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && |
11898 | plane_state->color_plane[0].stride != fb->pitches[0]); | |
df79cf44 | 11899 | |
3a612765 | 11900 | if (fb->pitches[0] != |
f90a85e7 | 11901 | drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { |
cd49f818 WK |
11902 | drm_dbg_kms(&dev_priv->drm, |
11903 | "Invalid cursor stride (%u) (cursor width %d)\n", | |
11904 | fb->pitches[0], | |
11905 | drm_rect_width(&plane_state->uapi.dst)); | |
1e1bb871 | 11906 | return -EINVAL; |
659056f2 | 11907 | } |
dd584fc0 | 11908 | |
659056f2 VS |
11909 | /* |
11910 | * There's something wrong with the cursor on CHV pipe C. | |
11911 | * If it straddles the left edge of the screen then | |
11912 | * moving it away from the edge or disabling it often | |
11913 | * results in a pipe underrun, and often that can lead to | |
11914 | * dead pipe (constant underrun reported, and it scans | |
11915 | * out just a solid color). To recover from that, the | |
11916 | * display power well must be turned off and on again. | |
11917 | * Refuse the put the cursor into that compromised position. | |
11918 | */ | |
11919 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
f90a85e7 | 11920 | plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { |
cd49f818 WK |
11921 | drm_dbg_kms(&dev_priv->drm, |
11922 | "CHV cursor C not allowed to straddle the left screen edge\n"); | |
659056f2 VS |
11923 | return -EINVAL; |
11924 | } | |
5efb3e28 | 11925 | |
659056f2 | 11926 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 11927 | |
659056f2 | 11928 | return 0; |
cda4b7d3 CW |
11929 | } |
11930 | ||
b2d03b0d VS |
11931 | static void i9xx_update_cursor(struct intel_plane *plane, |
11932 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 11933 | const struct intel_plane_state *plane_state) |
dc41c154 | 11934 | { |
cd5dcbf1 VS |
11935 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
11936 | enum pipe pipe = plane->pipe; | |
024faac7 | 11937 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 11938 | unsigned long irqflags; |
dc41c154 | 11939 | |
f90a85e7 ML |
11940 | if (plane_state && plane_state->uapi.visible) { |
11941 | unsigned width = drm_rect_width(&plane_state->uapi.dst); | |
11942 | unsigned height = drm_rect_height(&plane_state->uapi.dst); | |
3a612765 | 11943 | |
7eb31a0b VS |
11944 | cntl = plane_state->ctl | |
11945 | i9xx_cursor_ctl_crtc(crtc_state); | |
dc41c154 | 11946 | |
3a612765 ML |
11947 | if (width != height) |
11948 | fbc_ctl = CUR_FBC_CTL_EN | (height - 1); | |
dc41c154 | 11949 | |
b2d03b0d VS |
11950 | base = intel_cursor_base(plane_state); |
11951 | pos = intel_cursor_position(plane_state); | |
11952 | } | |
11953 | ||
11954 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
11955 | ||
e11ffddb VS |
11956 | /* |
11957 | * On some platforms writing CURCNTR first will also | |
11958 | * cause CURPOS to be armed by the CURBASE write. | |
11959 | * Without the CURCNTR write the CURPOS write would | |
83234d13 VS |
11960 | * arm itself. Thus we always update CURCNTR before |
11961 | * CURPOS. | |
8753d2bc VS |
11962 | * |
11963 | * On other platforms CURPOS always requires the | |
11964 | * CURBASE write to arm the update. Additonally | |
11965 | * a write to any of the cursor register will cancel | |
11966 | * an already armed cursor update. Thus leaving out | |
11967 | * the CURBASE write after CURPOS could lead to a | |
11968 | * cursor that doesn't appear to move, or even change | |
11969 | * shape. Thus we always write CURBASE. | |
e11ffddb | 11970 | * |
83234d13 VS |
11971 | * The other registers are armed by by the CURBASE write |
11972 | * except when the plane is getting enabled at which time | |
11973 | * the CURCNTR write arms the update. | |
e11ffddb | 11974 | */ |
ff43bc37 VS |
11975 | |
11976 | if (INTEL_GEN(dev_priv) >= 9) | |
11977 | skl_write_cursor_wm(plane, crtc_state); | |
11978 | ||
0bcbcba7 JRS |
11979 | if (!needs_modeset(crtc_state)) |
11980 | intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); | |
11981 | ||
e11ffddb VS |
11982 | if (plane->cursor.base != base || |
11983 | plane->cursor.size != fbc_ctl || | |
11984 | plane->cursor.cntl != cntl) { | |
e11ffddb | 11985 | if (HAS_CUR_FBC(dev_priv)) |
dc008bf0 JN |
11986 | intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), |
11987 | fbc_ctl); | |
11988 | intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); | |
11989 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); | |
11990 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
75343a44 | 11991 | |
e11ffddb VS |
11992 | plane->cursor.base = base; |
11993 | plane->cursor.size = fbc_ctl; | |
11994 | plane->cursor.cntl = cntl; | |
dc41c154 | 11995 | } else { |
dc008bf0 JN |
11996 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); |
11997 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
dc41c154 VS |
11998 | } |
11999 | ||
b2d03b0d | 12000 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
12001 | } |
12002 | ||
b2d03b0d | 12003 | static void i9xx_disable_cursor(struct intel_plane *plane, |
0dd14be3 | 12004 | const struct intel_crtc_state *crtc_state) |
cda4b7d3 | 12005 | { |
0dd14be3 | 12006 | i9xx_update_cursor(plane, crtc_state, NULL); |
dc41c154 VS |
12007 | } |
12008 | ||
eade6c89 VS |
12009 | static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, |
12010 | enum pipe *pipe) | |
51f5a096 VS |
12011 | { |
12012 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
12013 | enum intel_display_power_domain power_domain; | |
0e6e0be4 | 12014 | intel_wakeref_t wakeref; |
51f5a096 | 12015 | bool ret; |
eade6c89 | 12016 | u32 val; |
51f5a096 VS |
12017 | |
12018 | /* | |
12019 | * Not 100% correct for planes that can move between pipes, | |
12020 | * but that's only the case for gen2-3 which don't have any | |
12021 | * display power wells. | |
12022 | */ | |
eade6c89 | 12023 | power_domain = POWER_DOMAIN_PIPE(plane->pipe); |
0e6e0be4 CW |
12024 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
12025 | if (!wakeref) | |
51f5a096 VS |
12026 | return false; |
12027 | ||
dc008bf0 | 12028 | val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); |
eade6c89 | 12029 | |
b99b9ec1 | 12030 | ret = val & MCURSOR_MODE; |
eade6c89 VS |
12031 | |
12032 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
12033 | *pipe = plane->pipe; | |
12034 | else | |
12035 | *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> | |
12036 | MCURSOR_PIPE_SELECT_SHIFT; | |
51f5a096 | 12037 | |
0e6e0be4 | 12038 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
12039 | |
12040 | return ret; | |
12041 | } | |
dc41c154 | 12042 | |
79e53945 | 12043 | /* VESA 640x480x72Hz mode to set on the pipe */ |
bacdcd55 | 12044 | static const struct drm_display_mode load_detect_mode = { |
79e53945 JB |
12045 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
12046 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
12047 | }; | |
12048 | ||
a8bb6818 | 12049 | struct drm_framebuffer * |
24dbf51a CW |
12050 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
12051 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
12052 | { |
12053 | struct intel_framebuffer *intel_fb; | |
12054 | int ret; | |
12055 | ||
12056 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 12057 | if (!intel_fb) |
d2dff872 | 12058 | return ERR_PTR(-ENOMEM); |
d2dff872 | 12059 | |
24dbf51a | 12060 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
12061 | if (ret) |
12062 | goto err; | |
d2dff872 CW |
12063 | |
12064 | return &intel_fb->base; | |
dcb1394e | 12065 | |
dd4916c5 | 12066 | err: |
dd4916c5 | 12067 | kfree(intel_fb); |
dd4916c5 | 12068 | return ERR_PTR(ret); |
d2dff872 CW |
12069 | } |
12070 | ||
20bdc112 VS |
12071 | static int intel_modeset_disable_planes(struct drm_atomic_state *state, |
12072 | struct drm_crtc *crtc) | |
d3a40d1b | 12073 | { |
20bdc112 | 12074 | struct drm_plane *plane; |
d3a40d1b | 12075 | struct drm_plane_state *plane_state; |
20bdc112 | 12076 | int ret, i; |
d3a40d1b | 12077 | |
20bdc112 | 12078 | ret = drm_atomic_add_affected_planes(state, crtc); |
d3a40d1b ACO |
12079 | if (ret) |
12080 | return ret; | |
20bdc112 VS |
12081 | |
12082 | for_each_new_plane_in_state(state, plane, plane_state, i) { | |
12083 | if (plane_state->crtc != crtc) | |
12084 | continue; | |
12085 | ||
12086 | ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); | |
12087 | if (ret) | |
12088 | return ret; | |
12089 | ||
12090 | drm_atomic_set_fb_for_plane(plane_state, NULL); | |
12091 | } | |
d3a40d1b ACO |
12092 | |
12093 | return 0; | |
12094 | } | |
12095 | ||
6c5ed5ae | 12096 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
6c5ed5ae ML |
12097 | struct intel_load_detect_pipe *old, |
12098 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
12099 | { |
12100 | struct intel_crtc *intel_crtc; | |
d2434ab7 | 12101 | struct intel_encoder *intel_encoder = |
43a6d19c | 12102 | intel_attached_encoder(to_intel_connector(connector)); |
79e53945 | 12103 | struct drm_crtc *possible_crtc; |
4ef69c7a | 12104 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
12105 | struct drm_crtc *crtc = NULL; |
12106 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 12107 | struct drm_i915_private *dev_priv = to_i915(dev); |
51fd371b | 12108 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 12109 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 12110 | struct drm_connector_state *connector_state; |
4be07317 | 12111 | struct intel_crtc_state *crtc_state; |
51fd371b | 12112 | int ret, i = -1; |
79e53945 | 12113 | |
cd49f818 WK |
12114 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
12115 | connector->base.id, connector->name, | |
12116 | encoder->base.id, encoder->name); | |
d2dff872 | 12117 | |
edde3617 ML |
12118 | old->restore_state = NULL; |
12119 | ||
e57291c2 | 12120 | drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 12121 | |
79e53945 JB |
12122 | /* |
12123 | * Algorithm gets a little messy: | |
7a5e4805 | 12124 | * |
79e53945 JB |
12125 | * - if the connector already has an assigned crtc, use it (but make |
12126 | * sure it's on first) | |
7a5e4805 | 12127 | * |
79e53945 JB |
12128 | * - try to find the first unused crtc that can drive this connector, |
12129 | * and use that if we find one | |
79e53945 JB |
12130 | */ |
12131 | ||
12132 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
12133 | if (connector->state->crtc) { |
12134 | crtc = connector->state->crtc; | |
8261b191 | 12135 | |
51fd371b | 12136 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 12137 | if (ret) |
ad3c558f | 12138 | goto fail; |
8261b191 CW |
12139 | |
12140 | /* Make sure the crtc and connector are running */ | |
edde3617 | 12141 | goto found; |
79e53945 JB |
12142 | } |
12143 | ||
12144 | /* Find an unused one (if possible) */ | |
70e1e0ec | 12145 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
12146 | i++; |
12147 | if (!(encoder->possible_crtcs & (1 << i))) | |
12148 | continue; | |
edde3617 ML |
12149 | |
12150 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
12151 | if (ret) | |
12152 | goto fail; | |
12153 | ||
12154 | if (possible_crtc->state->enable) { | |
12155 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 12156 | continue; |
edde3617 | 12157 | } |
a459249c VS |
12158 | |
12159 | crtc = possible_crtc; | |
12160 | break; | |
79e53945 JB |
12161 | } |
12162 | ||
12163 | /* | |
12164 | * If we didn't find an unused CRTC, don't use any. | |
12165 | */ | |
12166 | if (!crtc) { | |
cd49f818 WK |
12167 | drm_dbg_kms(&dev_priv->drm, |
12168 | "no pipe available for load-detect\n"); | |
f4bf77b4 | 12169 | ret = -ENODEV; |
ad3c558f | 12170 | goto fail; |
79e53945 JB |
12171 | } |
12172 | ||
edde3617 ML |
12173 | found: |
12174 | intel_crtc = to_intel_crtc(crtc); | |
12175 | ||
83a57153 | 12176 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
12177 | restore_state = drm_atomic_state_alloc(dev); |
12178 | if (!state || !restore_state) { | |
12179 | ret = -ENOMEM; | |
12180 | goto fail; | |
12181 | } | |
83a57153 ACO |
12182 | |
12183 | state->acquire_ctx = ctx; | |
edde3617 | 12184 | restore_state->acquire_ctx = ctx; |
83a57153 | 12185 | |
944b0c76 ACO |
12186 | connector_state = drm_atomic_get_connector_state(state, connector); |
12187 | if (IS_ERR(connector_state)) { | |
12188 | ret = PTR_ERR(connector_state); | |
12189 | goto fail; | |
12190 | } | |
12191 | ||
edde3617 ML |
12192 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
12193 | if (ret) | |
12194 | goto fail; | |
944b0c76 | 12195 | |
4be07317 ACO |
12196 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
12197 | if (IS_ERR(crtc_state)) { | |
12198 | ret = PTR_ERR(crtc_state); | |
12199 | goto fail; | |
12200 | } | |
12201 | ||
aa42a50a | 12202 | crtc_state->uapi.active = true; |
4be07317 | 12203 | |
2225f3c6 | 12204 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, |
25f89954 | 12205 | &load_detect_mode); |
d3a40d1b ACO |
12206 | if (ret) |
12207 | goto fail; | |
12208 | ||
20bdc112 | 12209 | ret = intel_modeset_disable_planes(state, crtc); |
edde3617 ML |
12210 | if (ret) |
12211 | goto fail; | |
12212 | ||
12213 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
12214 | if (!ret) | |
12215 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
be90cc31 VS |
12216 | if (!ret) |
12217 | ret = drm_atomic_add_affected_planes(restore_state, crtc); | |
edde3617 | 12218 | if (ret) { |
cd49f818 WK |
12219 | drm_dbg_kms(&dev_priv->drm, |
12220 | "Failed to create a copy of old state to restore: %i\n", | |
12221 | ret); | |
edde3617 ML |
12222 | goto fail; |
12223 | } | |
8c7b5ccb | 12224 | |
3ba86073 ML |
12225 | ret = drm_atomic_commit(state); |
12226 | if (ret) { | |
cd49f818 WK |
12227 | drm_dbg_kms(&dev_priv->drm, |
12228 | "failed to set mode on load-detect pipe\n"); | |
412b61d8 | 12229 | goto fail; |
79e53945 | 12230 | } |
edde3617 ML |
12231 | |
12232 | old->restore_state = restore_state; | |
7abbd11f | 12233 | drm_atomic_state_put(state); |
7173188d | 12234 | |
79e53945 | 12235 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 12236 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 12237 | return true; |
412b61d8 | 12238 | |
ad3c558f | 12239 | fail: |
7fb71c8f CW |
12240 | if (state) { |
12241 | drm_atomic_state_put(state); | |
12242 | state = NULL; | |
12243 | } | |
12244 | if (restore_state) { | |
12245 | drm_atomic_state_put(restore_state); | |
12246 | restore_state = NULL; | |
12247 | } | |
83a57153 | 12248 | |
6c5ed5ae ML |
12249 | if (ret == -EDEADLK) |
12250 | return ret; | |
51fd371b | 12251 | |
412b61d8 | 12252 | return false; |
79e53945 JB |
12253 | } |
12254 | ||
d2434ab7 | 12255 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
12256 | struct intel_load_detect_pipe *old, |
12257 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 12258 | { |
d2434ab7 | 12259 | struct intel_encoder *intel_encoder = |
43a6d19c | 12260 | intel_attached_encoder(to_intel_connector(connector)); |
cd49f818 | 12261 | struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); |
4ef69c7a | 12262 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 12263 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 12264 | int ret; |
79e53945 | 12265 | |
cd49f818 WK |
12266 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
12267 | connector->base.id, connector->name, | |
12268 | encoder->base.id, encoder->name); | |
d2dff872 | 12269 | |
edde3617 | 12270 | if (!state) |
0622a53c | 12271 | return; |
79e53945 | 12272 | |
581e49fe | 12273 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 12274 | if (ret) |
cd49f818 WK |
12275 | drm_dbg_kms(&i915->drm, |
12276 | "Couldn't release load detect pipe: %i\n", ret); | |
0853695c | 12277 | drm_atomic_state_put(state); |
79e53945 JB |
12278 | } |
12279 | ||
da4a1efa | 12280 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 12281 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 12282 | { |
fac5e23e | 12283 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
12284 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
12285 | ||
12286 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 12287 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 12288 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 12289 | return 120000; |
cf819eff | 12290 | else if (!IS_GEN(dev_priv, 2)) |
da4a1efa VS |
12291 | return 96000; |
12292 | else | |
12293 | return 48000; | |
12294 | } | |
12295 | ||
79e53945 | 12296 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 12297 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 12298 | struct intel_crtc_state *pipe_config) |
79e53945 | 12299 | { |
f1f644dc | 12300 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 12301 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 12302 | enum pipe pipe = crtc->pipe; |
293623f7 | 12303 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 12304 | u32 fp; |
9e2c8475 | 12305 | struct dpll clock; |
dccbea3b | 12306 | int port_clock; |
da4a1efa | 12307 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
12308 | |
12309 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 12310 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 12311 | else |
293623f7 | 12312 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
12313 | |
12314 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 12315 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
12316 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
12317 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
12318 | } else { |
12319 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
12320 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
12321 | } | |
12322 | ||
cf819eff | 12323 | if (!IS_GEN(dev_priv, 2)) { |
9b1e14f4 | 12324 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
12325 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
12326 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
12327 | else |
12328 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
12329 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
12330 | ||
12331 | switch (dpll & DPLL_MODE_MASK) { | |
12332 | case DPLLB_MODE_DAC_SERIAL: | |
12333 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
12334 | 5 : 10; | |
12335 | break; | |
12336 | case DPLLB_MODE_LVDS: | |
12337 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
12338 | 7 : 14; | |
12339 | break; | |
12340 | default: | |
cd49f818 WK |
12341 | drm_dbg_kms(&dev_priv->drm, |
12342 | "Unknown DPLL mode %08x in programmed " | |
12343 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
f1f644dc | 12344 | return; |
79e53945 JB |
12345 | } |
12346 | ||
9b1e14f4 | 12347 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 12348 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 12349 | else |
dccbea3b | 12350 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 12351 | } else { |
dc008bf0 JN |
12352 | u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv, |
12353 | LVDS); | |
b1c560d1 | 12354 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
12355 | |
12356 | if (is_lvds) { | |
12357 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
12358 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
12359 | |
12360 | if (lvds & LVDS_CLKB_POWER_UP) | |
12361 | clock.p2 = 7; | |
12362 | else | |
12363 | clock.p2 = 14; | |
79e53945 JB |
12364 | } else { |
12365 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
12366 | clock.p1 = 2; | |
12367 | else { | |
12368 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
12369 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
12370 | } | |
12371 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
12372 | clock.p2 = 4; | |
12373 | else | |
12374 | clock.p2 = 2; | |
79e53945 | 12375 | } |
da4a1efa | 12376 | |
dccbea3b | 12377 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
12378 | } |
12379 | ||
18442d08 VS |
12380 | /* |
12381 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 12382 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
12383 | * encoder's get_config() function. |
12384 | */ | |
dccbea3b | 12385 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
12386 | } |
12387 | ||
6878da05 VS |
12388 | int intel_dotclock_calculate(int link_freq, |
12389 | const struct intel_link_m_n *m_n) | |
f1f644dc | 12390 | { |
f1f644dc JB |
12391 | /* |
12392 | * The calculation for the data clock is: | |
1041a02f | 12393 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 12394 | * But we want to avoid losing precison if possible, so: |
1041a02f | 12395 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
12396 | * |
12397 | * and the link clock is simpler: | |
1041a02f | 12398 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
12399 | */ |
12400 | ||
6878da05 VS |
12401 | if (!m_n->link_n) |
12402 | return 0; | |
f1f644dc | 12403 | |
3123698f | 12404 | return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); |
6878da05 | 12405 | } |
f1f644dc | 12406 | |
9eae5e27 LDM |
12407 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
12408 | struct intel_crtc_state *pipe_config) | |
6878da05 | 12409 | { |
e3b247da | 12410 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 12411 | |
18442d08 VS |
12412 | /* read out port_clock from the DPLL */ |
12413 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 12414 | |
f1f644dc | 12415 | /* |
e3b247da VS |
12416 | * In case there is an active pipe without active ports, |
12417 | * we may need some idea for the dotclock anyway. | |
12418 | * Calculate one based on the FDI configuration. | |
79e53945 | 12419 | */ |
1326a92c | 12420 | pipe_config->hw.adjusted_mode.crtc_clock = |
21a727b3 | 12421 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 12422 | &pipe_config->fdi_m_n); |
79e53945 JB |
12423 | } |
12424 | ||
979e94c1 VS |
12425 | static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, |
12426 | struct intel_crtc *crtc) | |
12427 | { | |
12428 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
12429 | ||
12430 | __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); | |
12431 | ||
12432 | crtc_state->cpu_transcoder = INVALID_TRANSCODER; | |
12433 | crtc_state->master_transcoder = INVALID_TRANSCODER; | |
12434 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; | |
12435 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID; | |
12436 | crtc_state->scaler_state.scaler_id = -1; | |
6671c367 | 12437 | crtc_state->mst_master_transcoder = INVALID_TRANSCODER; |
979e94c1 VS |
12438 | } |
12439 | ||
216383e9 VS |
12440 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) |
12441 | { | |
12442 | struct intel_crtc_state *crtc_state; | |
12443 | ||
12444 | crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); | |
12445 | ||
12446 | if (crtc_state) | |
12447 | intel_crtc_state_reset(crtc_state, crtc); | |
12448 | ||
12449 | return crtc_state; | |
12450 | } | |
12451 | ||
de330815 VS |
12452 | /* Returns the currently programmed mode of the given encoder. */ |
12453 | struct drm_display_mode * | |
12454 | intel_encoder_current_mode(struct intel_encoder *encoder) | |
79e53945 | 12455 | { |
de330815 VS |
12456 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
12457 | struct intel_crtc_state *crtc_state; | |
79e53945 | 12458 | struct drm_display_mode *mode; |
de330815 VS |
12459 | struct intel_crtc *crtc; |
12460 | enum pipe pipe; | |
12461 | ||
12462 | if (!encoder->get_hw_state(encoder, &pipe)) | |
12463 | return NULL; | |
12464 | ||
12465 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
79e53945 JB |
12466 | |
12467 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
12468 | if (!mode) | |
12469 | return NULL; | |
12470 | ||
216383e9 | 12471 | crtc_state = intel_crtc_state_alloc(crtc); |
de330815 | 12472 | if (!crtc_state) { |
3f36b937 TU |
12473 | kfree(mode); |
12474 | return NULL; | |
12475 | } | |
12476 | ||
11f9af16 | 12477 | if (!intel_crtc_get_pipe_config(crtc_state)) { |
de330815 VS |
12478 | kfree(crtc_state); |
12479 | kfree(mode); | |
12480 | return NULL; | |
12481 | } | |
e30a154b | 12482 | |
65c1ed30 | 12483 | intel_encoder_get_config(encoder, crtc_state); |
79e53945 | 12484 | |
33574ec9 | 12485 | intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); |
79e53945 | 12486 | |
de330815 | 12487 | kfree(crtc_state); |
3f36b937 | 12488 | |
79e53945 JB |
12489 | return mode; |
12490 | } | |
12491 | ||
12492 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
12493 | { | |
12494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12495 | ||
12496 | drm_crtc_cleanup(crtc); | |
12497 | kfree(intel_crtc); | |
12498 | } | |
12499 | ||
5a21b665 DV |
12500 | /** |
12501 | * intel_wm_need_update - Check whether watermarks need updating | |
6bf19817 CW |
12502 | * @cur: current plane state |
12503 | * @new: new plane state | |
5a21b665 DV |
12504 | * |
12505 | * Check current plane state versus the new one to determine whether | |
12506 | * watermarks need to be recalculated. | |
12507 | * | |
12508 | * Returns true or false. | |
12509 | */ | |
4f25720b | 12510 | static bool intel_wm_need_update(const struct intel_plane_state *cur, |
cd1d3ee9 | 12511 | struct intel_plane_state *new) |
5a21b665 | 12512 | { |
5a21b665 | 12513 | /* Update watermarks on tiling or size changes. */ |
f90a85e7 | 12514 | if (new->uapi.visible != cur->uapi.visible) |
5a21b665 DV |
12515 | return true; |
12516 | ||
7b3cb17a | 12517 | if (!cur->hw.fb || !new->hw.fb) |
5a21b665 DV |
12518 | return false; |
12519 | ||
7b3cb17a ML |
12520 | if (cur->hw.fb->modifier != new->hw.fb->modifier || |
12521 | cur->hw.rotation != new->hw.rotation || | |
f90a85e7 ML |
12522 | drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) || |
12523 | drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) || | |
12524 | drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) || | |
12525 | drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst)) | |
5a21b665 DV |
12526 | return true; |
12527 | ||
12528 | return false; | |
12529 | } | |
12530 | ||
b2b55502 | 12531 | static bool needs_scaling(const struct intel_plane_state *state) |
5a21b665 | 12532 | { |
f90a85e7 ML |
12533 | int src_w = drm_rect_width(&state->uapi.src) >> 16; |
12534 | int src_h = drm_rect_height(&state->uapi.src) >> 16; | |
12535 | int dst_w = drm_rect_width(&state->uapi.dst); | |
12536 | int dst_h = drm_rect_height(&state->uapi.dst); | |
5a21b665 DV |
12537 | |
12538 | return (src_w != dst_w || src_h != dst_h); | |
12539 | } | |
d21fbe87 | 12540 | |
b2b55502 | 12541 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
4f25720b | 12542 | struct intel_crtc_state *crtc_state, |
b2b55502 | 12543 | const struct intel_plane_state *old_plane_state, |
4f25720b | 12544 | struct intel_plane_state *plane_state) |
da20eabd | 12545 | { |
2225f3c6 | 12546 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f90a85e7 | 12547 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4f25720b ML |
12548 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
12549 | bool mode_changed = needs_modeset(crtc_state); | |
1326a92c ML |
12550 | bool was_crtc_enabled = old_crtc_state->hw.active; |
12551 | bool is_crtc_enabled = crtc_state->hw.active; | |
da20eabd | 12552 | bool turn_off, turn_on, visible, was_visible; |
78108b7c | 12553 | int ret; |
da20eabd | 12554 | |
e9728bd8 | 12555 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
4f25720b | 12556 | ret = skl_update_scaler_plane(crtc_state, plane_state); |
da20eabd ML |
12557 | if (ret) |
12558 | return ret; | |
12559 | } | |
12560 | ||
f90a85e7 ML |
12561 | was_visible = old_plane_state->uapi.visible; |
12562 | visible = plane_state->uapi.visible; | |
da20eabd | 12563 | |
e57291c2 | 12564 | if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) |
da20eabd ML |
12565 | was_visible = false; |
12566 | ||
35c08f43 ML |
12567 | /* |
12568 | * Visibility is calculated as if the crtc was on, but | |
12569 | * after scaler setup everything depends on it being off | |
12570 | * when the crtc isn't active. | |
f818ffea VS |
12571 | * |
12572 | * FIXME this is wrong for watermarks. Watermarks should also | |
12573 | * be computed as if the pipe would be active. Perhaps move | |
12574 | * per-plane wm computation to the .check_plane() hook, and | |
12575 | * only combine the results from all planes in the current place? | |
35c08f43 | 12576 | */ |
e9728bd8 | 12577 | if (!is_crtc_enabled) { |
cb1824bb VS |
12578 | intel_plane_set_invisible(crtc_state, plane_state); |
12579 | visible = false; | |
e9728bd8 | 12580 | } |
da20eabd ML |
12581 | |
12582 | if (!was_visible && !visible) | |
12583 | return 0; | |
12584 | ||
12585 | turn_off = was_visible && (!visible || mode_changed); | |
12586 | turn_on = visible && (!was_visible || mode_changed); | |
12587 | ||
cd49f818 WK |
12588 | drm_dbg_atomic(&dev_priv->drm, |
12589 | "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", | |
12590 | crtc->base.base.id, crtc->base.name, | |
12591 | plane->base.base.id, plane->base.name, | |
12592 | was_visible, visible, | |
12593 | turn_off, turn_on, mode_changed); | |
da20eabd | 12594 | |
caed361d | 12595 | if (turn_on) { |
04548cba | 12596 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
4f25720b | 12597 | crtc_state->update_wm_pre = true; |
caed361d VS |
12598 | |
12599 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 12600 | if (plane->id != PLANE_CURSOR) |
4f25720b | 12601 | crtc_state->disable_cxsr = true; |
caed361d | 12602 | } else if (turn_off) { |
04548cba | 12603 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
4f25720b | 12604 | crtc_state->update_wm_post = true; |
92826fcd | 12605 | |
852eb00d | 12606 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 12607 | if (plane->id != PLANE_CURSOR) |
4f25720b ML |
12608 | crtc_state->disable_cxsr = true; |
12609 | } else if (intel_wm_need_update(old_plane_state, plane_state)) { | |
04548cba | 12610 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df | 12611 | /* FIXME bollocks */ |
4f25720b ML |
12612 | crtc_state->update_wm_pre = true; |
12613 | crtc_state->update_wm_post = true; | |
b4ede6df | 12614 | } |
852eb00d | 12615 | } |
da20eabd | 12616 | |
8be6ca85 | 12617 | if (visible || was_visible) |
4f25720b | 12618 | crtc_state->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 12619 | |
31ae71fc | 12620 | /* |
8e7a4424 VS |
12621 | * ILK/SNB DVSACNTR/Sprite Enable |
12622 | * IVB SPR_CTL/Sprite Enable | |
12623 | * "When in Self Refresh Big FIFO mode, a write to enable the | |
12624 | * plane will be internally buffered and delayed while Big FIFO | |
12625 | * mode is exiting." | |
12626 | * | |
12627 | * Which means that enabling the sprite can take an extra frame | |
12628 | * when we start in big FIFO mode (LP1+). Thus we need to drop | |
12629 | * down to LP0 and wait for vblank in order to make sure the | |
12630 | * sprite gets enabled on the next vblank after the register write. | |
12631 | * Doing otherwise would risk enabling the sprite one frame after | |
12632 | * we've already signalled flip completion. We can resume LP1+ | |
12633 | * once the sprite has been enabled. | |
12634 | * | |
12635 | * | |
31ae71fc | 12636 | * WaCxSRDisabledForSpriteScaling:ivb |
8e7a4424 VS |
12637 | * IVB SPR_SCALE/Scaling Enable |
12638 | * "Low Power watermarks must be disabled for at least one | |
12639 | * frame before enabling sprite scaling, and kept disabled | |
12640 | * until sprite scaling is disabled." | |
12641 | * | |
12642 | * ILK/SNB DVSASCALE/Scaling Enable | |
12643 | * "When in Self Refresh Big FIFO mode, scaling enable will be | |
12644 | * masked off while Big FIFO mode is exiting." | |
31ae71fc | 12645 | * |
8e7a4424 VS |
12646 | * Despite the w/a only being listed for IVB we assume that |
12647 | * the ILK/SNB note has similar ramifications, hence we apply | |
12648 | * the w/a on all three platforms. | |
d8af3270 JPH |
12649 | * |
12650 | * With experimental results seems this is needed also for primary | |
12651 | * plane, not only sprite plane. | |
31ae71fc | 12652 | */ |
d8af3270 | 12653 | if (plane->id != PLANE_CURSOR && |
f3ce44a0 | 12654 | (IS_GEN_RANGE(dev_priv, 5, 6) || |
8e7a4424 VS |
12655 | IS_IVYBRIDGE(dev_priv)) && |
12656 | (turn_on || (!needs_scaling(old_plane_state) && | |
4f25720b ML |
12657 | needs_scaling(plane_state)))) |
12658 | crtc_state->disable_lp_wm = true; | |
d21fbe87 | 12659 | |
da20eabd ML |
12660 | return 0; |
12661 | } | |
12662 | ||
6d3a1ce7 ML |
12663 | static bool encoders_cloneable(const struct intel_encoder *a, |
12664 | const struct intel_encoder *b) | |
12665 | { | |
12666 | /* masks could be asymmetric, so check both ways */ | |
12667 | return a == b || (a->cloneable & (1 << b->type) && | |
12668 | b->cloneable & (1 << a->type)); | |
12669 | } | |
12670 | ||
aa07c1d3 | 12671 | static bool check_single_encoder_cloning(struct intel_atomic_state *state, |
6d3a1ce7 ML |
12672 | struct intel_crtc *crtc, |
12673 | struct intel_encoder *encoder) | |
12674 | { | |
12675 | struct intel_encoder *source_encoder; | |
12676 | struct drm_connector *connector; | |
12677 | struct drm_connector_state *connector_state; | |
12678 | int i; | |
12679 | ||
aa07c1d3 | 12680 | for_each_new_connector_in_state(&state->base, connector, connector_state, i) { |
6d3a1ce7 ML |
12681 | if (connector_state->crtc != &crtc->base) |
12682 | continue; | |
12683 | ||
12684 | source_encoder = | |
12685 | to_intel_encoder(connector_state->best_encoder); | |
12686 | if (!encoders_cloneable(encoder, source_encoder)) | |
12687 | return false; | |
12688 | } | |
12689 | ||
12690 | return true; | |
12691 | } | |
12692 | ||
1ab554b0 ML |
12693 | static int icl_add_linked_planes(struct intel_atomic_state *state) |
12694 | { | |
12695 | struct intel_plane *plane, *linked; | |
12696 | struct intel_plane_state *plane_state, *linked_plane_state; | |
12697 | int i; | |
12698 | ||
12699 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
c47b7ddb | 12700 | linked = plane_state->planar_linked_plane; |
1ab554b0 ML |
12701 | |
12702 | if (!linked) | |
12703 | continue; | |
12704 | ||
12705 | linked_plane_state = intel_atomic_get_plane_state(state, linked); | |
12706 | if (IS_ERR(linked_plane_state)) | |
12707 | return PTR_ERR(linked_plane_state); | |
12708 | ||
ce04ecd9 PB |
12709 | drm_WARN_ON(state->base.dev, |
12710 | linked_plane_state->planar_linked_plane != plane); | |
12711 | drm_WARN_ON(state->base.dev, | |
12712 | linked_plane_state->planar_slave == plane_state->planar_slave); | |
1ab554b0 ML |
12713 | } |
12714 | ||
12715 | return 0; | |
12716 | } | |
12717 | ||
12718 | static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) | |
12719 | { | |
2225f3c6 | 12720 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1ab554b0 | 12721 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2225f3c6 | 12722 | struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); |
1ab554b0 ML |
12723 | struct intel_plane *plane, *linked; |
12724 | struct intel_plane_state *plane_state; | |
12725 | int i; | |
12726 | ||
12727 | if (INTEL_GEN(dev_priv) < 11) | |
12728 | return 0; | |
12729 | ||
12730 | /* | |
12731 | * Destroy all old plane links and make the slave plane invisible | |
12732 | * in the crtc_state->active_planes mask. | |
12733 | */ | |
12734 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
c47b7ddb | 12735 | if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) |
1ab554b0 ML |
12736 | continue; |
12737 | ||
c47b7ddb | 12738 | plane_state->planar_linked_plane = NULL; |
f90a85e7 | 12739 | if (plane_state->planar_slave && !plane_state->uapi.visible) { |
1ab554b0 | 12740 | crtc_state->active_planes &= ~BIT(plane->id); |
afbd8a72 VS |
12741 | crtc_state->update_planes |= BIT(plane->id); |
12742 | } | |
1ab554b0 | 12743 | |
c47b7ddb | 12744 | plane_state->planar_slave = false; |
1ab554b0 ML |
12745 | } |
12746 | ||
12747 | if (!crtc_state->nv12_planes) | |
12748 | return 0; | |
12749 | ||
12750 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
12751 | struct intel_plane_state *linked_state = NULL; | |
12752 | ||
12753 | if (plane->pipe != crtc->pipe || | |
12754 | !(crtc_state->nv12_planes & BIT(plane->id))) | |
12755 | continue; | |
12756 | ||
12757 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { | |
99e2d8bc | 12758 | if (!icl_is_nv12_y_plane(dev_priv, linked->id)) |
1ab554b0 ML |
12759 | continue; |
12760 | ||
12761 | if (crtc_state->active_planes & BIT(linked->id)) | |
12762 | continue; | |
12763 | ||
12764 | linked_state = intel_atomic_get_plane_state(state, linked); | |
12765 | if (IS_ERR(linked_state)) | |
12766 | return PTR_ERR(linked_state); | |
12767 | ||
12768 | break; | |
12769 | } | |
12770 | ||
12771 | if (!linked_state) { | |
cd49f818 WK |
12772 | drm_dbg_kms(&dev_priv->drm, |
12773 | "Need %d free Y planes for planar YUV\n", | |
12774 | hweight8(crtc_state->nv12_planes)); | |
1ab554b0 ML |
12775 | |
12776 | return -EINVAL; | |
12777 | } | |
12778 | ||
c47b7ddb | 12779 | plane_state->planar_linked_plane = linked; |
1ab554b0 | 12780 | |
c47b7ddb ML |
12781 | linked_state->planar_slave = true; |
12782 | linked_state->planar_linked_plane = plane; | |
1ab554b0 | 12783 | crtc_state->active_planes |= BIT(linked->id); |
afbd8a72 | 12784 | crtc_state->update_planes |= BIT(linked->id); |
cd49f818 WK |
12785 | drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", |
12786 | linked->base.name, plane->base.name); | |
1f594b20 ML |
12787 | |
12788 | /* Copy parameters to slave plane */ | |
12789 | linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; | |
12790 | linked_state->color_ctl = plane_state->color_ctl; | |
103605e0 | 12791 | linked_state->view = plane_state->view; |
320625aa ID |
12792 | memcpy(linked_state->color_plane, plane_state->color_plane, |
12793 | sizeof(linked_state->color_plane)); | |
1f594b20 ML |
12794 | |
12795 | intel_plane_copy_uapi_to_hw_state(linked_state, plane_state); | |
12796 | linked_state->uapi.src = plane_state->uapi.src; | |
12797 | linked_state->uapi.dst = plane_state->uapi.dst; | |
12798 | ||
12799 | if (icl_is_hdr_plane(dev_priv, plane->id)) { | |
12800 | if (linked->id == PLANE_SPRITE5) | |
12801 | plane_state->cus_ctl |= PLANE_CUS_PLANE_7; | |
12802 | else if (linked->id == PLANE_SPRITE4) | |
12803 | plane_state->cus_ctl |= PLANE_CUS_PLANE_6; | |
99e2d8bc MR |
12804 | else if (linked->id == PLANE_SPRITE3) |
12805 | plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL; | |
12806 | else if (linked->id == PLANE_SPRITE2) | |
12807 | plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL; | |
1f594b20 ML |
12808 | else |
12809 | MISSING_CASE(linked->id); | |
12810 | } | |
1ab554b0 ML |
12811 | } |
12812 | ||
12813 | return 0; | |
12814 | } | |
12815 | ||
638d87c4 VS |
12816 | static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) |
12817 | { | |
2225f3c6 | 12818 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
638d87c4 | 12819 | struct intel_atomic_state *state = |
2225f3c6 | 12820 | to_intel_atomic_state(new_crtc_state->uapi.state); |
638d87c4 VS |
12821 | const struct intel_crtc_state *old_crtc_state = |
12822 | intel_atomic_get_old_crtc_state(state, crtc); | |
12823 | ||
12824 | return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; | |
12825 | } | |
12826 | ||
6dcde047 VS |
12827 | static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) |
12828 | { | |
bafcdad6 ML |
12829 | const struct drm_display_mode *pipe_mode = |
12830 | &crtc_state->hw.pipe_mode; | |
4003dac1 | 12831 | int linetime_wm; |
6dcde047 VS |
12832 | |
12833 | if (!crtc_state->hw.enable) | |
12834 | return 0; | |
12835 | ||
bafcdad6 ML |
12836 | linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, |
12837 | pipe_mode->crtc_clock); | |
4003dac1 VS |
12838 | |
12839 | return min(linetime_wm, 0x1ff); | |
6dcde047 VS |
12840 | } |
12841 | ||
28a30b45 VS |
12842 | static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, |
12843 | const struct intel_cdclk_state *cdclk_state) | |
6dcde047 | 12844 | { |
bafcdad6 ML |
12845 | const struct drm_display_mode *pipe_mode = |
12846 | &crtc_state->hw.pipe_mode; | |
4003dac1 | 12847 | int linetime_wm; |
6dcde047 VS |
12848 | |
12849 | if (!crtc_state->hw.enable) | |
12850 | return 0; | |
12851 | ||
bafcdad6 | 12852 | linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, |
4003dac1 VS |
12853 | cdclk_state->logical.cdclk); |
12854 | ||
12855 | return min(linetime_wm, 0x1ff); | |
6dcde047 VS |
12856 | } |
12857 | ||
12858 | static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) | |
12859 | { | |
12860 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
12861 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
bafcdad6 ML |
12862 | const struct drm_display_mode *pipe_mode = |
12863 | &crtc_state->hw.pipe_mode; | |
4003dac1 | 12864 | int linetime_wm; |
6dcde047 VS |
12865 | |
12866 | if (!crtc_state->hw.enable) | |
12867 | return 0; | |
12868 | ||
bafcdad6 | 12869 | linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, |
6dcde047 VS |
12870 | crtc_state->pixel_rate); |
12871 | ||
12872 | /* Display WA #1135: BXT:ALL GLK:ALL */ | |
12873 | if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) | |
12874 | linetime_wm /= 2; | |
12875 | ||
4003dac1 | 12876 | return min(linetime_wm, 0x1ff); |
6dcde047 VS |
12877 | } |
12878 | ||
28a30b45 VS |
12879 | static int hsw_compute_linetime_wm(struct intel_atomic_state *state, |
12880 | struct intel_crtc *crtc) | |
12881 | { | |
12882 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12883 | struct intel_crtc_state *crtc_state = | |
12884 | intel_atomic_get_new_crtc_state(state, crtc); | |
12885 | const struct intel_cdclk_state *cdclk_state; | |
12886 | ||
12887 | if (INTEL_GEN(dev_priv) >= 9) | |
12888 | crtc_state->linetime = skl_linetime_wm(crtc_state); | |
12889 | else | |
12890 | crtc_state->linetime = hsw_linetime_wm(crtc_state); | |
12891 | ||
12892 | if (!hsw_crtc_supports_ips(crtc)) | |
12893 | return 0; | |
12894 | ||
12895 | cdclk_state = intel_atomic_get_cdclk_state(state); | |
12896 | if (IS_ERR(cdclk_state)) | |
12897 | return PTR_ERR(cdclk_state); | |
12898 | ||
12899 | crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, | |
12900 | cdclk_state); | |
12901 | ||
12902 | return 0; | |
12903 | } | |
12904 | ||
131d3b1a VS |
12905 | static int intel_crtc_atomic_check(struct intel_atomic_state *state, |
12906 | struct intel_crtc *crtc) | |
6d3a1ce7 | 12907 | { |
2e7f76c1 VS |
12908 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
12909 | struct intel_crtc_state *crtc_state = | |
131d3b1a | 12910 | intel_atomic_get_new_crtc_state(state, crtc); |
2e7f76c1 | 12911 | bool mode_changed = needs_modeset(crtc_state); |
131d3b1a | 12912 | int ret; |
6d3a1ce7 | 12913 | |
440e84a5 | 12914 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) && |
1326a92c | 12915 | mode_changed && !crtc_state->hw.active) |
2e7f76c1 | 12916 | crtc_state->update_wm_post = true; |
eddfcbcd | 12917 | |
1326a92c | 12918 | if (mode_changed && crtc_state->hw.enable && |
ad421372 | 12919 | dev_priv->display.crtc_compute_clock && |
e57291c2 | 12920 | !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { |
2e7f76c1 | 12921 | ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); |
ad421372 ML |
12922 | if (ret) |
12923 | return ret; | |
12924 | } | |
12925 | ||
638d87c4 VS |
12926 | /* |
12927 | * May need to update pipe gamma enable bits | |
12928 | * when C8 planes are getting enabled/disabled. | |
12929 | */ | |
2e7f76c1 | 12930 | if (c8_planes_changed(crtc_state)) |
2225f3c6 | 12931 | crtc_state->uapi.color_mgmt_changed = true; |
638d87c4 | 12932 | |
2e7f76c1 | 12933 | if (mode_changed || crtc_state->update_pipe || |
2225f3c6 | 12934 | crtc_state->uapi.color_mgmt_changed) { |
2e7f76c1 | 12935 | ret = intel_color_check(crtc_state); |
82cf435b LL |
12936 | if (ret) |
12937 | return ret; | |
12938 | } | |
12939 | ||
86c8bbbe | 12940 | if (dev_priv->display.compute_pipe_wm) { |
2e7f76c1 | 12941 | ret = dev_priv->display.compute_pipe_wm(crtc_state); |
ed4a6a7c | 12942 | if (ret) { |
cd49f818 WK |
12943 | drm_dbg_kms(&dev_priv->drm, |
12944 | "Target pipe watermarks are invalid\n"); | |
ed4a6a7c MR |
12945 | return ret; |
12946 | } | |
12947 | } | |
12948 | ||
f255c624 | 12949 | if (dev_priv->display.compute_intermediate_wm) { |
e57291c2 PB |
12950 | if (drm_WARN_ON(&dev_priv->drm, |
12951 | !dev_priv->display.compute_pipe_wm)) | |
ed4a6a7c MR |
12952 | return 0; |
12953 | ||
12954 | /* | |
12955 | * Calculate 'intermediate' watermarks that satisfy both the | |
12956 | * old state and the new state. We can program these | |
12957 | * immediately. | |
12958 | */ | |
2e7f76c1 | 12959 | ret = dev_priv->display.compute_intermediate_wm(crtc_state); |
ed4a6a7c | 12960 | if (ret) { |
cd49f818 WK |
12961 | drm_dbg_kms(&dev_priv->drm, |
12962 | "No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12963 | return ret; |
ed4a6a7c | 12964 | } |
86c8bbbe MR |
12965 | } |
12966 | ||
6315b5d3 | 12967 | if (INTEL_GEN(dev_priv) >= 9) { |
40d42793 | 12968 | if (mode_changed || crtc_state->update_pipe) { |
2e7f76c1 | 12969 | ret = skl_update_scaler_crtc(crtc_state); |
40d42793 VS |
12970 | if (ret) |
12971 | return ret; | |
12972 | } | |
12973 | ||
12974 | ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); | |
28a30b45 VS |
12975 | if (ret) |
12976 | return ret; | |
e435d6e5 ML |
12977 | } |
12978 | ||
28a30b45 VS |
12979 | if (HAS_IPS(dev_priv)) { |
12980 | ret = hsw_compute_ips_config(crtc_state); | |
12981 | if (ret) | |
12982 | return ret; | |
12983 | } | |
12984 | ||
12985 | if (INTEL_GEN(dev_priv) >= 9 || | |
12986 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
12987 | ret = hsw_compute_linetime_wm(state, crtc); | |
12988 | if (ret) | |
12989 | return ret; | |
24f28450 | 12990 | |
6dcde047 VS |
12991 | } |
12992 | ||
0bcbcba7 JRS |
12993 | if (!mode_changed) { |
12994 | ret = intel_psr2_sel_fetch_update(state, crtc); | |
12995 | if (ret) | |
12996 | return ret; | |
12997 | } | |
6e43e276 | 12998 | |
28a30b45 | 12999 | return 0; |
6d3a1ce7 ML |
13000 | } |
13001 | ||
d29b2f9d ACO |
13002 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
13003 | { | |
13004 | struct intel_connector *connector; | |
f9e905ca | 13005 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 13006 | |
f9e905ca DV |
13007 | drm_connector_list_iter_begin(dev, &conn_iter); |
13008 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f | 13009 | if (connector->base.state->crtc) |
ef196b5c | 13010 | drm_connector_put(&connector->base); |
8863dc7f | 13011 | |
d29b2f9d ACO |
13012 | if (connector->base.encoder) { |
13013 | connector->base.state->best_encoder = | |
13014 | connector->base.encoder; | |
13015 | connector->base.state->crtc = | |
13016 | connector->base.encoder->crtc; | |
8863dc7f | 13017 | |
ef196b5c | 13018 | drm_connector_get(&connector->base); |
d29b2f9d ACO |
13019 | } else { |
13020 | connector->base.state->best_encoder = NULL; | |
13021 | connector->base.state->crtc = NULL; | |
13022 | } | |
13023 | } | |
f9e905ca | 13024 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
13025 | } |
13026 | ||
f1a12172 | 13027 | static int |
bcce8d86 VS |
13028 | compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, |
13029 | struct intel_crtc_state *pipe_config) | |
050f7aeb | 13030 | { |
bcce8d86 | 13031 | struct drm_connector *connector = conn_state->connector; |
cd49f818 | 13032 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
bcce8d86 | 13033 | const struct drm_display_info *info = &connector->display_info; |
f1a12172 | 13034 | int bpp; |
050f7aeb | 13035 | |
f1a12172 RS |
13036 | switch (conn_state->max_bpc) { |
13037 | case 6 ... 7: | |
13038 | bpp = 6 * 3; | |
13039 | break; | |
13040 | case 8 ... 9: | |
13041 | bpp = 8 * 3; | |
13042 | break; | |
13043 | case 10 ... 11: | |
13044 | bpp = 10 * 3; | |
13045 | break; | |
13046 | case 12: | |
13047 | bpp = 12 * 3; | |
13048 | break; | |
13049 | default: | |
13050 | return -EINVAL; | |
050f7aeb DV |
13051 | } |
13052 | ||
f1a12172 | 13053 | if (bpp < pipe_config->pipe_bpp) { |
cd49f818 WK |
13054 | drm_dbg_kms(&i915->drm, |
13055 | "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " | |
13056 | "EDID bpp %d, requested bpp %d, max platform bpp %d\n", | |
13057 | connector->base.id, connector->name, | |
13058 | bpp, 3 * info->bpc, | |
13059 | 3 * conn_state->max_requested_bpc, | |
13060 | pipe_config->pipe_bpp); | |
bcce8d86 | 13061 | |
f1a12172 | 13062 | pipe_config->pipe_bpp = bpp; |
050f7aeb | 13063 | } |
bcce8d86 | 13064 | |
f1a12172 | 13065 | return 0; |
050f7aeb DV |
13066 | } |
13067 | ||
4e53c2e0 | 13068 | static int |
050f7aeb | 13069 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 13070 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 13071 | { |
9beb5fea | 13072 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2225f3c6 | 13073 | struct drm_atomic_state *state = pipe_config->uapi.state; |
da3ced29 ACO |
13074 | struct drm_connector *connector; |
13075 | struct drm_connector_state *connector_state; | |
1486017f | 13076 | int bpp, i; |
4e53c2e0 | 13077 | |
9beb5fea TU |
13078 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
13079 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 13080 | bpp = 10*3; |
9beb5fea | 13081 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
13082 | bpp = 12*3; |
13083 | else | |
13084 | bpp = 8*3; | |
13085 | ||
4e53c2e0 DV |
13086 | pipe_config->pipe_bpp = bpp; |
13087 | ||
bcce8d86 | 13088 | /* Clamp display bpp to connector max bpp */ |
aa5e9b47 | 13089 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
bcce8d86 VS |
13090 | int ret; |
13091 | ||
da3ced29 | 13092 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
13093 | continue; |
13094 | ||
bcce8d86 VS |
13095 | ret = compute_sink_pipe_bpp(connector_state, pipe_config); |
13096 | if (ret) | |
13097 | return ret; | |
4e53c2e0 DV |
13098 | } |
13099 | ||
bcce8d86 | 13100 | return 0; |
4e53c2e0 DV |
13101 | } |
13102 | ||
3dfd8d71 JN |
13103 | static void intel_dump_crtc_timings(struct drm_i915_private *i915, |
13104 | const struct drm_display_mode *mode) | |
644db711 | 13105 | { |
3dfd8d71 JN |
13106 | drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " |
13107 | "type: 0x%x flags: 0x%x\n", | |
13108 | mode->crtc_clock, | |
13109 | mode->crtc_hdisplay, mode->crtc_hsync_start, | |
13110 | mode->crtc_hsync_end, mode->crtc_htotal, | |
13111 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
13112 | mode->crtc_vsync_end, mode->crtc_vtotal, | |
13113 | mode->type, mode->flags); | |
644db711 DV |
13114 | } |
13115 | ||
81b55ef1 | 13116 | static void |
926878fb VS |
13117 | intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, |
13118 | const char *id, unsigned int lane_count, | |
13119 | const struct intel_link_m_n *m_n) | |
f6982332 | 13120 | { |
cd49f818 WK |
13121 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
13122 | ||
13123 | drm_dbg_kms(&i915->drm, | |
13124 | "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
13125 | id, lane_count, | |
13126 | m_n->gmch_m, m_n->gmch_n, | |
13127 | m_n->link_m, m_n->link_n, m_n->tu); | |
f6982332 TU |
13128 | } |
13129 | ||
69e89032 VS |
13130 | static void |
13131 | intel_dump_infoframe(struct drm_i915_private *dev_priv, | |
13132 | const union hdmi_infoframe *frame) | |
13133 | { | |
bdbf43d7 | 13134 | if (!drm_debug_enabled(DRM_UT_KMS)) |
69e89032 VS |
13135 | return; |
13136 | ||
13137 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); | |
13138 | } | |
13139 | ||
42890250 GM |
13140 | static void |
13141 | intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, | |
13142 | const struct drm_dp_vsc_sdp *vsc) | |
13143 | { | |
13144 | if (!drm_debug_enabled(DRM_UT_KMS)) | |
13145 | return; | |
13146 | ||
13147 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); | |
13148 | } | |
13149 | ||
40b2be41 VS |
13150 | #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x |
13151 | ||
13152 | static const char * const output_type_str[] = { | |
13153 | OUTPUT_TYPE(UNUSED), | |
13154 | OUTPUT_TYPE(ANALOG), | |
13155 | OUTPUT_TYPE(DVO), | |
13156 | OUTPUT_TYPE(SDVO), | |
13157 | OUTPUT_TYPE(LVDS), | |
13158 | OUTPUT_TYPE(TVOUT), | |
13159 | OUTPUT_TYPE(HDMI), | |
13160 | OUTPUT_TYPE(DP), | |
13161 | OUTPUT_TYPE(EDP), | |
13162 | OUTPUT_TYPE(DSI), | |
7e732cac | 13163 | OUTPUT_TYPE(DDI), |
40b2be41 VS |
13164 | OUTPUT_TYPE(DP_MST), |
13165 | }; | |
13166 | ||
13167 | #undef OUTPUT_TYPE | |
13168 | ||
13169 | static void snprintf_output_types(char *buf, size_t len, | |
13170 | unsigned int output_types) | |
13171 | { | |
13172 | char *str = buf; | |
13173 | int i; | |
13174 | ||
13175 | str[0] = '\0'; | |
13176 | ||
13177 | for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { | |
13178 | int r; | |
13179 | ||
13180 | if ((output_types & BIT(i)) == 0) | |
13181 | continue; | |
13182 | ||
13183 | r = snprintf(str, len, "%s%s", | |
13184 | str != buf ? "," : "", output_type_str[i]); | |
13185 | if (r >= len) | |
13186 | break; | |
13187 | str += r; | |
13188 | len -= r; | |
13189 | ||
13190 | output_types &= ~BIT(i); | |
13191 | } | |
13192 | ||
13193 | WARN_ON_ONCE(output_types != 0); | |
13194 | } | |
13195 | ||
d9facae6 SS |
13196 | static const char * const output_format_str[] = { |
13197 | [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid", | |
13198 | [INTEL_OUTPUT_FORMAT_RGB] = "RGB", | |
33b7f3ee | 13199 | [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", |
8c79f844 | 13200 | [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", |
d9facae6 SS |
13201 | }; |
13202 | ||
13203 | static const char *output_formats(enum intel_output_format format) | |
13204 | { | |
33b7f3ee | 13205 | if (format >= ARRAY_SIZE(output_format_str)) |
d9facae6 SS |
13206 | format = INTEL_OUTPUT_FORMAT_INVALID; |
13207 | return output_format_str[format]; | |
13208 | } | |
13209 | ||
10d75f54 VS |
13210 | static void intel_dump_plane_state(const struct intel_plane_state *plane_state) |
13211 | { | |
f90a85e7 | 13212 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
cd49f818 | 13213 | struct drm_i915_private *i915 = to_i915(plane->base.dev); |
7b3cb17a | 13214 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
10d75f54 VS |
13215 | struct drm_format_name_buf format_name; |
13216 | ||
13217 | if (!fb) { | |
cd49f818 WK |
13218 | drm_dbg_kms(&i915->drm, |
13219 | "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", | |
13220 | plane->base.base.id, plane->base.name, | |
13221 | yesno(plane_state->uapi.visible)); | |
10d75f54 VS |
13222 | return; |
13223 | } | |
13224 | ||
cd49f818 | 13225 | drm_dbg_kms(&i915->drm, |
54defc10 | 13226 | "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s modifier = 0x%llx, visible: %s\n", |
cd49f818 WK |
13227 | plane->base.base.id, plane->base.name, |
13228 | fb->base.id, fb->width, fb->height, | |
13229 | drm_get_format_name(fb->format->format, &format_name), | |
54defc10 | 13230 | fb->modifier, yesno(plane_state->uapi.visible)); |
cd49f818 WK |
13231 | drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", |
13232 | plane_state->hw.rotation, plane_state->scaler_id); | |
f90a85e7 | 13233 | if (plane_state->uapi.visible) |
cd49f818 WK |
13234 | drm_dbg_kms(&i915->drm, |
13235 | "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", | |
13236 | DRM_RECT_FP_ARG(&plane_state->uapi.src), | |
13237 | DRM_RECT_ARG(&plane_state->uapi.dst)); | |
10d75f54 VS |
13238 | } |
13239 | ||
926878fb | 13240 | static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, |
10d75f54 | 13241 | struct intel_atomic_state *state, |
c0b03411 DV |
13242 | const char *context) |
13243 | { | |
2225f3c6 | 13244 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
10d75f54 VS |
13245 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
13246 | const struct intel_plane_state *plane_state; | |
13247 | struct intel_plane *plane; | |
40b2be41 | 13248 | char buf[64]; |
10d75f54 | 13249 | int i; |
6a60cd87 | 13250 | |
cd49f818 WK |
13251 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", |
13252 | crtc->base.base.id, crtc->base.name, | |
13253 | yesno(pipe_config->hw.enable), context); | |
c0b03411 | 13254 | |
1326a92c | 13255 | if (!pipe_config->hw.enable) |
10d75f54 VS |
13256 | goto dump_planes; |
13257 | ||
40b2be41 | 13258 | snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); |
cd49f818 WK |
13259 | drm_dbg_kms(&dev_priv->drm, |
13260 | "active: %s, output_types: %s (0x%x), output format: %s\n", | |
13261 | yesno(pipe_config->hw.active), | |
13262 | buf, pipe_config->output_types, | |
13263 | output_formats(pipe_config->output_format)); | |
d9facae6 | 13264 | |
cd49f818 WK |
13265 | drm_dbg_kms(&dev_priv->drm, |
13266 | "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", | |
13267 | transcoder_name(pipe_config->cpu_transcoder), | |
13268 | pipe_config->pipe_bpp, pipe_config->dither); | |
a4309657 | 13269 | |
cf52acde VS |
13270 | drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", |
13271 | transcoder_name(pipe_config->mst_master_transcoder)); | |
13272 | ||
05d756b0 VS |
13273 | drm_dbg_kms(&dev_priv->drm, |
13274 | "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", | |
13275 | transcoder_name(pipe_config->master_transcoder), | |
13276 | pipe_config->sync_mode_slaves_mask); | |
13277 | ||
a4309657 TU |
13278 | if (pipe_config->has_pch_encoder) |
13279 | intel_dump_m_n_config(pipe_config, "fdi", | |
13280 | pipe_config->fdi_lanes, | |
13281 | &pipe_config->fdi_m_n); | |
f6982332 TU |
13282 | |
13283 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
13284 | intel_dump_m_n_config(pipe_config, "dp m_n", |
13285 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
13286 | if (pipe_config->has_drrs) |
13287 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
13288 | pipe_config->lane_count, | |
13289 | &pipe_config->dp_m2_n2); | |
f6982332 | 13290 | } |
b95af8be | 13291 | |
cd49f818 WK |
13292 | drm_dbg_kms(&dev_priv->drm, |
13293 | "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", | |
13294 | pipe_config->has_audio, pipe_config->has_infoframe, | |
13295 | pipe_config->infoframes.enable); | |
69e89032 VS |
13296 | |
13297 | if (pipe_config->infoframes.enable & | |
13298 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) | |
cd49f818 WK |
13299 | drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", |
13300 | pipe_config->infoframes.gcp); | |
69e89032 VS |
13301 | if (pipe_config->infoframes.enable & |
13302 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) | |
13303 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); | |
13304 | if (pipe_config->infoframes.enable & | |
13305 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) | |
13306 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); | |
13307 | if (pipe_config->infoframes.enable & | |
13308 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) | |
13309 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); | |
bfbeba29 GM |
13310 | if (pipe_config->infoframes.enable & |
13311 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) | |
13312 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); | |
e274fb32 GM |
13313 | if (pipe_config->infoframes.enable & |
13314 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) | |
13315 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); | |
42890250 GM |
13316 | if (pipe_config->infoframes.enable & |
13317 | intel_hdmi_infoframe_enable(DP_SDP_VSC)) | |
13318 | intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); | |
69e89032 | 13319 | |
cd49f818 | 13320 | drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); |
1326a92c | 13321 | drm_mode_debug_printmodeline(&pipe_config->hw.mode); |
cd49f818 | 13322 | drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); |
1326a92c | 13323 | drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); |
3dfd8d71 | 13324 | intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); |
bafcdad6 ML |
13325 | drm_dbg_kms(&dev_priv->drm, "pipe mode:\n"); |
13326 | drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); | |
13327 | intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); | |
cd49f818 WK |
13328 | drm_dbg_kms(&dev_priv->drm, |
13329 | "port clock: %d, pipe src size: %dx%d, pixel rate %d\n", | |
13330 | pipe_config->port_clock, | |
13331 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, | |
13332 | pipe_config->pixel_rate); | |
dd2f616d | 13333 | |
6dcde047 VS |
13334 | drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", |
13335 | pipe_config->linetime, pipe_config->ips_linetime); | |
13336 | ||
dd2f616d | 13337 | if (INTEL_GEN(dev_priv) >= 9) |
cd49f818 WK |
13338 | drm_dbg_kms(&dev_priv->drm, |
13339 | "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
13340 | crtc->num_scalers, | |
13341 | pipe_config->scaler_state.scaler_users, | |
13342 | pipe_config->scaler_state.scaler_id); | |
a74f8375 | 13343 | |
b2ae318a | 13344 | if (HAS_GMCH(dev_priv)) |
cd49f818 WK |
13345 | drm_dbg_kms(&dev_priv->drm, |
13346 | "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
13347 | pipe_config->gmch_pfit.control, | |
13348 | pipe_config->gmch_pfit.pgm_ratios, | |
13349 | pipe_config->gmch_pfit.lvds_border_bits); | |
a74f8375 | 13350 | else |
cd49f818 | 13351 | drm_dbg_kms(&dev_priv->drm, |
35dd95b4 VS |
13352 | "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", |
13353 | DRM_RECT_ARG(&pipe_config->pch_pfit.dst), | |
cd49f818 WK |
13354 | enableddisabled(pipe_config->pch_pfit.enabled), |
13355 | yesno(pipe_config->pch_pfit.force_thru)); | |
a74f8375 | 13356 | |
cd49f818 WK |
13357 | drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n", |
13358 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 13359 | |
f50b79f0 | 13360 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 13361 | |
b1a4383d | 13362 | if (IS_CHERRYVIEW(dev_priv)) |
cd49f818 WK |
13363 | drm_dbg_kms(&dev_priv->drm, |
13364 | "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", | |
13365 | pipe_config->cgm_mode, pipe_config->gamma_mode, | |
13366 | pipe_config->gamma_enable, pipe_config->csc_enable); | |
b1a4383d | 13367 | else |
cd49f818 WK |
13368 | drm_dbg_kms(&dev_priv->drm, |
13369 | "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", | |
13370 | pipe_config->csc_mode, pipe_config->gamma_mode, | |
13371 | pipe_config->gamma_enable, pipe_config->csc_enable); | |
b1a4383d | 13372 | |
cfcd558c VS |
13373 | drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", |
13374 | pipe_config->hw.degamma_lut ? | |
13375 | drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, | |
13376 | pipe_config->hw.gamma_lut ? | |
13377 | drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); | |
13378 | ||
10d75f54 VS |
13379 | dump_planes: |
13380 | if (!state) | |
13381 | return; | |
6a60cd87 | 13382 | |
10d75f54 VS |
13383 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
13384 | if (plane->pipe == crtc->pipe) | |
13385 | intel_dump_plane_state(plane_state); | |
6a60cd87 | 13386 | } |
c0b03411 DV |
13387 | } |
13388 | ||
85829eb5 | 13389 | static bool check_digital_port_conflicts(struct intel_atomic_state *state) |
00f0b378 | 13390 | { |
85829eb5 | 13391 | struct drm_device *dev = state->base.dev; |
da3ced29 | 13392 | struct drm_connector *connector; |
2fd96b41 | 13393 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 13394 | unsigned int used_ports = 0; |
477321e0 | 13395 | unsigned int used_mst_ports = 0; |
bd67a8c1 | 13396 | bool ret = true; |
00f0b378 | 13397 | |
1d5a95b5 VS |
13398 | /* |
13399 | * We're going to peek into connector->state, | |
13400 | * hence connection_mutex must be held. | |
13401 | */ | |
13402 | drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); | |
13403 | ||
00f0b378 VS |
13404 | /* |
13405 | * Walk the connector list instead of the encoder | |
13406 | * list to detect the problem on ddi platforms | |
13407 | * where there's just one encoder per digital port. | |
13408 | */ | |
2fd96b41 GP |
13409 | drm_connector_list_iter_begin(dev, &conn_iter); |
13410 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
13411 | struct drm_connector_state *connector_state; |
13412 | struct intel_encoder *encoder; | |
13413 | ||
85829eb5 VS |
13414 | connector_state = |
13415 | drm_atomic_get_new_connector_state(&state->base, | |
13416 | connector); | |
0bff4858 VS |
13417 | if (!connector_state) |
13418 | connector_state = connector->state; | |
13419 | ||
5448a00d | 13420 | if (!connector_state->best_encoder) |
00f0b378 VS |
13421 | continue; |
13422 | ||
5448a00d ACO |
13423 | encoder = to_intel_encoder(connector_state->best_encoder); |
13424 | ||
e57291c2 | 13425 | drm_WARN_ON(dev, !connector_state->crtc); |
00f0b378 VS |
13426 | |
13427 | switch (encoder->type) { | |
7e732cac | 13428 | case INTEL_OUTPUT_DDI: |
e57291c2 | 13429 | if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) |
00f0b378 | 13430 | break; |
df561f66 | 13431 | fallthrough; |
cca0502b | 13432 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
13433 | case INTEL_OUTPUT_HDMI: |
13434 | case INTEL_OUTPUT_EDP: | |
00f0b378 | 13435 | /* the same port mustn't appear more than once */ |
2713eb41 | 13436 | if (used_ports & BIT(encoder->port)) |
bd67a8c1 | 13437 | ret = false; |
00f0b378 | 13438 | |
2713eb41 | 13439 | used_ports |= BIT(encoder->port); |
477321e0 VS |
13440 | break; |
13441 | case INTEL_OUTPUT_DP_MST: | |
13442 | used_mst_ports |= | |
8f4f2797 | 13443 | 1 << encoder->port; |
477321e0 | 13444 | break; |
00f0b378 VS |
13445 | default: |
13446 | break; | |
13447 | } | |
13448 | } | |
2fd96b41 | 13449 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 13450 | |
477321e0 VS |
13451 | /* can't mix MST and SST/HDMI on the same port */ |
13452 | if (used_ports & used_mst_ports) | |
13453 | return false; | |
13454 | ||
bd67a8c1 | 13455 | return ret; |
00f0b378 VS |
13456 | } |
13457 | ||
58d124ea | 13458 | static void |
aa07c1d3 MN |
13459 | intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, |
13460 | struct intel_crtc_state *crtc_state) | |
58d124ea | 13461 | { |
ee230706 MN |
13462 | const struct intel_crtc_state *from_crtc_state = crtc_state; |
13463 | ||
13464 | intel_crtc_copy_color_blobs(crtc_state, from_crtc_state); | |
58d124ea ML |
13465 | } |
13466 | ||
13467 | static void | |
aa07c1d3 MN |
13468 | intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state, |
13469 | struct intel_crtc_state *crtc_state) | |
58d124ea ML |
13470 | { |
13471 | crtc_state->hw.enable = crtc_state->uapi.enable; | |
13472 | crtc_state->hw.active = crtc_state->uapi.active; | |
13473 | crtc_state->hw.mode = crtc_state->uapi.mode; | |
13474 | crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode; | |
6d1a2fde | 13475 | crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; |
aa07c1d3 MN |
13476 | |
13477 | intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state); | |
58d124ea ML |
13478 | } |
13479 | ||
13480 | static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) | |
13481 | { | |
13482 | crtc_state->uapi.enable = crtc_state->hw.enable; | |
13483 | crtc_state->uapi.active = crtc_state->hw.active; | |
ce04ecd9 PB |
13484 | drm_WARN_ON(crtc_state->uapi.crtc->dev, |
13485 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); | |
58d124ea ML |
13486 | |
13487 | crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; | |
6d1a2fde | 13488 | crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; |
58d124ea ML |
13489 | |
13490 | /* copy color blobs to uapi */ | |
13491 | drm_property_replace_blob(&crtc_state->uapi.degamma_lut, | |
13492 | crtc_state->hw.degamma_lut); | |
13493 | drm_property_replace_blob(&crtc_state->uapi.gamma_lut, | |
13494 | crtc_state->hw.gamma_lut); | |
13495 | drm_property_replace_blob(&crtc_state->uapi.ctm, | |
13496 | crtc_state->hw.ctm); | |
13497 | } | |
13498 | ||
f81b845f | 13499 | static int |
aa07c1d3 MN |
13500 | intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, |
13501 | struct intel_crtc_state *crtc_state) | |
83a57153 | 13502 | { |
216383e9 VS |
13503 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
13504 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
f81b845f CW |
13505 | struct intel_crtc_state *saved_state; |
13506 | ||
216383e9 | 13507 | saved_state = intel_crtc_state_alloc(crtc); |
f81b845f CW |
13508 | if (!saved_state) |
13509 | return -ENOMEM; | |
83a57153 | 13510 | |
58d124ea ML |
13511 | /* free the old crtc_state->hw members */ |
13512 | intel_crtc_free_hw_state(crtc_state); | |
13513 | ||
7546a384 ACO |
13514 | /* FIXME: before the switch to atomic started, a new pipe_config was |
13515 | * kzalloc'd. Code that depends on any field being zero should be | |
13516 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
13517 | * only fields that are know to not cause problems are preserved. */ | |
13518 | ||
58d124ea | 13519 | saved_state->uapi = crtc_state->uapi; |
f81b845f CW |
13520 | saved_state->scaler_state = crtc_state->scaler_state; |
13521 | saved_state->shared_dpll = crtc_state->shared_dpll; | |
13522 | saved_state->dpll_hw_state = crtc_state->dpll_hw_state; | |
eea72c4c ID |
13523 | memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, |
13524 | sizeof(saved_state->icl_port_dplls)); | |
a8ebf607 | 13525 | saved_state->crc_enabled = crtc_state->crc_enabled; |
04548cba VS |
13526 | if (IS_G4X(dev_priv) || |
13527 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
f81b845f | 13528 | saved_state->wm = crtc_state->wm; |
4978cc93 | 13529 | |
58d124ea | 13530 | memcpy(crtc_state, saved_state, sizeof(*crtc_state)); |
f81b845f | 13531 | kfree(saved_state); |
58d124ea | 13532 | |
aa07c1d3 | 13533 | intel_crtc_copy_uapi_to_hw_state(state, crtc_state); |
58d124ea | 13534 | |
f81b845f | 13535 | return 0; |
83a57153 ACO |
13536 | } |
13537 | ||
548ee15b | 13538 | static int |
aa07c1d3 MN |
13539 | intel_modeset_pipe_config(struct intel_atomic_state *state, |
13540 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 13541 | { |
2225f3c6 | 13542 | struct drm_crtc *crtc = pipe_config->uapi.crtc; |
cd49f818 | 13543 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
da3ced29 | 13544 | struct drm_connector *connector; |
0b901879 | 13545 | struct drm_connector_state *connector_state; |
b50a1aa6 | 13546 | int base_bpp, ret, i; |
e29c22c0 | 13547 | bool retry = true; |
ee7b9f93 | 13548 | |
e143a21c DV |
13549 | pipe_config->cpu_transcoder = |
13550 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 13551 | |
2960bc9c ID |
13552 | /* |
13553 | * Sanitize sync polarity flags based on requested ones. If neither | |
13554 | * positive or negative polarity is requested, treat this as meaning | |
13555 | * negative polarity. | |
13556 | */ | |
1326a92c | 13557 | if (!(pipe_config->hw.adjusted_mode.flags & |
2960bc9c | 13558 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
1326a92c | 13559 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13560 | |
1326a92c | 13561 | if (!(pipe_config->hw.adjusted_mode.flags & |
2960bc9c | 13562 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
1326a92c | 13563 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13564 | |
bcce8d86 VS |
13565 | ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13566 | pipe_config); | |
13567 | if (ret) | |
13568 | return ret; | |
13569 | ||
13570 | base_bpp = pipe_config->pipe_bpp; | |
4e53c2e0 | 13571 | |
e41a56be VS |
13572 | /* |
13573 | * Determine the real pipe dimensions. Note that stereo modes can | |
13574 | * increase the actual pipe size due to the frame doubling and | |
13575 | * insertion of additional space for blanks between the frame. This | |
13576 | * is stored in the crtc timings. We use the requested mode to do this | |
13577 | * computation to clearly distinguish it from the adjusted mode, which | |
13578 | * can be changed by the connectors in the below retry loop. | |
13579 | */ | |
1326a92c | 13580 | drm_mode_get_hv_timing(&pipe_config->hw.mode, |
ecb7e16b GP |
13581 | &pipe_config->pipe_src_w, |
13582 | &pipe_config->pipe_src_h); | |
e41a56be | 13583 | |
aa07c1d3 | 13584 | for_each_new_connector_in_state(&state->base, connector, connector_state, i) { |
691313ea VS |
13585 | struct intel_encoder *encoder = |
13586 | to_intel_encoder(connector_state->best_encoder); | |
13587 | ||
253c84c8 VS |
13588 | if (connector_state->crtc != crtc) |
13589 | continue; | |
13590 | ||
e25148d0 | 13591 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
cd49f818 WK |
13592 | drm_dbg_kms(&i915->drm, |
13593 | "rejecting invalid cloning configuration\n"); | |
d26592c6 | 13594 | return -EINVAL; |
e25148d0 VS |
13595 | } |
13596 | ||
253c84c8 VS |
13597 | /* |
13598 | * Determine output_types before calling the .compute_config() | |
13599 | * hooks so that the hooks can use this information safely. | |
13600 | */ | |
7e732cac VS |
13601 | if (encoder->compute_output_type) |
13602 | pipe_config->output_types |= | |
13603 | BIT(encoder->compute_output_type(encoder, pipe_config, | |
13604 | connector_state)); | |
13605 | else | |
13606 | pipe_config->output_types |= BIT(encoder->type); | |
253c84c8 VS |
13607 | } |
13608 | ||
e29c22c0 | 13609 | encoder_retry: |
ef1b460d | 13610 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13611 | pipe_config->port_clock = 0; |
ef1b460d | 13612 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13613 | |
135c81b8 | 13614 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
1326a92c | 13615 | drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, |
2d112de7 | 13616 | CRTC_STEREO_DOUBLE); |
135c81b8 | 13617 | |
7758a113 DV |
13618 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13619 | * adjust it according to limitations or connector properties, and also | |
13620 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13621 | */ |
aa07c1d3 | 13622 | for_each_new_connector_in_state(&state->base, connector, connector_state, i) { |
691313ea VS |
13623 | struct intel_encoder *encoder = |
13624 | to_intel_encoder(connector_state->best_encoder); | |
13625 | ||
0b901879 | 13626 | if (connector_state->crtc != crtc) |
7758a113 | 13627 | continue; |
7ae89233 | 13628 | |
204474a6 LP |
13629 | ret = encoder->compute_config(encoder, pipe_config, |
13630 | connector_state); | |
13631 | if (ret < 0) { | |
13632 | if (ret != -EDEADLK) | |
cd49f818 WK |
13633 | drm_dbg_kms(&i915->drm, |
13634 | "Encoder config failure: %d\n", | |
13635 | ret); | |
204474a6 | 13636 | return ret; |
7758a113 | 13637 | } |
ee7b9f93 | 13638 | } |
47f1c6c9 | 13639 | |
ff9a6750 DV |
13640 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13641 | * done afterwards in case the encoder adjusts the mode. */ | |
13642 | if (!pipe_config->port_clock) | |
1326a92c | 13643 | pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock |
241bfc38 | 13644 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13645 | |
a43f6e0f | 13646 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8e2b4dff | 13647 | if (ret == -EDEADLK) |
d26592c6 | 13648 | return ret; |
e29c22c0 | 13649 | if (ret < 0) { |
cd49f818 | 13650 | drm_dbg_kms(&i915->drm, "CRTC fixup failed\n"); |
d26592c6 | 13651 | return ret; |
ee7b9f93 | 13652 | } |
e29c22c0 DV |
13653 | |
13654 | if (ret == RETRY) { | |
e57291c2 PB |
13655 | if (drm_WARN(&i915->drm, !retry, |
13656 | "loop in pipe configuration computation\n")) | |
d26592c6 | 13657 | return -EINVAL; |
e29c22c0 | 13658 | |
cd49f818 | 13659 | drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); |
e29c22c0 DV |
13660 | retry = false; |
13661 | goto encoder_retry; | |
13662 | } | |
13663 | ||
e8fa4270 | 13664 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
13665 | * only enable it on 6bpc panels and when its not a compliance |
13666 | * test requesting 6bpc video pattern. | |
13667 | */ | |
13668 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
13669 | !pipe_config->dither_force_disable; | |
cd49f818 WK |
13670 | drm_dbg_kms(&i915->drm, |
13671 | "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", | |
13672 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
4e53c2e0 | 13673 | |
d26592c6 | 13674 | return 0; |
ee7b9f93 | 13675 | } |
47f1c6c9 | 13676 | |
f2801424 VS |
13677 | static int |
13678 | intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) | |
13679 | { | |
13680 | struct intel_atomic_state *state = | |
13681 | to_intel_atomic_state(crtc_state->uapi.state); | |
13682 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
13683 | struct drm_connector_state *conn_state; | |
13684 | struct drm_connector *connector; | |
13685 | int i; | |
13686 | ||
13687 | for_each_new_connector_in_state(&state->base, connector, | |
13688 | conn_state, i) { | |
13689 | struct intel_encoder *encoder = | |
13690 | to_intel_encoder(conn_state->best_encoder); | |
13691 | int ret; | |
13692 | ||
13693 | if (conn_state->crtc != &crtc->base || | |
13694 | !encoder->compute_config_late) | |
13695 | continue; | |
13696 | ||
13697 | ret = encoder->compute_config_late(encoder, crtc_state, | |
13698 | conn_state); | |
13699 | if (ret) | |
13700 | return ret; | |
13701 | } | |
13702 | ||
13703 | return 0; | |
13704 | } | |
13705 | ||
2c1c5525 | 13706 | bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13707 | { |
3bd26263 | 13708 | int diff; |
f1f644dc JB |
13709 | |
13710 | if (clock1 == clock2) | |
13711 | return true; | |
13712 | ||
13713 | if (!clock1 || !clock2) | |
13714 | return false; | |
13715 | ||
13716 | diff = abs(clock1 - clock2); | |
13717 | ||
13718 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13719 | return true; | |
13720 | ||
13721 | return false; | |
13722 | } | |
13723 | ||
cfb23ed6 ML |
13724 | static bool |
13725 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13726 | unsigned int m2, unsigned int n2, | |
13727 | bool exact) | |
13728 | { | |
13729 | if (m == m2 && n == n2) | |
13730 | return true; | |
13731 | ||
13732 | if (exact || !m || !n || !m2 || !n2) | |
13733 | return false; | |
13734 | ||
13735 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13736 | ||
31d10b57 ML |
13737 | if (n > n2) { |
13738 | while (n > n2) { | |
cfb23ed6 ML |
13739 | m2 <<= 1; |
13740 | n2 <<= 1; | |
13741 | } | |
31d10b57 ML |
13742 | } else if (n < n2) { |
13743 | while (n < n2) { | |
cfb23ed6 ML |
13744 | m <<= 1; |
13745 | n <<= 1; | |
13746 | } | |
13747 | } | |
13748 | ||
31d10b57 ML |
13749 | if (n != n2) |
13750 | return false; | |
13751 | ||
13752 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13753 | } |
13754 | ||
13755 | static bool | |
13756 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
b124ea43 VS |
13757 | const struct intel_link_m_n *m2_n2, |
13758 | bool exact) | |
13759 | { | |
13760 | return m_n->tu == m2_n2->tu && | |
13761 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13762 | m2_n2->gmch_m, m2_n2->gmch_n, exact) && | |
13763 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13764 | m2_n2->link_m, m2_n2->link_n, exact); | |
cfb23ed6 ML |
13765 | } |
13766 | ||
6454cb9f VS |
13767 | static bool |
13768 | intel_compare_infoframe(const union hdmi_infoframe *a, | |
13769 | const union hdmi_infoframe *b) | |
13770 | { | |
13771 | return memcmp(a, b, sizeof(*a)) == 0; | |
13772 | } | |
13773 | ||
2c3928e4 GM |
13774 | static bool |
13775 | intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, | |
13776 | const struct drm_dp_vsc_sdp *b) | |
13777 | { | |
13778 | return memcmp(a, b, sizeof(*a)) == 0; | |
13779 | } | |
13780 | ||
6454cb9f | 13781 | static void |
dde84833 VS |
13782 | pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, |
13783 | bool fastset, const char *name, | |
13784 | const union hdmi_infoframe *a, | |
13785 | const union hdmi_infoframe *b) | |
6454cb9f | 13786 | { |
dde84833 | 13787 | if (fastset) { |
bdbf43d7 | 13788 | if (!drm_debug_enabled(DRM_UT_KMS)) |
6454cb9f VS |
13789 | return; |
13790 | ||
cd49f818 WK |
13791 | drm_dbg_kms(&dev_priv->drm, |
13792 | "fastset mismatch in %s infoframe\n", name); | |
13793 | drm_dbg_kms(&dev_priv->drm, "expected:\n"); | |
6454cb9f | 13794 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); |
cd49f818 | 13795 | drm_dbg_kms(&dev_priv->drm, "found:\n"); |
6454cb9f VS |
13796 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); |
13797 | } else { | |
cd49f818 WK |
13798 | drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); |
13799 | drm_err(&dev_priv->drm, "expected:\n"); | |
6454cb9f | 13800 | hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); |
cd49f818 | 13801 | drm_err(&dev_priv->drm, "found:\n"); |
6454cb9f VS |
13802 | hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); |
13803 | } | |
13804 | } | |
13805 | ||
2c3928e4 GM |
13806 | static void |
13807 | pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, | |
13808 | bool fastset, const char *name, | |
13809 | const struct drm_dp_vsc_sdp *a, | |
13810 | const struct drm_dp_vsc_sdp *b) | |
13811 | { | |
13812 | if (fastset) { | |
13813 | if (!drm_debug_enabled(DRM_UT_KMS)) | |
13814 | return; | |
13815 | ||
13816 | drm_dbg_kms(&dev_priv->drm, | |
13817 | "fastset mismatch in %s dp sdp\n", name); | |
13818 | drm_dbg_kms(&dev_priv->drm, "expected:\n"); | |
13819 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); | |
13820 | drm_dbg_kms(&dev_priv->drm, "found:\n"); | |
13821 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); | |
13822 | } else { | |
13823 | drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); | |
13824 | drm_err(&dev_priv->drm, "expected:\n"); | |
13825 | drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); | |
13826 | drm_err(&dev_priv->drm, "found:\n"); | |
13827 | drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); | |
13828 | } | |
13829 | } | |
13830 | ||
73cefd90 LDM |
13831 | static void __printf(4, 5) |
13832 | pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, | |
13833 | const char *name, const char *format, ...) | |
4e8048f8 | 13834 | { |
cd49f818 | 13835 | struct drm_i915_private *i915 = to_i915(crtc->base.dev); |
4e8048f8 TU |
13836 | struct va_format vaf; |
13837 | va_list args; | |
13838 | ||
4e8048f8 TU |
13839 | va_start(args, format); |
13840 | vaf.fmt = format; | |
13841 | vaf.va = &args; | |
13842 | ||
dde84833 | 13843 | if (fastset) |
cd49f818 WK |
13844 | drm_dbg_kms(&i915->drm, |
13845 | "[CRTC:%d:%s] fastset mismatch in %s %pV\n", | |
13846 | crtc->base.base.id, crtc->base.name, name, &vaf); | |
99a95487 | 13847 | else |
cd49f818 WK |
13848 | drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", |
13849 | crtc->base.base.id, crtc->base.name, name, &vaf); | |
4e8048f8 TU |
13850 | |
13851 | va_end(args); | |
13852 | } | |
13853 | ||
3d6535cb HG |
13854 | static bool fastboot_enabled(struct drm_i915_private *dev_priv) |
13855 | { | |
8a25c4be JN |
13856 | if (dev_priv->params.fastboot != -1) |
13857 | return dev_priv->params.fastboot; | |
3d6535cb HG |
13858 | |
13859 | /* Enable fastboot by default on Skylake and newer */ | |
7360c9f6 HG |
13860 | if (INTEL_GEN(dev_priv) >= 9) |
13861 | return true; | |
13862 | ||
13863 | /* Enable fastboot by default on VLV and CHV */ | |
13864 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13865 | return true; | |
13866 | ||
13867 | /* Disabled by default on all others */ | |
13868 | return false; | |
3d6535cb HG |
13869 | } |
13870 | ||
0e8ffe1b | 13871 | static bool |
b124ea43 VS |
13872 | intel_pipe_config_compare(const struct intel_crtc_state *current_config, |
13873 | const struct intel_crtc_state *pipe_config, | |
dde84833 | 13874 | bool fastset) |
0e8ffe1b | 13875 | { |
2225f3c6 ML |
13876 | struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); |
13877 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); | |
cfb23ed6 | 13878 | bool ret = true; |
7e764059 | 13879 | u32 bp_gamma = 0; |
dde84833 | 13880 | bool fixup_inherited = fastset && |
a227569d | 13881 | current_config->inherited && !pipe_config->inherited; |
cfb23ed6 | 13882 | |
3d6535cb | 13883 | if (fixup_inherited && !fastboot_enabled(dev_priv)) { |
cd49f818 WK |
13884 | drm_dbg_kms(&dev_priv->drm, |
13885 | "initial modeset and fastboot not set\n"); | |
d19f958d ML |
13886 | ret = false; |
13887 | } | |
13888 | ||
eadd2721 | 13889 | #define PIPE_CONF_CHECK_X(name) do { \ |
66e985c0 | 13890 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13891 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13892 | "(expected 0x%08x, found 0x%08x)", \ |
dde84833 VS |
13893 | current_config->name, \ |
13894 | pipe_config->name); \ | |
cfb23ed6 | 13895 | ret = false; \ |
eadd2721 VS |
13896 | } \ |
13897 | } while (0) | |
66e985c0 | 13898 | |
eadd2721 | 13899 | #define PIPE_CONF_CHECK_I(name) do { \ |
08a24034 | 13900 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13901 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13902 | "(expected %i, found %i)", \ |
dde84833 VS |
13903 | current_config->name, \ |
13904 | pipe_config->name); \ | |
cfb23ed6 | 13905 | ret = false; \ |
eadd2721 VS |
13906 | } \ |
13907 | } while (0) | |
cfb23ed6 | 13908 | |
eadd2721 | 13909 | #define PIPE_CONF_CHECK_BOOL(name) do { \ |
d640bf79 | 13910 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13911 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13912 | "(expected %s, found %s)", \ |
dde84833 VS |
13913 | yesno(current_config->name), \ |
13914 | yesno(pipe_config->name)); \ | |
d640bf79 | 13915 | ret = false; \ |
eadd2721 VS |
13916 | } \ |
13917 | } while (0) | |
d640bf79 | 13918 | |
4493e098 ML |
13919 | /* |
13920 | * Checks state where we only read out the enabling, but not the entire | |
13921 | * state itself (like full infoframes or ELD for audio). These states | |
13922 | * require a full modeset on bootup to fix up. | |
13923 | */ | |
eadd2721 | 13924 | #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ |
4493e098 ML |
13925 | if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ |
13926 | PIPE_CONF_CHECK_BOOL(name); \ | |
13927 | } else { \ | |
73cefd90 | 13928 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13929 | "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ |
dde84833 VS |
13930 | yesno(current_config->name), \ |
13931 | yesno(pipe_config->name)); \ | |
4493e098 | 13932 | ret = false; \ |
eadd2721 VS |
13933 | } \ |
13934 | } while (0) | |
4493e098 | 13935 | |
eadd2721 | 13936 | #define PIPE_CONF_CHECK_P(name) do { \ |
8106ddbd | 13937 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13938 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13939 | "(expected %p, found %p)", \ |
dde84833 VS |
13940 | current_config->name, \ |
13941 | pipe_config->name); \ | |
8106ddbd | 13942 | ret = false; \ |
eadd2721 VS |
13943 | } \ |
13944 | } while (0) | |
8106ddbd | 13945 | |
eadd2721 | 13946 | #define PIPE_CONF_CHECK_M_N(name) do { \ |
cfb23ed6 ML |
13947 | if (!intel_compare_link_m_n(¤t_config->name, \ |
13948 | &pipe_config->name,\ | |
dde84833 | 13949 | !fastset)) { \ |
73cefd90 | 13950 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
dde84833 | 13951 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
cbd9b9f2 | 13952 | "found tu %i, gmch %i/%i link %i/%i)", \ |
dde84833 VS |
13953 | current_config->name.tu, \ |
13954 | current_config->name.gmch_m, \ | |
13955 | current_config->name.gmch_n, \ | |
13956 | current_config->name.link_m, \ | |
13957 | current_config->name.link_n, \ | |
13958 | pipe_config->name.tu, \ | |
13959 | pipe_config->name.gmch_m, \ | |
13960 | pipe_config->name.gmch_n, \ | |
13961 | pipe_config->name.link_m, \ | |
13962 | pipe_config->name.link_n); \ | |
cfb23ed6 | 13963 | ret = false; \ |
eadd2721 VS |
13964 | } \ |
13965 | } while (0) | |
cfb23ed6 | 13966 | |
55c561a7 DV |
13967 | /* This is required for BDW+ where there is only one set of registers for |
13968 | * switching between high and low RR. | |
13969 | * This macro can be used whenever a comparison has to be made between one | |
13970 | * hw state and multiple sw state variables. | |
13971 | */ | |
eadd2721 | 13972 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ |
cfb23ed6 | 13973 | if (!intel_compare_link_m_n(¤t_config->name, \ |
dde84833 | 13974 | &pipe_config->name, !fastset) && \ |
cfb23ed6 | 13975 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
dde84833 | 13976 | &pipe_config->name, !fastset)) { \ |
73cefd90 | 13977 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
dde84833 VS |
13978 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
13979 | "or tu %i gmch %i/%i link %i/%i, " \ | |
cbd9b9f2 | 13980 | "found tu %i, gmch %i/%i link %i/%i)", \ |
dde84833 VS |
13981 | current_config->name.tu, \ |
13982 | current_config->name.gmch_m, \ | |
13983 | current_config->name.gmch_n, \ | |
13984 | current_config->name.link_m, \ | |
13985 | current_config->name.link_n, \ | |
13986 | current_config->alt_name.tu, \ | |
13987 | current_config->alt_name.gmch_m, \ | |
13988 | current_config->alt_name.gmch_n, \ | |
13989 | current_config->alt_name.link_m, \ | |
13990 | current_config->alt_name.link_n, \ | |
13991 | pipe_config->name.tu, \ | |
13992 | pipe_config->name.gmch_m, \ | |
13993 | pipe_config->name.gmch_n, \ | |
13994 | pipe_config->name.link_m, \ | |
13995 | pipe_config->name.link_n); \ | |
cfb23ed6 | 13996 | ret = false; \ |
eadd2721 VS |
13997 | } \ |
13998 | } while (0) | |
88adfff1 | 13999 | |
eadd2721 | 14000 | #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ |
1bd1bd80 | 14001 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
73cefd90 | 14002 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 14003 | "(%x) (expected %i, found %i)", \ |
dde84833 VS |
14004 | (mask), \ |
14005 | current_config->name & (mask), \ | |
14006 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 14007 | ret = false; \ |
eadd2721 VS |
14008 | } \ |
14009 | } while (0) | |
1bd1bd80 | 14010 | |
eadd2721 | 14011 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ |
5e550656 | 14012 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
73cefd90 | 14013 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 14014 | "(expected %i, found %i)", \ |
dde84833 VS |
14015 | current_config->name, \ |
14016 | pipe_config->name); \ | |
cfb23ed6 | 14017 | ret = false; \ |
eadd2721 VS |
14018 | } \ |
14019 | } while (0) | |
5e550656 | 14020 | |
6454cb9f VS |
14021 | #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ |
14022 | if (!intel_compare_infoframe(¤t_config->infoframes.name, \ | |
14023 | &pipe_config->infoframes.name)) { \ | |
dde84833 VS |
14024 | pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ |
14025 | ¤t_config->infoframes.name, \ | |
14026 | &pipe_config->infoframes.name); \ | |
6454cb9f VS |
14027 | ret = false; \ |
14028 | } \ | |
14029 | } while (0) | |
14030 | ||
2c3928e4 GM |
14031 | #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ |
14032 | if (!current_config->has_psr && !pipe_config->has_psr && \ | |
14033 | !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ | |
14034 | &pipe_config->infoframes.name)) { \ | |
14035 | pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ | |
14036 | ¤t_config->infoframes.name, \ | |
14037 | &pipe_config->infoframes.name); \ | |
14038 | ret = false; \ | |
14039 | } \ | |
14040 | } while (0) | |
14041 | ||
7e764059 SS |
14042 | #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ |
14043 | if (current_config->name1 != pipe_config->name1) { \ | |
73cefd90 | 14044 | pipe_config_mismatch(fastset, crtc, __stringify(name1), \ |
cbd9b9f2 | 14045 | "(expected %i, found %i, won't compare lut values)", \ |
7e764059 SS |
14046 | current_config->name1, \ |
14047 | pipe_config->name1); \ | |
14048 | ret = false;\ | |
14049 | } else { \ | |
14050 | if (!intel_color_lut_equal(current_config->name2, \ | |
14051 | pipe_config->name2, pipe_config->name1, \ | |
14052 | bit_precision)) { \ | |
73cefd90 | 14053 | pipe_config_mismatch(fastset, crtc, __stringify(name2), \ |
cbd9b9f2 | 14054 | "hw_state doesn't match sw_state"); \ |
7e764059 SS |
14055 | ret = false; \ |
14056 | } \ | |
14057 | } \ | |
14058 | } while (0) | |
14059 | ||
6454cb9f | 14060 | #define PIPE_CONF_QUIRK(quirk) \ |
bb760063 DV |
14061 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
14062 | ||
eccb140b DV |
14063 | PIPE_CONF_CHECK_I(cpu_transcoder); |
14064 | ||
d640bf79 | 14065 | PIPE_CONF_CHECK_BOOL(has_pch_encoder); |
08a24034 | 14066 | PIPE_CONF_CHECK_I(fdi_lanes); |
cfb23ed6 | 14067 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 14068 | |
90a6b7b0 | 14069 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 14070 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 14071 | |
6315b5d3 | 14072 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
14073 | PIPE_CONF_CHECK_M_N(dp_m_n); |
14074 | ||
cfb23ed6 ML |
14075 | if (current_config->has_drrs) |
14076 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
14077 | } else | |
14078 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 14079 | |
253c84c8 | 14080 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 14081 | |
bafcdad6 ML |
14082 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); |
14083 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); | |
14084 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); | |
14085 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); | |
14086 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); | |
14087 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); | |
14088 | ||
14089 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); | |
14090 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); | |
14091 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); | |
14092 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); | |
14093 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); | |
14094 | PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); | |
14095 | ||
aa42a50a ML |
14096 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); |
14097 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); | |
14098 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); | |
14099 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); | |
14100 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); | |
14101 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 14102 | |
aa42a50a ML |
14103 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); |
14104 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); | |
14105 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); | |
14106 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); | |
14107 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); | |
14108 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 14109 | |
c93f54cf | 14110 | PIPE_CONF_CHECK_I(pixel_multiplier); |
d9facae6 | 14111 | PIPE_CONF_CHECK_I(output_format); |
d640bf79 | 14112 | PIPE_CONF_CHECK_BOOL(has_hdmi_sink); |
772c2a51 | 14113 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 14114 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
d640bf79 | 14115 | PIPE_CONF_CHECK_BOOL(limited_color_range); |
15953637 | 14116 | |
d640bf79 ML |
14117 | PIPE_CONF_CHECK_BOOL(hdmi_scrambling); |
14118 | PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); | |
7afc7f81 | 14119 | PIPE_CONF_CHECK_BOOL(has_infoframe); |
8aa940c8 | 14120 | PIPE_CONF_CHECK_BOOL(fec_enable); |
6c49f241 | 14121 | |
4493e098 | 14122 | PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); |
9ed109a7 | 14123 | |
aa42a50a | 14124 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
1bd1bd80 DV |
14125 | DRM_MODE_FLAG_INTERLACE); |
14126 | ||
bb760063 | 14127 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
aa42a50a | 14128 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 14129 | DRM_MODE_FLAG_PHSYNC); |
aa42a50a | 14130 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 14131 | DRM_MODE_FLAG_NHSYNC); |
aa42a50a | 14132 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 14133 | DRM_MODE_FLAG_PVSYNC); |
aa42a50a | 14134 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 DV |
14135 | DRM_MODE_FLAG_NVSYNC); |
14136 | } | |
045ac3b5 | 14137 | |
333b8ca8 | 14138 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 14139 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 14140 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 14141 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 14142 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 14143 | |
13b7648b VS |
14144 | /* |
14145 | * Changing the EDP transcoder input mux | |
14146 | * (A_ONOFF vs. A_ON) requires a full modeset. | |
14147 | */ | |
dc0c0bfe | 14148 | PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); |
13b7648b | 14149 | |
dde84833 | 14150 | if (!fastset) { |
bfd16b2a ML |
14151 | PIPE_CONF_CHECK_I(pipe_src_w); |
14152 | PIPE_CONF_CHECK_I(pipe_src_h); | |
14153 | ||
d640bf79 | 14154 | PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); |
bfd16b2a | 14155 | if (current_config->pch_pfit.enabled) { |
35dd95b4 VS |
14156 | PIPE_CONF_CHECK_I(pch_pfit.dst.x1); |
14157 | PIPE_CONF_CHECK_I(pch_pfit.dst.y1); | |
14158 | PIPE_CONF_CHECK_I(pch_pfit.dst.x2); | |
14159 | PIPE_CONF_CHECK_I(pch_pfit.dst.y2); | |
bfd16b2a | 14160 | } |
2fa2fe9a | 14161 | |
7aefe2b5 | 14162 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 14163 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
9d5441de VS |
14164 | |
14165 | PIPE_CONF_CHECK_X(gamma_mode); | |
9fdfb8e7 VS |
14166 | if (IS_CHERRYVIEW(dev_priv)) |
14167 | PIPE_CONF_CHECK_X(cgm_mode); | |
14168 | else | |
14169 | PIPE_CONF_CHECK_X(csc_mode); | |
5f29ab23 | 14170 | PIPE_CONF_CHECK_BOOL(gamma_enable); |
8271b2ef | 14171 | PIPE_CONF_CHECK_BOOL(csc_enable); |
7e764059 | 14172 | |
6dcde047 VS |
14173 | PIPE_CONF_CHECK_I(linetime); |
14174 | PIPE_CONF_CHECK_I(ips_linetime); | |
14175 | ||
7e764059 SS |
14176 | bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); |
14177 | if (bp_gamma) | |
aa42a50a | 14178 | PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); |
7aefe2b5 | 14179 | } |
a1b2278e | 14180 | |
d640bf79 | 14181 | PIPE_CONF_CHECK_BOOL(double_wide); |
282740f7 | 14182 | |
8106ddbd | 14183 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 14184 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 14185 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
14186 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
14187 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 14188 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 14189 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
14190 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
14191 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
14192 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
2de38138 PZ |
14193 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); |
14194 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); | |
14195 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); | |
14196 | PIPE_CONF_CHECK_X(dpll_hw_state.pll0); | |
14197 | PIPE_CONF_CHECK_X(dpll_hw_state.pll1); | |
14198 | PIPE_CONF_CHECK_X(dpll_hw_state.pll2); | |
14199 | PIPE_CONF_CHECK_X(dpll_hw_state.pll3); | |
14200 | PIPE_CONF_CHECK_X(dpll_hw_state.pll6); | |
14201 | PIPE_CONF_CHECK_X(dpll_hw_state.pll8); | |
14202 | PIPE_CONF_CHECK_X(dpll_hw_state.pll9); | |
14203 | PIPE_CONF_CHECK_X(dpll_hw_state.pll10); | |
14204 | PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); | |
c27e917e PZ |
14205 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); |
14206 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); | |
14207 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); | |
14208 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); | |
14209 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); | |
14210 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); | |
14211 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); | |
14212 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); | |
14213 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); | |
14214 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); | |
c0d43d62 | 14215 | |
47eacbab VS |
14216 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
14217 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
14218 | ||
9beb5fea | 14219 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
14220 | PIPE_CONF_CHECK_I(pipe_bpp); |
14221 | ||
bafcdad6 | 14222 | PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); |
aa42a50a | 14223 | PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); |
a9a7e98a | 14224 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 14225 | |
53e9bf5e VS |
14226 | PIPE_CONF_CHECK_I(min_voltage_level); |
14227 | ||
6454cb9f VS |
14228 | PIPE_CONF_CHECK_X(infoframes.enable); |
14229 | PIPE_CONF_CHECK_X(infoframes.gcp); | |
14230 | PIPE_CONF_CHECK_INFOFRAME(avi); | |
14231 | PIPE_CONF_CHECK_INFOFRAME(spd); | |
14232 | PIPE_CONF_CHECK_INFOFRAME(hdmi); | |
b37f588e | 14233 | PIPE_CONF_CHECK_INFOFRAME(drm); |
2c3928e4 | 14234 | PIPE_CONF_CHECK_DP_VSC_SDP(vsc); |
6454cb9f | 14235 | |
b33950dd | 14236 | PIPE_CONF_CHECK_X(sync_mode_slaves_mask); |
bfb926e3 MN |
14237 | PIPE_CONF_CHECK_I(master_transcoder); |
14238 | ||
fbacb15e JN |
14239 | PIPE_CONF_CHECK_I(dsc.compression_enable); |
14240 | PIPE_CONF_CHECK_I(dsc.dsc_split); | |
14241 | PIPE_CONF_CHECK_I(dsc.compressed_bpp); | |
14242 | ||
6671c367 JRS |
14243 | PIPE_CONF_CHECK_I(mst_master_transcoder); |
14244 | ||
66e985c0 | 14245 | #undef PIPE_CONF_CHECK_X |
08a24034 | 14246 | #undef PIPE_CONF_CHECK_I |
d640bf79 | 14247 | #undef PIPE_CONF_CHECK_BOOL |
4493e098 | 14248 | #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE |
8106ddbd | 14249 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 14250 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 14251 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
7e764059 | 14252 | #undef PIPE_CONF_CHECK_COLOR_LUT |
bb760063 | 14253 | #undef PIPE_CONF_QUIRK |
88adfff1 | 14254 | |
cfb23ed6 | 14255 | return ret; |
0e8ffe1b DV |
14256 | } |
14257 | ||
e3b247da VS |
14258 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
14259 | const struct intel_crtc_state *pipe_config) | |
14260 | { | |
14261 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 14262 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da | 14263 | &pipe_config->fdi_m_n); |
1326a92c | 14264 | int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; |
e3b247da VS |
14265 | |
14266 | /* | |
14267 | * FDI already provided one idea for the dotclock. | |
14268 | * Yell if the encoder disagrees. | |
14269 | */ | |
e57291c2 PB |
14270 | drm_WARN(&dev_priv->drm, |
14271 | !intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
14272 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
14273 | fdi_dotclock, dotclock); | |
e3b247da VS |
14274 | } |
14275 | } | |
14276 | ||
3b4bf24d ML |
14277 | static void verify_wm_state(struct intel_crtc *crtc, |
14278 | struct intel_crtc_state *new_crtc_state) | |
08db6652 | 14279 | { |
3b4bf24d | 14280 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
370d757d CW |
14281 | struct skl_hw_state { |
14282 | struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; | |
14283 | struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; | |
370d757d CW |
14284 | struct skl_pipe_wm wm; |
14285 | } *hw; | |
370d757d | 14286 | struct skl_pipe_wm *sw_wm; |
3de8a14c | 14287 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; |
072fcc30 | 14288 | u8 hw_enabled_slices; |
3b4bf24d | 14289 | const enum pipe pipe = crtc->pipe; |
3de8a14c | 14290 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 14291 | |
1326a92c | 14292 | if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active) |
08db6652 DL |
14293 | return; |
14294 | ||
370d757d CW |
14295 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
14296 | if (!hw) | |
14297 | return; | |
14298 | ||
3b4bf24d ML |
14299 | skl_pipe_wm_get_hw_state(crtc, &hw->wm); |
14300 | sw_wm = &new_crtc_state->wm.skl.optimal; | |
3de8a14c | 14301 | |
3b4bf24d | 14302 | skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); |
ff43bc37 | 14303 | |
0f0f9aee | 14304 | hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); |
08db6652 | 14305 | |
370d757d | 14306 | if (INTEL_GEN(dev_priv) >= 11 && |
3cf43cdc | 14307 | hw_enabled_slices != dev_priv->dbuf.enabled_slices) |
cd49f818 | 14308 | drm_err(&dev_priv->drm, |
0f0f9aee | 14309 | "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", |
3cf43cdc | 14310 | dev_priv->dbuf.enabled_slices, |
072fcc30 | 14311 | hw_enabled_slices); |
370d757d | 14312 | |
e7c84544 | 14313 | /* planes */ |
8b364b41 | 14314 | for_each_universal_plane(dev_priv, pipe, plane) { |
370d757d CW |
14315 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
14316 | ||
14317 | hw_plane_wm = &hw->wm.planes[plane]; | |
3de8a14c | 14318 | sw_plane_wm = &sw_wm->planes[plane]; |
08db6652 | 14319 | |
3de8a14c | 14320 | /* Watermarks */ |
14321 | for (level = 0; level <= max_level; level++) { | |
14322 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
7241c57d SL |
14323 | &sw_plane_wm->wm[level]) || |
14324 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], | |
14325 | &sw_plane_wm->sagv_wm0))) | |
3de8a14c | 14326 | continue; |
14327 | ||
cd49f818 WK |
14328 | drm_err(&dev_priv->drm, |
14329 | "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14330 | pipe_name(pipe), plane + 1, level, | |
14331 | sw_plane_wm->wm[level].plane_en, | |
14332 | sw_plane_wm->wm[level].plane_res_b, | |
14333 | sw_plane_wm->wm[level].plane_res_l, | |
14334 | hw_plane_wm->wm[level].plane_en, | |
14335 | hw_plane_wm->wm[level].plane_res_b, | |
14336 | hw_plane_wm->wm[level].plane_res_l); | |
3de8a14c | 14337 | } |
08db6652 | 14338 | |
3de8a14c | 14339 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
14340 | &sw_plane_wm->trans_wm)) { | |
cd49f818 WK |
14341 | drm_err(&dev_priv->drm, |
14342 | "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14343 | pipe_name(pipe), plane + 1, | |
14344 | sw_plane_wm->trans_wm.plane_en, | |
14345 | sw_plane_wm->trans_wm.plane_res_b, | |
14346 | sw_plane_wm->trans_wm.plane_res_l, | |
14347 | hw_plane_wm->trans_wm.plane_en, | |
14348 | hw_plane_wm->trans_wm.plane_res_b, | |
14349 | hw_plane_wm->trans_wm.plane_res_l); | |
3de8a14c | 14350 | } |
14351 | ||
14352 | /* DDB */ | |
370d757d | 14353 | hw_ddb_entry = &hw->ddb_y[plane]; |
3b4bf24d | 14354 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; |
3de8a14c | 14355 | |
14356 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
cd49f818 WK |
14357 | drm_err(&dev_priv->drm, |
14358 | "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", | |
14359 | pipe_name(pipe), plane + 1, | |
14360 | sw_ddb_entry->start, sw_ddb_entry->end, | |
14361 | hw_ddb_entry->start, hw_ddb_entry->end); | |
3de8a14c | 14362 | } |
e7c84544 | 14363 | } |
08db6652 | 14364 | |
27082493 L |
14365 | /* |
14366 | * cursor | |
14367 | * If the cursor plane isn't active, we may not have updated it's ddb | |
14368 | * allocation. In that case since the ddb allocation will be updated | |
14369 | * once the plane becomes visible, we can skip this check | |
14370 | */ | |
cd5dcbf1 | 14371 | if (1) { |
370d757d CW |
14372 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
14373 | ||
14374 | hw_plane_wm = &hw->wm.planes[PLANE_CURSOR]; | |
3de8a14c | 14375 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; |
14376 | ||
14377 | /* Watermarks */ | |
14378 | for (level = 0; level <= max_level; level++) { | |
14379 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
7241c57d SL |
14380 | &sw_plane_wm->wm[level]) || |
14381 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], | |
14382 | &sw_plane_wm->sagv_wm0))) | |
3de8a14c | 14383 | continue; |
14384 | ||
cd49f818 WK |
14385 | drm_err(&dev_priv->drm, |
14386 | "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14387 | pipe_name(pipe), level, | |
14388 | sw_plane_wm->wm[level].plane_en, | |
14389 | sw_plane_wm->wm[level].plane_res_b, | |
14390 | sw_plane_wm->wm[level].plane_res_l, | |
14391 | hw_plane_wm->wm[level].plane_en, | |
14392 | hw_plane_wm->wm[level].plane_res_b, | |
14393 | hw_plane_wm->wm[level].plane_res_l); | |
3de8a14c | 14394 | } |
14395 | ||
14396 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
14397 | &sw_plane_wm->trans_wm)) { | |
cd49f818 WK |
14398 | drm_err(&dev_priv->drm, |
14399 | "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14400 | pipe_name(pipe), | |
14401 | sw_plane_wm->trans_wm.plane_en, | |
14402 | sw_plane_wm->trans_wm.plane_res_b, | |
14403 | sw_plane_wm->trans_wm.plane_res_l, | |
14404 | hw_plane_wm->trans_wm.plane_en, | |
14405 | hw_plane_wm->trans_wm.plane_res_b, | |
14406 | hw_plane_wm->trans_wm.plane_res_l); | |
3de8a14c | 14407 | } |
14408 | ||
14409 | /* DDB */ | |
370d757d | 14410 | hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; |
3b4bf24d | 14411 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; |
27082493 | 14412 | |
3de8a14c | 14413 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
cd49f818 WK |
14414 | drm_err(&dev_priv->drm, |
14415 | "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", | |
14416 | pipe_name(pipe), | |
14417 | sw_ddb_entry->start, sw_ddb_entry->end, | |
14418 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 14419 | } |
08db6652 | 14420 | } |
370d757d CW |
14421 | |
14422 | kfree(hw); | |
08db6652 DL |
14423 | } |
14424 | ||
91d1b4bd | 14425 | static void |
3b4bf24d ML |
14426 | verify_connector_state(struct intel_atomic_state *state, |
14427 | struct intel_crtc *crtc) | |
8af6cf88 | 14428 | { |
35dd3c64 | 14429 | struct drm_connector *connector; |
aa5e9b47 | 14430 | struct drm_connector_state *new_conn_state; |
677100ce | 14431 | int i; |
8af6cf88 | 14432 | |
3b4bf24d | 14433 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { |
35dd3c64 | 14434 | struct drm_encoder *encoder = connector->encoder; |
3b4bf24d | 14435 | struct intel_crtc_state *crtc_state = NULL; |
ad3c558f | 14436 | |
3b4bf24d | 14437 | if (new_conn_state->crtc != &crtc->base) |
e7c84544 ML |
14438 | continue; |
14439 | ||
749d98b8 | 14440 | if (crtc) |
3b4bf24d | 14441 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); |
749d98b8 ML |
14442 | |
14443 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 14444 | |
aa5e9b47 | 14445 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 14446 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 14447 | } |
91d1b4bd DV |
14448 | } |
14449 | ||
14450 | static void | |
3b4bf24d | 14451 | verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) |
91d1b4bd DV |
14452 | { |
14453 | struct intel_encoder *encoder; | |
86b04268 DV |
14454 | struct drm_connector *connector; |
14455 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
14456 | int i; | |
8af6cf88 | 14457 | |
3b4bf24d | 14458 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
86b04268 | 14459 | bool enabled = false, found = false; |
4d20cd86 | 14460 | enum pipe pipe; |
8af6cf88 | 14461 | |
cd49f818 WK |
14462 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", |
14463 | encoder->base.base.id, | |
14464 | encoder->base.name); | |
8af6cf88 | 14465 | |
3b4bf24d | 14466 | for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, |
86b04268 DV |
14467 | new_conn_state, i) { |
14468 | if (old_conn_state->best_encoder == &encoder->base) | |
14469 | found = true; | |
14470 | ||
14471 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 14472 | continue; |
86b04268 | 14473 | found = enabled = true; |
ad3c558f | 14474 | |
86b04268 | 14475 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
14476 | encoder->base.crtc, |
14477 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 14478 | } |
86b04268 DV |
14479 | |
14480 | if (!found) | |
14481 | continue; | |
0e32b39c | 14482 | |
e2c719b7 | 14483 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
14484 | "encoder's enabled state mismatch " |
14485 | "(expected %i, found %i)\n", | |
14486 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
14487 | |
14488 | if (!encoder->base.crtc) { | |
4d20cd86 | 14489 | bool active; |
7c60d198 | 14490 | |
4d20cd86 ML |
14491 | active = encoder->get_hw_state(encoder, &pipe); |
14492 | I915_STATE_WARN(active, | |
14493 | "encoder detached but still enabled on pipe %c.\n", | |
14494 | pipe_name(pipe)); | |
7c60d198 | 14495 | } |
8af6cf88 | 14496 | } |
91d1b4bd DV |
14497 | } |
14498 | ||
14499 | static void | |
3b4bf24d ML |
14500 | verify_crtc_state(struct intel_crtc *crtc, |
14501 | struct intel_crtc_state *old_crtc_state, | |
14502 | struct intel_crtc_state *new_crtc_state) | |
91d1b4bd | 14503 | { |
3b4bf24d | 14504 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 14505 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 14506 | struct intel_encoder *encoder; |
979e94c1 VS |
14507 | struct intel_crtc_state *pipe_config = old_crtc_state; |
14508 | struct drm_atomic_state *state = old_crtc_state->uapi.state; | |
045ac3b5 | 14509 | |
2225f3c6 | 14510 | __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); |
58d124ea | 14511 | intel_crtc_free_hw_state(old_crtc_state); |
979e94c1 VS |
14512 | intel_crtc_state_reset(old_crtc_state, crtc); |
14513 | old_crtc_state->uapi.state = state; | |
8af6cf88 | 14514 | |
cd49f818 WK |
14515 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, |
14516 | crtc->base.name); | |
8af6cf88 | 14517 | |
504c7bd8 VS |
14518 | pipe_config->hw.enable = new_crtc_state->hw.enable; |
14519 | ||
291106cb | 14520 | intel_crtc_get_pipe_config(pipe_config); |
d62cf62a | 14521 | |
e56134bc | 14522 | /* we keep both pipes enabled on 830 */ |
504c7bd8 VS |
14523 | if (IS_I830(dev_priv) && pipe_config->hw.active) |
14524 | pipe_config->hw.active = new_crtc_state->hw.active; | |
6c49f241 | 14525 | |
504c7bd8 | 14526 | I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, |
1326a92c ML |
14527 | "crtc active state doesn't match with hw state " |
14528 | "(expected %i, found %i)\n", | |
504c7bd8 | 14529 | new_crtc_state->hw.active, pipe_config->hw.active); |
0e8ffe1b | 14530 | |
1326a92c ML |
14531 | I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, |
14532 | "transitional active state does not match atomic hw state " | |
14533 | "(expected %i, found %i)\n", | |
14534 | new_crtc_state->hw.active, crtc->active); | |
4d20cd86 | 14535 | |
3b4bf24d | 14536 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
e7c84544 | 14537 | enum pipe pipe; |
504c7bd8 | 14538 | bool active; |
4d20cd86 | 14539 | |
e7c84544 | 14540 | active = encoder->get_hw_state(encoder, &pipe); |
1326a92c ML |
14541 | I915_STATE_WARN(active != new_crtc_state->hw.active, |
14542 | "[ENCODER:%i] active %i with crtc active %i\n", | |
14543 | encoder->base.base.id, active, | |
14544 | new_crtc_state->hw.active); | |
4d20cd86 | 14545 | |
3b4bf24d | 14546 | I915_STATE_WARN(active && crtc->pipe != pipe, |
e7c84544 ML |
14547 | "Encoder connected to wrong pipe %c\n", |
14548 | pipe_name(pipe)); | |
4d20cd86 | 14549 | |
e1214b95 | 14550 | if (active) |
65c1ed30 | 14551 | intel_encoder_get_config(encoder, pipe_config); |
e7c84544 | 14552 | } |
53d9f4e9 | 14553 | |
1326a92c | 14554 | if (!new_crtc_state->hw.active) |
e7c84544 | 14555 | return; |
cfb23ed6 | 14556 | |
e7c84544 | 14557 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 14558 | |
3b4bf24d ML |
14559 | if (!intel_pipe_config_compare(new_crtc_state, |
14560 | pipe_config, false)) { | |
e7c84544 | 14561 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
10d75f54 | 14562 | intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); |
3b4bf24d | 14563 | intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); |
8af6cf88 DV |
14564 | } |
14565 | } | |
14566 | ||
cff109f0 VS |
14567 | static void |
14568 | intel_verify_planes(struct intel_atomic_state *state) | |
14569 | { | |
14570 | struct intel_plane *plane; | |
14571 | const struct intel_plane_state *plane_state; | |
14572 | int i; | |
14573 | ||
14574 | for_each_new_intel_plane_in_state(state, plane, | |
14575 | plane_state, i) | |
c47b7ddb | 14576 | assert_plane(plane, plane_state->planar_slave || |
f90a85e7 | 14577 | plane_state->uapi.visible); |
cff109f0 VS |
14578 | } |
14579 | ||
91d1b4bd | 14580 | static void |
c0ead703 ML |
14581 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
14582 | struct intel_shared_dpll *pll, | |
3b4bf24d ML |
14583 | struct intel_crtc *crtc, |
14584 | struct intel_crtc_state *new_crtc_state) | |
91d1b4bd | 14585 | { |
91d1b4bd | 14586 | struct intel_dpll_hw_state dpll_hw_state; |
40560e26 | 14587 | unsigned int crtc_mask; |
e7c84544 | 14588 | bool active; |
5358901f | 14589 | |
e7c84544 | 14590 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 14591 | |
cd49f818 | 14592 | drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); |
5358901f | 14593 | |
fdbc5d68 | 14594 | active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 14595 | |
5cd281f6 | 14596 | if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { |
e7c84544 ML |
14597 | I915_STATE_WARN(!pll->on && pll->active_mask, |
14598 | "pll in active use but not on in sw tracking\n"); | |
14599 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
14600 | "pll is on but not used by any active crtc\n"); | |
14601 | I915_STATE_WARN(pll->on != active, | |
14602 | "pll on state mismatch (expected %i, found %i)\n", | |
14603 | pll->on, active); | |
14604 | } | |
5358901f | 14605 | |
e7c84544 | 14606 | if (!crtc) { |
2c42e535 | 14607 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 14608 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 14609 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 14610 | |
e7c84544 ML |
14611 | return; |
14612 | } | |
14613 | ||
3b4bf24d | 14614 | crtc_mask = drm_crtc_mask(&crtc->base); |
e7c84544 | 14615 | |
1326a92c | 14616 | if (new_crtc_state->hw.active) |
e7c84544 ML |
14617 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), |
14618 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
aca9310a | 14619 | pipe_name(crtc->pipe), pll->active_mask); |
e7c84544 ML |
14620 | else |
14621 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
14622 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
aca9310a | 14623 | pipe_name(crtc->pipe), pll->active_mask); |
2dd66ebd | 14624 | |
2c42e535 | 14625 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 14626 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 14627 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 14628 | |
2c42e535 | 14629 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
14630 | &dpll_hw_state, |
14631 | sizeof(dpll_hw_state)), | |
14632 | "pll hw state mismatch\n"); | |
14633 | } | |
14634 | ||
14635 | static void | |
3b4bf24d ML |
14636 | verify_shared_dpll_state(struct intel_crtc *crtc, |
14637 | struct intel_crtc_state *old_crtc_state, | |
14638 | struct intel_crtc_state *new_crtc_state) | |
e7c84544 | 14639 | { |
3b4bf24d | 14640 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
e7c84544 | 14641 | |
3b4bf24d ML |
14642 | if (new_crtc_state->shared_dpll) |
14643 | verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); | |
e7c84544 | 14644 | |
3b4bf24d ML |
14645 | if (old_crtc_state->shared_dpll && |
14646 | old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { | |
14647 | unsigned int crtc_mask = drm_crtc_mask(&crtc->base); | |
14648 | struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; | |
e7c84544 ML |
14649 | |
14650 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
14651 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
aca9310a | 14652 | pipe_name(crtc->pipe)); |
2c42e535 | 14653 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 | 14654 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
aca9310a | 14655 | pipe_name(crtc->pipe)); |
5358901f | 14656 | } |
8af6cf88 DV |
14657 | } |
14658 | ||
e7c84544 | 14659 | static void |
855e0d68 ML |
14660 | intel_modeset_verify_crtc(struct intel_crtc *crtc, |
14661 | struct intel_atomic_state *state, | |
3b4bf24d ML |
14662 | struct intel_crtc_state *old_crtc_state, |
14663 | struct intel_crtc_state *new_crtc_state) | |
e7c84544 | 14664 | { |
3b4bf24d | 14665 | if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) |
5a21b665 DV |
14666 | return; |
14667 | ||
3b4bf24d ML |
14668 | verify_wm_state(crtc, new_crtc_state); |
14669 | verify_connector_state(state, crtc); | |
14670 | verify_crtc_state(crtc, old_crtc_state, new_crtc_state); | |
14671 | verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); | |
e7c84544 ML |
14672 | } |
14673 | ||
14674 | static void | |
3b4bf24d | 14675 | verify_disabled_dpll_state(struct drm_i915_private *dev_priv) |
e7c84544 | 14676 | { |
e7c84544 ML |
14677 | int i; |
14678 | ||
353ad959 ID |
14679 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) |
14680 | verify_single_dpll_state(dev_priv, | |
14681 | &dev_priv->dpll.shared_dplls[i], | |
14682 | NULL, NULL); | |
e7c84544 ML |
14683 | } |
14684 | ||
14685 | static void | |
3b4bf24d | 14686 | intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, |
855e0d68 | 14687 | struct intel_atomic_state *state) |
e7c84544 | 14688 | { |
3b4bf24d ML |
14689 | verify_encoder_state(dev_priv, state); |
14690 | verify_connector_state(state, NULL); | |
14691 | verify_disabled_dpll_state(dev_priv); | |
e7c84544 ML |
14692 | } |
14693 | ||
99325429 VS |
14694 | static void |
14695 | intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) | |
80715b2f | 14696 | { |
2225f3c6 | 14697 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4f8036a2 | 14698 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
99325429 | 14699 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 14700 | &crtc_state->hw.adjusted_mode; |
99325429 VS |
14701 | |
14702 | drm_calc_timestamping_constants(&crtc->base, adjusted_mode); | |
80715b2f | 14703 | |
af157b76 VS |
14704 | crtc->mode_flags = crtc_state->mode_flags; |
14705 | ||
80715b2f VS |
14706 | /* |
14707 | * The scanline counter increments at the leading edge of hsync. | |
14708 | * | |
14709 | * On most platforms it starts counting from vtotal-1 on the | |
14710 | * first active line. That means the scanline counter value is | |
14711 | * always one less than what we would expect. Ie. just after | |
14712 | * start of vblank, which also occurs at start of hsync (on the | |
14713 | * last active line), the scanline counter will read vblank_start-1. | |
14714 | * | |
14715 | * On gen2 the scanline counter starts counting from 1 instead | |
14716 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
14717 | * to keep the value positive), instead of adding one. | |
14718 | * | |
14719 | * On HSW+ the behaviour of the scanline counter depends on the output | |
14720 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
14721 | * there's an extra 1 line difference. So we need to add two instead of | |
14722 | * one to the value. | |
ec1b4ee2 VS |
14723 | * |
14724 | * On VLV/CHV DSI the scanline counter would appear to increment | |
14725 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
14726 | * that means we can't tell whether we're in vblank or not while | |
14727 | * we're on that particular line. We must still set scanline_offset | |
14728 | * to 1 so that the vblank timestamps come out correct when we query | |
14729 | * the scanline counter from within the vblank interrupt handler. | |
14730 | * However if queried just before the start of vblank we'll get an | |
14731 | * answer that's slightly in the future. | |
80715b2f | 14732 | */ |
cf819eff | 14733 | if (IS_GEN(dev_priv, 2)) { |
80715b2f VS |
14734 | int vtotal; |
14735 | ||
124abe07 VS |
14736 | vtotal = adjusted_mode->crtc_vtotal; |
14737 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
14738 | vtotal /= 2; |
14739 | ||
14740 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 14741 | } else if (HAS_DDI(dev_priv) && |
f2bdd112 | 14742 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
80715b2f | 14743 | crtc->scanline_offset = 2; |
99325429 | 14744 | } else { |
80715b2f | 14745 | crtc->scanline_offset = 1; |
99325429 | 14746 | } |
80715b2f VS |
14747 | } |
14748 | ||
c3b1e6c6 | 14749 | static void intel_modeset_clear_plls(struct intel_atomic_state *state) |
ed6739ef | 14750 | { |
c3b1e6c6 | 14751 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
866955fa | 14752 | struct intel_crtc_state *new_crtc_state; |
c3b1e6c6 | 14753 | struct intel_crtc *crtc; |
0a9ab303 | 14754 | int i; |
ed6739ef ACO |
14755 | |
14756 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 14757 | return; |
ed6739ef | 14758 | |
866955fa | 14759 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
69f786ae | 14760 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
14761 | continue; |
14762 | ||
866955fa | 14763 | intel_release_shared_dplls(state, crtc); |
ad421372 | 14764 | } |
ed6739ef ACO |
14765 | } |
14766 | ||
99d736a2 ML |
14767 | /* |
14768 | * This implements the workaround described in the "notes" section of the mode | |
14769 | * set sequence documentation. When going from no pipes or single pipe to | |
14770 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
14771 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
14772 | */ | |
1e98f88c | 14773 | static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) |
99d736a2 | 14774 | { |
bca0bfa3 VS |
14775 | struct intel_crtc_state *crtc_state; |
14776 | struct intel_crtc *crtc; | |
99d736a2 ML |
14777 | struct intel_crtc_state *first_crtc_state = NULL; |
14778 | struct intel_crtc_state *other_crtc_state = NULL; | |
14779 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
14780 | int i; | |
14781 | ||
14782 | /* look at all crtc's that are going to be enabled in during modeset */ | |
bca0bfa3 | 14783 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { |
1326a92c | 14784 | if (!crtc_state->hw.active || |
69f786ae | 14785 | !needs_modeset(crtc_state)) |
99d736a2 ML |
14786 | continue; |
14787 | ||
14788 | if (first_crtc_state) { | |
bca0bfa3 | 14789 | other_crtc_state = crtc_state; |
99d736a2 ML |
14790 | break; |
14791 | } else { | |
bca0bfa3 VS |
14792 | first_crtc_state = crtc_state; |
14793 | first_pipe = crtc->pipe; | |
99d736a2 ML |
14794 | } |
14795 | } | |
14796 | ||
14797 | /* No workaround needed? */ | |
14798 | if (!first_crtc_state) | |
14799 | return 0; | |
14800 | ||
14801 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
bca0bfa3 VS |
14802 | for_each_intel_crtc(state->base.dev, crtc) { |
14803 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
14804 | if (IS_ERR(crtc_state)) | |
14805 | return PTR_ERR(crtc_state); | |
99d736a2 | 14806 | |
bca0bfa3 | 14807 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; |
99d736a2 | 14808 | |
1326a92c | 14809 | if (!crtc_state->hw.active || |
69f786ae | 14810 | needs_modeset(crtc_state)) |
99d736a2 ML |
14811 | continue; |
14812 | ||
14813 | /* 2 or more enabled crtcs means no need for w/a */ | |
14814 | if (enabled_pipe != INVALID_PIPE) | |
14815 | return 0; | |
14816 | ||
bca0bfa3 | 14817 | enabled_pipe = crtc->pipe; |
99d736a2 ML |
14818 | } |
14819 | ||
14820 | if (enabled_pipe != INVALID_PIPE) | |
14821 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
14822 | else if (other_crtc_state) | |
14823 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
14824 | ||
14825 | return 0; | |
14826 | } | |
14827 | ||
aac97871 VS |
14828 | u8 intel_calc_active_pipes(struct intel_atomic_state *state, |
14829 | u8 active_pipes) | |
14830 | { | |
14831 | const struct intel_crtc_state *crtc_state; | |
14832 | struct intel_crtc *crtc; | |
14833 | int i; | |
14834 | ||
14835 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
14836 | if (crtc_state->hw.active) | |
14837 | active_pipes |= BIT(crtc->pipe); | |
14838 | else | |
14839 | active_pipes &= ~BIT(crtc->pipe); | |
14840 | } | |
14841 | ||
14842 | return active_pipes; | |
14843 | } | |
14844 | ||
5643dd9c | 14845 | static int intel_modeset_checks(struct intel_atomic_state *state) |
054518dd | 14846 | { |
5643dd9c | 14847 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
054518dd | 14848 | |
5643dd9c | 14849 | state->modeset = true; |
1d5a95b5 | 14850 | |
565602d7 | 14851 | if (IS_HASWELL(dev_priv)) |
1e98f88c | 14852 | return hsw_mode_set_planes_workaround(state); |
99d736a2 | 14853 | |
ad421372 | 14854 | return 0; |
c347a676 ACO |
14855 | } |
14856 | ||
aa363136 MR |
14857 | /* |
14858 | * Handle calculation of various watermark data at the end of the atomic check | |
14859 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14860 | * handlers to ensure that all derived state has been updated. | |
14861 | */ | |
cd1d3ee9 | 14862 | static int calc_watermark_data(struct intel_atomic_state *state) |
aa363136 | 14863 | { |
cd1d3ee9 | 14864 | struct drm_device *dev = state->base.dev; |
98d39494 | 14865 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14866 | |
14867 | /* Is there platform-specific watermark information to calculate? */ | |
14868 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14869 | return dev_priv->display.compute_global_watermarks(state); |
14870 | ||
14871 | return 0; | |
aa363136 MR |
14872 | } |
14873 | ||
b124ea43 | 14874 | static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, |
f0521558 VS |
14875 | struct intel_crtc_state *new_crtc_state) |
14876 | { | |
b124ea43 | 14877 | if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) |
f0521558 VS |
14878 | return; |
14879 | ||
2225f3c6 | 14880 | new_crtc_state->uapi.mode_changed = false; |
f0521558 | 14881 | new_crtc_state->update_pipe = true; |
5cb5b370 | 14882 | } |
f0521558 | 14883 | |
5cb5b370 JRS |
14884 | static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, |
14885 | struct intel_crtc_state *new_crtc_state) | |
14886 | { | |
f0521558 VS |
14887 | /* |
14888 | * If we're not doing the full modeset we want to | |
14889 | * keep the current M/N values as they may be | |
14890 | * sufficiently different to the computed values | |
14891 | * to cause problems. | |
14892 | * | |
14893 | * FIXME: should really copy more fuzzy state here | |
14894 | */ | |
14895 | new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; | |
14896 | new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; | |
14897 | new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; | |
14898 | new_crtc_state->has_drrs = old_crtc_state->has_drrs; | |
14899 | } | |
14900 | ||
bb6ae9e6 VS |
14901 | static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, |
14902 | struct intel_crtc *crtc, | |
14903 | u8 plane_ids_mask) | |
131d3b1a | 14904 | { |
bb6ae9e6 VS |
14905 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
14906 | struct intel_plane *plane; | |
14907 | ||
14908 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { | |
14909 | struct intel_plane_state *plane_state; | |
14910 | ||
14911 | if ((plane_ids_mask & BIT(plane->id)) == 0) | |
14912 | continue; | |
14913 | ||
14914 | plane_state = intel_atomic_get_plane_state(state, plane); | |
14915 | if (IS_ERR(plane_state)) | |
14916 | return PTR_ERR(plane_state); | |
14917 | } | |
14918 | ||
14919 | return 0; | |
14920 | } | |
14921 | ||
14922 | static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) | |
14923 | { | |
14924 | /* See {hsw,vlv,ivb}_plane_ratio() */ | |
14925 | return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || | |
14926 | IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || | |
cf129762 | 14927 | IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11); |
bb6ae9e6 VS |
14928 | } |
14929 | ||
4f0b4352 | 14930 | static int intel_atomic_check_planes(struct intel_atomic_state *state) |
bb6ae9e6 VS |
14931 | { |
14932 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
14933 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
131d3b1a VS |
14934 | struct intel_plane_state *plane_state; |
14935 | struct intel_plane *plane; | |
bb6ae9e6 | 14936 | struct intel_crtc *crtc; |
131d3b1a VS |
14937 | int i, ret; |
14938 | ||
bb6ae9e6 VS |
14939 | ret = icl_add_linked_planes(state); |
14940 | if (ret) | |
14941 | return ret; | |
14942 | ||
131d3b1a VS |
14943 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
14944 | ret = intel_plane_atomic_check(state, plane); | |
14945 | if (ret) { | |
cd49f818 WK |
14946 | drm_dbg_atomic(&dev_priv->drm, |
14947 | "[PLANE:%d:%s] atomic driver check failed\n", | |
14948 | plane->base.base.id, plane->base.name); | |
131d3b1a VS |
14949 | return ret; |
14950 | } | |
14951 | } | |
14952 | ||
bb6ae9e6 VS |
14953 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
14954 | new_crtc_state, i) { | |
14955 | u8 old_active_planes, new_active_planes; | |
14956 | ||
14957 | ret = icl_check_nv12_planes(new_crtc_state); | |
14958 | if (ret) | |
14959 | return ret; | |
14960 | ||
14961 | /* | |
14962 | * On some platforms the number of active planes affects | |
14963 | * the planes' minimum cdclk calculation. Add such planes | |
14964 | * to the state before we compute the minimum cdclk. | |
14965 | */ | |
14966 | if (!active_planes_affects_min_cdclk(dev_priv)) | |
14967 | continue; | |
14968 | ||
14969 | old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); | |
14970 | new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); | |
14971 | ||
9877c37e SL |
14972 | /* |
14973 | * Not only the number of planes, but if the plane configuration had | |
14974 | * changed might already mean we need to recompute min CDCLK, | |
14975 | * because different planes might consume different amount of Dbuf bandwidth | |
14976 | * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor | |
14977 | */ | |
14978 | if (old_active_planes == new_active_planes) | |
bb6ae9e6 VS |
14979 | continue; |
14980 | ||
14981 | ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); | |
14982 | if (ret) | |
14983 | return ret; | |
14984 | } | |
14985 | ||
4f0b4352 SL |
14986 | return 0; |
14987 | } | |
14988 | ||
14989 | static int intel_atomic_check_cdclk(struct intel_atomic_state *state, | |
14990 | bool *need_cdclk_calc) | |
14991 | { | |
cd191546 | 14992 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
dc98f50f VS |
14993 | const struct intel_cdclk_state *old_cdclk_state; |
14994 | const struct intel_cdclk_state *new_cdclk_state; | |
4f0b4352 | 14995 | struct intel_plane_state *plane_state; |
19aefbc7 | 14996 | struct intel_bw_state *new_bw_state; |
4f0b4352 | 14997 | struct intel_plane *plane; |
19aefbc7 SL |
14998 | int min_cdclk = 0; |
14999 | enum pipe pipe; | |
4f0b4352 | 15000 | int ret; |
19aefbc7 | 15001 | int i; |
bb6ae9e6 VS |
15002 | /* |
15003 | * active_planes bitmask has been updated, and potentially | |
15004 | * affected planes are part of the state. We can now | |
15005 | * compute the minimum cdclk for each plane. | |
15006 | */ | |
28a30b45 VS |
15007 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
15008 | ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); | |
15009 | if (ret) | |
15010 | return ret; | |
15011 | } | |
bb6ae9e6 | 15012 | |
dc98f50f | 15013 | old_cdclk_state = intel_atomic_get_old_cdclk_state(state); |
cd191546 SL |
15014 | new_cdclk_state = intel_atomic_get_new_cdclk_state(state); |
15015 | ||
dc98f50f VS |
15016 | if (new_cdclk_state && |
15017 | old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) | |
cd191546 SL |
15018 | *need_cdclk_calc = true; |
15019 | ||
15020 | ret = dev_priv->display.bw_calc_min_cdclk(state); | |
15021 | if (ret) | |
15022 | return ret; | |
15023 | ||
19aefbc7 | 15024 | new_bw_state = intel_atomic_get_new_bw_state(state); |
cd191546 | 15025 | |
19aefbc7 SL |
15026 | if (!new_cdclk_state || !new_bw_state) |
15027 | return 0; | |
cd191546 | 15028 | |
19aefbc7 SL |
15029 | for_each_pipe(dev_priv, pipe) { |
15030 | min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); | |
cd191546 SL |
15031 | |
15032 | /* | |
15033 | * Currently do this change only if we need to increase | |
15034 | */ | |
19aefbc7 | 15035 | if (new_bw_state->min_cdclk > min_cdclk) |
cd191546 SL |
15036 | *need_cdclk_calc = true; |
15037 | } | |
15038 | ||
131d3b1a VS |
15039 | return 0; |
15040 | } | |
15041 | ||
15042 | static int intel_atomic_check_crtcs(struct intel_atomic_state *state) | |
15043 | { | |
15044 | struct intel_crtc_state *crtc_state; | |
15045 | struct intel_crtc *crtc; | |
15046 | int i; | |
15047 | ||
15048 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
cd49f818 | 15049 | struct drm_i915_private *i915 = to_i915(crtc->base.dev); |
eba10ec8 VS |
15050 | int ret; |
15051 | ||
15052 | ret = intel_crtc_atomic_check(state, crtc); | |
131d3b1a | 15053 | if (ret) { |
cd49f818 WK |
15054 | drm_dbg_atomic(&i915->drm, |
15055 | "[CRTC:%d:%s] atomic driver check failed\n", | |
15056 | crtc->base.base.id, crtc->base.name); | |
131d3b1a VS |
15057 | return ret; |
15058 | } | |
15059 | } | |
15060 | ||
15061 | return 0; | |
15062 | } | |
15063 | ||
d0eed154 VS |
15064 | static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, |
15065 | u8 transcoders) | |
080d47bf | 15066 | { |
d0eed154 | 15067 | const struct intel_crtc_state *new_crtc_state; |
080d47bf JRS |
15068 | struct intel_crtc *crtc; |
15069 | int i; | |
15070 | ||
d0eed154 VS |
15071 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
15072 | if (new_crtc_state->hw.enable && | |
15073 | transcoders & BIT(new_crtc_state->cpu_transcoder) && | |
15074 | needs_modeset(new_crtc_state)) | |
15075 | return true; | |
15076 | } | |
080d47bf JRS |
15077 | |
15078 | return false; | |
15079 | } | |
15080 | ||
6914c968 K |
15081 | /** |
15082 | * DOC: asynchronous flip implementation | |
15083 | * | |
15084 | * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC | |
15085 | * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. | |
15086 | * Correspondingly, support is currently added for primary plane only. | |
15087 | * | |
15088 | * Async flip can only change the plane surface address, so anything else | |
15089 | * changing is rejected from the intel_atomic_check_async() function. | |
15090 | * Once this check is cleared, flip done interrupt is enabled using | |
15091 | * the skl_enable_flip_done() function. | |
15092 | * | |
15093 | * As soon as the surface address register is written, flip done interrupt is | |
15094 | * generated and the requested events are sent to the usersapce in the interrupt | |
15095 | * handler itself. The timestamp and sequence sent during the flip done event | |
15096 | * correspond to the last vblank and have no relation to the actual time when | |
15097 | * the flip done event was sent. | |
15098 | */ | |
30ff93af K |
15099 | static int intel_atomic_check_async(struct intel_atomic_state *state) |
15100 | { | |
15101 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
15102 | const struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
15103 | const struct intel_plane_state *new_plane_state, *old_plane_state; | |
15104 | struct intel_crtc *crtc; | |
15105 | struct intel_plane *plane; | |
15106 | int i; | |
15107 | ||
15108 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15109 | new_crtc_state, i) { | |
15110 | if (needs_modeset(new_crtc_state)) { | |
15111 | drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n"); | |
15112 | return -EINVAL; | |
15113 | } | |
15114 | ||
15115 | if (!new_crtc_state->hw.active) { | |
15116 | drm_dbg_kms(&i915->drm, "CRTC inactive\n"); | |
15117 | return -EINVAL; | |
15118 | } | |
15119 | if (old_crtc_state->active_planes != new_crtc_state->active_planes) { | |
15120 | drm_dbg_kms(&i915->drm, | |
15121 | "Active planes cannot be changed during async flip\n"); | |
15122 | return -EINVAL; | |
15123 | } | |
15124 | } | |
15125 | ||
15126 | for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, | |
15127 | new_plane_state, i) { | |
15128 | /* | |
15129 | * TODO: Async flip is only supported through the page flip IOCTL | |
15130 | * as of now. So support currently added for primary plane only. | |
15131 | * Support for other planes on platforms on which supports | |
15132 | * this(vlv/chv and icl+) should be added when async flip is | |
15133 | * enabled in the atomic IOCTL path. | |
15134 | */ | |
15135 | if (plane->id != PLANE_PRIMARY) | |
15136 | return -EINVAL; | |
15137 | ||
15138 | /* | |
15139 | * FIXME: This check is kept generic for all platforms. | |
15140 | * Need to verify this for all gen9 and gen10 platforms to enable | |
15141 | * this selectively if required. | |
15142 | */ | |
15143 | switch (new_plane_state->hw.fb->modifier) { | |
15144 | case I915_FORMAT_MOD_X_TILED: | |
15145 | case I915_FORMAT_MOD_Y_TILED: | |
15146 | case I915_FORMAT_MOD_Yf_TILED: | |
15147 | break; | |
15148 | default: | |
15149 | drm_dbg_kms(&i915->drm, | |
15150 | "Linear memory/CCS does not support async flips\n"); | |
15151 | return -EINVAL; | |
15152 | } | |
15153 | ||
15154 | if (old_plane_state->color_plane[0].stride != | |
15155 | new_plane_state->color_plane[0].stride) { | |
15156 | drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n"); | |
15157 | return -EINVAL; | |
15158 | } | |
15159 | ||
15160 | if (old_plane_state->hw.fb->modifier != | |
15161 | new_plane_state->hw.fb->modifier) { | |
15162 | drm_dbg_kms(&i915->drm, | |
15163 | "Framebuffer modifiers cannot be changed in async flip\n"); | |
15164 | return -EINVAL; | |
15165 | } | |
15166 | ||
15167 | if (old_plane_state->hw.fb->format != | |
15168 | new_plane_state->hw.fb->format) { | |
15169 | drm_dbg_kms(&i915->drm, | |
15170 | "Framebuffer format cannot be changed in async flip\n"); | |
15171 | return -EINVAL; | |
15172 | } | |
15173 | ||
15174 | if (old_plane_state->hw.rotation != | |
15175 | new_plane_state->hw.rotation) { | |
15176 | drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n"); | |
15177 | return -EINVAL; | |
15178 | } | |
15179 | ||
15180 | if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || | |
15181 | !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { | |
15182 | drm_dbg_kms(&i915->drm, | |
15183 | "Plane size/co-ordinates cannot be changed in async flip\n"); | |
15184 | return -EINVAL; | |
15185 | } | |
15186 | ||
15187 | if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { | |
15188 | drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n"); | |
15189 | return -EINVAL; | |
15190 | } | |
15191 | ||
15192 | if (old_plane_state->hw.pixel_blend_mode != | |
15193 | new_plane_state->hw.pixel_blend_mode) { | |
15194 | drm_dbg_kms(&i915->drm, | |
15195 | "Pixel blend mode cannot be changed in async flip\n"); | |
15196 | return -EINVAL; | |
15197 | } | |
15198 | ||
15199 | if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { | |
15200 | drm_dbg_kms(&i915->drm, | |
15201 | "Color encoding cannot be changed in async flip\n"); | |
15202 | return -EINVAL; | |
15203 | } | |
15204 | ||
15205 | if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { | |
15206 | drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n"); | |
15207 | return -EINVAL; | |
15208 | } | |
15209 | } | |
15210 | ||
15211 | return 0; | |
15212 | } | |
15213 | ||
74c090b1 ML |
15214 | /** |
15215 | * intel_atomic_check - validate state object | |
15216 | * @dev: drm device | |
70972f51 | 15217 | * @_state: state to validate |
74c090b1 ML |
15218 | */ |
15219 | static int intel_atomic_check(struct drm_device *dev, | |
9a86a07c | 15220 | struct drm_atomic_state *_state) |
c347a676 | 15221 | { |
dd8b3bdb | 15222 | struct drm_i915_private *dev_priv = to_i915(dev); |
9a86a07c VS |
15223 | struct intel_atomic_state *state = to_intel_atomic_state(_state); |
15224 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
15225 | struct intel_crtc *crtc; | |
c347a676 | 15226 | int ret, i; |
1d5a95b5 | 15227 | bool any_ms = false; |
c347a676 | 15228 | |
9a86a07c VS |
15229 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15230 | new_crtc_state, i) { | |
a227569d | 15231 | if (new_crtc_state->inherited != old_crtc_state->inherited) |
2225f3c6 | 15232 | new_crtc_state->uapi.mode_changed = true; |
8c58f73c ML |
15233 | } |
15234 | ||
9a86a07c | 15235 | ret = drm_atomic_helper_check_modeset(dev, &state->base); |
054518dd | 15236 | if (ret) |
2833920d | 15237 | goto fail; |
054518dd | 15238 | |
9a86a07c VS |
15239 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15240 | new_crtc_state, i) { | |
58d124ea ML |
15241 | if (!needs_modeset(new_crtc_state)) { |
15242 | /* Light copy */ | |
aa07c1d3 | 15243 | intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state); |
58d124ea | 15244 | |
c347a676 | 15245 | continue; |
58d124ea | 15246 | } |
c347a676 | 15247 | |
aa07c1d3 | 15248 | ret = intel_crtc_prepare_cleared_state(state, new_crtc_state); |
58d124ea ML |
15249 | if (ret) |
15250 | goto fail; | |
15251 | ||
fff13e63 VS |
15252 | if (!new_crtc_state->hw.enable) |
15253 | continue; | |
15254 | ||
aa07c1d3 | 15255 | ret = intel_modeset_pipe_config(state, new_crtc_state); |
2833920d VS |
15256 | if (ret) |
15257 | goto fail; | |
f2801424 VS |
15258 | } |
15259 | ||
15260 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15261 | new_crtc_state, i) { | |
15262 | if (!needs_modeset(new_crtc_state)) | |
15263 | continue; | |
15264 | ||
15265 | ret = intel_modeset_pipe_config_late(new_crtc_state); | |
15266 | if (ret) | |
15267 | goto fail; | |
c347a676 | 15268 | |
f0521558 | 15269 | intel_crtc_check_fastset(old_crtc_state, new_crtc_state); |
5cb5b370 | 15270 | } |
26495481 | 15271 | |
080d47bf JRS |
15272 | /** |
15273 | * Check if fastset is allowed by external dependencies like other | |
15274 | * pipes and transcoders. | |
15275 | * | |
15276 | * Right now it only forces a fullmodeset when the MST master | |
15277 | * transcoder did not changed but the pipe of the master transcoder | |
05a8e451 JRS |
15278 | * needs a fullmodeset so all slaves also needs to do a fullmodeset or |
15279 | * in case of port synced crtcs, if one of the synced crtcs | |
15280 | * needs a full modeset, all other synced crtcs should be | |
15281 | * forced a full modeset. | |
080d47bf JRS |
15282 | */ |
15283 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { | |
05a8e451 | 15284 | if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state)) |
080d47bf JRS |
15285 | continue; |
15286 | ||
05a8e451 JRS |
15287 | if (intel_dp_mst_is_slave_trans(new_crtc_state)) { |
15288 | enum transcoder master = new_crtc_state->mst_master_transcoder; | |
15289 | ||
d0eed154 | 15290 | if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { |
05a8e451 JRS |
15291 | new_crtc_state->uapi.mode_changed = true; |
15292 | new_crtc_state->update_pipe = false; | |
15293 | } | |
d0eed154 VS |
15294 | } |
15295 | ||
15296 | if (is_trans_port_sync_mode(new_crtc_state)) { | |
8c47eb86 MN |
15297 | u8 trans = new_crtc_state->sync_mode_slaves_mask; |
15298 | ||
15299 | if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) | |
15300 | trans |= BIT(new_crtc_state->master_transcoder); | |
05a8e451 | 15301 | |
d0eed154 VS |
15302 | if (intel_cpu_transcoders_need_modeset(state, trans)) { |
15303 | new_crtc_state->uapi.mode_changed = true; | |
15304 | new_crtc_state->update_pipe = false; | |
15305 | } | |
080d47bf JRS |
15306 | } |
15307 | } | |
15308 | ||
5cb5b370 JRS |
15309 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15310 | new_crtc_state, i) { | |
15311 | if (needs_modeset(new_crtc_state)) { | |
26495481 | 15312 | any_ms = true; |
5cb5b370 JRS |
15313 | continue; |
15314 | } | |
15315 | ||
15316 | if (!new_crtc_state->update_pipe) | |
15317 | continue; | |
15318 | ||
15319 | intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); | |
c347a676 ACO |
15320 | } |
15321 | ||
bf5da83e | 15322 | if (any_ms && !check_digital_port_conflicts(state)) { |
cd49f818 WK |
15323 | drm_dbg_kms(&dev_priv->drm, |
15324 | "rejecting conflicting digital port configuration\n"); | |
66b51b80 | 15325 | ret = -EINVAL; |
bf5da83e VS |
15326 | goto fail; |
15327 | } | |
15328 | ||
9a86a07c | 15329 | ret = drm_dp_mst_atomic_check(&state->base); |
eceae147 | 15330 | if (ret) |
2833920d | 15331 | goto fail; |
eceae147 | 15332 | |
4f0b4352 | 15333 | ret = intel_atomic_check_planes(state); |
bb6ae9e6 VS |
15334 | if (ret) |
15335 | goto fail; | |
15336 | ||
0f8839f5 VS |
15337 | /* |
15338 | * distrust_bios_wm will force a full dbuf recomputation | |
15339 | * but the hardware state will only get updated accordingly | |
15340 | * if state->modeset==true. Hence distrust_bios_wm==true && | |
15341 | * state->modeset==false is an invalid combination which | |
15342 | * would cause the hardware and software dbuf state to get | |
15343 | * out of sync. We must prevent that. | |
15344 | * | |
15345 | * FIXME clean up this mess and introduce better | |
15346 | * state tracking for dbuf. | |
15347 | */ | |
15348 | if (dev_priv->wm.distrust_bios_wm) | |
15349 | any_ms = true; | |
15350 | ||
9a86a07c VS |
15351 | intel_fbc_choose_crtc(dev_priv, state); |
15352 | ret = calc_watermark_data(state); | |
c457d9cf | 15353 | if (ret) |
2833920d | 15354 | goto fail; |
c457d9cf | 15355 | |
9a86a07c | 15356 | ret = intel_bw_atomic_check(state); |
c457d9cf | 15357 | if (ret) |
2833920d | 15358 | goto fail; |
c457d9cf | 15359 | |
4f0b4352 SL |
15360 | ret = intel_atomic_check_cdclk(state, &any_ms); |
15361 | if (ret) | |
15362 | goto fail; | |
15363 | ||
c93b9b2c | 15364 | if (any_ms) { |
cf696856 KV |
15365 | ret = intel_modeset_checks(state); |
15366 | if (ret) | |
15367 | goto fail; | |
15368 | ||
c93b9b2c SL |
15369 | ret = intel_modeset_calc_cdclk(state); |
15370 | if (ret) | |
15371 | return ret; | |
15372 | ||
15373 | intel_modeset_clear_plls(state); | |
15374 | } | |
15375 | ||
15376 | ret = intel_atomic_check_crtcs(state); | |
15377 | if (ret) | |
15378 | goto fail; | |
15379 | ||
a0e70104 VS |
15380 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15381 | new_crtc_state, i) { | |
30ff93af K |
15382 | if (new_crtc_state->uapi.async_flip) { |
15383 | ret = intel_atomic_check_async(state); | |
15384 | if (ret) | |
15385 | goto fail; | |
15386 | } | |
15387 | ||
69f786ae | 15388 | if (!needs_modeset(new_crtc_state) && |
a0e70104 VS |
15389 | !new_crtc_state->update_pipe) |
15390 | continue; | |
15391 | ||
10d75f54 | 15392 | intel_dump_pipe_config(new_crtc_state, state, |
69f786ae | 15393 | needs_modeset(new_crtc_state) ? |
a0e70104 VS |
15394 | "[modeset]" : "[fastset]"); |
15395 | } | |
15396 | ||
c457d9cf | 15397 | return 0; |
2833920d VS |
15398 | |
15399 | fail: | |
15400 | if (ret == -EDEADLK) | |
15401 | return ret; | |
15402 | ||
15403 | /* | |
15404 | * FIXME would probably be nice to know which crtc specifically | |
15405 | * caused the failure, in cases where we can pinpoint it. | |
15406 | */ | |
15407 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15408 | new_crtc_state, i) | |
10d75f54 | 15409 | intel_dump_pipe_config(new_crtc_state, state, "[failed]"); |
2833920d VS |
15410 | |
15411 | return ret; | |
054518dd ACO |
15412 | } |
15413 | ||
a85fb467 | 15414 | static int intel_atomic_prepare_commit(struct intel_atomic_state *state) |
5008e874 | 15415 | { |
afeda4f3 AM |
15416 | struct intel_crtc_state *crtc_state; |
15417 | struct intel_crtc *crtc; | |
15418 | int i, ret; | |
15419 | ||
15420 | ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); | |
15421 | if (ret < 0) | |
15422 | return ret; | |
15423 | ||
15424 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
15425 | bool mode_changed = needs_modeset(crtc_state); | |
15426 | ||
15427 | if (mode_changed || crtc_state->update_pipe || | |
15428 | crtc_state->uapi.color_mgmt_changed) { | |
15429 | intel_dsb_prepare(crtc_state); | |
15430 | } | |
15431 | } | |
15432 | ||
15433 | return 0; | |
5008e874 ML |
15434 | } |
15435 | ||
a2991414 ML |
15436 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
15437 | { | |
15438 | struct drm_device *dev = crtc->base.dev; | |
32db0b65 | 15439 | struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; |
a2991414 | 15440 | |
32db0b65 | 15441 | if (!vblank->max_vblank_count) |
734cbbf3 | 15442 | return (u32)drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 | 15443 | |
08fa8fd0 | 15444 | return crtc->base.funcs->get_vblank_counter(&crtc->base); |
a2991414 ML |
15445 | } |
15446 | ||
d8bd3e15 ML |
15447 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
15448 | struct intel_crtc_state *crtc_state) | |
15449 | { | |
15450 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
15451 | ||
cfdd1747 | 15452 | if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes) |
d8bd3e15 ML |
15453 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); |
15454 | ||
15455 | if (crtc_state->has_pch_encoder) { | |
15456 | enum pipe pch_transcoder = | |
15457 | intel_crtc_pch_transcoder(crtc); | |
15458 | ||
15459 | intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); | |
15460 | } | |
15461 | } | |
15462 | ||
15463 | static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, | |
15464 | const struct intel_crtc_state *new_crtc_state) | |
15465 | { | |
2225f3c6 | 15466 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
d8bd3e15 ML |
15467 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
15468 | ||
d8bd3e15 ML |
15469 | /* |
15470 | * Update pipe size and adjust fitter if needed: the reason for this is | |
15471 | * that in compute_mode_changes we check the native mode (not the pfit | |
15472 | * mode) to see if we can flip rather than do a full mode set. In the | |
15473 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
15474 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
15475 | * sized surface. | |
15476 | */ | |
15477 | intel_set_pipe_src_size(new_crtc_state); | |
15478 | ||
15479 | /* on skylake this is done by detaching scalers */ | |
15480 | if (INTEL_GEN(dev_priv) >= 9) { | |
15481 | skl_detach_scalers(new_crtc_state); | |
15482 | ||
15483 | if (new_crtc_state->pch_pfit.enabled) | |
f6df4d46 | 15484 | skl_pfit_enable(new_crtc_state); |
d8bd3e15 ML |
15485 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
15486 | if (new_crtc_state->pch_pfit.enabled) | |
9eae5e27 | 15487 | ilk_pfit_enable(new_crtc_state); |
d8bd3e15 | 15488 | else if (old_crtc_state->pch_pfit.enabled) |
9eae5e27 | 15489 | ilk_pfit_disable(old_crtc_state); |
d8bd3e15 ML |
15490 | } |
15491 | ||
6dcde047 VS |
15492 | /* |
15493 | * The register is supposedly single buffered so perhaps | |
15494 | * not 100% correct to do this here. But SKL+ calculate | |
15495 | * this based on the adjust pixel rate so pfit changes do | |
15496 | * affect it and so it must be updated for fastsets. | |
15497 | * HSW/BDW only really need this here for fastboot, after | |
15498 | * that the value should not change without a full modeset. | |
15499 | */ | |
15500 | if (INTEL_GEN(dev_priv) >= 9 || | |
15501 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
15502 | hsw_set_linetime_wm(new_crtc_state); | |
15503 | ||
d8bd3e15 ML |
15504 | if (INTEL_GEN(dev_priv) >= 11) |
15505 | icl_set_pipe_chicken(crtc); | |
15506 | } | |
15507 | ||
15508 | static void commit_pipe_config(struct intel_atomic_state *state, | |
b932da3c | 15509 | struct intel_crtc *crtc) |
d8bd3e15 ML |
15510 | { |
15511 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
b932da3c VS |
15512 | const struct intel_crtc_state *old_crtc_state = |
15513 | intel_atomic_get_old_crtc_state(state, crtc); | |
15514 | const struct intel_crtc_state *new_crtc_state = | |
15515 | intel_atomic_get_new_crtc_state(state, crtc); | |
d8bd3e15 ML |
15516 | bool modeset = needs_modeset(new_crtc_state); |
15517 | ||
15518 | /* | |
15519 | * During modesets pipe configuration was programmed as the | |
15520 | * CRTC was enabled. | |
15521 | */ | |
15522 | if (!modeset) { | |
2225f3c6 | 15523 | if (new_crtc_state->uapi.color_mgmt_changed || |
d8bd3e15 ML |
15524 | new_crtc_state->update_pipe) |
15525 | intel_color_commit(new_crtc_state); | |
15526 | ||
15527 | if (INTEL_GEN(dev_priv) >= 9) | |
15528 | skl_detach_scalers(new_crtc_state); | |
15529 | ||
15530 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) | |
15531 | bdw_set_pipemisc(new_crtc_state); | |
15532 | ||
15533 | if (new_crtc_state->update_pipe) | |
15534 | intel_pipe_fastset(old_crtc_state, new_crtc_state); | |
6e43e276 JRS |
15535 | |
15536 | intel_psr2_program_trans_man_trk_ctl(new_crtc_state); | |
d8bd3e15 ML |
15537 | } |
15538 | ||
15539 | if (dev_priv->display.atomic_update_watermarks) | |
7a8fdb1f | 15540 | dev_priv->display.atomic_update_watermarks(state, crtc); |
d8bd3e15 ML |
15541 | } |
15542 | ||
b932da3c VS |
15543 | static void intel_enable_crtc(struct intel_atomic_state *state, |
15544 | struct intel_crtc *crtc) | |
896e5bb0 | 15545 | { |
d8bd3e15 | 15546 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
b932da3c VS |
15547 | const struct intel_crtc_state *new_crtc_state = |
15548 | intel_atomic_get_new_crtc_state(state, crtc); | |
896e5bb0 | 15549 | |
b932da3c VS |
15550 | if (!needs_modeset(new_crtc_state)) |
15551 | return; | |
99325429 | 15552 | |
b932da3c | 15553 | intel_crtc_update_active_timings(new_crtc_state); |
033b7a23 | 15554 | |
b932da3c VS |
15555 | dev_priv->display.crtc_enable(state, crtc); |
15556 | ||
15557 | /* vblanks work again, re-enable pipe CRC. */ | |
15558 | intel_crtc_enable_pipe_crc(crtc); | |
15559 | } | |
15560 | ||
15561 | static void intel_update_crtc(struct intel_atomic_state *state, | |
15562 | struct intel_crtc *crtc) | |
15563 | { | |
15564 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
15565 | const struct intel_crtc_state *old_crtc_state = | |
15566 | intel_atomic_get_old_crtc_state(state, crtc); | |
15567 | struct intel_crtc_state *new_crtc_state = | |
15568 | intel_atomic_get_new_crtc_state(state, crtc); | |
15569 | bool modeset = needs_modeset(new_crtc_state); | |
15570 | ||
15571 | if (!modeset) { | |
0ccc42a2 VS |
15572 | if (new_crtc_state->preload_luts && |
15573 | (new_crtc_state->uapi.color_mgmt_changed || | |
15574 | new_crtc_state->update_pipe)) | |
15575 | intel_color_load_luts(new_crtc_state); | |
15576 | ||
bee43ca4 | 15577 | intel_pre_plane_update(state, crtc); |
608ed4ab | 15578 | |
855e0d68 | 15579 | if (new_crtc_state->update_pipe) |
021ba100 | 15580 | intel_encoders_update_pipe(state, crtc); |
896e5bb0 L |
15581 | } |
15582 | ||
855e0d68 ML |
15583 | if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) |
15584 | intel_fbc_disable(crtc); | |
9ecc6eab VS |
15585 | else |
15586 | intel_fbc_enable(state, crtc); | |
896e5bb0 | 15587 | |
d8bd3e15 ML |
15588 | /* Perform vblank evasion around commit operation */ |
15589 | intel_pipe_update_start(new_crtc_state); | |
15590 | ||
b932da3c | 15591 | commit_pipe_config(state, crtc); |
6c246b81 | 15592 | |
5f2e5112 | 15593 | if (INTEL_GEN(dev_priv) >= 9) |
855e0d68 | 15594 | skl_update_planes_on_crtc(state, crtc); |
5f2e5112 | 15595 | else |
855e0d68 | 15596 | i9xx_update_planes_on_crtc(state, crtc); |
6c246b81 | 15597 | |
d8bd3e15 ML |
15598 | intel_pipe_update_end(new_crtc_state); |
15599 | ||
15600 | /* | |
15601 | * We usually enable FIFO underrun interrupts as part of the | |
15602 | * CRTC enable sequence during modesets. But when we inherit a | |
15603 | * valid pipe configuration from the BIOS we need to take care | |
15604 | * of enabling them on the CRTC's first fastset. | |
15605 | */ | |
15606 | if (new_crtc_state->update_pipe && !modeset && | |
a227569d | 15607 | old_crtc_state->inherited) |
d8bd3e15 | 15608 | intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); |
896e5bb0 L |
15609 | } |
15610 | ||
eadf6f91 | 15611 | |
66d9cec8 MN |
15612 | static void intel_old_crtc_state_disables(struct intel_atomic_state *state, |
15613 | struct intel_crtc_state *old_crtc_state, | |
15614 | struct intel_crtc_state *new_crtc_state, | |
15615 | struct intel_crtc *crtc) | |
15616 | { | |
15617 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
15618 | ||
15619 | intel_crtc_disable_planes(state, crtc); | |
15620 | ||
15621 | /* | |
15622 | * We need to disable pipe CRC before disabling the pipe, | |
15623 | * or we race against vblank off. | |
15624 | */ | |
15625 | intel_crtc_disable_pipe_crc(crtc); | |
15626 | ||
7451a074 | 15627 | dev_priv->display.crtc_disable(state, crtc); |
66d9cec8 MN |
15628 | crtc->active = false; |
15629 | intel_fbc_disable(crtc); | |
15630 | intel_disable_shared_dpll(old_crtc_state); | |
15631 | ||
66d9cec8 | 15632 | /* FIXME unify this for all platforms */ |
1326a92c | 15633 | if (!new_crtc_state->hw.active && |
66d9cec8 MN |
15634 | !HAS_GMCH(dev_priv) && |
15635 | dev_priv->display.initial_watermarks) | |
7a8fdb1f | 15636 | dev_priv->display.initial_watermarks(state, crtc); |
66d9cec8 MN |
15637 | } |
15638 | ||
15639 | static void intel_commit_modeset_disables(struct intel_atomic_state *state) | |
15640 | { | |
15641 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; | |
15642 | struct intel_crtc *crtc; | |
ad457191 | 15643 | u32 handled = 0; |
66d9cec8 MN |
15644 | int i; |
15645 | ||
6671c367 | 15646 | /* Only disable port sync and MST slaves */ |
ad457191 JRS |
15647 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15648 | new_crtc_state, i) { | |
66d9cec8 MN |
15649 | if (!needs_modeset(new_crtc_state)) |
15650 | continue; | |
15651 | ||
ad457191 JRS |
15652 | if (!old_crtc_state->hw.active) |
15653 | continue; | |
15654 | ||
a6c948f9 MN |
15655 | /* In case of Transcoder port Sync master slave CRTCs can be |
15656 | * assigned in any order and we need to make sure that | |
15657 | * slave CRTCs are disabled first and then master CRTC since | |
15658 | * Slave vblanks are masked till Master Vblanks. | |
15659 | */ | |
6671c367 JRS |
15660 | if (!is_trans_port_sync_slave(old_crtc_state) && |
15661 | !intel_dp_mst_is_slave_trans(old_crtc_state)) | |
ad457191 | 15662 | continue; |
66d9cec8 | 15663 | |
ad457191 JRS |
15664 | intel_pre_plane_update(state, crtc); |
15665 | intel_old_crtc_state_disables(state, old_crtc_state, | |
15666 | new_crtc_state, crtc); | |
15667 | handled |= BIT(crtc->pipe); | |
15668 | } | |
15669 | ||
15670 | /* Disable everything else left on */ | |
15671 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15672 | new_crtc_state, i) { | |
15673 | if (!needs_modeset(new_crtc_state) || | |
15674 | (handled & BIT(crtc->pipe))) | |
15675 | continue; | |
15676 | ||
15677 | intel_pre_plane_update(state, crtc); | |
15678 | if (old_crtc_state->hw.active) | |
15679 | intel_old_crtc_state_disables(state, old_crtc_state, | |
15680 | new_crtc_state, crtc); | |
66d9cec8 MN |
15681 | } |
15682 | } | |
15683 | ||
0c841271 | 15684 | static void intel_commit_modeset_enables(struct intel_atomic_state *state) |
896e5bb0 | 15685 | { |
b932da3c | 15686 | struct intel_crtc_state *new_crtc_state; |
855e0d68 | 15687 | struct intel_crtc *crtc; |
896e5bb0 L |
15688 | int i; |
15689 | ||
b932da3c | 15690 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
1326a92c | 15691 | if (!new_crtc_state->hw.active) |
896e5bb0 L |
15692 | continue; |
15693 | ||
b932da3c VS |
15694 | intel_enable_crtc(state, crtc); |
15695 | intel_update_crtc(state, crtc); | |
896e5bb0 L |
15696 | } |
15697 | } | |
15698 | ||
0c841271 | 15699 | static void skl_commit_modeset_enables(struct intel_atomic_state *state) |
27082493 | 15700 | { |
855e0d68 ML |
15701 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
15702 | struct intel_crtc *crtc; | |
15703 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
53cc6880 | 15704 | struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; |
659f1415 | 15705 | u8 update_pipes = 0, modeset_pipes = 0; |
601a9ee0 | 15706 | int i; |
5eff503b | 15707 | |
601a9ee0 | 15708 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
ee34801c VS |
15709 | enum pipe pipe = crtc->pipe; |
15710 | ||
659f1415 JRS |
15711 | if (!new_crtc_state->hw.active) |
15712 | continue; | |
15713 | ||
5eff503b | 15714 | /* ignore allocations for crtc's that have been turned off. */ |
659f1415 | 15715 | if (!needs_modeset(new_crtc_state)) { |
ee34801c VS |
15716 | entries[pipe] = old_crtc_state->wm.skl.ddb; |
15717 | update_pipes |= BIT(pipe); | |
659f1415 | 15718 | } else { |
ee34801c | 15719 | modeset_pipes |= BIT(pipe); |
659f1415 | 15720 | } |
601a9ee0 | 15721 | } |
27082493 L |
15722 | |
15723 | /* | |
15724 | * Whenever the number of active pipes changes, we need to make sure we | |
15725 | * update the pipes in the right order so that their ddb allocations | |
659f1415 | 15726 | * never overlap with each other between CRTC updates. Otherwise we'll |
27082493 | 15727 | * cause pipe underruns and other bad stuff. |
659f1415 JRS |
15728 | * |
15729 | * So first lets enable all pipes that do not need a fullmodeset as | |
15730 | * those don't have any external dependency. | |
27082493 | 15731 | */ |
659f1415 | 15732 | while (update_pipes) { |
601a9ee0 VS |
15733 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15734 | new_crtc_state, i) { | |
36b53a29 | 15735 | enum pipe pipe = crtc->pipe; |
27082493 | 15736 | |
659f1415 | 15737 | if ((update_pipes & BIT(pipe)) == 0) |
27082493 | 15738 | continue; |
5eff503b | 15739 | |
855e0d68 | 15740 | if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, |
7a0a6ee7 | 15741 | entries, I915_MAX_PIPES, pipe)) |
27082493 L |
15742 | continue; |
15743 | ||
ee34801c | 15744 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
659f1415 JRS |
15745 | update_pipes &= ~BIT(pipe); |
15746 | ||
b932da3c | 15747 | intel_update_crtc(state, crtc); |
27082493 | 15748 | |
601a9ee0 VS |
15749 | /* |
15750 | * If this is an already active pipe, it's DDB changed, | |
15751 | * and this isn't the last pipe that needs updating | |
15752 | * then we need to wait for a vblank to pass for the | |
15753 | * new ddb allocation to take effect. | |
15754 | */ | |
15755 | if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, | |
15756 | &old_crtc_state->wm.skl.ddb) && | |
659f1415 | 15757 | (update_pipes | modeset_pipes)) |
0f0f74bc | 15758 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 | 15759 | } |
601a9ee0 | 15760 | } |
aa9664ff | 15761 | |
1ff241ea VS |
15762 | update_pipes = modeset_pipes; |
15763 | ||
659f1415 JRS |
15764 | /* |
15765 | * Enable all pipes that needs a modeset and do not depends on other | |
15766 | * pipes | |
15767 | */ | |
4f05d7ae | 15768 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
659f1415 JRS |
15769 | enum pipe pipe = crtc->pipe; |
15770 | ||
15771 | if ((modeset_pipes & BIT(pipe)) == 0) | |
15772 | continue; | |
15773 | ||
15774 | if (intel_dp_mst_is_slave_trans(new_crtc_state) || | |
d82a855a | 15775 | is_trans_port_sync_master(new_crtc_state)) |
659f1415 JRS |
15776 | continue; |
15777 | ||
659f1415 JRS |
15778 | modeset_pipes &= ~BIT(pipe); |
15779 | ||
d82a855a | 15780 | intel_enable_crtc(state, crtc); |
659f1415 JRS |
15781 | } |
15782 | ||
15783 | /* | |
1ff241ea | 15784 | * Then we enable all remaining pipes that depend on other |
d82a855a | 15785 | * pipes: MST slaves and port sync masters. |
659f1415 | 15786 | */ |
b932da3c | 15787 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
659f1415 JRS |
15788 | enum pipe pipe = crtc->pipe; |
15789 | ||
15790 | if ((modeset_pipes & BIT(pipe)) == 0) | |
15791 | continue; | |
15792 | ||
1ff241ea VS |
15793 | modeset_pipes &= ~BIT(pipe); |
15794 | ||
15795 | intel_enable_crtc(state, crtc); | |
15796 | } | |
15797 | ||
15798 | /* | |
15799 | * Finally we do the plane updates/etc. for all pipes that got enabled. | |
15800 | */ | |
15801 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { | |
15802 | enum pipe pipe = crtc->pipe; | |
15803 | ||
15804 | if ((update_pipes & BIT(pipe)) == 0) | |
15805 | continue; | |
15806 | ||
e57291c2 | 15807 | drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, |
7a0a6ee7 | 15808 | entries, I915_MAX_PIPES, pipe)); |
659f1415 | 15809 | |
ee34801c | 15810 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
1ff241ea | 15811 | update_pipes &= ~BIT(pipe); |
659f1415 | 15812 | |
b932da3c | 15813 | intel_update_crtc(state, crtc); |
659f1415 JRS |
15814 | } |
15815 | ||
e57291c2 | 15816 | drm_WARN_ON(&dev_priv->drm, modeset_pipes); |
1ff241ea | 15817 | drm_WARN_ON(&dev_priv->drm, update_pipes); |
27082493 L |
15818 | } |
15819 | ||
ba318c61 CW |
15820 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
15821 | { | |
15822 | struct intel_atomic_state *state, *next; | |
15823 | struct llist_node *freed; | |
15824 | ||
15825 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
15826 | llist_for_each_entry_safe(state, next, freed, freed) | |
15827 | drm_atomic_state_put(&state->base); | |
15828 | } | |
15829 | ||
15830 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
15831 | { | |
15832 | struct drm_i915_private *dev_priv = | |
15833 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
15834 | ||
15835 | intel_atomic_helper_free_state(dev_priv); | |
15836 | } | |
15837 | ||
9db529aa DV |
15838 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
15839 | { | |
15840 | struct wait_queue_entry wait_fence, wait_reset; | |
15841 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
15842 | ||
15843 | init_wait_entry(&wait_fence, 0); | |
15844 | init_wait_entry(&wait_reset, 0); | |
15845 | for (;;) { | |
15846 | prepare_to_wait(&intel_state->commit_ready.wait, | |
15847 | &wait_fence, TASK_UNINTERRUPTIBLE); | |
cb823ed9 CW |
15848 | prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
15849 | I915_RESET_MODESET), | |
9db529aa DV |
15850 | &wait_reset, TASK_UNINTERRUPTIBLE); |
15851 | ||
15852 | ||
cb823ed9 CW |
15853 | if (i915_sw_fence_done(&intel_state->commit_ready) || |
15854 | test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) | |
9db529aa DV |
15855 | break; |
15856 | ||
15857 | schedule(); | |
15858 | } | |
15859 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); | |
cb823ed9 CW |
15860 | finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
15861 | I915_RESET_MODESET), | |
15862 | &wait_reset); | |
9db529aa DV |
15863 | } |
15864 | ||
afeda4f3 AM |
15865 | static void intel_cleanup_dsbs(struct intel_atomic_state *state) |
15866 | { | |
15867 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
15868 | struct intel_crtc *crtc; | |
15869 | int i; | |
15870 | ||
15871 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15872 | new_crtc_state, i) | |
15873 | intel_dsb_cleanup(old_crtc_state); | |
15874 | } | |
15875 | ||
8d52e447 CW |
15876 | static void intel_atomic_cleanup_work(struct work_struct *work) |
15877 | { | |
afeda4f3 AM |
15878 | struct intel_atomic_state *state = |
15879 | container_of(work, struct intel_atomic_state, base.commit_work); | |
15880 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
8d52e447 | 15881 | |
afeda4f3 AM |
15882 | intel_cleanup_dsbs(state); |
15883 | drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); | |
15884 | drm_atomic_helper_commit_cleanup_done(&state->base); | |
15885 | drm_atomic_state_put(&state->base); | |
8d52e447 CW |
15886 | |
15887 | intel_atomic_helper_free_state(i915); | |
15888 | } | |
15889 | ||
855e0d68 | 15890 | static void intel_atomic_commit_tail(struct intel_atomic_state *state) |
a6778b3c | 15891 | { |
855e0d68 | 15892 | struct drm_device *dev = state->base.dev; |
fac5e23e | 15893 | struct drm_i915_private *dev_priv = to_i915(dev); |
855e0d68 ML |
15894 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; |
15895 | struct intel_crtc *crtc; | |
d8fc70b7 | 15896 | u64 put_domains[I915_MAX_PIPES] = {}; |
0e6e0be4 | 15897 | intel_wakeref_t wakeref = 0; |
e95433c7 | 15898 | int i; |
a6778b3c | 15899 | |
855e0d68 | 15900 | intel_atomic_commit_fence_wait(state); |
42b062b0 | 15901 | |
855e0d68 | 15902 | drm_atomic_helper_wait_for_dependencies(&state->base); |
ea0000f0 | 15903 | |
855e0d68 | 15904 | if (state->modeset) |
0e6e0be4 | 15905 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 15906 | |
7bff9779 ML |
15907 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15908 | new_crtc_state, i) { | |
855e0d68 ML |
15909 | if (needs_modeset(new_crtc_state) || |
15910 | new_crtc_state->update_pipe) { | |
a539205a | 15911 | |
855e0d68 | 15912 | put_domains[crtc->pipe] = |
afe0c21b | 15913 | modeset_get_crtc_power_domains(new_crtc_state); |
5a21b665 | 15914 | } |
b8cecdf5 | 15915 | } |
7758a113 | 15916 | |
66d9cec8 MN |
15917 | intel_commit_modeset_disables(state); |
15918 | ||
855e0d68 ML |
15919 | /* FIXME: Eventually get rid of our crtc->config pointer */ |
15920 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) | |
15921 | crtc->config = new_crtc_state; | |
f6e5b160 | 15922 | |
855e0d68 ML |
15923 | if (state->modeset) { |
15924 | drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); | |
33c8df89 | 15925 | |
5604e9ce | 15926 | intel_set_cdclk_pre_plane_update(state); |
f6d1973d | 15927 | |
3b4bf24d | 15928 | intel_modeset_verify_disabled(dev_priv, state); |
4740b0f2 | 15929 | } |
47fab737 | 15930 | |
ecab0f3d SL |
15931 | intel_sagv_pre_plane_update(state); |
15932 | ||
896e5bb0 | 15933 | /* Complete the events for pipes that have now been disabled */ |
855e0d68 ML |
15934 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
15935 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 15936 | |
1f7528c4 | 15937 | /* Complete events for now disable pipes here. */ |
2225f3c6 | 15938 | if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { |
1f7528c4 | 15939 | spin_lock_irq(&dev->event_lock); |
2225f3c6 ML |
15940 | drm_crtc_send_vblank_event(&crtc->base, |
15941 | new_crtc_state->uapi.event); | |
1f7528c4 DV |
15942 | spin_unlock_irq(&dev->event_lock); |
15943 | ||
2225f3c6 | 15944 | new_crtc_state->uapi.event = NULL; |
1f7528c4 | 15945 | } |
177246a8 MR |
15946 | } |
15947 | ||
24a7bfe0 ID |
15948 | if (state->modeset) |
15949 | intel_encoders_update_prepare(state); | |
15950 | ||
c7c0e7eb | 15951 | intel_dbuf_pre_plane_update(state); |
b06cf595 | 15952 | |
1288f9b0 K |
15953 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
15954 | if (new_crtc_state->uapi.async_flip) | |
15955 | skl_enable_flip_done(crtc); | |
15956 | } | |
15957 | ||
896e5bb0 | 15958 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0c841271 | 15959 | dev_priv->display.commit_modeset_enables(state); |
896e5bb0 | 15960 | |
24a7bfe0 ID |
15961 | if (state->modeset) { |
15962 | intel_encoders_update_complete(state); | |
15963 | ||
5604e9ce | 15964 | intel_set_cdclk_post_plane_update(state); |
24a7bfe0 | 15965 | } |
59f9e9ca | 15966 | |
94f05024 DV |
15967 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
15968 | * already, but still need the state for the delayed optimization. To | |
15969 | * fix this: | |
15970 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
15971 | * - schedule that vblank worker _before_ calling hw_done | |
15972 | * - at the start of commit_tail, cancel it _synchrously | |
15973 | * - switch over to the vblank wait helper in the core after that since | |
15974 | * we don't need out special handling any more. | |
15975 | */ | |
855e0d68 | 15976 | drm_atomic_helper_wait_for_flip_done(dev, &state->base); |
5a21b665 | 15977 | |
855e0d68 | 15978 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
1288f9b0 K |
15979 | if (new_crtc_state->uapi.async_flip) |
15980 | skl_disable_flip_done(crtc); | |
15981 | ||
1326a92c | 15982 | if (new_crtc_state->hw.active && |
855e0d68 | 15983 | !needs_modeset(new_crtc_state) && |
0ccc42a2 | 15984 | !new_crtc_state->preload_luts && |
2225f3c6 | 15985 | (new_crtc_state->uapi.color_mgmt_changed || |
855e0d68 ML |
15986 | new_crtc_state->update_pipe)) |
15987 | intel_color_load_luts(new_crtc_state); | |
051a6d8d VS |
15988 | } |
15989 | ||
5a21b665 DV |
15990 | /* |
15991 | * Now that the vblank has passed, we can go ahead and program the | |
15992 | * optimal watermarks on platforms that need two-step watermark | |
15993 | * programming. | |
15994 | * | |
15995 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
15996 | */ | |
7181f5c5 VS |
15997 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15998 | new_crtc_state, i) { | |
15999 | /* | |
16000 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
16001 | * So re-enable underrun reporting after some planes get enabled. | |
16002 | * | |
16003 | * We do this before .optimize_watermarks() so that we have a | |
16004 | * chance of catching underruns with the intermediate watermarks | |
16005 | * vs. the new plane configuration. | |
16006 | */ | |
16007 | if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state)) | |
16008 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
16009 | ||
5a21b665 | 16010 | if (dev_priv->display.optimize_watermarks) |
7a8fdb1f | 16011 | dev_priv->display.optimize_watermarks(state, crtc); |
5a21b665 DV |
16012 | } |
16013 | ||
c7c0e7eb | 16014 | intel_dbuf_post_plane_update(state); |
b06cf595 | 16015 | |
855e0d68 | 16016 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
bee43ca4 | 16017 | intel_post_plane_update(state, crtc); |
5a21b665 DV |
16018 | |
16019 | if (put_domains[i]) | |
16020 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
16021 | ||
aa5e9b47 | 16022 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
afeda4f3 AM |
16023 | |
16024 | /* | |
16025 | * DSB cleanup is done in cleanup_work aligning with framebuffer | |
16026 | * cleanup. So copy and reset the dsb structure to sync with | |
16027 | * commit_done and later do dsb cleanup in cleanup_work. | |
16028 | */ | |
16029 | old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); | |
5a21b665 DV |
16030 | } |
16031 | ||
7181f5c5 VS |
16032 | /* Underruns don't always raise interrupts, so check manually */ |
16033 | intel_check_cpu_fifo_underruns(dev_priv); | |
16034 | intel_check_pch_fifo_underruns(dev_priv); | |
16035 | ||
ecab0f3d | 16036 | if (state->modeset) |
855e0d68 | 16037 | intel_verify_planes(state); |
cff109f0 | 16038 | |
ecab0f3d | 16039 | intel_sagv_post_plane_update(state); |
656d1b89 | 16040 | |
855e0d68 | 16041 | drm_atomic_helper_commit_hw_done(&state->base); |
94f05024 | 16042 | |
855e0d68 | 16043 | if (state->modeset) { |
d5553c09 CW |
16044 | /* As one of the primary mmio accessors, KMS has a high |
16045 | * likelihood of triggering bugs in unclaimed access. After we | |
16046 | * finish modesetting, see if an error has been flagged, and if | |
16047 | * so enable debugging for the next modeset - and hope we catch | |
16048 | * the culprit. | |
16049 | */ | |
2cf7bf6f | 16050 | intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); |
0e6e0be4 | 16051 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); |
d5553c09 | 16052 | } |
855e0d68 | 16053 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); |
5a21b665 | 16054 | |
8d52e447 CW |
16055 | /* |
16056 | * Defer the cleanup of the old state to a separate worker to not | |
16057 | * impede the current task (userspace for blocking modesets) that | |
16058 | * are executed inline. For out-of-line asynchronous modesets/flips, | |
16059 | * deferring to a new worker seems overkill, but we would place a | |
16060 | * schedule point (cond_resched()) here anyway to keep latencies | |
16061 | * down. | |
16062 | */ | |
855e0d68 ML |
16063 | INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); |
16064 | queue_work(system_highpri_wq, &state->base.commit_work); | |
94f05024 DV |
16065 | } |
16066 | ||
16067 | static void intel_atomic_commit_work(struct work_struct *work) | |
16068 | { | |
855e0d68 ML |
16069 | struct intel_atomic_state *state = |
16070 | container_of(work, struct intel_atomic_state, base.commit_work); | |
c004a90b | 16071 | |
94f05024 DV |
16072 | intel_atomic_commit_tail(state); |
16073 | } | |
16074 | ||
c004a90b CW |
16075 | static int __i915_sw_fence_call |
16076 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
16077 | enum i915_sw_fence_notify notify) | |
16078 | { | |
16079 | struct intel_atomic_state *state = | |
16080 | container_of(fence, struct intel_atomic_state, commit_ready); | |
16081 | ||
16082 | switch (notify) { | |
16083 | case FENCE_COMPLETE: | |
42b062b0 | 16084 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 16085 | break; |
c004a90b | 16086 | case FENCE_FREE: |
eb955eee CW |
16087 | { |
16088 | struct intel_atomic_helper *helper = | |
16089 | &to_i915(state->base.dev)->atomic_helper; | |
16090 | ||
16091 | if (llist_add(&state->freed, &helper->free_list)) | |
16092 | schedule_work(&helper->free_work); | |
16093 | break; | |
16094 | } | |
c004a90b CW |
16095 | } |
16096 | ||
16097 | return NOTIFY_DONE; | |
16098 | } | |
16099 | ||
e3b4089c | 16100 | static void intel_atomic_track_fbs(struct intel_atomic_state *state) |
6c9c1b38 | 16101 | { |
e3b4089c VS |
16102 | struct intel_plane_state *old_plane_state, *new_plane_state; |
16103 | struct intel_plane *plane; | |
6c9c1b38 DV |
16104 | int i; |
16105 | ||
e3b4089c VS |
16106 | for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, |
16107 | new_plane_state, i) | |
7b3cb17a ML |
16108 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), |
16109 | to_intel_frontbuffer(new_plane_state->hw.fb), | |
8e7cb179 | 16110 | plane->frontbuffer_bit); |
6c9c1b38 DV |
16111 | } |
16112 | ||
94f05024 | 16113 | static int intel_atomic_commit(struct drm_device *dev, |
a85fb467 | 16114 | struct drm_atomic_state *_state, |
94f05024 DV |
16115 | bool nonblock) |
16116 | { | |
a85fb467 | 16117 | struct intel_atomic_state *state = to_intel_atomic_state(_state); |
fac5e23e | 16118 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
16119 | int ret = 0; |
16120 | ||
a85fb467 | 16121 | state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
2e2f08d0 | 16122 | |
a85fb467 VS |
16123 | drm_atomic_state_get(&state->base); |
16124 | i915_sw_fence_init(&state->commit_ready, | |
c004a90b | 16125 | intel_atomic_commit_ready); |
94f05024 | 16126 | |
440df938 VS |
16127 | /* |
16128 | * The intel_legacy_cursor_update() fast path takes care | |
16129 | * of avoiding the vblank waits for simple cursor | |
16130 | * movement and flips. For cursor on/off and size changes, | |
16131 | * we want to perform the vblank waits so that watermark | |
16132 | * updates happen during the correct frames. Gen9+ have | |
16133 | * double buffered watermarks and so shouldn't need this. | |
16134 | * | |
3cf50c63 ML |
16135 | * Unset state->legacy_cursor_update before the call to |
16136 | * drm_atomic_helper_setup_commit() because otherwise | |
16137 | * drm_atomic_helper_wait_for_flip_done() is a noop and | |
16138 | * we get FIFO underruns because we didn't wait | |
16139 | * for vblank. | |
440df938 VS |
16140 | * |
16141 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
16142 | * (assuming we had any) would solve these problems. | |
16143 | */ | |
a85fb467 | 16144 | if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) { |
213f1bd0 ML |
16145 | struct intel_crtc_state *new_crtc_state; |
16146 | struct intel_crtc *crtc; | |
16147 | int i; | |
16148 | ||
a85fb467 | 16149 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) |
213f1bd0 ML |
16150 | if (new_crtc_state->wm.need_postvbl_update || |
16151 | new_crtc_state->update_wm_post) | |
a85fb467 | 16152 | state->base.legacy_cursor_update = false; |
213f1bd0 | 16153 | } |
440df938 | 16154 | |
a85fb467 | 16155 | ret = intel_atomic_prepare_commit(state); |
3cf50c63 | 16156 | if (ret) { |
cd49f818 WK |
16157 | drm_dbg_atomic(&dev_priv->drm, |
16158 | "Preparing state failed with %i\n", ret); | |
a85fb467 VS |
16159 | i915_sw_fence_commit(&state->commit_ready); |
16160 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); | |
3cf50c63 ML |
16161 | return ret; |
16162 | } | |
16163 | ||
a85fb467 | 16164 | ret = drm_atomic_helper_setup_commit(&state->base, nonblock); |
3cf50c63 | 16165 | if (!ret) |
a85fb467 | 16166 | ret = drm_atomic_helper_swap_state(&state->base, true); |
0ef1905e VS |
16167 | if (!ret) |
16168 | intel_atomic_swap_global_state(state); | |
3cf50c63 | 16169 | |
0806f4ee | 16170 | if (ret) { |
afeda4f3 AM |
16171 | struct intel_crtc_state *new_crtc_state; |
16172 | struct intel_crtc *crtc; | |
16173 | int i; | |
16174 | ||
a85fb467 | 16175 | i915_sw_fence_commit(&state->commit_ready); |
0806f4ee | 16176 | |
afeda4f3 AM |
16177 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) |
16178 | intel_dsb_cleanup(new_crtc_state); | |
16179 | ||
a85fb467 VS |
16180 | drm_atomic_helper_cleanup_planes(dev, &state->base); |
16181 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); | |
0806f4ee ML |
16182 | return ret; |
16183 | } | |
94f05024 | 16184 | dev_priv->wm.distrust_bios_wm = false; |
a85fb467 VS |
16185 | intel_shared_dpll_swap_state(state); |
16186 | intel_atomic_track_fbs(state); | |
94f05024 | 16187 | |
a85fb467 VS |
16188 | drm_atomic_state_get(&state->base); |
16189 | INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); | |
c004a90b | 16190 | |
a85fb467 VS |
16191 | i915_sw_fence_commit(&state->commit_ready); |
16192 | if (nonblock && state->modeset) { | |
16193 | queue_work(dev_priv->modeset_wq, &state->base.commit_work); | |
757fffcf | 16194 | } else if (nonblock) { |
c26a0586 | 16195 | queue_work(dev_priv->flip_wq, &state->base.commit_work); |
757fffcf | 16196 | } else { |
a85fb467 | 16197 | if (state->modeset) |
757fffcf | 16198 | flush_workqueue(dev_priv->modeset_wq); |
a85fb467 | 16199 | intel_atomic_commit_tail(state); |
757fffcf | 16200 | } |
75714940 | 16201 | |
74c090b1 | 16202 | return 0; |
7f27126e JB |
16203 | } |
16204 | ||
74d290f8 CW |
16205 | struct wait_rps_boost { |
16206 | struct wait_queue_entry wait; | |
16207 | ||
16208 | struct drm_crtc *crtc; | |
e61e0f51 | 16209 | struct i915_request *request; |
74d290f8 CW |
16210 | }; |
16211 | ||
16212 | static int do_rps_boost(struct wait_queue_entry *_wait, | |
16213 | unsigned mode, int sync, void *key) | |
16214 | { | |
16215 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); | |
e61e0f51 | 16216 | struct i915_request *rq = wait->request; |
74d290f8 | 16217 | |
e9af4ea2 CW |
16218 | /* |
16219 | * If we missed the vblank, but the request is already running it | |
16220 | * is reasonable to assume that it will complete before the next | |
16221 | * vblank without our intervention, so leave RPS alone. | |
16222 | */ | |
e61e0f51 | 16223 | if (!i915_request_started(rq)) |
3e7abf81 | 16224 | intel_rps_boost(rq); |
e61e0f51 | 16225 | i915_request_put(rq); |
74d290f8 CW |
16226 | |
16227 | drm_crtc_vblank_put(wait->crtc); | |
16228 | ||
16229 | list_del(&wait->wait.entry); | |
16230 | kfree(wait); | |
16231 | return 1; | |
16232 | } | |
16233 | ||
16234 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, | |
16235 | struct dma_fence *fence) | |
16236 | { | |
16237 | struct wait_rps_boost *wait; | |
16238 | ||
16239 | if (!dma_fence_is_i915(fence)) | |
16240 | return; | |
16241 | ||
16242 | if (INTEL_GEN(to_i915(crtc->dev)) < 6) | |
16243 | return; | |
16244 | ||
16245 | if (drm_crtc_vblank_get(crtc)) | |
16246 | return; | |
16247 | ||
16248 | wait = kmalloc(sizeof(*wait), GFP_KERNEL); | |
16249 | if (!wait) { | |
16250 | drm_crtc_vblank_put(crtc); | |
16251 | return; | |
16252 | } | |
16253 | ||
16254 | wait->request = to_request(dma_fence_get(fence)); | |
16255 | wait->crtc = crtc; | |
16256 | ||
16257 | wait->wait.func = do_rps_boost; | |
16258 | wait->wait.flags = 0; | |
16259 | ||
16260 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); | |
16261 | } | |
16262 | ||
ef1a1914 VS |
16263 | static int intel_plane_pin_fb(struct intel_plane_state *plane_state) |
16264 | { | |
f90a85e7 | 16265 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
ef1a1914 | 16266 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 16267 | struct drm_framebuffer *fb = plane_state->hw.fb; |
ef1a1914 VS |
16268 | struct i915_vma *vma; |
16269 | ||
16270 | if (plane->id == PLANE_CURSOR && | |
d53db442 | 16271 | INTEL_INFO(dev_priv)->display.cursor_needs_physical) { |
ef1a1914 VS |
16272 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
16273 | const int align = intel_cursor_alignment(dev_priv); | |
4a477651 | 16274 | int err; |
ef1a1914 | 16275 | |
4a477651 CW |
16276 | err = i915_gem_object_attach_phys(obj, align); |
16277 | if (err) | |
16278 | return err; | |
ef1a1914 VS |
16279 | } |
16280 | ||
16281 | vma = intel_pin_and_fence_fb_obj(fb, | |
f5929c53 | 16282 | &plane_state->view, |
ef1a1914 VS |
16283 | intel_plane_uses_fence(plane_state), |
16284 | &plane_state->flags); | |
16285 | if (IS_ERR(vma)) | |
16286 | return PTR_ERR(vma); | |
16287 | ||
16288 | plane_state->vma = vma; | |
16289 | ||
16290 | return 0; | |
16291 | } | |
16292 | ||
16293 | static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) | |
16294 | { | |
16295 | struct i915_vma *vma; | |
16296 | ||
16297 | vma = fetch_and_zero(&old_plane_state->vma); | |
16298 | if (vma) | |
16299 | intel_unpin_fb_vma(vma, old_plane_state->flags); | |
16300 | } | |
16301 | ||
b7268c5e CW |
16302 | static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) |
16303 | { | |
16304 | struct i915_sched_attr attr = { | |
058179e7 | 16305 | .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY), |
b7268c5e CW |
16306 | }; |
16307 | ||
16308 | i915_gem_object_wait_priority(obj, 0, &attr); | |
16309 | } | |
16310 | ||
6beb8c23 MR |
16311 | /** |
16312 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
723196f4 | 16313 | * @_plane: drm plane to prepare for |
1fd37669 | 16314 | * @_new_plane_state: the plane state being prepared |
6beb8c23 MR |
16315 | * |
16316 | * Prepares a framebuffer for usage on a display plane. Generally this | |
16317 | * involves pinning the underlying object and updating the frontbuffer tracking | |
16318 | * bits. Some older platforms need special physical address handling for | |
16319 | * cursor planes. | |
16320 | * | |
16321 | * Returns 0 on success, negative error code on failure. | |
16322 | */ | |
16323 | int | |
b2faf669 | 16324 | intel_prepare_plane_fb(struct drm_plane *_plane, |
04c8b0bf | 16325 | struct drm_plane_state *_new_plane_state) |
465c120c | 16326 | { |
b2faf669 | 16327 | struct intel_plane *plane = to_intel_plane(_plane); |
04c8b0bf ML |
16328 | struct intel_plane_state *new_plane_state = |
16329 | to_intel_plane_state(_new_plane_state); | |
fa528334 | 16330 | struct intel_atomic_state *state = |
f90a85e7 | 16331 | to_intel_atomic_state(new_plane_state->uapi.state); |
b2faf669 VS |
16332 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
16333 | const struct intel_plane_state *old_plane_state = | |
fa528334 | 16334 | intel_atomic_get_old_plane_state(state, plane); |
b2faf669 VS |
16335 | struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb); |
16336 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb); | |
c004a90b | 16337 | int ret; |
465c120c | 16338 | |
5008e874 | 16339 | if (old_obj) { |
b2faf669 | 16340 | const struct intel_crtc_state *crtc_state = |
fa528334 | 16341 | intel_atomic_get_new_crtc_state(state, |
b2faf669 | 16342 | to_intel_crtc(old_plane_state->hw.crtc)); |
5008e874 ML |
16343 | |
16344 | /* Big Hammer, we also need to ensure that any pending | |
16345 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
16346 | * current scanout is retired before unpinning the old | |
16347 | * framebuffer. Note that we rely on userspace rendering | |
16348 | * into the buffer attached to the pipe they are waiting | |
16349 | * on. If not, userspace generates a GPU hang with IPEHR | |
16350 | * point to the MI_WAIT_FOR_EVENT. | |
16351 | * | |
16352 | * This should only fail upon a hung GPU, in which case we | |
16353 | * can safely continue. | |
16354 | */ | |
c004a90b | 16355 | if (needs_modeset(crtc_state)) { |
fa528334 | 16356 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
ef78f7b1 | 16357 | old_obj->base.resv, NULL, |
c004a90b CW |
16358 | false, 0, |
16359 | GFP_KERNEL); | |
16360 | if (ret < 0) | |
16361 | return ret; | |
f4457ae7 | 16362 | } |
5008e874 ML |
16363 | } |
16364 | ||
f90a85e7 | 16365 | if (new_plane_state->uapi.fence) { /* explicit fencing */ |
fa528334 | 16366 | ret = i915_sw_fence_await_dma_fence(&state->commit_ready, |
f90a85e7 | 16367 | new_plane_state->uapi.fence, |
16dc224f | 16368 | i915_fence_timeout(dev_priv), |
c004a90b CW |
16369 | GFP_KERNEL); |
16370 | if (ret < 0) | |
16371 | return ret; | |
16372 | } | |
16373 | ||
c37efb99 CW |
16374 | if (!obj) |
16375 | return 0; | |
16376 | ||
4d3088c7 | 16377 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
16378 | if (ret) |
16379 | return ret; | |
16380 | ||
04c8b0bf | 16381 | ret = intel_plane_pin_fb(new_plane_state); |
fd70075f | 16382 | |
4d3088c7 | 16383 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
16384 | if (ret) |
16385 | return ret; | |
16386 | ||
e2f3496e | 16387 | fb_obj_bump_render_priority(obj); |
da42104f | 16388 | i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB); |
07bcd99b | 16389 | |
f90a85e7 | 16390 | if (!new_plane_state->uapi.fence) { /* implicit fencing */ |
74d290f8 CW |
16391 | struct dma_fence *fence; |
16392 | ||
fa528334 | 16393 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
ef78f7b1 | 16394 | obj->base.resv, NULL, |
16dc224f CW |
16395 | false, |
16396 | i915_fence_timeout(dev_priv), | |
c004a90b CW |
16397 | GFP_KERNEL); |
16398 | if (ret < 0) | |
6fef8510 | 16399 | goto unpin_fb; |
74d290f8 | 16400 | |
52791eee | 16401 | fence = dma_resv_get_excl_rcu(obj->base.resv); |
74d290f8 | 16402 | if (fence) { |
7b3cb17a | 16403 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
04c8b0bf | 16404 | fence); |
74d290f8 CW |
16405 | dma_fence_put(fence); |
16406 | } | |
16407 | } else { | |
7b3cb17a | 16408 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
f90a85e7 | 16409 | new_plane_state->uapi.fence); |
c004a90b | 16410 | } |
5a21b665 | 16411 | |
60548c55 CW |
16412 | /* |
16413 | * We declare pageflips to be interactive and so merit a small bias | |
16414 | * towards upclocking to deliver the frame on time. By only changing | |
16415 | * the RPS thresholds to sample more regularly and aim for higher | |
16416 | * clocks we can hopefully deliver low power workloads (like kodi) | |
16417 | * that are not quite steady state without resorting to forcing | |
16418 | * maximum clocks following a vblank miss (see do_rps_boost()). | |
16419 | */ | |
fa528334 | 16420 | if (!state->rps_interactive) { |
3e7abf81 | 16421 | intel_rps_mark_interactive(&dev_priv->gt.rps, true); |
fa528334 | 16422 | state->rps_interactive = true; |
60548c55 CW |
16423 | } |
16424 | ||
d07f0e59 | 16425 | return 0; |
6fef8510 VS |
16426 | |
16427 | unpin_fb: | |
16428 | intel_plane_unpin_fb(new_plane_state); | |
16429 | ||
16430 | return ret; | |
6beb8c23 MR |
16431 | } |
16432 | ||
38f3ce3a MR |
16433 | /** |
16434 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
16435 | * @plane: drm plane to clean up for | |
1fd37669 | 16436 | * @_old_plane_state: the state from the previous modeset |
38f3ce3a MR |
16437 | * |
16438 | * Cleans up a framebuffer that has just been removed from a plane. | |
16439 | */ | |
16440 | void | |
16441 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
04c8b0bf | 16442 | struct drm_plane_state *_old_plane_state) |
38f3ce3a | 16443 | { |
04c8b0bf ML |
16444 | struct intel_plane_state *old_plane_state = |
16445 | to_intel_plane_state(_old_plane_state); | |
fa528334 | 16446 | struct intel_atomic_state *state = |
f90a85e7 | 16447 | to_intel_atomic_state(old_plane_state->uapi.state); |
ef1a1914 | 16448 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
58fa1760 VS |
16449 | struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb); |
16450 | ||
16451 | if (!obj) | |
16452 | return; | |
38f3ce3a | 16453 | |
fa528334 | 16454 | if (state->rps_interactive) { |
3e7abf81 | 16455 | intel_rps_mark_interactive(&dev_priv->gt.rps, false); |
fa528334 | 16456 | state->rps_interactive = false; |
60548c55 CW |
16457 | } |
16458 | ||
be1e3415 | 16459 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
04c8b0bf | 16460 | intel_plane_unpin_fb(old_plane_state); |
465c120c MR |
16461 | } |
16462 | ||
cf4c7c12 | 16463 | /** |
4a3b8769 MR |
16464 | * intel_plane_destroy - destroy a plane |
16465 | * @plane: plane to destroy | |
cf4c7c12 | 16466 | * |
4a3b8769 MR |
16467 | * Common destruction function for all types of planes (primary, cursor, |
16468 | * sprite). | |
cf4c7c12 | 16469 | */ |
4a3b8769 | 16470 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 16471 | { |
465c120c | 16472 | drm_plane_cleanup(plane); |
69ae561f | 16473 | kfree(to_intel_plane(plane)); |
465c120c MR |
16474 | } |
16475 | ||
a38189c5 VS |
16476 | static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, |
16477 | u32 format, u64 modifier) | |
714244e2 | 16478 | { |
a38189c5 VS |
16479 | switch (modifier) { |
16480 | case DRM_FORMAT_MOD_LINEAR: | |
16481 | case I915_FORMAT_MOD_X_TILED: | |
16482 | break; | |
16483 | default: | |
16484 | return false; | |
16485 | } | |
16486 | ||
714244e2 BW |
16487 | switch (format) { |
16488 | case DRM_FORMAT_C8: | |
16489 | case DRM_FORMAT_RGB565: | |
16490 | case DRM_FORMAT_XRGB1555: | |
16491 | case DRM_FORMAT_XRGB8888: | |
16492 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
16493 | modifier == I915_FORMAT_MOD_X_TILED; | |
16494 | default: | |
16495 | return false; | |
16496 | } | |
16497 | } | |
16498 | ||
a38189c5 VS |
16499 | static bool i965_plane_format_mod_supported(struct drm_plane *_plane, |
16500 | u32 format, u64 modifier) | |
714244e2 | 16501 | { |
a38189c5 VS |
16502 | switch (modifier) { |
16503 | case DRM_FORMAT_MOD_LINEAR: | |
16504 | case I915_FORMAT_MOD_X_TILED: | |
16505 | break; | |
16506 | default: | |
16507 | return false; | |
16508 | } | |
16509 | ||
714244e2 BW |
16510 | switch (format) { |
16511 | case DRM_FORMAT_C8: | |
16512 | case DRM_FORMAT_RGB565: | |
16513 | case DRM_FORMAT_XRGB8888: | |
16514 | case DRM_FORMAT_XBGR8888: | |
73263cb6 VS |
16515 | case DRM_FORMAT_ARGB8888: |
16516 | case DRM_FORMAT_ABGR8888: | |
714244e2 BW |
16517 | case DRM_FORMAT_XRGB2101010: |
16518 | case DRM_FORMAT_XBGR2101010: | |
73263cb6 VS |
16519 | case DRM_FORMAT_ARGB2101010: |
16520 | case DRM_FORMAT_ABGR2101010: | |
03b0ce95 | 16521 | case DRM_FORMAT_XBGR16161616F: |
714244e2 BW |
16522 | return modifier == DRM_FORMAT_MOD_LINEAR || |
16523 | modifier == I915_FORMAT_MOD_X_TILED; | |
16524 | default: | |
16525 | return false; | |
16526 | } | |
16527 | } | |
16528 | ||
a38189c5 VS |
16529 | static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, |
16530 | u32 format, u64 modifier) | |
714244e2 | 16531 | { |
a38189c5 VS |
16532 | return modifier == DRM_FORMAT_MOD_LINEAR && |
16533 | format == DRM_FORMAT_ARGB8888; | |
714244e2 BW |
16534 | } |
16535 | ||
679bfe84 | 16536 | static const struct drm_plane_funcs i965_plane_funcs = { |
a38189c5 VS |
16537 | .update_plane = drm_atomic_helper_update_plane, |
16538 | .disable_plane = drm_atomic_helper_disable_plane, | |
16539 | .destroy = intel_plane_destroy, | |
a38189c5 VS |
16540 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16541 | .atomic_destroy_state = intel_plane_destroy_state, | |
16542 | .format_mod_supported = i965_plane_format_mod_supported, | |
16543 | }; | |
714244e2 | 16544 | |
679bfe84 | 16545 | static const struct drm_plane_funcs i8xx_plane_funcs = { |
70a101f8 MR |
16546 | .update_plane = drm_atomic_helper_update_plane, |
16547 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 16548 | .destroy = intel_plane_destroy, |
ea2c67bb MR |
16549 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16550 | .atomic_destroy_state = intel_plane_destroy_state, | |
a38189c5 | 16551 | .format_mod_supported = i8xx_plane_format_mod_supported, |
465c120c MR |
16552 | }; |
16553 | ||
f79f2692 | 16554 | static int |
4078c983 VS |
16555 | intel_legacy_cursor_update(struct drm_plane *_plane, |
16556 | struct drm_crtc *_crtc, | |
f79f2692 ML |
16557 | struct drm_framebuffer *fb, |
16558 | int crtc_x, int crtc_y, | |
16559 | unsigned int crtc_w, unsigned int crtc_h, | |
ba3f4d0a JN |
16560 | u32 src_x, u32 src_y, |
16561 | u32 src_w, u32 src_h, | |
34a2ab5e | 16562 | struct drm_modeset_acquire_ctx *ctx) |
f79f2692 | 16563 | { |
4078c983 VS |
16564 | struct intel_plane *plane = to_intel_plane(_plane); |
16565 | struct intel_crtc *crtc = to_intel_crtc(_crtc); | |
16566 | struct intel_plane_state *old_plane_state = | |
16567 | to_intel_plane_state(plane->base.state); | |
16568 | struct intel_plane_state *new_plane_state; | |
c249c5f6 | 16569 | struct intel_crtc_state *crtc_state = |
4078c983 | 16570 | to_intel_crtc_state(crtc->base.state); |
c249c5f6 | 16571 | struct intel_crtc_state *new_crtc_state; |
8e7cb179 | 16572 | int ret; |
f79f2692 ML |
16573 | |
16574 | /* | |
16575 | * When crtc is inactive or there is a modeset pending, | |
16576 | * wait for it to complete in the slowpath | |
16577 | */ | |
1326a92c | 16578 | if (!crtc_state->hw.active || needs_modeset(crtc_state) || |
c249c5f6 | 16579 | crtc_state->update_pipe) |
f79f2692 ML |
16580 | goto slow; |
16581 | ||
669c9215 ML |
16582 | /* |
16583 | * Don't do an async update if there is an outstanding commit modifying | |
16584 | * the plane. This prevents our async update's changes from getting | |
16585 | * overridden by a previous synchronous update's state. | |
16586 | */ | |
f90a85e7 ML |
16587 | if (old_plane_state->uapi.commit && |
16588 | !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) | |
669c9215 | 16589 | goto slow; |
f79f2692 ML |
16590 | |
16591 | /* | |
16592 | * If any parameters change that may affect watermarks, | |
16593 | * take the slowpath. Only changing fb or position should be | |
16594 | * in the fastpath. | |
16595 | */ | |
a456f65f ML |
16596 | if (old_plane_state->uapi.crtc != &crtc->base || |
16597 | old_plane_state->uapi.src_w != src_w || | |
16598 | old_plane_state->uapi.src_h != src_h || | |
16599 | old_plane_state->uapi.crtc_w != crtc_w || | |
16600 | old_plane_state->uapi.crtc_h != crtc_h || | |
16601 | !old_plane_state->uapi.fb != !fb) | |
f79f2692 ML |
16602 | goto slow; |
16603 | ||
4078c983 | 16604 | new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); |
f79f2692 ML |
16605 | if (!new_plane_state) |
16606 | return -ENOMEM; | |
16607 | ||
4078c983 | 16608 | new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); |
c249c5f6 ML |
16609 | if (!new_crtc_state) { |
16610 | ret = -ENOMEM; | |
16611 | goto out_free; | |
16612 | } | |
16613 | ||
a456f65f | 16614 | drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); |
f79f2692 | 16615 | |
a456f65f ML |
16616 | new_plane_state->uapi.src_x = src_x; |
16617 | new_plane_state->uapi.src_y = src_y; | |
16618 | new_plane_state->uapi.src_w = src_w; | |
16619 | new_plane_state->uapi.src_h = src_h; | |
16620 | new_plane_state->uapi.crtc_x = crtc_x; | |
16621 | new_plane_state->uapi.crtc_y = crtc_y; | |
16622 | new_plane_state->uapi.crtc_w = crtc_w; | |
16623 | new_plane_state->uapi.crtc_h = crtc_h; | |
f79f2692 | 16624 | |
7d8d2cbc VS |
16625 | intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); |
16626 | ||
c249c5f6 | 16627 | ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, |
4078c983 | 16628 | old_plane_state, new_plane_state); |
f79f2692 ML |
16629 | if (ret) |
16630 | goto out_free; | |
16631 | ||
4078c983 | 16632 | ret = intel_plane_pin_fb(new_plane_state); |
ef1a1914 | 16633 | if (ret) |
2850748e | 16634 | goto out_free; |
f79f2692 | 16635 | |
a456f65f ML |
16636 | intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), |
16637 | ORIGIN_FLIP); | |
16638 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), | |
16639 | to_intel_frontbuffer(new_plane_state->hw.fb), | |
4078c983 | 16640 | plane->frontbuffer_bit); |
f79f2692 ML |
16641 | |
16642 | /* Swap plane state */ | |
a456f65f | 16643 | plane->base.state = &new_plane_state->uapi; |
f79f2692 | 16644 | |
c249c5f6 ML |
16645 | /* |
16646 | * We cannot swap crtc_state as it may be in use by an atomic commit or | |
16647 | * page flip that's running simultaneously. If we swap crtc_state and | |
16648 | * destroy the old state, we will cause a use-after-free there. | |
16649 | * | |
16650 | * Only update active_planes, which is needed for our internal | |
16651 | * bookkeeping. Either value will do the right thing when updating | |
16652 | * planes atomically. If the cursor was part of the atomic update then | |
16653 | * we would have taken the slowpath. | |
16654 | */ | |
16655 | crtc_state->active_planes = new_crtc_state->active_planes; | |
16656 | ||
a456f65f | 16657 | if (new_plane_state->uapi.visible) |
4078c983 | 16658 | intel_update_plane(plane, crtc_state, new_plane_state); |
c48b86f9 | 16659 | else |
4078c983 | 16660 | intel_disable_plane(plane, crtc_state); |
f79f2692 | 16661 | |
4078c983 | 16662 | intel_plane_unpin_fb(old_plane_state); |
f79f2692 | 16663 | |
f79f2692 | 16664 | out_free: |
c249c5f6 | 16665 | if (new_crtc_state) |
2225f3c6 | 16666 | intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); |
669c9215 | 16667 | if (ret) |
a456f65f | 16668 | intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); |
669c9215 | 16669 | else |
a456f65f | 16670 | intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); |
f79f2692 ML |
16671 | return ret; |
16672 | ||
f79f2692 | 16673 | slow: |
4078c983 | 16674 | return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, |
f79f2692 | 16675 | crtc_x, crtc_y, crtc_w, crtc_h, |
34a2ab5e | 16676 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
16677 | } |
16678 | ||
16679 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
16680 | .update_plane = intel_legacy_cursor_update, | |
16681 | .disable_plane = drm_atomic_helper_disable_plane, | |
16682 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
16683 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16684 | .atomic_destroy_state = intel_plane_destroy_state, | |
a38189c5 | 16685 | .format_mod_supported = intel_cursor_format_mod_supported, |
f79f2692 ML |
16686 | }; |
16687 | ||
cf1805e6 VS |
16688 | static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, |
16689 | enum i9xx_plane_id i9xx_plane) | |
16690 | { | |
16691 | if (!HAS_FBC(dev_priv)) | |
16692 | return false; | |
16693 | ||
16694 | if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
16695 | return i9xx_plane == PLANE_A; /* tied to pipe A */ | |
16696 | else if (IS_IVYBRIDGE(dev_priv)) | |
16697 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || | |
16698 | i9xx_plane == PLANE_C; | |
16699 | else if (INTEL_GEN(dev_priv) >= 4) | |
16700 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; | |
16701 | else | |
16702 | return i9xx_plane == PLANE_A; | |
16703 | } | |
16704 | ||
b079bd17 | 16705 | static struct intel_plane * |
580503c7 | 16706 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 16707 | { |
881440a8 | 16708 | struct intel_plane *plane; |
a38189c5 | 16709 | const struct drm_plane_funcs *plane_funcs; |
93ca7e00 | 16710 | unsigned int supported_rotations; |
881440a8 VS |
16711 | const u32 *formats; |
16712 | int num_formats; | |
ca9cab18 | 16713 | int ret, zpos; |
465c120c | 16714 | |
b7c80600 VS |
16715 | if (INTEL_GEN(dev_priv) >= 9) |
16716 | return skl_universal_plane_create(dev_priv, pipe, | |
16717 | PLANE_PRIMARY); | |
16718 | ||
881440a8 VS |
16719 | plane = intel_plane_alloc(); |
16720 | if (IS_ERR(plane)) | |
16721 | return plane; | |
ea2c67bb | 16722 | |
881440a8 | 16723 | plane->pipe = pipe; |
e3c566df VS |
16724 | /* |
16725 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
16726 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
16727 | */ | |
ddf08d32 VS |
16728 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 && |
16729 | INTEL_NUM_PIPES(dev_priv) == 2) | |
881440a8 | 16730 | plane->i9xx_plane = (enum i9xx_plane_id) !pipe; |
e3c566df | 16731 | else |
881440a8 VS |
16732 | plane->i9xx_plane = (enum i9xx_plane_id) pipe; |
16733 | plane->id = PLANE_PRIMARY; | |
16734 | plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); | |
cf1805e6 | 16735 | |
881440a8 VS |
16736 | plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); |
16737 | if (plane->has_fbc) { | |
cf1805e6 VS |
16738 | struct intel_fbc *fbc = &dev_priv->fbc; |
16739 | ||
881440a8 | 16740 | fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; |
cf1805e6 VS |
16741 | } |
16742 | ||
73263cb6 VS |
16743 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
16744 | formats = vlv_primary_formats; | |
16745 | num_formats = ARRAY_SIZE(vlv_primary_formats); | |
73263cb6 | 16746 | } else if (INTEL_GEN(dev_priv) >= 4) { |
03b0ce95 VS |
16747 | /* |
16748 | * WaFP16GammaEnabling:ivb | |
16749 | * "Workaround : When using the 64-bit format, the plane | |
16750 | * output on each color channel has one quarter amplitude. | |
16751 | * It can be brought up to full amplitude by using pipe | |
16752 | * gamma correction or pipe color space conversion to | |
16753 | * multiply the plane output by four." | |
16754 | * | |
16755 | * There is no dedicated plane gamma for the primary plane, | |
16756 | * and using the pipe gamma/csc could conflict with other | |
16757 | * planes, so we choose not to expose fp16 on IVB primary | |
16758 | * planes. HSW primary planes no longer have this problem. | |
16759 | */ | |
16760 | if (IS_IVYBRIDGE(dev_priv)) { | |
16761 | formats = ivb_primary_formats; | |
16762 | num_formats = ARRAY_SIZE(ivb_primary_formats); | |
16763 | } else { | |
16764 | formats = i965_primary_formats; | |
16765 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
16766 | } | |
6c0fd451 | 16767 | } else { |
881440a8 | 16768 | formats = i8xx_primary_formats; |
6c0fd451 | 16769 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
dbb1a6fb | 16770 | } |
a8d201af | 16771 | |
dbb1a6fb VS |
16772 | if (INTEL_GEN(dev_priv) >= 4) |
16773 | plane_funcs = &i965_plane_funcs; | |
16774 | else | |
16775 | plane_funcs = &i8xx_plane_funcs; | |
16776 | ||
16777 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
16778 | plane->min_cdclk = vlv_plane_min_cdclk; | |
16779 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
16780 | plane->min_cdclk = hsw_plane_min_cdclk; | |
16781 | else if (IS_IVYBRIDGE(dev_priv)) | |
16782 | plane->min_cdclk = ivb_plane_min_cdclk; | |
16783 | else | |
bb6ae9e6 | 16784 | plane->min_cdclk = i9xx_plane_min_cdclk; |
a38189c5 | 16785 | |
dbb1a6fb VS |
16786 | plane->max_stride = i9xx_plane_max_stride; |
16787 | plane->update_plane = i9xx_update_plane; | |
16788 | plane->disable_plane = i9xx_disable_plane; | |
16789 | plane->get_hw_state = i9xx_plane_get_hw_state; | |
16790 | plane->check_plane = i9xx_plane_check; | |
465c120c | 16791 | |
b7c80600 | 16792 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
881440a8 | 16793 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
6875eb3f | 16794 | 0, plane_funcs, |
dbb1a6fb VS |
16795 | formats, num_formats, |
16796 | i9xx_format_modifiers, | |
38573dc1 VS |
16797 | DRM_PLANE_TYPE_PRIMARY, |
16798 | "primary %c", pipe_name(pipe)); | |
16799 | else | |
881440a8 | 16800 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
6875eb3f | 16801 | 0, plane_funcs, |
dbb1a6fb VS |
16802 | formats, num_formats, |
16803 | i9xx_format_modifiers, | |
38573dc1 | 16804 | DRM_PLANE_TYPE_PRIMARY, |
ed15030d | 16805 | "plane %c", |
881440a8 | 16806 | plane_name(plane->i9xx_plane)); |
fca0ce2a VS |
16807 | if (ret) |
16808 | goto fail; | |
48404c1e | 16809 | |
b7c80600 | 16810 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
4ea7be2b | 16811 | supported_rotations = |
c2c446ad RF |
16812 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
16813 | DRM_MODE_REFLECT_X; | |
5481e27f | 16814 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 16815 | supported_rotations = |
c2c446ad | 16816 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 16817 | } else { |
c2c446ad | 16818 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
16819 | } |
16820 | ||
5481e27f | 16821 | if (INTEL_GEN(dev_priv) >= 4) |
881440a8 | 16822 | drm_plane_create_rotation_property(&plane->base, |
c2c446ad | 16823 | DRM_MODE_ROTATE_0, |
93ca7e00 | 16824 | supported_rotations); |
48404c1e | 16825 | |
ca9cab18 VS |
16826 | zpos = 0; |
16827 | drm_plane_create_zpos_immutable_property(&plane->base, zpos); | |
16828 | ||
881440a8 | 16829 | drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); |
ea2c67bb | 16830 | |
881440a8 | 16831 | return plane; |
fca0ce2a VS |
16832 | |
16833 | fail: | |
881440a8 | 16834 | intel_plane_free(plane); |
fca0ce2a | 16835 | |
b079bd17 | 16836 | return ERR_PTR(ret); |
465c120c MR |
16837 | } |
16838 | ||
b079bd17 | 16839 | static struct intel_plane * |
b2d03b0d VS |
16840 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
16841 | enum pipe pipe) | |
3d7d6510 | 16842 | { |
c539b579 | 16843 | struct intel_plane *cursor; |
ca9cab18 | 16844 | int ret, zpos; |
3d7d6510 | 16845 | |
c539b579 VS |
16846 | cursor = intel_plane_alloc(); |
16847 | if (IS_ERR(cursor)) | |
16848 | return cursor; | |
ea2c67bb | 16849 | |
3d7d6510 | 16850 | cursor->pipe = pipe; |
ed15030d | 16851 | cursor->i9xx_plane = (enum i9xx_plane_id) pipe; |
b14e5848 | 16852 | cursor->id = PLANE_CURSOR; |
c19e1124 | 16853 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); |
b2d03b0d VS |
16854 | |
16855 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
ddd5713d | 16856 | cursor->max_stride = i845_cursor_max_stride; |
b2d03b0d VS |
16857 | cursor->update_plane = i845_update_cursor; |
16858 | cursor->disable_plane = i845_disable_cursor; | |
51f5a096 | 16859 | cursor->get_hw_state = i845_cursor_get_hw_state; |
659056f2 | 16860 | cursor->check_plane = i845_check_cursor; |
b2d03b0d | 16861 | } else { |
ddd5713d | 16862 | cursor->max_stride = i9xx_cursor_max_stride; |
b2d03b0d VS |
16863 | cursor->update_plane = i9xx_update_cursor; |
16864 | cursor->disable_plane = i9xx_disable_cursor; | |
51f5a096 | 16865 | cursor->get_hw_state = i9xx_cursor_get_hw_state; |
659056f2 | 16866 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 16867 | } |
3d7d6510 | 16868 | |
cd5dcbf1 VS |
16869 | cursor->cursor.base = ~0; |
16870 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
16871 | |
16872 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
16873 | cursor->cursor.size = ~0; | |
3d7d6510 | 16874 | |
580503c7 | 16875 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
6875eb3f | 16876 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
16877 | intel_cursor_formats, |
16878 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
16879 | cursor_format_modifiers, |
16880 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 16881 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
16882 | if (ret) |
16883 | goto fail; | |
4398ad45 | 16884 | |
5481e27f | 16885 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 16886 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
16887 | DRM_MODE_ROTATE_0, |
16888 | DRM_MODE_ROTATE_0 | | |
16889 | DRM_MODE_ROTATE_180); | |
4398ad45 | 16890 | |
ca9cab18 VS |
16891 | zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; |
16892 | drm_plane_create_zpos_immutable_property(&cursor->base, zpos); | |
16893 | ||
093a3a30 JRS |
16894 | if (INTEL_GEN(dev_priv) >= 12) |
16895 | drm_plane_enable_fb_damage_clips(&cursor->base); | |
16896 | ||
ea2c67bb MR |
16897 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
16898 | ||
b079bd17 | 16899 | return cursor; |
fca0ce2a VS |
16900 | |
16901 | fail: | |
c539b579 | 16902 | intel_plane_free(cursor); |
fca0ce2a | 16903 | |
b079bd17 | 16904 | return ERR_PTR(ret); |
3d7d6510 MR |
16905 | } |
16906 | ||
08fa8fd0 VS |
16907 | #define INTEL_CRTC_FUNCS \ |
16908 | .gamma_set = drm_atomic_helper_legacy_gamma_set, \ | |
16909 | .set_config = drm_atomic_helper_set_config, \ | |
16910 | .destroy = intel_crtc_destroy, \ | |
16911 | .page_flip = drm_atomic_helper_page_flip, \ | |
16912 | .atomic_duplicate_state = intel_crtc_duplicate_state, \ | |
16913 | .atomic_destroy_state = intel_crtc_destroy_state, \ | |
16914 | .set_crc_source = intel_crtc_set_crc_source, \ | |
16915 | .verify_crc_source = intel_crtc_verify_crc_source, \ | |
16916 | .get_crc_sources = intel_crtc_get_crc_sources | |
16917 | ||
16918 | static const struct drm_crtc_funcs bdw_crtc_funcs = { | |
16919 | INTEL_CRTC_FUNCS, | |
16920 | ||
16921 | .get_vblank_counter = g4x_get_vblank_counter, | |
16922 | .enable_vblank = bdw_enable_vblank, | |
16923 | .disable_vblank = bdw_disable_vblank, | |
4bbffbf3 | 16924 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16925 | }; |
16926 | ||
16927 | static const struct drm_crtc_funcs ilk_crtc_funcs = { | |
16928 | INTEL_CRTC_FUNCS, | |
16929 | ||
16930 | .get_vblank_counter = g4x_get_vblank_counter, | |
16931 | .enable_vblank = ilk_enable_vblank, | |
16932 | .disable_vblank = ilk_disable_vblank, | |
4bbffbf3 | 16933 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16934 | }; |
16935 | ||
16936 | static const struct drm_crtc_funcs g4x_crtc_funcs = { | |
16937 | INTEL_CRTC_FUNCS, | |
16938 | ||
16939 | .get_vblank_counter = g4x_get_vblank_counter, | |
16940 | .enable_vblank = i965_enable_vblank, | |
16941 | .disable_vblank = i965_disable_vblank, | |
4bbffbf3 | 16942 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16943 | }; |
16944 | ||
16945 | static const struct drm_crtc_funcs i965_crtc_funcs = { | |
16946 | INTEL_CRTC_FUNCS, | |
16947 | ||
16948 | .get_vblank_counter = i915_get_vblank_counter, | |
16949 | .enable_vblank = i965_enable_vblank, | |
16950 | .disable_vblank = i965_disable_vblank, | |
4bbffbf3 | 16951 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16952 | }; |
16953 | ||
7d423af9 | 16954 | static const struct drm_crtc_funcs i915gm_crtc_funcs = { |
08fa8fd0 VS |
16955 | INTEL_CRTC_FUNCS, |
16956 | ||
16957 | .get_vblank_counter = i915_get_vblank_counter, | |
7d423af9 VS |
16958 | .enable_vblank = i915gm_enable_vblank, |
16959 | .disable_vblank = i915gm_disable_vblank, | |
4bbffbf3 | 16960 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16961 | }; |
16962 | ||
16963 | static const struct drm_crtc_funcs i915_crtc_funcs = { | |
16964 | INTEL_CRTC_FUNCS, | |
16965 | ||
16966 | .get_vblank_counter = i915_get_vblank_counter, | |
16967 | .enable_vblank = i8xx_enable_vblank, | |
16968 | .disable_vblank = i8xx_disable_vblank, | |
4bbffbf3 | 16969 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16970 | }; |
16971 | ||
16972 | static const struct drm_crtc_funcs i8xx_crtc_funcs = { | |
16973 | INTEL_CRTC_FUNCS, | |
16974 | ||
16975 | /* no hw vblank counter */ | |
16976 | .enable_vblank = i8xx_enable_vblank, | |
16977 | .disable_vblank = i8xx_disable_vblank, | |
4bbffbf3 | 16978 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16979 | }; |
16980 | ||
66434539 | 16981 | static struct intel_crtc *intel_crtc_alloc(void) |
79e53945 | 16982 | { |
66434539 | 16983 | struct intel_crtc_state *crtc_state; |
f44bfa7f | 16984 | struct intel_crtc *crtc; |
79e53945 | 16985 | |
f44bfa7f VS |
16986 | crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); |
16987 | if (!crtc) | |
66434539 | 16988 | return ERR_PTR(-ENOMEM); |
79e53945 | 16989 | |
216383e9 | 16990 | crtc_state = intel_crtc_state_alloc(crtc); |
b079bd17 | 16991 | if (!crtc_state) { |
66434539 VS |
16992 | kfree(crtc); |
16993 | return ERR_PTR(-ENOMEM); | |
b079bd17 | 16994 | } |
66434539 | 16995 | |
979e94c1 | 16996 | crtc->base.state = &crtc_state->uapi; |
f44bfa7f | 16997 | crtc->config = crtc_state; |
f5de6e07 | 16998 | |
66434539 VS |
16999 | return crtc; |
17000 | } | |
17001 | ||
17002 | static void intel_crtc_free(struct intel_crtc *crtc) | |
17003 | { | |
17004 | intel_crtc_destroy_state(&crtc->base, crtc->base.state); | |
17005 | kfree(crtc); | |
17006 | } | |
17007 | ||
6875eb3f AG |
17008 | static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) |
17009 | { | |
17010 | struct intel_plane *plane; | |
17011 | ||
17012 | for_each_intel_plane(&dev_priv->drm, plane) { | |
17013 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, | |
17014 | plane->pipe); | |
17015 | ||
17016 | plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); | |
17017 | } | |
17018 | } | |
17019 | ||
66434539 VS |
17020 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
17021 | { | |
17022 | struct intel_plane *primary, *cursor; | |
17023 | const struct drm_crtc_funcs *funcs; | |
17024 | struct intel_crtc *crtc; | |
17025 | int sprite, ret; | |
17026 | ||
17027 | crtc = intel_crtc_alloc(); | |
17028 | if (IS_ERR(crtc)) | |
17029 | return PTR_ERR(crtc); | |
17030 | ||
17031 | crtc->pipe = pipe; | |
17032 | crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe]; | |
17033 | ||
580503c7 | 17034 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
17035 | if (IS_ERR(primary)) { |
17036 | ret = PTR_ERR(primary); | |
3d7d6510 | 17037 | goto fail; |
b079bd17 | 17038 | } |
f44bfa7f | 17039 | crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 17040 | |
a81d6fa0 | 17041 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
17042 | struct intel_plane *plane; |
17043 | ||
580503c7 | 17044 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 17045 | if (IS_ERR(plane)) { |
b079bd17 VS |
17046 | ret = PTR_ERR(plane); |
17047 | goto fail; | |
17048 | } | |
f44bfa7f | 17049 | crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
17050 | } |
17051 | ||
580503c7 | 17052 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 17053 | if (IS_ERR(cursor)) { |
b079bd17 | 17054 | ret = PTR_ERR(cursor); |
3d7d6510 | 17055 | goto fail; |
b079bd17 | 17056 | } |
f44bfa7f | 17057 | crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 17058 | |
08fa8fd0 VS |
17059 | if (HAS_GMCH(dev_priv)) { |
17060 | if (IS_CHERRYVIEW(dev_priv) || | |
17061 | IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) | |
17062 | funcs = &g4x_crtc_funcs; | |
17063 | else if (IS_GEN(dev_priv, 4)) | |
17064 | funcs = &i965_crtc_funcs; | |
7d423af9 VS |
17065 | else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) |
17066 | funcs = &i915gm_crtc_funcs; | |
08fa8fd0 VS |
17067 | else if (IS_GEN(dev_priv, 3)) |
17068 | funcs = &i915_crtc_funcs; | |
17069 | else | |
17070 | funcs = &i8xx_crtc_funcs; | |
17071 | } else { | |
17072 | if (INTEL_GEN(dev_priv) >= 8) | |
17073 | funcs = &bdw_crtc_funcs; | |
17074 | else | |
17075 | funcs = &ilk_crtc_funcs; | |
17076 | } | |
17077 | ||
f44bfa7f | 17078 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, |
b079bd17 | 17079 | &primary->base, &cursor->base, |
08fa8fd0 | 17080 | funcs, "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
17081 | if (ret) |
17082 | goto fail; | |
79e53945 | 17083 | |
1947fd13 VS |
17084 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || |
17085 | dev_priv->pipe_to_crtc_mapping[pipe] != NULL); | |
f44bfa7f | 17086 | dev_priv->pipe_to_crtc_mapping[pipe] = crtc; |
1947fd13 VS |
17087 | |
17088 | if (INTEL_GEN(dev_priv) < 9) { | |
17089 | enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; | |
17090 | ||
17091 | BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || | |
17092 | dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); | |
f44bfa7f | 17093 | dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; |
1947fd13 | 17094 | } |
22fd0fab | 17095 | |
6d1a2fde PB |
17096 | if (INTEL_GEN(dev_priv) >= 10) |
17097 | drm_crtc_create_scaling_filter_property(&crtc->base, | |
17098 | BIT(DRM_SCALING_FILTER_DEFAULT) | | |
17099 | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); | |
17100 | ||
f44bfa7f | 17101 | intel_color_init(crtc); |
8563b1e8 | 17102 | |
00535527 JN |
17103 | intel_crtc_crc_init(crtc); |
17104 | ||
e57291c2 | 17105 | drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); |
b079bd17 VS |
17106 | |
17107 | return 0; | |
3d7d6510 MR |
17108 | |
17109 | fail: | |
66434539 | 17110 | intel_crtc_free(crtc); |
b079bd17 VS |
17111 | |
17112 | return ret; | |
79e53945 JB |
17113 | } |
17114 | ||
6a20fe7b VS |
17115 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
17116 | struct drm_file *file) | |
08d7b3d1 | 17117 | { |
08d7b3d1 | 17118 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 17119 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 17120 | struct intel_crtc *crtc; |
08d7b3d1 | 17121 | |
418da172 | 17122 | drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); |
71240ed2 | 17123 | if (!drmmode_crtc) |
3f2c2057 | 17124 | return -ENOENT; |
08d7b3d1 | 17125 | |
7707e653 | 17126 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 17127 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 17128 | |
c05422d5 | 17129 | return 0; |
08d7b3d1 CW |
17130 | } |
17131 | ||
c08f995a | 17132 | static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) |
79e53945 | 17133 | { |
66a9278e DV |
17134 | struct drm_device *dev = encoder->base.dev; |
17135 | struct intel_encoder *source_encoder; | |
c08f995a | 17136 | u32 possible_clones = 0; |
79e53945 | 17137 | |
b2784e15 | 17138 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 17139 | if (encoders_cloneable(encoder, source_encoder)) |
c08f995a | 17140 | possible_clones |= drm_encoder_mask(&source_encoder->base); |
79e53945 | 17141 | } |
4ef69c7a | 17142 | |
c08f995a | 17143 | return possible_clones; |
79e53945 JB |
17144 | } |
17145 | ||
ed500bf6 VS |
17146 | static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) |
17147 | { | |
17148 | struct drm_device *dev = encoder->base.dev; | |
17149 | struct intel_crtc *crtc; | |
17150 | u32 possible_crtcs = 0; | |
17151 | ||
17152 | for_each_intel_crtc(dev, crtc) { | |
981329ce | 17153 | if (encoder->pipe_mask & BIT(crtc->pipe)) |
ed500bf6 VS |
17154 | possible_crtcs |= drm_crtc_mask(&crtc->base); |
17155 | } | |
17156 | ||
17157 | return possible_crtcs; | |
17158 | } | |
17159 | ||
a5916fd7 | 17160 | static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 17161 | { |
646d5772 | 17162 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
17163 | return false; |
17164 | ||
dc008bf0 | 17165 | if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) |
4d302442 CW |
17166 | return false; |
17167 | ||
dc008bf0 | 17168 | if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
17169 | return false; |
17170 | ||
17171 | return true; | |
17172 | } | |
17173 | ||
63cb4e64 | 17174 | static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 17175 | { |
6315b5d3 | 17176 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
17177 | return false; |
17178 | ||
50a0bc90 | 17179 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
17180 | return false; |
17181 | ||
4f8036a2 | 17182 | if (HAS_PCH_LPT_H(dev_priv) && |
dc008bf0 | 17183 | intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
65e472e4 VS |
17184 | return false; |
17185 | ||
70ac54d0 | 17186 | /* DDI E can't be used if DDI A requires 4 lanes */ |
dc008bf0 | 17187 | if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
17188 | return false; |
17189 | ||
e4abb733 | 17190 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
17191 | return false; |
17192 | ||
17193 | return true; | |
17194 | } | |
17195 | ||
8090ba8c ID |
17196 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
17197 | { | |
17198 | int pps_num; | |
17199 | int pps_idx; | |
17200 | ||
17201 | if (HAS_DDI(dev_priv)) | |
17202 | return; | |
17203 | /* | |
17204 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
17205 | * everywhere where registers can be write protected. | |
17206 | */ | |
17207 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
17208 | pps_num = 2; | |
17209 | else | |
17210 | pps_num = 1; | |
17211 | ||
17212 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
dc008bf0 | 17213 | u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); |
8090ba8c ID |
17214 | |
17215 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
dc008bf0 | 17216 | intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); |
8090ba8c ID |
17217 | } |
17218 | } | |
17219 | ||
44cb734c ID |
17220 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
17221 | { | |
cc3f90f0 | 17222 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
17223 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
17224 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
17225 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
17226 | else | |
17227 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
17228 | |
17229 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
17230 | } |
17231 | ||
c39055b0 | 17232 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 17233 | { |
4ef69c7a | 17234 | struct intel_encoder *encoder; |
cb0953d7 | 17235 | bool dpd_is_edp = false; |
79e53945 | 17236 | |
44cb734c ID |
17237 | intel_pps_init(dev_priv); |
17238 | ||
b81dddb9 | 17239 | if (!HAS_DISPLAY(dev_priv)) |
fc0c5a9d CW |
17240 | return; |
17241 | ||
aefaa1f4 MR |
17242 | if (IS_ROCKETLAKE(dev_priv)) { |
17243 | intel_ddi_init(dev_priv, PORT_A); | |
17244 | intel_ddi_init(dev_priv, PORT_B); | |
1d8ca002 VS |
17245 | intel_ddi_init(dev_priv, PORT_TC1); |
17246 | intel_ddi_init(dev_priv, PORT_TC2); | |
aefaa1f4 | 17247 | } else if (INTEL_GEN(dev_priv) >= 12) { |
55cd5048 MK |
17248 | intel_ddi_init(dev_priv, PORT_A); |
17249 | intel_ddi_init(dev_priv, PORT_B); | |
1d8ca002 VS |
17250 | intel_ddi_init(dev_priv, PORT_TC1); |
17251 | intel_ddi_init(dev_priv, PORT_TC2); | |
ba8a5cb2 | 17252 | intel_ddi_init(dev_priv, PORT_TC3); |
1d8ca002 VS |
17253 | intel_ddi_init(dev_priv, PORT_TC4); |
17254 | intel_ddi_init(dev_priv, PORT_TC5); | |
17255 | intel_ddi_init(dev_priv, PORT_TC6); | |
33365fec | 17256 | icl_dsi_init(dev_priv); |
24ea098b | 17257 | } else if (IS_JSL_EHL(dev_priv)) { |
759c9ab5 BP |
17258 | intel_ddi_init(dev_priv, PORT_A); |
17259 | intel_ddi_init(dev_priv, PORT_B); | |
17260 | intel_ddi_init(dev_priv, PORT_C); | |
719d2400 | 17261 | intel_ddi_init(dev_priv, PORT_D); |
759c9ab5 | 17262 | icl_dsi_init(dev_priv); |
55cd5048 | 17263 | } else if (IS_GEN(dev_priv, 11)) { |
00c92d92 PZ |
17264 | intel_ddi_init(dev_priv, PORT_A); |
17265 | intel_ddi_init(dev_priv, PORT_B); | |
17266 | intel_ddi_init(dev_priv, PORT_C); | |
17267 | intel_ddi_init(dev_priv, PORT_D); | |
17268 | intel_ddi_init(dev_priv, PORT_E); | |
3f2e9ed0 ID |
17269 | /* |
17270 | * On some ICL SKUs port F is not present. No strap bits for | |
17271 | * this, so rely on VBT. | |
2b34e562 | 17272 | * Work around broken VBTs on SKUs known to have no port F. |
3f2e9ed0 | 17273 | */ |
2b34e562 ID |
17274 | if (IS_ICL_WITH_PORT_F(dev_priv) && |
17275 | intel_bios_is_port_present(dev_priv, PORT_F)) | |
3f2e9ed0 ID |
17276 | intel_ddi_init(dev_priv, PORT_F); |
17277 | ||
bf4d57ff | 17278 | icl_dsi_init(dev_priv); |
00c92d92 | 17279 | } else if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
17280 | /* |
17281 | * FIXME: Broxton doesn't support port detection via the | |
17282 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
17283 | * detect the ports. | |
17284 | */ | |
c39055b0 ACO |
17285 | intel_ddi_init(dev_priv, PORT_A); |
17286 | intel_ddi_init(dev_priv, PORT_B); | |
17287 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 17288 | |
e518634b | 17289 | vlv_dsi_init(dev_priv); |
4f8036a2 | 17290 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
17291 | int found; |
17292 | ||
63cb4e64 JN |
17293 | if (intel_ddi_crt_present(dev_priv)) |
17294 | intel_crt_init(dev_priv); | |
17295 | ||
de31facd JB |
17296 | /* |
17297 | * Haswell uses DDI functions to detect digital outputs. | |
17298 | * On SKL pre-D0 the strap isn't connected, so we assume | |
17299 | * it's there. | |
17300 | */ | |
dc008bf0 | 17301 | found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 17302 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 17303 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 17304 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 | 17305 | |
9787e835 | 17306 | /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP |
0e72a5b5 | 17307 | * register */ |
dc008bf0 | 17308 | found = intel_de_read(dev_priv, SFUSE_STRAP); |
0e72a5b5 ED |
17309 | |
17310 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 17311 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 17312 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 17313 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 17314 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 17315 | intel_ddi_init(dev_priv, PORT_D); |
9787e835 RV |
17316 | if (found & SFUSE_STRAP_DDIF_DETECTED) |
17317 | intel_ddi_init(dev_priv, PORT_F); | |
2800e4c2 RV |
17318 | /* |
17319 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
17320 | */ | |
b976dc53 | 17321 | if (IS_GEN9_BC(dev_priv) && |
e9d49bb7 | 17322 | intel_bios_is_port_present(dev_priv, PORT_E)) |
c39055b0 | 17323 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 17324 | |
6e266956 | 17325 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 17326 | int found; |
63cb4e64 | 17327 | |
0fafa226 JN |
17328 | /* |
17329 | * intel_edp_init_connector() depends on this completing first, | |
17330 | * to prevent the registration of both eDP and LVDS and the | |
17331 | * incorrect sharing of the PPS. | |
17332 | */ | |
17333 | intel_lvds_init(dev_priv); | |
74d021ea | 17334 | intel_crt_init(dev_priv); |
63cb4e64 | 17335 | |
7b91bf7f | 17336 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
270b3042 | 17337 | |
a5916fd7 | 17338 | if (ilk_has_edp_a(dev_priv)) |
c39055b0 | 17339 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 17340 | |
dc008bf0 | 17341 | if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 17342 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 17343 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 17344 | if (!found) |
c39055b0 | 17345 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
dc008bf0 | 17346 | if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 17347 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
17348 | } |
17349 | ||
dc008bf0 | 17350 | if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 17351 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 17352 | |
dc008bf0 | 17353 | if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 17354 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 17355 | |
dc008bf0 | 17356 | if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) |
c39055b0 | 17357 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 17358 | |
dc008bf0 | 17359 | if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) |
c39055b0 | 17360 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 17361 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 17362 | bool has_edp, has_port; |
457c52d8 | 17363 | |
63cb4e64 JN |
17364 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) |
17365 | intel_crt_init(dev_priv); | |
17366 | ||
e17ac6db VS |
17367 | /* |
17368 | * The DP_DETECTED bit is the latched state of the DDC | |
17369 | * SDA pin at boot. However since eDP doesn't require DDC | |
17370 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
17371 | * eDP ports may have been muxed to an alternate function. | |
17372 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
17373 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
17374 | * detect eDP ports. | |
22f35042 VS |
17375 | * |
17376 | * Sadly the straps seem to be missing sometimes even for HDMI | |
17377 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
17378 | * and VBT for the presence of the port. Additionally we can't | |
17379 | * trust the port type the VBT declares as we've seen at least | |
17380 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 17381 | */ |
7b91bf7f | 17382 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
22f35042 | 17383 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
dc008bf0 | 17384 | if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) |
c39055b0 | 17385 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
dc008bf0 | 17386 | if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 17387 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 17388 | |
7b91bf7f | 17389 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
22f35042 | 17390 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
dc008bf0 | 17391 | if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) |
c39055b0 | 17392 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
dc008bf0 | 17393 | if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 17394 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 17395 | |
920a14b2 | 17396 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
17397 | /* |
17398 | * eDP not supported on port D, | |
17399 | * so no need to worry about it | |
17400 | */ | |
17401 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
dc008bf0 | 17402 | if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) |
c39055b0 | 17403 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
dc008bf0 | 17404 | if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 17405 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
17406 | } |
17407 | ||
e518634b | 17408 | vlv_dsi_init(dev_priv); |
63cb4e64 | 17409 | } else if (IS_PINEVIEW(dev_priv)) { |
0fafa226 | 17410 | intel_lvds_init(dev_priv); |
74d021ea | 17411 | intel_crt_init(dev_priv); |
63cb4e64 | 17412 | } else if (IS_GEN_RANGE(dev_priv, 3, 4)) { |
27185ae1 | 17413 | bool found = false; |
7d57382e | 17414 | |
9bedc7ed JN |
17415 | if (IS_MOBILE(dev_priv)) |
17416 | intel_lvds_init(dev_priv); | |
0fafa226 | 17417 | |
74d021ea | 17418 | intel_crt_init(dev_priv); |
63cb4e64 | 17419 | |
dc008bf0 | 17420 | if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { |
cd49f818 | 17421 | drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); |
c39055b0 | 17422 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 17423 | if (!found && IS_G4X(dev_priv)) { |
cd49f818 WK |
17424 | drm_dbg_kms(&dev_priv->drm, |
17425 | "probing HDMI on SDVOB\n"); | |
c39055b0 | 17426 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 17427 | } |
27185ae1 | 17428 | |
9beb5fea | 17429 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 17430 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 17431 | } |
13520b05 KH |
17432 | |
17433 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 17434 | |
dc008bf0 | 17435 | if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { |
cd49f818 | 17436 | drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); |
c39055b0 | 17437 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 17438 | } |
27185ae1 | 17439 | |
dc008bf0 | 17440 | if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 17441 | |
9beb5fea | 17442 | if (IS_G4X(dev_priv)) { |
cd49f818 WK |
17443 | drm_dbg_kms(&dev_priv->drm, |
17444 | "probing HDMI on SDVOC\n"); | |
c39055b0 | 17445 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 17446 | } |
9beb5fea | 17447 | if (IS_G4X(dev_priv)) |
c39055b0 | 17448 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 17449 | } |
27185ae1 | 17450 | |
dc008bf0 | 17451 | if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) |
c39055b0 | 17452 | intel_dp_init(dev_priv, DP_D, PORT_D); |
d6521463 JN |
17453 | |
17454 | if (SUPPORTS_TV(dev_priv)) | |
17455 | intel_tv_init(dev_priv); | |
63cb4e64 | 17456 | } else if (IS_GEN(dev_priv, 2)) { |
346073ce | 17457 | if (IS_I85X(dev_priv)) |
9bedc7ed | 17458 | intel_lvds_init(dev_priv); |
0fafa226 | 17459 | |
74d021ea | 17460 | intel_crt_init(dev_priv); |
c39055b0 | 17461 | intel_dvo_init(dev_priv); |
63cb4e64 | 17462 | } |
79e53945 | 17463 | |
c39055b0 | 17464 | intel_psr_init(dev_priv); |
7c8f8a70 | 17465 | |
c39055b0 | 17466 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
ed500bf6 VS |
17467 | encoder->base.possible_crtcs = |
17468 | intel_encoder_possible_crtcs(encoder); | |
4ef69c7a | 17469 | encoder->base.possible_clones = |
c08f995a | 17470 | intel_encoder_possible_clones(encoder); |
79e53945 | 17471 | } |
47356eb6 | 17472 | |
c39055b0 | 17473 | intel_init_pch_refclk(dev_priv); |
270b3042 | 17474 | |
c39055b0 | 17475 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
17476 | } |
17477 | ||
17478 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
17479 | { | |
17480 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 17481 | |
ef2d633e | 17482 | drm_framebuffer_cleanup(fb); |
8e7cb179 | 17483 | intel_frontbuffer_put(intel_fb->frontbuffer); |
70001cd2 | 17484 | |
79e53945 JB |
17485 | kfree(intel_fb); |
17486 | } | |
17487 | ||
17488 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 17489 | struct drm_file *file, |
79e53945 JB |
17490 | unsigned int *handle) |
17491 | { | |
a5ff7a45 | 17492 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
cd49f818 | 17493 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
79e53945 | 17494 | |
cc917ab4 | 17495 | if (obj->userptr.mm) { |
cd49f818 WK |
17496 | drm_dbg(&i915->drm, |
17497 | "attempting to use a userptr for a framebuffer, denied\n"); | |
cc917ab4 CW |
17498 | return -EINVAL; |
17499 | } | |
17500 | ||
05394f39 | 17501 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
17502 | } |
17503 | ||
86c98588 RV |
17504 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
17505 | struct drm_file *file, | |
17506 | unsigned flags, unsigned color, | |
17507 | struct drm_clip_rect *clips, | |
17508 | unsigned num_clips) | |
17509 | { | |
5a97bcc6 | 17510 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 17511 | |
5a97bcc6 | 17512 | i915_gem_object_flush_if_display(obj); |
8e7cb179 | 17513 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
86c98588 RV |
17514 | |
17515 | return 0; | |
17516 | } | |
17517 | ||
79e53945 JB |
17518 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
17519 | .destroy = intel_user_framebuffer_destroy, | |
17520 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 17521 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
17522 | }; |
17523 | ||
24dbf51a CW |
17524 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
17525 | struct drm_i915_gem_object *obj, | |
17526 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 17527 | { |
24dbf51a | 17528 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 17529 | struct drm_framebuffer *fb = &intel_fb->base; |
a88c40eb | 17530 | u32 max_stride; |
dd689287 | 17531 | unsigned int tiling, stride; |
24dbf51a | 17532 | int ret = -EINVAL; |
2e2adb05 | 17533 | int i; |
79e53945 | 17534 | |
8e7cb179 CW |
17535 | intel_fb->frontbuffer = intel_frontbuffer_get(obj); |
17536 | if (!intel_fb->frontbuffer) | |
17537 | return -ENOMEM; | |
17538 | ||
80f0b679 | 17539 | i915_gem_object_lock(obj, NULL); |
dd689287 CW |
17540 | tiling = i915_gem_object_get_tiling(obj); |
17541 | stride = i915_gem_object_get_stride(obj); | |
17542 | i915_gem_object_unlock(obj); | |
dd4916c5 | 17543 | |
2a80eada | 17544 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
17545 | /* |
17546 | * If there's a fence, enforce that | |
17547 | * the fb modifier and tiling mode match. | |
17548 | */ | |
17549 | if (tiling != I915_TILING_NONE && | |
17550 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
cd49f818 WK |
17551 | drm_dbg_kms(&dev_priv->drm, |
17552 | "tiling_mode doesn't match fb modifier\n"); | |
24dbf51a | 17553 | goto err; |
2a80eada DV |
17554 | } |
17555 | } else { | |
c2ff7370 | 17556 | if (tiling == I915_TILING_X) { |
2a80eada | 17557 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 17558 | } else if (tiling == I915_TILING_Y) { |
cd49f818 WK |
17559 | drm_dbg_kms(&dev_priv->drm, |
17560 | "No Y tiling for legacy addfb\n"); | |
24dbf51a | 17561 | goto err; |
2a80eada DV |
17562 | } |
17563 | } | |
17564 | ||
17e8fd11 VS |
17565 | if (!drm_any_plane_has_format(&dev_priv->drm, |
17566 | mode_cmd->pixel_format, | |
17567 | mode_cmd->modifier[0])) { | |
17568 | struct drm_format_name_buf format_name; | |
17569 | ||
cd49f818 WK |
17570 | drm_dbg_kms(&dev_priv->drm, |
17571 | "unsupported pixel format %s / modifier 0x%llx\n", | |
17572 | drm_get_format_name(mode_cmd->pixel_format, | |
17573 | &format_name), | |
17574 | mode_cmd->modifier[0]); | |
24dbf51a | 17575 | goto err; |
c16ed4be | 17576 | } |
57cd6508 | 17577 | |
c2ff7370 VS |
17578 | /* |
17579 | * gen2/3 display engine uses the fence if present, | |
17580 | * so the tiling mode must match the fb modifier exactly. | |
17581 | */ | |
c56b89f1 | 17582 | if (INTEL_GEN(dev_priv) < 4 && |
c2ff7370 | 17583 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
cd49f818 WK |
17584 | drm_dbg_kms(&dev_priv->drm, |
17585 | "tiling_mode must match fb modifier exactly on gen2/3\n"); | |
9aceb5c1 | 17586 | goto err; |
c2ff7370 VS |
17587 | } |
17588 | ||
a88c40eb VS |
17589 | max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, |
17590 | mode_cmd->modifier[0]); | |
17591 | if (mode_cmd->pitches[0] > max_stride) { | |
cd49f818 WK |
17592 | drm_dbg_kms(&dev_priv->drm, |
17593 | "%s pitch (%u) must be at most %d\n", | |
17594 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? | |
17595 | "tiled" : "linear", | |
17596 | mode_cmd->pitches[0], max_stride); | |
24dbf51a | 17597 | goto err; |
c16ed4be | 17598 | } |
5d7bd705 | 17599 | |
c2ff7370 VS |
17600 | /* |
17601 | * If there's a fence, enforce that | |
17602 | * the fb pitch and fence stride match. | |
17603 | */ | |
144cc143 | 17604 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
cd49f818 WK |
17605 | drm_dbg_kms(&dev_priv->drm, |
17606 | "pitch (%d) must match tiling stride (%d)\n", | |
17607 | mode_cmd->pitches[0], stride); | |
24dbf51a | 17608 | goto err; |
c16ed4be | 17609 | } |
5d7bd705 | 17610 | |
90f9a336 | 17611 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
5cf15dfc | 17612 | if (mode_cmd->offsets[0] != 0) { |
cd49f818 WK |
17613 | drm_dbg_kms(&dev_priv->drm, |
17614 | "plane 0 offset (0x%08x) must be 0\n", | |
17615 | mode_cmd->offsets[0]); | |
24dbf51a | 17616 | goto err; |
5cf15dfc | 17617 | } |
90f9a336 | 17618 | |
2e2adb05 | 17619 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 17620 | |
2e2adb05 VS |
17621 | for (i = 0; i < fb->format->num_planes; i++) { |
17622 | u32 stride_alignment; | |
17623 | ||
17624 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
cd49f818 WK |
17625 | drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", |
17626 | i); | |
37875d6b | 17627 | goto err; |
2e2adb05 VS |
17628 | } |
17629 | ||
17630 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
2e2adb05 | 17631 | if (fb->pitches[i] & (stride_alignment - 1)) { |
cd49f818 WK |
17632 | drm_dbg_kms(&dev_priv->drm, |
17633 | "plane %d pitch (%d) must be at least %u byte aligned\n", | |
17634 | i, fb->pitches[i], stride_alignment); | |
2e2adb05 VS |
17635 | goto err; |
17636 | } | |
d88c4afd | 17637 | |
71df86f0 ID |
17638 | if (is_gen12_ccs_plane(fb, i)) { |
17639 | int ccs_aux_stride = gen12_ccs_aux_stride(fb, i); | |
17640 | ||
17641 | if (fb->pitches[i] != ccs_aux_stride) { | |
cd49f818 WK |
17642 | drm_dbg_kms(&dev_priv->drm, |
17643 | "ccs aux plane %d pitch (%d) must be %d\n", | |
17644 | i, | |
17645 | fb->pitches[i], ccs_aux_stride); | |
71df86f0 ID |
17646 | goto err; |
17647 | } | |
17648 | } | |
17649 | ||
a268bcd7 DS |
17650 | fb->obj[i] = &obj->base; |
17651 | } | |
c7d73f6a | 17652 | |
2e2adb05 | 17653 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 17654 | if (ret) |
9aceb5c1 | 17655 | goto err; |
2d7a215f | 17656 | |
2e2adb05 | 17657 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 | 17658 | if (ret) { |
cd49f818 | 17659 | drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); |
24dbf51a | 17660 | goto err; |
79e53945 JB |
17661 | } |
17662 | ||
79e53945 | 17663 | return 0; |
24dbf51a CW |
17664 | |
17665 | err: | |
8e7cb179 | 17666 | intel_frontbuffer_put(intel_fb->frontbuffer); |
24dbf51a | 17667 | return ret; |
79e53945 JB |
17668 | } |
17669 | ||
79e53945 JB |
17670 | static struct drm_framebuffer * |
17671 | intel_user_framebuffer_create(struct drm_device *dev, | |
17672 | struct drm_file *filp, | |
1eb83451 | 17673 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 17674 | { |
dcb1394e | 17675 | struct drm_framebuffer *fb; |
05394f39 | 17676 | struct drm_i915_gem_object *obj; |
76dc3769 | 17677 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 17678 | |
03ac0642 CW |
17679 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
17680 | if (!obj) | |
cce13ff7 | 17681 | return ERR_PTR(-ENOENT); |
79e53945 | 17682 | |
24dbf51a | 17683 | fb = intel_framebuffer_create(obj, &mode_cmd); |
8e7cb179 | 17684 | i915_gem_object_put(obj); |
dcb1394e LW |
17685 | |
17686 | return fb; | |
79e53945 JB |
17687 | } |
17688 | ||
e995ca0b VS |
17689 | static enum drm_mode_status |
17690 | intel_mode_valid(struct drm_device *dev, | |
17691 | const struct drm_display_mode *mode) | |
17692 | { | |
ad77c537 VS |
17693 | struct drm_i915_private *dev_priv = to_i915(dev); |
17694 | int hdisplay_max, htotal_max; | |
17695 | int vdisplay_max, vtotal_max; | |
17696 | ||
e4dd27aa VS |
17697 | /* |
17698 | * Can't reject DBLSCAN here because Xorg ddxen can add piles | |
17699 | * of DBLSCAN modes to the output's mode list when they detect | |
17700 | * the scaling mode property on the connector. And they don't | |
17701 | * ask the kernel to validate those modes in any way until | |
17702 | * modeset time at which point the client gets a protocol error. | |
17703 | * So in order to not upset those clients we silently ignore the | |
17704 | * DBLSCAN flag on such connectors. For other connectors we will | |
17705 | * reject modes with the DBLSCAN flag in encoder->compute_config(). | |
17706 | * And we always reject DBLSCAN modes in connector->mode_valid() | |
17707 | * as we never want such modes on the connector's mode list. | |
17708 | */ | |
17709 | ||
e995ca0b VS |
17710 | if (mode->vscan > 1) |
17711 | return MODE_NO_VSCAN; | |
17712 | ||
e995ca0b VS |
17713 | if (mode->flags & DRM_MODE_FLAG_HSKEW) |
17714 | return MODE_H_ILLEGAL; | |
17715 | ||
17716 | if (mode->flags & (DRM_MODE_FLAG_CSYNC | | |
17717 | DRM_MODE_FLAG_NCSYNC | | |
17718 | DRM_MODE_FLAG_PCSYNC)) | |
17719 | return MODE_HSYNC; | |
17720 | ||
17721 | if (mode->flags & (DRM_MODE_FLAG_BCAST | | |
17722 | DRM_MODE_FLAG_PIXMUX | | |
17723 | DRM_MODE_FLAG_CLKDIV2)) | |
17724 | return MODE_BAD; | |
17725 | ||
2d20411e | 17726 | /* Transcoder timing limits */ |
12a97df0 MN |
17727 | if (INTEL_GEN(dev_priv) >= 11) { |
17728 | hdisplay_max = 16384; | |
17729 | vdisplay_max = 8192; | |
17730 | htotal_max = 16384; | |
17731 | vtotal_max = 8192; | |
17732 | } else if (INTEL_GEN(dev_priv) >= 9 || | |
17733 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
ad77c537 VS |
17734 | hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ |
17735 | vdisplay_max = 4096; | |
17736 | htotal_max = 8192; | |
17737 | vtotal_max = 8192; | |
17738 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
17739 | hdisplay_max = 4096; | |
17740 | vdisplay_max = 4096; | |
17741 | htotal_max = 8192; | |
17742 | vtotal_max = 8192; | |
17743 | } else { | |
17744 | hdisplay_max = 2048; | |
17745 | vdisplay_max = 2048; | |
17746 | htotal_max = 4096; | |
17747 | vtotal_max = 4096; | |
17748 | } | |
17749 | ||
17750 | if (mode->hdisplay > hdisplay_max || | |
17751 | mode->hsync_start > htotal_max || | |
17752 | mode->hsync_end > htotal_max || | |
17753 | mode->htotal > htotal_max) | |
17754 | return MODE_H_ILLEGAL; | |
17755 | ||
17756 | if (mode->vdisplay > vdisplay_max || | |
17757 | mode->vsync_start > vtotal_max || | |
17758 | mode->vsync_end > vtotal_max || | |
17759 | mode->vtotal > vtotal_max) | |
17760 | return MODE_V_ILLEGAL; | |
17761 | ||
8f4b1068 VS |
17762 | if (INTEL_GEN(dev_priv) >= 5) { |
17763 | if (mode->hdisplay < 64 || | |
17764 | mode->htotal - mode->hdisplay < 32) | |
17765 | return MODE_H_ILLEGAL; | |
17766 | ||
17767 | if (mode->vtotal - mode->vdisplay < 5) | |
17768 | return MODE_V_ILLEGAL; | |
17769 | } else { | |
17770 | if (mode->htotal - mode->hdisplay < 32) | |
17771 | return MODE_H_ILLEGAL; | |
17772 | ||
17773 | if (mode->vtotal - mode->vdisplay < 3) | |
17774 | return MODE_V_ILLEGAL; | |
17775 | } | |
17776 | ||
e995ca0b VS |
17777 | return MODE_OK; |
17778 | } | |
17779 | ||
2d20411e VS |
17780 | enum drm_mode_status |
17781 | intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, | |
17782 | const struct drm_display_mode *mode) | |
17783 | { | |
17784 | int plane_width_max, plane_height_max; | |
17785 | ||
17786 | /* | |
17787 | * intel_mode_valid() should be | |
17788 | * sufficient on older platforms. | |
17789 | */ | |
17790 | if (INTEL_GEN(dev_priv) < 9) | |
17791 | return MODE_OK; | |
17792 | ||
17793 | /* | |
17794 | * Most people will probably want a fullscreen | |
17795 | * plane so let's not advertize modes that are | |
17796 | * too big for that. | |
17797 | */ | |
17798 | if (INTEL_GEN(dev_priv) >= 11) { | |
17799 | plane_width_max = 5120; | |
17800 | plane_height_max = 4320; | |
17801 | } else { | |
17802 | plane_width_max = 5120; | |
17803 | plane_height_max = 4096; | |
17804 | } | |
17805 | ||
17806 | if (mode->hdisplay > plane_width_max) | |
17807 | return MODE_H_ILLEGAL; | |
17808 | ||
17809 | if (mode->vdisplay > plane_height_max) | |
17810 | return MODE_V_ILLEGAL; | |
17811 | ||
17812 | return MODE_OK; | |
17813 | } | |
17814 | ||
79e53945 | 17815 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 17816 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 17817 | .get_format_info = intel_get_format_info, |
0632fef6 | 17818 | .output_poll_changed = intel_fbdev_output_poll_changed, |
e995ca0b | 17819 | .mode_valid = intel_mode_valid, |
5ee67f1c MR |
17820 | .atomic_check = intel_atomic_check, |
17821 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
17822 | .atomic_state_alloc = intel_atomic_state_alloc, |
17823 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 17824 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
17825 | }; |
17826 | ||
88212941 ID |
17827 | /** |
17828 | * intel_init_display_hooks - initialize the display modesetting hooks | |
17829 | * @dev_priv: device private | |
17830 | */ | |
17831 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 17832 | { |
7ff89ca2 VS |
17833 | intel_init_cdclk_hooks(dev_priv); |
17834 | ||
c56b89f1 | 17835 | if (INTEL_GEN(dev_priv) >= 9) { |
1e98f88c | 17836 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
5724dbd1 | 17837 | dev_priv->display.get_initial_plane_config = |
f6df4d46 | 17838 | skl_get_initial_plane_config; |
1e98f88c LDM |
17839 | dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; |
17840 | dev_priv->display.crtc_enable = hsw_crtc_enable; | |
17841 | dev_priv->display.crtc_disable = hsw_crtc_disable; | |
88212941 | 17842 | } else if (HAS_DDI(dev_priv)) { |
1e98f88c | 17843 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
5724dbd1 | 17844 | dev_priv->display.get_initial_plane_config = |
81894b2f | 17845 | i9xx_get_initial_plane_config; |
797d0259 | 17846 | dev_priv->display.crtc_compute_clock = |
1e98f88c LDM |
17847 | hsw_crtc_compute_clock; |
17848 | dev_priv->display.crtc_enable = hsw_crtc_enable; | |
17849 | dev_priv->display.crtc_disable = hsw_crtc_disable; | |
88212941 | 17850 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9eae5e27 | 17851 | dev_priv->display.get_pipe_config = ilk_get_pipe_config; |
5724dbd1 | 17852 | dev_priv->display.get_initial_plane_config = |
81894b2f | 17853 | i9xx_get_initial_plane_config; |
3fb37703 | 17854 | dev_priv->display.crtc_compute_clock = |
9eae5e27 LDM |
17855 | ilk_crtc_compute_clock; |
17856 | dev_priv->display.crtc_enable = ilk_crtc_enable; | |
17857 | dev_priv->display.crtc_disable = ilk_crtc_disable; | |
65b3d6a9 | 17858 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 17859 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
17860 | dev_priv->display.get_initial_plane_config = |
17861 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
17862 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
17863 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
17864 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
17865 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
17866 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17867 | dev_priv->display.get_initial_plane_config = | |
17868 | i9xx_get_initial_plane_config; | |
17869 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
17870 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
17871 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
17872 | } else if (IS_G4X(dev_priv)) { |
17873 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17874 | dev_priv->display.get_initial_plane_config = | |
17875 | i9xx_get_initial_plane_config; | |
17876 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
17877 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17878 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
17879 | } else if (IS_PINEVIEW(dev_priv)) { |
17880 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17881 | dev_priv->display.get_initial_plane_config = | |
17882 | i9xx_get_initial_plane_config; | |
17883 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
17884 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17885 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
cf819eff | 17886 | } else if (!IS_GEN(dev_priv, 2)) { |
0e8ffe1b | 17887 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
17888 | dev_priv->display.get_initial_plane_config = |
17889 | i9xx_get_initial_plane_config; | |
d6dfee7a | 17890 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
17891 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
17892 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
17893 | } else { |
17894 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17895 | dev_priv->display.get_initial_plane_config = | |
17896 | i9xx_get_initial_plane_config; | |
17897 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
17898 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17899 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 17900 | } |
e70236a8 | 17901 | |
cf819eff | 17902 | if (IS_GEN(dev_priv, 5)) { |
9eae5e27 | 17903 | dev_priv->display.fdi_link_train = ilk_fdi_link_train; |
cf819eff | 17904 | } else if (IS_GEN(dev_priv, 6)) { |
3bb11b53 | 17905 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 17906 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
17907 | /* FIXME: detect B0+ stepping and use auto training */ |
17908 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
445e780b VS |
17909 | } |
17910 | ||
bd30ca2d | 17911 | if (INTEL_GEN(dev_priv) >= 9) |
0c841271 | 17912 | dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; |
27082493 | 17913 | else |
0c841271 | 17914 | dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; |
66d9cec8 | 17915 | |
e70236a8 JB |
17916 | } |
17917 | ||
6cd02e77 | 17918 | void intel_modeset_init_hw(struct drm_i915_private *i915) |
f817586c | 17919 | { |
1965de63 | 17920 | struct intel_cdclk_state *cdclk_state = |
28a30b45 | 17921 | to_intel_cdclk_state(i915->cdclk.obj.state); |
3cf43cdc VS |
17922 | struct intel_dbuf_state *dbuf_state = |
17923 | to_intel_dbuf_state(i915->dbuf.obj.state); | |
1965de63 | 17924 | |
6cd02e77 | 17925 | intel_update_cdclk(i915); |
0bb94e03 | 17926 | intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); |
1965de63 | 17927 | cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; |
3cf43cdc VS |
17928 | |
17929 | dbuf_state->enabled_slices = i915->dbuf.enabled_slices; | |
f817586c DV |
17930 | } |
17931 | ||
d1b2828a VS |
17932 | static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) |
17933 | { | |
17934 | struct drm_plane *plane; | |
af157b76 | 17935 | struct intel_crtc *crtc; |
d1b2828a | 17936 | |
af157b76 VS |
17937 | for_each_intel_crtc(state->dev, crtc) { |
17938 | struct intel_crtc_state *crtc_state; | |
d1b2828a | 17939 | |
af157b76 | 17940 | crtc_state = intel_atomic_get_crtc_state(state, crtc); |
d1b2828a VS |
17941 | if (IS_ERR(crtc_state)) |
17942 | return PTR_ERR(crtc_state); | |
af157b76 VS |
17943 | |
17944 | if (crtc_state->hw.active) { | |
17945 | /* | |
17946 | * Preserve the inherited flag to avoid | |
17947 | * taking the full modeset path. | |
17948 | */ | |
a227569d | 17949 | crtc_state->inherited = true; |
af157b76 | 17950 | } |
d1b2828a VS |
17951 | } |
17952 | ||
17953 | drm_for_each_plane(plane, state->dev) { | |
17954 | struct drm_plane_state *plane_state; | |
17955 | ||
17956 | plane_state = drm_atomic_get_plane_state(state, plane); | |
17957 | if (IS_ERR(plane_state)) | |
17958 | return PTR_ERR(plane_state); | |
17959 | } | |
17960 | ||
17961 | return 0; | |
17962 | } | |
17963 | ||
d93c0372 MR |
17964 | /* |
17965 | * Calculate what we think the watermarks should be for the state we've read | |
17966 | * out of the hardware and then immediately program those watermarks so that | |
17967 | * we ensure the hardware settings match our internal state. | |
17968 | * | |
17969 | * We can calculate what we think WM's should be by creating a duplicate of the | |
17970 | * current state (which was constructed during hardware readout) and running it | |
17971 | * through the atomic check code to calculate new watermark values in the | |
17972 | * state object. | |
17973 | */ | |
d1b2828a | 17974 | static void sanitize_watermarks(struct drm_i915_private *dev_priv) |
d93c0372 | 17975 | { |
d93c0372 | 17976 | struct drm_atomic_state *state; |
ccf010fb | 17977 | struct intel_atomic_state *intel_state; |
49743e1d ML |
17978 | struct intel_crtc *crtc; |
17979 | struct intel_crtc_state *crtc_state; | |
d93c0372 MR |
17980 | struct drm_modeset_acquire_ctx ctx; |
17981 | int ret; | |
17982 | int i; | |
17983 | ||
17984 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 17985 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
17986 | return; |
17987 | ||
d1b2828a | 17988 | state = drm_atomic_state_alloc(&dev_priv->drm); |
e57291c2 | 17989 | if (drm_WARN_ON(&dev_priv->drm, !state)) |
d1b2828a | 17990 | return; |
d93c0372 | 17991 | |
ccf010fb ML |
17992 | intel_state = to_intel_atomic_state(state); |
17993 | ||
d1b2828a VS |
17994 | drm_modeset_acquire_init(&ctx, 0); |
17995 | ||
17996 | retry: | |
17997 | state->acquire_ctx = &ctx; | |
17998 | ||
ed4a6a7c MR |
17999 | /* |
18000 | * Hardware readout is the only time we don't want to calculate | |
18001 | * intermediate watermarks (since we don't trust the current | |
18002 | * watermarks). | |
18003 | */ | |
b2ae318a | 18004 | if (!HAS_GMCH(dev_priv)) |
602ae835 | 18005 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 18006 | |
d1b2828a VS |
18007 | ret = sanitize_watermarks_add_affected(state); |
18008 | if (ret) | |
18009 | goto fail; | |
18010 | ||
18011 | ret = intel_atomic_check(&dev_priv->drm, state); | |
18012 | if (ret) | |
18013 | goto fail; | |
d93c0372 MR |
18014 | |
18015 | /* Write calculated watermark values back */ | |
49743e1d ML |
18016 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { |
18017 | crtc_state->wm.need_postvbl_update = true; | |
7a8fdb1f | 18018 | dev_priv->display.optimize_watermarks(intel_state, crtc); |
556fe36d | 18019 | |
49743e1d | 18020 | to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; |
d93c0372 MR |
18021 | } |
18022 | ||
0cd1262d | 18023 | fail: |
d1b2828a VS |
18024 | if (ret == -EDEADLK) { |
18025 | drm_atomic_state_clear(state); | |
18026 | drm_modeset_backoff(&ctx); | |
18027 | goto retry; | |
18028 | } | |
18029 | ||
18030 | /* | |
18031 | * If we fail here, it means that the hardware appears to be | |
18032 | * programmed in a way that shouldn't be possible, given our | |
18033 | * understanding of watermark requirements. This might mean a | |
18034 | * mistake in the hardware readout code or a mistake in the | |
18035 | * watermark calculations for a given platform. Raise a WARN | |
18036 | * so that this is noticeable. | |
18037 | * | |
18038 | * If this actually happens, we'll have to just leave the | |
18039 | * BIOS-programmed watermarks untouched and hope for the best. | |
18040 | */ | |
e57291c2 PB |
18041 | drm_WARN(&dev_priv->drm, ret, |
18042 | "Could not determine valid watermarks for inherited state\n"); | |
d1b2828a VS |
18043 | |
18044 | drm_atomic_state_put(state); | |
18045 | ||
d93c0372 MR |
18046 | drm_modeset_drop_locks(&ctx); |
18047 | drm_modeset_acquire_fini(&ctx); | |
18048 | } | |
18049 | ||
58ecd9d5 CW |
18050 | static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) |
18051 | { | |
cf819eff | 18052 | if (IS_GEN(dev_priv, 5)) { |
58ecd9d5 | 18053 | u32 fdi_pll_clk = |
dc008bf0 | 18054 | intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; |
58ecd9d5 CW |
18055 | |
18056 | dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; | |
cf819eff | 18057 | } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { |
58ecd9d5 CW |
18058 | dev_priv->fdi_pll_freq = 270000; |
18059 | } else { | |
18060 | return; | |
18061 | } | |
18062 | ||
cd49f818 | 18063 | drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); |
58ecd9d5 CW |
18064 | } |
18065 | ||
516a49cc AS |
18066 | static int intel_initial_commit(struct drm_device *dev) |
18067 | { | |
18068 | struct drm_atomic_state *state = NULL; | |
18069 | struct drm_modeset_acquire_ctx ctx; | |
3558cafc | 18070 | struct intel_crtc *crtc; |
516a49cc AS |
18071 | int ret = 0; |
18072 | ||
18073 | state = drm_atomic_state_alloc(dev); | |
18074 | if (!state) | |
18075 | return -ENOMEM; | |
18076 | ||
18077 | drm_modeset_acquire_init(&ctx, 0); | |
18078 | ||
18079 | retry: | |
18080 | state->acquire_ctx = &ctx; | |
18081 | ||
3558cafc ML |
18082 | for_each_intel_crtc(dev, crtc) { |
18083 | struct intel_crtc_state *crtc_state = | |
18084 | intel_atomic_get_crtc_state(state, crtc); | |
18085 | ||
516a49cc AS |
18086 | if (IS_ERR(crtc_state)) { |
18087 | ret = PTR_ERR(crtc_state); | |
18088 | goto out; | |
18089 | } | |
18090 | ||
1326a92c | 18091 | if (crtc_state->hw.active) { |
b671d6ef ID |
18092 | struct intel_encoder *encoder; |
18093 | ||
af157b76 VS |
18094 | /* |
18095 | * We've not yet detected sink capabilities | |
18096 | * (audio,infoframes,etc.) and thus we don't want to | |
18097 | * force a full state recomputation yet. We want that to | |
18098 | * happen only for the first real commit from userspace. | |
18099 | * So preserve the inherited flag for the time being. | |
18100 | */ | |
a227569d | 18101 | crtc_state->inherited = true; |
af157b76 | 18102 | |
3558cafc | 18103 | ret = drm_atomic_add_affected_planes(state, &crtc->base); |
516a49cc AS |
18104 | if (ret) |
18105 | goto out; | |
fa6af514 VS |
18106 | |
18107 | /* | |
18108 | * FIXME hack to force a LUT update to avoid the | |
18109 | * plane update forcing the pipe gamma on without | |
18110 | * having a proper LUT loaded. Remove once we | |
18111 | * have readout for pipe gamma enable. | |
18112 | */ | |
2225f3c6 | 18113 | crtc_state->uapi.color_mgmt_changed = true; |
a4277aa3 | 18114 | |
b671d6ef ID |
18115 | for_each_intel_encoder_mask(dev, encoder, |
18116 | crtc_state->uapi.encoder_mask) { | |
18117 | if (encoder->initial_fastset_check && | |
18118 | !encoder->initial_fastset_check(encoder, crtc_state)) { | |
18119 | ret = drm_atomic_add_affected_connectors(state, | |
18120 | &crtc->base); | |
18121 | if (ret) | |
18122 | goto out; | |
18123 | } | |
a4277aa3 | 18124 | } |
516a49cc AS |
18125 | } |
18126 | } | |
18127 | ||
18128 | ret = drm_atomic_commit(state); | |
18129 | ||
18130 | out: | |
18131 | if (ret == -EDEADLK) { | |
18132 | drm_atomic_state_clear(state); | |
18133 | drm_modeset_backoff(&ctx); | |
18134 | goto retry; | |
18135 | } | |
18136 | ||
18137 | drm_atomic_state_put(state); | |
18138 | ||
18139 | drm_modeset_drop_locks(&ctx); | |
18140 | drm_modeset_acquire_fini(&ctx); | |
18141 | ||
18142 | return ret; | |
18143 | } | |
18144 | ||
e1a3d989 JN |
18145 | static void intel_mode_config_init(struct drm_i915_private *i915) |
18146 | { | |
18147 | struct drm_mode_config *mode_config = &i915->drm.mode_config; | |
18148 | ||
18149 | drm_mode_config_init(&i915->drm); | |
0ef1905e | 18150 | INIT_LIST_HEAD(&i915->global_obj_list); |
e1a3d989 JN |
18151 | |
18152 | mode_config->min_width = 0; | |
18153 | mode_config->min_height = 0; | |
18154 | ||
18155 | mode_config->preferred_depth = 24; | |
18156 | mode_config->prefer_shadow = 1; | |
18157 | ||
18158 | mode_config->allow_fb_modifiers = true; | |
18159 | ||
18160 | mode_config->funcs = &intel_mode_funcs; | |
18161 | ||
55ea1cb1 K |
18162 | if (INTEL_GEN(i915) >= 9) |
18163 | mode_config->async_page_flip = true; | |
18164 | ||
e1a3d989 JN |
18165 | /* |
18166 | * Maximum framebuffer dimensions, chosen to match | |
18167 | * the maximum render engine surface size on gen4+. | |
18168 | */ | |
18169 | if (INTEL_GEN(i915) >= 7) { | |
18170 | mode_config->max_width = 16384; | |
18171 | mode_config->max_height = 16384; | |
18172 | } else if (INTEL_GEN(i915) >= 4) { | |
18173 | mode_config->max_width = 8192; | |
18174 | mode_config->max_height = 8192; | |
18175 | } else if (IS_GEN(i915, 3)) { | |
18176 | mode_config->max_width = 4096; | |
18177 | mode_config->max_height = 4096; | |
18178 | } else { | |
18179 | mode_config->max_width = 2048; | |
18180 | mode_config->max_height = 2048; | |
18181 | } | |
18182 | ||
18183 | if (IS_I845G(i915) || IS_I865G(i915)) { | |
18184 | mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; | |
18185 | mode_config->cursor_height = 1023; | |
5e9e0a3a VS |
18186 | } else if (IS_I830(i915) || IS_I85X(i915) || |
18187 | IS_I915G(i915) || IS_I915GM(i915)) { | |
e1a3d989 JN |
18188 | mode_config->cursor_width = 64; |
18189 | mode_config->cursor_height = 64; | |
18190 | } else { | |
18191 | mode_config->cursor_width = 256; | |
18192 | mode_config->cursor_height = 256; | |
18193 | } | |
18194 | } | |
18195 | ||
0ef1905e VS |
18196 | static void intel_mode_config_cleanup(struct drm_i915_private *i915) |
18197 | { | |
18198 | intel_atomic_global_obj_cleanup(i915); | |
18199 | drm_mode_config_cleanup(&i915->drm); | |
18200 | } | |
18201 | ||
1586f620 CW |
18202 | static void plane_config_fini(struct intel_initial_plane_config *plane_config) |
18203 | { | |
18204 | if (plane_config->fb) { | |
18205 | struct drm_framebuffer *fb = &plane_config->fb->base; | |
18206 | ||
18207 | /* We may only have the stub and not a full framebuffer */ | |
18208 | if (drm_framebuffer_read_refcount(fb)) | |
18209 | drm_framebuffer_put(fb); | |
18210 | else | |
18211 | kfree(fb); | |
18212 | } | |
9c4ce97d CW |
18213 | |
18214 | if (plane_config->vma) | |
18215 | i915_vma_put(plane_config->vma); | |
1586f620 CW |
18216 | } |
18217 | ||
80f286a5 JN |
18218 | /* part #1: call before irq install */ |
18219 | int intel_modeset_init_noirq(struct drm_i915_private *i915) | |
79e53945 | 18220 | { |
516a49cc | 18221 | int ret; |
79e53945 | 18222 | |
24d98a54 JN |
18223 | if (i915_inject_probe_failure(i915)) |
18224 | return -ENODEV; | |
18225 | ||
da27bd41 | 18226 | if (HAS_DISPLAY(i915)) { |
24d98a54 JN |
18227 | ret = drm_vblank_init(&i915->drm, |
18228 | INTEL_NUM_PIPES(i915)); | |
18229 | if (ret) | |
18230 | return ret; | |
18231 | } | |
18232 | ||
18233 | intel_bios_init(i915); | |
18234 | ||
18235 | ret = intel_vga_register(i915); | |
18236 | if (ret) | |
18237 | goto cleanup_bios; | |
18238 | ||
18239 | /* FIXME: completely on the wrong abstraction layer */ | |
18240 | intel_power_domains_init_hw(i915, false); | |
18241 | ||
18242 | intel_csr_ucode_init(i915); | |
18243 | ||
6cd02e77 JN |
18244 | i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); |
18245 | i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | | |
18246 | WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); | |
757fffcf | 18247 | |
6cd02e77 | 18248 | intel_mode_config_init(i915); |
79e53945 | 18249 | |
28a30b45 VS |
18250 | ret = intel_cdclk_init(i915); |
18251 | if (ret) | |
24d98a54 | 18252 | goto cleanup_vga_client_pw_domain_csr; |
28a30b45 | 18253 | |
3cf43cdc VS |
18254 | ret = intel_dbuf_init(i915); |
18255 | if (ret) | |
24d98a54 | 18256 | goto cleanup_vga_client_pw_domain_csr; |
3cf43cdc | 18257 | |
6cd02e77 | 18258 | ret = intel_bw_init(i915); |
c457d9cf | 18259 | if (ret) |
24d98a54 | 18260 | goto cleanup_vga_client_pw_domain_csr; |
c457d9cf | 18261 | |
6cd02e77 JN |
18262 | init_llist_head(&i915->atomic_helper.free_list); |
18263 | INIT_WORK(&i915->atomic_helper.free_work, | |
ba318c61 | 18264 | intel_atomic_helper_free_state_worker); |
eb955eee | 18265 | |
6cd02e77 | 18266 | intel_init_quirks(i915); |
b690e96c | 18267 | |
6cd02e77 | 18268 | intel_fbc_init(i915); |
acde44b5 | 18269 | |
80f286a5 | 18270 | return 0; |
24d98a54 JN |
18271 | |
18272 | cleanup_vga_client_pw_domain_csr: | |
18273 | intel_csr_ucode_fini(i915); | |
18274 | intel_power_domains_driver_remove(i915); | |
18275 | intel_vga_unregister(i915); | |
18276 | cleanup_bios: | |
18277 | intel_bios_driver_remove(i915); | |
18278 | ||
18279 | return ret; | |
80f286a5 JN |
18280 | } |
18281 | ||
a5f2488f JN |
18282 | /* part #2: call after irq install, but before gem init */ |
18283 | int intel_modeset_init_nogem(struct drm_i915_private *i915) | |
80f286a5 JN |
18284 | { |
18285 | struct drm_device *dev = &i915->drm; | |
18286 | enum pipe pipe; | |
18287 | struct intel_crtc *crtc; | |
18288 | int ret; | |
18289 | ||
6cd02e77 | 18290 | intel_init_pm(i915); |
1fa61106 | 18291 | |
6cd02e77 | 18292 | intel_panel_sanitize_ssc(i915); |
69f92f67 | 18293 | |
9bfcf194 JN |
18294 | intel_gmbus_setup(i915); |
18295 | ||
cd49f818 WK |
18296 | drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", |
18297 | INTEL_NUM_PIPES(i915), | |
18298 | INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); | |
79e53945 | 18299 | |
da27bd41 | 18300 | if (HAS_DISPLAY(i915)) { |
6cd02e77 JN |
18301 | for_each_pipe(i915, pipe) { |
18302 | ret = intel_crtc_init(i915, pipe); | |
ef404bc6 | 18303 | if (ret) { |
0ef1905e | 18304 | intel_mode_config_cleanup(i915); |
ef404bc6 JN |
18305 | return ret; |
18306 | } | |
b079bd17 | 18307 | } |
79e53945 JB |
18308 | } |
18309 | ||
6875eb3f | 18310 | intel_plane_possible_crtcs_init(i915); |
e72f9fbf | 18311 | intel_shared_dpll_init(dev); |
6cd02e77 | 18312 | intel_update_fdi_pll_freq(i915); |
ee7b9f93 | 18313 | |
6cd02e77 JN |
18314 | intel_update_czclk(i915); |
18315 | intel_modeset_init_hw(i915); | |
5be6e334 | 18316 | |
6cd02e77 | 18317 | intel_hdcp_component_init(i915); |
9055aac7 | 18318 | |
6cd02e77 JN |
18319 | if (i915->max_cdclk_freq == 0) |
18320 | intel_update_max_cdclk(i915); | |
b2045352 | 18321 | |
ddff9a60 MR |
18322 | /* |
18323 | * If the platform has HTI, we need to find out whether it has reserved | |
18324 | * any display resources before we create our display outputs. | |
18325 | */ | |
18326 | if (INTEL_INFO(i915)->display.has_hti) | |
18327 | i915->hti_state = intel_de_read(i915, HDPORT_STATE); | |
18328 | ||
9cce37f4 | 18329 | /* Just disable it once at startup */ |
4fb87831 | 18330 | intel_vga_disable(i915); |
6cd02e77 | 18331 | intel_setup_outputs(i915); |
11be49eb | 18332 | |
6e9f798d | 18333 | drm_modeset_lock_all(dev); |
aecd36b8 | 18334 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 18335 | drm_modeset_unlock_all(dev); |
46f297fb | 18336 | |
d3fcc808 | 18337 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
18338 | struct intel_initial_plane_config plane_config = {}; |
18339 | ||
46f297fb JB |
18340 | if (!crtc->active) |
18341 | continue; | |
18342 | ||
46f297fb | 18343 | /* |
46f297fb JB |
18344 | * Note that reserving the BIOS fb up front prevents us |
18345 | * from stuffing other stolen allocations like the ring | |
18346 | * on top. This prevents some ugliness at boot time, and | |
18347 | * can even allow for smooth boot transitions if the BIOS | |
18348 | * fb is large enough for the active pipe configuration. | |
18349 | */ | |
6cd02e77 | 18350 | i915->display.get_initial_plane_config(crtc, &plane_config); |
eeebeac5 ML |
18351 | |
18352 | /* | |
18353 | * If the fb is shared between multiple heads, we'll | |
18354 | * just get the first one. | |
18355 | */ | |
18356 | intel_find_initial_plane_obj(crtc, &plane_config); | |
1586f620 CW |
18357 | |
18358 | plane_config_fini(&plane_config); | |
46f297fb | 18359 | } |
d93c0372 MR |
18360 | |
18361 | /* | |
18362 | * Make sure hardware watermarks really match the state we read out. | |
18363 | * Note that we need to do this after reconstructing the BIOS fb's | |
18364 | * since the watermark calculation done here will use pstate->fb. | |
18365 | */ | |
6cd02e77 | 18366 | if (!HAS_GMCH(i915)) |
d1b2828a | 18367 | sanitize_watermarks(i915); |
b079bd17 | 18368 | |
516a49cc AS |
18369 | /* |
18370 | * Force all active planes to recompute their states. So that on | |
18371 | * mode_setcrtc after probe, all the intel_plane_state variables | |
18372 | * are already calculated and there is no assert_plane warnings | |
18373 | * during bootup. | |
18374 | */ | |
18375 | ret = intel_initial_commit(dev); | |
18376 | if (ret) | |
cd49f818 | 18377 | drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n"); |
516a49cc | 18378 | |
b079bd17 | 18379 | return 0; |
2c7111db CW |
18380 | } |
18381 | ||
a5f2488f JN |
18382 | /* part #3: call after gem init */ |
18383 | int intel_modeset_init(struct drm_i915_private *i915) | |
18384 | { | |
18385 | int ret; | |
18386 | ||
da27bd41 | 18387 | if (!HAS_DISPLAY(i915)) |
a5f2488f JN |
18388 | return 0; |
18389 | ||
71c8415d JN |
18390 | intel_overlay_setup(i915); |
18391 | ||
a5f2488f JN |
18392 | ret = intel_fbdev_init(&i915->drm); |
18393 | if (ret) | |
18394 | return ret; | |
18395 | ||
18396 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
18397 | intel_hpd_init(i915); | |
4c8d4651 | 18398 | intel_hpd_poll_disable(i915); |
a5f2488f JN |
18399 | |
18400 | intel_init_ipc(i915); | |
18401 | ||
a5f2488f JN |
18402 | return 0; |
18403 | } | |
18404 | ||
2ee0da16 VS |
18405 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
18406 | { | |
d5fb43cb | 18407 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
2ee0da16 VS |
18408 | /* 640x480@60Hz, ~25175 kHz */ |
18409 | struct dpll clock = { | |
18410 | .m1 = 18, | |
18411 | .m2 = 7, | |
18412 | .p1 = 13, | |
18413 | .p2 = 4, | |
18414 | .n = 2, | |
18415 | }; | |
18416 | u32 dpll, fp; | |
18417 | int i; | |
18418 | ||
e57291c2 PB |
18419 | drm_WARN_ON(&dev_priv->drm, |
18420 | i9xx_calc_dpll_params(48000, &clock) != 25154); | |
2ee0da16 | 18421 | |
cd49f818 WK |
18422 | drm_dbg_kms(&dev_priv->drm, |
18423 | "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
18424 | pipe_name(pipe), clock.vco, clock.dot); | |
2ee0da16 VS |
18425 | |
18426 | fp = i9xx_dpll_compute_fp(&clock); | |
171d1562 | 18427 | dpll = DPLL_DVO_2X_MODE | |
2ee0da16 VS |
18428 | DPLL_VGA_MODE_DIS | |
18429 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
18430 | PLL_P2_DIVIDE_BY_4 | | |
18431 | PLL_REF_INPUT_DREFCLK | | |
18432 | DPLL_VCO_ENABLE; | |
18433 | ||
dc008bf0 JN |
18434 | intel_de_write(dev_priv, FP0(pipe), fp); |
18435 | intel_de_write(dev_priv, FP1(pipe), fp); | |
2ee0da16 | 18436 | |
dc008bf0 JN |
18437 | intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); |
18438 | intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
18439 | intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
18440 | intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
18441 | intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
18442 | intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
18443 | intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
2ee0da16 VS |
18444 | |
18445 | /* | |
18446 | * Apparently we need to have VGA mode enabled prior to changing | |
18447 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
18448 | * dividers, even though the register value does change. | |
18449 | */ | |
dc008bf0 JN |
18450 | intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); |
18451 | intel_de_write(dev_priv, DPLL(pipe), dpll); | |
2ee0da16 VS |
18452 | |
18453 | /* Wait for the clocks to stabilize. */ | |
dc008bf0 | 18454 | intel_de_posting_read(dev_priv, DPLL(pipe)); |
2ee0da16 VS |
18455 | udelay(150); |
18456 | ||
18457 | /* The pixel multiplier can only be updated once the | |
18458 | * DPLL is enabled and the clocks are stable. | |
18459 | * | |
18460 | * So write it again. | |
18461 | */ | |
dc008bf0 | 18462 | intel_de_write(dev_priv, DPLL(pipe), dpll); |
2ee0da16 VS |
18463 | |
18464 | /* We do this three times for luck */ | |
18465 | for (i = 0; i < 3 ; i++) { | |
dc008bf0 JN |
18466 | intel_de_write(dev_priv, DPLL(pipe), dpll); |
18467 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
2ee0da16 VS |
18468 | udelay(150); /* wait for warmup */ |
18469 | } | |
18470 | ||
dc008bf0 JN |
18471 | intel_de_write(dev_priv, PIPECONF(pipe), |
18472 | PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
18473 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
d5fb43cb VS |
18474 | |
18475 | intel_wait_for_pipe_scanline_moving(crtc); | |
2ee0da16 VS |
18476 | } |
18477 | ||
18478 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
18479 | { | |
8fedd64d VS |
18480 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
18481 | ||
cd49f818 WK |
18482 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", |
18483 | pipe_name(pipe)); | |
2ee0da16 | 18484 | |
e57291c2 PB |
18485 | drm_WARN_ON(&dev_priv->drm, |
18486 | intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & | |
18487 | DISPLAY_PLANE_ENABLE); | |
18488 | drm_WARN_ON(&dev_priv->drm, | |
18489 | intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & | |
18490 | DISPLAY_PLANE_ENABLE); | |
18491 | drm_WARN_ON(&dev_priv->drm, | |
18492 | intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & | |
18493 | DISPLAY_PLANE_ENABLE); | |
18494 | drm_WARN_ON(&dev_priv->drm, | |
18495 | intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); | |
18496 | drm_WARN_ON(&dev_priv->drm, | |
18497 | intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE); | |
2ee0da16 | 18498 | |
dc008bf0 JN |
18499 | intel_de_write(dev_priv, PIPECONF(pipe), 0); |
18500 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
2ee0da16 | 18501 | |
8fedd64d | 18502 | intel_wait_for_pipe_scanline_stopped(crtc); |
2ee0da16 | 18503 | |
dc008bf0 JN |
18504 | intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); |
18505 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
2ee0da16 VS |
18506 | } |
18507 | ||
b1e01595 VS |
18508 | static void |
18509 | intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) | |
18510 | { | |
18511 | struct intel_crtc *crtc; | |
fa555837 | 18512 | |
b1e01595 VS |
18513 | if (INTEL_GEN(dev_priv) >= 4) |
18514 | return; | |
fa555837 | 18515 | |
b1e01595 VS |
18516 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
18517 | struct intel_plane *plane = | |
18518 | to_intel_plane(crtc->base.primary); | |
62358aa4 VS |
18519 | struct intel_crtc *plane_crtc; |
18520 | enum pipe pipe; | |
b1e01595 | 18521 | |
62358aa4 VS |
18522 | if (!plane->get_hw_state(plane, &pipe)) |
18523 | continue; | |
18524 | ||
18525 | if (pipe == crtc->pipe) | |
b1e01595 VS |
18526 | continue; |
18527 | ||
cd49f818 WK |
18528 | drm_dbg_kms(&dev_priv->drm, |
18529 | "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", | |
18530 | plane->base.base.id, plane->base.name); | |
62358aa4 VS |
18531 | |
18532 | plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
18533 | intel_plane_disable_noatomic(plane_crtc, plane); | |
b1e01595 | 18534 | } |
fa555837 DV |
18535 | } |
18536 | ||
02e93c35 VS |
18537 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
18538 | { | |
18539 | struct drm_device *dev = crtc->base.dev; | |
18540 | struct intel_encoder *encoder; | |
18541 | ||
18542 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
18543 | return true; | |
18544 | ||
18545 | return false; | |
18546 | } | |
18547 | ||
496b0fc3 ML |
18548 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
18549 | { | |
18550 | struct drm_device *dev = encoder->base.dev; | |
18551 | struct intel_connector *connector; | |
18552 | ||
18553 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
18554 | return connector; | |
18555 | ||
18556 | return NULL; | |
18557 | } | |
18558 | ||
a168f5b3 | 18559 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
ecf837d9 | 18560 | enum pipe pch_transcoder) |
a168f5b3 VS |
18561 | { |
18562 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
ecf837d9 | 18563 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); |
a168f5b3 VS |
18564 | } |
18565 | ||
cc7a4cff | 18566 | static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state) |
24929352 | 18567 | { |
cc7a4cff VS |
18568 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
18569 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1b52ad46 | 18570 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
24929352 | 18571 | |
cc7a4cff VS |
18572 | if (INTEL_GEN(dev_priv) >= 9 || |
18573 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
18574 | i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); | |
18575 | u32 val; | |
18576 | ||
18577 | if (transcoder_is_dsi(cpu_transcoder)) | |
18578 | return; | |
18579 | ||
dc008bf0 | 18580 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18581 | val &= ~HSW_FRAME_START_DELAY_MASK; |
18582 | val |= HSW_FRAME_START_DELAY(0); | |
dc008bf0 | 18583 | intel_de_write(dev_priv, reg, val); |
cc7a4cff | 18584 | } else { |
4d1de975 | 18585 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
cc7a4cff VS |
18586 | u32 val; |
18587 | ||
dc008bf0 | 18588 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18589 | val &= ~PIPECONF_FRAME_START_DELAY_MASK; |
18590 | val |= PIPECONF_FRAME_START_DELAY(0); | |
dc008bf0 | 18591 | intel_de_write(dev_priv, reg, val); |
cc7a4cff VS |
18592 | } |
18593 | ||
18594 | if (!crtc_state->has_pch_encoder) | |
18595 | return; | |
18596 | ||
18597 | if (HAS_PCH_IBX(dev_priv)) { | |
18598 | i915_reg_t reg = PCH_TRANSCONF(crtc->pipe); | |
18599 | u32 val; | |
18600 | ||
dc008bf0 | 18601 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18602 | val &= ~TRANS_FRAME_START_DELAY_MASK; |
18603 | val |= TRANS_FRAME_START_DELAY(0); | |
dc008bf0 | 18604 | intel_de_write(dev_priv, reg, val); |
cc7a4cff | 18605 | } else { |
7df49149 VS |
18606 | enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); |
18607 | i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder); | |
cc7a4cff | 18608 | u32 val; |
4d1de975 | 18609 | |
dc008bf0 | 18610 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18611 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
18612 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 18613 | intel_de_write(dev_priv, reg, val); |
4d1de975 | 18614 | } |
cc7a4cff VS |
18615 | } |
18616 | ||
18617 | static void intel_sanitize_crtc(struct intel_crtc *crtc, | |
18618 | struct drm_modeset_acquire_ctx *ctx) | |
18619 | { | |
18620 | struct drm_device *dev = crtc->base.dev; | |
18621 | struct drm_i915_private *dev_priv = to_i915(dev); | |
18622 | struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); | |
24929352 | 18623 | |
1326a92c | 18624 | if (crtc_state->hw.active) { |
f9cd7b88 VS |
18625 | struct intel_plane *plane; |
18626 | ||
cc7a4cff VS |
18627 | /* Clear any frame start delays used for debugging left by the BIOS */ |
18628 | intel_sanitize_frame_start_delay(crtc_state); | |
18629 | ||
f9cd7b88 VS |
18630 | /* Disable everything but the primary plane */ |
18631 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
b1e01595 VS |
18632 | const struct intel_plane_state *plane_state = |
18633 | to_intel_plane_state(plane->base.state); | |
f9cd7b88 | 18634 | |
f90a85e7 | 18635 | if (plane_state->uapi.visible && |
b1e01595 VS |
18636 | plane->base.type != DRM_PLANE_TYPE_PRIMARY) |
18637 | intel_plane_disable_noatomic(crtc, plane); | |
f9cd7b88 | 18638 | } |
c0550305 MR |
18639 | |
18640 | /* | |
18641 | * Disable any background color set by the BIOS, but enable the | |
18642 | * gamma and CSC to match how we program our planes. | |
18643 | */ | |
18644 | if (INTEL_GEN(dev_priv) >= 9) | |
dc008bf0 JN |
18645 | intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe), |
18646 | SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE); | |
9625604c | 18647 | } |
d3eaf884 | 18648 | |
24929352 DV |
18649 | /* Adjust the state of the output pipe according to whether we |
18650 | * have active connectors/encoders. */ | |
1326a92c | 18651 | if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc)) |
56273062 | 18652 | intel_crtc_disable_noatomic(crtc, ctx); |
24929352 | 18653 | |
1326a92c | 18654 | if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { |
4cc31489 DV |
18655 | /* |
18656 | * We start out with underrun reporting disabled to avoid races. | |
18657 | * For correct bookkeeping mark this on active crtcs. | |
18658 | * | |
c5ab3bc0 DV |
18659 | * Also on gmch platforms we dont have any hardware bits to |
18660 | * disable the underrun reporting. Which means we need to start | |
18661 | * out with underrun reporting disabled also on inactive pipes, | |
18662 | * since otherwise we'll complain about the garbage we read when | |
18663 | * e.g. coming up after runtime pm. | |
18664 | * | |
4cc31489 DV |
18665 | * No protection against concurrent access is required - at |
18666 | * worst a fifo underrun happens which also sets this to false. | |
18667 | */ | |
18668 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
18669 | /* |
18670 | * We track the PCH trancoder underrun reporting state | |
18671 | * within the crtc. With crtc for pipe A housing the underrun | |
18672 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
18673 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
18674 | * and marking underrun reporting as disabled for the non-existing | |
18675 | * PCH transcoders B and C would prevent enabling the south | |
18676 | * error interrupt (see cpt_can_enable_serr_int()). | |
18677 | */ | |
ecf837d9 | 18678 | if (has_pch_trancoder(dev_priv, crtc->pipe)) |
a168f5b3 | 18679 | crtc->pch_fifo_underrun_disabled = true; |
4cc31489 | 18680 | } |
24929352 DV |
18681 | } |
18682 | ||
7bed8adc VS |
18683 | static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) |
18684 | { | |
2225f3c6 | 18685 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7bed8adc VS |
18686 | |
18687 | /* | |
18688 | * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram | |
18689 | * the hardware when a high res displays plugged in. DPLL P | |
18690 | * divider is zero, and the pipe timings are bonkers. We'll | |
18691 | * try to disable everything in that case. | |
18692 | * | |
18693 | * FIXME would be nice to be able to sanitize this state | |
18694 | * without several WARNs, but for now let's take the easy | |
18695 | * road. | |
18696 | */ | |
18697 | return IS_GEN(dev_priv, 6) && | |
1326a92c | 18698 | crtc_state->hw.active && |
7bed8adc VS |
18699 | crtc_state->shared_dpll && |
18700 | crtc_state->port_clock == 0; | |
18701 | } | |
18702 | ||
24929352 DV |
18703 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
18704 | { | |
70332ac5 | 18705 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24929352 | 18706 | struct intel_connector *connector; |
7bed8adc VS |
18707 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
18708 | struct intel_crtc_state *crtc_state = crtc ? | |
18709 | to_intel_crtc_state(crtc->base.state) : NULL; | |
24929352 DV |
18710 | |
18711 | /* We need to check both for a crtc link (meaning that the | |
18712 | * encoder is active and trying to read from a pipe) and the | |
18713 | * pipe itself being active. */ | |
7bed8adc | 18714 | bool has_active_crtc = crtc_state && |
1326a92c | 18715 | crtc_state->hw.active; |
7bed8adc VS |
18716 | |
18717 | if (crtc_state && has_bogus_dpll_config(crtc_state)) { | |
cd49f818 WK |
18718 | drm_dbg_kms(&dev_priv->drm, |
18719 | "BIOS has misprogrammed the hardware. Disabling pipe %c\n", | |
18720 | pipe_name(crtc->pipe)); | |
7bed8adc VS |
18721 | has_active_crtc = false; |
18722 | } | |
24929352 | 18723 | |
496b0fc3 ML |
18724 | connector = intel_encoder_find_connector(encoder); |
18725 | if (connector && !has_active_crtc) { | |
cd49f818 WK |
18726 | drm_dbg_kms(&dev_priv->drm, |
18727 | "[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
18728 | encoder->base.base.id, | |
18729 | encoder->base.name); | |
24929352 DV |
18730 | |
18731 | /* Connector is active, but has no active pipe. This is | |
18732 | * fallout from our resume register restoring. Disable | |
18733 | * the encoder manually again. */ | |
7bed8adc VS |
18734 | if (crtc_state) { |
18735 | struct drm_encoder *best_encoder; | |
fd6bbda9 | 18736 | |
cd49f818 WK |
18737 | drm_dbg_kms(&dev_priv->drm, |
18738 | "[ENCODER:%d:%s] manually disabled\n", | |
18739 | encoder->base.base.id, | |
18740 | encoder->base.name); | |
7bed8adc VS |
18741 | |
18742 | /* avoid oopsing in case the hooks consult best_encoder */ | |
18743 | best_encoder = connector->base.state->best_encoder; | |
18744 | connector->base.state->best_encoder = &encoder->base; | |
18745 | ||
ede9771d | 18746 | /* FIXME NULL atomic state passed! */ |
c84c6fe3 | 18747 | if (encoder->disable) |
ede9771d | 18748 | encoder->disable(NULL, encoder, crtc_state, |
7bed8adc | 18749 | connector->base.state); |
a62d1497 | 18750 | if (encoder->post_disable) |
ede9771d | 18751 | encoder->post_disable(NULL, encoder, crtc_state, |
7bed8adc VS |
18752 | connector->base.state); |
18753 | ||
18754 | connector->base.state->best_encoder = best_encoder; | |
24929352 | 18755 | } |
7f1950fb | 18756 | encoder->base.crtc = NULL; |
24929352 DV |
18757 | |
18758 | /* Inconsistent output/port/pipe state happens presumably due to | |
18759 | * a bug in one of the get_hw_state functions. Or someplace else | |
18760 | * in our code, like the register restore mess on resume. Clamp | |
18761 | * things to off as a safer default. */ | |
fd6bbda9 ML |
18762 | |
18763 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
18764 | connector->base.encoder = NULL; | |
24929352 | 18765 | } |
d6cae4aa ML |
18766 | |
18767 | /* notify opregion of the sanitized encoder state */ | |
18768 | intel_opregion_notify_encoder(encoder, connector && has_active_crtc); | |
70332ac5 ID |
18769 | |
18770 | if (INTEL_GEN(dev_priv) >= 11) | |
18771 | icl_sanitize_encoder_pll_mapping(encoder); | |
24929352 DV |
18772 | } |
18773 | ||
f9cd7b88 | 18774 | /* FIXME read out full plane state for all planes */ |
62358aa4 | 18775 | static void readout_plane_state(struct drm_i915_private *dev_priv) |
d032ffa0 | 18776 | { |
b1e01595 | 18777 | struct intel_plane *plane; |
62358aa4 | 18778 | struct intel_crtc *crtc; |
d032ffa0 | 18779 | |
62358aa4 | 18780 | for_each_intel_plane(&dev_priv->drm, plane) { |
b1e01595 VS |
18781 | struct intel_plane_state *plane_state = |
18782 | to_intel_plane_state(plane->base.state); | |
62358aa4 VS |
18783 | struct intel_crtc_state *crtc_state; |
18784 | enum pipe pipe = PIPE_A; | |
eade6c89 VS |
18785 | bool visible; |
18786 | ||
18787 | visible = plane->get_hw_state(plane, &pipe); | |
b26d3ea3 | 18788 | |
62358aa4 VS |
18789 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
18790 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
18791 | ||
b1e01595 | 18792 | intel_set_plane_visible(crtc_state, plane_state, visible); |
7a4a2a46 | 18793 | |
cd49f818 WK |
18794 | drm_dbg_kms(&dev_priv->drm, |
18795 | "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", | |
18796 | plane->base.base.id, plane->base.name, | |
18797 | enableddisabled(visible), pipe_name(pipe)); | |
b1e01595 | 18798 | } |
62358aa4 VS |
18799 | |
18800 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
18801 | struct intel_crtc_state *crtc_state = | |
18802 | to_intel_crtc_state(crtc->base.state); | |
18803 | ||
18804 | fixup_active_planes(crtc_state); | |
18805 | } | |
98ec7739 VS |
18806 | } |
18807 | ||
30e984df | 18808 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 18809 | { |
fac5e23e | 18810 | struct drm_i915_private *dev_priv = to_i915(dev); |
28a30b45 VS |
18811 | struct intel_cdclk_state *cdclk_state = |
18812 | to_intel_cdclk_state(dev_priv->cdclk.obj.state); | |
3cf43cdc VS |
18813 | struct intel_dbuf_state *dbuf_state = |
18814 | to_intel_dbuf_state(dev_priv->dbuf.obj.state); | |
24929352 | 18815 | enum pipe pipe; |
24929352 DV |
18816 | struct intel_crtc *crtc; |
18817 | struct intel_encoder *encoder; | |
18818 | struct intel_connector *connector; | |
f9e905ca | 18819 | struct drm_connector_list_iter conn_iter; |
0c2d5512 | 18820 | u8 active_pipes = 0; |
24929352 | 18821 | |
d3fcc808 | 18822 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
18823 | struct intel_crtc_state *crtc_state = |
18824 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 18825 | |
2225f3c6 | 18826 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); |
58d124ea | 18827 | intel_crtc_free_hw_state(crtc_state); |
979e94c1 | 18828 | intel_crtc_state_reset(crtc_state, crtc); |
24929352 | 18829 | |
291106cb VS |
18830 | intel_crtc_get_pipe_config(crtc_state); |
18831 | ||
18832 | crtc_state->hw.enable = crtc_state->hw.active; | |
565602d7 | 18833 | |
1326a92c ML |
18834 | crtc->base.enabled = crtc_state->hw.enable; |
18835 | crtc->active = crtc_state->hw.active; | |
565602d7 | 18836 | |
1326a92c | 18837 | if (crtc_state->hw.active) |
0c2d5512 | 18838 | active_pipes |= BIT(crtc->pipe); |
565602d7 | 18839 | |
cd49f818 WK |
18840 | drm_dbg_kms(&dev_priv->drm, |
18841 | "[CRTC:%d:%s] hw state readout: %s\n", | |
18842 | crtc->base.base.id, crtc->base.name, | |
18843 | enableddisabled(crtc_state->hw.active)); | |
24929352 DV |
18844 | } |
18845 | ||
3cf43cdc VS |
18846 | dev_priv->active_pipes = cdclk_state->active_pipes = |
18847 | dbuf_state->active_pipes = active_pipes; | |
0c2d5512 | 18848 | |
62358aa4 VS |
18849 | readout_plane_state(dev_priv); |
18850 | ||
830b2cdc | 18851 | intel_dpll_readout_hw_state(dev_priv); |
5358901f | 18852 | |
b2784e15 | 18853 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
18854 | pipe = 0; |
18855 | ||
18856 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
18857 | struct intel_crtc_state *crtc_state; |
18858 | ||
98187836 | 18859 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 18860 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 18861 | |
045ac3b5 | 18862 | encoder->base.crtc = &crtc->base; |
65c1ed30 | 18863 | intel_encoder_get_config(encoder, crtc_state); |
f9e76a6e ID |
18864 | if (encoder->sync_state) |
18865 | encoder->sync_state(encoder, crtc_state); | |
24929352 DV |
18866 | } else { |
18867 | encoder->base.crtc = NULL; | |
18868 | } | |
18869 | ||
cd49f818 WK |
18870 | drm_dbg_kms(&dev_priv->drm, |
18871 | "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", | |
18872 | encoder->base.base.id, encoder->base.name, | |
18873 | enableddisabled(encoder->base.crtc), | |
18874 | pipe_name(pipe)); | |
24929352 DV |
18875 | } |
18876 | ||
f9e905ca DV |
18877 | drm_connector_list_iter_begin(dev, &conn_iter); |
18878 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 | 18879 | if (connector->get_hw_state(connector)) { |
de3b67af VS |
18880 | struct intel_crtc_state *crtc_state; |
18881 | struct intel_crtc *crtc; | |
18882 | ||
24929352 | 18883 | connector->base.dpms = DRM_MODE_DPMS_ON; |
2aa974c9 | 18884 | |
fa7edcd2 | 18885 | encoder = intel_attached_encoder(connector); |
2aa974c9 ML |
18886 | connector->base.encoder = &encoder->base; |
18887 | ||
de3b67af VS |
18888 | crtc = to_intel_crtc(encoder->base.crtc); |
18889 | crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; | |
18890 | ||
1326a92c | 18891 | if (crtc_state && crtc_state->hw.active) { |
2aa974c9 ML |
18892 | /* |
18893 | * This has to be done during hardware readout | |
18894 | * because anything calling .crtc_disable may | |
18895 | * rely on the connector_mask being accurate. | |
18896 | */ | |
2225f3c6 | 18897 | crtc_state->uapi.connector_mask |= |
40560e26 | 18898 | drm_connector_mask(&connector->base); |
2225f3c6 | 18899 | crtc_state->uapi.encoder_mask |= |
40560e26 | 18900 | drm_encoder_mask(&encoder->base); |
2aa974c9 | 18901 | } |
24929352 DV |
18902 | } else { |
18903 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
18904 | connector->base.encoder = NULL; | |
18905 | } | |
cd49f818 WK |
18906 | drm_dbg_kms(&dev_priv->drm, |
18907 | "[CONNECTOR:%d:%s] hw state readout: %s\n", | |
18908 | connector->base.base.id, connector->base.name, | |
18909 | enableddisabled(connector->base.encoder)); | |
24929352 | 18910 | } |
f9e905ca | 18911 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
18912 | |
18913 | for_each_intel_crtc(dev, crtc) { | |
c457d9cf VS |
18914 | struct intel_bw_state *bw_state = |
18915 | to_intel_bw_state(dev_priv->bw_obj.state); | |
a8cd6da0 VS |
18916 | struct intel_crtc_state *crtc_state = |
18917 | to_intel_crtc_state(crtc->base.state); | |
c457d9cf | 18918 | struct intel_plane *plane; |
d305e061 | 18919 | int min_cdclk = 0; |
aca1ebf4 | 18920 | |
1326a92c | 18921 | if (crtc_state->hw.active) { |
7f4c6284 VS |
18922 | /* |
18923 | * The initial mode needs to be set in order to keep | |
18924 | * the atomic core happy. It wants a valid mode if the | |
18925 | * crtc's enabled, so we do the above call. | |
18926 | * | |
7800fb69 DV |
18927 | * But we don't set all the derived state fully, hence |
18928 | * set a flag to indicate that a full recalculation is | |
18929 | * needed on the next commit. | |
7f4c6284 | 18930 | */ |
a227569d | 18931 | crtc_state->inherited = true; |
9eca6832 | 18932 | |
99325429 | 18933 | intel_crtc_update_active_timings(crtc_state); |
58d124ea ML |
18934 | |
18935 | intel_crtc_copy_hw_to_uapi_state(crtc_state); | |
7f4c6284 | 18936 | } |
e3b247da | 18937 | |
c457d9cf VS |
18938 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { |
18939 | const struct intel_plane_state *plane_state = | |
18940 | to_intel_plane_state(plane->base.state); | |
18941 | ||
18942 | /* | |
18943 | * FIXME don't have the fb yet, so can't | |
18944 | * use intel_plane_data_rate() :( | |
18945 | */ | |
f90a85e7 | 18946 | if (plane_state->uapi.visible) |
c457d9cf VS |
18947 | crtc_state->data_rate[plane->id] = |
18948 | 4 * crtc_state->pixel_rate; | |
bb6ae9e6 VS |
18949 | /* |
18950 | * FIXME don't have the fb yet, so can't | |
18951 | * use plane->min_cdclk() :( | |
18952 | */ | |
f90a85e7 | 18953 | if (plane_state->uapi.visible && plane->min_cdclk) { |
bb6ae9e6 VS |
18954 | if (crtc_state->double_wide || |
18955 | INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
18956 | crtc_state->min_cdclk[plane->id] = | |
18957 | DIV_ROUND_UP(crtc_state->pixel_rate, 2); | |
18958 | else | |
18959 | crtc_state->min_cdclk[plane->id] = | |
18960 | crtc_state->pixel_rate; | |
18961 | } | |
cd49f818 WK |
18962 | drm_dbg_kms(&dev_priv->drm, |
18963 | "[PLANE:%d:%s] min_cdclk %d kHz\n", | |
18964 | plane->base.base.id, plane->base.name, | |
18965 | crtc_state->min_cdclk[plane->id]); | |
bb6ae9e6 VS |
18966 | } |
18967 | ||
1326a92c | 18968 | if (crtc_state->hw.active) { |
bb6ae9e6 | 18969 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
e57291c2 | 18970 | if (drm_WARN_ON(dev, min_cdclk < 0)) |
bb6ae9e6 | 18971 | min_cdclk = 0; |
c457d9cf VS |
18972 | } |
18973 | ||
1965de63 VS |
18974 | cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; |
18975 | cdclk_state->min_voltage_level[crtc->pipe] = | |
bb6ae9e6 VS |
18976 | crtc_state->min_voltage_level; |
18977 | ||
c457d9cf VS |
18978 | intel_bw_crtc_update(bw_state, crtc_state); |
18979 | ||
a8cd6da0 | 18980 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 18981 | } |
30e984df DV |
18982 | } |
18983 | ||
62b69566 ACO |
18984 | static void |
18985 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
18986 | { | |
18987 | struct intel_encoder *encoder; | |
18988 | ||
18989 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
52528055 | 18990 | struct intel_crtc_state *crtc_state; |
62b69566 ACO |
18991 | |
18992 | if (!encoder->get_power_domains) | |
18993 | continue; | |
18994 | ||
52528055 | 18995 | /* |
b79ebe74 ID |
18996 | * MST-primary and inactive encoders don't have a crtc state |
18997 | * and neither of these require any power domain references. | |
52528055 | 18998 | */ |
b79ebe74 ID |
18999 | if (!encoder->base.crtc) |
19000 | continue; | |
52528055 | 19001 | |
b79ebe74 | 19002 | crtc_state = to_intel_crtc_state(encoder->base.crtc->state); |
3a52fb7e | 19003 | encoder->get_power_domains(encoder, crtc_state); |
62b69566 ACO |
19004 | } |
19005 | } | |
19006 | ||
df49ec82 RV |
19007 | static void intel_early_display_was(struct drm_i915_private *dev_priv) |
19008 | { | |
1e1a139d MR |
19009 | /* |
19010 | * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl | |
19011 | * Also known as Wa_14010480278. | |
19012 | */ | |
19013 | if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv)) | |
dc008bf0 JN |
19014 | intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, |
19015 | intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); | |
df49ec82 RV |
19016 | |
19017 | if (IS_HASWELL(dev_priv)) { | |
19018 | /* | |
19019 | * WaRsPkgCStateDisplayPMReq:hsw | |
19020 | * System hang if this isn't done before disabling all planes! | |
19021 | */ | |
dc008bf0 JN |
19022 | intel_de_write(dev_priv, CHICKEN_PAR1_1, |
19023 | intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
df49ec82 | 19024 | } |
562ad8ad VS |
19025 | |
19026 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { | |
19027 | /* Display WA #1142:kbl,cfl,cml */ | |
19028 | intel_de_rmw(dev_priv, CHICKEN_PAR1_1, | |
19029 | KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); | |
19030 | intel_de_rmw(dev_priv, CHICKEN_MISC_2, | |
19031 | KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, | |
19032 | KBL_ARB_FILL_SPARE_14); | |
19033 | } | |
df49ec82 RV |
19034 | } |
19035 | ||
3aefb67f VS |
19036 | static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, |
19037 | enum port port, i915_reg_t hdmi_reg) | |
19038 | { | |
dc008bf0 | 19039 | u32 val = intel_de_read(dev_priv, hdmi_reg); |
3aefb67f VS |
19040 | |
19041 | if (val & SDVO_ENABLE || | |
19042 | (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) | |
19043 | return; | |
19044 | ||
cd49f818 WK |
19045 | drm_dbg_kms(&dev_priv->drm, |
19046 | "Sanitizing transcoder select for HDMI %c\n", | |
19047 | port_name(port)); | |
3aefb67f VS |
19048 | |
19049 | val &= ~SDVO_PIPE_SEL_MASK; | |
19050 | val |= SDVO_PIPE_SEL(PIPE_A); | |
19051 | ||
dc008bf0 | 19052 | intel_de_write(dev_priv, hdmi_reg, val); |
3aefb67f VS |
19053 | } |
19054 | ||
19055 | static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, | |
19056 | enum port port, i915_reg_t dp_reg) | |
19057 | { | |
dc008bf0 | 19058 | u32 val = intel_de_read(dev_priv, dp_reg); |
3aefb67f VS |
19059 | |
19060 | if (val & DP_PORT_EN || | |
19061 | (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) | |
19062 | return; | |
19063 | ||
cd49f818 WK |
19064 | drm_dbg_kms(&dev_priv->drm, |
19065 | "Sanitizing transcoder select for DP %c\n", | |
19066 | port_name(port)); | |
3aefb67f VS |
19067 | |
19068 | val &= ~DP_PIPE_SEL_MASK; | |
19069 | val |= DP_PIPE_SEL(PIPE_A); | |
19070 | ||
dc008bf0 | 19071 | intel_de_write(dev_priv, dp_reg, val); |
3aefb67f VS |
19072 | } |
19073 | ||
19074 | static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) | |
19075 | { | |
19076 | /* | |
19077 | * The BIOS may select transcoder B on some of the PCH | |
19078 | * ports even it doesn't enable the port. This would trip | |
19079 | * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). | |
19080 | * Sanitize the transcoder select bits to prevent that. We | |
19081 | * assume that the BIOS never actually enabled the port, | |
19082 | * because if it did we'd actually have to toggle the port | |
19083 | * on and back off to make the transcoder A select stick | |
19084 | * (see. intel_dp_link_down(), intel_disable_hdmi(), | |
19085 | * intel_disable_sdvo()). | |
19086 | */ | |
19087 | ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); | |
19088 | ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); | |
19089 | ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); | |
19090 | ||
19091 | /* PCH SDVOB multiplex with HDMIB */ | |
19092 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); | |
19093 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); | |
19094 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); | |
19095 | } | |
19096 | ||
043e9bda ML |
19097 | /* Scan out the current hw modeset state, |
19098 | * and sanitizes it to the current state | |
19099 | */ | |
19100 | static void | |
aecd36b8 VS |
19101 | intel_modeset_setup_hw_state(struct drm_device *dev, |
19102 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 19103 | { |
fac5e23e | 19104 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 19105 | struct intel_encoder *encoder; |
0e6e0be4 CW |
19106 | struct intel_crtc *crtc; |
19107 | intel_wakeref_t wakeref; | |
30e984df | 19108 | |
0e6e0be4 | 19109 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
2cd9a689 | 19110 | |
df49ec82 | 19111 | intel_early_display_was(dev_priv); |
30e984df | 19112 | intel_modeset_readout_hw_state(dev); |
24929352 DV |
19113 | |
19114 | /* HW state is read out, now we need to sanitize this mess. */ | |
32691b58 ID |
19115 | |
19116 | /* Sanitize the TypeC port mode upfront, encoders depend on this */ | |
19117 | for_each_intel_encoder(dev, encoder) { | |
d8fe2ab6 MR |
19118 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
19119 | ||
32691b58 ID |
19120 | /* We need to sanitize only the MST primary port. */ |
19121 | if (encoder->type != INTEL_OUTPUT_DP_MST && | |
d8fe2ab6 | 19122 | intel_phy_is_tc(dev_priv, phy)) |
b7d02c3a | 19123 | intel_tc_port_sanitize(enc_to_dig_port(encoder)); |
32691b58 ID |
19124 | } |
19125 | ||
62b69566 | 19126 | get_encoder_power_domains(dev_priv); |
3aefb67f VS |
19127 | |
19128 | if (HAS_PCH_IBX(dev_priv)) | |
19129 | ibx_sanitize_pch_ports(dev_priv); | |
62b69566 | 19130 | |
68bc30de VS |
19131 | /* |
19132 | * intel_sanitize_plane_mapping() may need to do vblank | |
19133 | * waits, so we need vblank interrupts restored beforehand. | |
19134 | */ | |
19135 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
777bf6d7 VS |
19136 | struct intel_crtc_state *crtc_state = |
19137 | to_intel_crtc_state(crtc->base.state); | |
32db0b65 | 19138 | |
68bc30de | 19139 | drm_crtc_vblank_reset(&crtc->base); |
b1e01595 | 19140 | |
1326a92c | 19141 | if (crtc_state->hw.active) |
32db0b65 | 19142 | intel_crtc_vblank_on(crtc_state); |
24929352 DV |
19143 | } |
19144 | ||
68bc30de | 19145 | intel_sanitize_plane_mapping(dev_priv); |
e2af48c6 | 19146 | |
68bc30de VS |
19147 | for_each_intel_encoder(dev, encoder) |
19148 | intel_sanitize_encoder(encoder); | |
19149 | ||
19150 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
777bf6d7 | 19151 | struct intel_crtc_state *crtc_state = |
7b0bcead | 19152 | to_intel_crtc_state(crtc->base.state); |
777bf6d7 | 19153 | |
aecd36b8 | 19154 | intel_sanitize_crtc(crtc, ctx); |
10d75f54 | 19155 | intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); |
24929352 | 19156 | } |
9a935856 | 19157 | |
d29b2f9d ACO |
19158 | intel_modeset_update_connector_atomic_state(dev); |
19159 | ||
830b2cdc | 19160 | intel_dpll_sanitize_state(dev_priv); |
35c95375 | 19161 | |
04548cba | 19162 | if (IS_G4X(dev_priv)) { |
cd1d3ee9 | 19163 | g4x_wm_get_hw_state(dev_priv); |
04548cba VS |
19164 | g4x_wm_sanitize(dev_priv); |
19165 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
cd1d3ee9 | 19166 | vlv_wm_get_hw_state(dev_priv); |
602ae835 | 19167 | vlv_wm_sanitize(dev_priv); |
a029fa4d | 19168 | } else if (INTEL_GEN(dev_priv) >= 9) { |
cd1d3ee9 | 19169 | skl_wm_get_hw_state(dev_priv); |
602ae835 | 19170 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cd1d3ee9 | 19171 | ilk_wm_get_hw_state(dev_priv); |
602ae835 | 19172 | } |
292b990e ML |
19173 | |
19174 | for_each_intel_crtc(dev, crtc) { | |
777bf6d7 VS |
19175 | struct intel_crtc_state *crtc_state = |
19176 | to_intel_crtc_state(crtc->base.state); | |
d8fc70b7 | 19177 | u64 put_domains; |
292b990e | 19178 | |
afe0c21b | 19179 | put_domains = modeset_get_crtc_power_domains(crtc_state); |
e57291c2 | 19180 | if (drm_WARN_ON(dev, put_domains)) |
292b990e ML |
19181 | modeset_put_power_domains(dev_priv, put_domains); |
19182 | } | |
2cd9a689 | 19183 | |
0e6e0be4 | 19184 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); |
043e9bda | 19185 | } |
7d0bc1ea | 19186 | |
043e9bda ML |
19187 | void intel_display_resume(struct drm_device *dev) |
19188 | { | |
e2c8b870 ML |
19189 | struct drm_i915_private *dev_priv = to_i915(dev); |
19190 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
19191 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 19192 | int ret; |
f30da187 | 19193 | |
e2c8b870 | 19194 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
19195 | if (state) |
19196 | state->acquire_ctx = &ctx; | |
043e9bda | 19197 | |
e2c8b870 | 19198 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 19199 | |
73974893 ML |
19200 | while (1) { |
19201 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
19202 | if (ret != -EDEADLK) | |
19203 | break; | |
043e9bda | 19204 | |
e2c8b870 | 19205 | drm_modeset_backoff(&ctx); |
e2c8b870 | 19206 | } |
043e9bda | 19207 | |
73974893 | 19208 | if (!ret) |
581e49fe | 19209 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 19210 | |
2503a0fe | 19211 | intel_enable_ipc(dev_priv); |
e2c8b870 ML |
19212 | drm_modeset_drop_locks(&ctx); |
19213 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 19214 | |
0853695c | 19215 | if (ret) |
cd49f818 WK |
19216 | drm_err(&dev_priv->drm, |
19217 | "Restoring old state failed with %i\n", ret); | |
3c5e37f1 CW |
19218 | if (state) |
19219 | drm_atomic_state_put(state); | |
2c7111db CW |
19220 | } |
19221 | ||
9980c3c1 | 19222 | static void intel_hpd_poll_fini(struct drm_i915_private *i915) |
886c6b86 MN |
19223 | { |
19224 | struct intel_connector *connector; | |
19225 | struct drm_connector_list_iter conn_iter; | |
19226 | ||
448aa911 | 19227 | /* Kill all the work that may have been queued by hpd. */ |
9980c3c1 | 19228 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); |
886c6b86 MN |
19229 | for_each_intel_connector_iter(connector, &conn_iter) { |
19230 | if (connector->modeset_retry_work.func) | |
19231 | cancel_work_sync(&connector->modeset_retry_work); | |
d3dacc70 R |
19232 | if (connector->hdcp.shim) { |
19233 | cancel_delayed_work_sync(&connector->hdcp.check_work); | |
19234 | cancel_work_sync(&connector->hdcp.prop_work); | |
ee5e5e7a | 19235 | } |
886c6b86 MN |
19236 | } |
19237 | drm_connector_list_iter_end(&conn_iter); | |
19238 | } | |
19239 | ||
93a0ed6c | 19240 | /* part #1: call before irq uninstall */ |
9980c3c1 | 19241 | void intel_modeset_driver_remove(struct drm_i915_private *i915) |
79e53945 | 19242 | { |
9980c3c1 JN |
19243 | flush_workqueue(i915->flip_wq); |
19244 | flush_workqueue(i915->modeset_wq); | |
8bcf9f70 | 19245 | |
9980c3c1 | 19246 | flush_work(&i915->atomic_helper.free_work); |
e57291c2 | 19247 | drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); |
93a0ed6c | 19248 | } |
eb955eee | 19249 | |
93a0ed6c JN |
19250 | /* part #2: call after irq uninstall */ |
19251 | void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) | |
19252 | { | |
fd0c0642 DV |
19253 | /* |
19254 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
19255 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
19256 | */ | |
9980c3c1 | 19257 | intel_hpd_poll_fini(i915); |
fd0c0642 | 19258 | |
d5746bf2 JRS |
19259 | /* |
19260 | * MST topology needs to be suspended so we don't have any calls to | |
19261 | * fbdev after it's finalized. MST will be destroyed later as part of | |
19262 | * drm_mode_config_cleanup() | |
19263 | */ | |
19264 | intel_dp_mst_suspend(i915); | |
19265 | ||
4f256d82 | 19266 | /* poll work can call into fbdev, hence clean that up afterwards */ |
9980c3c1 | 19267 | intel_fbdev_fini(i915); |
4f256d82 | 19268 | |
723bfd70 JB |
19269 | intel_unregister_dsm_handler(); |
19270 | ||
9980c3c1 | 19271 | intel_fbc_global_disable(i915); |
69341a5e | 19272 | |
1630fe75 CW |
19273 | /* flush any delayed tasks or pending work */ |
19274 | flush_scheduled_work(); | |
19275 | ||
9980c3c1 | 19276 | intel_hdcp_component_fini(i915); |
9055aac7 | 19277 | |
0ef1905e | 19278 | intel_mode_config_cleanup(i915); |
4d7bb011 | 19279 | |
9980c3c1 | 19280 | intel_overlay_cleanup(i915); |
ae48434c | 19281 | |
9980c3c1 | 19282 | intel_gmbus_teardown(i915); |
757fffcf | 19283 | |
9980c3c1 JN |
19284 | destroy_workqueue(i915->flip_wq); |
19285 | destroy_workqueue(i915->modeset_wq); | |
acde44b5 | 19286 | |
9980c3c1 | 19287 | intel_fbc_cleanup_cfb(i915); |
79e53945 JB |
19288 | } |
19289 | ||
eb4612d8 JN |
19290 | /* part #3: call after gem init */ |
19291 | void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) | |
19292 | { | |
19293 | intel_csr_ucode_fini(i915); | |
19294 | ||
19295 | intel_power_domains_driver_remove(i915); | |
19296 | ||
19297 | intel_vga_unregister(i915); | |
19298 | ||
19299 | intel_bios_driver_remove(i915); | |
19300 | } | |
19301 | ||
98a2f411 CW |
19302 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
19303 | ||
c4a1d9e4 | 19304 | struct intel_display_error_state { |
ff57f1b0 PZ |
19305 | |
19306 | u32 power_well_driver; | |
19307 | ||
c4a1d9e4 CW |
19308 | struct intel_cursor_error_state { |
19309 | u32 control; | |
19310 | u32 position; | |
19311 | u32 base; | |
19312 | u32 size; | |
52331309 | 19313 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
19314 | |
19315 | struct intel_pipe_error_state { | |
ddf9c536 | 19316 | bool power_domain_on; |
c4a1d9e4 | 19317 | u32 source; |
f301b1e1 | 19318 | u32 stat; |
52331309 | 19319 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
19320 | |
19321 | struct intel_plane_error_state { | |
19322 | u32 control; | |
19323 | u32 stride; | |
19324 | u32 size; | |
19325 | u32 pos; | |
19326 | u32 addr; | |
19327 | u32 surface; | |
19328 | u32 tile_offset; | |
52331309 | 19329 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
19330 | |
19331 | struct intel_transcoder_error_state { | |
062de72b | 19332 | bool available; |
ddf9c536 | 19333 | bool power_domain_on; |
63b66e5b CW |
19334 | enum transcoder cpu_transcoder; |
19335 | ||
19336 | u32 conf; | |
19337 | ||
19338 | u32 htotal; | |
19339 | u32 hblank; | |
19340 | u32 hsync; | |
19341 | u32 vtotal; | |
19342 | u32 vblank; | |
19343 | u32 vsync; | |
f1f1d4fa | 19344 | } transcoder[5]; |
c4a1d9e4 CW |
19345 | }; |
19346 | ||
19347 | struct intel_display_error_state * | |
c033666a | 19348 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 19349 | { |
c4a1d9e4 | 19350 | struct intel_display_error_state *error; |
63b66e5b CW |
19351 | int transcoders[] = { |
19352 | TRANSCODER_A, | |
19353 | TRANSCODER_B, | |
19354 | TRANSCODER_C, | |
f1f1d4fa | 19355 | TRANSCODER_D, |
63b66e5b CW |
19356 | TRANSCODER_EDP, |
19357 | }; | |
c4a1d9e4 CW |
19358 | int i; |
19359 | ||
062de72b LDM |
19360 | BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder)); |
19361 | ||
da27bd41 | 19362 | if (!HAS_DISPLAY(dev_priv)) |
63b66e5b CW |
19363 | return NULL; |
19364 | ||
9d1cb914 | 19365 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
19366 | if (error == NULL) |
19367 | return NULL; | |
19368 | ||
c033666a | 19369 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
dc008bf0 JN |
19370 | error->power_well_driver = intel_de_read(dev_priv, |
19371 | HSW_PWR_WELL_CTL2); | |
ff57f1b0 | 19372 | |
055e393f | 19373 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 19374 | error->pipe[i].power_domain_on = |
f458ebbc DV |
19375 | __intel_display_power_is_enabled(dev_priv, |
19376 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 19377 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
19378 | continue; |
19379 | ||
dc008bf0 JN |
19380 | error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i)); |
19381 | error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i)); | |
19382 | error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i)); | |
c4a1d9e4 | 19383 | |
dc008bf0 JN |
19384 | error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)); |
19385 | error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i)); | |
c033666a | 19386 | if (INTEL_GEN(dev_priv) <= 3) { |
dc008bf0 JN |
19387 | error->plane[i].size = intel_de_read(dev_priv, |
19388 | DSPSIZE(i)); | |
19389 | error->plane[i].pos = intel_de_read(dev_priv, | |
19390 | DSPPOS(i)); | |
80ca378b | 19391 | } |
c033666a | 19392 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
dc008bf0 JN |
19393 | error->plane[i].addr = intel_de_read(dev_priv, |
19394 | DSPADDR(i)); | |
c033666a | 19395 | if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
19396 | error->plane[i].surface = intel_de_read(dev_priv, |
19397 | DSPSURF(i)); | |
19398 | error->plane[i].tile_offset = intel_de_read(dev_priv, | |
19399 | DSPTILEOFF(i)); | |
c4a1d9e4 CW |
19400 | } |
19401 | ||
dc008bf0 | 19402 | error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)); |
f301b1e1 | 19403 | |
b2ae318a | 19404 | if (HAS_GMCH(dev_priv)) |
dc008bf0 JN |
19405 | error->pipe[i].stat = intel_de_read(dev_priv, |
19406 | PIPESTAT(i)); | |
63b66e5b CW |
19407 | } |
19408 | ||
062de72b | 19409 | for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { |
63b66e5b CW |
19410 | enum transcoder cpu_transcoder = transcoders[i]; |
19411 | ||
10cf8e75 | 19412 | if (!HAS_TRANSCODER(dev_priv, cpu_transcoder)) |
062de72b LDM |
19413 | continue; |
19414 | ||
19415 | error->transcoder[i].available = true; | |
ddf9c536 | 19416 | error->transcoder[i].power_domain_on = |
f458ebbc | 19417 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 19418 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 19419 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
19420 | continue; |
19421 | ||
63b66e5b CW |
19422 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
19423 | ||
dc008bf0 JN |
19424 | error->transcoder[i].conf = intel_de_read(dev_priv, |
19425 | PIPECONF(cpu_transcoder)); | |
19426 | error->transcoder[i].htotal = intel_de_read(dev_priv, | |
19427 | HTOTAL(cpu_transcoder)); | |
19428 | error->transcoder[i].hblank = intel_de_read(dev_priv, | |
19429 | HBLANK(cpu_transcoder)); | |
19430 | error->transcoder[i].hsync = intel_de_read(dev_priv, | |
19431 | HSYNC(cpu_transcoder)); | |
19432 | error->transcoder[i].vtotal = intel_de_read(dev_priv, | |
19433 | VTOTAL(cpu_transcoder)); | |
19434 | error->transcoder[i].vblank = intel_de_read(dev_priv, | |
19435 | VBLANK(cpu_transcoder)); | |
19436 | error->transcoder[i].vsync = intel_de_read(dev_priv, | |
19437 | VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
19438 | } |
19439 | ||
19440 | return error; | |
19441 | } | |
19442 | ||
edc3d884 MK |
19443 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
19444 | ||
c4a1d9e4 | 19445 | void |
edc3d884 | 19446 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
19447 | struct intel_display_error_state *error) |
19448 | { | |
5a4c6f1b | 19449 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
19450 | int i; |
19451 | ||
63b66e5b CW |
19452 | if (!error) |
19453 | return; | |
19454 | ||
24977870 | 19455 | err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv)); |
8652744b | 19456 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 19457 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 19458 | error->power_well_driver); |
055e393f | 19459 | for_each_pipe(dev_priv, i) { |
edc3d884 | 19460 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 19461 | err_printf(m, " Power: %s\n", |
87ad3212 | 19462 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 19463 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 19464 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
19465 | |
19466 | err_printf(m, "Plane [%d]:\n", i); | |
19467 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
19468 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 19469 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
19470 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
19471 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 19472 | } |
772c2a51 | 19473 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 19474 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 19475 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
19476 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
19477 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
19478 | } |
19479 | ||
edc3d884 MK |
19480 | err_printf(m, "Cursor [%d]:\n", i); |
19481 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
19482 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
19483 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 19484 | } |
63b66e5b | 19485 | |
062de72b LDM |
19486 | for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { |
19487 | if (!error->transcoder[i].available) | |
19488 | continue; | |
19489 | ||
da205630 | 19490 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 19491 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 19492 | err_printf(m, " Power: %s\n", |
87ad3212 | 19493 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
19494 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
19495 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
19496 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
19497 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
19498 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
19499 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
19500 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
19501 | } | |
c4a1d9e4 | 19502 | } |
98a2f411 CW |
19503 | |
19504 | #endif |