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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
d0e93599 SR |
28 | #include <linux/input.h> |
29 | #include <linux/intel-iommu.h> | |
7662c8bd | 30 | #include <linux/kernel.h> |
d0e93599 | 31 | #include <linux/module.h> |
52791eee | 32 | #include <linux/dma-resv.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
d0e93599 | 34 | |
319c1d42 | 35 | #include <drm/drm_atomic.h> |
c196e1d6 | 36 | #include <drm/drm_atomic_helper.h> |
d0e93599 | 37 | #include <drm/drm_atomic_uapi.h> |
093a3a30 | 38 | #include <drm/drm_damage_helper.h> |
760285e7 | 39 | #include <drm/drm_dp_helper.h> |
d0e93599 SR |
40 | #include <drm/drm_edid.h> |
41 | #include <drm/drm_fourcc.h> | |
465c120c | 42 | #include <drm/drm_plane_helper.h> |
fcd70cd3 | 43 | #include <drm/drm_probe_helper.h> |
465c120c | 44 | #include <drm/drm_rect.h> |
d0e93599 | 45 | |
379bc100 JN |
46 | #include "display/intel_crt.h" |
47 | #include "display/intel_ddi.h" | |
48 | #include "display/intel_dp.h" | |
6671c367 | 49 | #include "display/intel_dp_mst.h" |
ddff9a60 | 50 | #include "display/intel_dpll_mgr.h" |
379bc100 JN |
51 | #include "display/intel_dsi.h" |
52 | #include "display/intel_dvo.h" | |
53 | #include "display/intel_gmbus.h" | |
54 | #include "display/intel_hdmi.h" | |
55 | #include "display/intel_lvds.h" | |
56 | #include "display/intel_sdvo.h" | |
57 | #include "display/intel_tv.h" | |
58 | #include "display/intel_vdsc.h" | |
59 | ||
3e7abf81 AS |
60 | #include "gt/intel_rps.h" |
61 | ||
d0e93599 | 62 | #include "i915_drv.h" |
d0e93599 | 63 | #include "i915_trace.h" |
4e49d35c | 64 | #include "intel_acpi.h" |
12392a74 | 65 | #include "intel_atomic.h" |
56dabc93 | 66 | #include "intel_atomic_plane.h" |
c457d9cf | 67 | #include "intel_bw.h" |
e7674ef6 | 68 | #include "intel_cdclk.h" |
1d455f8d | 69 | #include "intel_color.h" |
24d98a54 | 70 | #include "intel_csr.h" |
1d455f8d | 71 | #include "intel_display_types.h" |
3c954c41 | 72 | #include "intel_dp_link_training.h" |
98afa316 | 73 | #include "intel_fbc.h" |
6dfccb95 | 74 | #include "intel_fbdev.h" |
8834e365 | 75 | #include "intel_fifo_underrun.h" |
d0e93599 | 76 | #include "intel_frontbuffer.h" |
408bd917 | 77 | #include "intel_hdcp.h" |
dbeb38d9 | 78 | #include "intel_hotplug.h" |
05ca9306 | 79 | #include "intel_overlay.h" |
c6a35b9c | 80 | #include "intel_pipe_crc.h" |
696173b0 | 81 | #include "intel_pm.h" |
55367a27 | 82 | #include "intel_psr.h" |
220b92bf | 83 | #include "intel_quirks.h" |
56c5098f | 84 | #include "intel_sideband.h" |
f9a79f9a | 85 | #include "intel_sprite.h" |
32691b58 | 86 | #include "intel_tc.h" |
4fb87831 | 87 | #include "intel_vga.h" |
79e53945 | 88 | |
465c120c | 89 | /* Primary plane formats for gen <= 3 */ |
ba3f4d0a | 90 | static const u32 i8xx_primary_formats[] = { |
67fe7dc5 | 91 | DRM_FORMAT_C8, |
465c120c | 92 | DRM_FORMAT_XRGB1555, |
12fef149 | 93 | DRM_FORMAT_RGB565, |
67fe7dc5 | 94 | DRM_FORMAT_XRGB8888, |
465c120c MR |
95 | }; |
96 | ||
03b0ce95 VS |
97 | /* Primary plane formats for ivb (no fp16 due to hw issue) */ |
98 | static const u32 ivb_primary_formats[] = { | |
99 | DRM_FORMAT_C8, | |
100 | DRM_FORMAT_RGB565, | |
101 | DRM_FORMAT_XRGB8888, | |
102 | DRM_FORMAT_XBGR8888, | |
103 | DRM_FORMAT_XRGB2101010, | |
104 | DRM_FORMAT_XBGR2101010, | |
105 | }; | |
106 | ||
107 | /* Primary plane formats for gen >= 4, except ivb */ | |
ba3f4d0a | 108 | static const u32 i965_primary_formats[] = { |
6c0fd451 DL |
109 | DRM_FORMAT_C8, |
110 | DRM_FORMAT_RGB565, | |
111 | DRM_FORMAT_XRGB8888, | |
112 | DRM_FORMAT_XBGR8888, | |
113 | DRM_FORMAT_XRGB2101010, | |
114 | DRM_FORMAT_XBGR2101010, | |
03b0ce95 | 115 | DRM_FORMAT_XBGR16161616F, |
6c0fd451 DL |
116 | }; |
117 | ||
73263cb6 VS |
118 | /* Primary plane formats for vlv/chv */ |
119 | static const u32 vlv_primary_formats[] = { | |
120 | DRM_FORMAT_C8, | |
121 | DRM_FORMAT_RGB565, | |
122 | DRM_FORMAT_XRGB8888, | |
123 | DRM_FORMAT_XBGR8888, | |
124 | DRM_FORMAT_ARGB8888, | |
125 | DRM_FORMAT_ABGR8888, | |
126 | DRM_FORMAT_XRGB2101010, | |
127 | DRM_FORMAT_XBGR2101010, | |
128 | DRM_FORMAT_ARGB2101010, | |
129 | DRM_FORMAT_ABGR2101010, | |
130 | DRM_FORMAT_XBGR16161616F, | |
131 | }; | |
132 | ||
ba3f4d0a | 133 | static const u64 i9xx_format_modifiers[] = { |
714244e2 BW |
134 | I915_FORMAT_MOD_X_TILED, |
135 | DRM_FORMAT_MOD_LINEAR, | |
136 | DRM_FORMAT_MOD_INVALID | |
137 | }; | |
138 | ||
3d7d6510 | 139 | /* Cursor formats */ |
ba3f4d0a | 140 | static const u32 intel_cursor_formats[] = { |
3d7d6510 MR |
141 | DRM_FORMAT_ARGB8888, |
142 | }; | |
143 | ||
ba3f4d0a | 144 | static const u64 cursor_format_modifiers[] = { |
714244e2 BW |
145 | DRM_FORMAT_MOD_LINEAR, |
146 | DRM_FORMAT_MOD_INVALID | |
147 | }; | |
148 | ||
f1f644dc | 149 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 150 | struct intel_crtc_state *pipe_config); |
9eae5e27 LDM |
151 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
152 | struct intel_crtc_state *pipe_config); | |
f1f644dc | 153 | |
24dbf51a CW |
154 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
155 | struct drm_i915_gem_object *obj, | |
156 | struct drm_mode_fb_cmd2 *mode_cmd); | |
44fe7f35 ML |
157 | static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state); |
158 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); | |
4c354754 ML |
159 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
160 | const struct intel_link_m_n *m_n, | |
161 | const struct intel_link_m_n *m2_n2); | |
fdf73510 | 162 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); |
9eae5e27 | 163 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); |
1e98f88c | 164 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state); |
9b11215e | 165 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); |
d288f65f | 166 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 167 | const struct intel_crtc_state *pipe_config); |
d288f65f | 168 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 169 | const struct intel_crtc_state *pipe_config); |
f6df4d46 | 170 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state); |
9eae5e27 | 171 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); |
aecd36b8 VS |
172 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
173 | struct drm_modeset_acquire_ctx *ctx); | |
216383e9 | 174 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); |
e7457a9a | 175 | |
d4906093 | 176 | struct intel_limit { |
4c5def93 ACO |
177 | struct { |
178 | int min, max; | |
179 | } dot, vco, n, m, m1, m2, p, p1; | |
180 | ||
181 | struct { | |
182 | int dot_limit; | |
183 | int p2_slow, p2_fast; | |
184 | } p2; | |
d4906093 | 185 | }; |
79e53945 | 186 | |
bfa7df01 | 187 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 188 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
189 | { |
190 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
191 | ||
192 | /* Obtain SKU information */ | |
bfa7df01 VS |
193 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
194 | CCK_FUSE_HPLL_FREQ_MASK; | |
bfa7df01 VS |
195 | |
196 | return vco_freq[hpll_freq] * 1000; | |
197 | } | |
198 | ||
c30fec65 VS |
199 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
200 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
201 | { |
202 | u32 val; | |
203 | int divider; | |
204 | ||
bfa7df01 | 205 | val = vlv_cck_read(dev_priv, reg); |
bfa7df01 VS |
206 | divider = val & CCK_FREQUENCY_VALUES; |
207 | ||
e57291c2 PB |
208 | drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != |
209 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
210 | "%s change in progress\n", name); | |
bfa7df01 | 211 | |
c30fec65 VS |
212 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
213 | } | |
214 | ||
7ff89ca2 VS |
215 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
216 | const char *name, u32 reg) | |
c30fec65 | 217 | { |
337fa6e0 CW |
218 | int hpll; |
219 | ||
220 | vlv_cck_get(dev_priv); | |
221 | ||
c30fec65 | 222 | if (dev_priv->hpll_freq == 0) |
49cd97a3 | 223 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 | 224 | |
337fa6e0 CW |
225 | hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); |
226 | ||
227 | vlv_cck_put(dev_priv); | |
228 | ||
229 | return hpll; | |
bfa7df01 VS |
230 | } |
231 | ||
bfa7df01 VS |
232 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
233 | { | |
666a4537 | 234 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
235 | return; |
236 | ||
237 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
238 | CCK_CZ_CLOCK_CONTROL); | |
239 | ||
cd49f818 WK |
240 | drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", |
241 | dev_priv->czclk_freq); | |
bfa7df01 VS |
242 | } |
243 | ||
81b55ef1 JN |
244 | /* units of 100MHz */ |
245 | static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv, | |
246 | const struct intel_crtc_state *pipe_config) | |
021357ac | 247 | { |
21a727b3 VS |
248 | if (HAS_DDI(dev_priv)) |
249 | return pipe_config->port_clock; /* SPLL */ | |
e3b247da | 250 | else |
58ecd9d5 | 251 | return dev_priv->fdi_pll_freq; |
021357ac CW |
252 | } |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
265 | }; |
266 | ||
1b6f4958 | 267 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 268 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 269 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 270 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
271 | .m = { .min = 96, .max = 140 }, |
272 | .m1 = { .min = 18, .max = 26 }, | |
273 | .m2 = { .min = 6, .max = 16 }, | |
274 | .p = { .min = 4, .max = 128 }, | |
275 | .p1 = { .min = 2, .max = 33 }, | |
276 | .p2 = { .dot_limit = 165000, | |
277 | .p2_slow = 4, .p2_fast = 4 }, | |
278 | }; | |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 281 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 282 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 283 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
284 | .m = { .min = 96, .max = 140 }, |
285 | .m1 = { .min = 18, .max = 26 }, | |
286 | .m2 = { .min = 6, .max = 16 }, | |
287 | .p = { .min = 4, .max = 128 }, | |
288 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 165000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 291 | }; |
273e27ca | 292 | |
1b6f4958 | 293 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
294 | .dot = { .min = 20000, .max = 400000 }, |
295 | .vco = { .min = 1400000, .max = 2800000 }, | |
296 | .n = { .min = 1, .max = 6 }, | |
297 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
298 | .m1 = { .min = 8, .max = 18 }, |
299 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
300 | .p = { .min = 5, .max = 80 }, |
301 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
302 | .p2 = { .dot_limit = 200000, |
303 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
304 | }; |
305 | ||
1b6f4958 | 306 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
307 | .dot = { .min = 20000, .max = 400000 }, |
308 | .vco = { .min = 1400000, .max = 2800000 }, | |
309 | .n = { .min = 1, .max = 6 }, | |
310 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
311 | .m1 = { .min = 8, .max = 18 }, |
312 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
313 | .p = { .min = 7, .max = 98 }, |
314 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
315 | .p2 = { .dot_limit = 112000, |
316 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
317 | }; |
318 | ||
273e27ca | 319 | |
1b6f4958 | 320 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 270000 }, |
322 | .vco = { .min = 1750000, .max = 3500000}, | |
323 | .n = { .min = 1, .max = 4 }, | |
324 | .m = { .min = 104, .max = 138 }, | |
325 | .m1 = { .min = 17, .max = 23 }, | |
326 | .m2 = { .min = 5, .max = 11 }, | |
327 | .p = { .min = 10, .max = 30 }, | |
328 | .p1 = { .min = 1, .max = 3}, | |
329 | .p2 = { .dot_limit = 270000, | |
330 | .p2_slow = 10, | |
331 | .p2_fast = 10 | |
044c7c41 | 332 | }, |
e4b36699 KP |
333 | }; |
334 | ||
1b6f4958 | 335 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
336 | .dot = { .min = 22000, .max = 400000 }, |
337 | .vco = { .min = 1750000, .max = 3500000}, | |
338 | .n = { .min = 1, .max = 4 }, | |
339 | .m = { .min = 104, .max = 138 }, | |
340 | .m1 = { .min = 16, .max = 23 }, | |
341 | .m2 = { .min = 5, .max = 11 }, | |
342 | .p = { .min = 5, .max = 80 }, | |
343 | .p1 = { .min = 1, .max = 8}, | |
344 | .p2 = { .dot_limit = 165000, | |
345 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
346 | }; |
347 | ||
1b6f4958 | 348 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
349 | .dot = { .min = 20000, .max = 115000 }, |
350 | .vco = { .min = 1750000, .max = 3500000 }, | |
351 | .n = { .min = 1, .max = 3 }, | |
352 | .m = { .min = 104, .max = 138 }, | |
353 | .m1 = { .min = 17, .max = 23 }, | |
354 | .m2 = { .min = 5, .max = 11 }, | |
355 | .p = { .min = 28, .max = 112 }, | |
356 | .p1 = { .min = 2, .max = 8 }, | |
357 | .p2 = { .dot_limit = 0, | |
358 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 359 | }, |
e4b36699 KP |
360 | }; |
361 | ||
1b6f4958 | 362 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
363 | .dot = { .min = 80000, .max = 224000 }, |
364 | .vco = { .min = 1750000, .max = 3500000 }, | |
365 | .n = { .min = 1, .max = 3 }, | |
366 | .m = { .min = 104, .max = 138 }, | |
367 | .m1 = { .min = 17, .max = 23 }, | |
368 | .m2 = { .min = 5, .max = 11 }, | |
369 | .p = { .min = 14, .max = 42 }, | |
370 | .p1 = { .min = 2, .max = 6 }, | |
371 | .p2 = { .dot_limit = 0, | |
372 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 373 | }, |
e4b36699 KP |
374 | }; |
375 | ||
1d218220 | 376 | static const struct intel_limit pnv_limits_sdvo = { |
0206e353 AJ |
377 | .dot = { .min = 20000, .max = 400000}, |
378 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 379 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
380 | .n = { .min = 3, .max = 6 }, |
381 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 382 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
383 | .m1 = { .min = 0, .max = 0 }, |
384 | .m2 = { .min = 0, .max = 254 }, | |
385 | .p = { .min = 5, .max = 80 }, | |
386 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
387 | .p2 = { .dot_limit = 200000, |
388 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
389 | }; |
390 | ||
1d218220 | 391 | static const struct intel_limit pnv_limits_lvds = { |
0206e353 AJ |
392 | .dot = { .min = 20000, .max = 400000 }, |
393 | .vco = { .min = 1700000, .max = 3500000 }, | |
394 | .n = { .min = 3, .max = 6 }, | |
395 | .m = { .min = 2, .max = 256 }, | |
396 | .m1 = { .min = 0, .max = 0 }, | |
397 | .m2 = { .min = 0, .max = 254 }, | |
398 | .p = { .min = 7, .max = 112 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
400 | .p2 = { .dot_limit = 112000, |
401 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
402 | }; |
403 | ||
273e27ca EA |
404 | /* Ironlake / Sandybridge |
405 | * | |
406 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
407 | * the range value for them is (actual_value - 2). | |
408 | */ | |
9eae5e27 | 409 | static const struct intel_limit ilk_limits_dac = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 5 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 5, .max = 80 }, | |
417 | .p1 = { .min = 1, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
420 | }; |
421 | ||
9eae5e27 | 422 | static const struct intel_limit ilk_limits_single_lvds = { |
273e27ca EA |
423 | .dot = { .min = 25000, .max = 350000 }, |
424 | .vco = { .min = 1760000, .max = 3510000 }, | |
425 | .n = { .min = 1, .max = 3 }, | |
426 | .m = { .min = 79, .max = 118 }, | |
427 | .m1 = { .min = 12, .max = 22 }, | |
428 | .m2 = { .min = 5, .max = 9 }, | |
429 | .p = { .min = 28, .max = 112 }, | |
430 | .p1 = { .min = 2, .max = 8 }, | |
431 | .p2 = { .dot_limit = 225000, | |
432 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
433 | }; |
434 | ||
9eae5e27 | 435 | static const struct intel_limit ilk_limits_dual_lvds = { |
273e27ca EA |
436 | .dot = { .min = 25000, .max = 350000 }, |
437 | .vco = { .min = 1760000, .max = 3510000 }, | |
438 | .n = { .min = 1, .max = 3 }, | |
439 | .m = { .min = 79, .max = 127 }, | |
440 | .m1 = { .min = 12, .max = 22 }, | |
441 | .m2 = { .min = 5, .max = 9 }, | |
442 | .p = { .min = 14, .max = 56 }, | |
443 | .p1 = { .min = 2, .max = 8 }, | |
444 | .p2 = { .dot_limit = 225000, | |
445 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
446 | }; |
447 | ||
273e27ca | 448 | /* LVDS 100mhz refclk limits. */ |
9eae5e27 | 449 | static const struct intel_limit ilk_limits_single_lvds_100m = { |
273e27ca EA |
450 | .dot = { .min = 25000, .max = 350000 }, |
451 | .vco = { .min = 1760000, .max = 3510000 }, | |
452 | .n = { .min = 1, .max = 2 }, | |
453 | .m = { .min = 79, .max = 126 }, | |
454 | .m1 = { .min = 12, .max = 22 }, | |
455 | .m2 = { .min = 5, .max = 9 }, | |
456 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 457 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
458 | .p2 = { .dot_limit = 225000, |
459 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
460 | }; |
461 | ||
9eae5e27 | 462 | static const struct intel_limit ilk_limits_dual_lvds_100m = { |
273e27ca EA |
463 | .dot = { .min = 25000, .max = 350000 }, |
464 | .vco = { .min = 1760000, .max = 3510000 }, | |
465 | .n = { .min = 1, .max = 3 }, | |
466 | .m = { .min = 79, .max = 126 }, | |
467 | .m1 = { .min = 12, .max = 22 }, | |
468 | .m2 = { .min = 5, .max = 9 }, | |
469 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 470 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
471 | .p2 = { .dot_limit = 225000, |
472 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
473 | }; |
474 | ||
1b6f4958 | 475 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
476 | /* |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 483 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 484 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
485 | .m1 = { .min = 2, .max = 3 }, |
486 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 487 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 488 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
489 | }; |
490 | ||
1b6f4958 | 491 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
492 | /* |
493 | * These are the data rate limits (measured in fast clocks) | |
494 | * since those are the strictest limits we have. The fast | |
495 | * clock and actual rate limits are more relaxed, so checking | |
496 | * them would make no difference. | |
497 | */ | |
498 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 499 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
500 | .n = { .min = 1, .max = 1 }, |
501 | .m1 = { .min = 2, .max = 2 }, | |
502 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
503 | .p1 = { .min = 2, .max = 4 }, | |
504 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
505 | }; | |
506 | ||
1b6f4958 | 507 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
508 | /* FIXME: find real dot limits */ |
509 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 510 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
511 | .n = { .min = 1, .max = 1 }, |
512 | .m1 = { .min = 2, .max = 2 }, | |
513 | /* FIXME: find real m2 limits */ | |
514 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
515 | .p1 = { .min = 2, .max = 4 }, | |
516 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
517 | }; | |
518 | ||
51eb1a1d | 519 | /* WA Display #0827: Gen9:all */ |
c4a4efa9 | 520 | static void |
d048a268 | 521 | skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) |
c4a4efa9 | 522 | { |
c4a4efa9 | 523 | if (enable) |
dc008bf0 JN |
524 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
525 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); | |
c4a4efa9 | 526 | else |
dc008bf0 JN |
527 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
528 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); | |
c4a4efa9 VS |
529 | } |
530 | ||
f96198ab | 531 | /* Wa_2006604312:icl,ehl */ |
51eb1a1d RS |
532 | static void |
533 | icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, | |
534 | bool enable) | |
535 | { | |
536 | if (enable) | |
dc008bf0 JN |
537 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
538 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); | |
51eb1a1d | 539 | else |
dc008bf0 JN |
540 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), |
541 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); | |
51eb1a1d RS |
542 | } |
543 | ||
cdba954e | 544 | static bool |
69f786ae | 545 | needs_modeset(const struct intel_crtc_state *state) |
cdba954e | 546 | { |
2225f3c6 | 547 | return drm_atomic_crtc_needs_modeset(&state->uapi); |
cdba954e ACO |
548 | } |
549 | ||
d82a855a VS |
550 | static bool |
551 | is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) | |
bfb926e3 | 552 | { |
d82a855a | 553 | return crtc_state->master_transcoder != INVALID_TRANSCODER; |
bfb926e3 MN |
554 | } |
555 | ||
ad457191 | 556 | static bool |
d82a855a | 557 | is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) |
ad457191 | 558 | { |
d82a855a VS |
559 | return crtc_state->sync_mode_slaves_mask != 0; |
560 | } | |
561 | ||
562 | bool | |
563 | is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) | |
564 | { | |
565 | return is_trans_port_sync_master(crtc_state) || | |
566 | is_trans_port_sync_slave(crtc_state); | |
ad457191 JRS |
567 | } |
568 | ||
dccbea3b ID |
569 | /* |
570 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
571 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
572 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
573 | * The helpers' return value is the rate of the clock that is fed to the | |
574 | * display engine's pipe which can be the above fast dot clock rate or a | |
575 | * divided-down version of it. | |
576 | */ | |
f2b115e6 | 577 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 578 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 579 | { |
2177832f SL |
580 | clock->m = clock->m2 + 2; |
581 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 582 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 583 | return 0; |
fb03ac01 VS |
584 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
585 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
586 | |
587 | return clock->dot; | |
2177832f SL |
588 | } |
589 | ||
ba3f4d0a | 590 | static u32 i9xx_dpll_compute_m(struct dpll *dpll) |
7429e9d4 DV |
591 | { |
592 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
593 | } | |
594 | ||
9e2c8475 | 595 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 596 | { |
7429e9d4 | 597 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 598 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 599 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 600 | return 0; |
fb03ac01 VS |
601 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
602 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
603 | |
604 | return clock->dot; | |
79e53945 JB |
605 | } |
606 | ||
9e2c8475 | 607 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
608 | { |
609 | clock->m = clock->m1 * clock->m2; | |
610 | clock->p = clock->p1 * clock->p2; | |
611 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 612 | return 0; |
589eca67 ID |
613 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
614 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
615 | |
616 | return clock->dot / 5; | |
589eca67 ID |
617 | } |
618 | ||
9e2c8475 | 619 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
620 | { |
621 | clock->m = clock->m1 * clock->m2; | |
622 | clock->p = clock->p1 * clock->p2; | |
623 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 624 | return 0; |
d492a29d | 625 | clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), |
ba3f4d0a | 626 | clock->n << 22); |
ef9348c8 | 627 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
dccbea3b ID |
628 | |
629 | return clock->dot / 5; | |
ef9348c8 CML |
630 | } |
631 | ||
c38c1455 | 632 | /* |
79e53945 JB |
633 | * Returns whether the given set of divisors are valid for a given refclk with |
634 | * the given connectors. | |
635 | */ | |
4fb5eec9 | 636 | static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 637 | const struct intel_limit *limit, |
9e2c8475 | 638 | const struct dpll *clock) |
79e53945 | 639 | { |
4fb5eec9 JN |
640 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
641 | return false; | |
642 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
643 | return false; | |
644 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
645 | return false; | |
646 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
647 | return false; | |
f01b7962 | 648 | |
e2d214ae | 649 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 650 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 | 651 | if (clock->m1 <= clock->m2) |
4fb5eec9 | 652 | return false; |
f01b7962 | 653 | |
e2d214ae | 654 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 655 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 | 656 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
4fb5eec9 | 657 | return false; |
f01b7962 | 658 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
4fb5eec9 | 659 | return false; |
f01b7962 VS |
660 | } |
661 | ||
79e53945 | 662 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
4fb5eec9 | 663 | return false; |
79e53945 JB |
664 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
665 | * connector, etc., rather than just a single range. | |
666 | */ | |
667 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
4fb5eec9 | 668 | return false; |
79e53945 JB |
669 | |
670 | return true; | |
671 | } | |
672 | ||
3b1429d9 | 673 | static int |
1b6f4958 | 674 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
675 | const struct intel_crtc_state *crtc_state, |
676 | int target) | |
79e53945 | 677 | { |
2225f3c6 | 678 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
79e53945 | 679 | |
2d84d2b3 | 680 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 681 | /* |
a210b028 DV |
682 | * For LVDS just rely on its current settings for dual-channel. |
683 | * We haven't figured out how to reliably set up different | |
684 | * single/dual channel state, if we even can. | |
79e53945 | 685 | */ |
d2daff2c | 686 | if (intel_is_dual_link_lvds(dev_priv)) |
3b1429d9 | 687 | return limit->p2.p2_fast; |
79e53945 | 688 | else |
3b1429d9 | 689 | return limit->p2.p2_slow; |
79e53945 JB |
690 | } else { |
691 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 692 | return limit->p2.p2_slow; |
79e53945 | 693 | else |
3b1429d9 | 694 | return limit->p2.p2_fast; |
79e53945 | 695 | } |
3b1429d9 VS |
696 | } |
697 | ||
70e8aa21 ACO |
698 | /* |
699 | * Returns a set of divisors for the desired target clock with the given | |
700 | * refclk, or FALSE. The returned values represent the clock equation: | |
701 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
702 | * | |
703 | * Target and reference clocks are specified in kHz. | |
704 | * | |
705 | * If match_clock is provided, then best_clock P divider must match the P | |
706 | * divider from @match_clock used for LVDS downclocking. | |
707 | */ | |
3b1429d9 | 708 | static bool |
1b6f4958 | 709 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 710 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
711 | int target, int refclk, struct dpll *match_clock, |
712 | struct dpll *best_clock) | |
3b1429d9 | 713 | { |
2225f3c6 | 714 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 715 | struct dpll clock; |
3b1429d9 | 716 | int err = target; |
79e53945 | 717 | |
0206e353 | 718 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 719 | |
3b1429d9 VS |
720 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
721 | ||
42158660 ZY |
722 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
723 | clock.m1++) { | |
724 | for (clock.m2 = limit->m2.min; | |
725 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 726 | if (clock.m2 >= clock.m1) |
42158660 ZY |
727 | break; |
728 | for (clock.n = limit->n.min; | |
729 | clock.n <= limit->n.max; clock.n++) { | |
730 | for (clock.p1 = limit->p1.min; | |
731 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
732 | int this_err; |
733 | ||
dccbea3b | 734 | i9xx_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 735 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 736 | limit, |
ac58c3f0 DV |
737 | &clock)) |
738 | continue; | |
739 | if (match_clock && | |
740 | clock.p != match_clock->p) | |
741 | continue; | |
742 | ||
743 | this_err = abs(clock.dot - target); | |
744 | if (this_err < err) { | |
745 | *best_clock = clock; | |
746 | err = this_err; | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
751 | } | |
752 | ||
753 | return (err != target); | |
754 | } | |
755 | ||
70e8aa21 ACO |
756 | /* |
757 | * Returns a set of divisors for the desired target clock with the given | |
758 | * refclk, or FALSE. The returned values represent the clock equation: | |
759 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
760 | * | |
761 | * Target and reference clocks are specified in kHz. | |
762 | * | |
763 | * If match_clock is provided, then best_clock P divider must match the P | |
764 | * divider from @match_clock used for LVDS downclocking. | |
765 | */ | |
ac58c3f0 | 766 | static bool |
1b6f4958 | 767 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 768 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
769 | int target, int refclk, struct dpll *match_clock, |
770 | struct dpll *best_clock) | |
79e53945 | 771 | { |
2225f3c6 | 772 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 773 | struct dpll clock; |
79e53945 JB |
774 | int err = target; |
775 | ||
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
784 | for (clock.n = limit->n.min; |
785 | clock.n <= limit->n.max; clock.n++) { | |
786 | for (clock.p1 = limit->p1.min; | |
787 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
788 | int this_err; |
789 | ||
dccbea3b | 790 | pnv_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 791 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 792 | limit, |
1b894b59 | 793 | &clock)) |
79e53945 | 794 | continue; |
cec2f356 SP |
795 | if (match_clock && |
796 | clock.p != match_clock->p) | |
797 | continue; | |
79e53945 JB |
798 | |
799 | this_err = abs(clock.dot - target); | |
800 | if (this_err < err) { | |
801 | *best_clock = clock; | |
802 | err = this_err; | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
809 | return (err != target); | |
810 | } | |
811 | ||
997c030c ACO |
812 | /* |
813 | * Returns a set of divisors for the desired target clock with the given | |
814 | * refclk, or FALSE. The returned values represent the clock equation: | |
815 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
816 | * |
817 | * Target and reference clocks are specified in kHz. | |
818 | * | |
819 | * If match_clock is provided, then best_clock P divider must match the P | |
820 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 821 | */ |
d4906093 | 822 | static bool |
1b6f4958 | 823 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 824 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
825 | int target, int refclk, struct dpll *match_clock, |
826 | struct dpll *best_clock) | |
d4906093 | 827 | { |
2225f3c6 | 828 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
9e2c8475 | 829 | struct dpll clock; |
d4906093 | 830 | int max_n; |
3b1429d9 | 831 | bool found = false; |
6ba770dc AJ |
832 | /* approximately equals target * 0.00585 */ |
833 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
834 | |
835 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
836 | |
837 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
838 | ||
d4906093 | 839 | max_n = limit->n.max; |
f77f13e2 | 840 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 841 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 842 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
843 | for (clock.m1 = limit->m1.max; |
844 | clock.m1 >= limit->m1.min; clock.m1--) { | |
845 | for (clock.m2 = limit->m2.max; | |
846 | clock.m2 >= limit->m2.min; clock.m2--) { | |
847 | for (clock.p1 = limit->p1.max; | |
848 | clock.p1 >= limit->p1.min; clock.p1--) { | |
849 | int this_err; | |
850 | ||
dccbea3b | 851 | i9xx_calc_dpll_params(refclk, &clock); |
4fb5eec9 | 852 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 853 | limit, |
1b894b59 | 854 | &clock)) |
d4906093 | 855 | continue; |
1b894b59 CW |
856 | |
857 | this_err = abs(clock.dot - target); | |
d4906093 ML |
858 | if (this_err < err_most) { |
859 | *best_clock = clock; | |
860 | err_most = this_err; | |
861 | max_n = clock.n; | |
862 | found = true; | |
863 | } | |
864 | } | |
865 | } | |
866 | } | |
867 | } | |
2c07245f ZW |
868 | return found; |
869 | } | |
870 | ||
d5dd62bd ID |
871 | /* |
872 | * Check if the calculated PLL configuration is more optimal compared to the | |
873 | * best configuration and error found so far. Return the calculated error. | |
874 | */ | |
875 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
876 | const struct dpll *calculated_clock, |
877 | const struct dpll *best_clock, | |
d5dd62bd ID |
878 | unsigned int best_error_ppm, |
879 | unsigned int *error_ppm) | |
880 | { | |
9ca3ba01 ID |
881 | /* |
882 | * For CHV ignore the error and consider only the P value. | |
883 | * Prefer a bigger P value based on HW requirements. | |
884 | */ | |
920a14b2 | 885 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
886 | *error_ppm = 0; |
887 | ||
888 | return calculated_clock->p > best_clock->p; | |
889 | } | |
890 | ||
e57291c2 | 891 | if (drm_WARN_ON_ONCE(dev, !target_freq)) |
24be4e46 ID |
892 | return false; |
893 | ||
d5dd62bd ID |
894 | *error_ppm = div_u64(1000000ULL * |
895 | abs(target_freq - calculated_clock->dot), | |
896 | target_freq); | |
897 | /* | |
898 | * Prefer a better P value over a better (smaller) error if the error | |
899 | * is small. Ensure this preference for future configurations too by | |
900 | * setting the error to 0. | |
901 | */ | |
902 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
903 | *error_ppm = 0; | |
904 | ||
905 | return true; | |
906 | } | |
907 | ||
908 | return *error_ppm + 10 < best_error_ppm; | |
909 | } | |
910 | ||
65b3d6a9 ACO |
911 | /* |
912 | * Returns a set of divisors for the desired target clock with the given | |
913 | * refclk, or FALSE. The returned values represent the clock equation: | |
914 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
915 | */ | |
a0c4da24 | 916 | static bool |
1b6f4958 | 917 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 918 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
919 | int target, int refclk, struct dpll *match_clock, |
920 | struct dpll *best_clock) | |
a0c4da24 | 921 | { |
2225f3c6 | 922 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a919ff14 | 923 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 924 | struct dpll clock; |
69e4f900 | 925 | unsigned int bestppm = 1000000; |
27e639bf VS |
926 | /* min update 19.2 MHz */ |
927 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 928 | bool found = false; |
a0c4da24 | 929 | |
6b4bf1c4 VS |
930 | target *= 5; /* fast clock */ |
931 | ||
932 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
933 | |
934 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 935 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 936 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 937 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 938 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 939 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 940 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 941 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 942 | unsigned int ppm; |
69e4f900 | 943 | |
6b4bf1c4 VS |
944 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
945 | refclk * clock.m1); | |
946 | ||
dccbea3b | 947 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 948 | |
4fb5eec9 | 949 | if (!intel_pll_is_valid(to_i915(dev), |
e2d214ae | 950 | limit, |
f01b7962 | 951 | &clock)) |
43b0ac53 VS |
952 | continue; |
953 | ||
d5dd62bd ID |
954 | if (!vlv_PLL_is_optimal(dev, target, |
955 | &clock, | |
956 | best_clock, | |
957 | bestppm, &ppm)) | |
958 | continue; | |
6b4bf1c4 | 959 | |
d5dd62bd ID |
960 | *best_clock = clock; |
961 | bestppm = ppm; | |
962 | found = true; | |
a0c4da24 JB |
963 | } |
964 | } | |
965 | } | |
966 | } | |
a0c4da24 | 967 | |
49e497ef | 968 | return found; |
a0c4da24 | 969 | } |
a4fc5ed6 | 970 | |
65b3d6a9 ACO |
971 | /* |
972 | * Returns a set of divisors for the desired target clock with the given | |
973 | * refclk, or FALSE. The returned values represent the clock equation: | |
974 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
975 | */ | |
ef9348c8 | 976 | static bool |
1b6f4958 | 977 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 978 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
979 | int target, int refclk, struct dpll *match_clock, |
980 | struct dpll *best_clock) | |
ef9348c8 | 981 | { |
2225f3c6 | 982 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a919ff14 | 983 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 984 | unsigned int best_error_ppm; |
9e2c8475 | 985 | struct dpll clock; |
ba3f4d0a | 986 | u64 m2; |
ef9348c8 CML |
987 | int found = false; |
988 | ||
989 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 990 | best_error_ppm = 1000000; |
ef9348c8 CML |
991 | |
992 | /* | |
993 | * Based on hardware doc, the n always set to 1, and m1 always | |
994 | * set to 2. If requires to support 200Mhz refclk, we need to | |
995 | * revisit this because n may not 1 anymore. | |
996 | */ | |
997 | clock.n = 1, clock.m1 = 2; | |
998 | target *= 5; /* fast clock */ | |
999 | ||
1000 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1001 | for (clock.p2 = limit->p2.p2_fast; | |
1002 | clock.p2 >= limit->p2.p2_slow; | |
1003 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1004 | unsigned int error_ppm; |
ef9348c8 CML |
1005 | |
1006 | clock.p = clock.p1 * clock.p2; | |
1007 | ||
d492a29d VS |
1008 | m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, |
1009 | refclk * clock.m1); | |
ef9348c8 CML |
1010 | |
1011 | if (m2 > INT_MAX/clock.m1) | |
1012 | continue; | |
1013 | ||
1014 | clock.m2 = m2; | |
1015 | ||
dccbea3b | 1016 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 1017 | |
4fb5eec9 | 1018 | if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
1019 | continue; |
1020 | ||
9ca3ba01 ID |
1021 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1022 | best_error_ppm, &error_ppm)) | |
1023 | continue; | |
1024 | ||
1025 | *best_clock = clock; | |
1026 | best_error_ppm = error_ppm; | |
1027 | found = true; | |
ef9348c8 CML |
1028 | } |
1029 | } | |
1030 | ||
1031 | return found; | |
1032 | } | |
1033 | ||
e40396d0 | 1034 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
9e2c8475 | 1035 | struct dpll *best_clock) |
5ab7b0b7 | 1036 | { |
65b3d6a9 | 1037 | int refclk = 100000; |
1b6f4958 | 1038 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1039 | |
65b3d6a9 | 1040 | return chv_find_best_dpll(limit, crtc_state, |
e40396d0 VS |
1041 | crtc_state->port_clock, refclk, |
1042 | NULL, best_clock); | |
5ab7b0b7 ID |
1043 | } |
1044 | ||
8fedd64d VS |
1045 | static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe) | |
fbf49ea2 | 1047 | { |
f0f59a00 | 1048 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1049 | u32 line1, line2; |
1050 | u32 line_mask; | |
1051 | ||
cf819eff | 1052 | if (IS_GEN(dev_priv, 2)) |
fbf49ea2 VS |
1053 | line_mask = DSL_LINEMASK_GEN2; |
1054 | else | |
1055 | line_mask = DSL_LINEMASK_GEN3; | |
1056 | ||
dc008bf0 | 1057 | line1 = intel_de_read(dev_priv, reg) & line_mask; |
6adfb1ef | 1058 | msleep(5); |
dc008bf0 | 1059 | line2 = intel_de_read(dev_priv, reg) & line_mask; |
fbf49ea2 | 1060 | |
8fedd64d VS |
1061 | return line1 != line2; |
1062 | } | |
1063 | ||
1064 | static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) | |
1065 | { | |
1066 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1067 | enum pipe pipe = crtc->pipe; | |
1068 | ||
1069 | /* Wait for the display line to settle/start moving */ | |
1070 | if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) | |
cd49f818 WK |
1071 | drm_err(&dev_priv->drm, |
1072 | "pipe %c scanline %s wait timed out\n", | |
1073 | pipe_name(pipe), onoff(state)); | |
8fedd64d VS |
1074 | } |
1075 | ||
1076 | static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) | |
1077 | { | |
1078 | wait_for_pipe_scanline_moving(crtc, false); | |
1079 | } | |
1080 | ||
1081 | static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) | |
1082 | { | |
1083 | wait_for_pipe_scanline_moving(crtc, true); | |
fbf49ea2 VS |
1084 | } |
1085 | ||
4972f70a VS |
1086 | static void |
1087 | intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) | |
9d0498a2 | 1088 | { |
2225f3c6 | 1089 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
6315b5d3 | 1090 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab7ad7f6 | 1091 | |
6315b5d3 | 1092 | if (INTEL_GEN(dev_priv) >= 4) { |
4972f70a | 1093 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
f0f59a00 | 1094 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1095 | |
1096 | /* Wait for the Pipe State to go off */ | |
4cb3b44d DCS |
1097 | if (intel_de_wait_for_clear(dev_priv, reg, |
1098 | I965_PIPECONF_ACTIVE, 100)) | |
e57291c2 PB |
1099 | drm_WARN(&dev_priv->drm, 1, |
1100 | "pipe_off wait timed out\n"); | |
ab7ad7f6 | 1101 | } else { |
8fedd64d | 1102 | intel_wait_for_pipe_scanline_stopped(crtc); |
ab7ad7f6 | 1103 | } |
79e53945 JB |
1104 | } |
1105 | ||
b24e7179 | 1106 | /* Only for pre-ILK configs */ |
55607e8a DV |
1107 | void assert_pll(struct drm_i915_private *dev_priv, |
1108 | enum pipe pipe, bool state) | |
b24e7179 | 1109 | { |
b24e7179 JB |
1110 | u32 val; |
1111 | bool cur_state; | |
1112 | ||
dc008bf0 | 1113 | val = intel_de_read(dev_priv, DPLL(pipe)); |
b24e7179 | 1114 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1115 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1116 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1117 | onoff(state), onoff(cur_state)); |
b24e7179 | 1118 | } |
b24e7179 | 1119 | |
23538ef1 | 1120 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1121 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1122 | { |
1123 | u32 val; | |
1124 | bool cur_state; | |
1125 | ||
221c7862 | 1126 | vlv_cck_get(dev_priv); |
23538ef1 | 1127 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
221c7862 | 1128 | vlv_cck_put(dev_priv); |
23538ef1 JN |
1129 | |
1130 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1131 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1132 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1133 | onoff(state), onoff(cur_state)); |
23538ef1 | 1134 | } |
23538ef1 | 1135 | |
040484af JB |
1136 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1137 | enum pipe pipe, bool state) | |
1138 | { | |
040484af JB |
1139 | bool cur_state; |
1140 | ||
2d1fe073 | 1141 | if (HAS_DDI(dev_priv)) { |
a722146b VS |
1142 | /* |
1143 | * DDI does not have a specific FDI_TX register. | |
1144 | * | |
1145 | * FDI is never fed from EDP transcoder | |
1146 | * so pipe->transcoder cast is fine here. | |
1147 | */ | |
1148 | enum transcoder cpu_transcoder = (enum transcoder)pipe; | |
dc008bf0 JN |
1149 | u32 val = intel_de_read(dev_priv, |
1150 | TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
ad80a810 | 1151 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1152 | } else { |
dc008bf0 | 1153 | u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1154 | cur_state = !!(val & FDI_TX_ENABLE); |
1155 | } | |
e2c719b7 | 1156 | I915_STATE_WARN(cur_state != state, |
040484af | 1157 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1158 | onoff(state), onoff(cur_state)); |
040484af JB |
1159 | } |
1160 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1161 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1162 | ||
1163 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1164 | enum pipe pipe, bool state) | |
1165 | { | |
040484af JB |
1166 | u32 val; |
1167 | bool cur_state; | |
1168 | ||
dc008bf0 | 1169 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); |
d63fa0dc | 1170 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1171 | I915_STATE_WARN(cur_state != state, |
040484af | 1172 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1173 | onoff(state), onoff(cur_state)); |
040484af JB |
1174 | } |
1175 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1176 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1177 | ||
1178 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1179 | enum pipe pipe) | |
1180 | { | |
040484af JB |
1181 | u32 val; |
1182 | ||
1183 | /* ILK FDI PLL is always enabled */ | |
cf819eff | 1184 | if (IS_GEN(dev_priv, 5)) |
040484af JB |
1185 | return; |
1186 | ||
bf507ef7 | 1187 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1188 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1189 | return; |
1190 | ||
dc008bf0 | 1191 | val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); |
e2c719b7 | 1192 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1193 | } |
1194 | ||
55607e8a DV |
1195 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
040484af | 1197 | { |
040484af | 1198 | u32 val; |
55607e8a | 1199 | bool cur_state; |
040484af | 1200 | |
dc008bf0 | 1201 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); |
55607e8a | 1202 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1203 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1204 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1205 | onoff(state), onoff(cur_state)); |
040484af JB |
1206 | } |
1207 | ||
4f8036a2 | 1208 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1209 | { |
f0f59a00 | 1210 | i915_reg_t pp_reg; |
ea0760cf | 1211 | u32 val; |
10ed55e4 | 1212 | enum pipe panel_pipe = INVALID_PIPE; |
0de3b485 | 1213 | bool locked = true; |
ea0760cf | 1214 | |
e57291c2 | 1215 | if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) |
bedd4dba JN |
1216 | return; |
1217 | ||
4f8036a2 | 1218 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1219 | u32 port_sel; |
1220 | ||
44cb734c | 1221 | pp_reg = PP_CONTROL(0); |
dc008bf0 | 1222 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; |
bedd4dba | 1223 | |
4c23dea4 VS |
1224 | switch (port_sel) { |
1225 | case PANEL_PORT_SELECT_LVDS: | |
a44628b9 | 1226 | intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe); |
4c23dea4 VS |
1227 | break; |
1228 | case PANEL_PORT_SELECT_DPA: | |
1229 | intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe); | |
1230 | break; | |
1231 | case PANEL_PORT_SELECT_DPC: | |
1232 | intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe); | |
1233 | break; | |
1234 | case PANEL_PORT_SELECT_DPD: | |
1235 | intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe); | |
1236 | break; | |
1237 | default: | |
1238 | MISSING_CASE(port_sel); | |
1239 | break; | |
1240 | } | |
4f8036a2 | 1241 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1242 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1243 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1244 | panel_pipe = pipe; |
ea0760cf | 1245 | } else { |
f0d2b758 VS |
1246 | u32 port_sel; |
1247 | ||
44cb734c | 1248 | pp_reg = PP_CONTROL(0); |
dc008bf0 | 1249 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; |
f0d2b758 | 1250 | |
e57291c2 PB |
1251 | drm_WARN_ON(&dev_priv->drm, |
1252 | port_sel != PANEL_PORT_SELECT_LVDS); | |
a44628b9 | 1253 | intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); |
ea0760cf JB |
1254 | } |
1255 | ||
dc008bf0 | 1256 | val = intel_de_read(dev_priv, pp_reg); |
ea0760cf | 1257 | if (!(val & PANEL_POWER_ON) || |
ec49ba2d | 1258 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1259 | locked = false; |
1260 | ||
e2c719b7 | 1261 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1262 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1263 | pipe_name(pipe)); |
ea0760cf JB |
1264 | } |
1265 | ||
b840d907 | 1266 | void assert_pipe(struct drm_i915_private *dev_priv, |
b104e8b2 | 1267 | enum transcoder cpu_transcoder, bool state) |
b24e7179 | 1268 | { |
63d7bbe9 | 1269 | bool cur_state; |
4feed0eb | 1270 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 1271 | intel_wakeref_t wakeref; |
b24e7179 | 1272 | |
e56134bc VS |
1273 | /* we keep both pipes enabled on 830 */ |
1274 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1275 | state = true; |
1276 | ||
4feed0eb | 1277 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
0e6e0be4 CW |
1278 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
1279 | if (wakeref) { | |
dc008bf0 | 1280 | u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); |
69310161 | 1281 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb | 1282 | |
0e6e0be4 | 1283 | intel_display_power_put(dev_priv, power_domain, wakeref); |
4feed0eb ID |
1284 | } else { |
1285 | cur_state = false; | |
69310161 PZ |
1286 | } |
1287 | ||
e2c719b7 | 1288 | I915_STATE_WARN(cur_state != state, |
b104e8b2 VS |
1289 | "transcoder %s assertion failure (expected %s, current %s)\n", |
1290 | transcoder_name(cpu_transcoder), | |
1291 | onoff(state), onoff(cur_state)); | |
b24e7179 JB |
1292 | } |
1293 | ||
51f5a096 | 1294 | static void assert_plane(struct intel_plane *plane, bool state) |
b24e7179 | 1295 | { |
eade6c89 VS |
1296 | enum pipe pipe; |
1297 | bool cur_state; | |
1298 | ||
1299 | cur_state = plane->get_hw_state(plane, &pipe); | |
b24e7179 | 1300 | |
e2c719b7 | 1301 | I915_STATE_WARN(cur_state != state, |
51f5a096 VS |
1302 | "%s assertion failure (expected %s, current %s)\n", |
1303 | plane->base.name, onoff(state), onoff(cur_state)); | |
b24e7179 JB |
1304 | } |
1305 | ||
51f5a096 VS |
1306 | #define assert_plane_enabled(p) assert_plane(p, true) |
1307 | #define assert_plane_disabled(p) assert_plane(p, false) | |
931872fc | 1308 | |
51f5a096 | 1309 | static void assert_planes_disabled(struct intel_crtc *crtc) |
b24e7179 | 1310 | { |
51f5a096 VS |
1311 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1312 | struct intel_plane *plane; | |
19332d7a | 1313 | |
51f5a096 VS |
1314 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) |
1315 | assert_plane_disabled(plane); | |
19332d7a JB |
1316 | } |
1317 | ||
08c71e5e VS |
1318 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1319 | { | |
e2c719b7 | 1320 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1321 | drm_crtc_vblank_put(crtc); |
1322 | } | |
1323 | ||
7abd4b35 ACO |
1324 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1325 | enum pipe pipe) | |
92f2584a | 1326 | { |
92f2584a JB |
1327 | u32 val; |
1328 | bool enabled; | |
1329 | ||
dc008bf0 | 1330 | val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); |
92f2584a | 1331 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1332 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1333 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1334 | pipe_name(pipe)); | |
92f2584a JB |
1335 | } |
1336 | ||
59b74c49 VS |
1337 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1338 | enum pipe pipe, enum port port, | |
1339 | i915_reg_t dp_reg) | |
f0575e92 | 1340 | { |
59b74c49 VS |
1341 | enum pipe port_pipe; |
1342 | bool state; | |
f0575e92 | 1343 | |
59b74c49 | 1344 | state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); |
f0575e92 | 1345 | |
59b74c49 VS |
1346 | I915_STATE_WARN(state && port_pipe == pipe, |
1347 | "PCH DP %c enabled on transcoder %c, should be disabled\n", | |
1348 | port_name(port), pipe_name(pipe)); | |
1349 | ||
1350 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, | |
1351 | "IBX PCH DP %c still using transcoder B\n", | |
1352 | port_name(port)); | |
291906f1 JB |
1353 | } |
1354 | ||
1355 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
76203467 VS |
1356 | enum pipe pipe, enum port port, |
1357 | i915_reg_t hdmi_reg) | |
291906f1 | 1358 | { |
76203467 VS |
1359 | enum pipe port_pipe; |
1360 | bool state; | |
1361 | ||
1362 | state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); | |
1363 | ||
1364 | I915_STATE_WARN(state && port_pipe == pipe, | |
1365 | "PCH HDMI %c enabled on transcoder %c, should be disabled\n", | |
1366 | port_name(port), pipe_name(pipe)); | |
de9a35ab | 1367 | |
76203467 VS |
1368 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, |
1369 | "IBX PCH HDMI %c still using transcoder B\n", | |
1370 | port_name(port)); | |
291906f1 JB |
1371 | } |
1372 | ||
1373 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1374 | enum pipe pipe) | |
1375 | { | |
6102a8ee | 1376 | enum pipe port_pipe; |
291906f1 | 1377 | |
59b74c49 VS |
1378 | assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); |
1379 | assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); | |
1380 | assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); | |
291906f1 | 1381 | |
6102a8ee VS |
1382 | I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && |
1383 | port_pipe == pipe, | |
1384 | "PCH VGA enabled on transcoder %c, should be disabled\n", | |
1385 | pipe_name(pipe)); | |
291906f1 | 1386 | |
a44628b9 VS |
1387 | I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && |
1388 | port_pipe == pipe, | |
1389 | "PCH LVDS enabled on transcoder %c, should be disabled\n", | |
1390 | pipe_name(pipe)); | |
291906f1 | 1391 | |
3aefb67f | 1392 | /* PCH SDVOB multiplex with HDMIB */ |
76203467 VS |
1393 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); |
1394 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); | |
1395 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); | |
291906f1 JB |
1396 | } |
1397 | ||
cd2d34d9 VS |
1398 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1399 | const struct intel_crtc_state *pipe_config) | |
1400 | { | |
1401 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1402 | enum pipe pipe = crtc->pipe; | |
1403 | ||
dc008bf0 JN |
1404 | intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
1405 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
cd2d34d9 VS |
1406 | udelay(150); |
1407 | ||
4cb3b44d | 1408 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) |
cd49f818 | 1409 | drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1410 | } |
1411 | ||
d288f65f | 1412 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1413 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1414 | { |
cd2d34d9 | 1415 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1416 | enum pipe pipe = crtc->pipe; |
87442f73 | 1417 | |
b104e8b2 | 1418 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
87442f73 | 1419 | |
87442f73 | 1420 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1421 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1422 | |
cd2d34d9 VS |
1423 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1424 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1425 | |
dc008bf0 JN |
1426 | intel_de_write(dev_priv, DPLL_MD(pipe), |
1427 | pipe_config->dpll_hw_state.dpll_md); | |
1428 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)); | |
87442f73 DV |
1429 | } |
1430 | ||
cd2d34d9 VS |
1431 | |
1432 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1433 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1434 | { |
cd2d34d9 | 1435 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1436 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1437 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1438 | u32 tmp; |
1439 | ||
221c7862 | 1440 | vlv_dpio_get(dev_priv); |
9d556c99 CML |
1441 | |
1442 | /* Enable back the 10bit clock to display controller */ | |
1443 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1444 | tmp |= DPIO_DCLKP_EN; | |
1445 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1446 | ||
221c7862 | 1447 | vlv_dpio_put(dev_priv); |
54433e91 | 1448 | |
9d556c99 CML |
1449 | /* |
1450 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1451 | */ | |
1452 | udelay(1); | |
1453 | ||
1454 | /* Enable PLL */ | |
dc008bf0 | 1455 | intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1456 | |
1457 | /* Check PLL is locked */ | |
4cb3b44d | 1458 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) |
cd49f818 | 1459 | drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1460 | } |
1461 | ||
1462 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1463 | const struct intel_crtc_state *pipe_config) | |
1464 | { | |
1465 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1466 | enum pipe pipe = crtc->pipe; | |
1467 | ||
b104e8b2 | 1468 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
cd2d34d9 VS |
1469 | |
1470 | /* PLL is protected by panel, make sure we can write it */ | |
1471 | assert_panel_unlocked(dev_priv, pipe); | |
1472 | ||
1473 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1474 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1475 | |
c231775c VS |
1476 | if (pipe != PIPE_A) { |
1477 | /* | |
1478 | * WaPixelRepeatModeFixForC0:chv | |
1479 | * | |
1480 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1481 | * the value from DPLLBMD to either pipe B or C. | |
1482 | */ | |
dc008bf0 JN |
1483 | intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); |
1484 | intel_de_write(dev_priv, DPLL_MD(PIPE_B), | |
1485 | pipe_config->dpll_hw_state.dpll_md); | |
1486 | intel_de_write(dev_priv, CBR4_VLV, 0); | |
c231775c VS |
1487 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; |
1488 | ||
1489 | /* | |
1490 | * DPLLB VGA mode also seems to cause problems. | |
1491 | * We should always have it disabled. | |
1492 | */ | |
e57291c2 PB |
1493 | drm_WARN_ON(&dev_priv->drm, |
1494 | (intel_de_read(dev_priv, DPLL(PIPE_B)) & | |
1495 | DPLL_VGA_MODE_DIS) == 0); | |
c231775c | 1496 | } else { |
dc008bf0 JN |
1497 | intel_de_write(dev_priv, DPLL_MD(pipe), |
1498 | pipe_config->dpll_hw_state.dpll_md); | |
1499 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)); | |
c231775c | 1500 | } |
9d556c99 CML |
1501 | } |
1502 | ||
9e7d5699 VS |
1503 | static bool i9xx_has_pps(struct drm_i915_private *dev_priv) |
1504 | { | |
1505 | if (IS_I830(dev_priv)) | |
1506 | return false; | |
1507 | ||
1508 | return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); | |
1509 | } | |
1510 | ||
939994da VS |
1511 | static void i9xx_enable_pll(struct intel_crtc *crtc, |
1512 | const struct intel_crtc_state *crtc_state) | |
63d7bbe9 | 1513 | { |
6315b5d3 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1515 | i915_reg_t reg = DPLL(crtc->pipe); |
939994da | 1516 | u32 dpll = crtc_state->dpll_hw_state.dpll; |
bb408dd2 | 1517 | int i; |
63d7bbe9 | 1518 | |
b104e8b2 | 1519 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
58c6eaa2 | 1520 | |
63d7bbe9 | 1521 | /* PLL is protected by panel, make sure we can write it */ |
9e7d5699 | 1522 | if (i9xx_has_pps(dev_priv)) |
66e3d5c0 | 1523 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1524 | |
c2b63374 VS |
1525 | /* |
1526 | * Apparently we need to have VGA mode enabled prior to changing | |
1527 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1528 | * dividers, even though the register value does change. | |
1529 | */ | |
dc008bf0 JN |
1530 | intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); |
1531 | intel_de_write(dev_priv, reg, dpll); | |
8e7a65aa | 1532 | |
66e3d5c0 | 1533 | /* Wait for the clocks to stabilize. */ |
dc008bf0 | 1534 | intel_de_posting_read(dev_priv, reg); |
66e3d5c0 DV |
1535 | udelay(150); |
1536 | ||
6315b5d3 | 1537 | if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
1538 | intel_de_write(dev_priv, DPLL_MD(crtc->pipe), |
1539 | crtc_state->dpll_hw_state.dpll_md); | |
66e3d5c0 DV |
1540 | } else { |
1541 | /* The pixel multiplier can only be updated once the | |
1542 | * DPLL is enabled and the clocks are stable. | |
1543 | * | |
1544 | * So write it again. | |
1545 | */ | |
dc008bf0 | 1546 | intel_de_write(dev_priv, reg, dpll); |
66e3d5c0 | 1547 | } |
63d7bbe9 JB |
1548 | |
1549 | /* We do this three times for luck */ | |
bb408dd2 | 1550 | for (i = 0; i < 3; i++) { |
dc008bf0 JN |
1551 | intel_de_write(dev_priv, reg, dpll); |
1552 | intel_de_posting_read(dev_priv, reg); | |
bb408dd2 VS |
1553 | udelay(150); /* wait for warmup */ |
1554 | } | |
63d7bbe9 JB |
1555 | } |
1556 | ||
b2354c78 | 1557 | static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) |
63d7bbe9 | 1558 | { |
2225f3c6 | 1559 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 1560 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1561 | enum pipe pipe = crtc->pipe; |
1562 | ||
b6b5d049 | 1563 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1564 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1565 | return; |
1566 | ||
1567 | /* Make sure the pipe isn't still relying on us */ | |
b104e8b2 | 1568 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
63d7bbe9 | 1569 | |
dc008bf0 JN |
1570 | intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); |
1571 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
63d7bbe9 JB |
1572 | } |
1573 | ||
f6071166 JB |
1574 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1575 | { | |
b8afb911 | 1576 | u32 val; |
f6071166 JB |
1577 | |
1578 | /* Make sure the pipe isn't still relying on us */ | |
b104e8b2 | 1579 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe); |
f6071166 | 1580 | |
03ed5cbf VS |
1581 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1582 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1583 | if (pipe != PIPE_A) | |
1584 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1585 | ||
dc008bf0 JN |
1586 | intel_de_write(dev_priv, DPLL(pipe), val); |
1587 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
076ed3b2 CML |
1588 | } |
1589 | ||
1590 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1591 | { | |
d752048d | 1592 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1593 | u32 val; |
1594 | ||
a11b0703 | 1595 | /* Make sure the pipe isn't still relying on us */ |
b104e8b2 | 1596 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe); |
076ed3b2 | 1597 | |
60bfe44f VS |
1598 | val = DPLL_SSC_REF_CLK_CHV | |
1599 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1600 | if (pipe != PIPE_A) |
1601 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1602 | |
dc008bf0 JN |
1603 | intel_de_write(dev_priv, DPLL(pipe), val); |
1604 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
d752048d | 1605 | |
221c7862 | 1606 | vlv_dpio_get(dev_priv); |
d752048d VS |
1607 | |
1608 | /* Disable 10bit clock to display controller */ | |
1609 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1610 | val &= ~DPIO_DCLKP_EN; | |
1611 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1612 | ||
221c7862 | 1613 | vlv_dpio_put(dev_priv); |
f6071166 JB |
1614 | } |
1615 | ||
e4607fcf | 1616 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
7801f3b7 | 1617 | struct intel_digital_port *dig_port, |
9b6de0a1 | 1618 | unsigned int expected_mask) |
89b667f8 JB |
1619 | { |
1620 | u32 port_mask; | |
f0f59a00 | 1621 | i915_reg_t dpll_reg; |
89b667f8 | 1622 | |
7801f3b7 | 1623 | switch (dig_port->base.port) { |
e4607fcf | 1624 | case PORT_B: |
89b667f8 | 1625 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1626 | dpll_reg = DPLL(0); |
e4607fcf CML |
1627 | break; |
1628 | case PORT_C: | |
89b667f8 | 1629 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1630 | dpll_reg = DPLL(0); |
9b6de0a1 | 1631 | expected_mask <<= 4; |
00fc31b7 CML |
1632 | break; |
1633 | case PORT_D: | |
1634 | port_mask = DPLL_PORTD_READY_MASK; | |
1635 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1636 | break; |
1637 | default: | |
1638 | BUG(); | |
1639 | } | |
89b667f8 | 1640 | |
4cb3b44d DCS |
1641 | if (intel_de_wait_for_register(dev_priv, dpll_reg, |
1642 | port_mask, expected_mask, 1000)) | |
e57291c2 PB |
1643 | drm_WARN(&dev_priv->drm, 1, |
1644 | "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", | |
7801f3b7 | 1645 | dig_port->base.base.base.id, dig_port->base.base.name, |
e57291c2 PB |
1646 | intel_de_read(dev_priv, dpll_reg) & port_mask, |
1647 | expected_mask); | |
89b667f8 JB |
1648 | } |
1649 | ||
9eae5e27 | 1650 | static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) |
040484af | 1651 | { |
2225f3c6 | 1652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7efd90fb ML |
1653 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1654 | enum pipe pipe = crtc->pipe; | |
f0f59a00 | 1655 | i915_reg_t reg; |
ba3f4d0a | 1656 | u32 val, pipeconf_val; |
040484af | 1657 | |
040484af | 1658 | /* Make sure PCH DPLL is enabled */ |
7efd90fb | 1659 | assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); |
040484af JB |
1660 | |
1661 | /* FDI must be feeding us bits for PCH ports */ | |
1662 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1663 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1664 | ||
6e266956 | 1665 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 | 1666 | reg = TRANS_CHICKEN2(pipe); |
dc008bf0 | 1667 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
1668 | /* |
1669 | * Workaround: Set the timing override bit | |
1670 | * before enabling the pch transcoder. | |
1671 | */ | |
23670b32 | 1672 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
cc7a4cff VS |
1673 | /* Configure frame start delay to match the CPU */ |
1674 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; | |
1675 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 1676 | intel_de_write(dev_priv, reg, val); |
59c859d6 | 1677 | } |
23670b32 | 1678 | |
ab9412ba | 1679 | reg = PCH_TRANSCONF(pipe); |
dc008bf0 JN |
1680 | val = intel_de_read(dev_priv, reg); |
1681 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); | |
e9bcff5c | 1682 | |
2d1fe073 | 1683 | if (HAS_PCH_IBX(dev_priv)) { |
cc7a4cff VS |
1684 | /* Configure frame start delay to match the CPU */ |
1685 | val &= ~TRANS_FRAME_START_DELAY_MASK; | |
1686 | val |= TRANS_FRAME_START_DELAY(0); | |
1687 | ||
e9bcff5c | 1688 | /* |
c5de7c6f VS |
1689 | * Make the BPC in transcoder be consistent with |
1690 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1691 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1692 | */ |
dfd07d72 | 1693 | val &= ~PIPECONF_BPC_MASK; |
7efd90fb | 1694 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1695 | val |= PIPECONF_8BPC; |
1696 | else | |
1697 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1698 | } |
5f7f726d PZ |
1699 | |
1700 | val &= ~TRANS_INTERLACE_MASK; | |
27b680f9 | 1701 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) { |
2d1fe073 | 1702 | if (HAS_PCH_IBX(dev_priv) && |
7efd90fb | 1703 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1704 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1705 | else | |
1706 | val |= TRANS_INTERLACED; | |
27b680f9 | 1707 | } else { |
5f7f726d | 1708 | val |= TRANS_PROGRESSIVE; |
27b680f9 | 1709 | } |
5f7f726d | 1710 | |
dc008bf0 | 1711 | intel_de_write(dev_priv, reg, val | TRANS_ENABLE); |
4cb3b44d | 1712 | if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) |
cd49f818 WK |
1713 | drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", |
1714 | pipe_name(pipe)); | |
040484af JB |
1715 | } |
1716 | ||
8fb033d7 | 1717 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1718 | enum transcoder cpu_transcoder) |
040484af | 1719 | { |
8fb033d7 | 1720 | u32 val, pipeconf_val; |
8fb033d7 | 1721 | |
8fb033d7 | 1722 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1723 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1724 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1725 | |
dc008bf0 | 1726 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); |
cc7a4cff | 1727 | /* Workaround: set timing override bit. */ |
23670b32 | 1728 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
cc7a4cff VS |
1729 | /* Configure frame start delay to match the CPU */ |
1730 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; | |
1731 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 1732 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1733 | |
25f3ef11 | 1734 | val = TRANS_ENABLE; |
dc008bf0 | 1735 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); |
8fb033d7 | 1736 | |
9a76b1c6 PZ |
1737 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1738 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1739 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1740 | else |
1741 | val |= TRANS_PROGRESSIVE; | |
1742 | ||
dc008bf0 | 1743 | intel_de_write(dev_priv, LPT_TRANSCONF, val); |
4cb3b44d DCS |
1744 | if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, |
1745 | TRANS_STATE_ENABLE, 100)) | |
cd49f818 | 1746 | drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1747 | } |
1748 | ||
9eae5e27 LDM |
1749 | static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1750 | enum pipe pipe) | |
040484af | 1751 | { |
f0f59a00 | 1752 | i915_reg_t reg; |
ba3f4d0a | 1753 | u32 val; |
040484af JB |
1754 | |
1755 | /* FDI relies on the transcoder */ | |
1756 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1757 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1758 | ||
291906f1 JB |
1759 | /* Ports must be off as well */ |
1760 | assert_pch_ports_disabled(dev_priv, pipe); | |
1761 | ||
ab9412ba | 1762 | reg = PCH_TRANSCONF(pipe); |
dc008bf0 | 1763 | val = intel_de_read(dev_priv, reg); |
040484af | 1764 | val &= ~TRANS_ENABLE; |
dc008bf0 | 1765 | intel_de_write(dev_priv, reg, val); |
040484af | 1766 | /* wait for PCH transcoder off, transcoder state */ |
4cb3b44d | 1767 | if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) |
cd49f818 WK |
1768 | drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", |
1769 | pipe_name(pipe)); | |
23670b32 | 1770 | |
6e266956 | 1771 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1772 | /* Workaround: Clear the timing override chicken bit again. */ |
1773 | reg = TRANS_CHICKEN2(pipe); | |
dc008bf0 | 1774 | val = intel_de_read(dev_priv, reg); |
23670b32 | 1775 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
dc008bf0 | 1776 | intel_de_write(dev_priv, reg, val); |
23670b32 | 1777 | } |
040484af JB |
1778 | } |
1779 | ||
b7076546 | 1780 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1781 | { |
8fb033d7 PZ |
1782 | u32 val; |
1783 | ||
dc008bf0 | 1784 | val = intel_de_read(dev_priv, LPT_TRANSCONF); |
8fb033d7 | 1785 | val &= ~TRANS_ENABLE; |
dc008bf0 | 1786 | intel_de_write(dev_priv, LPT_TRANSCONF, val); |
8fb033d7 | 1787 | /* wait for PCH transcoder off, transcoder state */ |
4cb3b44d DCS |
1788 | if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, |
1789 | TRANS_STATE_ENABLE, 50)) | |
cd49f818 | 1790 | drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1791 | |
1792 | /* Workaround: clear timing override bit. */ | |
dc008bf0 | 1793 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1794 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
dc008bf0 | 1795 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1796 | } |
1797 | ||
a2196033 | 1798 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1799 | { |
1800 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1801 | ||
65f2130c | 1802 | if (HAS_PCH_LPT(dev_priv)) |
a2196033 | 1803 | return PIPE_A; |
65f2130c | 1804 | else |
a2196033 | 1805 | return crtc->pipe; |
65f2130c VS |
1806 | } |
1807 | ||
32db0b65 VS |
1808 | static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) |
1809 | { | |
2225f3c6 | 1810 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
32db0b65 VS |
1811 | |
1812 | /* | |
1813 | * On i965gm the hardware frame counter reads | |
1814 | * zero when the TV encoder is enabled :( | |
1815 | */ | |
1816 | if (IS_I965GM(dev_priv) && | |
1817 | (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) | |
1818 | return 0; | |
1819 | ||
1820 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
1821 | return 0xffffffff; /* full 32 bit counter */ | |
1822 | else if (INTEL_GEN(dev_priv) >= 3) | |
1823 | return 0xffffff; /* only 24 bits of frame count */ | |
1824 | else | |
1825 | return 0; /* Gen2 doesn't have a hardware frame counter */ | |
1826 | } | |
1827 | ||
21fd23ac | 1828 | void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) |
32db0b65 | 1829 | { |
2225f3c6 | 1830 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
32db0b65 | 1831 | |
407b9405 | 1832 | assert_vblank_disabled(&crtc->base); |
32db0b65 VS |
1833 | drm_crtc_set_max_vblank_count(&crtc->base, |
1834 | intel_crtc_max_vblank_count(crtc_state)); | |
1835 | drm_crtc_vblank_on(&crtc->base); | |
1836 | } | |
1837 | ||
773b4b54 | 1838 | void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) |
d18b6bb8 | 1839 | { |
f5271ee5 VS |
1840 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1841 | ||
d18b6bb8 VS |
1842 | drm_crtc_vblank_off(&crtc->base); |
1843 | assert_vblank_disabled(&crtc->base); | |
1844 | } | |
1845 | ||
21fd23ac | 1846 | void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) |
b24e7179 | 1847 | { |
2225f3c6 | 1848 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
4972f70a VS |
1849 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1850 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; | |
0372264a | 1851 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1852 | i915_reg_t reg; |
b24e7179 JB |
1853 | u32 val; |
1854 | ||
cd49f818 | 1855 | drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); |
9e2ee2dd | 1856 | |
51f5a096 | 1857 | assert_planes_disabled(crtc); |
58c6eaa2 | 1858 | |
b24e7179 JB |
1859 | /* |
1860 | * A pipe without a PLL won't actually be able to drive bits from | |
1861 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1862 | * need the check. | |
1863 | */ | |
b2ae318a | 1864 | if (HAS_GMCH(dev_priv)) { |
4972f70a | 1865 | if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1866 | assert_dsi_pll_enabled(dev_priv); |
1867 | else | |
1868 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1869 | } else { |
4972f70a | 1870 | if (new_crtc_state->has_pch_encoder) { |
040484af | 1871 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1872 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1873 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1874 | assert_fdi_tx_pll_enabled(dev_priv, |
1875 | (enum pipe) cpu_transcoder); | |
040484af JB |
1876 | } |
1877 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1878 | } | |
b24e7179 | 1879 | |
4c888e7b | 1880 | trace_intel_pipe_enable(crtc); |
0b2599a4 | 1881 | |
702e7a56 | 1882 | reg = PIPECONF(cpu_transcoder); |
dc008bf0 | 1883 | val = intel_de_read(dev_priv, reg); |
7ad25d48 | 1884 | if (val & PIPECONF_ENABLE) { |
e56134bc | 1885 | /* we keep both pipes enabled on 830 */ |
e57291c2 | 1886 | drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); |
00d70b15 | 1887 | return; |
7ad25d48 | 1888 | } |
00d70b15 | 1889 | |
dc008bf0 JN |
1890 | intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); |
1891 | intel_de_posting_read(dev_priv, reg); | |
b7792d8b VS |
1892 | |
1893 | /* | |
8fedd64d VS |
1894 | * Until the pipe starts PIPEDSL reads will return a stale value, |
1895 | * which causes an apparent vblank timestamp jump when PIPEDSL | |
1896 | * resets to its proper value. That also messes up the frame count | |
1897 | * when it's derived from the timestamps. So let's wait for the | |
1898 | * pipe to start properly before we call drm_crtc_vblank_on() | |
b7792d8b | 1899 | */ |
32db0b65 | 1900 | if (intel_crtc_max_vblank_count(new_crtc_state) == 0) |
8fedd64d | 1901 | intel_wait_for_pipe_scanline_moving(crtc); |
b24e7179 JB |
1902 | } |
1903 | ||
773b4b54 | 1904 | void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) |
b24e7179 | 1905 | { |
2225f3c6 | 1906 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
fac5e23e | 1907 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4972f70a | 1908 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
575f7ab7 | 1909 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1910 | i915_reg_t reg; |
b24e7179 JB |
1911 | u32 val; |
1912 | ||
cd49f818 | 1913 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); |
9e2ee2dd | 1914 | |
b24e7179 JB |
1915 | /* |
1916 | * Make sure planes won't keep trying to pump pixels to us, | |
1917 | * or we might hang the display. | |
1918 | */ | |
51f5a096 | 1919 | assert_planes_disabled(crtc); |
b24e7179 | 1920 | |
4c888e7b | 1921 | trace_intel_pipe_disable(crtc); |
0b2599a4 | 1922 | |
702e7a56 | 1923 | reg = PIPECONF(cpu_transcoder); |
dc008bf0 | 1924 | val = intel_de_read(dev_priv, reg); |
00d70b15 CW |
1925 | if ((val & PIPECONF_ENABLE) == 0) |
1926 | return; | |
1927 | ||
67adc644 VS |
1928 | /* |
1929 | * Double wide has implications for planes | |
1930 | * so best keep it disabled when not needed. | |
1931 | */ | |
4972f70a | 1932 | if (old_crtc_state->double_wide) |
67adc644 VS |
1933 | val &= ~PIPECONF_DOUBLE_WIDE; |
1934 | ||
1935 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1936 | if (!IS_I830(dev_priv)) |
67adc644 VS |
1937 | val &= ~PIPECONF_ENABLE; |
1938 | ||
dc008bf0 | 1939 | intel_de_write(dev_priv, reg, val); |
67adc644 | 1940 | if ((val & PIPECONF_ENABLE) == 0) |
4972f70a | 1941 | intel_wait_for_pipe_off(old_crtc_state); |
b24e7179 JB |
1942 | } |
1943 | ||
832be82f VS |
1944 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1945 | { | |
cf819eff | 1946 | return IS_GEN(dev_priv, 2) ? 2048 : 4096; |
832be82f VS |
1947 | } |
1948 | ||
e7af9094 ID |
1949 | static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) |
1950 | { | |
1951 | if (!is_ccs_modifier(fb->modifier)) | |
1952 | return false; | |
1953 | ||
1954 | return plane >= fb->format->num_planes / 2; | |
1955 | } | |
1956 | ||
b3e57bcc DP |
1957 | static bool is_gen12_ccs_modifier(u64 modifier) |
1958 | { | |
2dfbf9d2 DP |
1959 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || |
1960 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; | |
1961 | ||
b3e57bcc DP |
1962 | } |
1963 | ||
1964 | static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) | |
1965 | { | |
1966 | return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); | |
1967 | } | |
1968 | ||
e7af9094 ID |
1969 | static bool is_aux_plane(const struct drm_framebuffer *fb, int plane) |
1970 | { | |
1971 | if (is_ccs_modifier(fb->modifier)) | |
1972 | return is_ccs_plane(fb, plane); | |
1973 | ||
1974 | return plane == 1; | |
1975 | } | |
1976 | ||
1977 | static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) | |
1978 | { | |
ce04ecd9 PB |
1979 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || |
1980 | (main_plane && main_plane >= fb->format->num_planes / 2)); | |
e7af9094 ID |
1981 | |
1982 | return fb->format->num_planes / 2 + main_plane; | |
1983 | } | |
1984 | ||
b3e57bcc DP |
1985 | static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) |
1986 | { | |
ce04ecd9 PB |
1987 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || |
1988 | ccs_plane < fb->format->num_planes / 2); | |
b3e57bcc DP |
1989 | |
1990 | return ccs_plane - fb->format->num_planes / 2; | |
1991 | } | |
1992 | ||
e7af9094 | 1993 | /* Return either the main plane's CCS or - if not a CCS FB - UV plane */ |
2dfbf9d2 | 1994 | int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) |
e7af9094 ID |
1995 | { |
1996 | if (is_ccs_modifier(fb->modifier)) | |
1997 | return main_to_ccs_plane(fb, main_plane); | |
1998 | ||
1999 | return 1; | |
2000 | } | |
2001 | ||
4941f35b ID |
2002 | bool |
2003 | intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, | |
2004 | uint64_t modifier) | |
2005 | { | |
2006 | return info->is_yuv && | |
2007 | info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2); | |
2008 | } | |
2009 | ||
d156135e ID |
2010 | static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, |
2011 | int color_plane) | |
2012 | { | |
2013 | return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && | |
2014 | color_plane == 1; | |
2015 | } | |
2016 | ||
d88c4afd | 2017 | static unsigned int |
5d2a1950 | 2018 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) |
7b49f948 | 2019 | { |
d88c4afd | 2020 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
5d2a1950 | 2021 | unsigned int cpp = fb->format->cpp[color_plane]; |
d88c4afd VS |
2022 | |
2023 | switch (fb->modifier) { | |
2f075565 | 2024 | case DRM_FORMAT_MOD_LINEAR: |
54d4d719 | 2025 | return intel_tile_size(dev_priv); |
7b49f948 | 2026 | case I915_FORMAT_MOD_X_TILED: |
cf819eff | 2027 | if (IS_GEN(dev_priv, 2)) |
7b49f948 VS |
2028 | return 128; |
2029 | else | |
2030 | return 512; | |
2e2adb05 | 2031 | case I915_FORMAT_MOD_Y_TILED_CCS: |
e7af9094 | 2032 | if (is_ccs_plane(fb, color_plane)) |
2e2adb05 | 2033 | return 128; |
df561f66 | 2034 | fallthrough; |
b3e57bcc | 2035 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2dfbf9d2 | 2036 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
b3e57bcc DP |
2037 | if (is_ccs_plane(fb, color_plane)) |
2038 | return 64; | |
df561f66 | 2039 | fallthrough; |
7b49f948 | 2040 | case I915_FORMAT_MOD_Y_TILED: |
cf819eff | 2041 | if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) |
7b49f948 VS |
2042 | return 128; |
2043 | else | |
2044 | return 512; | |
2e2adb05 | 2045 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
e7af9094 | 2046 | if (is_ccs_plane(fb, color_plane)) |
2e2adb05 | 2047 | return 128; |
df561f66 | 2048 | fallthrough; |
7b49f948 VS |
2049 | case I915_FORMAT_MOD_Yf_TILED: |
2050 | switch (cpp) { | |
2051 | case 1: | |
2052 | return 64; | |
2053 | case 2: | |
2054 | case 4: | |
2055 | return 128; | |
2056 | case 8: | |
2057 | case 16: | |
2058 | return 256; | |
2059 | default: | |
2060 | MISSING_CASE(cpp); | |
2061 | return cpp; | |
2062 | } | |
2063 | break; | |
2064 | default: | |
d88c4afd | 2065 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2066 | return cpp; |
2067 | } | |
2068 | } | |
2069 | ||
d88c4afd | 2070 | static unsigned int |
5d2a1950 | 2071 | intel_tile_height(const struct drm_framebuffer *fb, int color_plane) |
a57ce0b2 | 2072 | { |
b3e57bcc DP |
2073 | if (is_gen12_ccs_plane(fb, color_plane)) |
2074 | return 1; | |
2075 | ||
54d4d719 VS |
2076 | return intel_tile_size(to_i915(fb->dev)) / |
2077 | intel_tile_width_bytes(fb, color_plane); | |
6761dd31 TU |
2078 | } |
2079 | ||
8d0deca8 | 2080 | /* Return the tile dimensions in pixel units */ |
5d2a1950 | 2081 | static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, |
8d0deca8 | 2082 | unsigned int *tile_width, |
d88c4afd | 2083 | unsigned int *tile_height) |
8d0deca8 | 2084 | { |
5d2a1950 VS |
2085 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); |
2086 | unsigned int cpp = fb->format->cpp[color_plane]; | |
8d0deca8 VS |
2087 | |
2088 | *tile_width = tile_width_bytes / cpp; | |
021a4116 | 2089 | *tile_height = intel_tile_height(fb, color_plane); |
8d0deca8 VS |
2090 | } |
2091 | ||
d156135e ID |
2092 | static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, |
2093 | int color_plane) | |
2094 | { | |
2095 | unsigned int tile_width, tile_height; | |
2096 | ||
2097 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); | |
2098 | ||
2099 | return fb->pitches[color_plane] * tile_height; | |
2100 | } | |
2101 | ||
6761dd31 | 2102 | unsigned int |
d88c4afd | 2103 | intel_fb_align_height(const struct drm_framebuffer *fb, |
5d2a1950 | 2104 | int color_plane, unsigned int height) |
6761dd31 | 2105 | { |
5d2a1950 | 2106 | unsigned int tile_height = intel_tile_height(fb, color_plane); |
832be82f VS |
2107 | |
2108 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2109 | } |
2110 | ||
1663b9d6 VS |
2111 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2112 | { | |
2113 | unsigned int size = 0; | |
2114 | int i; | |
2115 | ||
2116 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2117 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2118 | ||
2119 | return size; | |
2120 | } | |
2121 | ||
1a74fc0b VS |
2122 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) |
2123 | { | |
2124 | unsigned int size = 0; | |
2125 | int i; | |
2126 | ||
2127 | for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) | |
2128 | size += rem_info->plane[i].width * rem_info->plane[i].height; | |
2129 | ||
2130 | return size; | |
2131 | } | |
2132 | ||
75c82a53 | 2133 | static void |
3465c580 VS |
2134 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2135 | const struct drm_framebuffer *fb, | |
2136 | unsigned int rotation) | |
f64b98cd | 2137 | { |
7b92c047 | 2138 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2139 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2140 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2141 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2142 | } |
2143 | } | |
50470bb0 | 2144 | |
fabac484 VS |
2145 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2146 | { | |
2147 | if (IS_I830(dev_priv)) | |
2148 | return 16 * 1024; | |
2149 | else if (IS_I85X(dev_priv)) | |
2150 | return 256; | |
d9e1551e VS |
2151 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2152 | return 32; | |
fabac484 VS |
2153 | else |
2154 | return 4 * 1024; | |
2155 | } | |
2156 | ||
603525d7 | 2157 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 | 2158 | { |
c56b89f1 | 2159 | if (INTEL_GEN(dev_priv) >= 9) |
4e9a86b6 | 2160 | return 256 * 1024; |
c0f86832 | 2161 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2162 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 | 2163 | return 128 * 1024; |
c56b89f1 | 2164 | else if (INTEL_GEN(dev_priv) >= 4) |
4e9a86b6 VS |
2165 | return 4 * 1024; |
2166 | else | |
44c5905e | 2167 | return 0; |
4e9a86b6 VS |
2168 | } |
2169 | ||
d88c4afd | 2170 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
5d2a1950 | 2171 | int color_plane) |
603525d7 | 2172 | { |
d88c4afd VS |
2173 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2174 | ||
b90c1ee1 | 2175 | /* AUX_DIST needs only 4K alignment */ |
d156135e ID |
2176 | if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) || |
2177 | is_ccs_plane(fb, color_plane)) | |
b90c1ee1 VS |
2178 | return 4096; |
2179 | ||
d88c4afd | 2180 | switch (fb->modifier) { |
2f075565 | 2181 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2182 | return intel_linear_alignment(dev_priv); |
2183 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2184 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2185 | return 256 * 1024; |
2186 | return 0; | |
2dfbf9d2 DP |
2187 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
2188 | if (is_semiplanar_uv_plane(fb, color_plane)) | |
2189 | return intel_tile_row_size(fb, color_plane); | |
df561f66 | 2190 | fallthrough; |
b3e57bcc DP |
2191 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2192 | return 16 * 1024; | |
2e2adb05 VS |
2193 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2194 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 | 2195 | case I915_FORMAT_MOD_Y_TILED: |
d156135e ID |
2196 | if (INTEL_GEN(dev_priv) >= 12 && |
2197 | is_semiplanar_uv_plane(fb, color_plane)) | |
2198 | return intel_tile_row_size(fb, color_plane); | |
df561f66 | 2199 | fallthrough; |
603525d7 VS |
2200 | case I915_FORMAT_MOD_Yf_TILED: |
2201 | return 1 * 1024 * 1024; | |
2202 | default: | |
d88c4afd | 2203 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2204 | return 0; |
2205 | } | |
2206 | } | |
2207 | ||
f7a02ad7 VS |
2208 | static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) |
2209 | { | |
f90a85e7 | 2210 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
f7a02ad7 VS |
2211 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2212 | ||
bb211c3d VS |
2213 | return INTEL_GEN(dev_priv) < 4 || |
2214 | (plane->has_fbc && | |
2215 | plane_state->view.type == I915_GGTT_VIEW_NORMAL); | |
f7a02ad7 VS |
2216 | } |
2217 | ||
058d88c4 | 2218 | struct i915_vma * |
5935485f | 2219 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
f5929c53 | 2220 | const struct i915_ggtt_view *view, |
f7a02ad7 | 2221 | bool uses_fence, |
5935485f | 2222 | unsigned long *out_flags) |
6b95a207 | 2223 | { |
850c4cdc | 2224 | struct drm_device *dev = fb->dev; |
fac5e23e | 2225 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2226 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1d264d91 | 2227 | intel_wakeref_t wakeref; |
058d88c4 | 2228 | struct i915_vma *vma; |
5935485f | 2229 | unsigned int pinctl; |
6b95a207 | 2230 | u32 alignment; |
6b95a207 | 2231 | |
e57291c2 | 2232 | if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) |
5a90606d | 2233 | return ERR_PTR(-EINVAL); |
ebcdd39e | 2234 | |
d88c4afd | 2235 | alignment = intel_surf_alignment(fb, 0); |
e57291c2 | 2236 | if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) |
7361bdb2 | 2237 | return ERR_PTR(-EINVAL); |
6b95a207 | 2238 | |
693db184 CW |
2239 | /* Note that the w/a also requires 64 PTE of padding following the |
2240 | * bo. We currently fill all unused PTE with the shadow page and so | |
2241 | * we should always have valid PTE following the scanout preventing | |
2242 | * the VT-d warning. | |
2243 | */ | |
48f112fe | 2244 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2245 | alignment = 256 * 1024; |
2246 | ||
d6dd6843 PZ |
2247 | /* |
2248 | * Global gtt pte registers are special registers which actually forward | |
2249 | * writes to a chunk of system memory. Which means that there is no risk | |
2250 | * that the register values disappear as soon as we call | |
2251 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2252 | * pin/unpin/fence and not more. | |
2253 | */ | |
d858d569 | 2254 | wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
d6dd6843 | 2255 | |
9db529aa DV |
2256 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
2257 | ||
8b1c78e0 CW |
2258 | /* |
2259 | * Valleyview is definitely limited to scanning out the first | |
5935485f CW |
2260 | * 512MiB. Lets presume this behaviour was inherited from the |
2261 | * g4x display engine and that all earlier gen are similarly | |
2262 | * limited. Testing suggests that it is a little more | |
2263 | * complicated than this. For example, Cherryview appears quite | |
2264 | * happy to scanout from anywhere within its global aperture. | |
2265 | */ | |
8b1c78e0 | 2266 | pinctl = 0; |
b2ae318a | 2267 | if (HAS_GMCH(dev_priv)) |
5935485f CW |
2268 | pinctl |= PIN_MAPPABLE; |
2269 | ||
2270 | vma = i915_gem_object_pin_to_display_plane(obj, | |
f5929c53 | 2271 | alignment, view, pinctl); |
49ef5294 CW |
2272 | if (IS_ERR(vma)) |
2273 | goto err; | |
6b95a207 | 2274 | |
f7a02ad7 | 2275 | if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { |
85798ac9 VS |
2276 | int ret; |
2277 | ||
8b1c78e0 CW |
2278 | /* |
2279 | * Install a fence for tiled scan-out. Pre-i965 always needs a | |
49ef5294 CW |
2280 | * fence, whereas 965+ only requires a fence if using |
2281 | * framebuffer compression. For simplicity, we always, when | |
2282 | * possible, install a fence as the cost is not that onerous. | |
2283 | * | |
2284 | * If we fail to fence the tiled scanout, then either the | |
2285 | * modeset will reject the change (which is highly unlikely as | |
2286 | * the affected systems, all but one, do not have unmappable | |
2287 | * space) or we will not be able to enable full powersaving | |
2288 | * techniques (also likely not to apply due to various limits | |
2289 | * FBC and the like impose on the size of the buffer, which | |
2290 | * presumably we violated anyway with this unmappable buffer). | |
2291 | * Anyway, it is presumably better to stumble onwards with | |
2292 | * something and try to run the system in a "less than optimal" | |
2293 | * mode that matches the user configuration. | |
2294 | */ | |
85798ac9 VS |
2295 | ret = i915_vma_pin_fence(vma); |
2296 | if (ret != 0 && INTEL_GEN(dev_priv) < 4) { | |
7509702b | 2297 | i915_gem_object_unpin_from_display_plane(vma); |
85798ac9 VS |
2298 | vma = ERR_PTR(ret); |
2299 | goto err; | |
2300 | } | |
2301 | ||
2302 | if (ret == 0 && vma->fence) | |
5935485f | 2303 | *out_flags |= PLANE_HAS_FENCE; |
9807216f | 2304 | } |
6b95a207 | 2305 | |
be1e3415 | 2306 | i915_vma_get(vma); |
49ef5294 | 2307 | err: |
9db529aa | 2308 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); |
d858d569 | 2309 | intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); |
058d88c4 | 2310 | return vma; |
6b95a207 KH |
2311 | } |
2312 | ||
5935485f | 2313 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) |
1690e1eb | 2314 | { |
80f0b679 | 2315 | i915_gem_object_lock(vma->obj, NULL); |
5935485f CW |
2316 | if (flags & PLANE_HAS_FENCE) |
2317 | i915_vma_unpin_fence(vma); | |
058d88c4 | 2318 | i915_gem_object_unpin_from_display_plane(vma); |
6951e589 CW |
2319 | i915_gem_object_unlock(vma->obj); |
2320 | ||
be1e3415 | 2321 | i915_vma_put(vma); |
1690e1eb CW |
2322 | } |
2323 | ||
5d2a1950 | 2324 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane, |
ef78ec94 VS |
2325 | unsigned int rotation) |
2326 | { | |
bd2ef25d | 2327 | if (drm_rotation_90_or_270(rotation)) |
5d2a1950 | 2328 | return to_intel_framebuffer(fb)->rotated[color_plane].pitch; |
ef78ec94 | 2329 | else |
5d2a1950 | 2330 | return fb->pitches[color_plane]; |
ef78ec94 VS |
2331 | } |
2332 | ||
6687c906 VS |
2333 | /* |
2334 | * Convert the x/y offsets into a linear offset. | |
2335 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2336 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2337 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2338 | */ | |
2339 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c | 2340 | const struct intel_plane_state *state, |
5d2a1950 | 2341 | int color_plane) |
6687c906 | 2342 | { |
7b3cb17a | 2343 | const struct drm_framebuffer *fb = state->hw.fb; |
5d2a1950 VS |
2344 | unsigned int cpp = fb->format->cpp[color_plane]; |
2345 | unsigned int pitch = state->color_plane[color_plane].stride; | |
6687c906 VS |
2346 | |
2347 | return y * pitch + x * cpp; | |
2348 | } | |
2349 | ||
2350 | /* | |
2351 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2352 | * specified plane src x/y offsets. The resulting x/y offsets | |
2353 | * specify the start of scanout from the beginning of the gtt mapping. | |
2354 | */ | |
2355 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c | 2356 | const struct intel_plane_state *state, |
5d2a1950 | 2357 | int color_plane) |
6687c906 VS |
2358 | |
2359 | { | |
54d4d719 VS |
2360 | *x += state->color_plane[color_plane].x; |
2361 | *y += state->color_plane[color_plane].y; | |
6687c906 VS |
2362 | } |
2363 | ||
6d19a44c VS |
2364 | static u32 intel_adjust_tile_offset(int *x, int *y, |
2365 | unsigned int tile_width, | |
2366 | unsigned int tile_height, | |
2367 | unsigned int tile_size, | |
2368 | unsigned int pitch_tiles, | |
2369 | u32 old_offset, | |
2370 | u32 new_offset) | |
29cf9491 | 2371 | { |
b9b24038 | 2372 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2373 | unsigned int tiles; |
2374 | ||
2375 | WARN_ON(old_offset & (tile_size - 1)); | |
2376 | WARN_ON(new_offset & (tile_size - 1)); | |
2377 | WARN_ON(new_offset > old_offset); | |
2378 | ||
2379 | tiles = (old_offset - new_offset) / tile_size; | |
2380 | ||
2381 | *y += tiles / pitch_tiles * tile_height; | |
2382 | *x += tiles % pitch_tiles * tile_width; | |
2383 | ||
b9b24038 VS |
2384 | /* minimize x in case it got needlessly big */ |
2385 | *y += *x / pitch_pixels * tile_height; | |
2386 | *x %= pitch_pixels; | |
2387 | ||
29cf9491 VS |
2388 | return new_offset; |
2389 | } | |
2390 | ||
b3e57bcc | 2391 | static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) |
2a11b1b4 | 2392 | { |
b3e57bcc DP |
2393 | return fb->modifier == DRM_FORMAT_MOD_LINEAR || |
2394 | is_gen12_ccs_plane(fb, color_plane); | |
2a11b1b4 DP |
2395 | } |
2396 | ||
6d19a44c | 2397 | static u32 intel_adjust_aligned_offset(int *x, int *y, |
5d2a1950 VS |
2398 | const struct drm_framebuffer *fb, |
2399 | int color_plane, | |
6d19a44c | 2400 | unsigned int rotation, |
df79cf44 | 2401 | unsigned int pitch, |
6d19a44c | 2402 | u32 old_offset, u32 new_offset) |
66a2d927 | 2403 | { |
6d19a44c | 2404 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
5d2a1950 | 2405 | unsigned int cpp = fb->format->cpp[color_plane]; |
66a2d927 | 2406 | |
e57291c2 | 2407 | drm_WARN_ON(&dev_priv->drm, new_offset > old_offset); |
66a2d927 | 2408 | |
b3e57bcc | 2409 | if (!is_surface_linear(fb, color_plane)) { |
66a2d927 VS |
2410 | unsigned int tile_size, tile_width, tile_height; |
2411 | unsigned int pitch_tiles; | |
2412 | ||
2413 | tile_size = intel_tile_size(dev_priv); | |
5d2a1950 | 2414 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
66a2d927 | 2415 | |
bd2ef25d | 2416 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2417 | pitch_tiles = pitch / tile_height; |
2418 | swap(tile_width, tile_height); | |
2419 | } else { | |
2420 | pitch_tiles = pitch / (tile_width * cpp); | |
2421 | } | |
2422 | ||
6d19a44c VS |
2423 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2424 | tile_size, pitch_tiles, | |
2425 | old_offset, new_offset); | |
66a2d927 VS |
2426 | } else { |
2427 | old_offset += *y * pitch + *x * cpp; | |
2428 | ||
2429 | *y = (old_offset - new_offset) / pitch; | |
2430 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2431 | } | |
2432 | ||
2433 | return new_offset; | |
2434 | } | |
2435 | ||
303ba695 VS |
2436 | /* |
2437 | * Adjust the tile offset by moving the difference into | |
2438 | * the x/y offsets. | |
2439 | */ | |
6d19a44c VS |
2440 | static u32 intel_plane_adjust_aligned_offset(int *x, int *y, |
2441 | const struct intel_plane_state *state, | |
5d2a1950 | 2442 | int color_plane, |
6d19a44c | 2443 | u32 old_offset, u32 new_offset) |
303ba695 | 2444 | { |
7b3cb17a ML |
2445 | return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, |
2446 | state->hw.rotation, | |
5d2a1950 | 2447 | state->color_plane[color_plane].stride, |
6d19a44c | 2448 | old_offset, new_offset); |
303ba695 VS |
2449 | } |
2450 | ||
8d0deca8 | 2451 | /* |
6d19a44c | 2452 | * Computes the aligned offset to the base tile and adjusts |
8d0deca8 VS |
2453 | * x, y. bytes per pixel is assumed to be a power-of-two. |
2454 | * | |
2455 | * In the 90/270 rotated case, x and y are assumed | |
2456 | * to be already rotated to match the rotated GTT view, and | |
2457 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2458 | * |
2459 | * This function is used when computing the derived information | |
2460 | * under intel_framebuffer, so using any of that information | |
2461 | * here is not allowed. Anything under drm_framebuffer can be | |
2462 | * used. This is why the user has to pass in the pitch since it | |
2463 | * is specified in the rotated orientation. | |
8d0deca8 | 2464 | */ |
6d19a44c VS |
2465 | static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv, |
2466 | int *x, int *y, | |
5d2a1950 VS |
2467 | const struct drm_framebuffer *fb, |
2468 | int color_plane, | |
6d19a44c VS |
2469 | unsigned int pitch, |
2470 | unsigned int rotation, | |
2471 | u32 alignment) | |
c2c75131 | 2472 | { |
5d2a1950 | 2473 | unsigned int cpp = fb->format->cpp[color_plane]; |
6687c906 | 2474 | u32 offset, offset_aligned; |
29cf9491 | 2475 | |
b3e57bcc | 2476 | if (!is_surface_linear(fb, color_plane)) { |
8d0deca8 VS |
2477 | unsigned int tile_size, tile_width, tile_height; |
2478 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2479 | |
d843310d | 2480 | tile_size = intel_tile_size(dev_priv); |
5d2a1950 | 2481 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
8d0deca8 | 2482 | |
bd2ef25d | 2483 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2484 | pitch_tiles = pitch / tile_height; |
2485 | swap(tile_width, tile_height); | |
2486 | } else { | |
2487 | pitch_tiles = pitch / (tile_width * cpp); | |
2488 | } | |
d843310d VS |
2489 | |
2490 | tile_rows = *y / tile_height; | |
2491 | *y %= tile_height; | |
c2c75131 | 2492 | |
8d0deca8 VS |
2493 | tiles = *x / tile_width; |
2494 | *x %= tile_width; | |
bc752862 | 2495 | |
29cf9491 | 2496 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
7361bdb2 ID |
2497 | |
2498 | offset_aligned = offset; | |
2499 | if (alignment) | |
2500 | offset_aligned = rounddown(offset_aligned, alignment); | |
bc752862 | 2501 | |
6d19a44c VS |
2502 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2503 | tile_size, pitch_tiles, | |
2504 | offset, offset_aligned); | |
29cf9491 | 2505 | } else { |
bc752862 | 2506 | offset = *y * pitch + *x * cpp; |
7361bdb2 ID |
2507 | offset_aligned = offset; |
2508 | if (alignment) { | |
2509 | offset_aligned = rounddown(offset_aligned, alignment); | |
2510 | *y = (offset % alignment) / pitch; | |
2511 | *x = ((offset % alignment) - *y * pitch) / cpp; | |
2512 | } else { | |
2513 | *y = *x = 0; | |
2514 | } | |
bc752862 | 2515 | } |
29cf9491 VS |
2516 | |
2517 | return offset_aligned; | |
c2c75131 DV |
2518 | } |
2519 | ||
6d19a44c VS |
2520 | static u32 intel_plane_compute_aligned_offset(int *x, int *y, |
2521 | const struct intel_plane_state *state, | |
5d2a1950 | 2522 | int color_plane) |
6687c906 | 2523 | { |
f90a85e7 | 2524 | struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); |
1e7b4fd8 | 2525 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
7b3cb17a ML |
2526 | const struct drm_framebuffer *fb = state->hw.fb; |
2527 | unsigned int rotation = state->hw.rotation; | |
5d2a1950 | 2528 | int pitch = state->color_plane[color_plane].stride; |
1e7b4fd8 VS |
2529 | u32 alignment; |
2530 | ||
2531 | if (intel_plane->id == PLANE_CURSOR) | |
2532 | alignment = intel_cursor_alignment(dev_priv); | |
2533 | else | |
5d2a1950 | 2534 | alignment = intel_surf_alignment(fb, color_plane); |
6687c906 | 2535 | |
5d2a1950 | 2536 | return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane, |
6d19a44c | 2537 | pitch, rotation, alignment); |
6687c906 VS |
2538 | } |
2539 | ||
303ba695 VS |
2540 | /* Convert the fb->offset[] into x/y offsets */ |
2541 | static int intel_fb_offset_to_xy(int *x, int *y, | |
5d2a1950 VS |
2542 | const struct drm_framebuffer *fb, |
2543 | int color_plane) | |
6687c906 | 2544 | { |
303ba695 | 2545 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
70bbe53c | 2546 | unsigned int height; |
d156135e ID |
2547 | u32 alignment; |
2548 | ||
2549 | if (INTEL_GEN(dev_priv) >= 12 && | |
2550 | is_semiplanar_uv_plane(fb, color_plane)) | |
2551 | alignment = intel_tile_row_size(fb, color_plane); | |
2552 | else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) | |
2553 | alignment = intel_tile_size(dev_priv); | |
2554 | else | |
2555 | alignment = 0; | |
6687c906 | 2556 | |
d156135e | 2557 | if (alignment != 0 && fb->offsets[color_plane] % alignment) { |
cd49f818 WK |
2558 | drm_dbg_kms(&dev_priv->drm, |
2559 | "Misaligned offset 0x%08x for color plane %d\n", | |
2560 | fb->offsets[color_plane], color_plane); | |
303ba695 | 2561 | return -EINVAL; |
70bbe53c VS |
2562 | } |
2563 | ||
2564 | height = drm_framebuffer_plane_height(fb->height, fb, color_plane); | |
2565 | height = ALIGN(height, intel_tile_height(fb, color_plane)); | |
2566 | ||
2567 | /* Catch potential overflows early */ | |
2568 | if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), | |
2569 | fb->offsets[color_plane])) { | |
cd49f818 WK |
2570 | drm_dbg_kms(&dev_priv->drm, |
2571 | "Bad offset 0x%08x or pitch %d for color plane %d\n", | |
2572 | fb->offsets[color_plane], fb->pitches[color_plane], | |
2573 | color_plane); | |
70bbe53c VS |
2574 | return -ERANGE; |
2575 | } | |
303ba695 VS |
2576 | |
2577 | *x = 0; | |
2578 | *y = 0; | |
2579 | ||
6d19a44c | 2580 | intel_adjust_aligned_offset(x, y, |
5d2a1950 VS |
2581 | fb, color_plane, DRM_MODE_ROTATE_0, |
2582 | fb->pitches[color_plane], | |
2583 | fb->offsets[color_plane], 0); | |
303ba695 VS |
2584 | |
2585 | return 0; | |
6687c906 VS |
2586 | } |
2587 | ||
ba3f4d0a | 2588 | static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) |
72618ebf VS |
2589 | { |
2590 | switch (fb_modifier) { | |
2591 | case I915_FORMAT_MOD_X_TILED: | |
2592 | return I915_TILING_X; | |
2593 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2594 | case I915_FORMAT_MOD_Y_TILED_CCS: |
b3e57bcc | 2595 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
2dfbf9d2 | 2596 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
72618ebf VS |
2597 | return I915_TILING_Y; |
2598 | default: | |
2599 | return I915_TILING_NONE; | |
2600 | } | |
2601 | } | |
2602 | ||
16af25fa VS |
2603 | /* |
2604 | * From the Sky Lake PRM: | |
2605 | * "The Color Control Surface (CCS) contains the compression status of | |
2606 | * the cache-line pairs. The compression state of the cache-line pair | |
2607 | * is specified by 2 bits in the CCS. Each CCS cache-line represents | |
2608 | * an area on the main surface of 16 x16 sets of 128 byte Y-tiled | |
2609 | * cache-line-pairs. CCS is always Y tiled." | |
2610 | * | |
2611 | * Since cache line pairs refers to horizontally adjacent cache lines, | |
2612 | * each cache line in the CCS corresponds to an area of 32x16 cache | |
2613 | * lines on the main surface. Since each pixel is 4 bytes, this gives | |
2614 | * us a ratio of one byte in the CCS for each 8x16 pixels in the | |
2615 | * main surface. | |
2616 | */ | |
b3e57bcc | 2617 | static const struct drm_format_info skl_ccs_formats[] = { |
38f30041 VS |
2618 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, |
2619 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2620 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, | |
2621 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2622 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, | |
2623 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, | |
2624 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, | |
2625 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, | |
bbfb6ce8 VS |
2626 | }; |
2627 | ||
b3e57bcc DP |
2628 | /* |
2629 | * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the | |
2630 | * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles | |
2631 | * in the main surface. With 4 byte pixels and each Y-tile having dimensions of | |
2632 | * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in | |
2633 | * the main surface. | |
2634 | */ | |
2635 | static const struct drm_format_info gen12_ccs_formats[] = { | |
2636 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, | |
2637 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2638 | .hsub = 1, .vsub = 1, }, | |
2639 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, | |
2640 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2641 | .hsub = 1, .vsub = 1, }, | |
2642 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, | |
2643 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2644 | .hsub = 1, .vsub = 1, .has_alpha = true }, | |
2645 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, | |
2646 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2647 | .hsub = 1, .vsub = 1, .has_alpha = true }, | |
2dfbf9d2 DP |
2648 | { .format = DRM_FORMAT_YUYV, .num_planes = 2, |
2649 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2650 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2651 | { .format = DRM_FORMAT_YVYU, .num_planes = 2, | |
2652 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2653 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2654 | { .format = DRM_FORMAT_UYVY, .num_planes = 2, | |
2655 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2656 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2657 | { .format = DRM_FORMAT_VYUY, .num_planes = 2, | |
2658 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, | |
2659 | .hsub = 2, .vsub = 1, .is_yuv = true }, | |
2660 | { .format = DRM_FORMAT_NV12, .num_planes = 4, | |
2661 | .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, | |
2662 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2663 | { .format = DRM_FORMAT_P010, .num_planes = 4, | |
2664 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2665 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2666 | { .format = DRM_FORMAT_P012, .num_planes = 4, | |
2667 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2668 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
2669 | { .format = DRM_FORMAT_P016, .num_planes = 4, | |
2670 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, | |
2671 | .hsub = 2, .vsub = 2, .is_yuv = true }, | |
b3e57bcc DP |
2672 | }; |
2673 | ||
bbfb6ce8 VS |
2674 | static const struct drm_format_info * |
2675 | lookup_format_info(const struct drm_format_info formats[], | |
2676 | int num_formats, u32 format) | |
2677 | { | |
2678 | int i; | |
2679 | ||
2680 | for (i = 0; i < num_formats; i++) { | |
2681 | if (formats[i].format == format) | |
2682 | return &formats[i]; | |
2683 | } | |
2684 | ||
2685 | return NULL; | |
2686 | } | |
2687 | ||
2688 | static const struct drm_format_info * | |
2689 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2690 | { | |
2691 | switch (cmd->modifier[0]) { | |
2692 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2693 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
b3e57bcc DP |
2694 | return lookup_format_info(skl_ccs_formats, |
2695 | ARRAY_SIZE(skl_ccs_formats), | |
2696 | cmd->pixel_format); | |
2697 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: | |
2dfbf9d2 | 2698 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
b3e57bcc DP |
2699 | return lookup_format_info(gen12_ccs_formats, |
2700 | ARRAY_SIZE(gen12_ccs_formats), | |
bbfb6ce8 VS |
2701 | cmd->pixel_format); |
2702 | default: | |
2703 | return NULL; | |
2704 | } | |
2705 | } | |
2706 | ||
63eaf9ac DP |
2707 | bool is_ccs_modifier(u64 modifier) |
2708 | { | |
b3e57bcc | 2709 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || |
2dfbf9d2 | 2710 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || |
b3e57bcc | 2711 | modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
63eaf9ac DP |
2712 | modifier == I915_FORMAT_MOD_Yf_TILED_CCS; |
2713 | } | |
2714 | ||
71df86f0 ID |
2715 | static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane) |
2716 | { | |
2717 | return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)], | |
2718 | 512) * 64; | |
2719 | } | |
2720 | ||
54d4d719 VS |
2721 | u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, |
2722 | u32 pixel_format, u64 modifier) | |
a88c40eb VS |
2723 | { |
2724 | struct intel_crtc *crtc; | |
2725 | struct intel_plane *plane; | |
2726 | ||
2727 | /* | |
2728 | * We assume the primary plane for pipe A has | |
eae3da27 AG |
2729 | * the highest stride limits of them all, |
2730 | * if in case pipe A is disabled, use the first pipe from pipe_mask. | |
a88c40eb | 2731 | */ |
eae3da27 | 2732 | crtc = intel_get_first_crtc(dev_priv); |
baea9ffe VS |
2733 | if (!crtc) |
2734 | return 0; | |
2735 | ||
a88c40eb VS |
2736 | plane = to_intel_plane(crtc->base.primary); |
2737 | ||
2738 | return plane->max_stride(plane, pixel_format, modifier, | |
2739 | DRM_MODE_ROTATE_0); | |
2740 | } | |
2741 | ||
54d4d719 VS |
2742 | static |
2743 | u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, | |
2744 | u32 pixel_format, u64 modifier) | |
2745 | { | |
20330129 VS |
2746 | /* |
2747 | * Arbitrary limit for gen4+ chosen to match the | |
2748 | * render engine max stride. | |
2749 | * | |
2750 | * The new CCS hash mode makes remapping impossible | |
2751 | */ | |
2752 | if (!is_ccs_modifier(modifier)) { | |
2753 | if (INTEL_GEN(dev_priv) >= 7) | |
2754 | return 256*1024; | |
2755 | else if (INTEL_GEN(dev_priv) >= 4) | |
2756 | return 128*1024; | |
2757 | } | |
2758 | ||
54d4d719 VS |
2759 | return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); |
2760 | } | |
2761 | ||
a88c40eb VS |
2762 | static u32 |
2763 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) | |
2764 | { | |
54d4d719 | 2765 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
b3e57bcc | 2766 | u32 tile_width; |
54d4d719 | 2767 | |
b3e57bcc | 2768 | if (is_surface_linear(fb, color_plane)) { |
54d4d719 VS |
2769 | u32 max_stride = intel_plane_fb_max_stride(dev_priv, |
2770 | fb->format->format, | |
2771 | fb->modifier); | |
2772 | ||
2773 | /* | |
2774 | * To make remapping with linear generally feasible | |
2775 | * we need the stride to be page aligned. | |
2776 | */ | |
b3e57bcc DP |
2777 | if (fb->pitches[color_plane] > max_stride && |
2778 | !is_ccs_modifier(fb->modifier)) | |
54d4d719 VS |
2779 | return intel_tile_size(dev_priv); |
2780 | else | |
2781 | return 64; | |
b3e57bcc | 2782 | } |
86f236bb | 2783 | |
b3e57bcc | 2784 | tile_width = intel_tile_width_bytes(fb, color_plane); |
2dfbf9d2 | 2785 | if (is_ccs_modifier(fb->modifier)) { |
86f236bb DP |
2786 | /* |
2787 | * Display WA #0531: skl,bxt,kbl,glk | |
2788 | * | |
2789 | * Render decompression and plane width > 3840 | |
2790 | * combined with horizontal panning requires the | |
2791 | * plane stride to be a multiple of 4. We'll just | |
2792 | * require the entire fb to accommodate that to avoid | |
2793 | * potential runtime errors at plane configuration time. | |
2794 | */ | |
2dfbf9d2 | 2795 | if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840) |
b3e57bcc DP |
2796 | tile_width *= 4; |
2797 | /* | |
2798 | * The main surface pitch must be padded to a multiple of four | |
2799 | * tile widths. | |
2800 | */ | |
2801 | else if (INTEL_GEN(dev_priv) >= 12) | |
86f236bb | 2802 | tile_width *= 4; |
54d4d719 | 2803 | } |
b3e57bcc | 2804 | return tile_width; |
54d4d719 VS |
2805 | } |
2806 | ||
2807 | bool intel_plane_can_remap(const struct intel_plane_state *plane_state) | |
2808 | { | |
f90a85e7 | 2809 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
54d4d719 | 2810 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 2811 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
54d4d719 VS |
2812 | int i; |
2813 | ||
2814 | /* We don't want to deal with remapping with cursors */ | |
2815 | if (plane->id == PLANE_CURSOR) | |
2816 | return false; | |
2817 | ||
2818 | /* | |
2819 | * The display engine limits already match/exceed the | |
2820 | * render engine limits, so not much point in remapping. | |
2821 | * Would also need to deal with the fence POT alignment | |
2822 | * and gen2 2KiB GTT tile size. | |
2823 | */ | |
2824 | if (INTEL_GEN(dev_priv) < 4) | |
2825 | return false; | |
2826 | ||
2827 | /* | |
2828 | * The new CCS hash mode isn't compatible with remapping as | |
2829 | * the virtual address of the pages affects the compressed data. | |
2830 | */ | |
2831 | if (is_ccs_modifier(fb->modifier)) | |
2832 | return false; | |
2833 | ||
2834 | /* Linear needs a page aligned stride for remapping */ | |
2835 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { | |
2836 | unsigned int alignment = intel_tile_size(dev_priv) - 1; | |
2837 | ||
2838 | for (i = 0; i < fb->format->num_planes; i++) { | |
2839 | if (fb->pitches[i] & alignment) | |
2840 | return false; | |
2841 | } | |
2842 | } | |
2843 | ||
2844 | return true; | |
2845 | } | |
2846 | ||
2847 | static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) | |
2848 | { | |
f90a85e7 | 2849 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
7b3cb17a ML |
2850 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
2851 | unsigned int rotation = plane_state->hw.rotation; | |
54d4d719 VS |
2852 | u32 stride, max_stride; |
2853 | ||
2854 | /* | |
2855 | * No remapping for invisible planes since we don't have | |
2856 | * an actual source viewport to remap. | |
2857 | */ | |
f90a85e7 | 2858 | if (!plane_state->uapi.visible) |
54d4d719 VS |
2859 | return false; |
2860 | ||
2861 | if (!intel_plane_can_remap(plane_state)) | |
2862 | return false; | |
2863 | ||
2864 | /* | |
2865 | * FIXME: aux plane limits on gen9+ are | |
2866 | * unclear in Bspec, for now no checking. | |
2867 | */ | |
2868 | stride = intel_fb_pitch(fb, 0, rotation); | |
2869 | max_stride = plane->max_stride(plane, fb->format->format, | |
2870 | fb->modifier, rotation); | |
2871 | ||
2872 | return stride > max_stride; | |
a88c40eb VS |
2873 | } |
2874 | ||
b3e57bcc DP |
2875 | static void |
2876 | intel_fb_plane_get_subsampling(int *hsub, int *vsub, | |
2877 | const struct drm_framebuffer *fb, | |
2878 | int color_plane) | |
2879 | { | |
2880 | int main_plane; | |
2881 | ||
2882 | if (color_plane == 0) { | |
2883 | *hsub = 1; | |
2884 | *vsub = 1; | |
2885 | ||
2886 | return; | |
2887 | } | |
2888 | ||
2889 | /* | |
2890 | * TODO: Deduct the subsampling from the char block for all CCS | |
2891 | * formats and planes. | |
2892 | */ | |
2893 | if (!is_gen12_ccs_plane(fb, color_plane)) { | |
2894 | *hsub = fb->format->hsub; | |
2895 | *vsub = fb->format->vsub; | |
2896 | ||
2897 | return; | |
2898 | } | |
2899 | ||
2900 | main_plane = ccs_to_main_plane(fb, color_plane); | |
2901 | *hsub = drm_format_info_block_width(fb->format, color_plane) / | |
2902 | drm_format_info_block_width(fb->format, main_plane); | |
2903 | ||
2904 | /* | |
2905 | * The min stride check in the core framebuffer_check() function | |
2906 | * assumes that format->hsub applies to every plane except for the | |
2907 | * first plane. That's incorrect for the CCS AUX plane of the first | |
2908 | * plane, but for the above check to pass we must define the block | |
2909 | * width with that subsampling applied to it. Adjust the width here | |
2910 | * accordingly, so we can calculate the actual subsampling factor. | |
2911 | */ | |
2912 | if (main_plane == 0) | |
2913 | *hsub *= fb->format->hsub; | |
2914 | ||
2915 | *vsub = 32; | |
2916 | } | |
13f2cb9a DP |
2917 | static int |
2918 | intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y) | |
2919 | { | |
3dfd8d71 | 2920 | struct drm_i915_private *i915 = to_i915(fb->dev); |
13f2cb9a | 2921 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
b3e57bcc DP |
2922 | int main_plane; |
2923 | int hsub, vsub; | |
13f2cb9a DP |
2924 | int tile_width, tile_height; |
2925 | int ccs_x, ccs_y; | |
2926 | int main_x, main_y; | |
2927 | ||
b3e57bcc | 2928 | if (!is_ccs_plane(fb, ccs_plane)) |
13f2cb9a DP |
2929 | return 0; |
2930 | ||
b3e57bcc DP |
2931 | intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height); |
2932 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); | |
13f2cb9a DP |
2933 | |
2934 | tile_width *= hsub; | |
2935 | tile_height *= vsub; | |
2936 | ||
2937 | ccs_x = (x * hsub) % tile_width; | |
2938 | ccs_y = (y * vsub) % tile_height; | |
b3e57bcc DP |
2939 | |
2940 | main_plane = ccs_to_main_plane(fb, ccs_plane); | |
2941 | main_x = intel_fb->normal[main_plane].x % tile_width; | |
2942 | main_y = intel_fb->normal[main_plane].y % tile_height; | |
13f2cb9a DP |
2943 | |
2944 | /* | |
2945 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2946 | * x/y offsets must match between CCS and the main surface. | |
2947 | */ | |
2948 | if (main_x != ccs_x || main_y != ccs_y) { | |
3dfd8d71 JN |
2949 | drm_dbg_kms(&i915->drm, |
2950 | "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
13f2cb9a DP |
2951 | main_x, main_y, |
2952 | ccs_x, ccs_y, | |
b3e57bcc DP |
2953 | intel_fb->normal[main_plane].x, |
2954 | intel_fb->normal[main_plane].y, | |
13f2cb9a DP |
2955 | x, y); |
2956 | return -EINVAL; | |
2957 | } | |
2958 | ||
2959 | return 0; | |
2960 | } | |
2961 | ||
b3e57bcc DP |
2962 | static void |
2963 | intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane) | |
2964 | { | |
577687bf ID |
2965 | int main_plane = is_ccs_plane(fb, color_plane) ? |
2966 | ccs_to_main_plane(fb, color_plane) : 0; | |
2967 | int main_hsub, main_vsub; | |
b3e57bcc DP |
2968 | int hsub, vsub; |
2969 | ||
577687bf | 2970 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane); |
b3e57bcc | 2971 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane); |
577687bf ID |
2972 | *w = fb->width / main_hsub / hsub; |
2973 | *h = fb->height / main_vsub / vsub; | |
b3e57bcc DP |
2974 | } |
2975 | ||
931cd348 DP |
2976 | /* |
2977 | * Setup the rotated view for an FB plane and return the size the GTT mapping | |
2978 | * requires for this view. | |
2979 | */ | |
2980 | static u32 | |
2981 | setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info, | |
2982 | u32 gtt_offset_rotated, int x, int y, | |
2983 | unsigned int width, unsigned int height, | |
2984 | unsigned int tile_size, | |
2985 | unsigned int tile_width, unsigned int tile_height, | |
2986 | struct drm_framebuffer *fb) | |
2987 | { | |
2988 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2989 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2990 | unsigned int pitch_tiles; | |
2991 | struct drm_rect r; | |
2992 | ||
2993 | /* Y or Yf modifiers required for 90/270 rotation */ | |
2994 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && | |
2995 | fb->modifier != I915_FORMAT_MOD_Yf_TILED) | |
2996 | return 0; | |
2997 | ||
ce04ecd9 | 2998 | if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane))) |
931cd348 DP |
2999 | return 0; |
3000 | ||
3001 | rot_info->plane[plane] = *plane_info; | |
3002 | ||
3003 | intel_fb->rotated[plane].pitch = plane_info->height * tile_height; | |
3004 | ||
3005 | /* rotate the x/y offsets to match the GTT view */ | |
3006 | drm_rect_init(&r, x, y, width, height); | |
3007 | drm_rect_rotate(&r, | |
3008 | plane_info->width * tile_width, | |
3009 | plane_info->height * tile_height, | |
3010 | DRM_MODE_ROTATE_270); | |
3011 | x = r.x1; | |
3012 | y = r.y1; | |
3013 | ||
3014 | /* rotate the tile dimensions to match the GTT view */ | |
3015 | pitch_tiles = intel_fb->rotated[plane].pitch / tile_height; | |
3016 | swap(tile_width, tile_height); | |
3017 | ||
3018 | /* | |
3019 | * We only keep the x/y offsets, so push all of the | |
3020 | * gtt offset into the x/y offsets. | |
3021 | */ | |
3022 | intel_adjust_tile_offset(&x, &y, | |
3023 | tile_width, tile_height, | |
3024 | tile_size, pitch_tiles, | |
3025 | gtt_offset_rotated * tile_size, 0); | |
3026 | ||
3027 | /* | |
3028 | * First pixel of the framebuffer from | |
3029 | * the start of the rotated gtt mapping. | |
3030 | */ | |
3031 | intel_fb->rotated[plane].x = x; | |
3032 | intel_fb->rotated[plane].y = y; | |
3033 | ||
3034 | return plane_info->width * plane_info->height; | |
3035 | } | |
3036 | ||
6687c906 VS |
3037 | static int |
3038 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
3039 | struct drm_framebuffer *fb) | |
3040 | { | |
3041 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
a5ff7a45 | 3042 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6687c906 VS |
3043 | u32 gtt_offset_rotated = 0; |
3044 | unsigned int max_size = 0; | |
bcb0b461 | 3045 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
3046 | unsigned int tile_size = intel_tile_size(dev_priv); |
3047 | ||
3048 | for (i = 0; i < num_planes; i++) { | |
3049 | unsigned int width, height; | |
3050 | unsigned int cpp, size; | |
3051 | u32 offset; | |
3052 | int x, y; | |
303ba695 | 3053 | int ret; |
6687c906 | 3054 | |
353c8598 | 3055 | cpp = fb->format->cpp[i]; |
b3e57bcc | 3056 | intel_fb_plane_dims(&width, &height, fb, i); |
6687c906 | 3057 | |
303ba695 VS |
3058 | ret = intel_fb_offset_to_xy(&x, &y, fb, i); |
3059 | if (ret) { | |
cd49f818 WK |
3060 | drm_dbg_kms(&dev_priv->drm, |
3061 | "bad fb plane %d offset: 0x%x\n", | |
3062 | i, fb->offsets[i]); | |
303ba695 VS |
3063 | return ret; |
3064 | } | |
6687c906 | 3065 | |
13f2cb9a DP |
3066 | ret = intel_fb_check_ccs_xy(fb, i, x, y); |
3067 | if (ret) | |
3068 | return ret; | |
2e2adb05 | 3069 | |
60d5f2a4 VS |
3070 | /* |
3071 | * The fence (if used) is aligned to the start of the object | |
3072 | * so having the framebuffer wrap around across the edge of the | |
3073 | * fenced region doesn't really work. We have no API to configure | |
3074 | * the fence start offset within the object (nor could we probably | |
3075 | * on gen2/3). So it's just easier if we just require that the | |
3076 | * fb layout agrees with the fence layout. We already check that the | |
3077 | * fb stride matches the fence stride elsewhere. | |
3078 | */ | |
a5ff7a45 | 3079 | if (i == 0 && i915_gem_object_is_tiled(obj) && |
60d5f2a4 | 3080 | (x + width) * cpp > fb->pitches[i]) { |
cd49f818 WK |
3081 | drm_dbg_kms(&dev_priv->drm, |
3082 | "bad fb plane %d offset: 0x%x\n", | |
3083 | i, fb->offsets[i]); | |
60d5f2a4 VS |
3084 | return -EINVAL; |
3085 | } | |
3086 | ||
6687c906 VS |
3087 | /* |
3088 | * First pixel of the framebuffer from | |
3089 | * the start of the normal gtt mapping. | |
3090 | */ | |
3091 | intel_fb->normal[i].x = x; | |
3092 | intel_fb->normal[i].y = y; | |
3093 | ||
6d19a44c VS |
3094 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i, |
3095 | fb->pitches[i], | |
3096 | DRM_MODE_ROTATE_0, | |
3097 | tile_size); | |
6687c906 VS |
3098 | offset /= tile_size; |
3099 | ||
b3e57bcc | 3100 | if (!is_surface_linear(fb, i)) { |
931cd348 | 3101 | struct intel_remapped_plane_info plane_info; |
6687c906 | 3102 | unsigned int tile_width, tile_height; |
6687c906 | 3103 | |
d88c4afd | 3104 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 | 3105 | |
931cd348 DP |
3106 | plane_info.offset = offset; |
3107 | plane_info.stride = DIV_ROUND_UP(fb->pitches[i], | |
3108 | tile_width * cpp); | |
3109 | plane_info.width = DIV_ROUND_UP(x + width, tile_width); | |
3110 | plane_info.height = DIV_ROUND_UP(y + height, | |
3111 | tile_height); | |
6687c906 VS |
3112 | |
3113 | /* how many tiles does this plane need */ | |
931cd348 | 3114 | size = plane_info.stride * plane_info.height; |
6687c906 VS |
3115 | /* |
3116 | * If the plane isn't horizontally tile aligned, | |
3117 | * we need one more tile. | |
3118 | */ | |
3119 | if (x != 0) | |
3120 | size++; | |
3121 | ||
931cd348 DP |
3122 | gtt_offset_rotated += |
3123 | setup_fb_rotation(i, &plane_info, | |
3124 | gtt_offset_rotated, | |
3125 | x, y, width, height, | |
3126 | tile_size, | |
3127 | tile_width, tile_height, | |
3128 | fb); | |
6687c906 VS |
3129 | } else { |
3130 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
3131 | x * cpp, tile_size); | |
3132 | } | |
3133 | ||
3134 | /* how many tiles in total needed in the bo */ | |
3135 | max_size = max(max_size, offset + size); | |
3136 | } | |
3137 | ||
4e05047d | 3138 | if (mul_u32_u32(max_size, tile_size) > obj->base.size) { |
cd49f818 WK |
3139 | drm_dbg_kms(&dev_priv->drm, |
3140 | "fb too big for bo (need %llu bytes, have %zu bytes)\n", | |
3141 | mul_u32_u32(max_size, tile_size), obj->base.size); | |
6687c906 VS |
3142 | return -EINVAL; |
3143 | } | |
3144 | ||
3145 | return 0; | |
3146 | } | |
3147 | ||
54d4d719 VS |
3148 | static void |
3149 | intel_plane_remap_gtt(struct intel_plane_state *plane_state) | |
3150 | { | |
3151 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 3152 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 3153 | struct drm_framebuffer *fb = plane_state->hw.fb; |
54d4d719 VS |
3154 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
3155 | struct intel_rotation_info *info = &plane_state->view.rotated; | |
7b3cb17a | 3156 | unsigned int rotation = plane_state->hw.rotation; |
54d4d719 VS |
3157 | int i, num_planes = fb->format->num_planes; |
3158 | unsigned int tile_size = intel_tile_size(dev_priv); | |
3159 | unsigned int src_x, src_y; | |
3160 | unsigned int src_w, src_h; | |
3161 | u32 gtt_offset = 0; | |
3162 | ||
3163 | memset(&plane_state->view, 0, sizeof(plane_state->view)); | |
3164 | plane_state->view.type = drm_rotation_90_or_270(rotation) ? | |
3165 | I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED; | |
3166 | ||
f90a85e7 ML |
3167 | src_x = plane_state->uapi.src.x1 >> 16; |
3168 | src_y = plane_state->uapi.src.y1 >> 16; | |
3169 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; | |
3170 | src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
54d4d719 | 3171 | |
e57291c2 | 3172 | drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier)); |
54d4d719 VS |
3173 | |
3174 | /* Make src coordinates relative to the viewport */ | |
f90a85e7 | 3175 | drm_rect_translate(&plane_state->uapi.src, |
54d4d719 VS |
3176 | -(src_x << 16), -(src_y << 16)); |
3177 | ||
3178 | /* Rotate src coordinates to match rotated GTT view */ | |
3179 | if (drm_rotation_90_or_270(rotation)) | |
f90a85e7 | 3180 | drm_rect_rotate(&plane_state->uapi.src, |
54d4d719 VS |
3181 | src_w << 16, src_h << 16, |
3182 | DRM_MODE_ROTATE_270); | |
3183 | ||
3184 | for (i = 0; i < num_planes; i++) { | |
3185 | unsigned int hsub = i ? fb->format->hsub : 1; | |
3186 | unsigned int vsub = i ? fb->format->vsub : 1; | |
3187 | unsigned int cpp = fb->format->cpp[i]; | |
3188 | unsigned int tile_width, tile_height; | |
3189 | unsigned int width, height; | |
3190 | unsigned int pitch_tiles; | |
3191 | unsigned int x, y; | |
3192 | u32 offset; | |
3193 | ||
3194 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
3195 | ||
3196 | x = src_x / hsub; | |
3197 | y = src_y / vsub; | |
3198 | width = src_w / hsub; | |
3199 | height = src_h / vsub; | |
3200 | ||
3201 | /* | |
3202 | * First pixel of the src viewport from the | |
3203 | * start of the normal gtt mapping. | |
3204 | */ | |
3205 | x += intel_fb->normal[i].x; | |
3206 | y += intel_fb->normal[i].y; | |
3207 | ||
3208 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, | |
3209 | fb, i, fb->pitches[i], | |
3210 | DRM_MODE_ROTATE_0, tile_size); | |
3211 | offset /= tile_size; | |
3212 | ||
e57291c2 | 3213 | drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane)); |
54d4d719 VS |
3214 | info->plane[i].offset = offset; |
3215 | info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], | |
3216 | tile_width * cpp); | |
3217 | info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
3218 | info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
3219 | ||
3220 | if (drm_rotation_90_or_270(rotation)) { | |
3221 | struct drm_rect r; | |
3222 | ||
3223 | /* rotate the x/y offsets to match the GTT view */ | |
fc1a0fb5 | 3224 | drm_rect_init(&r, x, y, width, height); |
54d4d719 VS |
3225 | drm_rect_rotate(&r, |
3226 | info->plane[i].width * tile_width, | |
3227 | info->plane[i].height * tile_height, | |
3228 | DRM_MODE_ROTATE_270); | |
3229 | x = r.x1; | |
3230 | y = r.y1; | |
3231 | ||
3232 | pitch_tiles = info->plane[i].height; | |
3233 | plane_state->color_plane[i].stride = pitch_tiles * tile_height; | |
3234 | ||
3235 | /* rotate the tile dimensions to match the GTT view */ | |
3236 | swap(tile_width, tile_height); | |
3237 | } else { | |
3238 | pitch_tiles = info->plane[i].width; | |
3239 | plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp; | |
3240 | } | |
3241 | ||
3242 | /* | |
3243 | * We only keep the x/y offsets, so push all of the | |
3244 | * gtt offset into the x/y offsets. | |
3245 | */ | |
3246 | intel_adjust_tile_offset(&x, &y, | |
3247 | tile_width, tile_height, | |
3248 | tile_size, pitch_tiles, | |
3249 | gtt_offset * tile_size, 0); | |
3250 | ||
3251 | gtt_offset += info->plane[i].width * info->plane[i].height; | |
3252 | ||
3253 | plane_state->color_plane[i].offset = 0; | |
3254 | plane_state->color_plane[i].x = x; | |
3255 | plane_state->color_plane[i].y = y; | |
3256 | } | |
3257 | } | |
3258 | ||
3259 | static int | |
3260 | intel_plane_compute_gtt(struct intel_plane_state *plane_state) | |
3261 | { | |
3262 | const struct intel_framebuffer *fb = | |
7b3cb17a ML |
3263 | to_intel_framebuffer(plane_state->hw.fb); |
3264 | unsigned int rotation = plane_state->hw.rotation; | |
54d4d719 VS |
3265 | int i, num_planes; |
3266 | ||
3267 | if (!fb) | |
3268 | return 0; | |
3269 | ||
3270 | num_planes = fb->base.format->num_planes; | |
3271 | ||
3272 | if (intel_plane_needs_remap(plane_state)) { | |
3273 | intel_plane_remap_gtt(plane_state); | |
3274 | ||
3275 | /* | |
3276 | * Sometimes even remapping can't overcome | |
3277 | * the stride limitations :( Can happen with | |
3278 | * big plane sizes and suitably misaligned | |
3279 | * offsets. | |
3280 | */ | |
3281 | return intel_plane_check_stride(plane_state); | |
3282 | } | |
3283 | ||
3284 | intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation); | |
3285 | ||
3286 | for (i = 0; i < num_planes; i++) { | |
3287 | plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation); | |
3288 | plane_state->color_plane[i].offset = 0; | |
3289 | ||
3290 | if (drm_rotation_90_or_270(rotation)) { | |
3291 | plane_state->color_plane[i].x = fb->rotated[i].x; | |
3292 | plane_state->color_plane[i].y = fb->rotated[i].y; | |
3293 | } else { | |
3294 | plane_state->color_plane[i].x = fb->normal[i].x; | |
3295 | plane_state->color_plane[i].y = fb->normal[i].y; | |
3296 | } | |
3297 | } | |
3298 | ||
3299 | /* Rotate src coordinates to match rotated GTT view */ | |
3300 | if (drm_rotation_90_or_270(rotation)) | |
f90a85e7 | 3301 | drm_rect_rotate(&plane_state->uapi.src, |
54d4d719 VS |
3302 | fb->base.width << 16, fb->base.height << 16, |
3303 | DRM_MODE_ROTATE_270); | |
3304 | ||
3305 | return intel_plane_check_stride(plane_state); | |
3306 | } | |
3307 | ||
b35d63fa | 3308 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
3309 | { |
3310 | switch (format) { | |
3311 | case DISPPLANE_8BPP: | |
3312 | return DRM_FORMAT_C8; | |
73263cb6 VS |
3313 | case DISPPLANE_BGRA555: |
3314 | return DRM_FORMAT_ARGB1555; | |
46f297fb JB |
3315 | case DISPPLANE_BGRX555: |
3316 | return DRM_FORMAT_XRGB1555; | |
3317 | case DISPPLANE_BGRX565: | |
3318 | return DRM_FORMAT_RGB565; | |
3319 | default: | |
3320 | case DISPPLANE_BGRX888: | |
3321 | return DRM_FORMAT_XRGB8888; | |
3322 | case DISPPLANE_RGBX888: | |
3323 | return DRM_FORMAT_XBGR8888; | |
73263cb6 VS |
3324 | case DISPPLANE_BGRA888: |
3325 | return DRM_FORMAT_ARGB8888; | |
3326 | case DISPPLANE_RGBA888: | |
3327 | return DRM_FORMAT_ABGR8888; | |
46f297fb JB |
3328 | case DISPPLANE_BGRX101010: |
3329 | return DRM_FORMAT_XRGB2101010; | |
3330 | case DISPPLANE_RGBX101010: | |
3331 | return DRM_FORMAT_XBGR2101010; | |
73263cb6 VS |
3332 | case DISPPLANE_BGRA101010: |
3333 | return DRM_FORMAT_ARGB2101010; | |
3334 | case DISPPLANE_RGBA101010: | |
3335 | return DRM_FORMAT_ABGR2101010; | |
03b0ce95 VS |
3336 | case DISPPLANE_RGBX161616: |
3337 | return DRM_FORMAT_XBGR16161616F; | |
46f297fb JB |
3338 | } |
3339 | } | |
3340 | ||
ddf34319 | 3341 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
bc8d7dff DL |
3342 | { |
3343 | switch (format) { | |
3344 | case PLANE_CTL_FORMAT_RGB_565: | |
3345 | return DRM_FORMAT_RGB565; | |
f34a291c MK |
3346 | case PLANE_CTL_FORMAT_NV12: |
3347 | return DRM_FORMAT_NV12; | |
da904174 SL |
3348 | case PLANE_CTL_FORMAT_XYUV: |
3349 | return DRM_FORMAT_XYUV8888; | |
df7d4156 JPH |
3350 | case PLANE_CTL_FORMAT_P010: |
3351 | return DRM_FORMAT_P010; | |
3352 | case PLANE_CTL_FORMAT_P012: | |
3353 | return DRM_FORMAT_P012; | |
3354 | case PLANE_CTL_FORMAT_P016: | |
3355 | return DRM_FORMAT_P016; | |
296e9b19 SS |
3356 | case PLANE_CTL_FORMAT_Y210: |
3357 | return DRM_FORMAT_Y210; | |
3358 | case PLANE_CTL_FORMAT_Y212: | |
3359 | return DRM_FORMAT_Y212; | |
3360 | case PLANE_CTL_FORMAT_Y216: | |
3361 | return DRM_FORMAT_Y216; | |
3362 | case PLANE_CTL_FORMAT_Y410: | |
ff01e697 | 3363 | return DRM_FORMAT_XVYU2101010; |
296e9b19 | 3364 | case PLANE_CTL_FORMAT_Y412: |
ff01e697 | 3365 | return DRM_FORMAT_XVYU12_16161616; |
296e9b19 | 3366 | case PLANE_CTL_FORMAT_Y416: |
ff01e697 | 3367 | return DRM_FORMAT_XVYU16161616; |
bc8d7dff DL |
3368 | default: |
3369 | case PLANE_CTL_FORMAT_XRGB_8888: | |
3370 | if (rgb_order) { | |
3371 | if (alpha) | |
3372 | return DRM_FORMAT_ABGR8888; | |
3373 | else | |
3374 | return DRM_FORMAT_XBGR8888; | |
3375 | } else { | |
3376 | if (alpha) | |
3377 | return DRM_FORMAT_ARGB8888; | |
3378 | else | |
3379 | return DRM_FORMAT_XRGB8888; | |
3380 | } | |
3381 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
f9c43a31 VS |
3382 | if (rgb_order) { |
3383 | if (alpha) | |
3384 | return DRM_FORMAT_ABGR2101010; | |
3385 | else | |
3386 | return DRM_FORMAT_XBGR2101010; | |
3387 | } else { | |
3388 | if (alpha) | |
3389 | return DRM_FORMAT_ARGB2101010; | |
3390 | else | |
3391 | return DRM_FORMAT_XRGB2101010; | |
3392 | } | |
a94bed60 KS |
3393 | case PLANE_CTL_FORMAT_XRGB_16161616F: |
3394 | if (rgb_order) { | |
3395 | if (alpha) | |
3396 | return DRM_FORMAT_ABGR16161616F; | |
3397 | else | |
3398 | return DRM_FORMAT_XBGR16161616F; | |
3399 | } else { | |
3400 | if (alpha) | |
3401 | return DRM_FORMAT_ARGB16161616F; | |
3402 | else | |
3403 | return DRM_FORMAT_XRGB16161616F; | |
3404 | } | |
bc8d7dff DL |
3405 | } |
3406 | } | |
3407 | ||
9c4ce97d CW |
3408 | static struct i915_vma * |
3409 | initial_plane_vma(struct drm_i915_private *i915, | |
3410 | struct intel_initial_plane_config *plane_config) | |
3411 | { | |
3412 | struct drm_i915_gem_object *obj; | |
3413 | struct i915_vma *vma; | |
3414 | u32 base, size; | |
3415 | ||
3416 | if (plane_config->size == 0) | |
3417 | return NULL; | |
3418 | ||
3419 | base = round_down(plane_config->base, | |
3420 | I915_GTT_MIN_ALIGNMENT); | |
3421 | size = round_up(plane_config->base + plane_config->size, | |
3422 | I915_GTT_MIN_ALIGNMENT); | |
3423 | size -= base; | |
3424 | ||
3425 | /* | |
3426 | * If the FB is too big, just don't use it since fbdev is not very | |
3427 | * important and we should probably use that space with FBC or other | |
3428 | * features. | |
3429 | */ | |
3430 | if (size * 2 > i915->stolen_usable_size) | |
3431 | return NULL; | |
3432 | ||
3433 | obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size); | |
3434 | if (IS_ERR(obj)) | |
3435 | return NULL; | |
3436 | ||
1664ffee VS |
3437 | /* |
3438 | * Mark it WT ahead of time to avoid changing the | |
3439 | * cache_level during fbdev initialization. The | |
3440 | * unbind there would get stuck waiting for rcu. | |
3441 | */ | |
3442 | i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? | |
3443 | I915_CACHE_WT : I915_CACHE_NONE); | |
3444 | ||
9c4ce97d CW |
3445 | switch (plane_config->tiling) { |
3446 | case I915_TILING_NONE: | |
3447 | break; | |
3448 | case I915_TILING_X: | |
3449 | case I915_TILING_Y: | |
3450 | obj->tiling_and_stride = | |
3451 | plane_config->fb->base.pitches[0] | | |
3452 | plane_config->tiling; | |
3453 | break; | |
3454 | default: | |
3455 | MISSING_CASE(plane_config->tiling); | |
3456 | goto err_obj; | |
3457 | } | |
3458 | ||
3459 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); | |
3460 | if (IS_ERR(vma)) | |
3461 | goto err_obj; | |
3462 | ||
47b08693 | 3463 | if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) |
9c4ce97d CW |
3464 | goto err_obj; |
3465 | ||
3466 | if (i915_gem_object_is_tiled(obj) && | |
3467 | !i915_vma_is_map_and_fenceable(vma)) | |
3468 | goto err_obj; | |
3469 | ||
3470 | return vma; | |
3471 | ||
3472 | err_obj: | |
3473 | i915_gem_object_put(obj); | |
3474 | return NULL; | |
3475 | } | |
3476 | ||
5724dbd1 | 3477 | static bool |
f6936e29 DV |
3478 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
3479 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
3480 | { |
3481 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 3482 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb | 3483 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
2d14030b | 3484 | struct drm_framebuffer *fb = &plane_config->fb->base; |
9c4ce97d | 3485 | struct i915_vma *vma; |
3badb49f | 3486 | |
914a4fd8 ID |
3487 | switch (fb->modifier) { |
3488 | case DRM_FORMAT_MOD_LINEAR: | |
3489 | case I915_FORMAT_MOD_X_TILED: | |
3490 | case I915_FORMAT_MOD_Y_TILED: | |
3491 | break; | |
3492 | default: | |
cd49f818 WK |
3493 | drm_dbg(&dev_priv->drm, |
3494 | "Unsupported modifier for initial FB: 0x%llx\n", | |
3495 | fb->modifier); | |
914a4fd8 ID |
3496 | return false; |
3497 | } | |
3498 | ||
9c4ce97d CW |
3499 | vma = initial_plane_vma(dev_priv, plane_config); |
3500 | if (!vma) | |
484b41dd | 3501 | return false; |
46f297fb | 3502 | |
438b74a5 | 3503 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
3504 | mode_cmd.width = fb->width; |
3505 | mode_cmd.height = fb->height; | |
3506 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 3507 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 3508 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 3509 | |
9c4ce97d CW |
3510 | if (intel_framebuffer_init(to_intel_framebuffer(fb), |
3511 | vma->obj, &mode_cmd)) { | |
cd49f818 | 3512 | drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); |
9c4ce97d | 3513 | goto err_vma; |
46f297fb | 3514 | } |
12c83d99 | 3515 | |
9c4ce97d CW |
3516 | plane_config->vma = vma; |
3517 | return true; | |
484b41dd | 3518 | |
9c4ce97d CW |
3519 | err_vma: |
3520 | i915_vma_put(vma); | |
3521 | return false; | |
484b41dd JB |
3522 | } |
3523 | ||
e9728bd8 VS |
3524 | static void |
3525 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
3526 | struct intel_plane_state *plane_state, | |
3527 | bool visible) | |
3528 | { | |
f90a85e7 | 3529 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
e9728bd8 | 3530 | |
f90a85e7 | 3531 | plane_state->uapi.visible = visible; |
e9728bd8 | 3532 | |
62358aa4 | 3533 | if (visible) |
2225f3c6 | 3534 | crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); |
62358aa4 | 3535 | else |
2225f3c6 | 3536 | crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); |
e9728bd8 VS |
3537 | } |
3538 | ||
62358aa4 VS |
3539 | static void fixup_active_planes(struct intel_crtc_state *crtc_state) |
3540 | { | |
2225f3c6 | 3541 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
62358aa4 VS |
3542 | struct drm_plane *plane; |
3543 | ||
3544 | /* | |
3545 | * Active_planes aliases if multiple "primary" or cursor planes | |
3546 | * have been used on the same (or wrong) pipe. plane_mask uses | |
3547 | * unique ids, hence we can use that to reconstruct active_planes. | |
3548 | */ | |
3549 | crtc_state->active_planes = 0; | |
3550 | ||
3551 | drm_for_each_plane_mask(plane, &dev_priv->drm, | |
2225f3c6 | 3552 | crtc_state->uapi.plane_mask) |
62358aa4 VS |
3553 | crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); |
3554 | } | |
3555 | ||
b1e01595 VS |
3556 | static void intel_plane_disable_noatomic(struct intel_crtc *crtc, |
3557 | struct intel_plane *plane) | |
3558 | { | |
23526249 | 3559 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b1e01595 VS |
3560 | struct intel_crtc_state *crtc_state = |
3561 | to_intel_crtc_state(crtc->base.state); | |
3562 | struct intel_plane_state *plane_state = | |
3563 | to_intel_plane_state(plane->base.state); | |
3564 | ||
cd49f818 WK |
3565 | drm_dbg_kms(&dev_priv->drm, |
3566 | "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", | |
3567 | plane->base.base.id, plane->base.name, | |
3568 | crtc->base.base.id, crtc->base.name); | |
7a4a2a46 | 3569 | |
b1e01595 | 3570 | intel_set_plane_visible(crtc_state, plane_state, false); |
62358aa4 | 3571 | fixup_active_planes(crtc_state); |
c457d9cf | 3572 | crtc_state->data_rate[plane->id] = 0; |
bb6ae9e6 | 3573 | crtc_state->min_cdclk[plane->id] = 0; |
b1e01595 VS |
3574 | |
3575 | if (plane->id == PLANE_PRIMARY) | |
23526249 VS |
3576 | hsw_disable_ips(crtc_state); |
3577 | ||
3578 | /* | |
3579 | * Vblank time updates from the shadow to live plane control register | |
3580 | * are blocked if the memory self-refresh mode is active at that | |
3581 | * moment. So to make sure the plane gets truly disabled, disable | |
3582 | * first the self-refresh mode. The self-refresh enable bit in turn | |
3583 | * will be checked/applied by the HW only at the next frame start | |
3584 | * event which is after the vblank start event, so we need to have a | |
3585 | * wait-for-vblank between disabling the plane and the pipe. | |
3586 | */ | |
3587 | if (HAS_GMCH(dev_priv) && | |
3588 | intel_set_memory_cxsr(dev_priv, false)) | |
3589 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
3590 | ||
3591 | /* | |
3592 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
3593 | * So disable underrun reporting before all the planes get disabled. | |
3594 | */ | |
3595 | if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes) | |
3596 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
b1e01595 | 3597 | |
c48b86f9 | 3598 | intel_disable_plane(plane, crtc_state); |
b1e01595 VS |
3599 | } |
3600 | ||
8e7cb179 CW |
3601 | static struct intel_frontbuffer * |
3602 | to_intel_frontbuffer(struct drm_framebuffer *fb) | |
3603 | { | |
3604 | return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; | |
3605 | } | |
3606 | ||
5724dbd1 | 3607 | static void |
f6936e29 DV |
3608 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
3609 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
3610 | { |
3611 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3612 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 3613 | struct drm_crtc *c; |
88595ac9 | 3614 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 3615 | struct drm_plane_state *plane_state = primary->state; |
200757f5 | 3616 | struct intel_plane *intel_plane = to_intel_plane(primary); |
0a8d8a86 MR |
3617 | struct intel_plane_state *intel_state = |
3618 | to_intel_plane_state(plane_state); | |
88595ac9 | 3619 | struct drm_framebuffer *fb; |
9c4ce97d | 3620 | struct i915_vma *vma; |
484b41dd | 3621 | |
2d14030b | 3622 | if (!plane_config->fb) |
484b41dd JB |
3623 | return; |
3624 | ||
f6936e29 | 3625 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 | 3626 | fb = &plane_config->fb->base; |
9c4ce97d | 3627 | vma = plane_config->vma; |
88595ac9 | 3628 | goto valid_fb; |
f55548b5 | 3629 | } |
484b41dd | 3630 | |
484b41dd JB |
3631 | /* |
3632 | * Failed to alloc the obj, check to see if we should share | |
3633 | * an fb with another CRTC instead | |
3634 | */ | |
70e1e0ec | 3635 | for_each_crtc(dev, c) { |
be1e3415 | 3636 | struct intel_plane_state *state; |
484b41dd JB |
3637 | |
3638 | if (c == &intel_crtc->base) | |
3639 | continue; | |
3640 | ||
be1e3415 | 3641 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
3642 | continue; |
3643 | ||
be1e3415 CW |
3644 | state = to_intel_plane_state(c->primary->state); |
3645 | if (!state->vma) | |
484b41dd JB |
3646 | continue; |
3647 | ||
be1e3415 | 3648 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
7b3cb17a | 3649 | fb = state->hw.fb; |
9c4ce97d | 3650 | vma = state->vma; |
88595ac9 | 3651 | goto valid_fb; |
484b41dd JB |
3652 | } |
3653 | } | |
88595ac9 | 3654 | |
200757f5 MR |
3655 | /* |
3656 | * We've failed to reconstruct the BIOS FB. Current display state | |
3657 | * indicates that the primary plane is visible, but has a NULL FB, | |
3658 | * which will lead to problems later if we don't fix it up. The | |
3659 | * simplest solution is to just disable the primary plane now and | |
3660 | * pretend the BIOS never had it enabled. | |
3661 | */ | |
b1e01595 | 3662 | intel_plane_disable_noatomic(intel_crtc, intel_plane); |
200757f5 | 3663 | |
88595ac9 DV |
3664 | return; |
3665 | ||
3666 | valid_fb: | |
7b3cb17a | 3667 | intel_state->hw.rotation = plane_config->rotation; |
f5929c53 | 3668 | intel_fill_fb_ggtt_view(&intel_state->view, fb, |
7b3cb17a | 3669 | intel_state->hw.rotation); |
df79cf44 | 3670 | intel_state->color_plane[0].stride = |
7b3cb17a | 3671 | intel_fb_pitch(fb, 0, intel_state->hw.rotation); |
df79cf44 | 3672 | |
9c4ce97d CW |
3673 | __i915_vma_pin(vma); |
3674 | intel_state->vma = i915_vma_get(vma); | |
3675 | if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0) | |
3676 | if (vma->fence) | |
3677 | intel_state->flags |= PLANE_HAS_FENCE; | |
07bcd99b | 3678 | |
f44e2659 VS |
3679 | plane_state->src_x = 0; |
3680 | plane_state->src_y = 0; | |
be5651f2 ML |
3681 | plane_state->src_w = fb->width << 16; |
3682 | plane_state->src_h = fb->height << 16; | |
3683 | ||
f44e2659 VS |
3684 | plane_state->crtc_x = 0; |
3685 | plane_state->crtc_y = 0; | |
be5651f2 ML |
3686 | plane_state->crtc_w = fb->width; |
3687 | plane_state->crtc_h = fb->height; | |
3688 | ||
f90a85e7 ML |
3689 | intel_state->uapi.src = drm_plane_state_src(plane_state); |
3690 | intel_state->uapi.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 3691 | |
8e7cb179 | 3692 | if (plane_config->tiling) |
88595ac9 DV |
3693 | dev_priv->preserve_bios_swizzle = true; |
3694 | ||
cd30fbca | 3695 | plane_state->fb = fb; |
1586f620 CW |
3696 | drm_framebuffer_get(fb); |
3697 | ||
cd30fbca | 3698 | plane_state->crtc = &intel_crtc->base; |
380015bf | 3699 | intel_plane_copy_uapi_to_hw_state(intel_state, intel_state); |
e9728bd8 | 3700 | |
9c4ce97d CW |
3701 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
3702 | ||
faf5bf0a | 3703 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
8e7cb179 | 3704 | &to_intel_frontbuffer(fb)->bits); |
46f297fb JB |
3705 | } |
3706 | ||
5d2a1950 VS |
3707 | static int skl_max_plane_width(const struct drm_framebuffer *fb, |
3708 | int color_plane, | |
b63a16f6 VS |
3709 | unsigned int rotation) |
3710 | { | |
5d2a1950 | 3711 | int cpp = fb->format->cpp[color_plane]; |
b63a16f6 | 3712 | |
bae781b2 | 3713 | switch (fb->modifier) { |
2f075565 | 3714 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 | 3715 | case I915_FORMAT_MOD_X_TILED: |
bed34ef5 VS |
3716 | /* |
3717 | * Validated limit is 4k, but has 5k should | |
3718 | * work apart from the following features: | |
3719 | * - Ytile (already limited to 4k) | |
3720 | * - FP16 (already limited to 4k) | |
3721 | * - render compression (already limited to 4k) | |
3722 | * - KVMR sprite and cursor (don't care) | |
3723 | * - horizontal panning (TODO verify this) | |
3724 | * - pipe and plane scaling (TODO verify this) | |
3725 | */ | |
3726 | if (cpp == 8) | |
3727 | return 4096; | |
3728 | else | |
3729 | return 5120; | |
2e2adb05 VS |
3730 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3731 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2dfbf9d2 | 3732 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
2e2adb05 | 3733 | /* FIXME AUX plane? */ |
b63a16f6 VS |
3734 | case I915_FORMAT_MOD_Y_TILED: |
3735 | case I915_FORMAT_MOD_Yf_TILED: | |
372b9ffb | 3736 | if (cpp == 8) |
b63a16f6 | 3737 | return 2048; |
372b9ffb | 3738 | else |
b63a16f6 | 3739 | return 4096; |
b63a16f6 | 3740 | default: |
bae781b2 | 3741 | MISSING_CASE(fb->modifier); |
372b9ffb | 3742 | return 2048; |
b63a16f6 | 3743 | } |
372b9ffb | 3744 | } |
b63a16f6 | 3745 | |
372b9ffb VS |
3746 | static int glk_max_plane_width(const struct drm_framebuffer *fb, |
3747 | int color_plane, | |
3748 | unsigned int rotation) | |
3749 | { | |
3750 | int cpp = fb->format->cpp[color_plane]; | |
3751 | ||
3752 | switch (fb->modifier) { | |
3753 | case DRM_FORMAT_MOD_LINEAR: | |
3754 | case I915_FORMAT_MOD_X_TILED: | |
3755 | if (cpp == 8) | |
3756 | return 4096; | |
3757 | else | |
3758 | return 5120; | |
3759 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
3760 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
3761 | /* FIXME AUX plane? */ | |
3762 | case I915_FORMAT_MOD_Y_TILED: | |
3763 | case I915_FORMAT_MOD_Yf_TILED: | |
3764 | if (cpp == 8) | |
3765 | return 2048; | |
3766 | else | |
3767 | return 5120; | |
3768 | default: | |
3769 | MISSING_CASE(fb->modifier); | |
3770 | return 2048; | |
3771 | } | |
3772 | } | |
3773 | ||
d24f1341 MA |
3774 | static int icl_min_plane_width(const struct drm_framebuffer *fb) |
3775 | { | |
3776 | /* Wa_14011264657, Wa_14011050563: gen11+ */ | |
3777 | switch (fb->format->format) { | |
3778 | case DRM_FORMAT_C8: | |
3779 | return 18; | |
3780 | case DRM_FORMAT_RGB565: | |
3781 | return 10; | |
3782 | case DRM_FORMAT_XRGB8888: | |
3783 | case DRM_FORMAT_XBGR8888: | |
3784 | case DRM_FORMAT_ARGB8888: | |
3785 | case DRM_FORMAT_ABGR8888: | |
3786 | case DRM_FORMAT_XRGB2101010: | |
3787 | case DRM_FORMAT_XBGR2101010: | |
3788 | case DRM_FORMAT_ARGB2101010: | |
3789 | case DRM_FORMAT_ABGR2101010: | |
3790 | case DRM_FORMAT_XVYU2101010: | |
3791 | case DRM_FORMAT_Y212: | |
3792 | case DRM_FORMAT_Y216: | |
3793 | return 6; | |
3794 | case DRM_FORMAT_NV12: | |
3795 | return 20; | |
3796 | case DRM_FORMAT_P010: | |
3797 | case DRM_FORMAT_P012: | |
3798 | case DRM_FORMAT_P016: | |
3799 | return 12; | |
3800 | case DRM_FORMAT_XRGB16161616F: | |
3801 | case DRM_FORMAT_XBGR16161616F: | |
3802 | case DRM_FORMAT_ARGB16161616F: | |
3803 | case DRM_FORMAT_ABGR16161616F: | |
3804 | case DRM_FORMAT_XVYU12_16161616: | |
3805 | case DRM_FORMAT_XVYU16161616: | |
3806 | return 4; | |
3807 | default: | |
3808 | return 1; | |
3809 | } | |
3810 | } | |
3811 | ||
372b9ffb VS |
3812 | static int icl_max_plane_width(const struct drm_framebuffer *fb, |
3813 | int color_plane, | |
3814 | unsigned int rotation) | |
3815 | { | |
3816 | return 5120; | |
b63a16f6 VS |
3817 | } |
3818 | ||
e91c8a29 MN |
3819 | static int skl_max_plane_height(void) |
3820 | { | |
3821 | return 4096; | |
3822 | } | |
3823 | ||
3824 | static int icl_max_plane_height(void) | |
3825 | { | |
3826 | return 4320; | |
3827 | } | |
3828 | ||
2dfbf9d2 DP |
3829 | static bool |
3830 | skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, | |
3831 | int main_x, int main_y, u32 main_offset, | |
3832 | int ccs_plane) | |
2e2adb05 | 3833 | { |
7b3cb17a | 3834 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
e7af9094 ID |
3835 | int aux_x = plane_state->color_plane[ccs_plane].x; |
3836 | int aux_y = plane_state->color_plane[ccs_plane].y; | |
3837 | u32 aux_offset = plane_state->color_plane[ccs_plane].offset; | |
3838 | u32 alignment = intel_surf_alignment(fb, ccs_plane); | |
b3e57bcc DP |
3839 | int hsub; |
3840 | int vsub; | |
2e2adb05 | 3841 | |
b3e57bcc | 3842 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
2e2adb05 VS |
3843 | while (aux_offset >= main_offset && aux_y <= main_y) { |
3844 | int x, y; | |
3845 | ||
3846 | if (aux_x == main_x && aux_y == main_y) | |
3847 | break; | |
3848 | ||
3849 | if (aux_offset == 0) | |
3850 | break; | |
3851 | ||
3852 | x = aux_x / hsub; | |
3853 | y = aux_y / vsub; | |
e7af9094 ID |
3854 | aux_offset = intel_plane_adjust_aligned_offset(&x, &y, |
3855 | plane_state, | |
3856 | ccs_plane, | |
3857 | aux_offset, | |
3858 | aux_offset - | |
3859 | alignment); | |
2e2adb05 VS |
3860 | aux_x = x * hsub + aux_x % hsub; |
3861 | aux_y = y * vsub + aux_y % vsub; | |
3862 | } | |
3863 | ||
3864 | if (aux_x != main_x || aux_y != main_y) | |
3865 | return false; | |
3866 | ||
e7af9094 ID |
3867 | plane_state->color_plane[ccs_plane].offset = aux_offset; |
3868 | plane_state->color_plane[ccs_plane].x = aux_x; | |
3869 | plane_state->color_plane[ccs_plane].y = aux_y; | |
2e2adb05 VS |
3870 | |
3871 | return true; | |
3872 | } | |
3873 | ||
5331889b VS |
3874 | unsigned int |
3875 | intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) | |
3876 | { | |
3877 | int x = 0, y = 0; | |
3878 | ||
3879 | intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, | |
3880 | plane_state->color_plane[0].offset, 0); | |
3881 | ||
3882 | return y; | |
3883 | } | |
3884 | ||
73266595 | 3885 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
b63a16f6 | 3886 | { |
f90a85e7 | 3887 | struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
3888 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
3889 | unsigned int rotation = plane_state->hw.rotation; | |
f90a85e7 ML |
3890 | int x = plane_state->uapi.src.x1 >> 16; |
3891 | int y = plane_state->uapi.src.y1 >> 16; | |
3892 | int w = drm_rect_width(&plane_state->uapi.src) >> 16; | |
3893 | int h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
d24f1341 MA |
3894 | int max_width, min_width, max_height; |
3895 | u32 alignment, offset; | |
e7af9094 ID |
3896 | int aux_plane = intel_main_to_aux_plane(fb, 0); |
3897 | u32 aux_offset = plane_state->color_plane[aux_plane].offset; | |
b63a16f6 | 3898 | |
d24f1341 | 3899 | if (INTEL_GEN(dev_priv) >= 11) { |
372b9ffb | 3900 | max_width = icl_max_plane_width(fb, 0, rotation); |
d24f1341 MA |
3901 | min_width = icl_min_plane_width(fb); |
3902 | } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { | |
372b9ffb | 3903 | max_width = glk_max_plane_width(fb, 0, rotation); |
d24f1341 MA |
3904 | min_width = 1; |
3905 | } else { | |
372b9ffb | 3906 | max_width = skl_max_plane_width(fb, 0, rotation); |
d24f1341 MA |
3907 | min_width = 1; |
3908 | } | |
372b9ffb | 3909 | |
e91c8a29 MN |
3910 | if (INTEL_GEN(dev_priv) >= 11) |
3911 | max_height = icl_max_plane_height(); | |
3912 | else | |
3913 | max_height = skl_max_plane_height(); | |
3914 | ||
d24f1341 | 3915 | if (w > max_width || w < min_width || h > max_height) { |
cd49f818 | 3916 | drm_dbg_kms(&dev_priv->drm, |
d24f1341 MA |
3917 | "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", |
3918 | w, h, min_width, max_width, max_height); | |
b63a16f6 VS |
3919 | return -EINVAL; |
3920 | } | |
3921 | ||
3922 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
6d19a44c | 3923 | offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); |
d88c4afd | 3924 | alignment = intel_surf_alignment(fb, 0); |
e57291c2 | 3925 | if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) |
7361bdb2 | 3926 | return -EINVAL; |
b63a16f6 | 3927 | |
8d970654 VS |
3928 | /* |
3929 | * AUX surface offset is specified as the distance from the | |
3930 | * main surface offset, and it must be non-negative. Make | |
3931 | * sure that is what we will get. | |
3932 | */ | |
3933 | if (offset > aux_offset) | |
6d19a44c VS |
3934 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3935 | offset, aux_offset & ~(alignment - 1)); | |
8d970654 | 3936 | |
b63a16f6 VS |
3937 | /* |
3938 | * When using an X-tiled surface, the plane blows up | |
3939 | * if the x offset + width exceed the stride. | |
3940 | * | |
3941 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3942 | */ | |
bae781b2 | 3943 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3944 | int cpp = fb->format->cpp[0]; |
b63a16f6 | 3945 | |
df79cf44 | 3946 | while ((x + w) * cpp > plane_state->color_plane[0].stride) { |
b63a16f6 | 3947 | if (offset == 0) { |
cd49f818 WK |
3948 | drm_dbg_kms(&dev_priv->drm, |
3949 | "Unable to find suitable display surface offset due to X-tiling\n"); | |
b63a16f6 VS |
3950 | return -EINVAL; |
3951 | } | |
3952 | ||
6d19a44c VS |
3953 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3954 | offset, offset - alignment); | |
b63a16f6 VS |
3955 | } |
3956 | } | |
3957 | ||
2e2adb05 VS |
3958 | /* |
3959 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3960 | * they match with the main surface x/y offsets. | |
3961 | */ | |
63eaf9ac | 3962 | if (is_ccs_modifier(fb->modifier)) { |
2dfbf9d2 DP |
3963 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, |
3964 | offset, aux_plane)) { | |
2e2adb05 VS |
3965 | if (offset == 0) |
3966 | break; | |
3967 | ||
6d19a44c VS |
3968 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
3969 | offset, offset - alignment); | |
2e2adb05 VS |
3970 | } |
3971 | ||
e7af9094 ID |
3972 | if (x != plane_state->color_plane[aux_plane].x || |
3973 | y != plane_state->color_plane[aux_plane].y) { | |
cd49f818 WK |
3974 | drm_dbg_kms(&dev_priv->drm, |
3975 | "Unable to find suitable display surface offset due to CCS\n"); | |
2e2adb05 VS |
3976 | return -EINVAL; |
3977 | } | |
3978 | } | |
3979 | ||
c11ada07 VS |
3980 | plane_state->color_plane[0].offset = offset; |
3981 | plane_state->color_plane[0].x = x; | |
3982 | plane_state->color_plane[0].y = y; | |
b63a16f6 | 3983 | |
54d4d719 VS |
3984 | /* |
3985 | * Put the final coordinates back so that the src | |
3986 | * coordinate checks will see the right values. | |
3987 | */ | |
f90a85e7 | 3988 | drm_rect_translate_to(&plane_state->uapi.src, |
dcdef1ab | 3989 | x << 16, y << 16); |
54d4d719 | 3990 | |
b63a16f6 VS |
3991 | return 0; |
3992 | } | |
3993 | ||
8d970654 VS |
3994 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3995 | { | |
cd49f818 | 3996 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
3997 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
3998 | unsigned int rotation = plane_state->hw.rotation; | |
2dfbf9d2 DP |
3999 | int uv_plane = 1; |
4000 | int max_width = skl_max_plane_width(fb, uv_plane, rotation); | |
8d970654 | 4001 | int max_height = 4096; |
f90a85e7 ML |
4002 | int x = plane_state->uapi.src.x1 >> 17; |
4003 | int y = plane_state->uapi.src.y1 >> 17; | |
4004 | int w = drm_rect_width(&plane_state->uapi.src) >> 17; | |
4005 | int h = drm_rect_height(&plane_state->uapi.src) >> 17; | |
8d970654 VS |
4006 | u32 offset; |
4007 | ||
2dfbf9d2 DP |
4008 | intel_add_fb_offsets(&x, &y, plane_state, uv_plane); |
4009 | offset = intel_plane_compute_aligned_offset(&x, &y, | |
4010 | plane_state, uv_plane); | |
8d970654 VS |
4011 | |
4012 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
4013 | if (w > max_width || h > max_height) { | |
cd49f818 WK |
4014 | drm_dbg_kms(&i915->drm, |
4015 | "CbCr source size %dx%d too big (limit %dx%d)\n", | |
4016 | w, h, max_width, max_height); | |
8d970654 VS |
4017 | return -EINVAL; |
4018 | } | |
4019 | ||
2dfbf9d2 DP |
4020 | if (is_ccs_modifier(fb->modifier)) { |
4021 | int ccs_plane = main_to_ccs_plane(fb, uv_plane); | |
4022 | int aux_offset = plane_state->color_plane[ccs_plane].offset; | |
4023 | int alignment = intel_surf_alignment(fb, uv_plane); | |
4024 | ||
4025 | if (offset > aux_offset) | |
4026 | offset = intel_plane_adjust_aligned_offset(&x, &y, | |
4027 | plane_state, | |
4028 | uv_plane, | |
4029 | offset, | |
4030 | aux_offset & ~(alignment - 1)); | |
4031 | ||
4032 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, | |
4033 | offset, ccs_plane)) { | |
4034 | if (offset == 0) | |
4035 | break; | |
4036 | ||
4037 | offset = intel_plane_adjust_aligned_offset(&x, &y, | |
4038 | plane_state, | |
4039 | uv_plane, | |
4040 | offset, offset - alignment); | |
4041 | } | |
4042 | ||
4043 | if (x != plane_state->color_plane[ccs_plane].x || | |
4044 | y != plane_state->color_plane[ccs_plane].y) { | |
cd49f818 WK |
4045 | drm_dbg_kms(&i915->drm, |
4046 | "Unable to find suitable display surface offset due to CCS\n"); | |
2dfbf9d2 DP |
4047 | return -EINVAL; |
4048 | } | |
4049 | } | |
4050 | ||
4051 | plane_state->color_plane[uv_plane].offset = offset; | |
4052 | plane_state->color_plane[uv_plane].x = x; | |
4053 | plane_state->color_plane[uv_plane].y = y; | |
8d970654 VS |
4054 | |
4055 | return 0; | |
4056 | } | |
4057 | ||
2e2adb05 VS |
4058 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
4059 | { | |
7b3cb17a | 4060 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 ML |
4061 | int src_x = plane_state->uapi.src.x1 >> 16; |
4062 | int src_y = plane_state->uapi.src.y1 >> 16; | |
2e2adb05 | 4063 | u32 offset; |
2dfbf9d2 | 4064 | int ccs_plane; |
2e2adb05 | 4065 | |
2dfbf9d2 DP |
4066 | for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { |
4067 | int main_hsub, main_vsub; | |
4068 | int hsub, vsub; | |
4069 | int x, y; | |
2e2adb05 | 4070 | |
2dfbf9d2 DP |
4071 | if (!is_ccs_plane(fb, ccs_plane)) |
4072 | continue; | |
4073 | ||
4074 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, | |
4075 | ccs_to_main_plane(fb, ccs_plane)); | |
4076 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); | |
4077 | ||
4078 | hsub *= main_hsub; | |
4079 | vsub *= main_vsub; | |
4080 | x = src_x / hsub; | |
4081 | y = src_y / vsub; | |
4082 | ||
4083 | intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); | |
4084 | ||
4085 | offset = intel_plane_compute_aligned_offset(&x, &y, | |
4086 | plane_state, | |
4087 | ccs_plane); | |
4088 | ||
4089 | plane_state->color_plane[ccs_plane].offset = offset; | |
4090 | plane_state->color_plane[ccs_plane].x = (x * hsub + | |
4091 | src_x % hsub) / | |
4092 | main_hsub; | |
4093 | plane_state->color_plane[ccs_plane].y = (y * vsub + | |
4094 | src_y % vsub) / | |
4095 | main_vsub; | |
4096 | } | |
2e2adb05 VS |
4097 | |
4098 | return 0; | |
4099 | } | |
4100 | ||
73266595 | 4101 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
b63a16f6 | 4102 | { |
7b3cb17a | 4103 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
214bba50 | 4104 | int ret, i; |
b63a16f6 | 4105 | |
54d4d719 | 4106 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
4107 | if (ret) |
4108 | return ret; | |
4109 | ||
f90a85e7 | 4110 | if (!plane_state->uapi.visible) |
a5e4c7d0 VS |
4111 | return 0; |
4112 | ||
8d970654 | 4113 | /* |
2dfbf9d2 DP |
4114 | * Handle the AUX surface first since the main surface setup depends on |
4115 | * it. | |
8d970654 | 4116 | */ |
2dfbf9d2 | 4117 | if (is_ccs_modifier(fb->modifier)) { |
2dfbf9d2 DP |
4118 | ret = skl_check_ccs_aux_surface(plane_state); |
4119 | if (ret) | |
4120 | return ret; | |
4121 | } | |
4122 | ||
4941f35b ID |
4123 | if (intel_format_info_is_yuv_semiplanar(fb->format, |
4124 | fb->modifier)) { | |
8d970654 VS |
4125 | ret = skl_check_nv12_aux_surface(plane_state); |
4126 | if (ret) | |
4127 | return ret; | |
2dfbf9d2 DP |
4128 | } |
4129 | ||
214bba50 VS |
4130 | for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) { |
4131 | plane_state->color_plane[i].offset = ~0xfff; | |
4132 | plane_state->color_plane[i].x = 0; | |
4133 | plane_state->color_plane[i].y = 0; | |
8d970654 VS |
4134 | } |
4135 | ||
73266595 | 4136 | ret = skl_check_main_surface(plane_state); |
b63a16f6 VS |
4137 | if (ret) |
4138 | return ret; | |
4139 | ||
4140 | return 0; | |
4141 | } | |
4142 | ||
bb6ae9e6 VS |
4143 | static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, |
4144 | const struct intel_plane_state *plane_state, | |
4145 | unsigned int *num, unsigned int *den) | |
4146 | { | |
7b3cb17a | 4147 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
bb6ae9e6 VS |
4148 | unsigned int cpp = fb->format->cpp[0]; |
4149 | ||
4150 | /* | |
4151 | * g4x bspec says 64bpp pixel rate can't exceed 80% | |
4152 | * of cdclk when the sprite plane is enabled on the | |
4153 | * same pipe. ilk/snb bspec says 64bpp pixel rate is | |
4154 | * never allowed to exceed 80% of cdclk. Let's just go | |
4155 | * with the ilk/snb limit always. | |
4156 | */ | |
4157 | if (cpp == 8) { | |
4158 | *num = 10; | |
4159 | *den = 8; | |
4160 | } else { | |
4161 | *num = 1; | |
4162 | *den = 1; | |
4163 | } | |
4164 | } | |
4165 | ||
4166 | static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, | |
4167 | const struct intel_plane_state *plane_state) | |
4168 | { | |
4169 | unsigned int pixel_rate; | |
4170 | unsigned int num, den; | |
4171 | ||
4172 | /* | |
4173 | * Note that crtc_state->pixel_rate accounts for both | |
4174 | * horizontal and vertical panel fitter downscaling factors. | |
4175 | * Pre-HSW bspec tells us to only consider the horizontal | |
4176 | * downscaling factor here. We ignore that and just consider | |
4177 | * both for simplicity. | |
4178 | */ | |
4179 | pixel_rate = crtc_state->pixel_rate; | |
4180 | ||
4181 | i9xx_plane_ratio(crtc_state, plane_state, &num, &den); | |
4182 | ||
4183 | /* two pixels per clock with double wide pipe */ | |
4184 | if (crtc_state->double_wide) | |
4185 | den *= 2; | |
4186 | ||
4187 | return DIV_ROUND_UP(pixel_rate * num, den); | |
4188 | } | |
4189 | ||
ddd5713d VS |
4190 | unsigned int |
4191 | i9xx_plane_max_stride(struct intel_plane *plane, | |
4192 | u32 pixel_format, u64 modifier, | |
4193 | unsigned int rotation) | |
4194 | { | |
4195 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
4196 | ||
b2ae318a | 4197 | if (!HAS_GMCH(dev_priv)) { |
ddd5713d VS |
4198 | return 32*1024; |
4199 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
4200 | if (modifier == I915_FORMAT_MOD_X_TILED) | |
4201 | return 16*1024; | |
4202 | else | |
4203 | return 32*1024; | |
4204 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
4205 | if (modifier == I915_FORMAT_MOD_X_TILED) | |
4206 | return 8*1024; | |
4207 | else | |
4208 | return 16*1024; | |
4209 | } else { | |
4210 | if (plane->i9xx_plane == PLANE_C) | |
4211 | return 4*1024; | |
4212 | else | |
4213 | return 8*1024; | |
4214 | } | |
4215 | } | |
4216 | ||
7eb31a0b VS |
4217 | static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4218 | { | |
2225f3c6 | 4219 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7eb31a0b VS |
4220 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4221 | u32 dspcntr = 0; | |
4222 | ||
5f29ab23 VS |
4223 | if (crtc_state->gamma_enable) |
4224 | dspcntr |= DISPPLANE_GAMMA_ENABLE; | |
7eb31a0b | 4225 | |
8271b2ef | 4226 | if (crtc_state->csc_enable) |
7eb31a0b VS |
4227 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
4228 | ||
4229 | if (INTEL_GEN(dev_priv) < 5) | |
4230 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
4231 | ||
4232 | return dspcntr; | |
4233 | } | |
4234 | ||
7145f60a VS |
4235 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
4236 | const struct intel_plane_state *plane_state) | |
81255565 | 4237 | { |
7145f60a | 4238 | struct drm_i915_private *dev_priv = |
f90a85e7 | 4239 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
4240 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4241 | unsigned int rotation = plane_state->hw.rotation; | |
7145f60a | 4242 | u32 dspcntr; |
c9ba6fad | 4243 | |
7eb31a0b | 4244 | dspcntr = DISPLAY_PLANE_ENABLE; |
f45651ba | 4245 | |
cf819eff LDM |
4246 | if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || |
4247 | IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 4248 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 4249 | |
438b74a5 | 4250 | switch (fb->format->format) { |
57779d06 | 4251 | case DRM_FORMAT_C8: |
81255565 JB |
4252 | dspcntr |= DISPPLANE_8BPP; |
4253 | break; | |
57779d06 | 4254 | case DRM_FORMAT_XRGB1555: |
57779d06 | 4255 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 4256 | break; |
73263cb6 VS |
4257 | case DRM_FORMAT_ARGB1555: |
4258 | dspcntr |= DISPPLANE_BGRA555; | |
4259 | break; | |
57779d06 VS |
4260 | case DRM_FORMAT_RGB565: |
4261 | dspcntr |= DISPPLANE_BGRX565; | |
4262 | break; | |
4263 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
4264 | dspcntr |= DISPPLANE_BGRX888; |
4265 | break; | |
4266 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
4267 | dspcntr |= DISPPLANE_RGBX888; |
4268 | break; | |
73263cb6 VS |
4269 | case DRM_FORMAT_ARGB8888: |
4270 | dspcntr |= DISPPLANE_BGRA888; | |
4271 | break; | |
4272 | case DRM_FORMAT_ABGR8888: | |
4273 | dspcntr |= DISPPLANE_RGBA888; | |
4274 | break; | |
57779d06 | 4275 | case DRM_FORMAT_XRGB2101010: |
57779d06 VS |
4276 | dspcntr |= DISPPLANE_BGRX101010; |
4277 | break; | |
4278 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 4279 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 | 4280 | break; |
73263cb6 VS |
4281 | case DRM_FORMAT_ARGB2101010: |
4282 | dspcntr |= DISPPLANE_BGRA101010; | |
4283 | break; | |
4284 | case DRM_FORMAT_ABGR2101010: | |
4285 | dspcntr |= DISPPLANE_RGBA101010; | |
4286 | break; | |
03b0ce95 VS |
4287 | case DRM_FORMAT_XBGR16161616F: |
4288 | dspcntr |= DISPPLANE_RGBX161616; | |
4289 | break; | |
81255565 | 4290 | default: |
7145f60a VS |
4291 | MISSING_CASE(fb->format->format); |
4292 | return 0; | |
81255565 | 4293 | } |
57779d06 | 4294 | |
72618ebf | 4295 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 4296 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 4297 | dspcntr |= DISPPLANE_TILED; |
81255565 | 4298 | |
c2c446ad | 4299 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
4300 | dspcntr |= DISPPLANE_ROTATE_180; |
4301 | ||
c2c446ad | 4302 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
4303 | dspcntr |= DISPPLANE_MIRROR; |
4304 | ||
7145f60a VS |
4305 | return dspcntr; |
4306 | } | |
de1aa629 | 4307 | |
f9407ae1 | 4308 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
4309 | { |
4310 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 4311 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 4312 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
03b0ce95 | 4313 | int src_x, src_y, src_w; |
5b7fcc44 | 4314 | u32 offset; |
fc3fed5d | 4315 | int ret; |
81255565 | 4316 | |
54d4d719 | 4317 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
4318 | if (ret) |
4319 | return ret; | |
4320 | ||
f90a85e7 | 4321 | if (!plane_state->uapi.visible) |
54d4d719 VS |
4322 | return 0; |
4323 | ||
f90a85e7 ML |
4324 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
4325 | src_x = plane_state->uapi.src.x1 >> 16; | |
4326 | src_y = plane_state->uapi.src.y1 >> 16; | |
54d4d719 | 4327 | |
03b0ce95 VS |
4328 | /* Undocumented hardware limit on i965/g4x/vlv/chv */ |
4329 | if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) | |
4330 | return -EINVAL; | |
4331 | ||
5b7fcc44 | 4332 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 4333 | |
5b7fcc44 | 4334 | if (INTEL_GEN(dev_priv) >= 4) |
6d19a44c VS |
4335 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, |
4336 | plane_state, 0); | |
5b7fcc44 VS |
4337 | else |
4338 | offset = 0; | |
4339 | ||
54d4d719 VS |
4340 | /* |
4341 | * Put the final coordinates back so that the src | |
4342 | * coordinate checks will see the right values. | |
4343 | */ | |
f90a85e7 | 4344 | drm_rect_translate_to(&plane_state->uapi.src, |
dcdef1ab | 4345 | src_x << 16, src_y << 16); |
54d4d719 | 4346 | |
5b7fcc44 VS |
4347 | /* HSW/BDW do this automagically in hardware */ |
4348 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
7b3cb17a | 4349 | unsigned int rotation = plane_state->hw.rotation; |
f90a85e7 ML |
4350 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
4351 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
5b7fcc44 | 4352 | |
c2c446ad | 4353 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
4354 | src_x += src_w - 1; |
4355 | src_y += src_h - 1; | |
c2c446ad | 4356 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
4357 | src_x += src_w - 1; |
4358 | } | |
48404c1e SJ |
4359 | } |
4360 | ||
c11ada07 VS |
4361 | plane_state->color_plane[0].offset = offset; |
4362 | plane_state->color_plane[0].x = src_x; | |
4363 | plane_state->color_plane[0].y = src_y; | |
5b7fcc44 VS |
4364 | |
4365 | return 0; | |
4366 | } | |
4367 | ||
26443a4b VS |
4368 | static bool i9xx_plane_has_windowing(struct intel_plane *plane) |
4369 | { | |
4370 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
4371 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
4372 | ||
4373 | if (IS_CHERRYVIEW(dev_priv)) | |
4374 | return i9xx_plane == PLANE_B; | |
4375 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
4376 | return false; | |
4377 | else if (IS_GEN(dev_priv, 4)) | |
4378 | return i9xx_plane == PLANE_C; | |
4379 | else | |
4380 | return i9xx_plane == PLANE_B || | |
4381 | i9xx_plane == PLANE_C; | |
4382 | } | |
4383 | ||
4e0b83a5 VS |
4384 | static int |
4385 | i9xx_plane_check(struct intel_crtc_state *crtc_state, | |
4386 | struct intel_plane_state *plane_state) | |
4387 | { | |
f90a85e7 | 4388 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4e0b83a5 VS |
4389 | int ret; |
4390 | ||
25721f82 VS |
4391 | ret = chv_plane_check_rotation(plane_state); |
4392 | if (ret) | |
4393 | return ret; | |
4394 | ||
f90a85e7 | 4395 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
2225f3c6 | 4396 | &crtc_state->uapi, |
4e0b83a5 VS |
4397 | DRM_PLANE_HELPER_NO_SCALING, |
4398 | DRM_PLANE_HELPER_NO_SCALING, | |
26443a4b VS |
4399 | i9xx_plane_has_windowing(plane), |
4400 | true); | |
4e0b83a5 VS |
4401 | if (ret) |
4402 | return ret; | |
4403 | ||
54d4d719 VS |
4404 | ret = i9xx_check_plane_surface(plane_state); |
4405 | if (ret) | |
4406 | return ret; | |
4407 | ||
f90a85e7 | 4408 | if (!plane_state->uapi.visible) |
4e0b83a5 VS |
4409 | return 0; |
4410 | ||
4411 | ret = intel_plane_check_src_coordinates(plane_state); | |
4412 | if (ret) | |
4413 | return ret; | |
4414 | ||
4e0b83a5 VS |
4415 | plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); |
4416 | ||
4417 | return 0; | |
4418 | } | |
4419 | ||
ed15030d VS |
4420 | static void i9xx_update_plane(struct intel_plane *plane, |
4421 | const struct intel_crtc_state *crtc_state, | |
4422 | const struct intel_plane_state *plane_state) | |
7145f60a | 4423 | { |
ed15030d | 4424 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
ed15030d | 4425 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
7145f60a | 4426 | u32 linear_offset; |
c11ada07 VS |
4427 | int x = plane_state->color_plane[0].x; |
4428 | int y = plane_state->color_plane[0].y; | |
f90a85e7 ML |
4429 | int crtc_x = plane_state->uapi.dst.x1; |
4430 | int crtc_y = plane_state->uapi.dst.y1; | |
4431 | int crtc_w = drm_rect_width(&plane_state->uapi.dst); | |
4432 | int crtc_h = drm_rect_height(&plane_state->uapi.dst); | |
7145f60a | 4433 | unsigned long irqflags; |
e288881b | 4434 | u32 dspaddr_offset; |
7eb31a0b VS |
4435 | u32 dspcntr; |
4436 | ||
4437 | dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); | |
7145f60a | 4438 | |
2949056c | 4439 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 4440 | |
5b7fcc44 | 4441 | if (INTEL_GEN(dev_priv) >= 4) |
c11ada07 | 4442 | dspaddr_offset = plane_state->color_plane[0].offset; |
5b7fcc44 | 4443 | else |
e288881b | 4444 | dspaddr_offset = linear_offset; |
6687c906 | 4445 | |
dd584fc0 VS |
4446 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4447 | ||
dc008bf0 JN |
4448 | intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), |
4449 | plane_state->color_plane[0].stride); | |
83234d13 | 4450 | |
78587de2 | 4451 | if (INTEL_GEN(dev_priv) < 4) { |
26443a4b VS |
4452 | /* |
4453 | * PLANE_A doesn't actually have a full window | |
4454 | * generator but let's assume we still need to | |
4455 | * program whatever is there. | |
78587de2 | 4456 | */ |
dc008bf0 JN |
4457 | intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), |
4458 | (crtc_y << 16) | crtc_x); | |
4459 | intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), | |
4460 | ((crtc_h - 1) << 16) | (crtc_w - 1)); | |
ed15030d | 4461 | } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { |
dc008bf0 JN |
4462 | intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), |
4463 | (crtc_y << 16) | crtc_x); | |
4464 | intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), | |
4465 | ((crtc_h - 1) << 16) | (crtc_w - 1)); | |
4466 | intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); | |
78587de2 VS |
4467 | } |
4468 | ||
3ba35e53 | 4469 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
dc008bf0 JN |
4470 | intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), |
4471 | (y << 16) | x); | |
3ba35e53 | 4472 | } else if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
4473 | intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), |
4474 | linear_offset); | |
4475 | intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), | |
4476 | (y << 16) | x); | |
83234d13 VS |
4477 | } |
4478 | ||
4479 | /* | |
4480 | * The control register self-arms if the plane was previously | |
4481 | * disabled. Try to make the plane enable atomic by writing | |
4482 | * the control register just before the surface register. | |
4483 | */ | |
dc008bf0 | 4484 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); |
83234d13 | 4485 | if (INTEL_GEN(dev_priv) >= 4) |
dc008bf0 JN |
4486 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), |
4487 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); | |
83234d13 | 4488 | else |
dc008bf0 JN |
4489 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), |
4490 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); | |
dd584fc0 VS |
4491 | |
4492 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
4493 | } |
4494 | ||
ed15030d | 4495 | static void i9xx_disable_plane(struct intel_plane *plane, |
0dd14be3 | 4496 | const struct intel_crtc_state *crtc_state) |
17638cd6 | 4497 | { |
ed15030d VS |
4498 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
4499 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
dd584fc0 | 4500 | unsigned long irqflags; |
7eb31a0b VS |
4501 | u32 dspcntr; |
4502 | ||
4503 | /* | |
4504 | * DSPCNTR pipe gamma enable on g4x+ and pipe csc | |
4505 | * enable on ilk+ affect the pipe bottom color as | |
4506 | * well, so we must configure them even if the plane | |
4507 | * is disabled. | |
4508 | * | |
4509 | * On pre-g4x there is no way to gamma correct the | |
4510 | * pipe bottom color but we'll keep on doing this | |
9d5441de | 4511 | * anyway so that the crtc state readout works correctly. |
7eb31a0b VS |
4512 | */ |
4513 | dspcntr = i9xx_plane_ctl_crtc(crtc_state); | |
dd584fc0 VS |
4514 | |
4515 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 4516 | |
dc008bf0 | 4517 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); |
ed15030d | 4518 | if (INTEL_GEN(dev_priv) >= 4) |
dc008bf0 | 4519 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); |
a8d201af | 4520 | else |
dc008bf0 | 4521 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); |
dd584fc0 VS |
4522 | |
4523 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 4524 | } |
c9ba6fad | 4525 | |
eade6c89 VS |
4526 | static bool i9xx_plane_get_hw_state(struct intel_plane *plane, |
4527 | enum pipe *pipe) | |
51f5a096 | 4528 | { |
ed15030d | 4529 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
51f5a096 | 4530 | enum intel_display_power_domain power_domain; |
ed15030d | 4531 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
0e6e0be4 | 4532 | intel_wakeref_t wakeref; |
51f5a096 | 4533 | bool ret; |
eade6c89 | 4534 | u32 val; |
51f5a096 VS |
4535 | |
4536 | /* | |
4537 | * Not 100% correct for planes that can move between pipes, | |
4538 | * but that's only the case for gen2-4 which don't have any | |
4539 | * display power wells. | |
4540 | */ | |
eade6c89 | 4541 | power_domain = POWER_DOMAIN_PIPE(plane->pipe); |
0e6e0be4 CW |
4542 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
4543 | if (!wakeref) | |
51f5a096 VS |
4544 | return false; |
4545 | ||
dc008bf0 | 4546 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
eade6c89 VS |
4547 | |
4548 | ret = val & DISPLAY_PLANE_ENABLE; | |
4549 | ||
4550 | if (INTEL_GEN(dev_priv) >= 5) | |
4551 | *pipe = plane->pipe; | |
4552 | else | |
4553 | *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
4554 | DISPPLANE_SEL_PIPE_SHIFT; | |
51f5a096 | 4555 | |
0e6e0be4 | 4556 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
4557 | |
4558 | return ret; | |
4559 | } | |
4560 | ||
e435d6e5 ML |
4561 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
4562 | { | |
4563 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4564 | struct drm_i915_private *dev_priv = to_i915(dev); |
f986ef2e VS |
4565 | unsigned long irqflags; |
4566 | ||
4567 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
4568 | ||
4569 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
4570 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
4571 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 | 4572 | |
f986ef2e | 4573 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
e435d6e5 ML |
4574 | } |
4575 | ||
a1b2278e CK |
4576 | /* |
4577 | * This function detaches (aka. unbinds) unused scalers in hardware | |
4578 | */ | |
15cbe5d0 | 4579 | static void skl_detach_scalers(const struct intel_crtc_state *crtc_state) |
a1b2278e | 4580 | { |
2225f3c6 | 4581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
15cbe5d0 ML |
4582 | const struct intel_crtc_scaler_state *scaler_state = |
4583 | &crtc_state->scaler_state; | |
a1b2278e CK |
4584 | int i; |
4585 | ||
a1b2278e CK |
4586 | /* loop through and disable scalers that aren't in use */ |
4587 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
4588 | if (!scaler_state->scalers[i].in_use) |
4589 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
4590 | } |
4591 | } | |
4592 | ||
b3cf5c06 VS |
4593 | static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, |
4594 | int color_plane, unsigned int rotation) | |
4595 | { | |
4596 | /* | |
4597 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
4598 | * linear buffers or in number of tiles for tiled buffers. | |
4599 | */ | |
b3e57bcc | 4600 | if (is_surface_linear(fb, color_plane)) |
b3cf5c06 VS |
4601 | return 64; |
4602 | else if (drm_rotation_90_or_270(rotation)) | |
4603 | return intel_tile_height(fb, color_plane); | |
4604 | else | |
4605 | return intel_tile_width_bytes(fb, color_plane); | |
4606 | } | |
4607 | ||
df79cf44 | 4608 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
5d2a1950 | 4609 | int color_plane) |
d2196774 | 4610 | { |
7b3cb17a ML |
4611 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4612 | unsigned int rotation = plane_state->hw.rotation; | |
5d2a1950 | 4613 | u32 stride = plane_state->color_plane[color_plane].stride; |
1b500535 | 4614 | |
5d2a1950 | 4615 | if (color_plane >= fb->format->num_planes) |
1b500535 VS |
4616 | return 0; |
4617 | ||
b3cf5c06 | 4618 | return stride / skl_plane_stride_mult(fb, color_plane, rotation); |
d2196774 VS |
4619 | } |
4620 | ||
ba3f4d0a | 4621 | static u32 skl_plane_ctl_format(u32 pixel_format) |
70d21f0e | 4622 | { |
6156a456 | 4623 | switch (pixel_format) { |
d161cf7a | 4624 | case DRM_FORMAT_C8: |
c34ce3d1 | 4625 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 4626 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 4627 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 4628 | case DRM_FORMAT_XBGR8888: |
4036c78c | 4629 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 4630 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 4631 | case DRM_FORMAT_XRGB8888: |
6156a456 | 4632 | case DRM_FORMAT_ARGB8888: |
4036c78c | 4633 | return PLANE_CTL_FORMAT_XRGB_8888; |
94e35ce2 | 4634 | case DRM_FORMAT_XBGR2101010: |
f9c43a31 | 4635 | case DRM_FORMAT_ABGR2101010: |
94e35ce2 | 4636 | return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; |
70d21f0e | 4637 | case DRM_FORMAT_XRGB2101010: |
f9c43a31 | 4638 | case DRM_FORMAT_ARGB2101010: |
c34ce3d1 | 4639 | return PLANE_CTL_FORMAT_XRGB_2101010; |
a94bed60 KS |
4640 | case DRM_FORMAT_XBGR16161616F: |
4641 | case DRM_FORMAT_ABGR16161616F: | |
4642 | return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; | |
4643 | case DRM_FORMAT_XRGB16161616F: | |
4644 | case DRM_FORMAT_ARGB16161616F: | |
4645 | return PLANE_CTL_FORMAT_XRGB_16161616F; | |
da904174 SL |
4646 | case DRM_FORMAT_XYUV8888: |
4647 | return PLANE_CTL_FORMAT_XYUV; | |
6156a456 | 4648 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 4649 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 4650 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 4651 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 4652 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 4653 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 4654 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 4655 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
77224cd5 CK |
4656 | case DRM_FORMAT_NV12: |
4657 | return PLANE_CTL_FORMAT_NV12; | |
df7d4156 JPH |
4658 | case DRM_FORMAT_P010: |
4659 | return PLANE_CTL_FORMAT_P010; | |
4660 | case DRM_FORMAT_P012: | |
4661 | return PLANE_CTL_FORMAT_P012; | |
4662 | case DRM_FORMAT_P016: | |
4663 | return PLANE_CTL_FORMAT_P016; | |
296e9b19 SS |
4664 | case DRM_FORMAT_Y210: |
4665 | return PLANE_CTL_FORMAT_Y210; | |
4666 | case DRM_FORMAT_Y212: | |
4667 | return PLANE_CTL_FORMAT_Y212; | |
4668 | case DRM_FORMAT_Y216: | |
4669 | return PLANE_CTL_FORMAT_Y216; | |
ff01e697 | 4670 | case DRM_FORMAT_XVYU2101010: |
296e9b19 | 4671 | return PLANE_CTL_FORMAT_Y410; |
ff01e697 | 4672 | case DRM_FORMAT_XVYU12_16161616: |
296e9b19 | 4673 | return PLANE_CTL_FORMAT_Y412; |
ff01e697 | 4674 | case DRM_FORMAT_XVYU16161616: |
296e9b19 | 4675 | return PLANE_CTL_FORMAT_Y416; |
70d21f0e | 4676 | default: |
4249eeef | 4677 | MISSING_CASE(pixel_format); |
70d21f0e | 4678 | } |
8cfcba41 | 4679 | |
c34ce3d1 | 4680 | return 0; |
6156a456 | 4681 | } |
70d21f0e | 4682 | |
b2081525 | 4683 | static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) |
4036c78c | 4684 | { |
7b3cb17a | 4685 | if (!plane_state->hw.fb->format->has_alpha) |
b2081525 ML |
4686 | return PLANE_CTL_ALPHA_DISABLE; |
4687 | ||
7b3cb17a | 4688 | switch (plane_state->hw.pixel_blend_mode) { |
b2081525 ML |
4689 | case DRM_MODE_BLEND_PIXEL_NONE: |
4690 | return PLANE_CTL_ALPHA_DISABLE; | |
4691 | case DRM_MODE_BLEND_PREMULTI: | |
4036c78c | 4692 | return PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
b2081525 ML |
4693 | case DRM_MODE_BLEND_COVERAGE: |
4694 | return PLANE_CTL_ALPHA_HW_PREMULTIPLY; | |
4036c78c | 4695 | default: |
7b3cb17a | 4696 | MISSING_CASE(plane_state->hw.pixel_blend_mode); |
4036c78c JA |
4697 | return PLANE_CTL_ALPHA_DISABLE; |
4698 | } | |
4699 | } | |
4700 | ||
b2081525 | 4701 | static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) |
4036c78c | 4702 | { |
7b3cb17a | 4703 | if (!plane_state->hw.fb->format->has_alpha) |
b2081525 ML |
4704 | return PLANE_COLOR_ALPHA_DISABLE; |
4705 | ||
7b3cb17a | 4706 | switch (plane_state->hw.pixel_blend_mode) { |
b2081525 ML |
4707 | case DRM_MODE_BLEND_PIXEL_NONE: |
4708 | return PLANE_COLOR_ALPHA_DISABLE; | |
4709 | case DRM_MODE_BLEND_PREMULTI: | |
4036c78c | 4710 | return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; |
b2081525 ML |
4711 | case DRM_MODE_BLEND_COVERAGE: |
4712 | return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; | |
4036c78c | 4713 | default: |
7b3cb17a | 4714 | MISSING_CASE(plane_state->hw.pixel_blend_mode); |
4036c78c JA |
4715 | return PLANE_COLOR_ALPHA_DISABLE; |
4716 | } | |
4717 | } | |
4718 | ||
ba3f4d0a | 4719 | static u32 skl_plane_ctl_tiling(u64 fb_modifier) |
6156a456 | 4720 | { |
6156a456 | 4721 | switch (fb_modifier) { |
2f075565 | 4722 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 4723 | break; |
30af77c4 | 4724 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 4725 | return PLANE_CTL_TILED_X; |
b321803d | 4726 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 4727 | return PLANE_CTL_TILED_Y; |
2e2adb05 | 4728 | case I915_FORMAT_MOD_Y_TILED_CCS: |
53867b46 | 4729 | return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; |
b3e57bcc DP |
4730 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: |
4731 | return PLANE_CTL_TILED_Y | | |
4732 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | | |
4733 | PLANE_CTL_CLEAR_COLOR_DISABLE; | |
2dfbf9d2 DP |
4734 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: |
4735 | return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; | |
b321803d | 4736 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 4737 | return PLANE_CTL_TILED_YF; |
2e2adb05 | 4738 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
53867b46 | 4739 | return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; |
70d21f0e | 4740 | default: |
6156a456 | 4741 | MISSING_CASE(fb_modifier); |
70d21f0e | 4742 | } |
8cfcba41 | 4743 | |
c34ce3d1 | 4744 | return 0; |
6156a456 | 4745 | } |
70d21f0e | 4746 | |
5f8e3f57 | 4747 | static u32 skl_plane_ctl_rotate(unsigned int rotate) |
6156a456 | 4748 | { |
5f8e3f57 | 4749 | switch (rotate) { |
c2c446ad | 4750 | case DRM_MODE_ROTATE_0: |
6156a456 | 4751 | break; |
1e8df167 | 4752 | /* |
c2c446ad | 4753 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
4754 | * while i915 HW rotation is clockwise, thats why this swapping. |
4755 | */ | |
c2c446ad | 4756 | case DRM_MODE_ROTATE_90: |
1e8df167 | 4757 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 4758 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 4759 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 4760 | case DRM_MODE_ROTATE_270: |
1e8df167 | 4761 | return PLANE_CTL_ROTATE_90; |
6156a456 | 4762 | default: |
5f8e3f57 JL |
4763 | MISSING_CASE(rotate); |
4764 | } | |
4765 | ||
4766 | return 0; | |
4767 | } | |
4768 | ||
4769 | static u32 cnl_plane_ctl_flip(unsigned int reflect) | |
4770 | { | |
4771 | switch (reflect) { | |
4772 | case 0: | |
4773 | break; | |
4774 | case DRM_MODE_REFLECT_X: | |
4775 | return PLANE_CTL_FLIP_HORIZONTAL; | |
4776 | case DRM_MODE_REFLECT_Y: | |
4777 | default: | |
4778 | MISSING_CASE(reflect); | |
6156a456 CK |
4779 | } |
4780 | ||
c34ce3d1 | 4781 | return 0; |
6156a456 CK |
4782 | } |
4783 | ||
7eb31a0b VS |
4784 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4785 | { | |
2225f3c6 | 4786 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7eb31a0b VS |
4787 | u32 plane_ctl = 0; |
4788 | ||
4789 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
4790 | return plane_ctl; | |
4791 | ||
5f29ab23 VS |
4792 | if (crtc_state->gamma_enable) |
4793 | plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; | |
4794 | ||
8271b2ef VS |
4795 | if (crtc_state->csc_enable) |
4796 | plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; | |
7eb31a0b VS |
4797 | |
4798 | return plane_ctl; | |
4799 | } | |
4800 | ||
2e881264 VS |
4801 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
4802 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
4803 | { |
4804 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 4805 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a ML |
4806 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
4807 | unsigned int rotation = plane_state->hw.rotation; | |
2e881264 | 4808 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
4809 | u32 plane_ctl; |
4810 | ||
4811 | plane_ctl = PLANE_CTL_ENABLE; | |
4812 | ||
4036c78c | 4813 | if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { |
b2081525 | 4814 | plane_ctl |= skl_plane_ctl_alpha(plane_state); |
7eb31a0b | 4815 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
b0f5c0ba | 4816 | |
7b3cb17a | 4817 | if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) |
b0f5c0ba | 4818 | plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; |
c8624ede | 4819 | |
7b3cb17a | 4820 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
c8624ede | 4821 | plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; |
46f788ba VS |
4822 | } |
4823 | ||
4824 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
4825 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
5f8e3f57 JL |
4826 | plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); |
4827 | ||
4828 | if (INTEL_GEN(dev_priv) >= 10) | |
4829 | plane_ctl |= cnl_plane_ctl_flip(rotation & | |
4830 | DRM_MODE_REFLECT_MASK); | |
46f788ba | 4831 | |
2e881264 VS |
4832 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
4833 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
4834 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
4835 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
4836 | ||
46f788ba VS |
4837 | return plane_ctl; |
4838 | } | |
4839 | ||
7eb31a0b VS |
4840 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) |
4841 | { | |
2225f3c6 | 4842 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7eb31a0b VS |
4843 | u32 plane_color_ctl = 0; |
4844 | ||
4845 | if (INTEL_GEN(dev_priv) >= 11) | |
4846 | return plane_color_ctl; | |
4847 | ||
5f29ab23 VS |
4848 | if (crtc_state->gamma_enable) |
4849 | plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; | |
4850 | ||
8271b2ef VS |
4851 | if (crtc_state->csc_enable) |
4852 | plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; | |
7eb31a0b VS |
4853 | |
4854 | return plane_color_ctl; | |
4855 | } | |
4856 | ||
4036c78c JA |
4857 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
4858 | const struct intel_plane_state *plane_state) | |
4859 | { | |
42fd20ed | 4860 | struct drm_i915_private *dev_priv = |
f90a85e7 | 4861 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 4862 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 | 4863 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4036c78c JA |
4864 | u32 plane_color_ctl = 0; |
4865 | ||
4036c78c | 4866 | plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; |
b2081525 | 4867 | plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); |
4036c78c | 4868 | |
42fd20ed | 4869 | if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { |
a0196dd6 KK |
4870 | switch (plane_state->hw.color_encoding) { |
4871 | case DRM_COLOR_YCBCR_BT709: | |
b0f5c0ba | 4872 | plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; |
a0196dd6 KK |
4873 | break; |
4874 | case DRM_COLOR_YCBCR_BT2020: | |
4875 | plane_color_ctl |= | |
4876 | PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; | |
4877 | break; | |
4878 | default: | |
4879 | plane_color_ctl |= | |
4880 | PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; | |
4881 | } | |
7b3cb17a | 4882 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
c8624ede | 4883 | plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; |
bfe60a02 US |
4884 | } else if (fb->format->is_yuv) { |
4885 | plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; | |
b0f5c0ba | 4886 | } |
012d79e6 | 4887 | |
4036c78c JA |
4888 | return plane_color_ctl; |
4889 | } | |
4890 | ||
73974893 ML |
4891 | static int |
4892 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
4893 | struct drm_atomic_state *state, |
4894 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
4895 | { |
4896 | struct drm_crtc_state *crtc_state; | |
4897 | struct drm_crtc *crtc; | |
4898 | int i, ret; | |
11c22da6 | 4899 | |
aecd36b8 | 4900 | intel_modeset_setup_hw_state(dev, ctx); |
4fb87831 | 4901 | intel_vga_redisable(to_i915(dev)); |
73974893 ML |
4902 | |
4903 | if (!state) | |
4904 | return 0; | |
4905 | ||
aa5e9b47 ML |
4906 | /* |
4907 | * We've duplicated the state, pointers to the old state are invalid. | |
4908 | * | |
4909 | * Don't attempt to use the old state until we commit the duplicated state. | |
4910 | */ | |
4911 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
4912 | /* |
4913 | * Force recalculation even if we restore | |
4914 | * current state. With fast modeset this may not result | |
4915 | * in a modeset when the state is compatible. | |
4916 | */ | |
4917 | crtc_state->mode_changed = true; | |
96a02917 | 4918 | } |
73974893 ML |
4919 | |
4920 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
b2ae318a | 4921 | if (!HAS_GMCH(to_i915(dev))) |
602ae835 | 4922 | to_intel_atomic_state(state)->skip_intermediate_wm = true; |
73974893 | 4923 | |
581e49fe | 4924 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 | 4925 | |
e57291c2 | 4926 | drm_WARN_ON(dev, ret == -EDEADLK); |
73974893 | 4927 | return ret; |
96a02917 VS |
4928 | } |
4929 | ||
4ac2ba2f VS |
4930 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
4931 | { | |
55277e1f | 4932 | return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && |
260e6b71 | 4933 | intel_has_gpu_reset(&dev_priv->gt)); |
4ac2ba2f VS |
4934 | } |
4935 | ||
c033666a | 4936 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 4937 | { |
73974893 ML |
4938 | struct drm_device *dev = &dev_priv->drm; |
4939 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
4940 | struct drm_atomic_state *state; | |
4941 | int ret; | |
4942 | ||
ce87ea15 | 4943 | /* reset doesn't touch the display */ |
8a25c4be | 4944 | if (!dev_priv->params.force_reset_modeset_test && |
ce87ea15 DV |
4945 | !gpu_reset_clobbers_display(dev_priv)) |
4946 | return; | |
4947 | ||
9db529aa | 4948 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
cb823ed9 CW |
4949 | set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags); |
4950 | smp_mb__after_atomic(); | |
4951 | wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET); | |
9db529aa DV |
4952 | |
4953 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { | |
cd49f818 WK |
4954 | drm_dbg_kms(&dev_priv->drm, |
4955 | "Modeset potentially stuck, unbreaking through wedging\n"); | |
cb823ed9 | 4956 | intel_gt_set_wedged(&dev_priv->gt); |
9db529aa | 4957 | } |
97154ec2 | 4958 | |
73974893 ML |
4959 | /* |
4960 | * Need mode_config.mutex so that we don't | |
4961 | * trample ongoing ->detect() and whatnot. | |
4962 | */ | |
4963 | mutex_lock(&dev->mode_config.mutex); | |
4964 | drm_modeset_acquire_init(ctx, 0); | |
4965 | while (1) { | |
4966 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
4967 | if (ret != -EDEADLK) | |
4968 | break; | |
4969 | ||
4970 | drm_modeset_backoff(ctx); | |
4971 | } | |
f98ce92f VS |
4972 | /* |
4973 | * Disabling the crtcs gracefully seems nicer. Also the | |
4974 | * g33 docs say we should at least disable all the planes. | |
4975 | */ | |
73974893 ML |
4976 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
4977 | if (IS_ERR(state)) { | |
4978 | ret = PTR_ERR(state); | |
cd49f818 WK |
4979 | drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", |
4980 | ret); | |
1e5a15d6 | 4981 | return; |
73974893 ML |
4982 | } |
4983 | ||
4984 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
4985 | if (ret) { | |
cd49f818 WK |
4986 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", |
4987 | ret); | |
1e5a15d6 ACO |
4988 | drm_atomic_state_put(state); |
4989 | return; | |
73974893 ML |
4990 | } |
4991 | ||
4992 | dev_priv->modeset_restore_state = state; | |
4993 | state->acquire_ctx = ctx; | |
7514747d VS |
4994 | } |
4995 | ||
c033666a | 4996 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 4997 | { |
73974893 ML |
4998 | struct drm_device *dev = &dev_priv->drm; |
4999 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
40da1d31 | 5000 | struct drm_atomic_state *state; |
73974893 ML |
5001 | int ret; |
5002 | ||
ce87ea15 | 5003 | /* reset doesn't touch the display */ |
cb823ed9 | 5004 | if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) |
ce87ea15 DV |
5005 | return; |
5006 | ||
40da1d31 | 5007 | state = fetch_and_zero(&dev_priv->modeset_restore_state); |
ce87ea15 DV |
5008 | if (!state) |
5009 | goto unlock; | |
5010 | ||
7514747d | 5011 | /* reset doesn't touch the display */ |
4ac2ba2f | 5012 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
5013 | /* for testing only restore the display */ |
5014 | ret = __intel_display_resume(dev, state, ctx); | |
942d5d0d | 5015 | if (ret) |
cd49f818 WK |
5016 | drm_err(&dev_priv->drm, |
5017 | "Restoring old state failed with %i\n", ret); | |
73974893 ML |
5018 | } else { |
5019 | /* | |
5020 | * The display has been reset as well, | |
5021 | * so need a full re-initialization. | |
5022 | */ | |
51f59205 | 5023 | intel_pps_unlock_regs_wa(dev_priv); |
6cd02e77 | 5024 | intel_modeset_init_hw(dev_priv); |
f72b84c6 | 5025 | intel_init_clock_gating(dev_priv); |
7514747d | 5026 | |
73974893 ML |
5027 | spin_lock_irq(&dev_priv->irq_lock); |
5028 | if (dev_priv->display.hpd_irq_setup) | |
5029 | dev_priv->display.hpd_irq_setup(dev_priv); | |
5030 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 5031 | |
581e49fe | 5032 | ret = __intel_display_resume(dev, state, ctx); |
73974893 | 5033 | if (ret) |
cd49f818 WK |
5034 | drm_err(&dev_priv->drm, |
5035 | "Restoring old state failed with %i\n", ret); | |
7514747d | 5036 | |
73974893 ML |
5037 | intel_hpd_init(dev_priv); |
5038 | } | |
7514747d | 5039 | |
ce87ea15 DV |
5040 | drm_atomic_state_put(state); |
5041 | unlock: | |
73974893 ML |
5042 | drm_modeset_drop_locks(ctx); |
5043 | drm_modeset_acquire_fini(ctx); | |
5044 | mutex_unlock(&dev->mode_config.mutex); | |
9db529aa | 5045 | |
cb823ed9 | 5046 | clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags); |
7514747d VS |
5047 | } |
5048 | ||
d1622119 VS |
5049 | static void icl_set_pipe_chicken(struct intel_crtc *crtc) |
5050 | { | |
5051 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
5052 | enum pipe pipe = crtc->pipe; | |
5053 | u32 tmp; | |
5054 | ||
dc008bf0 | 5055 | tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); |
d1622119 VS |
5056 | |
5057 | /* | |
5058 | * Display WA #1153: icl | |
5059 | * enable hardware to bypass the alpha math | |
5060 | * and rounding for per-pixel values 00 and 0xff | |
5061 | */ | |
5062 | tmp |= PER_PIXEL_ALPHA_BYPASS_EN; | |
26eeea15 AS |
5063 | /* |
5064 | * Display WA # 1605353570: icl | |
5065 | * Set the pixel rounding bit to 1 for allowing | |
5066 | * passthrough of Frame buffer pixels unmodified | |
5067 | * across pipe | |
5068 | */ | |
5069 | tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; | |
dc008bf0 | 5070 | intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); |
d1622119 VS |
5071 | } |
5072 | ||
4cbe4b2b | 5073 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 5074 | { |
4cbe4b2b | 5075 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5076 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5077 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5078 | i915_reg_t reg; |
5079 | u32 temp; | |
5e84e1a4 ZW |
5080 | |
5081 | /* enable normal train */ | |
5082 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5083 | temp = intel_de_read(dev_priv, reg); |
fd6b8f43 | 5084 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
5085 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
5086 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
5087 | } else { |
5088 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5089 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 5090 | } |
dc008bf0 | 5091 | intel_de_write(dev_priv, reg, temp); |
5e84e1a4 ZW |
5092 | |
5093 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5094 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5095 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
5096 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5097 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
5098 | } else { | |
5099 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5100 | temp |= FDI_LINK_TRAIN_NONE; | |
5101 | } | |
dc008bf0 | 5102 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
5e84e1a4 ZW |
5103 | |
5104 | /* wait one idle pattern time */ | |
dc008bf0 | 5105 | intel_de_posting_read(dev_priv, reg); |
5e84e1a4 | 5106 | udelay(1000); |
357555c0 JB |
5107 | |
5108 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 5109 | if (IS_IVYBRIDGE(dev_priv)) |
dc008bf0 JN |
5110 | intel_de_write(dev_priv, reg, |
5111 | intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
5112 | } |
5113 | ||
8db9d77b | 5114 | /* The FDI link training functions for ILK/Ibexpeak. */ |
9eae5e27 LDM |
5115 | static void ilk_fdi_link_train(struct intel_crtc *crtc, |
5116 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 5117 | { |
4cbe4b2b | 5118 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5119 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5120 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5121 | i915_reg_t reg; |
5122 | u32 temp, tries; | |
8db9d77b | 5123 | |
1c8562f6 | 5124 | /* FDI needs bits from pipe first */ |
b104e8b2 | 5125 | assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder); |
0fc932b8 | 5126 | |
e1a44743 AJ |
5127 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
5128 | for train result */ | |
5eddb70b | 5129 | reg = FDI_RX_IMR(pipe); |
dc008bf0 | 5130 | temp = intel_de_read(dev_priv, reg); |
e1a44743 AJ |
5131 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5132 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 JN |
5133 | intel_de_write(dev_priv, reg, temp); |
5134 | intel_de_read(dev_priv, reg); | |
e1a44743 AJ |
5135 | udelay(150); |
5136 | ||
8db9d77b | 5137 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b | 5138 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5139 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5140 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5141 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
5142 | temp &= ~FDI_LINK_TRAIN_NONE; |
5143 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5144 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
8db9d77b | 5145 | |
5eddb70b | 5146 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5147 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5148 | temp &= ~FDI_LINK_TRAIN_NONE; |
5149 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5150 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
5eddb70b | 5151 | |
dc008bf0 | 5152 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5153 | udelay(150); |
5154 | ||
5b2adf89 | 5155 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
dc008bf0 JN |
5156 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), |
5157 | FDI_RX_PHASE_SYNC_POINTER_OVR); | |
5158 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), | |
5159 | FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 5160 | |
5eddb70b | 5161 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 5162 | for (tries = 0; tries < 5; tries++) { |
dc008bf0 | 5163 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5164 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
8db9d77b ZW |
5165 | |
5166 | if ((temp & FDI_RX_BIT_LOCK)) { | |
cd49f818 | 5167 | drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); |
dc008bf0 | 5168 | intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
5169 | break; |
5170 | } | |
8db9d77b | 5171 | } |
e1a44743 | 5172 | if (tries == 5) |
cd49f818 | 5173 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); |
8db9d77b ZW |
5174 | |
5175 | /* Train 2 */ | |
5eddb70b | 5176 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5177 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5178 | temp &= ~FDI_LINK_TRAIN_NONE; |
5179 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
dc008bf0 | 5180 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5181 | |
5eddb70b | 5182 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5183 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5184 | temp &= ~FDI_LINK_TRAIN_NONE; |
5185 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
dc008bf0 | 5186 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5187 | |
dc008bf0 | 5188 | intel_de_posting_read(dev_priv, reg); |
5eddb70b | 5189 | udelay(150); |
8db9d77b | 5190 | |
5eddb70b | 5191 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 5192 | for (tries = 0; tries < 5; tries++) { |
dc008bf0 | 5193 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5194 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
8db9d77b ZW |
5195 | |
5196 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
dc008bf0 JN |
5197 | intel_de_write(dev_priv, reg, |
5198 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 | 5199 | drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); |
8db9d77b ZW |
5200 | break; |
5201 | } | |
8db9d77b | 5202 | } |
e1a44743 | 5203 | if (tries == 5) |
cd49f818 | 5204 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); |
8db9d77b | 5205 | |
cd49f818 | 5206 | drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); |
5c5313c8 | 5207 | |
8db9d77b ZW |
5208 | } |
5209 | ||
0206e353 | 5210 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
5211 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
5212 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
5213 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
5214 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
5215 | }; | |
5216 | ||
5217 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
5218 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
5219 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 5220 | { |
4cbe4b2b | 5221 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5222 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5223 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5224 | i915_reg_t reg; |
5225 | u32 temp, i, retry; | |
8db9d77b | 5226 | |
e1a44743 AJ |
5227 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
5228 | for train result */ | |
5eddb70b | 5229 | reg = FDI_RX_IMR(pipe); |
dc008bf0 | 5230 | temp = intel_de_read(dev_priv, reg); |
e1a44743 AJ |
5231 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5232 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 | 5233 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5234 | |
dc008bf0 | 5235 | intel_de_posting_read(dev_priv, reg); |
e1a44743 AJ |
5236 | udelay(150); |
5237 | ||
8db9d77b | 5238 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b | 5239 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5240 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5241 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5242 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
5243 | temp &= ~FDI_LINK_TRAIN_NONE; |
5244 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5245 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
5246 | /* SNB-B */ | |
5247 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
dc008bf0 | 5248 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
8db9d77b | 5249 | |
dc008bf0 JN |
5250 | intel_de_write(dev_priv, FDI_RX_MISC(pipe), |
5251 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
d74cf324 | 5252 | |
5eddb70b | 5253 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5254 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5255 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
5256 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5257 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
5258 | } else { | |
5259 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5260 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5261 | } | |
dc008bf0 | 5262 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
5eddb70b | 5263 | |
dc008bf0 | 5264 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5265 | udelay(150); |
5266 | ||
0206e353 | 5267 | for (i = 0; i < 4; i++) { |
5eddb70b | 5268 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5269 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5270 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5271 | temp |= snb_b_fdi_train_param[i]; | |
dc008bf0 | 5272 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5273 | |
dc008bf0 | 5274 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5275 | udelay(500); |
5276 | ||
fa37d39e SP |
5277 | for (retry = 0; retry < 5; retry++) { |
5278 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5279 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5280 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
fa37d39e | 5281 | if (temp & FDI_RX_BIT_LOCK) { |
dc008bf0 JN |
5282 | intel_de_write(dev_priv, reg, |
5283 | temp | FDI_RX_BIT_LOCK); | |
cd49f818 WK |
5284 | drm_dbg_kms(&dev_priv->drm, |
5285 | "FDI train 1 done.\n"); | |
fa37d39e SP |
5286 | break; |
5287 | } | |
5288 | udelay(50); | |
8db9d77b | 5289 | } |
fa37d39e SP |
5290 | if (retry < 5) |
5291 | break; | |
8db9d77b ZW |
5292 | } |
5293 | if (i == 4) | |
cd49f818 | 5294 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); |
8db9d77b ZW |
5295 | |
5296 | /* Train 2 */ | |
5eddb70b | 5297 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5298 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5299 | temp &= ~FDI_LINK_TRAIN_NONE; |
5300 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
cf819eff | 5301 | if (IS_GEN(dev_priv, 6)) { |
8db9d77b ZW |
5302 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5303 | /* SNB-B */ | |
5304 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5305 | } | |
dc008bf0 | 5306 | intel_de_write(dev_priv, reg, temp); |
8db9d77b | 5307 | |
5eddb70b | 5308 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5309 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5310 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
5311 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5312 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
5313 | } else { | |
5314 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5315 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5316 | } | |
dc008bf0 | 5317 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5318 | |
dc008bf0 | 5319 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5320 | udelay(150); |
5321 | ||
0206e353 | 5322 | for (i = 0; i < 4; i++) { |
5eddb70b | 5323 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5324 | temp = intel_de_read(dev_priv, reg); |
8db9d77b ZW |
5325 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
5326 | temp |= snb_b_fdi_train_param[i]; | |
dc008bf0 | 5327 | intel_de_write(dev_priv, reg, temp); |
5eddb70b | 5328 | |
dc008bf0 | 5329 | intel_de_posting_read(dev_priv, reg); |
8db9d77b ZW |
5330 | udelay(500); |
5331 | ||
fa37d39e SP |
5332 | for (retry = 0; retry < 5; retry++) { |
5333 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5334 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5335 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
fa37d39e | 5336 | if (temp & FDI_RX_SYMBOL_LOCK) { |
dc008bf0 JN |
5337 | intel_de_write(dev_priv, reg, |
5338 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 WK |
5339 | drm_dbg_kms(&dev_priv->drm, |
5340 | "FDI train 2 done.\n"); | |
fa37d39e SP |
5341 | break; |
5342 | } | |
5343 | udelay(50); | |
8db9d77b | 5344 | } |
fa37d39e SP |
5345 | if (retry < 5) |
5346 | break; | |
8db9d77b ZW |
5347 | } |
5348 | if (i == 4) | |
cd49f818 | 5349 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); |
8db9d77b | 5350 | |
cd49f818 | 5351 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); |
8db9d77b ZW |
5352 | } |
5353 | ||
357555c0 | 5354 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
5355 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
5356 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 5357 | { |
4cbe4b2b | 5358 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5359 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5360 | enum pipe pipe = crtc->pipe; |
f0f59a00 VS |
5361 | i915_reg_t reg; |
5362 | u32 temp, i, j; | |
357555c0 JB |
5363 | |
5364 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
5365 | for train result */ | |
5366 | reg = FDI_RX_IMR(pipe); | |
dc008bf0 | 5367 | temp = intel_de_read(dev_priv, reg); |
357555c0 JB |
5368 | temp &= ~FDI_RX_SYMBOL_LOCK; |
5369 | temp &= ~FDI_RX_BIT_LOCK; | |
dc008bf0 | 5370 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5371 | |
dc008bf0 | 5372 | intel_de_posting_read(dev_priv, reg); |
357555c0 JB |
5373 | udelay(150); |
5374 | ||
cd49f818 | 5375 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", |
dc008bf0 | 5376 | intel_de_read(dev_priv, FDI_RX_IIR(pipe))); |
01a415fd | 5377 | |
139ccd3f JB |
5378 | /* Try each vswing and preemphasis setting twice before moving on */ |
5379 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
5380 | /* disable first in case we need to retry */ | |
5381 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5382 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5383 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
5384 | temp &= ~FDI_TX_ENABLE; | |
dc008bf0 | 5385 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5386 | |
139ccd3f | 5387 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5388 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5389 | temp &= ~FDI_LINK_TRAIN_AUTO; |
5390 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
5391 | temp &= ~FDI_RX_ENABLE; | |
dc008bf0 | 5392 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5393 | |
139ccd3f | 5394 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 | 5395 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5396 | temp = intel_de_read(dev_priv, reg); |
139ccd3f | 5397 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 5398 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 5399 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 5400 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
5401 | temp |= snb_b_fdi_train_param[j/2]; |
5402 | temp |= FDI_COMPOSITE_SYNC; | |
dc008bf0 | 5403 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); |
357555c0 | 5404 | |
dc008bf0 JN |
5405 | intel_de_write(dev_priv, FDI_RX_MISC(pipe), |
5406 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 5407 | |
139ccd3f | 5408 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5409 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5410 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
5411 | temp |= FDI_COMPOSITE_SYNC; | |
dc008bf0 | 5412 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); |
357555c0 | 5413 | |
dc008bf0 | 5414 | intel_de_posting_read(dev_priv, reg); |
139ccd3f | 5415 | udelay(1); /* should be 0.5us */ |
357555c0 | 5416 | |
139ccd3f JB |
5417 | for (i = 0; i < 4; i++) { |
5418 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5419 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5420 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
357555c0 | 5421 | |
139ccd3f | 5422 | if (temp & FDI_RX_BIT_LOCK || |
dc008bf0 JN |
5423 | (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { |
5424 | intel_de_write(dev_priv, reg, | |
5425 | temp | FDI_RX_BIT_LOCK); | |
cd49f818 WK |
5426 | drm_dbg_kms(&dev_priv->drm, |
5427 | "FDI train 1 done, level %i.\n", | |
5428 | i); | |
139ccd3f JB |
5429 | break; |
5430 | } | |
5431 | udelay(1); /* should be 0.5us */ | |
5432 | } | |
5433 | if (i == 4) { | |
cd49f818 WK |
5434 | drm_dbg_kms(&dev_priv->drm, |
5435 | "FDI train 1 fail on vswing %d\n", j / 2); | |
139ccd3f JB |
5436 | continue; |
5437 | } | |
357555c0 | 5438 | |
139ccd3f | 5439 | /* Train 2 */ |
357555c0 | 5440 | reg = FDI_TX_CTL(pipe); |
dc008bf0 | 5441 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5442 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
5443 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
dc008bf0 | 5444 | intel_de_write(dev_priv, reg, temp); |
139ccd3f JB |
5445 | |
5446 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5447 | temp = intel_de_read(dev_priv, reg); |
139ccd3f JB |
5448 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5449 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
dc008bf0 | 5450 | intel_de_write(dev_priv, reg, temp); |
357555c0 | 5451 | |
dc008bf0 | 5452 | intel_de_posting_read(dev_priv, reg); |
139ccd3f | 5453 | udelay(2); /* should be 1.5us */ |
357555c0 | 5454 | |
139ccd3f JB |
5455 | for (i = 0; i < 4; i++) { |
5456 | reg = FDI_RX_IIR(pipe); | |
dc008bf0 | 5457 | temp = intel_de_read(dev_priv, reg); |
cd49f818 | 5458 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); |
357555c0 | 5459 | |
139ccd3f | 5460 | if (temp & FDI_RX_SYMBOL_LOCK || |
dc008bf0 JN |
5461 | (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { |
5462 | intel_de_write(dev_priv, reg, | |
5463 | temp | FDI_RX_SYMBOL_LOCK); | |
cd49f818 WK |
5464 | drm_dbg_kms(&dev_priv->drm, |
5465 | "FDI train 2 done, level %i.\n", | |
5466 | i); | |
139ccd3f JB |
5467 | goto train_done; |
5468 | } | |
5469 | udelay(2); /* should be 1.5us */ | |
357555c0 | 5470 | } |
139ccd3f | 5471 | if (i == 4) |
cd49f818 WK |
5472 | drm_dbg_kms(&dev_priv->drm, |
5473 | "FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 5474 | } |
357555c0 | 5475 | |
139ccd3f | 5476 | train_done: |
cd49f818 | 5477 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); |
357555c0 JB |
5478 | } |
5479 | ||
9eae5e27 | 5480 | static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) |
2c07245f | 5481 | { |
2225f3c6 | 5482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2354c78 | 5483 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
d048a268 | 5484 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 VS |
5485 | i915_reg_t reg; |
5486 | u32 temp; | |
c64e311e | 5487 | |
c98e9dcf | 5488 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b | 5489 | reg = FDI_RX_CTL(pipe); |
dc008bf0 | 5490 | temp = intel_de_read(dev_priv, reg); |
627eb5a3 | 5491 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
b2354c78 | 5492 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
dc008bf0 JN |
5493 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5494 | intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); | |
5eddb70b | 5495 | |
dc008bf0 | 5496 | intel_de_posting_read(dev_priv, reg); |
c98e9dcf JB |
5497 | udelay(200); |
5498 | ||
5499 | /* Switch from Rawclk to PCDclk */ | |
dc008bf0 JN |
5500 | temp = intel_de_read(dev_priv, reg); |
5501 | intel_de_write(dev_priv, reg, temp | FDI_PCDCLK); | |
5eddb70b | 5502 | |
dc008bf0 | 5503 | intel_de_posting_read(dev_priv, reg); |
c98e9dcf JB |
5504 | udelay(200); |
5505 | ||
20749730 PZ |
5506 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
5507 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5508 | temp = intel_de_read(dev_priv, reg); |
20749730 | 5509 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
dc008bf0 | 5510 | intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); |
5eddb70b | 5511 | |
dc008bf0 | 5512 | intel_de_posting_read(dev_priv, reg); |
20749730 | 5513 | udelay(100); |
6be4a607 | 5514 | } |
0e23b99d JB |
5515 | } |
5516 | ||
9eae5e27 | 5517 | static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc) |
88cefb6c DV |
5518 | { |
5519 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 5520 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5521 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 VS |
5522 | i915_reg_t reg; |
5523 | u32 temp; | |
88cefb6c DV |
5524 | |
5525 | /* Switch from PCDclk to Rawclk */ | |
5526 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 JN |
5527 | temp = intel_de_read(dev_priv, reg); |
5528 | intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK); | |
88cefb6c DV |
5529 | |
5530 | /* Disable CPU FDI TX PLL */ | |
5531 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 JN |
5532 | temp = intel_de_read(dev_priv, reg); |
5533 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE); | |
88cefb6c | 5534 | |
dc008bf0 | 5535 | intel_de_posting_read(dev_priv, reg); |
88cefb6c DV |
5536 | udelay(100); |
5537 | ||
5538 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 JN |
5539 | temp = intel_de_read(dev_priv, reg); |
5540 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE); | |
88cefb6c DV |
5541 | |
5542 | /* Wait for the clocks to turn off. */ | |
dc008bf0 | 5543 | intel_de_posting_read(dev_priv, reg); |
88cefb6c DV |
5544 | udelay(100); |
5545 | } | |
5546 | ||
9eae5e27 | 5547 | static void ilk_fdi_disable(struct intel_crtc *crtc) |
0fc932b8 | 5548 | { |
5b4f4e94 VS |
5549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5550 | enum pipe pipe = crtc->pipe; | |
f0f59a00 VS |
5551 | i915_reg_t reg; |
5552 | u32 temp; | |
0fc932b8 JB |
5553 | |
5554 | /* disable CPU FDI tx and PCH FDI rx */ | |
5555 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 JN |
5556 | temp = intel_de_read(dev_priv, reg); |
5557 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE); | |
5558 | intel_de_posting_read(dev_priv, reg); | |
0fc932b8 JB |
5559 | |
5560 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5561 | temp = intel_de_read(dev_priv, reg); |
0fc932b8 | 5562 | temp &= ~(0x7 << 16); |
dc008bf0 JN |
5563 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5564 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); | |
0fc932b8 | 5565 | |
dc008bf0 | 5566 | intel_de_posting_read(dev_priv, reg); |
0fc932b8 JB |
5567 | udelay(100); |
5568 | ||
5569 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 5570 | if (HAS_PCH_IBX(dev_priv)) |
dc008bf0 JN |
5571 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), |
5572 | FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
5573 | |
5574 | /* still set train pattern 1 */ | |
5575 | reg = FDI_TX_CTL(pipe); | |
dc008bf0 | 5576 | temp = intel_de_read(dev_priv, reg); |
0fc932b8 JB |
5577 | temp &= ~FDI_LINK_TRAIN_NONE; |
5578 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
dc008bf0 | 5579 | intel_de_write(dev_priv, reg, temp); |
0fc932b8 JB |
5580 | |
5581 | reg = FDI_RX_CTL(pipe); | |
dc008bf0 | 5582 | temp = intel_de_read(dev_priv, reg); |
6e266956 | 5583 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
5584 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
5585 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
5586 | } else { | |
5587 | temp &= ~FDI_LINK_TRAIN_NONE; | |
5588 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5589 | } | |
5590 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
5591 | temp &= ~(0x07 << 16); | |
dc008bf0 JN |
5592 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5593 | intel_de_write(dev_priv, reg, temp); | |
0fc932b8 | 5594 | |
dc008bf0 | 5595 | intel_de_posting_read(dev_priv, reg); |
0fc932b8 JB |
5596 | udelay(100); |
5597 | } | |
5598 | ||
49d73912 | 5599 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 5600 | { |
fa05887a DV |
5601 | struct drm_crtc *crtc; |
5602 | bool cleanup_done; | |
5603 | ||
5604 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
5605 | struct drm_crtc_commit *commit; | |
5606 | spin_lock(&crtc->commit_lock); | |
5607 | commit = list_first_entry_or_null(&crtc->commit_list, | |
5608 | struct drm_crtc_commit, commit_entry); | |
5609 | cleanup_done = commit ? | |
5610 | try_wait_for_completion(&commit->cleanup_done) : true; | |
5611 | spin_unlock(&crtc->commit_lock); | |
5612 | ||
5613 | if (cleanup_done) | |
5dce5b93 CW |
5614 | continue; |
5615 | ||
fa05887a | 5616 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
5617 | |
5618 | return true; | |
5619 | } | |
5620 | ||
5621 | return false; | |
5622 | } | |
5623 | ||
b7076546 | 5624 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
5625 | { |
5626 | u32 temp; | |
5627 | ||
dc008bf0 | 5628 | intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); |
060f02d8 VS |
5629 | |
5630 | mutex_lock(&dev_priv->sb_lock); | |
5631 | ||
5632 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
5633 | temp |= SBI_SSCCTL_DISABLE; | |
5634 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
5635 | ||
5636 | mutex_unlock(&dev_priv->sb_lock); | |
5637 | } | |
5638 | ||
e615efe4 | 5639 | /* Program iCLKIP clock to the desired frequency */ |
c5b36fac | 5640 | static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) |
e615efe4 | 5641 | { |
2225f3c6 | 5642 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
0dcdc382 | 5643 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1326a92c | 5644 | int clock = crtc_state->hw.adjusted_mode.crtc_clock; |
e615efe4 ED |
5645 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
5646 | u32 temp; | |
5647 | ||
060f02d8 | 5648 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 5649 | |
64b46a06 VS |
5650 | /* The iCLK virtual clock root frequency is in MHz, |
5651 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
5652 | * divisors, it is necessary to divide one by another, so we | |
5653 | * convert the virtual clock precision to KHz here for higher | |
5654 | * precision. | |
5655 | */ | |
5656 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
5657 | u32 iclk_virtual_root_freq = 172800 * 1000; |
5658 | u32 iclk_pi_range = 64; | |
64b46a06 | 5659 | u32 desired_divisor; |
e615efe4 | 5660 | |
64b46a06 VS |
5661 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
5662 | clock << auxdiv); | |
5663 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
5664 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 5665 | |
64b46a06 VS |
5666 | /* |
5667 | * Near 20MHz is a corner case which is | |
5668 | * out of range for the 7-bit divisor | |
5669 | */ | |
5670 | if (divsel <= 0x7f) | |
5671 | break; | |
e615efe4 ED |
5672 | } |
5673 | ||
5674 | /* This should not happen with any sane values */ | |
e57291c2 PB |
5675 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
5676 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
5677 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
5678 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
e615efe4 | 5679 | |
cd49f818 WK |
5680 | drm_dbg_kms(&dev_priv->drm, |
5681 | "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
5682 | clock, auxdiv, divsel, phasedir, phaseinc); | |
e615efe4 | 5683 | |
060f02d8 VS |
5684 | mutex_lock(&dev_priv->sb_lock); |
5685 | ||
e615efe4 | 5686 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 5687 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
5688 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
5689 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
5690 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
5691 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
5692 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
5693 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 5694 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
5695 | |
5696 | /* Program SSCAUXDIV */ | |
988d6ee8 | 5697 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
5698 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
5699 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 5700 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
5701 | |
5702 | /* Enable modulator and associated divider */ | |
988d6ee8 | 5703 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 5704 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 5705 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 5706 | |
060f02d8 VS |
5707 | mutex_unlock(&dev_priv->sb_lock); |
5708 | ||
e615efe4 ED |
5709 | /* Wait for initialization time */ |
5710 | udelay(24); | |
5711 | ||
dc008bf0 | 5712 | intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
e615efe4 ED |
5713 | } |
5714 | ||
8802e5b6 VS |
5715 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
5716 | { | |
5717 | u32 divsel, phaseinc, auxdiv; | |
5718 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
5719 | u32 iclk_pi_range = 64; | |
5720 | u32 desired_divisor; | |
5721 | u32 temp; | |
5722 | ||
dc008bf0 | 5723 | if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) |
8802e5b6 VS |
5724 | return 0; |
5725 | ||
5726 | mutex_lock(&dev_priv->sb_lock); | |
5727 | ||
5728 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
5729 | if (temp & SBI_SSCCTL_DISABLE) { | |
5730 | mutex_unlock(&dev_priv->sb_lock); | |
5731 | return 0; | |
5732 | } | |
5733 | ||
5734 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
5735 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
5736 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
5737 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
5738 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
5739 | ||
5740 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
5741 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
5742 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
5743 | ||
5744 | mutex_unlock(&dev_priv->sb_lock); | |
5745 | ||
5746 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
5747 | ||
5748 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
5749 | desired_divisor << auxdiv); | |
5750 | } | |
5751 | ||
9eae5e27 LDM |
5752 | static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, |
5753 | enum pipe pch_transcoder) | |
275f01b2 | 5754 | { |
2225f3c6 | 5755 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
5e1cdf54 ML |
5756 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5757 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
275f01b2 | 5758 | |
dc008bf0 JN |
5759 | intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), |
5760 | intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); | |
5761 | intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), | |
5762 | intel_de_read(dev_priv, HBLANK(cpu_transcoder))); | |
5763 | intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), | |
5764 | intel_de_read(dev_priv, HSYNC(cpu_transcoder))); | |
275f01b2 | 5765 | |
dc008bf0 JN |
5766 | intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), |
5767 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); | |
5768 | intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), | |
5769 | intel_de_read(dev_priv, VBLANK(cpu_transcoder))); | |
5770 | intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), | |
5771 | intel_de_read(dev_priv, VSYNC(cpu_transcoder))); | |
5772 | intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
5773 | intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); | |
275f01b2 DV |
5774 | } |
5775 | ||
b0b62d84 | 5776 | static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) |
1fbc0d78 | 5777 | { |
ba3f4d0a | 5778 | u32 temp; |
1fbc0d78 | 5779 | |
dc008bf0 | 5780 | temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); |
003632d9 | 5781 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
5782 | return; |
5783 | ||
e57291c2 PB |
5784 | drm_WARN_ON(&dev_priv->drm, |
5785 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & | |
5786 | FDI_RX_ENABLE); | |
5787 | drm_WARN_ON(&dev_priv->drm, | |
5788 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & | |
5789 | FDI_RX_ENABLE); | |
1fbc0d78 | 5790 | |
003632d9 ACO |
5791 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
5792 | if (enable) | |
5793 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5794 | ||
cd49f818 WK |
5795 | drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", |
5796 | enable ? "en" : "dis"); | |
dc008bf0 JN |
5797 | intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); |
5798 | intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); | |
1fbc0d78 DV |
5799 | } |
5800 | ||
74bb98ba | 5801 | static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) |
1fbc0d78 | 5802 | { |
2225f3c6 | 5803 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b0b62d84 | 5804 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1fbc0d78 | 5805 | |
b0b62d84 | 5806 | switch (crtc->pipe) { |
1fbc0d78 DV |
5807 | case PIPE_A: |
5808 | break; | |
5809 | case PIPE_B: | |
b0b62d84 ML |
5810 | if (crtc_state->fdi_lanes > 2) |
5811 | cpt_set_fdi_bc_bifurcation(dev_priv, false); | |
1fbc0d78 | 5812 | else |
b0b62d84 | 5813 | cpt_set_fdi_bc_bifurcation(dev_priv, true); |
1fbc0d78 DV |
5814 | |
5815 | break; | |
5816 | case PIPE_C: | |
b0b62d84 | 5817 | cpt_set_fdi_bc_bifurcation(dev_priv, true); |
1fbc0d78 DV |
5818 | |
5819 | break; | |
5820 | default: | |
5821 | BUG(); | |
5822 | } | |
5823 | } | |
5824 | ||
f606bc6d VS |
5825 | /* |
5826 | * Finds the encoder associated with the given CRTC. This can only be | |
5827 | * used when we know that the CRTC isn't feeding multiple encoders! | |
5828 | */ | |
5829 | static struct intel_encoder * | |
5a0b385e VS |
5830 | intel_get_crtc_new_encoder(const struct intel_atomic_state *state, |
5831 | const struct intel_crtc_state *crtc_state) | |
f606bc6d | 5832 | { |
2225f3c6 | 5833 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f606bc6d VS |
5834 | const struct drm_connector_state *connector_state; |
5835 | const struct drm_connector *connector; | |
5836 | struct intel_encoder *encoder = NULL; | |
5837 | int num_encoders = 0; | |
5838 | int i; | |
5839 | ||
5a0b385e | 5840 | for_each_new_connector_in_state(&state->base, connector, connector_state, i) { |
f606bc6d VS |
5841 | if (connector_state->crtc != &crtc->base) |
5842 | continue; | |
5843 | ||
5844 | encoder = to_intel_encoder(connector_state->best_encoder); | |
5845 | num_encoders++; | |
5846 | } | |
5847 | ||
3a47ae20 PB |
5848 | drm_WARN(encoder->base.dev, num_encoders != 1, |
5849 | "%d encoders for pipe %c\n", | |
5850 | num_encoders, pipe_name(crtc->pipe)); | |
f606bc6d VS |
5851 | |
5852 | return encoder; | |
5853 | } | |
5854 | ||
f67a559d JB |
5855 | /* |
5856 | * Enable PCH resources required for PCH ports: | |
5857 | * - PCH PLLs | |
5858 | * - FDI training & RX/TX | |
5859 | * - update transcoder timings | |
5860 | * - DP transcoding bits | |
5861 | * - transcoder | |
5862 | */ | |
9eae5e27 LDM |
5863 | static void ilk_pch_enable(const struct intel_atomic_state *state, |
5864 | const struct intel_crtc_state *crtc_state) | |
0e23b99d | 5865 | { |
2225f3c6 | 5866 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4cbe4b2b | 5867 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5868 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 5869 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 5870 | u32 temp; |
2c07245f | 5871 | |
ab9412ba | 5872 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 5873 | |
fd6b8f43 | 5874 | if (IS_IVYBRIDGE(dev_priv)) |
74bb98ba | 5875 | ivb_update_fdi_bc_bifurcation(crtc_state); |
1fbc0d78 | 5876 | |
cd986abb DV |
5877 | /* Write the TU size bits before fdi link training, so that error |
5878 | * detection works. */ | |
dc008bf0 JN |
5879 | intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), |
5880 | intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
cd986abb | 5881 | |
c98e9dcf | 5882 | /* For PCH output, training FDI link */ |
dc4a1094 | 5883 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 5884 | |
3ad8a208 DV |
5885 | /* We need to program the right clock selection before writing the pixel |
5886 | * mutliplier into the DPLL. */ | |
6e266956 | 5887 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 5888 | u32 sel; |
4b645f14 | 5889 | |
dc008bf0 | 5890 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
11887397 DV |
5891 | temp |= TRANS_DPLL_ENABLE(pipe); |
5892 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 5893 | if (crtc_state->shared_dpll == |
8106ddbd | 5894 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
5895 | temp |= sel; |
5896 | else | |
5897 | temp &= ~sel; | |
dc008bf0 | 5898 | intel_de_write(dev_priv, PCH_DPLL_SEL, temp); |
c98e9dcf | 5899 | } |
5eddb70b | 5900 | |
3ad8a208 DV |
5901 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
5902 | * transcoder, and we actually should do this to not upset any PCH | |
5903 | * transcoder that already use the clock when we share it. | |
5904 | * | |
5905 | * Note that enable_shared_dpll tries to do the right thing, but | |
5906 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
5907 | * the right LVDS enable sequence. */ | |
65c307fd | 5908 | intel_enable_shared_dpll(crtc_state); |
3ad8a208 | 5909 | |
d9b6cb56 JB |
5910 | /* set transcoder timing, panel must allow it */ |
5911 | assert_panel_unlocked(dev_priv, pipe); | |
9eae5e27 | 5912 | ilk_pch_transcoder_set_timings(crtc_state, pipe); |
8db9d77b | 5913 | |
303b81e0 | 5914 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 5915 | |
c98e9dcf | 5916 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 5917 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 5918 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 5919 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 5920 | &crtc_state->hw.adjusted_mode; |
dc008bf0 | 5921 | u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 5922 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
f67dc6d8 VS |
5923 | enum port port; |
5924 | ||
dc008bf0 | 5925 | temp = intel_de_read(dev_priv, reg); |
5eddb70b | 5926 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
220cad3c EA |
5927 | TRANS_DP_SYNC_MASK | |
5928 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 5929 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 5930 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 5931 | |
9c4edaee | 5932 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 5933 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 5934 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 5935 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf | 5936 | |
5a0b385e | 5937 | port = intel_get_crtc_new_encoder(state, crtc_state)->port; |
e57291c2 | 5938 | drm_WARN_ON(dev, port < PORT_B || port > PORT_D); |
f67dc6d8 | 5939 | temp |= TRANS_DP_PORT_SEL(port); |
2c07245f | 5940 | |
dc008bf0 | 5941 | intel_de_write(dev_priv, reg, temp); |
6be4a607 | 5942 | } |
b52eb4dc | 5943 | |
9eae5e27 | 5944 | ilk_enable_pch_transcoder(crtc_state); |
f67a559d JB |
5945 | } |
5946 | ||
21fd23ac | 5947 | void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 5948 | { |
2225f3c6 | 5949 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
0dcdc382 | 5950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 5951 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 5952 | |
a2196033 | 5953 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 5954 | |
c5b36fac | 5955 | lpt_program_iclkip(crtc_state); |
1507e5bd | 5956 | |
0540e488 | 5957 | /* Set transcoder timing. */ |
9eae5e27 | 5958 | ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); |
1507e5bd | 5959 | |
937bb610 | 5960 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
5961 | } |
5962 | ||
c684fb44 VS |
5963 | static void cpt_verify_modeset(struct drm_i915_private *dev_priv, |
5964 | enum pipe pipe) | |
d4270e57 | 5965 | { |
f0f59a00 | 5966 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
5967 | u32 temp; |
5968 | ||
dc008bf0 | 5969 | temp = intel_de_read(dev_priv, dslreg); |
d4270e57 | 5970 | udelay(500); |
dc008bf0 JN |
5971 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { |
5972 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) | |
cd49f818 WK |
5973 | drm_err(&dev_priv->drm, |
5974 | "mode set failed: pipe %c stuck\n", | |
5975 | pipe_name(pipe)); | |
d4270e57 JB |
5976 | } |
5977 | } | |
5978 | ||
0a59952b VS |
5979 | /* |
5980 | * The hardware phase 0.0 refers to the center of the pixel. | |
5981 | * We want to start from the top/left edge which is phase | |
5982 | * -0.5. That matches how the hardware calculates the scaling | |
5983 | * factors (from top-left of the first pixel to bottom-right | |
5984 | * of the last pixel, as opposed to the pixel centers). | |
5985 | * | |
5986 | * For 4:2:0 subsampled chroma planes we obviously have to | |
5987 | * adjust that so that the chroma sample position lands in | |
5988 | * the right spot. | |
5989 | * | |
5990 | * Note that for packed YCbCr 4:2:2 formats there is no way to | |
5991 | * control chroma siting. The hardware simply replicates the | |
5992 | * chroma samples for both of the luma samples, and thus we don't | |
5993 | * actually get the expected MPEG2 chroma siting convention :( | |
5994 | * The same behaviour is observed on pre-SKL platforms as well. | |
e7a278a3 VS |
5995 | * |
5996 | * Theory behind the formula (note that we ignore sub-pixel | |
5997 | * source coordinates): | |
5998 | * s = source sample position | |
5999 | * d = destination sample position | |
6000 | * | |
6001 | * Downscaling 4:1: | |
6002 | * -0.5 | |
6003 | * | 0.0 | |
6004 | * | | 1.5 (initial phase) | |
6005 | * | | | | |
6006 | * v v v | |
6007 | * | s | s | s | s | | |
6008 | * | d | | |
6009 | * | |
6010 | * Upscaling 1:4: | |
6011 | * -0.5 | |
6012 | * | -0.375 (initial phase) | |
6013 | * | | 0.0 | |
6014 | * | | | | |
6015 | * v v v | |
6016 | * | s | | |
6017 | * | d | d | d | d | | |
0a59952b | 6018 | */ |
e7a278a3 | 6019 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) |
0a59952b VS |
6020 | { |
6021 | int phase = -0x8000; | |
6022 | u16 trip = 0; | |
6023 | ||
6024 | if (chroma_cosited) | |
6025 | phase += (sub - 1) * 0x8000 / sub; | |
6026 | ||
e7a278a3 VS |
6027 | phase += scale / (2 * sub); |
6028 | ||
6029 | /* | |
6030 | * Hardware initial phase limited to [-0.5:1.5]. | |
6031 | * Since the max hardware scale factor is 3.0, we | |
6032 | * should never actually excdeed 1.0 here. | |
6033 | */ | |
6034 | WARN_ON(phase < -0x8000 || phase > 0x18000); | |
6035 | ||
0a59952b VS |
6036 | if (phase < 0) |
6037 | phase = 0x10000 + phase; | |
6038 | else | |
6039 | trip = PS_PHASE_TRIP; | |
6040 | ||
6041 | return ((phase >> 2) & PS_PHASE_MASK) | trip; | |
6042 | } | |
6043 | ||
69f44d3b JN |
6044 | #define SKL_MIN_SRC_W 8 |
6045 | #define SKL_MAX_SRC_W 4096 | |
6046 | #define SKL_MIN_SRC_H 8 | |
6047 | #define SKL_MAX_SRC_H 4096 | |
6048 | #define SKL_MIN_DST_W 8 | |
6049 | #define SKL_MAX_DST_W 4096 | |
6050 | #define SKL_MIN_DST_H 8 | |
6051 | #define SKL_MAX_DST_H 4096 | |
6052 | #define ICL_MAX_SRC_W 5120 | |
6053 | #define ICL_MAX_SRC_H 4096 | |
6054 | #define ICL_MAX_DST_W 5120 | |
6055 | #define ICL_MAX_DST_H 4096 | |
6056 | #define SKL_MIN_YUV_420_SRC_W 16 | |
6057 | #define SKL_MIN_YUV_420_SRC_H 16 | |
6058 | ||
86adf9d7 ML |
6059 | static int |
6060 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 6061 | unsigned int scaler_user, int *scaler_id, |
77224cd5 | 6062 | int src_w, int src_h, int dst_w, int dst_h, |
4941f35b ID |
6063 | const struct drm_format_info *format, |
6064 | u64 modifier, bool need_scaler) | |
a1b2278e | 6065 | { |
86adf9d7 ML |
6066 | struct intel_crtc_scaler_state *scaler_state = |
6067 | &crtc_state->scaler_state; | |
6068 | struct intel_crtc *intel_crtc = | |
2225f3c6 | 6069 | to_intel_crtc(crtc_state->uapi.crtc); |
7f58cbb1 MK |
6070 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
6071 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 6072 | &crtc_state->hw.adjusted_mode; |
6156a456 | 6073 | |
d96a7d2a VS |
6074 | /* |
6075 | * Src coordinates are already rotated by 270 degrees for | |
6076 | * the 90/270 degree plane rotation cases (to match the | |
6077 | * GTT mapping), hence no need to account for rotation here. | |
6078 | */ | |
b1554e23 ML |
6079 | if (src_w != dst_w || src_h != dst_h) |
6080 | need_scaler = true; | |
e5c05931 | 6081 | |
7f58cbb1 MK |
6082 | /* |
6083 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
6084 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
6085 | * Once NV12 is enabled, handle it here while allocating scaler | |
6086 | * for NV12. | |
6087 | */ | |
1326a92c | 6088 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable && |
b1554e23 | 6089 | need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
cd49f818 WK |
6090 | drm_dbg_kms(&dev_priv->drm, |
6091 | "Pipe/Plane scaling not supported with IF-ID mode\n"); | |
7f58cbb1 MK |
6092 | return -EINVAL; |
6093 | } | |
6094 | ||
a1b2278e CK |
6095 | /* |
6096 | * if plane is being disabled or scaler is no more required or force detach | |
6097 | * - free scaler binded to this plane/crtc | |
6098 | * - in order to do this, update crtc->scaler_usage | |
6099 | * | |
6100 | * Here scaler state in crtc_state is set free so that | |
6101 | * scaler can be assigned to other user. Actual register | |
6102 | * update to free the scaler is done in plane/panel-fit programming. | |
6103 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
6104 | */ | |
b1554e23 | 6105 | if (force_detach || !need_scaler) { |
a1b2278e | 6106 | if (*scaler_id >= 0) { |
86adf9d7 | 6107 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
6108 | scaler_state->scalers[*scaler_id].in_use = 0; |
6109 | ||
cd49f818 WK |
6110 | drm_dbg_kms(&dev_priv->drm, |
6111 | "scaler_user index %u.%u: " | |
6112 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
6113 | intel_crtc->pipe, scaler_user, *scaler_id, | |
6114 | scaler_state->scaler_users); | |
a1b2278e CK |
6115 | *scaler_id = -1; |
6116 | } | |
6117 | return 0; | |
6118 | } | |
6119 | ||
4941f35b | 6120 | if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && |
5d794288 | 6121 | (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { |
cd49f818 WK |
6122 | drm_dbg_kms(&dev_priv->drm, |
6123 | "Planar YUV: src dimensions not met\n"); | |
77224cd5 CK |
6124 | return -EINVAL; |
6125 | } | |
6126 | ||
a1b2278e CK |
6127 | /* range checks */ |
6128 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
323301af | 6129 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
2dd24a9c | 6130 | (INTEL_GEN(dev_priv) >= 11 && |
323301af NM |
6131 | (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || |
6132 | dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || | |
2dd24a9c | 6133 | (INTEL_GEN(dev_priv) < 11 && |
323301af NM |
6134 | (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
6135 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { | |
cd49f818 WK |
6136 | drm_dbg_kms(&dev_priv->drm, |
6137 | "scaler_user index %u.%u: src %ux%u dst %ux%u " | |
6138 | "size is out of scaler range\n", | |
6139 | intel_crtc->pipe, scaler_user, src_w, src_h, | |
6140 | dst_w, dst_h); | |
a1b2278e CK |
6141 | return -EINVAL; |
6142 | } | |
6143 | ||
86adf9d7 ML |
6144 | /* mark this plane as a scaler user in crtc_state */ |
6145 | scaler_state->scaler_users |= (1 << scaler_user); | |
cd49f818 WK |
6146 | drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " |
6147 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
6148 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
6149 | scaler_state->scaler_users); | |
86adf9d7 ML |
6150 | |
6151 | return 0; | |
6152 | } | |
6153 | ||
c5a01ec7 | 6154 | static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) |
86adf9d7 | 6155 | { |
c5a01ec7 VS |
6156 | const struct drm_display_mode *adjusted_mode = |
6157 | &crtc_state->hw.adjusted_mode; | |
6158 | int width, height; | |
b1554e23 | 6159 | |
c5a01ec7 | 6160 | if (crtc_state->pch_pfit.enabled) { |
35dd95b4 VS |
6161 | width = drm_rect_width(&crtc_state->pch_pfit.dst); |
6162 | height = drm_rect_height(&crtc_state->pch_pfit.dst); | |
c5a01ec7 VS |
6163 | } else { |
6164 | width = adjusted_mode->crtc_hdisplay; | |
6165 | height = adjusted_mode->crtc_vdisplay; | |
6166 | } | |
86adf9d7 | 6167 | |
c5a01ec7 VS |
6168 | return skl_update_scaler(crtc_state, !crtc_state->hw.active, |
6169 | SKL_CRTC_INDEX, | |
6170 | &crtc_state->scaler_state.scaler_id, | |
6171 | crtc_state->pipe_src_w, crtc_state->pipe_src_h, | |
6172 | width, height, NULL, 0, | |
6173 | crtc_state->pch_pfit.enabled); | |
86adf9d7 ML |
6174 | } |
6175 | ||
6176 | /** | |
6177 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
c38c1455 | 6178 | * @crtc_state: crtc's scaler state |
86adf9d7 ML |
6179 | * @plane_state: atomic plane state to update |
6180 | * | |
6181 | * Return | |
6182 | * 0 - scaler_usage updated successfully | |
6183 | * error - requested scaling cannot be supported or other error condition | |
6184 | */ | |
da20eabd ML |
6185 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
6186 | struct intel_plane_state *plane_state) | |
86adf9d7 | 6187 | { |
da20eabd | 6188 | struct intel_plane *intel_plane = |
f90a85e7 | 6189 | to_intel_plane(plane_state->uapi.plane); |
42fd20ed | 6190 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
7b3cb17a | 6191 | struct drm_framebuffer *fb = plane_state->hw.fb; |
86adf9d7 | 6192 | int ret; |
f90a85e7 | 6193 | bool force_detach = !fb || !plane_state->uapi.visible; |
b1554e23 ML |
6194 | bool need_scaler = false; |
6195 | ||
6196 | /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ | |
42fd20ed | 6197 | if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && |
4941f35b | 6198 | fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) |
b1554e23 | 6199 | need_scaler = true; |
86adf9d7 | 6200 | |
86adf9d7 ML |
6201 | ret = skl_update_scaler(crtc_state, force_detach, |
6202 | drm_plane_index(&intel_plane->base), | |
6203 | &plane_state->scaler_id, | |
f90a85e7 ML |
6204 | drm_rect_width(&plane_state->uapi.src) >> 16, |
6205 | drm_rect_height(&plane_state->uapi.src) >> 16, | |
6206 | drm_rect_width(&plane_state->uapi.dst), | |
6207 | drm_rect_height(&plane_state->uapi.dst), | |
4941f35b ID |
6208 | fb ? fb->format : NULL, |
6209 | fb ? fb->modifier : 0, | |
6210 | need_scaler); | |
86adf9d7 ML |
6211 | |
6212 | if (ret || plane_state->scaler_id < 0) | |
6213 | return ret; | |
6214 | ||
a1b2278e | 6215 | /* check colorkey */ |
6ec5bd34 | 6216 | if (plane_state->ckey.flags) { |
cd49f818 WK |
6217 | drm_dbg_kms(&dev_priv->drm, |
6218 | "[PLANE:%d:%s] scaling with color key not allowed", | |
6219 | intel_plane->base.base.id, | |
6220 | intel_plane->base.name); | |
a1b2278e CK |
6221 | return -EINVAL; |
6222 | } | |
6223 | ||
6224 | /* Check src format */ | |
438b74a5 | 6225 | switch (fb->format->format) { |
86adf9d7 ML |
6226 | case DRM_FORMAT_RGB565: |
6227 | case DRM_FORMAT_XBGR8888: | |
6228 | case DRM_FORMAT_XRGB8888: | |
6229 | case DRM_FORMAT_ABGR8888: | |
6230 | case DRM_FORMAT_ARGB8888: | |
6231 | case DRM_FORMAT_XRGB2101010: | |
6232 | case DRM_FORMAT_XBGR2101010: | |
f9c43a31 VS |
6233 | case DRM_FORMAT_ARGB2101010: |
6234 | case DRM_FORMAT_ABGR2101010: | |
86adf9d7 ML |
6235 | case DRM_FORMAT_YUYV: |
6236 | case DRM_FORMAT_YVYU: | |
6237 | case DRM_FORMAT_UYVY: | |
6238 | case DRM_FORMAT_VYUY: | |
77224cd5 | 6239 | case DRM_FORMAT_NV12: |
da904174 | 6240 | case DRM_FORMAT_XYUV8888: |
df7d4156 JPH |
6241 | case DRM_FORMAT_P010: |
6242 | case DRM_FORMAT_P012: | |
6243 | case DRM_FORMAT_P016: | |
296e9b19 SS |
6244 | case DRM_FORMAT_Y210: |
6245 | case DRM_FORMAT_Y212: | |
6246 | case DRM_FORMAT_Y216: | |
ff01e697 ML |
6247 | case DRM_FORMAT_XVYU2101010: |
6248 | case DRM_FORMAT_XVYU12_16161616: | |
6249 | case DRM_FORMAT_XVYU16161616: | |
86adf9d7 | 6250 | break; |
6e6c155d VS |
6251 | case DRM_FORMAT_XBGR16161616F: |
6252 | case DRM_FORMAT_ABGR16161616F: | |
6253 | case DRM_FORMAT_XRGB16161616F: | |
6254 | case DRM_FORMAT_ARGB16161616F: | |
6255 | if (INTEL_GEN(dev_priv) >= 11) | |
6256 | break; | |
df561f66 | 6257 | fallthrough; |
86adf9d7 | 6258 | default: |
cd49f818 WK |
6259 | drm_dbg_kms(&dev_priv->drm, |
6260 | "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", | |
6261 | intel_plane->base.base.id, intel_plane->base.name, | |
6262 | fb->base.id, fb->format->format); | |
86adf9d7 | 6263 | return -EINVAL; |
a1b2278e CK |
6264 | } |
6265 | ||
a1b2278e CK |
6266 | return 0; |
6267 | } | |
6268 | ||
f6df4d46 | 6269 | void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) |
e435d6e5 | 6270 | { |
cfb627c4 | 6271 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
e435d6e5 ML |
6272 | int i; |
6273 | ||
6274 | for (i = 0; i < crtc->num_scalers; i++) | |
6275 | skl_detach_scaler(crtc, i); | |
6276 | } | |
6277 | ||
f6df4d46 | 6278 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) |
bd2e244f | 6279 | { |
2225f3c6 | 6280 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 6281 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b2562712 ML |
6282 | const struct intel_crtc_scaler_state *scaler_state = |
6283 | &crtc_state->scaler_state; | |
35dd95b4 VS |
6284 | struct drm_rect src = { |
6285 | .x2 = crtc_state->pipe_src_w << 16, | |
6286 | .y2 = crtc_state->pipe_src_h << 16, | |
6287 | }; | |
6288 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; | |
eac9c585 | 6289 | u16 uv_rgb_hphase, uv_rgb_vphase; |
35dd95b4 VS |
6290 | enum pipe pipe = crtc->pipe; |
6291 | int width = drm_rect_width(dst); | |
6292 | int height = drm_rect_height(dst); | |
6293 | int x = dst->x1; | |
6294 | int y = dst->y1; | |
6295 | int hscale, vscale; | |
eac9c585 VS |
6296 | unsigned long irqflags; |
6297 | int id; | |
a1b2278e | 6298 | |
eac9c585 VS |
6299 | if (!crtc_state->pch_pfit.enabled) |
6300 | return; | |
a1b2278e | 6301 | |
eac9c585 VS |
6302 | if (drm_WARN_ON(&dev_priv->drm, |
6303 | crtc_state->scaler_state.scaler_id < 0)) | |
6304 | return; | |
a1b2278e | 6305 | |
35dd95b4 VS |
6306 | hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); |
6307 | vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); | |
e7a278a3 | 6308 | |
eac9c585 VS |
6309 | uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); |
6310 | uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); | |
0a59952b | 6311 | |
eac9c585 | 6312 | id = scaler_state->scaler_id; |
f986ef2e | 6313 | |
eac9c585 | 6314 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
f986ef2e | 6315 | |
eac9c585 VS |
6316 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN | |
6317 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
6318 | intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), | |
6319 | PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); | |
6320 | intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), | |
6321 | PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); | |
6322 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), | |
35dd95b4 | 6323 | x << 16 | y); |
eac9c585 | 6324 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), |
35dd95b4 | 6325 | width << 16 | height); |
f986ef2e | 6326 | |
eac9c585 | 6327 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
bd2e244f JB |
6328 | } |
6329 | ||
9eae5e27 | 6330 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) |
b074cec8 | 6331 | { |
2225f3c6 | 6332 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 6333 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
35dd95b4 | 6334 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; |
d048a268 | 6335 | enum pipe pipe = crtc->pipe; |
35dd95b4 VS |
6336 | int width = drm_rect_width(dst); |
6337 | int height = drm_rect_height(dst); | |
6338 | int x = dst->x1; | |
6339 | int y = dst->y1; | |
b074cec8 | 6340 | |
eac9c585 VS |
6341 | if (!crtc_state->pch_pfit.enabled) |
6342 | return; | |
6343 | ||
6344 | /* Force use of hard-coded filter coefficients | |
6345 | * as some pre-programmed values are broken, | |
6346 | * e.g. x201. | |
6347 | */ | |
6348 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) | |
6349 | intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | | |
6350 | PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); | |
6351 | else | |
6352 | intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | | |
6353 | PF_FILTER_MED_3x3); | |
35dd95b4 VS |
6354 | intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y); |
6355 | intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); | |
d4270e57 JB |
6356 | } |
6357 | ||
199ea381 | 6358 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state) |
d77e4531 | 6359 | { |
2225f3c6 | 6360 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
cea165c3 | 6361 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6362 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 6363 | |
24f28450 | 6364 | if (!crtc_state->ips_enabled) |
d77e4531 PZ |
6365 | return; |
6366 | ||
307e4498 ML |
6367 | /* |
6368 | * We can only enable IPS after we enable a plane and wait for a vblank | |
6369 | * This function is called from post_plane_update, which is run after | |
6370 | * a vblank wait. | |
6371 | */ | |
e57291c2 | 6372 | drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); |
51f5a096 | 6373 | |
8652744b | 6374 | if (IS_BROADWELL(dev_priv)) { |
e57291c2 PB |
6375 | drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, |
6376 | IPS_ENABLE | IPS_PCODE_CONTROL)); | |
2a114cc1 BW |
6377 | /* Quoting Art Runyan: "its not safe to expect any particular |
6378 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
6379 | * mailbox." Moreover, the mailbox may return a bogus state, |
6380 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
6381 | */ |
6382 | } else { | |
dc008bf0 | 6383 | intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE); |
2a114cc1 BW |
6384 | /* The bit only becomes 1 in the next vblank, so this wait here |
6385 | * is essentially intel_wait_for_vblank. If we don't have this | |
6386 | * and don't wait for vblanks until the end of crtc_enable, then | |
6387 | * the HW state readout code will complain that the expected | |
6388 | * IPS_CTL value is not the one we read. */ | |
4cb3b44d | 6389 | if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50)) |
cd49f818 WK |
6390 | drm_err(&dev_priv->drm, |
6391 | "Timed out waiting for IPS enable\n"); | |
2a114cc1 | 6392 | } |
d77e4531 PZ |
6393 | } |
6394 | ||
199ea381 | 6395 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state) |
d77e4531 | 6396 | { |
2225f3c6 | 6397 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
d77e4531 | 6398 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6399 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 6400 | |
199ea381 | 6401 | if (!crtc_state->ips_enabled) |
d77e4531 PZ |
6402 | return; |
6403 | ||
8652744b | 6404 | if (IS_BROADWELL(dev_priv)) { |
e57291c2 PB |
6405 | drm_WARN_ON(dev, |
6406 | sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
acb3ef0e ID |
6407 | /* |
6408 | * Wait for PCODE to finish disabling IPS. The BSpec specified | |
6409 | * 42ms timeout value leads to occasional timeouts so use 100ms | |
6410 | * instead. | |
6411 | */ | |
4cb3b44d | 6412 | if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100)) |
cd49f818 WK |
6413 | drm_err(&dev_priv->drm, |
6414 | "Timed out waiting for IPS disable\n"); | |
e59150dc | 6415 | } else { |
dc008bf0 JN |
6416 | intel_de_write(dev_priv, IPS_CTL, 0); |
6417 | intel_de_posting_read(dev_priv, IPS_CTL); | |
e59150dc | 6418 | } |
d77e4531 PZ |
6419 | |
6420 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 6421 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
6422 | } |
6423 | ||
7cac945f | 6424 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 6425 | { |
cb5eb072 | 6426 | if (intel_crtc->overlay) |
d3eedb1a | 6427 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
6428 | |
6429 | /* Let userspace switch the overlay on again. In most cases userspace | |
6430 | * has to recompute where to put it anyway. | |
6431 | */ | |
6432 | } | |
6433 | ||
24f28450 ML |
6434 | static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, |
6435 | const struct intel_crtc_state *new_crtc_state) | |
6436 | { | |
2225f3c6 | 6437 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
051a6d8d VS |
6438 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6439 | ||
24f28450 ML |
6440 | if (!old_crtc_state->ips_enabled) |
6441 | return false; | |
6442 | ||
69f786ae | 6443 | if (needs_modeset(new_crtc_state)) |
24f28450 ML |
6444 | return true; |
6445 | ||
051a6d8d VS |
6446 | /* |
6447 | * Workaround : Do not read or write the pipe palette/gamma data while | |
6448 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6449 | * | |
6450 | * Disable IPS before we program the LUT. | |
6451 | */ | |
6452 | if (IS_HASWELL(dev_priv) && | |
2225f3c6 | 6453 | (new_crtc_state->uapi.color_mgmt_changed || |
051a6d8d VS |
6454 | new_crtc_state->update_pipe) && |
6455 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) | |
6456 | return true; | |
6457 | ||
24f28450 ML |
6458 | return !new_crtc_state->ips_enabled; |
6459 | } | |
6460 | ||
6461 | static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, | |
6462 | const struct intel_crtc_state *new_crtc_state) | |
6463 | { | |
2225f3c6 | 6464 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
051a6d8d VS |
6465 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6466 | ||
24f28450 ML |
6467 | if (!new_crtc_state->ips_enabled) |
6468 | return false; | |
6469 | ||
69f786ae | 6470 | if (needs_modeset(new_crtc_state)) |
24f28450 ML |
6471 | return true; |
6472 | ||
051a6d8d VS |
6473 | /* |
6474 | * Workaround : Do not read or write the pipe palette/gamma data while | |
6475 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6476 | * | |
6477 | * Re-enable IPS after the LUT has been programmed. | |
6478 | */ | |
6479 | if (IS_HASWELL(dev_priv) && | |
2225f3c6 | 6480 | (new_crtc_state->uapi.color_mgmt_changed || |
051a6d8d VS |
6481 | new_crtc_state->update_pipe) && |
6482 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) | |
6483 | return true; | |
6484 | ||
24f28450 ML |
6485 | /* |
6486 | * We can't read out IPS on broadwell, assume the worst and | |
6487 | * forcibly enable IPS on the first fastset. | |
6488 | */ | |
a227569d | 6489 | if (new_crtc_state->update_pipe && old_crtc_state->inherited) |
24f28450 ML |
6490 | return true; |
6491 | ||
6492 | return !old_crtc_state->ips_enabled; | |
6493 | } | |
6494 | ||
d2432796 | 6495 | static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) |
8e021151 | 6496 | { |
d2432796 VS |
6497 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
6498 | ||
8e021151 ML |
6499 | if (!crtc_state->nv12_planes) |
6500 | return false; | |
6501 | ||
1347d3ce | 6502 | /* WA Display #0827: Gen9:all */ |
cf819eff | 6503 | if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) |
8e021151 ML |
6504 | return true; |
6505 | ||
6506 | return false; | |
6507 | } | |
6508 | ||
d2432796 | 6509 | static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) |
51eb1a1d | 6510 | { |
d2432796 VS |
6511 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
6512 | ||
f96198ab MA |
6513 | /* Wa_2006604312:icl,ehl */ |
6514 | if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11)) | |
51eb1a1d RS |
6515 | return true; |
6516 | ||
6517 | return false; | |
6518 | } | |
6519 | ||
7181f5c5 VS |
6520 | static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, |
6521 | const struct intel_crtc_state *new_crtc_state) | |
6522 | { | |
6523 | return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) && | |
6524 | new_crtc_state->active_planes; | |
6525 | } | |
6526 | ||
6527 | static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, | |
6528 | const struct intel_crtc_state *new_crtc_state) | |
6529 | { | |
6530 | return old_crtc_state->active_planes && | |
6531 | (!new_crtc_state->active_planes || needs_modeset(new_crtc_state)); | |
6532 | } | |
6533 | ||
bee43ca4 VS |
6534 | static void intel_post_plane_update(struct intel_atomic_state *state, |
6535 | struct intel_crtc *crtc) | |
5a21b665 | 6536 | { |
bee43ca4 | 6537 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
bee43ca4 VS |
6538 | const struct intel_crtc_state *old_crtc_state = |
6539 | intel_atomic_get_old_crtc_state(state, crtc); | |
6540 | const struct intel_crtc_state *new_crtc_state = | |
6541 | intel_atomic_get_new_crtc_state(state, crtc); | |
7181f5c5 | 6542 | enum pipe pipe = crtc->pipe; |
5a21b665 | 6543 | |
bee43ca4 | 6544 | intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); |
5a21b665 | 6545 | |
0e75fb8c | 6546 | if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) |
432081bc | 6547 | intel_update_watermarks(crtc); |
5a21b665 | 6548 | |
0e75fb8c VS |
6549 | if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state)) |
6550 | hsw_enable_ips(new_crtc_state); | |
24f28450 | 6551 | |
9ecc6eab | 6552 | intel_fbc_post_update(state, crtc); |
5a21b665 | 6553 | |
d2432796 | 6554 | if (needs_nv12_wa(old_crtc_state) && |
0e75fb8c | 6555 | !needs_nv12_wa(new_crtc_state)) |
7181f5c5 | 6556 | skl_wa_827(dev_priv, pipe, false); |
51eb1a1d | 6557 | |
d2432796 | 6558 | if (needs_scalerclk_wa(old_crtc_state) && |
0e75fb8c | 6559 | !needs_scalerclk_wa(new_crtc_state)) |
7181f5c5 | 6560 | icl_wa_scalerclkgating(dev_priv, pipe, false); |
5a21b665 DV |
6561 | } |
6562 | ||
bee43ca4 VS |
6563 | static void intel_pre_plane_update(struct intel_atomic_state *state, |
6564 | struct intel_crtc *crtc) | |
ac21b225 | 6565 | { |
bee43ca4 | 6566 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
bee43ca4 VS |
6567 | const struct intel_crtc_state *old_crtc_state = |
6568 | intel_atomic_get_old_crtc_state(state, crtc); | |
6569 | const struct intel_crtc_state *new_crtc_state = | |
6570 | intel_atomic_get_new_crtc_state(state, crtc); | |
7181f5c5 | 6571 | enum pipe pipe = crtc->pipe; |
ac21b225 | 6572 | |
0e75fb8c | 6573 | if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state)) |
24f28450 ML |
6574 | hsw_disable_ips(old_crtc_state); |
6575 | ||
9ecc6eab | 6576 | if (intel_fbc_pre_update(state, crtc)) |
07fd0df8 VS |
6577 | intel_wait_for_vblank(dev_priv, pipe); |
6578 | ||
8e021151 | 6579 | /* Display WA 827 */ |
d2432796 | 6580 | if (!needs_nv12_wa(old_crtc_state) && |
0e75fb8c | 6581 | needs_nv12_wa(new_crtc_state)) |
7181f5c5 | 6582 | skl_wa_827(dev_priv, pipe, true); |
51eb1a1d | 6583 | |
f96198ab | 6584 | /* Wa_2006604312:icl,ehl */ |
d2432796 | 6585 | if (!needs_scalerclk_wa(old_crtc_state) && |
0e75fb8c | 6586 | needs_scalerclk_wa(new_crtc_state)) |
7181f5c5 | 6587 | icl_wa_scalerclkgating(dev_priv, pipe, true); |
8e021151 | 6588 | |
5eeb798b VS |
6589 | /* |
6590 | * Vblank time updates from the shadow to live plane control register | |
6591 | * are blocked if the memory self-refresh mode is active at that | |
6592 | * moment. So to make sure the plane gets truly disabled, disable | |
6593 | * first the self-refresh mode. The self-refresh enable bit in turn | |
6594 | * will be checked/applied by the HW only at the next frame start | |
6595 | * event which is after the vblank start event, so we need to have a | |
6596 | * wait-for-vblank between disabling the plane and the pipe. | |
6597 | */ | |
1326a92c | 6598 | if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && |
0e75fb8c | 6599 | new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) |
7181f5c5 | 6600 | intel_wait_for_vblank(dev_priv, pipe); |
92826fcd | 6601 | |
ed4a6a7c MR |
6602 | /* |
6603 | * IVB workaround: must disable low power watermarks for at least | |
6604 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
6605 | * when scaling is disabled. | |
6606 | * | |
6607 | * WaCxSRDisabledForSpriteScaling:ivb | |
6608 | */ | |
0e75fb8c VS |
6609 | if (old_crtc_state->hw.active && |
6610 | new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) | |
7181f5c5 | 6611 | intel_wait_for_vblank(dev_priv, pipe); |
ed4a6a7c MR |
6612 | |
6613 | /* | |
7181f5c5 VS |
6614 | * If we're doing a modeset we don't need to do any |
6615 | * pre-vblank watermark programming here. | |
ed4a6a7c | 6616 | */ |
7181f5c5 VS |
6617 | if (!needs_modeset(new_crtc_state)) { |
6618 | /* | |
6619 | * For platforms that support atomic watermarks, program the | |
6620 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
6621 | * will be the intermediate values that are safe for both pre- and | |
6622 | * post- vblank; when vblank happens, the 'active' values will be set | |
6623 | * to the final 'target' values and we'll do this again to get the | |
6624 | * optimal watermarks. For gen9+ platforms, the values we program here | |
6625 | * will be the final target values which will get automatically latched | |
6626 | * at vblank time; no further programming will be necessary. | |
6627 | * | |
6628 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
6629 | * we'll continue to update watermarks the old way, if flags tell | |
6630 | * us to. | |
6631 | */ | |
6632 | if (dev_priv->display.initial_watermarks) | |
6633 | dev_priv->display.initial_watermarks(state, crtc); | |
6634 | else if (new_crtc_state->update_wm_pre) | |
6635 | intel_update_watermarks(crtc); | |
6636 | } | |
ed4a6a7c MR |
6637 | |
6638 | /* | |
7181f5c5 VS |
6639 | * Gen2 reports pipe underruns whenever all planes are disabled. |
6640 | * So disable underrun reporting before all the planes get disabled. | |
ed4a6a7c | 6641 | * |
7181f5c5 VS |
6642 | * We do this after .initial_watermarks() so that we have a |
6643 | * chance of catching underruns with the intermediate watermarks | |
6644 | * vs. the old plane configuration. | |
ed4a6a7c | 6645 | */ |
7181f5c5 VS |
6646 | if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state)) |
6647 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ac21b225 ML |
6648 | } |
6649 | ||
0dd14be3 VS |
6650 | static void intel_crtc_disable_planes(struct intel_atomic_state *state, |
6651 | struct intel_crtc *crtc) | |
87d4300a | 6652 | { |
0dd14be3 VS |
6653 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6654 | const struct intel_crtc_state *new_crtc_state = | |
6655 | intel_atomic_get_new_crtc_state(state, crtc); | |
6656 | unsigned int update_mask = new_crtc_state->update_planes; | |
6657 | const struct intel_plane_state *old_plane_state; | |
f59e9701 ML |
6658 | struct intel_plane *plane; |
6659 | unsigned fb_bits = 0; | |
0dd14be3 | 6660 | int i; |
87d4300a | 6661 | |
f59e9701 | 6662 | intel_crtc_dpms_overlay_disable(crtc); |
27321ae8 | 6663 | |
0dd14be3 VS |
6664 | for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { |
6665 | if (crtc->pipe != plane->pipe || | |
6666 | !(update_mask & BIT(plane->id))) | |
6667 | continue; | |
6668 | ||
c48b86f9 | 6669 | intel_disable_plane(plane, new_crtc_state); |
f98551ae | 6670 | |
f90a85e7 | 6671 | if (old_plane_state->uapi.visible) |
f59e9701 | 6672 | fb_bits |= plane->frontbuffer_bit; |
f59e9701 ML |
6673 | } |
6674 | ||
0dd14be3 | 6675 | intel_frontbuffer_flip(dev_priv, fb_bits); |
a5c4d7bc VS |
6676 | } |
6677 | ||
24a7bfe0 ID |
6678 | /* |
6679 | * intel_connector_primary_encoder - get the primary encoder for a connector | |
6680 | * @connector: connector for which to return the encoder | |
6681 | * | |
6682 | * Returns the primary encoder for a connector. There is a 1:1 mapping from | |
6683 | * all connectors to their encoder, except for DP-MST connectors which have | |
6684 | * both a virtual and a primary encoder. These DP-MST primary encoders can be | |
6685 | * pointed to by as many DP-MST connectors as there are pipes. | |
6686 | */ | |
6687 | static struct intel_encoder * | |
6688 | intel_connector_primary_encoder(struct intel_connector *connector) | |
6689 | { | |
6690 | struct intel_encoder *encoder; | |
6691 | ||
6692 | if (connector->mst_port) | |
6693 | return &dp_to_dig_port(connector->mst_port)->base; | |
6694 | ||
43a6d19c | 6695 | encoder = intel_attached_encoder(connector); |
ce04ecd9 | 6696 | drm_WARN_ON(connector->base.dev, !encoder); |
24a7bfe0 ID |
6697 | |
6698 | return encoder; | |
6699 | } | |
6700 | ||
24a7bfe0 ID |
6701 | static void intel_encoders_update_prepare(struct intel_atomic_state *state) |
6702 | { | |
24a7bfe0 | 6703 | struct drm_connector_state *new_conn_state; |
ee36c7c0 | 6704 | struct drm_connector *connector; |
24a7bfe0 ID |
6705 | int i; |
6706 | ||
ee36c7c0 JRS |
6707 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, |
6708 | i) { | |
6709 | struct intel_connector *intel_connector; | |
24a7bfe0 ID |
6710 | struct intel_encoder *encoder; |
6711 | struct intel_crtc *crtc; | |
6712 | ||
ee36c7c0 | 6713 | if (!intel_connector_needs_modeset(state, connector)) |
24a7bfe0 ID |
6714 | continue; |
6715 | ||
ee36c7c0 JRS |
6716 | intel_connector = to_intel_connector(connector); |
6717 | encoder = intel_connector_primary_encoder(intel_connector); | |
24a7bfe0 ID |
6718 | if (!encoder->update_prepare) |
6719 | continue; | |
6720 | ||
6721 | crtc = new_conn_state->crtc ? | |
6722 | to_intel_crtc(new_conn_state->crtc) : NULL; | |
6723 | encoder->update_prepare(state, encoder, crtc); | |
6724 | } | |
6725 | } | |
6726 | ||
6727 | static void intel_encoders_update_complete(struct intel_atomic_state *state) | |
6728 | { | |
24a7bfe0 | 6729 | struct drm_connector_state *new_conn_state; |
ee36c7c0 | 6730 | struct drm_connector *connector; |
24a7bfe0 ID |
6731 | int i; |
6732 | ||
ee36c7c0 JRS |
6733 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, |
6734 | i) { | |
6735 | struct intel_connector *intel_connector; | |
24a7bfe0 ID |
6736 | struct intel_encoder *encoder; |
6737 | struct intel_crtc *crtc; | |
6738 | ||
ee36c7c0 | 6739 | if (!intel_connector_needs_modeset(state, connector)) |
24a7bfe0 ID |
6740 | continue; |
6741 | ||
ee36c7c0 JRS |
6742 | intel_connector = to_intel_connector(connector); |
6743 | encoder = intel_connector_primary_encoder(intel_connector); | |
24a7bfe0 ID |
6744 | if (!encoder->update_complete) |
6745 | continue; | |
6746 | ||
6747 | crtc = new_conn_state->crtc ? | |
6748 | to_intel_crtc(new_conn_state->crtc) : NULL; | |
6749 | encoder->update_complete(state, encoder, crtc); | |
6750 | } | |
6751 | } | |
6752 | ||
021ba100 VS |
6753 | static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, |
6754 | struct intel_crtc *crtc) | |
fb1c98b1 | 6755 | { |
021ba100 VS |
6756 | const struct intel_crtc_state *crtc_state = |
6757 | intel_atomic_get_new_crtc_state(state, crtc); | |
6758 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6759 | struct drm_connector *conn; |
6760 | int i; | |
6761 | ||
855e0d68 | 6762 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6763 | struct intel_encoder *encoder = |
6764 | to_intel_encoder(conn_state->best_encoder); | |
6765 | ||
855e0d68 | 6766 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6767 | continue; |
6768 | ||
6769 | if (encoder->pre_pll_enable) | |
ede9771d VS |
6770 | encoder->pre_pll_enable(state, encoder, |
6771 | crtc_state, conn_state); | |
fb1c98b1 ML |
6772 | } |
6773 | } | |
6774 | ||
021ba100 VS |
6775 | static void intel_encoders_pre_enable(struct intel_atomic_state *state, |
6776 | struct intel_crtc *crtc) | |
fb1c98b1 | 6777 | { |
021ba100 VS |
6778 | const struct intel_crtc_state *crtc_state = |
6779 | intel_atomic_get_new_crtc_state(state, crtc); | |
6780 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6781 | struct drm_connector *conn; |
6782 | int i; | |
6783 | ||
855e0d68 | 6784 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6785 | struct intel_encoder *encoder = |
6786 | to_intel_encoder(conn_state->best_encoder); | |
6787 | ||
855e0d68 | 6788 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6789 | continue; |
6790 | ||
6791 | if (encoder->pre_enable) | |
ede9771d VS |
6792 | encoder->pre_enable(state, encoder, |
6793 | crtc_state, conn_state); | |
fb1c98b1 ML |
6794 | } |
6795 | } | |
6796 | ||
021ba100 VS |
6797 | static void intel_encoders_enable(struct intel_atomic_state *state, |
6798 | struct intel_crtc *crtc) | |
fb1c98b1 | 6799 | { |
021ba100 VS |
6800 | const struct intel_crtc_state *crtc_state = |
6801 | intel_atomic_get_new_crtc_state(state, crtc); | |
6802 | const struct drm_connector_state *conn_state; | |
fb1c98b1 ML |
6803 | struct drm_connector *conn; |
6804 | int i; | |
6805 | ||
855e0d68 | 6806 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
fb1c98b1 ML |
6807 | struct intel_encoder *encoder = |
6808 | to_intel_encoder(conn_state->best_encoder); | |
6809 | ||
855e0d68 | 6810 | if (conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6811 | continue; |
6812 | ||
c84c6fe3 | 6813 | if (encoder->enable) |
ede9771d VS |
6814 | encoder->enable(state, encoder, |
6815 | crtc_state, conn_state); | |
fb1c98b1 ML |
6816 | intel_opregion_notify_encoder(encoder, true); |
6817 | } | |
6818 | } | |
6819 | ||
021ba100 VS |
6820 | static void intel_encoders_disable(struct intel_atomic_state *state, |
6821 | struct intel_crtc *crtc) | |
fb1c98b1 | 6822 | { |
021ba100 VS |
6823 | const struct intel_crtc_state *old_crtc_state = |
6824 | intel_atomic_get_old_crtc_state(state, crtc); | |
6825 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6826 | struct drm_connector *conn; |
6827 | int i; | |
6828 | ||
855e0d68 | 6829 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6830 | struct intel_encoder *encoder = |
6831 | to_intel_encoder(old_conn_state->best_encoder); | |
6832 | ||
855e0d68 | 6833 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6834 | continue; |
6835 | ||
6836 | intel_opregion_notify_encoder(encoder, false); | |
c84c6fe3 | 6837 | if (encoder->disable) |
ede9771d VS |
6838 | encoder->disable(state, encoder, |
6839 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6840 | } |
6841 | } | |
6842 | ||
021ba100 VS |
6843 | static void intel_encoders_post_disable(struct intel_atomic_state *state, |
6844 | struct intel_crtc *crtc) | |
fb1c98b1 | 6845 | { |
021ba100 VS |
6846 | const struct intel_crtc_state *old_crtc_state = |
6847 | intel_atomic_get_old_crtc_state(state, crtc); | |
6848 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6849 | struct drm_connector *conn; |
6850 | int i; | |
6851 | ||
855e0d68 | 6852 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6853 | struct intel_encoder *encoder = |
6854 | to_intel_encoder(old_conn_state->best_encoder); | |
6855 | ||
855e0d68 | 6856 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6857 | continue; |
6858 | ||
6859 | if (encoder->post_disable) | |
ede9771d VS |
6860 | encoder->post_disable(state, encoder, |
6861 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6862 | } |
6863 | } | |
6864 | ||
021ba100 VS |
6865 | static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, |
6866 | struct intel_crtc *crtc) | |
fb1c98b1 | 6867 | { |
021ba100 VS |
6868 | const struct intel_crtc_state *old_crtc_state = |
6869 | intel_atomic_get_old_crtc_state(state, crtc); | |
6870 | const struct drm_connector_state *old_conn_state; | |
fb1c98b1 ML |
6871 | struct drm_connector *conn; |
6872 | int i; | |
6873 | ||
855e0d68 | 6874 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { |
fb1c98b1 ML |
6875 | struct intel_encoder *encoder = |
6876 | to_intel_encoder(old_conn_state->best_encoder); | |
6877 | ||
855e0d68 | 6878 | if (old_conn_state->crtc != &crtc->base) |
fb1c98b1 ML |
6879 | continue; |
6880 | ||
6881 | if (encoder->post_pll_disable) | |
ede9771d VS |
6882 | encoder->post_pll_disable(state, encoder, |
6883 | old_crtc_state, old_conn_state); | |
fb1c98b1 ML |
6884 | } |
6885 | } | |
6886 | ||
021ba100 VS |
6887 | static void intel_encoders_update_pipe(struct intel_atomic_state *state, |
6888 | struct intel_crtc *crtc) | |
608ed4ab | 6889 | { |
021ba100 VS |
6890 | const struct intel_crtc_state *crtc_state = |
6891 | intel_atomic_get_new_crtc_state(state, crtc); | |
6892 | const struct drm_connector_state *conn_state; | |
608ed4ab HG |
6893 | struct drm_connector *conn; |
6894 | int i; | |
6895 | ||
855e0d68 | 6896 | for_each_new_connector_in_state(&state->base, conn, conn_state, i) { |
608ed4ab HG |
6897 | struct intel_encoder *encoder = |
6898 | to_intel_encoder(conn_state->best_encoder); | |
6899 | ||
855e0d68 | 6900 | if (conn_state->crtc != &crtc->base) |
608ed4ab HG |
6901 | continue; |
6902 | ||
6903 | if (encoder->update_pipe) | |
ede9771d VS |
6904 | encoder->update_pipe(state, encoder, |
6905 | crtc_state, conn_state); | |
608ed4ab HG |
6906 | } |
6907 | } | |
6908 | ||
73a116be VS |
6909 | static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) |
6910 | { | |
2225f3c6 | 6911 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
73a116be VS |
6912 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
6913 | ||
6914 | plane->disable_plane(plane, crtc_state); | |
6915 | } | |
6916 | ||
9eae5e27 LDM |
6917 | static void ilk_crtc_enable(struct intel_atomic_state *state, |
6918 | struct intel_crtc *crtc) | |
f67a559d | 6919 | { |
7451a074 VS |
6920 | const struct intel_crtc_state *new_crtc_state = |
6921 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
6922 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6923 | enum pipe pipe = crtc->pipe; | |
f67a559d | 6924 | |
e57291c2 | 6925 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
f67a559d JB |
6926 | return; |
6927 | ||
b2c0593a VS |
6928 | /* |
6929 | * Sometimes spurious CPU pipe underruns happen during FDI | |
6930 | * training, at least with VGA+HDMI cloning. Suppress them. | |
6931 | * | |
6932 | * On ILK we get an occasional spurious CPU pipe underruns | |
6933 | * between eDP port A enable and vdd enable. Also PCH port | |
6934 | * enable seems to result in the occasional CPU pipe underrun. | |
6935 | * | |
6936 | * Spurious PCH underruns also occur during PCH enabling. | |
6937 | */ | |
2b5b6312 VS |
6938 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
6939 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca | 6940 | |
502d8714 VS |
6941 | if (new_crtc_state->has_pch_encoder) |
6942 | intel_prepare_shared_dpll(new_crtc_state); | |
b14b1055 | 6943 | |
502d8714 VS |
6944 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
6945 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
29407aab | 6946 | |
502d8714 VS |
6947 | intel_set_pipe_timings(new_crtc_state); |
6948 | intel_set_pipe_src_size(new_crtc_state); | |
29407aab | 6949 | |
502d8714 VS |
6950 | if (new_crtc_state->has_pch_encoder) |
6951 | intel_cpu_transcoder_set_m_n(new_crtc_state, | |
6952 | &new_crtc_state->fdi_m_n, NULL); | |
29407aab | 6953 | |
9eae5e27 | 6954 | ilk_set_pipeconf(new_crtc_state); |
29407aab | 6955 | |
e44c84a1 | 6956 | crtc->active = true; |
8664281b | 6957 | |
e44c84a1 | 6958 | intel_encoders_pre_enable(state, crtc); |
f67a559d | 6959 | |
502d8714 | 6960 | if (new_crtc_state->has_pch_encoder) { |
fff367c7 DV |
6961 | /* Note: FDI PLL enabling _must_ be done before we enable the |
6962 | * cpu pipes, hence this is separate from all the other fdi/pch | |
6963 | * enabling. */ | |
9eae5e27 | 6964 | ilk_fdi_pll_enable(new_crtc_state); |
46b6f814 DV |
6965 | } else { |
6966 | assert_fdi_tx_disabled(dev_priv, pipe); | |
6967 | assert_fdi_rx_disabled(dev_priv, pipe); | |
6968 | } | |
f67a559d | 6969 | |
9eae5e27 | 6970 | ilk_pfit_enable(new_crtc_state); |
f67a559d | 6971 | |
9c54c0dd JB |
6972 | /* |
6973 | * On ILK+ LUT must be loaded before the pipe is running but with | |
6974 | * clocks enabled | |
6975 | */ | |
502d8714 VS |
6976 | intel_color_load_luts(new_crtc_state); |
6977 | intel_color_commit(new_crtc_state); | |
73a116be | 6978 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 6979 | intel_disable_primary_plane(new_crtc_state); |
9c54c0dd | 6980 | |
7a8fdb1f | 6981 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 6982 | dev_priv->display.initial_watermarks(state, crtc); |
502d8714 | 6983 | intel_enable_pipe(new_crtc_state); |
f67a559d | 6984 | |
502d8714 | 6985 | if (new_crtc_state->has_pch_encoder) |
9eae5e27 | 6986 | ilk_pch_enable(state, new_crtc_state); |
c98e9dcf | 6987 | |
502d8714 | 6988 | intel_crtc_vblank_on(new_crtc_state); |
f9b61ff6 | 6989 | |
e44c84a1 | 6990 | intel_encoders_enable(state, crtc); |
61b77ddd | 6991 | |
6e266956 | 6992 | if (HAS_PCH_CPT(dev_priv)) |
c684fb44 | 6993 | cpt_verify_modeset(dev_priv, pipe); |
37ca8d4c | 6994 | |
ea80a661 VS |
6995 | /* |
6996 | * Must wait for vblank to avoid spurious PCH FIFO underruns. | |
6997 | * And a second vblank wait is needed at least on ILK with | |
6998 | * some interlaced HDMI modes. Let's do the double wait always | |
6999 | * in case there are more corner cases we don't know about. | |
7000 | */ | |
502d8714 | 7001 | if (new_crtc_state->has_pch_encoder) { |
ea80a661 | 7002 | intel_wait_for_vblank(dev_priv, pipe); |
0f0f74bc | 7003 | intel_wait_for_vblank(dev_priv, pipe); |
ea80a661 | 7004 | } |
b2c0593a | 7005 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 7006 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
7007 | } |
7008 | ||
42db64ef PZ |
7009 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
7010 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
7011 | { | |
50a0bc90 | 7012 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
7013 | } |
7014 | ||
ed69cd40 ID |
7015 | static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, |
7016 | enum pipe pipe, bool apply) | |
7017 | { | |
dc008bf0 | 7018 | u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); |
ed69cd40 ID |
7019 | u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; |
7020 | ||
7021 | if (apply) | |
7022 | val |= mask; | |
7023 | else | |
7024 | val &= ~mask; | |
7025 | ||
dc008bf0 | 7026 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); |
ed69cd40 ID |
7027 | } |
7028 | ||
c3cc39c5 MK |
7029 | static void icl_pipe_mbus_enable(struct intel_crtc *crtc) |
7030 | { | |
7031 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7032 | enum pipe pipe = crtc->pipe; | |
ba3f4d0a | 7033 | u32 val; |
c3cc39c5 | 7034 | |
443d5e39 | 7035 | val = MBUS_DBOX_A_CREDIT(2); |
30fcc338 RV |
7036 | |
7037 | if (INTEL_GEN(dev_priv) >= 12) { | |
7038 | val |= MBUS_DBOX_BW_CREDIT(2); | |
7039 | val |= MBUS_DBOX_B_CREDIT(12); | |
7040 | } else { | |
7041 | val |= MBUS_DBOX_BW_CREDIT(1); | |
7042 | val |= MBUS_DBOX_B_CREDIT(8); | |
7043 | } | |
c3cc39c5 | 7044 | |
dc008bf0 | 7045 | intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); |
c3cc39c5 MK |
7046 | } |
7047 | ||
6dcde047 VS |
7048 | static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) |
7049 | { | |
7050 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
7051 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7052 | ||
7053 | intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), | |
7054 | HSW_LINETIME(crtc_state->linetime) | | |
7055 | HSW_IPS_LINETIME(crtc_state->ips_linetime)); | |
7056 | } | |
7057 | ||
cc7a4cff VS |
7058 | static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) |
7059 | { | |
7060 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
7061 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7062 | i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); | |
7063 | u32 val; | |
7064 | ||
dc008bf0 | 7065 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
7066 | val &= ~HSW_FRAME_START_DELAY_MASK; |
7067 | val |= HSW_FRAME_START_DELAY(0); | |
dc008bf0 | 7068 | intel_de_write(dev_priv, reg, val); |
cc7a4cff VS |
7069 | } |
7070 | ||
1e98f88c LDM |
7071 | static void hsw_crtc_enable(struct intel_atomic_state *state, |
7072 | struct intel_crtc *crtc) | |
4f771f10 | 7073 | { |
7451a074 VS |
7074 | const struct intel_crtc_state *new_crtc_state = |
7075 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7076 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7077 | enum pipe pipe = crtc->pipe, hsw_workaround_pipe; | |
502d8714 | 7078 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; |
ed69cd40 | 7079 | bool psl_clkgate_wa; |
4f771f10 | 7080 | |
e57291c2 | 7081 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
4f771f10 PZ |
7082 | return; |
7083 | ||
e44c84a1 | 7084 | intel_encoders_pre_pll_enable(state, crtc); |
95a7a2ae | 7085 | |
502d8714 VS |
7086 | if (new_crtc_state->shared_dpll) |
7087 | intel_enable_shared_dpll(new_crtc_state); | |
df8ad70c | 7088 | |
e44c84a1 | 7089 | intel_encoders_pre_enable(state, crtc); |
c8af5274 | 7090 | |
d7edc4e5 | 7091 | if (!transcoder_is_dsi(cpu_transcoder)) |
502d8714 | 7092 | intel_set_pipe_timings(new_crtc_state); |
4d1de975 | 7093 | |
502d8714 | 7094 | intel_set_pipe_src_size(new_crtc_state); |
229fca97 | 7095 | |
4d1de975 | 7096 | if (cpu_transcoder != TRANSCODER_EDP && |
502d8714 | 7097 | !transcoder_is_dsi(cpu_transcoder)) |
dc008bf0 JN |
7098 | intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), |
7099 | new_crtc_state->pixel_multiplier - 1); | |
ebb69c95 | 7100 | |
502d8714 VS |
7101 | if (new_crtc_state->has_pch_encoder) |
7102 | intel_cpu_transcoder_set_m_n(new_crtc_state, | |
7103 | &new_crtc_state->fdi_m_n, NULL); | |
229fca97 | 7104 | |
cc7a4cff | 7105 | if (!transcoder_is_dsi(cpu_transcoder)) { |
502d8714 | 7106 | hsw_set_frame_start_delay(new_crtc_state); |
1e98f88c | 7107 | hsw_set_pipeconf(new_crtc_state); |
cc7a4cff | 7108 | } |
4d1de975 | 7109 | |
9b11215e | 7110 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
502d8714 | 7111 | bdw_set_pipemisc(new_crtc_state); |
229fca97 | 7112 | |
e44c84a1 | 7113 | crtc->active = true; |
8664281b | 7114 | |
ed69cd40 ID |
7115 | /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ |
7116 | psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && | |
502d8714 | 7117 | new_crtc_state->pch_pfit.enabled; |
ed69cd40 ID |
7118 | if (psl_clkgate_wa) |
7119 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); | |
7120 | ||
6315b5d3 | 7121 | if (INTEL_GEN(dev_priv) >= 9) |
f6df4d46 | 7122 | skl_pfit_enable(new_crtc_state); |
ff6d9f55 | 7123 | else |
9eae5e27 | 7124 | ilk_pfit_enable(new_crtc_state); |
4f771f10 PZ |
7125 | |
7126 | /* | |
7127 | * On ILK+ LUT must be loaded before the pipe is running but with | |
7128 | * clocks enabled | |
7129 | */ | |
502d8714 VS |
7130 | intel_color_load_luts(new_crtc_state); |
7131 | intel_color_commit(new_crtc_state); | |
73a116be VS |
7132 | /* update DSPCNTR to configure gamma/csc for pipe bottom color */ |
7133 | if (INTEL_GEN(dev_priv) < 9) | |
502d8714 | 7134 | intel_disable_primary_plane(new_crtc_state); |
4f771f10 | 7135 | |
6dcde047 VS |
7136 | hsw_set_linetime_wm(new_crtc_state); |
7137 | ||
d1622119 | 7138 | if (INTEL_GEN(dev_priv) >= 11) |
e44c84a1 | 7139 | icl_set_pipe_chicken(crtc); |
e16a3750 | 7140 | |
7a8fdb1f | 7141 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 7142 | dev_priv->display.initial_watermarks(state, crtc); |
4d1de975 | 7143 | |
c3cc39c5 | 7144 | if (INTEL_GEN(dev_priv) >= 11) |
e44c84a1 | 7145 | icl_pipe_mbus_enable(crtc); |
c3cc39c5 | 7146 | |
e44c84a1 | 7147 | intel_encoders_enable(state, crtc); |
4f771f10 | 7148 | |
ed69cd40 ID |
7149 | if (psl_clkgate_wa) { |
7150 | intel_wait_for_vblank(dev_priv, pipe); | |
7151 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); | |
7152 | } | |
7153 | ||
e4916946 PZ |
7154 | /* If we change the relative order between pipe/planes enabling, we need |
7155 | * to change the workaround. */ | |
502d8714 | 7156 | hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; |
772c2a51 | 7157 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
7158 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
7159 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 7160 | } |
4f771f10 PZ |
7161 | } |
7162 | ||
9eae5e27 | 7163 | void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
3f8dce3a | 7164 | { |
2225f3c6 | 7165 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
b2562712 ML |
7166 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7167 | enum pipe pipe = crtc->pipe; | |
3f8dce3a DV |
7168 | |
7169 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
7170 | * it's in use. The hw state code will make sure we get this right. */ | |
eac9c585 VS |
7171 | if (!old_crtc_state->pch_pfit.enabled) |
7172 | return; | |
7173 | ||
7174 | intel_de_write(dev_priv, PF_CTL(pipe), 0); | |
7175 | intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); | |
7176 | intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); | |
3f8dce3a DV |
7177 | } |
7178 | ||
9eae5e27 LDM |
7179 | static void ilk_crtc_disable(struct intel_atomic_state *state, |
7180 | struct intel_crtc *crtc) | |
6be4a607 | 7181 | { |
7451a074 VS |
7182 | const struct intel_crtc_state *old_crtc_state = |
7183 | intel_atomic_get_old_crtc_state(state, crtc); | |
e44c84a1 VS |
7184 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7185 | enum pipe pipe = crtc->pipe; | |
b52eb4dc | 7186 | |
b2c0593a VS |
7187 | /* |
7188 | * Sometimes spurious CPU pipe underruns happen when the | |
7189 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
7190 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
7191 | */ | |
2b5b6312 VS |
7192 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
7193 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 7194 | |
e44c84a1 | 7195 | intel_encoders_disable(state, crtc); |
ea9d758d | 7196 | |
f5271ee5 | 7197 | intel_crtc_vblank_off(old_crtc_state); |
f9b61ff6 | 7198 | |
4972f70a | 7199 | intel_disable_pipe(old_crtc_state); |
32f9d658 | 7200 | |
9eae5e27 | 7201 | ilk_pfit_disable(old_crtc_state); |
2c07245f | 7202 | |
6f405638 | 7203 | if (old_crtc_state->has_pch_encoder) |
9eae5e27 | 7204 | ilk_fdi_disable(crtc); |
5a74f70a | 7205 | |
e44c84a1 | 7206 | intel_encoders_post_disable(state, crtc); |
2c07245f | 7207 | |
6f405638 | 7208 | if (old_crtc_state->has_pch_encoder) { |
9eae5e27 | 7209 | ilk_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 7210 | |
6e266956 | 7211 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
7212 | i915_reg_t reg; |
7213 | u32 temp; | |
7214 | ||
d925c59a DV |
7215 | /* disable TRANS_DP_CTL */ |
7216 | reg = TRANS_DP_CTL(pipe); | |
dc008bf0 | 7217 | temp = intel_de_read(dev_priv, reg); |
d925c59a DV |
7218 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
7219 | TRANS_DP_PORT_SEL_MASK); | |
7220 | temp |= TRANS_DP_PORT_SEL_NONE; | |
dc008bf0 | 7221 | intel_de_write(dev_priv, reg, temp); |
d925c59a DV |
7222 | |
7223 | /* disable DPLL_SEL */ | |
dc008bf0 | 7224 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
11887397 | 7225 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
dc008bf0 | 7226 | intel_de_write(dev_priv, PCH_DPLL_SEL, temp); |
9db4a9c7 | 7227 | } |
e3421a18 | 7228 | |
9eae5e27 | 7229 | ilk_fdi_pll_disable(crtc); |
d925c59a | 7230 | } |
81b088ca | 7231 | |
b2c0593a | 7232 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 7233 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 7234 | } |
1b3c7a47 | 7235 | |
1e98f88c LDM |
7236 | static void hsw_crtc_disable(struct intel_atomic_state *state, |
7237 | struct intel_crtc *crtc) | |
ee7b9f93 | 7238 | { |
773b4b54 VS |
7239 | /* |
7240 | * FIXME collapse everything to one hook. | |
7241 | * Need care with mst->ddi interactions. | |
7242 | */ | |
e44c84a1 | 7243 | intel_encoders_disable(state, crtc); |
e44c84a1 | 7244 | intel_encoders_post_disable(state, crtc); |
4f771f10 PZ |
7245 | } |
7246 | ||
b2562712 | 7247 | static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) |
2dd24552 | 7248 | { |
2225f3c6 | 7249 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2562712 | 7250 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2dd24552 | 7251 | |
b2562712 | 7252 | if (!crtc_state->gmch_pfit.control) |
2dd24552 JB |
7253 | return; |
7254 | ||
2dd24552 | 7255 | /* |
c0b03411 DV |
7256 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
7257 | * according to register description and PRM. | |
2dd24552 | 7258 | */ |
e57291c2 PB |
7259 | drm_WARN_ON(&dev_priv->drm, |
7260 | intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); | |
b104e8b2 | 7261 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); |
2dd24552 | 7262 | |
dc008bf0 JN |
7263 | intel_de_write(dev_priv, PFIT_PGM_RATIOS, |
7264 | crtc_state->gmch_pfit.pgm_ratios); | |
7265 | intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); | |
5a80c45c DV |
7266 | |
7267 | /* Border color in case we don't scale up to the full screen. Black by | |
7268 | * default, change to something else for debugging. */ | |
dc008bf0 | 7269 | intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); |
2dd24552 JB |
7270 | } |
7271 | ||
358633e7 MR |
7272 | bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) |
7273 | { | |
7274 | if (phy == PHY_NONE) | |
7275 | return false; | |
aefaa1f4 MR |
7276 | else if (IS_ROCKETLAKE(dev_priv)) |
7277 | return phy <= PHY_D; | |
7278 | else if (IS_ELKHARTLAKE(dev_priv)) | |
358633e7 | 7279 | return phy <= PHY_C; |
aefaa1f4 | 7280 | else if (INTEL_GEN(dev_priv) >= 11) |
358633e7 | 7281 | return phy <= PHY_B; |
aefaa1f4 MR |
7282 | else |
7283 | return false; | |
358633e7 MR |
7284 | } |
7285 | ||
358633e7 MR |
7286 | bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) |
7287 | { | |
aefaa1f4 MR |
7288 | if (IS_ROCKETLAKE(dev_priv)) |
7289 | return false; | |
7290 | else if (INTEL_GEN(dev_priv) >= 12) | |
5c719708 | 7291 | return phy >= PHY_D && phy <= PHY_I; |
aefaa1f4 | 7292 | else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) |
358633e7 | 7293 | return phy >= PHY_C && phy <= PHY_F; |
aefaa1f4 MR |
7294 | else |
7295 | return false; | |
358633e7 MR |
7296 | } |
7297 | ||
7298 | enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) | |
7299 | { | |
aefaa1f4 MR |
7300 | if (IS_ROCKETLAKE(i915) && port >= PORT_D) |
7301 | return (enum phy)port - 1; | |
7302 | else if (IS_ELKHARTLAKE(i915) && port == PORT_D) | |
358633e7 MR |
7303 | return PHY_A; |
7304 | ||
7305 | return (enum phy)port; | |
7306 | } | |
7307 | ||
ac213c1b PZ |
7308 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) |
7309 | { | |
358633e7 | 7310 | if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) |
ac213c1b PZ |
7311 | return PORT_TC_NONE; |
7312 | ||
6c8337da VK |
7313 | if (INTEL_GEN(dev_priv) >= 12) |
7314 | return port - PORT_D; | |
7315 | ||
ac213c1b PZ |
7316 | return port - PORT_C; |
7317 | } | |
7318 | ||
79f255a0 | 7319 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
7320 | { |
7321 | switch (port) { | |
7322 | case PORT_A: | |
6331a704 | 7323 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 7324 | case PORT_B: |
6331a704 | 7325 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 7326 | case PORT_C: |
6331a704 | 7327 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 7328 | case PORT_D: |
6331a704 | 7329 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 7330 | case PORT_E: |
6331a704 | 7331 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
9787e835 RV |
7332 | case PORT_F: |
7333 | return POWER_DOMAIN_PORT_DDI_F_LANES; | |
eb8de23c KA |
7334 | case PORT_G: |
7335 | return POWER_DOMAIN_PORT_DDI_G_LANES; | |
07c9b088 VS |
7336 | case PORT_H: |
7337 | return POWER_DOMAIN_PORT_DDI_H_LANES; | |
7338 | case PORT_I: | |
7339 | return POWER_DOMAIN_PORT_DDI_I_LANES; | |
d05410f9 | 7340 | default: |
b9fec167 | 7341 | MISSING_CASE(port); |
d05410f9 DA |
7342 | return POWER_DOMAIN_PORT_OTHER; |
7343 | } | |
7344 | } | |
7345 | ||
337837ac ID |
7346 | enum intel_display_power_domain |
7347 | intel_aux_power_domain(struct intel_digital_port *dig_port) | |
7348 | { | |
dd7239c5 | 7349 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
d8fe2ab6 | 7350 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
dd7239c5 | 7351 | |
d8fe2ab6 | 7352 | if (intel_phy_is_tc(dev_priv, phy) && |
dd7239c5 ID |
7353 | dig_port->tc_mode == TC_PORT_TBT_ALT) { |
7354 | switch (dig_port->aux_ch) { | |
7355 | case AUX_CH_C: | |
8a84bacb | 7356 | return POWER_DOMAIN_AUX_C_TBT; |
dd7239c5 | 7357 | case AUX_CH_D: |
8a84bacb | 7358 | return POWER_DOMAIN_AUX_D_TBT; |
dd7239c5 | 7359 | case AUX_CH_E: |
8a84bacb | 7360 | return POWER_DOMAIN_AUX_E_TBT; |
dd7239c5 | 7361 | case AUX_CH_F: |
8a84bacb | 7362 | return POWER_DOMAIN_AUX_F_TBT; |
eb8de23c KA |
7363 | case AUX_CH_G: |
7364 | return POWER_DOMAIN_AUX_G_TBT; | |
244f2e9c VS |
7365 | case AUX_CH_H: |
7366 | return POWER_DOMAIN_AUX_H_TBT; | |
7367 | case AUX_CH_I: | |
7368 | return POWER_DOMAIN_AUX_I_TBT; | |
dd7239c5 ID |
7369 | default: |
7370 | MISSING_CASE(dig_port->aux_ch); | |
8a84bacb | 7371 | return POWER_DOMAIN_AUX_C_TBT; |
dd7239c5 ID |
7372 | } |
7373 | } | |
7374 | ||
dba6b0b4 JRS |
7375 | return intel_legacy_aux_to_power_domain(dig_port->aux_ch); |
7376 | } | |
7377 | ||
7378 | /* | |
7379 | * Converts aux_ch to power_domain without caring about TBT ports for that use | |
7380 | * intel_aux_power_domain() | |
7381 | */ | |
7382 | enum intel_display_power_domain | |
7383 | intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) | |
7384 | { | |
7385 | switch (aux_ch) { | |
337837ac ID |
7386 | case AUX_CH_A: |
7387 | return POWER_DOMAIN_AUX_A; | |
7388 | case AUX_CH_B: | |
7389 | return POWER_DOMAIN_AUX_B; | |
7390 | case AUX_CH_C: | |
7391 | return POWER_DOMAIN_AUX_C; | |
7392 | case AUX_CH_D: | |
7393 | return POWER_DOMAIN_AUX_D; | |
7394 | case AUX_CH_E: | |
7395 | return POWER_DOMAIN_AUX_E; | |
7396 | case AUX_CH_F: | |
7397 | return POWER_DOMAIN_AUX_F; | |
eb8de23c KA |
7398 | case AUX_CH_G: |
7399 | return POWER_DOMAIN_AUX_G; | |
244f2e9c VS |
7400 | case AUX_CH_H: |
7401 | return POWER_DOMAIN_AUX_H; | |
7402 | case AUX_CH_I: | |
7403 | return POWER_DOMAIN_AUX_I; | |
337837ac | 7404 | default: |
dba6b0b4 | 7405 | MISSING_CASE(aux_ch); |
337837ac ID |
7406 | return POWER_DOMAIN_AUX_A; |
7407 | } | |
7408 | } | |
7409 | ||
afe0c21b | 7410 | static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
77d22dca | 7411 | { |
2225f3c6 | 7412 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
afe0c21b | 7413 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
74bff5f9 | 7414 | struct drm_encoder *encoder; |
855e0d68 | 7415 | enum pipe pipe = crtc->pipe; |
d8fc70b7 | 7416 | u64 mask; |
74bff5f9 | 7417 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 7418 | |
1326a92c | 7419 | if (!crtc_state->hw.active) |
292b990e ML |
7420 | return 0; |
7421 | ||
17bd6e66 ID |
7422 | mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); |
7423 | mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
7424 | if (crtc_state->pch_pfit.enabled || |
7425 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 7426 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 7427 | |
afe0c21b | 7428 | drm_for_each_encoder_mask(encoder, &dev_priv->drm, |
2225f3c6 | 7429 | crtc_state->uapi.encoder_mask) { |
74bff5f9 ML |
7430 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
7431 | ||
79f255a0 | 7432 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 7433 | } |
319be8ae | 7434 | |
37255d8d | 7435 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
17bd6e66 | 7436 | mask |= BIT_ULL(POWER_DOMAIN_AUDIO); |
37255d8d | 7437 | |
15e7ec29 | 7438 | if (crtc_state->shared_dpll) |
08d8e170 | 7439 | mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); |
15e7ec29 | 7440 | |
77d22dca ID |
7441 | return mask; |
7442 | } | |
7443 | ||
d2d15016 | 7444 | static u64 |
afe0c21b | 7445 | modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
77d22dca | 7446 | { |
2225f3c6 | 7447 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
855e0d68 | 7448 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
292b990e | 7449 | enum intel_display_power_domain domain; |
d8fc70b7 | 7450 | u64 domains, new_domains, old_domains; |
77d22dca | 7451 | |
855e0d68 ML |
7452 | old_domains = crtc->enabled_power_domains; |
7453 | crtc->enabled_power_domains = new_domains = | |
afe0c21b | 7454 | get_crtc_power_domains(crtc_state); |
77d22dca | 7455 | |
5a21b665 | 7456 | domains = new_domains & ~old_domains; |
292b990e ML |
7457 | |
7458 | for_each_power_domain(domain, domains) | |
7459 | intel_display_power_get(dev_priv, domain); | |
7460 | ||
5a21b665 | 7461 | return old_domains & ~new_domains; |
292b990e ML |
7462 | } |
7463 | ||
7464 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 7465 | u64 domains) |
292b990e ML |
7466 | { |
7467 | enum intel_display_power_domain domain; | |
7468 | ||
7469 | for_each_power_domain(domain, domains) | |
0e6e0be4 | 7470 | intel_display_power_put_unchecked(dev_priv, domain); |
292b990e | 7471 | } |
77d22dca | 7472 | |
7451a074 VS |
7473 | static void valleyview_crtc_enable(struct intel_atomic_state *state, |
7474 | struct intel_crtc *crtc) | |
adafdc6f | 7475 | { |
7451a074 VS |
7476 | const struct intel_crtc_state *new_crtc_state = |
7477 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7478 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7479 | enum pipe pipe = crtc->pipe; | |
adafdc6f | 7480 | |
e57291c2 | 7481 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
7ff89ca2 | 7482 | return; |
adafdc6f | 7483 | |
502d8714 VS |
7484 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
7485 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
b2045352 | 7486 | |
502d8714 VS |
7487 | intel_set_pipe_timings(new_crtc_state); |
7488 | intel_set_pipe_src_size(new_crtc_state); | |
b2045352 | 7489 | |
7ff89ca2 | 7490 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
dc008bf0 JN |
7491 | intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
7492 | intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
7493 | } |
7494 | ||
502d8714 | 7495 | i9xx_set_pipeconf(new_crtc_state); |
560a7ae4 | 7496 | |
e44c84a1 | 7497 | crtc->active = true; |
92891e45 | 7498 | |
7ff89ca2 | 7499 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 7500 | |
e44c84a1 | 7501 | intel_encoders_pre_pll_enable(state, crtc); |
5f199dfa | 7502 | |
7ff89ca2 | 7503 | if (IS_CHERRYVIEW(dev_priv)) { |
502d8714 VS |
7504 | chv_prepare_pll(crtc, new_crtc_state); |
7505 | chv_enable_pll(crtc, new_crtc_state); | |
7ff89ca2 | 7506 | } else { |
502d8714 VS |
7507 | vlv_prepare_pll(crtc, new_crtc_state); |
7508 | vlv_enable_pll(crtc, new_crtc_state); | |
5f199dfa VS |
7509 | } |
7510 | ||
e44c84a1 | 7511 | intel_encoders_pre_enable(state, crtc); |
5f199dfa | 7512 | |
502d8714 | 7513 | i9xx_pfit_enable(new_crtc_state); |
89b3c3c7 | 7514 | |
502d8714 VS |
7515 | intel_color_load_luts(new_crtc_state); |
7516 | intel_color_commit(new_crtc_state); | |
73a116be | 7517 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 7518 | intel_disable_primary_plane(new_crtc_state); |
89b3c3c7 | 7519 | |
e44c84a1 | 7520 | dev_priv->display.initial_watermarks(state, crtc); |
502d8714 | 7521 | intel_enable_pipe(new_crtc_state); |
7ff89ca2 | 7522 | |
502d8714 | 7523 | intel_crtc_vblank_on(new_crtc_state); |
89b3c3c7 | 7524 | |
e44c84a1 | 7525 | intel_encoders_enable(state, crtc); |
89b3c3c7 ACO |
7526 | } |
7527 | ||
b2354c78 | 7528 | static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) |
2b73001e | 7529 | { |
2225f3c6 | 7530 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b2354c78 | 7531 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
83d7c81f | 7532 | |
dc008bf0 JN |
7533 | intel_de_write(dev_priv, FP0(crtc->pipe), |
7534 | crtc_state->dpll_hw_state.fp0); | |
7535 | intel_de_write(dev_priv, FP1(crtc->pipe), | |
7536 | crtc_state->dpll_hw_state.fp1); | |
2b73001e VS |
7537 | } |
7538 | ||
7451a074 VS |
7539 | static void i9xx_crtc_enable(struct intel_atomic_state *state, |
7540 | struct intel_crtc *crtc) | |
2b73001e | 7541 | { |
7451a074 VS |
7542 | const struct intel_crtc_state *new_crtc_state = |
7543 | intel_atomic_get_new_crtc_state(state, crtc); | |
e44c84a1 VS |
7544 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7545 | enum pipe pipe = crtc->pipe; | |
2b73001e | 7546 | |
e57291c2 | 7547 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)) |
7ff89ca2 | 7548 | return; |
2b73001e | 7549 | |
502d8714 | 7550 | i9xx_set_pll_dividers(new_crtc_state); |
2b73001e | 7551 | |
502d8714 VS |
7552 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
7553 | intel_dp_set_m_n(new_crtc_state, M1_N1); | |
83d7c81f | 7554 | |
502d8714 VS |
7555 | intel_set_pipe_timings(new_crtc_state); |
7556 | intel_set_pipe_src_size(new_crtc_state); | |
2b73001e | 7557 | |
502d8714 | 7558 | i9xx_set_pipeconf(new_crtc_state); |
f8437dd1 | 7559 | |
e44c84a1 | 7560 | crtc->active = true; |
5f199dfa | 7561 | |
cf819eff | 7562 | if (!IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7563 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 7564 | |
e44c84a1 | 7565 | intel_encoders_pre_enable(state, crtc); |
f8437dd1 | 7566 | |
502d8714 | 7567 | i9xx_enable_pll(crtc, new_crtc_state); |
f8437dd1 | 7568 | |
502d8714 | 7569 | i9xx_pfit_enable(new_crtc_state); |
f8437dd1 | 7570 | |
502d8714 VS |
7571 | intel_color_load_luts(new_crtc_state); |
7572 | intel_color_commit(new_crtc_state); | |
73a116be | 7573 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
502d8714 | 7574 | intel_disable_primary_plane(new_crtc_state); |
f8437dd1 | 7575 | |
7a8fdb1f | 7576 | if (dev_priv->display.initial_watermarks) |
e44c84a1 | 7577 | dev_priv->display.initial_watermarks(state, crtc); |
04548cba | 7578 | else |
e44c84a1 | 7579 | intel_update_watermarks(crtc); |
502d8714 | 7580 | intel_enable_pipe(new_crtc_state); |
f8437dd1 | 7581 | |
502d8714 | 7582 | intel_crtc_vblank_on(new_crtc_state); |
f8437dd1 | 7583 | |
e44c84a1 | 7584 | intel_encoders_enable(state, crtc); |
f6a7d395 VS |
7585 | |
7586 | /* prevents spurious underruns */ | |
7587 | if (IS_GEN(dev_priv, 2)) | |
7588 | intel_wait_for_vblank(dev_priv, pipe); | |
7ff89ca2 | 7589 | } |
f8437dd1 | 7590 | |
b2562712 | 7591 | static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
7ff89ca2 | 7592 | { |
2225f3c6 | 7593 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
b2562712 | 7594 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f8437dd1 | 7595 | |
b2562712 | 7596 | if (!old_crtc_state->gmch_pfit.control) |
f8437dd1 | 7597 | return; |
f8437dd1 | 7598 | |
b104e8b2 | 7599 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); |
7ff89ca2 | 7600 | |
cd49f818 | 7601 | drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", |
dc008bf0 JN |
7602 | intel_de_read(dev_priv, PFIT_CONTROL)); |
7603 | intel_de_write(dev_priv, PFIT_CONTROL, 0); | |
f8437dd1 VK |
7604 | } |
7605 | ||
7451a074 VS |
7606 | static void i9xx_crtc_disable(struct intel_atomic_state *state, |
7607 | struct intel_crtc *crtc) | |
f8437dd1 | 7608 | { |
7451a074 VS |
7609 | struct intel_crtc_state *old_crtc_state = |
7610 | intel_atomic_get_old_crtc_state(state, crtc); | |
e44c84a1 VS |
7611 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7612 | enum pipe pipe = crtc->pipe; | |
d66a2194 | 7613 | |
d66a2194 | 7614 | /* |
7ff89ca2 VS |
7615 | * On gen2 planes are double buffered but the pipe isn't, so we must |
7616 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 7617 | */ |
cf819eff | 7618 | if (IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7619 | intel_wait_for_vblank(dev_priv, pipe); |
d66a2194 | 7620 | |
e44c84a1 | 7621 | intel_encoders_disable(state, crtc); |
d66a2194 | 7622 | |
f5271ee5 | 7623 | intel_crtc_vblank_off(old_crtc_state); |
d66a2194 | 7624 | |
4972f70a | 7625 | intel_disable_pipe(old_crtc_state); |
d66a2194 | 7626 | |
b2562712 | 7627 | i9xx_pfit_disable(old_crtc_state); |
89b3c3c7 | 7628 | |
e44c84a1 | 7629 | intel_encoders_post_disable(state, crtc); |
d66a2194 | 7630 | |
6f405638 | 7631 | if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { |
7ff89ca2 VS |
7632 | if (IS_CHERRYVIEW(dev_priv)) |
7633 | chv_disable_pll(dev_priv, pipe); | |
7634 | else if (IS_VALLEYVIEW(dev_priv)) | |
7635 | vlv_disable_pll(dev_priv, pipe); | |
7636 | else | |
b2354c78 | 7637 | i9xx_disable_pll(old_crtc_state); |
7ff89ca2 | 7638 | } |
c2e001ef | 7639 | |
e44c84a1 | 7640 | intel_encoders_post_pll_disable(state, crtc); |
89b3c3c7 | 7641 | |
cf819eff | 7642 | if (!IS_GEN(dev_priv, 2)) |
7ff89ca2 | 7643 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
ff32c54e VS |
7644 | |
7645 | if (!dev_priv->display.initial_watermarks) | |
e44c84a1 | 7646 | intel_update_watermarks(crtc); |
2ee0da16 VS |
7647 | |
7648 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
7649 | if (IS_I830(dev_priv)) | |
7650 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
7651 | } |
7652 | ||
56273062 | 7653 | static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, |
da1d0e26 | 7654 | struct drm_modeset_acquire_ctx *ctx) |
f8437dd1 | 7655 | { |
7ff89ca2 | 7656 | struct intel_encoder *encoder; |
56273062 | 7657 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
c457d9cf VS |
7658 | struct intel_bw_state *bw_state = |
7659 | to_intel_bw_state(dev_priv->bw_obj.state); | |
1965de63 | 7660 | struct intel_cdclk_state *cdclk_state = |
28a30b45 | 7661 | to_intel_cdclk_state(dev_priv->cdclk.obj.state); |
3cf43cdc VS |
7662 | struct intel_dbuf_state *dbuf_state = |
7663 | to_intel_dbuf_state(dev_priv->dbuf.obj.state); | |
1e460bf9 | 7664 | struct intel_crtc_state *crtc_state = |
56273062 | 7665 | to_intel_crtc_state(crtc->base.state); |
7ff89ca2 | 7666 | enum intel_display_power_domain domain; |
b1e01595 | 7667 | struct intel_plane *plane; |
7ff89ca2 | 7668 | struct drm_atomic_state *state; |
1e460bf9 | 7669 | struct intel_crtc_state *temp_crtc_state; |
56273062 VS |
7670 | enum pipe pipe = crtc->pipe; |
7671 | u64 domains; | |
7ff89ca2 | 7672 | int ret; |
f8437dd1 | 7673 | |
56273062 | 7674 | if (!crtc_state->hw.active) |
7ff89ca2 | 7675 | return; |
a8ca4934 | 7676 | |
56273062 | 7677 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { |
b1e01595 VS |
7678 | const struct intel_plane_state *plane_state = |
7679 | to_intel_plane_state(plane->base.state); | |
709e05c3 | 7680 | |
f90a85e7 | 7681 | if (plane_state->uapi.visible) |
56273062 | 7682 | intel_plane_disable_noatomic(crtc, plane); |
7ff89ca2 | 7683 | } |
5d96d8af | 7684 | |
56273062 | 7685 | state = drm_atomic_state_alloc(&dev_priv->drm); |
7ff89ca2 | 7686 | if (!state) { |
cd49f818 WK |
7687 | drm_dbg_kms(&dev_priv->drm, |
7688 | "failed to disable [CRTC:%d:%s], out of memory", | |
7689 | crtc->base.base.id, crtc->base.name); | |
1c3f7700 | 7690 | return; |
7ff89ca2 | 7691 | } |
9f7eb31a | 7692 | |
da1d0e26 | 7693 | state->acquire_ctx = ctx; |
ea61791e | 7694 | |
7ff89ca2 | 7695 | /* Everything's already locked, -EDEADLK can't happen. */ |
56273062 VS |
7696 | temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); |
7697 | ret = drm_atomic_add_affected_connectors(state, &crtc->base); | |
9f7eb31a | 7698 | |
e57291c2 | 7699 | drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); |
5d96d8af | 7700 | |
56273062 | 7701 | dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc); |
4a806558 | 7702 | |
0853695c | 7703 | drm_atomic_state_put(state); |
842e0307 | 7704 | |
cd49f818 WK |
7705 | drm_dbg_kms(&dev_priv->drm, |
7706 | "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", | |
7707 | crtc->base.base.id, crtc->base.name); | |
56273062 VS |
7708 | |
7709 | crtc->active = false; | |
7710 | crtc->base.enabled = false; | |
7711 | ||
e57291c2 PB |
7712 | drm_WARN_ON(&dev_priv->drm, |
7713 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); | |
56273062 VS |
7714 | crtc_state->uapi.active = false; |
7715 | crtc_state->uapi.connector_mask = 0; | |
7716 | crtc_state->uapi.encoder_mask = 0; | |
58d124ea ML |
7717 | intel_crtc_free_hw_state(crtc_state); |
7718 | memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); | |
842e0307 | 7719 | |
56273062 | 7720 | for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) |
842e0307 ML |
7721 | encoder->base.crtc = NULL; |
7722 | ||
56273062 VS |
7723 | intel_fbc_disable(crtc); |
7724 | intel_update_watermarks(crtc); | |
7725 | intel_disable_shared_dpll(crtc_state); | |
b17d48e2 | 7726 | |
56273062 | 7727 | domains = crtc->enabled_power_domains; |
b17d48e2 | 7728 | for_each_power_domain(domain, domains) |
0e6e0be4 | 7729 | intel_display_power_put_unchecked(dev_priv, domain); |
56273062 | 7730 | crtc->enabled_power_domains = 0; |
565602d7 | 7731 | |
56273062 | 7732 | dev_priv->active_pipes &= ~BIT(pipe); |
1965de63 VS |
7733 | cdclk_state->min_cdclk[pipe] = 0; |
7734 | cdclk_state->min_voltage_level[pipe] = 0; | |
0c2d5512 | 7735 | cdclk_state->active_pipes &= ~BIT(pipe); |
c457d9cf | 7736 | |
3cf43cdc VS |
7737 | dbuf_state->active_pipes &= ~BIT(pipe); |
7738 | ||
56273062 VS |
7739 | bw_state->data_rate[pipe] = 0; |
7740 | bw_state->num_active_planes[pipe] = 0; | |
b17d48e2 ML |
7741 | } |
7742 | ||
6b72d486 ML |
7743 | /* |
7744 | * turn all crtc's off, but do not adjust state | |
7745 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
7746 | */ | |
70e0bd74 | 7747 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 7748 | { |
e2c8b870 | 7749 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 7750 | struct drm_atomic_state *state; |
e2c8b870 | 7751 | int ret; |
70e0bd74 | 7752 | |
e2c8b870 ML |
7753 | state = drm_atomic_helper_suspend(dev); |
7754 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 | 7755 | if (ret) |
cd49f818 WK |
7756 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", |
7757 | ret); | |
e2c8b870 ML |
7758 | else |
7759 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 7760 | return ret; |
ee7b9f93 JB |
7761 | } |
7762 | ||
ea5b213a | 7763 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 7764 | { |
4ef69c7a | 7765 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 7766 | |
ea5b213a CW |
7767 | drm_encoder_cleanup(encoder); |
7768 | kfree(intel_encoder); | |
7e7d76c3 JB |
7769 | } |
7770 | ||
0a91ca29 DV |
7771 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
7772 | * internal consistency). */ | |
3b4bf24d | 7773 | static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, |
749d98b8 | 7774 | struct drm_connector_state *conn_state) |
79e53945 | 7775 | { |
749d98b8 | 7776 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
cd49f818 | 7777 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
35dd3c64 | 7778 | |
cd49f818 WK |
7779 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", |
7780 | connector->base.base.id, connector->base.name); | |
35dd3c64 | 7781 | |
0a91ca29 | 7782 | if (connector->get_hw_state(connector)) { |
fa7edcd2 | 7783 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
0a91ca29 | 7784 | |
749d98b8 | 7785 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 7786 | "connector enabled without attached crtc\n"); |
0a91ca29 | 7787 | |
749d98b8 | 7788 | if (!crtc_state) |
35dd3c64 ML |
7789 | return; |
7790 | ||
1326a92c ML |
7791 | I915_STATE_WARN(!crtc_state->hw.active, |
7792 | "connector is active, but attached crtc isn't\n"); | |
35dd3c64 | 7793 | |
e85376cb | 7794 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
7795 | return; |
7796 | ||
e85376cb | 7797 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
7798 | "atomic encoder doesn't match attached encoder\n"); |
7799 | ||
e85376cb | 7800 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
7801 | "attached encoder crtc differs from connector crtc\n"); |
7802 | } else { | |
1326a92c ML |
7803 | I915_STATE_WARN(crtc_state && crtc_state->hw.active, |
7804 | "attached crtc is active, but connector isn't\n"); | |
749d98b8 | 7805 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 7806 | "best encoder set without crtc!\n"); |
0a91ca29 | 7807 | } |
79e53945 JB |
7808 | } |
7809 | ||
6d293983 | 7810 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7811 | { |
1326a92c | 7812 | if (crtc_state->hw.enable && crtc_state->has_pch_encoder) |
6d293983 | 7813 | return crtc_state->fdi_lanes; |
d272ddfa VS |
7814 | |
7815 | return 0; | |
7816 | } | |
7817 | ||
9eae5e27 LDM |
7818 | static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
7819 | struct intel_crtc_state *pipe_config) | |
1857e1da | 7820 | { |
8652744b | 7821 | struct drm_i915_private *dev_priv = to_i915(dev); |
2225f3c6 | 7822 | struct drm_atomic_state *state = pipe_config->uapi.state; |
6d293983 ACO |
7823 | struct intel_crtc *other_crtc; |
7824 | struct intel_crtc_state *other_crtc_state; | |
7825 | ||
cd49f818 WK |
7826 | drm_dbg_kms(&dev_priv->drm, |
7827 | "checking fdi config on pipe %c, lanes %i\n", | |
7828 | pipe_name(pipe), pipe_config->fdi_lanes); | |
1857e1da | 7829 | if (pipe_config->fdi_lanes > 4) { |
cd49f818 WK |
7830 | drm_dbg_kms(&dev_priv->drm, |
7831 | "invalid fdi lane config on pipe %c: %i lanes\n", | |
7832 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7833 | return -EINVAL; |
1857e1da DV |
7834 | } |
7835 | ||
8652744b | 7836 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da | 7837 | if (pipe_config->fdi_lanes > 2) { |
cd49f818 WK |
7838 | drm_dbg_kms(&dev_priv->drm, |
7839 | "only 2 lanes on haswell, required: %i lanes\n", | |
7840 | pipe_config->fdi_lanes); | |
6d293983 | 7841 | return -EINVAL; |
1857e1da | 7842 | } else { |
6d293983 | 7843 | return 0; |
1857e1da DV |
7844 | } |
7845 | } | |
7846 | ||
24977870 | 7847 | if (INTEL_NUM_PIPES(dev_priv) == 2) |
6d293983 | 7848 | return 0; |
1857e1da DV |
7849 | |
7850 | /* Ivybridge 3 pipe is really complicated */ | |
7851 | switch (pipe) { | |
7852 | case PIPE_A: | |
6d293983 | 7853 | return 0; |
1857e1da | 7854 | case PIPE_B: |
6d293983 ACO |
7855 | if (pipe_config->fdi_lanes <= 2) |
7856 | return 0; | |
7857 | ||
b91eb5cc | 7858 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7859 | other_crtc_state = |
7860 | intel_atomic_get_crtc_state(state, other_crtc); | |
7861 | if (IS_ERR(other_crtc_state)) | |
7862 | return PTR_ERR(other_crtc_state); | |
7863 | ||
7864 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
cd49f818 WK |
7865 | drm_dbg_kms(&dev_priv->drm, |
7866 | "invalid shared fdi lane config on pipe %c: %i lanes\n", | |
7867 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7868 | return -EINVAL; |
1857e1da | 7869 | } |
6d293983 | 7870 | return 0; |
1857e1da | 7871 | case PIPE_C: |
251cc67c | 7872 | if (pipe_config->fdi_lanes > 2) { |
cd49f818 WK |
7873 | drm_dbg_kms(&dev_priv->drm, |
7874 | "only 2 lanes on pipe %c: required %i lanes\n", | |
7875 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7876 | return -EINVAL; |
251cc67c | 7877 | } |
6d293983 | 7878 | |
b91eb5cc | 7879 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7880 | other_crtc_state = |
7881 | intel_atomic_get_crtc_state(state, other_crtc); | |
7882 | if (IS_ERR(other_crtc_state)) | |
7883 | return PTR_ERR(other_crtc_state); | |
7884 | ||
7885 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
cd49f818 WK |
7886 | drm_dbg_kms(&dev_priv->drm, |
7887 | "fdi link B uses too many lanes to enable link C\n"); | |
6d293983 | 7888 | return -EINVAL; |
1857e1da | 7889 | } |
6d293983 | 7890 | return 0; |
1857e1da DV |
7891 | default: |
7892 | BUG(); | |
7893 | } | |
7894 | } | |
7895 | ||
e29c22c0 | 7896 | #define RETRY 1 |
9eae5e27 LDM |
7897 | static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc, |
7898 | struct intel_crtc_state *pipe_config) | |
877d48d5 | 7899 | { |
1857e1da | 7900 | struct drm_device *dev = intel_crtc->base.dev; |
cd49f818 | 7901 | struct drm_i915_private *i915 = to_i915(dev); |
1326a92c | 7902 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
6d293983 ACO |
7903 | int lane, link_bw, fdi_dotclock, ret; |
7904 | bool needs_recompute = false; | |
877d48d5 | 7905 | |
e29c22c0 | 7906 | retry: |
877d48d5 DV |
7907 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7908 | * each output octet as 10 bits. The actual frequency | |
7909 | * is stored as a divider into a 100MHz clock, and the | |
7910 | * mode pixel clock is stored in units of 1KHz. | |
7911 | * Hence the bw of each lane in terms of the mode signal | |
7912 | * is: | |
7913 | */ | |
cd49f818 | 7914 | link_bw = intel_fdi_link_freq(i915, pipe_config); |
877d48d5 | 7915 | |
241bfc38 | 7916 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7917 | |
9eae5e27 LDM |
7918 | lane = ilk_get_lanes_required(fdi_dotclock, link_bw, |
7919 | pipe_config->pipe_bpp); | |
877d48d5 DV |
7920 | |
7921 | pipe_config->fdi_lanes = lane; | |
7922 | ||
2bd89a07 | 7923 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
ed06efb8 | 7924 | link_bw, &pipe_config->fdi_m_n, false, false); |
1857e1da | 7925 | |
9eae5e27 | 7926 | ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
8e2b4dff VS |
7927 | if (ret == -EDEADLK) |
7928 | return ret; | |
7929 | ||
6d293983 | 7930 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 7931 | pipe_config->pipe_bpp -= 2*3; |
cd49f818 WK |
7932 | drm_dbg_kms(&i915->drm, |
7933 | "fdi link bw constraint, reducing pipe bpp to %i\n", | |
7934 | pipe_config->pipe_bpp); | |
7ff89ca2 VS |
7935 | needs_recompute = true; |
7936 | pipe_config->bw_constrained = true; | |
257a7ffc | 7937 | |
7ff89ca2 | 7938 | goto retry; |
257a7ffc | 7939 | } |
79e53945 | 7940 | |
7ff89ca2 VS |
7941 | if (needs_recompute) |
7942 | return RETRY; | |
e70236a8 | 7943 | |
7ff89ca2 | 7944 | return ret; |
e70236a8 JB |
7945 | } |
7946 | ||
24f28450 | 7947 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) |
e70236a8 | 7948 | { |
2225f3c6 | 7949 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
24f28450 ML |
7950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7951 | ||
7952 | /* IPS only exists on ULT machines and is tied to pipe A. */ | |
7953 | if (!hsw_crtc_supports_ips(crtc)) | |
6e644626 VS |
7954 | return false; |
7955 | ||
8a25c4be | 7956 | if (!dev_priv->params.enable_ips) |
7ff89ca2 | 7957 | return false; |
e70236a8 | 7958 | |
24f28450 ML |
7959 | if (crtc_state->pipe_bpp > 24) |
7960 | return false; | |
1b1d2716 | 7961 | |
65cd2b3f | 7962 | /* |
7ff89ca2 VS |
7963 | * We compare against max which means we must take |
7964 | * the increased cdclk requirement into account when | |
7965 | * calculating the new cdclk. | |
7966 | * | |
7967 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 7968 | */ |
24f28450 ML |
7969 | if (IS_BROADWELL(dev_priv) && |
7970 | crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) | |
7971 | return false; | |
7972 | ||
7973 | return true; | |
e70236a8 | 7974 | } |
79e53945 | 7975 | |
28a30b45 | 7976 | static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state) |
7ff89ca2 | 7977 | { |
24f28450 | 7978 | struct drm_i915_private *dev_priv = |
2225f3c6 | 7979 | to_i915(crtc_state->uapi.crtc->dev); |
28a30b45 | 7980 | struct intel_atomic_state *state = |
2225f3c6 | 7981 | to_intel_atomic_state(crtc_state->uapi.state); |
28a30b45 VS |
7982 | |
7983 | crtc_state->ips_enabled = false; | |
24f28450 ML |
7984 | |
7985 | if (!hsw_crtc_state_ips_capable(crtc_state)) | |
28a30b45 | 7986 | return 0; |
24f28450 | 7987 | |
a8ebf607 JRS |
7988 | /* |
7989 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
7990 | * enabled and disabled dynamically based on package C states, | |
7991 | * user space can't make reliable use of the CRCs, so let's just | |
7992 | * completely disable it. | |
7993 | */ | |
7994 | if (crtc_state->crc_enabled) | |
28a30b45 | 7995 | return 0; |
24f28450 | 7996 | |
adbe5c5c ML |
7997 | /* IPS should be fine as long as at least one plane is enabled. */ |
7998 | if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) | |
28a30b45 | 7999 | return 0; |
34edce2f | 8000 | |
28a30b45 VS |
8001 | if (IS_BROADWELL(dev_priv)) { |
8002 | const struct intel_cdclk_state *cdclk_state; | |
24f28450 | 8003 | |
28a30b45 VS |
8004 | cdclk_state = intel_atomic_get_cdclk_state(state); |
8005 | if (IS_ERR(cdclk_state)) | |
8006 | return PTR_ERR(cdclk_state); | |
8007 | ||
8008 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
8009 | if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) | |
8010 | return 0; | |
8011 | } | |
8012 | ||
8013 | crtc_state->ips_enabled = true; | |
8014 | ||
8015 | return 0; | |
34edce2f VS |
8016 | } |
8017 | ||
7ff89ca2 | 8018 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 8019 | { |
7ff89ca2 | 8020 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 8021 | |
7ff89ca2 | 8022 | /* GDG double wide on either pipe, otherwise pipe A only */ |
c56b89f1 | 8023 | return INTEL_GEN(dev_priv) < 4 && |
7ff89ca2 | 8024 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
34edce2f VS |
8025 | } |
8026 | ||
eac9c585 | 8027 | static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) |
ceb99320 | 8028 | { |
eac9c585 | 8029 | u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock; |
35dd95b4 | 8030 | unsigned int pipe_w, pipe_h, pfit_w, pfit_h; |
ceb99320 VS |
8031 | |
8032 | /* | |
8033 | * We only use IF-ID interlacing. If we ever use | |
8034 | * PF-ID we'll need to adjust the pixel_rate here. | |
8035 | */ | |
8036 | ||
eac9c585 VS |
8037 | if (!crtc_state->pch_pfit.enabled) |
8038 | return pixel_rate; | |
ceb99320 | 8039 | |
eac9c585 VS |
8040 | pipe_w = crtc_state->pipe_src_w; |
8041 | pipe_h = crtc_state->pipe_src_h; | |
ceb99320 | 8042 | |
35dd95b4 VS |
8043 | pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst); |
8044 | pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst); | |
8045 | ||
eac9c585 VS |
8046 | if (pipe_w < pfit_w) |
8047 | pipe_w = pfit_w; | |
8048 | if (pipe_h < pfit_h) | |
8049 | pipe_h = pfit_h; | |
ceb99320 | 8050 | |
eac9c585 VS |
8051 | if (drm_WARN_ON(crtc_state->uapi.crtc->dev, |
8052 | !pfit_w || !pfit_h)) | |
8053 | return pixel_rate; | |
ceb99320 | 8054 | |
eac9c585 VS |
8055 | return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h), |
8056 | pfit_w * pfit_h); | |
ceb99320 VS |
8057 | } |
8058 | ||
7ff89ca2 | 8059 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 8060 | { |
2225f3c6 | 8061 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
34edce2f | 8062 | |
b2ae318a | 8063 | if (HAS_GMCH(dev_priv)) |
7ff89ca2 VS |
8064 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ |
8065 | crtc_state->pixel_rate = | |
1326a92c | 8066 | crtc_state->hw.adjusted_mode.crtc_clock; |
7ff89ca2 VS |
8067 | else |
8068 | crtc_state->pixel_rate = | |
8069 | ilk_pipe_pixel_rate(crtc_state); | |
8070 | } | |
34edce2f | 8071 | |
7ff89ca2 VS |
8072 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
8073 | struct intel_crtc_state *pipe_config) | |
8074 | { | |
d2daff2c | 8075 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1326a92c | 8076 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
7ff89ca2 | 8077 | int clock_limit = dev_priv->max_dotclk_freq; |
34edce2f | 8078 | |
7ff89ca2 VS |
8079 | if (INTEL_GEN(dev_priv) < 4) { |
8080 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 8081 | |
7ff89ca2 VS |
8082 | /* |
8083 | * Enable double wide mode when the dot clock | |
8084 | * is > 90% of the (display) core speed. | |
8085 | */ | |
8086 | if (intel_crtc_supports_double_wide(crtc) && | |
8087 | adjusted_mode->crtc_clock > clock_limit) { | |
8088 | clock_limit = dev_priv->max_dotclk_freq; | |
8089 | pipe_config->double_wide = true; | |
8090 | } | |
34edce2f VS |
8091 | } |
8092 | ||
7ff89ca2 | 8093 | if (adjusted_mode->crtc_clock > clock_limit) { |
cd49f818 WK |
8094 | drm_dbg_kms(&dev_priv->drm, |
8095 | "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
8096 | adjusted_mode->crtc_clock, clock_limit, | |
8097 | yesno(pipe_config->double_wide)); | |
7ff89ca2 VS |
8098 | return -EINVAL; |
8099 | } | |
34edce2f | 8100 | |
8c79f844 SS |
8101 | if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
8102 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) && | |
1326a92c | 8103 | pipe_config->hw.ctm) { |
25edf915 SS |
8104 | /* |
8105 | * There is only one pipe CSC unit per pipe, and we need that | |
8106 | * for output conversion from RGB->YCBCR. So if CTM is already | |
8107 | * applied we can't support YCBCR420 output. | |
8108 | */ | |
cd49f818 WK |
8109 | drm_dbg_kms(&dev_priv->drm, |
8110 | "YCBCR420 and CTM together are not possible\n"); | |
25edf915 SS |
8111 | return -EINVAL; |
8112 | } | |
8113 | ||
7ff89ca2 VS |
8114 | /* |
8115 | * Pipe horizontal size must be even in: | |
8116 | * - DVO ganged mode | |
8117 | * - LVDS dual channel mode | |
8118 | * - Double wide pipe | |
8119 | */ | |
0574bd88 VS |
8120 | if (pipe_config->pipe_src_w & 1) { |
8121 | if (pipe_config->double_wide) { | |
cd49f818 WK |
8122 | drm_dbg_kms(&dev_priv->drm, |
8123 | "Odd pipe source width not supported with double wide pipe\n"); | |
0574bd88 VS |
8124 | return -EINVAL; |
8125 | } | |
8126 | ||
8127 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
d2daff2c | 8128 | intel_is_dual_link_lvds(dev_priv)) { |
cd49f818 WK |
8129 | drm_dbg_kms(&dev_priv->drm, |
8130 | "Odd pipe source width not supported with dual link LVDS\n"); | |
0574bd88 VS |
8131 | return -EINVAL; |
8132 | } | |
8133 | } | |
34edce2f | 8134 | |
7ff89ca2 VS |
8135 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
8136 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
8137 | */ | |
8138 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
8139 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
8140 | return -EINVAL; | |
34edce2f | 8141 | |
7ff89ca2 | 8142 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 8143 | |
7ff89ca2 | 8144 | if (pipe_config->has_pch_encoder) |
9eae5e27 | 8145 | return ilk_fdi_compute_config(crtc, pipe_config); |
34edce2f | 8146 | |
7ff89ca2 | 8147 | return 0; |
34edce2f VS |
8148 | } |
8149 | ||
2c07245f | 8150 | static void |
ba3f4d0a | 8151 | intel_reduce_m_n_ratio(u32 *num, u32 *den) |
2c07245f | 8152 | { |
a65851af VS |
8153 | while (*num > DATA_LINK_M_N_MASK || |
8154 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
8155 | *num >>= 1; |
8156 | *den >>= 1; | |
8157 | } | |
8158 | } | |
8159 | ||
a65851af | 8160 | static void compute_m_n(unsigned int m, unsigned int n, |
ba3f4d0a | 8161 | u32 *ret_m, u32 *ret_n, |
53ca2edc | 8162 | bool constant_n) |
a65851af | 8163 | { |
9a86cda0 | 8164 | /* |
53ca2edc LS |
8165 | * Several DP dongles in particular seem to be fussy about |
8166 | * too large link M/N values. Give N value as 0x8000 that | |
8167 | * should be acceptable by specific devices. 0x8000 is the | |
8168 | * specified fixed N value for asynchronous clock mode, | |
8169 | * which the devices expect also in synchronous clock mode. | |
9a86cda0 | 8170 | */ |
53ca2edc | 8171 | if (constant_n) |
b22960b8 | 8172 | *ret_n = DP_LINK_CONSTANT_N_VALUE; |
53ca2edc LS |
8173 | else |
8174 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
9a86cda0 | 8175 | |
d492a29d | 8176 | *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); |
a65851af VS |
8177 | intel_reduce_m_n_ratio(ret_m, ret_n); |
8178 | } | |
8179 | ||
e69d0bc1 | 8180 | void |
a4a15777 | 8181 | intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, |
e69d0bc1 | 8182 | int pixel_clock, int link_clock, |
b31e85ed | 8183 | struct intel_link_m_n *m_n, |
ed06efb8 | 8184 | bool constant_n, bool fec_enable) |
2c07245f | 8185 | { |
ed06efb8 ML |
8186 | u32 data_clock = bits_per_pixel * pixel_clock; |
8187 | ||
8188 | if (fec_enable) | |
8189 | data_clock = intel_dp_mode_to_fec_clock(data_clock); | |
a65851af | 8190 | |
ed06efb8 ML |
8191 | m_n->tu = 64; |
8192 | compute_m_n(data_clock, | |
a65851af | 8193 | link_clock * nlanes * 8, |
b31e85ed | 8194 | &m_n->gmch_m, &m_n->gmch_n, |
53ca2edc | 8195 | constant_n); |
a65851af VS |
8196 | |
8197 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed | 8198 | &m_n->link_m, &m_n->link_n, |
53ca2edc | 8199 | constant_n); |
2c07245f ZW |
8200 | } |
8201 | ||
064bd628 JN |
8202 | static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) |
8203 | { | |
8204 | /* | |
8205 | * There may be no VBT; and if the BIOS enabled SSC we can | |
8206 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
8207 | * BIOS isn't using it, don't assume it will work even if the VBT | |
8208 | * indicates as much. | |
8209 | */ | |
8210 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { | |
dc008bf0 JN |
8211 | bool bios_lvds_use_ssc = intel_de_read(dev_priv, |
8212 | PCH_DREF_CONTROL) & | |
064bd628 JN |
8213 | DREF_SSC1_ENABLE; |
8214 | ||
8215 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
cd49f818 WK |
8216 | drm_dbg_kms(&dev_priv->drm, |
8217 | "SSC %s by BIOS, overriding VBT which says %s\n", | |
8218 | enableddisabled(bios_lvds_use_ssc), | |
8219 | enableddisabled(dev_priv->vbt.lvds_use_ssc)); | |
064bd628 JN |
8220 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
8221 | } | |
8222 | } | |
8223 | } | |
8224 | ||
81b55ef1 | 8225 | static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
a7615030 | 8226 | { |
8a25c4be JN |
8227 | if (dev_priv->params.panel_use_ssc >= 0) |
8228 | return dev_priv->params.panel_use_ssc != 0; | |
41aa3448 | 8229 | return dev_priv->vbt.lvds_use_ssc |
435793df | 8230 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
8231 | } |
8232 | ||
ba3f4d0a | 8233 | static u32 pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 8234 | { |
7df00d7a | 8235 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 8236 | } |
f47709a9 | 8237 | |
ba3f4d0a | 8238 | static u32 i9xx_dpll_compute_fp(struct dpll *dpll) |
7429e9d4 DV |
8239 | { |
8240 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
8241 | } |
8242 | ||
f47709a9 | 8243 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 8244 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 8245 | struct dpll *reduced_clock) |
a7516a05 | 8246 | { |
9b1e14f4 | 8247 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
8248 | u32 fp, fp2 = 0; |
8249 | ||
9b1e14f4 | 8250 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 8251 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 8252 | if (reduced_clock) |
7429e9d4 | 8253 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 8254 | } else { |
190f68c5 | 8255 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 8256 | if (reduced_clock) |
7429e9d4 | 8257 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
8258 | } |
8259 | ||
190f68c5 | 8260 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 8261 | |
2d84d2b3 | 8262 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 8263 | reduced_clock) { |
190f68c5 | 8264 | crtc_state->dpll_hw_state.fp1 = fp2; |
a7516a05 | 8265 | } else { |
190f68c5 | 8266 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
8267 | } |
8268 | } | |
8269 | ||
5e69f97f CML |
8270 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
8271 | pipe) | |
89b667f8 JB |
8272 | { |
8273 | u32 reg_val; | |
8274 | ||
8275 | /* | |
8276 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
8277 | * and set it to a reasonable value instead. | |
8278 | */ | |
ab3c759a | 8279 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
8280 | reg_val &= 0xffffff00; |
8281 | reg_val |= 0x00000030; | |
ab3c759a | 8282 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 8283 | |
ab3c759a | 8284 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
8285 | reg_val &= 0x00ffffff; |
8286 | reg_val |= 0x8c000000; | |
ab3c759a | 8287 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 8288 | |
ab3c759a | 8289 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 8290 | reg_val &= 0xffffff00; |
ab3c759a | 8291 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 8292 | |
ab3c759a | 8293 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
8294 | reg_val &= 0x00ffffff; |
8295 | reg_val |= 0xb0000000; | |
ab3c759a | 8296 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
8297 | } |
8298 | ||
4c354754 ML |
8299 | static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
8300 | const struct intel_link_m_n *m_n) | |
b551842d | 8301 | { |
2225f3c6 | 8302 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4c354754 ML |
8303 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8304 | enum pipe pipe = crtc->pipe; | |
b551842d | 8305 | |
dc008bf0 JN |
8306 | intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe), |
8307 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8308 | intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
8309 | intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
8310 | intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
8311 | } |
8312 | ||
4207c8b9 ML |
8313 | static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, |
8314 | enum transcoder transcoder) | |
8315 | { | |
8316 | if (IS_HASWELL(dev_priv)) | |
8317 | return transcoder == TRANSCODER_EDP; | |
8318 | ||
8319 | /* | |
8320 | * Strictly speaking some registers are available before | |
8321 | * gen7, but we only support DRRS on gen7+ | |
8322 | */ | |
cf819eff | 8323 | return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); |
4207c8b9 ML |
8324 | } |
8325 | ||
4c354754 ML |
8326 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
8327 | const struct intel_link_m_n *m_n, | |
8328 | const struct intel_link_m_n *m2_n2) | |
b551842d | 8329 | { |
2225f3c6 | 8330 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 8331 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4c354754 ML |
8332 | enum pipe pipe = crtc->pipe; |
8333 | enum transcoder transcoder = crtc_state->cpu_transcoder; | |
b551842d | 8334 | |
6315b5d3 | 8335 | if (INTEL_GEN(dev_priv) >= 5) { |
dc008bf0 JN |
8336 | intel_de_write(dev_priv, PIPE_DATA_M1(transcoder), |
8337 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8338 | intel_de_write(dev_priv, PIPE_DATA_N1(transcoder), | |
8339 | m_n->gmch_n); | |
8340 | intel_de_write(dev_priv, PIPE_LINK_M1(transcoder), | |
8341 | m_n->link_m); | |
8342 | intel_de_write(dev_priv, PIPE_LINK_N1(transcoder), | |
8343 | m_n->link_n); | |
4207c8b9 ML |
8344 | /* |
8345 | * M2_N2 registers are set only if DRRS is supported | |
8346 | * (to make sure the registers are not unnecessarily accessed). | |
f769cd24 | 8347 | */ |
4207c8b9 ML |
8348 | if (m2_n2 && crtc_state->has_drrs && |
8349 | transcoder_has_m2_n2(dev_priv, transcoder)) { | |
dc008bf0 JN |
8350 | intel_de_write(dev_priv, PIPE_DATA_M2(transcoder), |
8351 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
8352 | intel_de_write(dev_priv, PIPE_DATA_N2(transcoder), | |
8353 | m2_n2->gmch_n); | |
8354 | intel_de_write(dev_priv, PIPE_LINK_M2(transcoder), | |
8355 | m2_n2->link_m); | |
8356 | intel_de_write(dev_priv, PIPE_LINK_N2(transcoder), | |
8357 | m2_n2->link_n); | |
f769cd24 | 8358 | } |
b551842d | 8359 | } else { |
dc008bf0 JN |
8360 | intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe), |
8361 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
8362 | intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
8363 | intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
8364 | intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
8365 | } |
8366 | } | |
8367 | ||
4c354754 | 8368 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n) |
03afc4a2 | 8369 | { |
4c354754 | 8370 | const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
cd49f818 | 8371 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
fe3cd48d R |
8372 | |
8373 | if (m_n == M1_N1) { | |
4c354754 ML |
8374 | dp_m_n = &crtc_state->dp_m_n; |
8375 | dp_m2_n2 = &crtc_state->dp_m2_n2; | |
fe3cd48d R |
8376 | } else if (m_n == M2_N2) { |
8377 | ||
8378 | /* | |
8379 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
8380 | * needs to be programmed into M1_N1. | |
8381 | */ | |
4c354754 | 8382 | dp_m_n = &crtc_state->dp_m2_n2; |
fe3cd48d | 8383 | } else { |
cd49f818 | 8384 | drm_err(&i915->drm, "Unsupported divider value\n"); |
fe3cd48d R |
8385 | return; |
8386 | } | |
8387 | ||
4c354754 ML |
8388 | if (crtc_state->has_pch_encoder) |
8389 | intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n); | |
03afc4a2 | 8390 | else |
4c354754 | 8391 | intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
8392 | } |
8393 | ||
251ac862 DV |
8394 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
8395 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 8396 | { |
03ed5cbf | 8397 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 8398 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
8399 | if (crtc->pipe != PIPE_A) |
8400 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 8401 | |
cd2d34d9 | 8402 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 8403 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
8404 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
8405 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
8406 | ||
03ed5cbf VS |
8407 | pipe_config->dpll_hw_state.dpll_md = |
8408 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8409 | } | |
bdd4b6a6 | 8410 | |
03ed5cbf VS |
8411 | static void chv_compute_dpll(struct intel_crtc *crtc, |
8412 | struct intel_crtc_state *pipe_config) | |
8413 | { | |
8414 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 8415 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
8416 | if (crtc->pipe != PIPE_A) |
8417 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
8418 | ||
cd2d34d9 | 8419 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 8420 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
8421 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
8422 | ||
03ed5cbf VS |
8423 | pipe_config->dpll_hw_state.dpll_md = |
8424 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
8425 | } |
8426 | ||
d288f65f | 8427 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 8428 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 8429 | { |
f47709a9 | 8430 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8431 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8432 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 8433 | u32 mdiv; |
a0c4da24 | 8434 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 8435 | u32 coreclk, reg_val; |
a0c4da24 | 8436 | |
cd2d34d9 | 8437 | /* Enable Refclk */ |
dc008bf0 JN |
8438 | intel_de_write(dev_priv, DPLL(pipe), |
8439 | pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
cd2d34d9 VS |
8440 | |
8441 | /* No need to actually set up the DPLL with DSI */ | |
8442 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8443 | return; | |
8444 | ||
221c7862 | 8445 | vlv_dpio_get(dev_priv); |
09153000 | 8446 | |
d288f65f VS |
8447 | bestn = pipe_config->dpll.n; |
8448 | bestm1 = pipe_config->dpll.m1; | |
8449 | bestm2 = pipe_config->dpll.m2; | |
8450 | bestp1 = pipe_config->dpll.p1; | |
8451 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 8452 | |
89b667f8 JB |
8453 | /* See eDP HDMI DPIO driver vbios notes doc */ |
8454 | ||
8455 | /* PLL B needs special handling */ | |
bdd4b6a6 | 8456 | if (pipe == PIPE_B) |
5e69f97f | 8457 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
8458 | |
8459 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 8460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
8461 | |
8462 | /* Disable target IRef on PLL */ | |
ab3c759a | 8463 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 8464 | reg_val &= 0x00ffffff; |
ab3c759a | 8465 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
8466 | |
8467 | /* Disable fast lock */ | |
ab3c759a | 8468 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
8469 | |
8470 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
8471 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
8472 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
8473 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 8474 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
8475 | |
8476 | /* | |
8477 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
8478 | * but we don't support that). | |
8479 | * Note: don't use the DAC post divider as it seems unstable. | |
8480 | */ | |
8481 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 8482 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 8483 | |
a0c4da24 | 8484 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 8485 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 8486 | |
89b667f8 | 8487 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 8488 | if (pipe_config->port_clock == 162000 || |
92d54b07 ML |
8489 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || |
8490 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 8491 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 8492 | 0x009f0003); |
89b667f8 | 8493 | else |
ab3c759a | 8494 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
8495 | 0x00d0000f); |
8496 | ||
37a5650b | 8497 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 8498 | /* Use SSC source */ |
bdd4b6a6 | 8499 | if (pipe == PIPE_A) |
ab3c759a | 8500 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8501 | 0x0df40000); |
8502 | else | |
ab3c759a | 8503 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8504 | 0x0df70000); |
8505 | } else { /* HDMI or VGA */ | |
8506 | /* Use bend source */ | |
bdd4b6a6 | 8507 | if (pipe == PIPE_A) |
ab3c759a | 8508 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8509 | 0x0df70000); |
8510 | else | |
ab3c759a | 8511 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
8512 | 0x0df40000); |
8513 | } | |
a0c4da24 | 8514 | |
ab3c759a | 8515 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 8516 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
92d54b07 | 8517 | if (intel_crtc_has_dp_encoder(pipe_config)) |
89b667f8 | 8518 | coreclk |= 0x01000000; |
ab3c759a | 8519 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 8520 | |
ab3c759a | 8521 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
221c7862 CW |
8522 | |
8523 | vlv_dpio_put(dev_priv); | |
a0c4da24 JB |
8524 | } |
8525 | ||
d288f65f | 8526 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 8527 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
8528 | { |
8529 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8530 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8531 | enum pipe pipe = crtc->pipe; |
9d556c99 | 8532 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 8533 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 8534 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 8535 | u32 dpio_val; |
9cbe40c1 | 8536 | int vco; |
9d556c99 | 8537 | |
cd2d34d9 | 8538 | /* Enable Refclk and SSC */ |
dc008bf0 JN |
8539 | intel_de_write(dev_priv, DPLL(pipe), |
8540 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
cd2d34d9 VS |
8541 | |
8542 | /* No need to actually set up the DPLL with DSI */ | |
8543 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8544 | return; | |
8545 | ||
d288f65f VS |
8546 | bestn = pipe_config->dpll.n; |
8547 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
8548 | bestm1 = pipe_config->dpll.m1; | |
8549 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8550 | bestp1 = pipe_config->dpll.p1; | |
8551 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8552 | vco = pipe_config->dpll.vco; |
a945ce7e | 8553 | dpio_val = 0; |
9cbe40c1 | 8554 | loopfilter = 0; |
9d556c99 | 8555 | |
221c7862 | 8556 | vlv_dpio_get(dev_priv); |
9d556c99 | 8557 | |
9d556c99 CML |
8558 | /* p1 and p2 divider */ |
8559 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8560 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8561 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8562 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8563 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8564 | ||
8565 | /* Feedback post-divider - m2 */ | |
8566 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8567 | ||
8568 | /* Feedback refclk divider - n and m1 */ | |
8569 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8570 | DPIO_CHV_M1_DIV_BY_2 | | |
8571 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8572 | ||
8573 | /* M2 fraction division */ | |
25a25dfc | 8574 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8575 | |
8576 | /* M2 fraction division enable */ | |
a945ce7e VP |
8577 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8578 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8579 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8580 | if (bestm2_frac) | |
8581 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8582 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8583 | |
de3a0fde VP |
8584 | /* Program digital lock detect threshold */ |
8585 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8586 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8587 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8588 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8589 | if (!bestm2_frac) | |
8590 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8591 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8592 | ||
9d556c99 | 8593 | /* Loop filter */ |
9cbe40c1 VP |
8594 | if (vco == 5400000) { |
8595 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8596 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8597 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8598 | tribuf_calcntr = 0x9; | |
8599 | } else if (vco <= 6200000) { | |
8600 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8601 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8602 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8603 | tribuf_calcntr = 0x9; | |
8604 | } else if (vco <= 6480000) { | |
8605 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8606 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8607 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8608 | tribuf_calcntr = 0x8; | |
8609 | } else { | |
8610 | /* Not supported. Apply the same limits as in the max case */ | |
8611 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8612 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8613 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8614 | tribuf_calcntr = 0; | |
8615 | } | |
9d556c99 CML |
8616 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8617 | ||
968040b2 | 8618 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8619 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8620 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8621 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8622 | ||
9d556c99 CML |
8623 | /* AFC Recal */ |
8624 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8625 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8626 | DPIO_AFC_RECAL); | |
8627 | ||
221c7862 | 8628 | vlv_dpio_put(dev_priv); |
9d556c99 CML |
8629 | } |
8630 | ||
d288f65f VS |
8631 | /** |
8632 | * vlv_force_pll_on - forcibly enable just the PLL | |
8633 | * @dev_priv: i915 private structure | |
8634 | * @pipe: pipe PLL to enable | |
8635 | * @dpll: PLL configuration | |
8636 | * | |
8637 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8638 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8639 | * be enabled. | |
8640 | */ | |
30ad9814 | 8641 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8642 | const struct dpll *dpll) |
d288f65f | 8643 | { |
b91eb5cc | 8644 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8645 | struct intel_crtc_state *pipe_config; |
8646 | ||
216383e9 | 8647 | pipe_config = intel_crtc_state_alloc(crtc); |
3f36b937 TU |
8648 | if (!pipe_config) |
8649 | return -ENOMEM; | |
8650 | ||
b104e8b2 | 8651 | pipe_config->cpu_transcoder = (enum transcoder)pipe; |
3f36b937 TU |
8652 | pipe_config->pixel_multiplier = 1; |
8653 | pipe_config->dpll = *dpll; | |
d288f65f | 8654 | |
30ad9814 | 8655 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8656 | chv_compute_dpll(crtc, pipe_config); |
8657 | chv_prepare_pll(crtc, pipe_config); | |
8658 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8659 | } else { |
3f36b937 TU |
8660 | vlv_compute_dpll(crtc, pipe_config); |
8661 | vlv_prepare_pll(crtc, pipe_config); | |
8662 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8663 | } |
3f36b937 TU |
8664 | |
8665 | kfree(pipe_config); | |
8666 | ||
8667 | return 0; | |
d288f65f VS |
8668 | } |
8669 | ||
8670 | /** | |
8671 | * vlv_force_pll_off - forcibly disable just the PLL | |
8672 | * @dev_priv: i915 private structure | |
8673 | * @pipe: pipe PLL to disable | |
8674 | * | |
8675 | * Disable the PLL for @pipe. To be used in cases where we need | |
8676 | * the PLL enabled even when @pipe is not going to be enabled. | |
8677 | */ | |
30ad9814 | 8678 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8679 | { |
30ad9814 VS |
8680 | if (IS_CHERRYVIEW(dev_priv)) |
8681 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8682 | else |
30ad9814 | 8683 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8684 | } |
8685 | ||
251ac862 DV |
8686 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8687 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8688 | struct dpll *reduced_clock) |
eb1cbe48 | 8689 | { |
9b1e14f4 | 8690 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8691 | u32 dpll; |
190f68c5 | 8692 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8693 | |
190f68c5 | 8694 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8695 | |
eb1cbe48 DV |
8696 | dpll = DPLL_VGA_MODE_DIS; |
8697 | ||
2d84d2b3 | 8698 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8699 | dpll |= DPLLB_MODE_LVDS; |
8700 | else | |
8701 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8702 | |
73f67aa8 JN |
8703 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8704 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 8705 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8706 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8707 | } |
198a037f | 8708 | |
3d6e9ee0 VS |
8709 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8710 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8711 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8712 | |
37a5650b | 8713 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8714 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8715 | |
8716 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8717 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8718 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8719 | else { | |
8720 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8721 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8722 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8723 | } | |
8724 | switch (clock->p2) { | |
8725 | case 5: | |
8726 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8727 | break; | |
8728 | case 7: | |
8729 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8730 | break; | |
8731 | case 10: | |
8732 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8733 | break; | |
8734 | case 14: | |
8735 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8736 | break; | |
8737 | } | |
9b1e14f4 | 8738 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8739 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8740 | ||
190f68c5 | 8741 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8742 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8743 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8744 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8745 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8746 | else | |
8747 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8748 | ||
8749 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8750 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8751 | |
9b1e14f4 | 8752 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8753 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8754 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8755 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8756 | } |
8757 | } | |
8758 | ||
251ac862 DV |
8759 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8760 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8761 | struct dpll *reduced_clock) |
eb1cbe48 | 8762 | { |
f47709a9 | 8763 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8764 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8765 | u32 dpll; |
190f68c5 | 8766 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8767 | |
190f68c5 | 8768 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8769 | |
eb1cbe48 DV |
8770 | dpll = DPLL_VGA_MODE_DIS; |
8771 | ||
2d84d2b3 | 8772 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8773 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8774 | } else { | |
8775 | if (clock->p1 == 2) | |
8776 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8777 | else | |
8778 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8779 | if (clock->p2 == 4) | |
8780 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8781 | } | |
8782 | ||
171d1562 VS |
8783 | /* |
8784 | * Bspec: | |
8785 | * "[Almador Errata}: For the correct operation of the muxed DVO pins | |
8786 | * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, | |
8787 | * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock | |
8788 | * Enable) must be set to “1” in both the DPLL A Control Register | |
8789 | * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." | |
8790 | * | |
8791 | * For simplicity We simply keep both bits always enabled in | |
8792 | * both DPLLS. The spec says we should disable the DVO 2X clock | |
8793 | * when not needed, but this seems to work fine in practice. | |
8794 | */ | |
8795 | if (IS_I830(dev_priv) || | |
50a0bc90 | 8796 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
8797 | dpll |= DPLL_DVO_2X_MODE; |
8798 | ||
2d84d2b3 | 8799 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8800 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8801 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8802 | else | |
8803 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8804 | ||
8805 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8806 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8807 | } |
8808 | ||
44fe7f35 | 8809 | static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) |
b0e77b9c | 8810 | { |
2225f3c6 | 8811 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
44fe7f35 ML |
8812 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8813 | enum pipe pipe = crtc->pipe; | |
8814 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
1326a92c | 8815 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
ba3f4d0a | 8816 | u32 crtc_vtotal, crtc_vblank_end; |
1caea6e9 | 8817 | int vsyncshift = 0; |
4d8a62ea DV |
8818 | |
8819 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8820 | * the hw state checker will get angry at the mismatch. */ | |
8821 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8822 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8823 | |
609aeaca | 8824 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8825 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8826 | crtc_vtotal -= 1; |
8827 | crtc_vblank_end -= 1; | |
609aeaca | 8828 | |
44fe7f35 | 8829 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8830 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8831 | else | |
8832 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8833 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8834 | if (vsyncshift < 0) |
8835 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8836 | } |
8837 | ||
6315b5d3 | 8838 | if (INTEL_GEN(dev_priv) > 3) |
dc008bf0 JN |
8839 | intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), |
8840 | vsyncshift); | |
8841 | ||
8842 | intel_de_write(dev_priv, HTOTAL(cpu_transcoder), | |
8843 | (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
8844 | intel_de_write(dev_priv, HBLANK(cpu_transcoder), | |
8845 | (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
8846 | intel_de_write(dev_priv, HSYNC(cpu_transcoder), | |
8847 | (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8848 | ||
8849 | intel_de_write(dev_priv, VTOTAL(cpu_transcoder), | |
8850 | (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); | |
8851 | intel_de_write(dev_priv, VBLANK(cpu_transcoder), | |
8852 | (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); | |
8853 | intel_de_write(dev_priv, VSYNC(cpu_transcoder), | |
8854 | (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
b0e77b9c | 8855 | |
b5e508d4 PZ |
8856 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8857 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8858 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8859 | * bits. */ | |
772c2a51 | 8860 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 | 8861 | (pipe == PIPE_B || pipe == PIPE_C)) |
dc008bf0 JN |
8862 | intel_de_write(dev_priv, VTOTAL(pipe), |
8863 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); | |
b5e508d4 | 8864 | |
bc58be60 JN |
8865 | } |
8866 | ||
44fe7f35 | 8867 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) |
bc58be60 | 8868 | { |
2225f3c6 | 8869 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
44fe7f35 ML |
8870 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8871 | enum pipe pipe = crtc->pipe; | |
bc58be60 | 8872 | |
b0e77b9c PZ |
8873 | /* pipesrc controls the size that is scaled from, which should |
8874 | * always be the user's requested size. | |
8875 | */ | |
dc008bf0 JN |
8876 | intel_de_write(dev_priv, PIPESRC(pipe), |
8877 | ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); | |
b0e77b9c PZ |
8878 | } |
8879 | ||
60a02311 VS |
8880 | static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) |
8881 | { | |
2225f3c6 | 8882 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
60a02311 VS |
8883 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
8884 | ||
8885 | if (IS_GEN(dev_priv, 2)) | |
8886 | return false; | |
8887 | ||
8888 | if (INTEL_GEN(dev_priv) >= 9 || | |
8889 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
dc008bf0 | 8890 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; |
60a02311 | 8891 | else |
dc008bf0 | 8892 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; |
60a02311 VS |
8893 | } |
8894 | ||
1bd1bd80 | 8895 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8896 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8897 | { |
8898 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8899 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 | 8900 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
ba3f4d0a | 8901 | u32 tmp; |
1bd1bd80 | 8902 | |
dc008bf0 | 8903 | tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); |
1326a92c ML |
8904 | pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8905 | pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
3c23ed13 VK |
8906 | |
8907 | if (!transcoder_is_dsi(cpu_transcoder)) { | |
dc008bf0 | 8908 | tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); |
1326a92c | 8909 | pipe_config->hw.adjusted_mode.crtc_hblank_start = |
3c23ed13 | 8910 | (tmp & 0xffff) + 1; |
1326a92c | 8911 | pipe_config->hw.adjusted_mode.crtc_hblank_end = |
3c23ed13 VK |
8912 | ((tmp >> 16) & 0xffff) + 1; |
8913 | } | |
dc008bf0 | 8914 | tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); |
1326a92c ML |
8915 | pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8916 | pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8917 | |
dc008bf0 | 8918 | tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); |
1326a92c ML |
8919 | pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8920 | pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
3c23ed13 VK |
8921 | |
8922 | if (!transcoder_is_dsi(cpu_transcoder)) { | |
dc008bf0 | 8923 | tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); |
1326a92c | 8924 | pipe_config->hw.adjusted_mode.crtc_vblank_start = |
3c23ed13 | 8925 | (tmp & 0xffff) + 1; |
1326a92c | 8926 | pipe_config->hw.adjusted_mode.crtc_vblank_end = |
3c23ed13 VK |
8927 | ((tmp >> 16) & 0xffff) + 1; |
8928 | } | |
dc008bf0 | 8929 | tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); |
1326a92c ML |
8930 | pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8931 | pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8932 | |
60a02311 | 8933 | if (intel_pipe_is_interlaced(pipe_config)) { |
1326a92c ML |
8934 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8935 | pipe_config->hw.adjusted_mode.crtc_vtotal += 1; | |
8936 | pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8937 | } |
bc58be60 JN |
8938 | } |
8939 | ||
8940 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8941 | struct intel_crtc_state *pipe_config) | |
8942 | { | |
8943 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8944 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8945 | u32 tmp; |
1bd1bd80 | 8946 | |
dc008bf0 | 8947 | tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); |
37327abd VS |
8948 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8949 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8950 | ||
1326a92c ML |
8951 | pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h; |
8952 | pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8953 | } |
8954 | ||
f6a83288 | 8955 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8956 | struct intel_crtc_state *pipe_config) |
babea61d | 8957 | { |
1326a92c ML |
8958 | mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay; |
8959 | mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal; | |
8960 | mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start; | |
8961 | mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end; | |
babea61d | 8962 | |
1326a92c ML |
8963 | mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay; |
8964 | mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal; | |
8965 | mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start; | |
8966 | mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end; | |
babea61d | 8967 | |
1326a92c | 8968 | mode->flags = pipe_config->hw.adjusted_mode.flags; |
cd13f5ab | 8969 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8970 | |
1326a92c | 8971 | mode->clock = pipe_config->hw.adjusted_mode.crtc_clock; |
cd13f5ab | 8972 | |
cd13f5ab | 8973 | drm_mode_set_name(mode); |
babea61d JB |
8974 | } |
8975 | ||
fdf73510 | 8976 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) |
84b046f3 | 8977 | { |
2225f3c6 | 8978 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 | 8979 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ba3f4d0a | 8980 | u32 pipeconf; |
84b046f3 | 8981 | |
9f11a9e4 | 8982 | pipeconf = 0; |
84b046f3 | 8983 | |
e56134bc VS |
8984 | /* we keep both pipes enabled on 830 */ |
8985 | if (IS_I830(dev_priv)) | |
dc008bf0 | 8986 | pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 8987 | |
fdf73510 | 8988 | if (crtc_state->double_wide) |
cf532bb2 | 8989 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8990 | |
ff9ce46e | 8991 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8992 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8993 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8994 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
fdf73510 | 8995 | if (crtc_state->dither && crtc_state->pipe_bpp != 30) |
ff9ce46e | 8996 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8997 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8998 | |
fdf73510 | 8999 | switch (crtc_state->pipe_bpp) { |
ff9ce46e DV |
9000 | case 18: |
9001 | pipeconf |= PIPECONF_6BPC; | |
9002 | break; | |
9003 | case 24: | |
9004 | pipeconf |= PIPECONF_8BPC; | |
9005 | break; | |
9006 | case 30: | |
9007 | pipeconf |= PIPECONF_10BPC; | |
9008 | break; | |
9009 | default: | |
9010 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
9011 | BUG(); | |
84b046f3 DV |
9012 | } |
9013 | } | |
9014 | ||
1326a92c | 9015 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 9016 | if (INTEL_GEN(dev_priv) < 4 || |
fdf73510 | 9017 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
9018 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
9019 | else | |
9020 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
27b680f9 | 9021 | } else { |
84b046f3 | 9022 | pipeconf |= PIPECONF_PROGRESSIVE; |
27b680f9 | 9023 | } |
84b046f3 | 9024 | |
920a14b2 | 9025 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
fdf73510 | 9026 | crtc_state->limited_color_range) |
9f11a9e4 | 9027 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 9028 | |
9d5441de VS |
9029 | pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); |
9030 | ||
cc7a4cff VS |
9031 | pipeconf |= PIPECONF_FRAME_START_DELAY(0); |
9032 | ||
dc008bf0 JN |
9033 | intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); |
9034 | intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); | |
84b046f3 DV |
9035 | } |
9036 | ||
81c97f52 ACO |
9037 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
9038 | struct intel_crtc_state *crtc_state) | |
9039 | { | |
9040 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9041 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9042 | const struct intel_limit *limit; |
81c97f52 ACO |
9043 | int refclk = 48000; |
9044 | ||
9045 | memset(&crtc_state->dpll_hw_state, 0, | |
9046 | sizeof(crtc_state->dpll_hw_state)); | |
9047 | ||
2d84d2b3 | 9048 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
9049 | if (intel_panel_use_ssc(dev_priv)) { |
9050 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9051 | drm_dbg_kms(&dev_priv->drm, |
9052 | "using SSC reference clock of %d kHz\n", | |
9053 | refclk); | |
81c97f52 ACO |
9054 | } |
9055 | ||
9056 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 9057 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
9058 | limit = &intel_limits_i8xx_dvo; |
9059 | } else { | |
9060 | limit = &intel_limits_i8xx_dac; | |
9061 | } | |
9062 | ||
9063 | if (!crtc_state->clock_set && | |
9064 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9065 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9066 | drm_err(&dev_priv->drm, |
9067 | "Couldn't find PLL settings for mode!\n"); | |
81c97f52 ACO |
9068 | return -EINVAL; |
9069 | } | |
9070 | ||
9071 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
9072 | ||
9073 | return 0; | |
9074 | } | |
9075 | ||
19ec6693 ACO |
9076 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
9077 | struct intel_crtc_state *crtc_state) | |
9078 | { | |
d2daff2c | 9079 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1b6f4958 | 9080 | const struct intel_limit *limit; |
19ec6693 ACO |
9081 | int refclk = 96000; |
9082 | ||
9083 | memset(&crtc_state->dpll_hw_state, 0, | |
9084 | sizeof(crtc_state->dpll_hw_state)); | |
9085 | ||
2d84d2b3 | 9086 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
9087 | if (intel_panel_use_ssc(dev_priv)) { |
9088 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9089 | drm_dbg_kms(&dev_priv->drm, |
9090 | "using SSC reference clock of %d kHz\n", | |
9091 | refclk); | |
19ec6693 ACO |
9092 | } |
9093 | ||
d2daff2c | 9094 | if (intel_is_dual_link_lvds(dev_priv)) |
19ec6693 ACO |
9095 | limit = &intel_limits_g4x_dual_channel_lvds; |
9096 | else | |
9097 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
9098 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
9099 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 9100 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 9101 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
9102 | limit = &intel_limits_g4x_sdvo; |
9103 | } else { | |
9104 | /* The option is for other outputs */ | |
9105 | limit = &intel_limits_i9xx_sdvo; | |
9106 | } | |
9107 | ||
9108 | if (!crtc_state->clock_set && | |
9109 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9110 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9111 | drm_err(&dev_priv->drm, |
9112 | "Couldn't find PLL settings for mode!\n"); | |
19ec6693 ACO |
9113 | return -EINVAL; |
9114 | } | |
9115 | ||
9116 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
9117 | ||
9118 | return 0; | |
9119 | } | |
9120 | ||
70e8aa21 ACO |
9121 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
9122 | struct intel_crtc_state *crtc_state) | |
9123 | { | |
9124 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9125 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9126 | const struct intel_limit *limit; |
70e8aa21 ACO |
9127 | int refclk = 96000; |
9128 | ||
9129 | memset(&crtc_state->dpll_hw_state, 0, | |
9130 | sizeof(crtc_state->dpll_hw_state)); | |
9131 | ||
2d84d2b3 | 9132 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
9133 | if (intel_panel_use_ssc(dev_priv)) { |
9134 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9135 | drm_dbg_kms(&dev_priv->drm, |
9136 | "using SSC reference clock of %d kHz\n", | |
9137 | refclk); | |
70e8aa21 ACO |
9138 | } |
9139 | ||
1d218220 | 9140 | limit = &pnv_limits_lvds; |
70e8aa21 | 9141 | } else { |
1d218220 | 9142 | limit = &pnv_limits_sdvo; |
70e8aa21 ACO |
9143 | } |
9144 | ||
9145 | if (!crtc_state->clock_set && | |
9146 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9147 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9148 | drm_err(&dev_priv->drm, |
9149 | "Couldn't find PLL settings for mode!\n"); | |
70e8aa21 ACO |
9150 | return -EINVAL; |
9151 | } | |
9152 | ||
9153 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
9154 | ||
9155 | return 0; | |
9156 | } | |
9157 | ||
190f68c5 ACO |
9158 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
9159 | struct intel_crtc_state *crtc_state) | |
79e53945 | 9160 | { |
c7653199 | 9161 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9162 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 9163 | const struct intel_limit *limit; |
81c97f52 | 9164 | int refclk = 96000; |
79e53945 | 9165 | |
dd3cd74a ACO |
9166 | memset(&crtc_state->dpll_hw_state, 0, |
9167 | sizeof(crtc_state->dpll_hw_state)); | |
9168 | ||
2d84d2b3 | 9169 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
9170 | if (intel_panel_use_ssc(dev_priv)) { |
9171 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
cd49f818 WK |
9172 | drm_dbg_kms(&dev_priv->drm, |
9173 | "using SSC reference clock of %d kHz\n", | |
9174 | refclk); | |
70e8aa21 | 9175 | } |
43565a06 | 9176 | |
70e8aa21 ACO |
9177 | limit = &intel_limits_i9xx_lvds; |
9178 | } else { | |
9179 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 9180 | } |
79e53945 | 9181 | |
70e8aa21 ACO |
9182 | if (!crtc_state->clock_set && |
9183 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9184 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
9185 | drm_err(&dev_priv->drm, |
9186 | "Couldn't find PLL settings for mode!\n"); | |
70e8aa21 | 9187 | return -EINVAL; |
f47709a9 | 9188 | } |
7026d4ac | 9189 | |
81c97f52 | 9190 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 9191 | |
c8f7a0db | 9192 | return 0; |
f564048e EA |
9193 | } |
9194 | ||
65b3d6a9 ACO |
9195 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
9196 | struct intel_crtc_state *crtc_state) | |
9197 | { | |
9198 | int refclk = 100000; | |
1b6f4958 | 9199 | const struct intel_limit *limit = &intel_limits_chv; |
cd49f818 | 9200 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
65b3d6a9 ACO |
9201 | |
9202 | memset(&crtc_state->dpll_hw_state, 0, | |
9203 | sizeof(crtc_state->dpll_hw_state)); | |
9204 | ||
65b3d6a9 ACO |
9205 | if (!crtc_state->clock_set && |
9206 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9207 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 | 9208 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); |
65b3d6a9 ACO |
9209 | return -EINVAL; |
9210 | } | |
9211 | ||
9212 | chv_compute_dpll(crtc, crtc_state); | |
9213 | ||
9214 | return 0; | |
9215 | } | |
9216 | ||
9217 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
9218 | struct intel_crtc_state *crtc_state) | |
9219 | { | |
9220 | int refclk = 100000; | |
1b6f4958 | 9221 | const struct intel_limit *limit = &intel_limits_vlv; |
cd49f818 | 9222 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
65b3d6a9 ACO |
9223 | |
9224 | memset(&crtc_state->dpll_hw_state, 0, | |
9225 | sizeof(crtc_state->dpll_hw_state)); | |
9226 | ||
65b3d6a9 ACO |
9227 | if (!crtc_state->clock_set && |
9228 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
9229 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 | 9230 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); |
65b3d6a9 ACO |
9231 | return -EINVAL; |
9232 | } | |
9233 | ||
9234 | vlv_compute_dpll(crtc, crtc_state); | |
9235 | ||
9236 | return 0; | |
9237 | } | |
9238 | ||
b7c8093f VS |
9239 | static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) |
9240 | { | |
9241 | if (IS_I830(dev_priv)) | |
9242 | return false; | |
9243 | ||
9244 | return INTEL_GEN(dev_priv) >= 4 || | |
9245 | IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); | |
9246 | } | |
9247 | ||
eac9c585 | 9248 | static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) |
2fa2fe9a | 9249 | { |
eac9c585 | 9250 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6315b5d3 | 9251 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ba3f4d0a | 9252 | u32 tmp; |
2fa2fe9a | 9253 | |
b7c8093f | 9254 | if (!i9xx_has_pfit(dev_priv)) |
dc9e7dec VS |
9255 | return; |
9256 | ||
dc008bf0 | 9257 | tmp = intel_de_read(dev_priv, PFIT_CONTROL); |
06922821 DV |
9258 | if (!(tmp & PFIT_ENABLE)) |
9259 | return; | |
2fa2fe9a | 9260 | |
06922821 | 9261 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 9262 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
9263 | if (crtc->pipe != PIPE_B) |
9264 | return; | |
2fa2fe9a DV |
9265 | } else { |
9266 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
9267 | return; | |
9268 | } | |
9269 | ||
eac9c585 VS |
9270 | crtc_state->gmch_pfit.control = tmp; |
9271 | crtc_state->gmch_pfit.pgm_ratios = | |
9272 | intel_de_read(dev_priv, PFIT_PGM_RATIOS); | |
2fa2fe9a DV |
9273 | } |
9274 | ||
acbec814 | 9275 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9276 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
9277 | { |
9278 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9279 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 9280 | enum pipe pipe = crtc->pipe; |
9e2c8475 | 9281 | struct dpll clock; |
acbec814 | 9282 | u32 mdiv; |
662c6ecb | 9283 | int refclk = 100000; |
acbec814 | 9284 | |
b521973b VS |
9285 | /* In case of DSI, DPLL will not be used */ |
9286 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
9287 | return; |
9288 | ||
221c7862 | 9289 | vlv_dpio_get(dev_priv); |
ab3c759a | 9290 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
221c7862 | 9291 | vlv_dpio_put(dev_priv); |
acbec814 JB |
9292 | |
9293 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
9294 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
9295 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
9296 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
9297 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
9298 | ||
dccbea3b | 9299 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
9300 | } |
9301 | ||
5724dbd1 DL |
9302 | static void |
9303 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
9304 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
9305 | { |
9306 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9307 | struct drm_i915_private *dev_priv = to_i915(dev); |
282e83ef VS |
9308 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
9309 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
eade6c89 | 9310 | enum pipe pipe; |
1ad292b5 | 9311 | u32 val, base, offset; |
1ad292b5 | 9312 | int fourcc, pixel_format; |
6761dd31 | 9313 | unsigned int aligned_height; |
b113d5ee | 9314 | struct drm_framebuffer *fb; |
1b842c89 | 9315 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 9316 | |
eade6c89 | 9317 | if (!plane->get_hw_state(plane, &pipe)) |
42a7b088 DL |
9318 | return; |
9319 | ||
e57291c2 | 9320 | drm_WARN_ON(dev, pipe != crtc->pipe); |
eade6c89 | 9321 | |
d9806c9f | 9322 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9323 | if (!intel_fb) { |
cd49f818 | 9324 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); |
1ad292b5 JB |
9325 | return; |
9326 | } | |
9327 | ||
1b842c89 DL |
9328 | fb = &intel_fb->base; |
9329 | ||
d2e9f5fc VS |
9330 | fb->dev = dev; |
9331 | ||
dc008bf0 | 9332 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
2924b8cc | 9333 | |
6315b5d3 | 9334 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 9335 | if (val & DISPPLANE_TILED) { |
49af449b | 9336 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 9337 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e | 9338 | } |
f43348a3 VS |
9339 | |
9340 | if (val & DISPPLANE_ROTATE_180) | |
9341 | plane_config->rotation = DRM_MODE_ROTATE_180; | |
18c5247e | 9342 | } |
1ad292b5 | 9343 | |
f43348a3 VS |
9344 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && |
9345 | val & DISPPLANE_MIRROR) | |
9346 | plane_config->rotation |= DRM_MODE_REFLECT_X; | |
9347 | ||
1ad292b5 | 9348 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
b35d63fa | 9349 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 9350 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 9351 | |
81894b2f | 9352 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
dc008bf0 JN |
9353 | offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); |
9354 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; | |
81894b2f | 9355 | } else if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 9356 | if (plane_config->tiling) |
dc008bf0 JN |
9357 | offset = intel_de_read(dev_priv, |
9358 | DSPTILEOFF(i9xx_plane)); | |
1ad292b5 | 9359 | else |
dc008bf0 JN |
9360 | offset = intel_de_read(dev_priv, |
9361 | DSPLINOFF(i9xx_plane)); | |
9362 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; | |
1ad292b5 | 9363 | } else { |
dc008bf0 | 9364 | base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); |
1ad292b5 JB |
9365 | } |
9366 | plane_config->base = base; | |
9367 | ||
dc008bf0 | 9368 | val = intel_de_read(dev_priv, PIPESRC(pipe)); |
b113d5ee DL |
9369 | fb->width = ((val >> 16) & 0xfff) + 1; |
9370 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 | 9371 | |
dc008bf0 | 9372 | val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); |
b113d5ee | 9373 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 9374 | |
d88c4afd | 9375 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 9376 | |
f37b5c2b | 9377 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 9378 | |
cd49f818 WK |
9379 | drm_dbg_kms(&dev_priv->drm, |
9380 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9381 | crtc->base.name, plane->base.name, fb->width, fb->height, | |
9382 | fb->format->cpp[0] * 8, base, fb->pitches[0], | |
9383 | plane_config->size); | |
1ad292b5 | 9384 | |
2d14030b | 9385 | plane_config->fb = intel_fb; |
1ad292b5 JB |
9386 | } |
9387 | ||
70b23a98 | 9388 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9389 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
9390 | { |
9391 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9392 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 9393 | enum pipe pipe = crtc->pipe; |
70b23a98 | 9394 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9e2c8475 | 9395 | struct dpll clock; |
0d7b6b11 | 9396 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
9397 | int refclk = 100000; |
9398 | ||
b521973b VS |
9399 | /* In case of DSI, DPLL will not be used */ |
9400 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
9401 | return; | |
9402 | ||
221c7862 | 9403 | vlv_dpio_get(dev_priv); |
70b23a98 VS |
9404 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
9405 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
9406 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
9407 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 9408 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
221c7862 | 9409 | vlv_dpio_put(dev_priv); |
70b23a98 VS |
9410 | |
9411 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
9412 | clock.m2 = (pll_dw0 & 0xff) << 22; |
9413 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
9414 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
9415 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
9416 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
9417 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
9418 | ||
dccbea3b | 9419 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
9420 | } |
9421 | ||
b10d1173 VS |
9422 | static enum intel_output_format |
9423 | bdw_get_pipemisc_output_format(struct intel_crtc *crtc) | |
33b7f3ee SS |
9424 | { |
9425 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
b10d1173 VS |
9426 | u32 tmp; |
9427 | ||
dc008bf0 | 9428 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); |
b10d1173 VS |
9429 | |
9430 | if (tmp & PIPEMISC_YUV420_ENABLE) { | |
9431 | /* We support 4:2:0 in full blend mode only */ | |
e57291c2 PB |
9432 | drm_WARN_ON(&dev_priv->drm, |
9433 | (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); | |
33b7f3ee | 9434 | |
b10d1173 VS |
9435 | return INTEL_OUTPUT_FORMAT_YCBCR420; |
9436 | } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { | |
9437 | return INTEL_OUTPUT_FORMAT_YCBCR444; | |
9438 | } else { | |
9439 | return INTEL_OUTPUT_FORMAT_RGB; | |
9440 | } | |
33b7f3ee SS |
9441 | } |
9442 | ||
5f29ab23 VS |
9443 | static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) |
9444 | { | |
2225f3c6 | 9445 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
5f29ab23 VS |
9446 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
9447 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
9448 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; | |
9449 | u32 tmp; | |
9450 | ||
dc008bf0 | 9451 | tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); |
5f29ab23 VS |
9452 | |
9453 | if (tmp & DISPPLANE_GAMMA_ENABLE) | |
9454 | crtc_state->gamma_enable = true; | |
8271b2ef VS |
9455 | |
9456 | if (!HAS_GMCH(dev_priv) && | |
9457 | tmp & DISPPLANE_PIPE_CSC_ENABLE) | |
9458 | crtc_state->csc_enable = true; | |
5f29ab23 VS |
9459 | } |
9460 | ||
0e8ffe1b | 9461 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9462 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9463 | { |
6315b5d3 | 9464 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9465 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 9466 | intel_wakeref_t wakeref; |
ba3f4d0a | 9467 | u32 tmp; |
1729050e | 9468 | bool ret; |
0e8ffe1b | 9469 | |
1729050e | 9470 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
0e6e0be4 CW |
9471 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
9472 | if (!wakeref) | |
b5482bd0 ID |
9473 | return false; |
9474 | ||
d9facae6 | 9475 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
e143a21c | 9476 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9477 | pipe_config->shared_dpll = NULL; |
eccb140b | 9478 | |
1729050e ID |
9479 | ret = false; |
9480 | ||
dc008bf0 | 9481 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); |
0e8ffe1b | 9482 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 9483 | goto out; |
0e8ffe1b | 9484 | |
9beb5fea TU |
9485 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
9486 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
9487 | switch (tmp & PIPECONF_BPC_MASK) { |
9488 | case PIPECONF_6BPC: | |
9489 | pipe_config->pipe_bpp = 18; | |
9490 | break; | |
9491 | case PIPECONF_8BPC: | |
9492 | pipe_config->pipe_bpp = 24; | |
9493 | break; | |
9494 | case PIPECONF_10BPC: | |
9495 | pipe_config->pipe_bpp = 30; | |
9496 | break; | |
9497 | default: | |
9498 | break; | |
9499 | } | |
9500 | } | |
9501 | ||
920a14b2 | 9502 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 9503 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
9504 | pipe_config->limited_color_range = true; |
9505 | ||
9d5441de VS |
9506 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >> |
9507 | PIPECONF_GAMMA_MODE_SHIFT; | |
9508 | ||
9fdfb8e7 | 9509 | if (IS_CHERRYVIEW(dev_priv)) |
dc008bf0 JN |
9510 | pipe_config->cgm_mode = intel_de_read(dev_priv, |
9511 | CGM_PIPE_MODE(crtc->pipe)); | |
9fdfb8e7 | 9512 | |
5f29ab23 | 9513 | i9xx_get_pipe_color_config(pipe_config); |
3633e511 | 9514 | intel_color_get_config(pipe_config); |
5f29ab23 | 9515 | |
6315b5d3 | 9516 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
9517 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
9518 | ||
1bd1bd80 | 9519 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9520 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9521 | |
eac9c585 | 9522 | i9xx_get_pfit_config(pipe_config); |
2fa2fe9a | 9523 | |
6315b5d3 | 9524 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 9525 | /* No way to read it out on pipes B and C */ |
920a14b2 | 9526 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
9527 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
9528 | else | |
dc008bf0 | 9529 | tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); |
6c49f241 DV |
9530 | pipe_config->pixel_multiplier = |
9531 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
9532 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 9533 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 9534 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 9535 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
dc008bf0 | 9536 | tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); |
6c49f241 DV |
9537 | pipe_config->pixel_multiplier = |
9538 | ((tmp & SDVO_MULTIPLIER_MASK) | |
9539 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
9540 | } else { | |
9541 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
9542 | * port and will be fixed up in the encoder->get_config | |
9543 | * function. */ | |
9544 | pipe_config->pixel_multiplier = 1; | |
9545 | } | |
dc008bf0 JN |
9546 | pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, |
9547 | DPLL(crtc->pipe)); | |
920a14b2 | 9548 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
dc008bf0 JN |
9549 | pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, |
9550 | FP0(crtc->pipe)); | |
9551 | pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, | |
9552 | FP1(crtc->pipe)); | |
165e901c VS |
9553 | } else { |
9554 | /* Mask out read-only status bits. */ | |
9555 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
9556 | DPLL_PORTC_READY_MASK | | |
9557 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 9558 | } |
6c49f241 | 9559 | |
920a14b2 | 9560 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 9561 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 9562 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
9563 | vlv_crtc_clock_get(crtc, pipe_config); |
9564 | else | |
9565 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 9566 | |
0f64614d VS |
9567 | /* |
9568 | * Normally the dotclock is filled in by the encoder .get_config() | |
9569 | * but in case the pipe is enabled w/o any ports we need a sane | |
9570 | * default. | |
9571 | */ | |
1326a92c | 9572 | pipe_config->hw.adjusted_mode.crtc_clock = |
0f64614d VS |
9573 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
9574 | ||
1729050e ID |
9575 | ret = true; |
9576 | ||
9577 | out: | |
0e6e0be4 | 9578 | intel_display_power_put(dev_priv, power_domain, wakeref); |
1729050e ID |
9579 | |
9580 | return ret; | |
0e8ffe1b DV |
9581 | } |
9582 | ||
9eae5e27 | 9583 | static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 9584 | { |
13d83a67 | 9585 | struct intel_encoder *encoder; |
1c1a24d2 | 9586 | int i; |
74cfd7ac | 9587 | u32 val, final; |
13d83a67 | 9588 | bool has_lvds = false; |
199e5d79 | 9589 | bool has_cpu_edp = false; |
199e5d79 | 9590 | bool has_panel = false; |
99eb6a01 KP |
9591 | bool has_ck505 = false; |
9592 | bool can_ssc = false; | |
1c1a24d2 | 9593 | bool using_ssc_source = false; |
13d83a67 JB |
9594 | |
9595 | /* We need to take the global config into account */ | |
c39055b0 | 9596 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
9597 | switch (encoder->type) { |
9598 | case INTEL_OUTPUT_LVDS: | |
9599 | has_panel = true; | |
9600 | has_lvds = true; | |
9601 | break; | |
9602 | case INTEL_OUTPUT_EDP: | |
9603 | has_panel = true; | |
8f4f2797 | 9604 | if (encoder->port == PORT_A) |
199e5d79 KP |
9605 | has_cpu_edp = true; |
9606 | break; | |
6847d71b PZ |
9607 | default: |
9608 | break; | |
13d83a67 JB |
9609 | } |
9610 | } | |
9611 | ||
6e266956 | 9612 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 9613 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
9614 | can_ssc = has_ck505; |
9615 | } else { | |
9616 | has_ck505 = false; | |
9617 | can_ssc = true; | |
9618 | } | |
9619 | ||
1c1a24d2 | 9620 | /* Check if any DPLLs are using the SSC source */ |
353ad959 | 9621 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { |
dc008bf0 | 9622 | u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); |
1c1a24d2 L |
9623 | |
9624 | if (!(temp & DPLL_VCO_ENABLE)) | |
9625 | continue; | |
9626 | ||
9627 | if ((temp & PLL_REF_INPUT_MASK) == | |
9628 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
9629 | using_ssc_source = true; | |
9630 | break; | |
9631 | } | |
9632 | } | |
9633 | ||
cd49f818 WK |
9634 | drm_dbg_kms(&dev_priv->drm, |
9635 | "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
9636 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
9637 | |
9638 | /* Ironlake: try to setup display ref clock before DPLL | |
9639 | * enabling. This is only under driver's control after | |
9640 | * PCH B stepping, previous chipset stepping should be | |
9641 | * ignoring this setting. | |
9642 | */ | |
dc008bf0 | 9643 | val = intel_de_read(dev_priv, PCH_DREF_CONTROL); |
74cfd7ac CW |
9644 | |
9645 | /* As we must carefully and slowly disable/enable each source in turn, | |
9646 | * compute the final state we want first and check if we need to | |
9647 | * make any changes at all. | |
9648 | */ | |
9649 | final = val; | |
9650 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
9651 | if (has_ck505) | |
9652 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
9653 | else | |
9654 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
9655 | ||
8c07eb68 | 9656 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 9657 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 9658 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
9659 | |
9660 | if (has_panel) { | |
9661 | final |= DREF_SSC_SOURCE_ENABLE; | |
9662 | ||
9663 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9664 | final |= DREF_SSC1_ENABLE; | |
9665 | ||
9666 | if (has_cpu_edp) { | |
9667 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9668 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9669 | else | |
9670 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9671 | } else | |
9672 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9673 | } else if (using_ssc_source) { |
9674 | final |= DREF_SSC_SOURCE_ENABLE; | |
9675 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9676 | } |
9677 | ||
9678 | if (final == val) | |
9679 | return; | |
9680 | ||
13d83a67 | 9681 | /* Always enable nonspread source */ |
74cfd7ac | 9682 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9683 | |
99eb6a01 | 9684 | if (has_ck505) |
74cfd7ac | 9685 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9686 | else |
74cfd7ac | 9687 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9688 | |
199e5d79 | 9689 | if (has_panel) { |
74cfd7ac CW |
9690 | val &= ~DREF_SSC_SOURCE_MASK; |
9691 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9692 | |
199e5d79 | 9693 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9694 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
cd49f818 | 9695 | drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n"); |
74cfd7ac | 9696 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9697 | } else |
74cfd7ac | 9698 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9699 | |
9700 | /* Get SSC going before enabling the outputs */ | |
dc008bf0 JN |
9701 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9702 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9703 | udelay(200); |
9704 | ||
74cfd7ac | 9705 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9706 | |
9707 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9708 | if (has_cpu_edp) { |
99eb6a01 | 9709 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
cd49f818 WK |
9710 | drm_dbg_kms(&dev_priv->drm, |
9711 | "Using SSC on eDP\n"); | |
74cfd7ac | 9712 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9713 | } else |
74cfd7ac | 9714 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9715 | } else |
74cfd7ac | 9716 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9717 | |
dc008bf0 JN |
9718 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9719 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9720 | udelay(200); |
9721 | } else { | |
cd49f818 | 9722 | drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); |
199e5d79 | 9723 | |
74cfd7ac | 9724 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9725 | |
9726 | /* Turn off CPU output */ | |
74cfd7ac | 9727 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9728 | |
dc008bf0 JN |
9729 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9730 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
199e5d79 KP |
9731 | udelay(200); |
9732 | ||
1c1a24d2 | 9733 | if (!using_ssc_source) { |
cd49f818 | 9734 | drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); |
199e5d79 | 9735 | |
1c1a24d2 L |
9736 | /* Turn off the SSC source */ |
9737 | val &= ~DREF_SSC_SOURCE_MASK; | |
9738 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9739 | |
1c1a24d2 L |
9740 | /* Turn off SSC1 */ |
9741 | val &= ~DREF_SSC1_ENABLE; | |
9742 | ||
dc008bf0 JN |
9743 | intel_de_write(dev_priv, PCH_DREF_CONTROL, val); |
9744 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); | |
1c1a24d2 L |
9745 | udelay(200); |
9746 | } | |
13d83a67 | 9747 | } |
74cfd7ac CW |
9748 | |
9749 | BUG_ON(val != final); | |
13d83a67 JB |
9750 | } |
9751 | ||
f31f2d55 | 9752 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9753 | { |
ba3f4d0a | 9754 | u32 tmp; |
dde86e2d | 9755 | |
dc008bf0 | 9756 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); |
0ff066a9 | 9757 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
dc008bf0 | 9758 | intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); |
dde86e2d | 9759 | |
dc008bf0 | 9760 | if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & |
cf3598c2 | 9761 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
cd49f818 | 9762 | drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); |
dde86e2d | 9763 | |
dc008bf0 | 9764 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); |
0ff066a9 | 9765 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
dc008bf0 | 9766 | intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); |
dde86e2d | 9767 | |
dc008bf0 | 9768 | if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & |
cf3598c2 | 9769 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
cd49f818 | 9770 | drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9771 | } |
9772 | ||
9773 | /* WaMPhyProgramming:hsw */ | |
9774 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9775 | { | |
ba3f4d0a | 9776 | u32 tmp; |
dde86e2d PZ |
9777 | |
9778 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9779 | tmp &= ~(0xFF << 24); | |
9780 | tmp |= (0x12 << 24); | |
9781 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9782 | ||
dde86e2d PZ |
9783 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9784 | tmp |= (1 << 11); | |
9785 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9786 | ||
9787 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9788 | tmp |= (1 << 11); | |
9789 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9790 | ||
dde86e2d PZ |
9791 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9792 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9793 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9794 | ||
9795 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9796 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9797 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9798 | ||
0ff066a9 PZ |
9799 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9800 | tmp &= ~(7 << 13); | |
9801 | tmp |= (5 << 13); | |
9802 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9803 | |
0ff066a9 PZ |
9804 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9805 | tmp &= ~(7 << 13); | |
9806 | tmp |= (5 << 13); | |
9807 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9808 | |
9809 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9810 | tmp &= ~0xFF; | |
9811 | tmp |= 0x1C; | |
9812 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9813 | ||
9814 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9815 | tmp &= ~0xFF; | |
9816 | tmp |= 0x1C; | |
9817 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9818 | ||
9819 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9820 | tmp &= ~(0xFF << 16); | |
9821 | tmp |= (0x1C << 16); | |
9822 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9823 | ||
9824 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9825 | tmp &= ~(0xFF << 16); | |
9826 | tmp |= (0x1C << 16); | |
9827 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9828 | ||
0ff066a9 PZ |
9829 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9830 | tmp |= (1 << 27); | |
9831 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9832 | |
0ff066a9 PZ |
9833 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9834 | tmp |= (1 << 27); | |
9835 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9836 | |
0ff066a9 PZ |
9837 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9838 | tmp &= ~(0xF << 28); | |
9839 | tmp |= (4 << 28); | |
9840 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9841 | |
0ff066a9 PZ |
9842 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9843 | tmp &= ~(0xF << 28); | |
9844 | tmp |= (4 << 28); | |
9845 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9846 | } |
9847 | ||
2fa86a1f PZ |
9848 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9849 | * Programming" based on the parameters passed: | |
9850 | * - Sequence to enable CLKOUT_DP | |
9851 | * - Sequence to enable CLKOUT_DP without spread | |
9852 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9853 | */ | |
c39055b0 ACO |
9854 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
9855 | bool with_spread, bool with_fdi) | |
f31f2d55 | 9856 | { |
ba3f4d0a | 9857 | u32 reg, tmp; |
2fa86a1f | 9858 | |
e57291c2 PB |
9859 | if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, |
9860 | "FDI requires downspread\n")) | |
2fa86a1f | 9861 | with_spread = true; |
e57291c2 PB |
9862 | if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && |
9863 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9864 | with_fdi = false; |
f31f2d55 | 9865 | |
a580516d | 9866 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9867 | |
9868 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9869 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9870 | tmp |= SBI_SSCCTL_PATHALT; | |
9871 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9872 | ||
9873 | udelay(24); | |
9874 | ||
2fa86a1f PZ |
9875 | if (with_spread) { |
9876 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9877 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9878 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9879 | |
2fa86a1f PZ |
9880 | if (with_fdi) { |
9881 | lpt_reset_fdi_mphy(dev_priv); | |
9882 | lpt_program_fdi_mphy(dev_priv); | |
9883 | } | |
9884 | } | |
dde86e2d | 9885 | |
4f8036a2 | 9886 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9887 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9888 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9889 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9890 | |
a580516d | 9891 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9892 | } |
9893 | ||
47701c3b | 9894 | /* Sequence to disable CLKOUT_DP */ |
46034d2b | 9895 | void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 9896 | { |
ba3f4d0a | 9897 | u32 reg, tmp; |
47701c3b | 9898 | |
a580516d | 9899 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9900 | |
4f8036a2 | 9901 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9902 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9903 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9904 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9905 | ||
9906 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9907 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9908 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9909 | tmp |= SBI_SSCCTL_PATHALT; | |
9910 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9911 | udelay(32); | |
9912 | } | |
9913 | tmp |= SBI_SSCCTL_DISABLE; | |
9914 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9915 | } | |
9916 | ||
a580516d | 9917 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9918 | } |
9919 | ||
f7be2c21 VS |
9920 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9921 | ||
ba3f4d0a | 9922 | static const u16 sscdivintphase[] = { |
f7be2c21 VS |
9923 | [BEND_IDX( 50)] = 0x3B23, |
9924 | [BEND_IDX( 45)] = 0x3B23, | |
9925 | [BEND_IDX( 40)] = 0x3C23, | |
9926 | [BEND_IDX( 35)] = 0x3C23, | |
9927 | [BEND_IDX( 30)] = 0x3D23, | |
9928 | [BEND_IDX( 25)] = 0x3D23, | |
9929 | [BEND_IDX( 20)] = 0x3E23, | |
9930 | [BEND_IDX( 15)] = 0x3E23, | |
9931 | [BEND_IDX( 10)] = 0x3F23, | |
9932 | [BEND_IDX( 5)] = 0x3F23, | |
9933 | [BEND_IDX( 0)] = 0x0025, | |
9934 | [BEND_IDX( -5)] = 0x0025, | |
9935 | [BEND_IDX(-10)] = 0x0125, | |
9936 | [BEND_IDX(-15)] = 0x0125, | |
9937 | [BEND_IDX(-20)] = 0x0225, | |
9938 | [BEND_IDX(-25)] = 0x0225, | |
9939 | [BEND_IDX(-30)] = 0x0325, | |
9940 | [BEND_IDX(-35)] = 0x0325, | |
9941 | [BEND_IDX(-40)] = 0x0425, | |
9942 | [BEND_IDX(-45)] = 0x0425, | |
9943 | [BEND_IDX(-50)] = 0x0525, | |
9944 | }; | |
9945 | ||
9946 | /* | |
9947 | * Bend CLKOUT_DP | |
9948 | * steps -50 to 50 inclusive, in steps of 5 | |
9949 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9950 | * change in clock period = -(steps / 10) * 5.787 ps | |
9951 | */ | |
9952 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9953 | { | |
ba3f4d0a | 9954 | u32 tmp; |
f7be2c21 VS |
9955 | int idx = BEND_IDX(steps); |
9956 | ||
e57291c2 | 9957 | if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) |
f7be2c21 VS |
9958 | return; |
9959 | ||
e57291c2 | 9960 | if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) |
f7be2c21 VS |
9961 | return; |
9962 | ||
9963 | mutex_lock(&dev_priv->sb_lock); | |
9964 | ||
9965 | if (steps % 10 != 0) | |
9966 | tmp = 0xAAAAAAAB; | |
9967 | else | |
9968 | tmp = 0x00000000; | |
9969 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9970 | ||
9971 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9972 | tmp &= 0xffff0000; | |
9973 | tmp |= sscdivintphase[idx]; | |
9974 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9975 | ||
9976 | mutex_unlock(&dev_priv->sb_lock); | |
9977 | } | |
9978 | ||
9979 | #undef BEND_IDX | |
9980 | ||
b16c7ed9 VS |
9981 | static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) |
9982 | { | |
dc008bf0 JN |
9983 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
9984 | u32 ctl = intel_de_read(dev_priv, SPLL_CTL); | |
b16c7ed9 VS |
9985 | |
9986 | if ((ctl & SPLL_PLL_ENABLE) == 0) | |
9987 | return false; | |
9988 | ||
4a95e36f | 9989 | if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC && |
b16c7ed9 VS |
9990 | (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) |
9991 | return true; | |
9992 | ||
9993 | if (IS_BROADWELL(dev_priv) && | |
4a95e36f | 9994 | (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW) |
b16c7ed9 VS |
9995 | return true; |
9996 | ||
9997 | return false; | |
9998 | } | |
9999 | ||
10000 | static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, | |
10001 | enum intel_dpll_id id) | |
10002 | { | |
dc008bf0 JN |
10003 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
10004 | u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); | |
b16c7ed9 VS |
10005 | |
10006 | if ((ctl & WRPLL_PLL_ENABLE) == 0) | |
10007 | return false; | |
10008 | ||
4a95e36f | 10009 | if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC) |
b16c7ed9 VS |
10010 | return true; |
10011 | ||
10012 | if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) && | |
4a95e36f | 10013 | (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW && |
b16c7ed9 VS |
10014 | (fuse_strap & HSW_CPU_SSC_ENABLE) == 0) |
10015 | return true; | |
10016 | ||
10017 | return false; | |
10018 | } | |
10019 | ||
c39055b0 | 10020 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 10021 | { |
bf8fa3d3 | 10022 | struct intel_encoder *encoder; |
b16c7ed9 | 10023 | bool has_fdi = false; |
bf8fa3d3 | 10024 | |
c39055b0 | 10025 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
10026 | switch (encoder->type) { |
10027 | case INTEL_OUTPUT_ANALOG: | |
b16c7ed9 | 10028 | has_fdi = true; |
bf8fa3d3 | 10029 | break; |
6847d71b PZ |
10030 | default: |
10031 | break; | |
bf8fa3d3 PZ |
10032 | } |
10033 | } | |
10034 | ||
b16c7ed9 VS |
10035 | /* |
10036 | * The BIOS may have decided to use the PCH SSC | |
10037 | * reference so we must not disable it until the | |
10038 | * relevant PLLs have stopped relying on it. We'll | |
10039 | * just leave the PCH SSC reference enabled in case | |
10040 | * any active PLL is using it. It will get disabled | |
10041 | * after runtime suspend if we don't have FDI. | |
10042 | * | |
10043 | * TODO: Move the whole reference clock handling | |
10044 | * to the modeset sequence proper so that we can | |
10045 | * actually enable/disable/reconfigure these things | |
10046 | * safely. To do that we need to introduce a real | |
10047 | * clock hierarchy. That would also allow us to do | |
10048 | * clock bending finally. | |
10049 | */ | |
dd5279c7 VS |
10050 | dev_priv->pch_ssc_use = 0; |
10051 | ||
b16c7ed9 | 10052 | if (spll_uses_pch_ssc(dev_priv)) { |
cd49f818 | 10053 | drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n"); |
dd5279c7 | 10054 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); |
b16c7ed9 VS |
10055 | } |
10056 | ||
10057 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { | |
cd49f818 | 10058 | drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n"); |
dd5279c7 | 10059 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); |
b16c7ed9 VS |
10060 | } |
10061 | ||
10062 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { | |
cd49f818 | 10063 | drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n"); |
dd5279c7 | 10064 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); |
b16c7ed9 VS |
10065 | } |
10066 | ||
dd5279c7 | 10067 | if (dev_priv->pch_ssc_use) |
b16c7ed9 VS |
10068 | return; |
10069 | ||
10070 | if (has_fdi) { | |
c39055b0 ACO |
10071 | lpt_bend_clkout_dp(dev_priv, 0); |
10072 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 10073 | } else { |
c39055b0 | 10074 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 10075 | } |
bf8fa3d3 PZ |
10076 | } |
10077 | ||
dde86e2d PZ |
10078 | /* |
10079 | * Initialize reference clocks when the driver loads | |
10080 | */ | |
c39055b0 | 10081 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 10082 | { |
6e266956 | 10083 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
9eae5e27 | 10084 | ilk_init_pch_refclk(dev_priv); |
6e266956 | 10085 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 10086 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
10087 | } |
10088 | ||
9eae5e27 | 10089 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) |
79e53945 | 10090 | { |
2225f3c6 | 10091 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 ML |
10092 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10093 | enum pipe pipe = crtc->pipe; | |
ba3f4d0a | 10094 | u32 val; |
c8203565 | 10095 | |
78114071 | 10096 | val = 0; |
c8203565 | 10097 | |
fdf73510 | 10098 | switch (crtc_state->pipe_bpp) { |
c8203565 | 10099 | case 18: |
dfd07d72 | 10100 | val |= PIPECONF_6BPC; |
c8203565 PZ |
10101 | break; |
10102 | case 24: | |
dfd07d72 | 10103 | val |= PIPECONF_8BPC; |
c8203565 PZ |
10104 | break; |
10105 | case 30: | |
dfd07d72 | 10106 | val |= PIPECONF_10BPC; |
c8203565 PZ |
10107 | break; |
10108 | case 36: | |
dfd07d72 | 10109 | val |= PIPECONF_12BPC; |
c8203565 PZ |
10110 | break; |
10111 | default: | |
cc769b62 PZ |
10112 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
10113 | BUG(); | |
c8203565 PZ |
10114 | } |
10115 | ||
fdf73510 | 10116 | if (crtc_state->dither) |
c8203565 PZ |
10117 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
10118 | ||
1326a92c | 10119 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
10120 | val |= PIPECONF_INTERLACED_ILK; |
10121 | else | |
10122 | val |= PIPECONF_PROGRESSIVE; | |
10123 | ||
d1844606 VS |
10124 | /* |
10125 | * This would end up with an odd purple hue over | |
10126 | * the entire display. Make sure we don't do it. | |
10127 | */ | |
e57291c2 PB |
10128 | drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && |
10129 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); | |
d1844606 | 10130 | |
90f8ed85 VS |
10131 | if (crtc_state->limited_color_range && |
10132 | !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) | |
3685a8f3 | 10133 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 10134 | |
d1844606 VS |
10135 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) |
10136 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; | |
10137 | ||
9d5441de VS |
10138 | val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); |
10139 | ||
cc7a4cff VS |
10140 | val |= PIPECONF_FRAME_START_DELAY(0); |
10141 | ||
dc008bf0 JN |
10142 | intel_de_write(dev_priv, PIPECONF(pipe), val); |
10143 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
c8203565 PZ |
10144 | } |
10145 | ||
1e98f88c | 10146 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) |
ee2b0b38 | 10147 | { |
2225f3c6 | 10148 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
fdf73510 ML |
10149 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10150 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
391bf048 | 10151 | u32 val = 0; |
ee2b0b38 | 10152 | |
fdf73510 | 10153 | if (IS_HASWELL(dev_priv) && crtc_state->dither) |
ee2b0b38 PZ |
10154 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
10155 | ||
1326a92c | 10156 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
10157 | val |= PIPECONF_INTERLACED_ILK; |
10158 | else | |
10159 | val |= PIPECONF_PROGRESSIVE; | |
10160 | ||
ac0f01ce VS |
10161 | if (IS_HASWELL(dev_priv) && |
10162 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
10163 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; | |
10164 | ||
dc008bf0 JN |
10165 | intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); |
10166 | intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); | |
391bf048 JN |
10167 | } |
10168 | ||
9b11215e | 10169 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) |
391bf048 | 10170 | { |
2225f3c6 | 10171 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
9b11215e VS |
10172 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
10173 | u32 val = 0; | |
756f85cf | 10174 | |
9b11215e VS |
10175 | switch (crtc_state->pipe_bpp) { |
10176 | case 18: | |
10177 | val |= PIPEMISC_DITHER_6_BPC; | |
10178 | break; | |
10179 | case 24: | |
10180 | val |= PIPEMISC_DITHER_8_BPC; | |
10181 | break; | |
10182 | case 30: | |
10183 | val |= PIPEMISC_DITHER_10_BPC; | |
10184 | break; | |
10185 | case 36: | |
10186 | val |= PIPEMISC_DITHER_12_BPC; | |
10187 | break; | |
10188 | default: | |
10189 | MISSING_CASE(crtc_state->pipe_bpp); | |
10190 | break; | |
10191 | } | |
756f85cf | 10192 | |
9b11215e VS |
10193 | if (crtc_state->dither) |
10194 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
756f85cf | 10195 | |
9b11215e VS |
10196 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
10197 | crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) | |
10198 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
8c79f844 | 10199 | |
9b11215e VS |
10200 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
10201 | val |= PIPEMISC_YUV420_ENABLE | | |
10202 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
b22ca995 | 10203 | |
09b25812 | 10204 | if (INTEL_GEN(dev_priv) >= 11 && |
b7ffc4a8 VS |
10205 | (crtc_state->active_planes & ~(icl_hdr_plane_mask() | |
10206 | BIT(PLANE_CURSOR))) == 0) | |
09b25812 VS |
10207 | val |= PIPEMISC_HDR_MODE_PRECISION; |
10208 | ||
041be481 VS |
10209 | if (INTEL_GEN(dev_priv) >= 12) |
10210 | val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; | |
10211 | ||
dc008bf0 | 10212 | intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); |
ee2b0b38 PZ |
10213 | } |
10214 | ||
8ae89743 VK |
10215 | int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) |
10216 | { | |
10217 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10218 | u32 tmp; | |
10219 | ||
dc008bf0 | 10220 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); |
8ae89743 VK |
10221 | |
10222 | switch (tmp & PIPEMISC_DITHER_BPC_MASK) { | |
10223 | case PIPEMISC_DITHER_6_BPC: | |
10224 | return 18; | |
10225 | case PIPEMISC_DITHER_8_BPC: | |
10226 | return 24; | |
10227 | case PIPEMISC_DITHER_10_BPC: | |
10228 | return 30; | |
10229 | case PIPEMISC_DITHER_12_BPC: | |
10230 | return 36; | |
10231 | default: | |
10232 | MISSING_CASE(tmp); | |
10233 | return 0; | |
10234 | } | |
10235 | } | |
10236 | ||
9eae5e27 | 10237 | int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) |
d4b1931c PZ |
10238 | { |
10239 | /* | |
10240 | * Account for spread spectrum to avoid | |
10241 | * oversubscribing the link. Max center spread | |
10242 | * is 2.5%; use 5% for safety's sake. | |
10243 | */ | |
10244 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 10245 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
10246 | } |
10247 | ||
9eae5e27 | 10248 | static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 10249 | { |
7429e9d4 | 10250 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
10251 | } |
10252 | ||
9eae5e27 LDM |
10253 | static void ilk_compute_dpll(struct intel_crtc *crtc, |
10254 | struct intel_crtc_state *crtc_state, | |
10255 | struct dpll *reduced_clock) | |
79e53945 | 10256 | { |
d2daff2c | 10257 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b75ca6f6 | 10258 | u32 dpll, fp, fp2; |
3d6e9ee0 | 10259 | int factor; |
79e53945 | 10260 | |
c1858123 | 10261 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 10262 | factor = 21; |
3d6e9ee0 | 10263 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 10264 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 10265 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
d2daff2c VS |
10266 | (HAS_PCH_IBX(dev_priv) && |
10267 | intel_is_dual_link_lvds(dev_priv))) | |
8febb297 | 10268 | factor = 25; |
27b680f9 | 10269 | } else if (crtc_state->sdvo_tv_clock) { |
8febb297 | 10270 | factor = 20; |
27b680f9 | 10271 | } |
c1858123 | 10272 | |
b75ca6f6 ACO |
10273 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
10274 | ||
9eae5e27 | 10275 | if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
10276 | fp |= FP_CB_TUNE; |
10277 | ||
10278 | if (reduced_clock) { | |
10279 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 10280 | |
b75ca6f6 ACO |
10281 | if (reduced_clock->m < factor * reduced_clock->n) |
10282 | fp2 |= FP_CB_TUNE; | |
10283 | } else { | |
10284 | fp2 = fp; | |
10285 | } | |
9a7c7890 | 10286 | |
5eddb70b | 10287 | dpll = 0; |
2c07245f | 10288 | |
3d6e9ee0 | 10289 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
10290 | dpll |= DPLLB_MODE_LVDS; |
10291 | else | |
10292 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 10293 | |
190f68c5 | 10294 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 10295 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 10296 | |
3d6e9ee0 VS |
10297 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
10298 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 10299 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 10300 | |
37a5650b | 10301 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 10302 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 10303 | |
7d7f8633 VS |
10304 | /* |
10305 | * The high speed IO clock is only really required for | |
10306 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
10307 | * possible to share the DPLL between CRT and HDMI. Enabling | |
10308 | * the clock needlessly does no real harm, except use up a | |
10309 | * bit of power potentially. | |
10310 | * | |
10311 | * We'll limit this to IVB with 3 pipes, since it has only two | |
10312 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
10313 | * driving PCH ports at the same time. On SNB we could do this, | |
10314 | * and potentially avoid enabling the second DPLL, but it's not | |
10315 | * clear if it''s a win or loss power wise. No point in doing | |
10316 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
10317 | */ | |
24977870 | 10318 | if (INTEL_NUM_PIPES(dev_priv) == 3 && |
7d7f8633 VS |
10319 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) |
10320 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
10321 | ||
a07d6787 | 10322 | /* compute bitmask from p1 value */ |
190f68c5 | 10323 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 10324 | /* also FPA1 */ |
190f68c5 | 10325 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 10326 | |
190f68c5 | 10327 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
10328 | case 5: |
10329 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
10330 | break; | |
10331 | case 7: | |
10332 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
10333 | break; | |
10334 | case 10: | |
10335 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
10336 | break; | |
10337 | case 14: | |
10338 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
10339 | break; | |
79e53945 JB |
10340 | } |
10341 | ||
3d6e9ee0 VS |
10342 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
10343 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 10344 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
10345 | else |
10346 | dpll |= PLL_REF_INPUT_DREFCLK; | |
10347 | ||
b75ca6f6 ACO |
10348 | dpll |= DPLL_VCO_ENABLE; |
10349 | ||
10350 | crtc_state->dpll_hw_state.dpll = dpll; | |
10351 | crtc_state->dpll_hw_state.fp0 = fp; | |
10352 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
10353 | } |
10354 | ||
9eae5e27 LDM |
10355 | static int ilk_crtc_compute_clock(struct intel_crtc *crtc, |
10356 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 10357 | { |
d2daff2c | 10358 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
866955fa | 10359 | struct intel_atomic_state *state = |
2225f3c6 | 10360 | to_intel_atomic_state(crtc_state->uapi.state); |
1b6f4958 | 10361 | const struct intel_limit *limit; |
997c030c | 10362 | int refclk = 120000; |
de13a2e3 | 10363 | |
dd3cd74a ACO |
10364 | memset(&crtc_state->dpll_hw_state, 0, |
10365 | sizeof(crtc_state->dpll_hw_state)); | |
10366 | ||
ded220e2 ACO |
10367 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
10368 | if (!crtc_state->has_pch_encoder) | |
10369 | return 0; | |
79e53945 | 10370 | |
2d84d2b3 | 10371 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c | 10372 | if (intel_panel_use_ssc(dev_priv)) { |
cd49f818 WK |
10373 | drm_dbg_kms(&dev_priv->drm, |
10374 | "using SSC reference clock of %d kHz\n", | |
10375 | dev_priv->vbt.lvds_ssc_freq); | |
997c030c ACO |
10376 | refclk = dev_priv->vbt.lvds_ssc_freq; |
10377 | } | |
10378 | ||
d2daff2c | 10379 | if (intel_is_dual_link_lvds(dev_priv)) { |
997c030c | 10380 | if (refclk == 100000) |
9eae5e27 | 10381 | limit = &ilk_limits_dual_lvds_100m; |
997c030c | 10382 | else |
9eae5e27 | 10383 | limit = &ilk_limits_dual_lvds; |
997c030c ACO |
10384 | } else { |
10385 | if (refclk == 100000) | |
9eae5e27 | 10386 | limit = &ilk_limits_single_lvds_100m; |
997c030c | 10387 | else |
9eae5e27 | 10388 | limit = &ilk_limits_single_lvds; |
997c030c ACO |
10389 | } |
10390 | } else { | |
9eae5e27 | 10391 | limit = &ilk_limits_dac; |
997c030c ACO |
10392 | } |
10393 | ||
364ee29d | 10394 | if (!crtc_state->clock_set && |
997c030c ACO |
10395 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
10396 | refclk, NULL, &crtc_state->dpll)) { | |
cd49f818 WK |
10397 | drm_err(&dev_priv->drm, |
10398 | "Couldn't find PLL settings for mode!\n"); | |
364ee29d | 10399 | return -EINVAL; |
f47709a9 | 10400 | } |
79e53945 | 10401 | |
9eae5e27 | 10402 | ilk_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 10403 | |
866955fa | 10404 | if (!intel_reserve_shared_dplls(state, crtc, NULL)) { |
cd49f818 WK |
10405 | drm_dbg_kms(&dev_priv->drm, |
10406 | "failed to find PLL for pipe %c\n", | |
10407 | pipe_name(crtc->pipe)); | |
ded220e2 | 10408 | return -EINVAL; |
3fb37703 | 10409 | } |
79e53945 | 10410 | |
c8f7a0db | 10411 | return 0; |
79e53945 JB |
10412 | } |
10413 | ||
eb14cb74 VS |
10414 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
10415 | struct intel_link_m_n *m_n) | |
10416 | { | |
10417 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10418 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
10419 | enum pipe pipe = crtc->pipe; |
10420 | ||
dc008bf0 JN |
10421 | m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe)); |
10422 | m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe)); | |
10423 | m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) | |
eb14cb74 | 10424 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10425 | m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe)); |
10426 | m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) | |
eb14cb74 VS |
10427 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10428 | } | |
10429 | ||
10430 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
10431 | enum transcoder transcoder, | |
b95af8be VK |
10432 | struct intel_link_m_n *m_n, |
10433 | struct intel_link_m_n *m2_n2) | |
72419203 | 10434 | { |
6315b5d3 | 10435 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 10436 | enum pipe pipe = crtc->pipe; |
72419203 | 10437 | |
6315b5d3 | 10438 | if (INTEL_GEN(dev_priv) >= 5) { |
dc008bf0 JN |
10439 | m_n->link_m = intel_de_read(dev_priv, |
10440 | PIPE_LINK_M1(transcoder)); | |
10441 | m_n->link_n = intel_de_read(dev_priv, | |
10442 | PIPE_LINK_N1(transcoder)); | |
10443 | m_n->gmch_m = intel_de_read(dev_priv, | |
10444 | PIPE_DATA_M1(transcoder)) | |
eb14cb74 | 10445 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10446 | m_n->gmch_n = intel_de_read(dev_priv, |
10447 | PIPE_DATA_N1(transcoder)); | |
10448 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder)) | |
eb14cb74 | 10449 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
4207c8b9 ML |
10450 | |
10451 | if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { | |
dc008bf0 JN |
10452 | m2_n2->link_m = intel_de_read(dev_priv, |
10453 | PIPE_LINK_M2(transcoder)); | |
10454 | m2_n2->link_n = intel_de_read(dev_priv, | |
10455 | PIPE_LINK_N2(transcoder)); | |
10456 | m2_n2->gmch_m = intel_de_read(dev_priv, | |
10457 | PIPE_DATA_M2(transcoder)) | |
b95af8be | 10458 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10459 | m2_n2->gmch_n = intel_de_read(dev_priv, |
10460 | PIPE_DATA_N2(transcoder)); | |
10461 | m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder)) | |
b95af8be VK |
10462 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10463 | } | |
eb14cb74 | 10464 | } else { |
dc008bf0 JN |
10465 | m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe)); |
10466 | m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe)); | |
10467 | m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) | |
eb14cb74 | 10468 | & ~TU_SIZE_MASK; |
dc008bf0 JN |
10469 | m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe)); |
10470 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) | |
eb14cb74 VS |
10471 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
10472 | } | |
10473 | } | |
10474 | ||
10475 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 10476 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 10477 | { |
681a8504 | 10478 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
10479 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
10480 | else | |
10481 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
10482 | &pipe_config->dp_m_n, |
10483 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 10484 | } |
72419203 | 10485 | |
9eae5e27 LDM |
10486 | static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc, |
10487 | struct intel_crtc_state *pipe_config) | |
eb14cb74 VS |
10488 | { |
10489 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 10490 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
10491 | } |
10492 | ||
35dd95b4 VS |
10493 | static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, |
10494 | u32 pos, u32 size) | |
10495 | { | |
10496 | drm_rect_init(&crtc_state->pch_pfit.dst, | |
10497 | pos >> 16, pos & 0xffff, | |
10498 | size >> 16, size & 0xffff); | |
10499 | } | |
10500 | ||
eac9c585 | 10501 | static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) |
bd2e244f | 10502 | { |
eac9c585 VS |
10503 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
10504 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10505 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
a1b2278e CK |
10506 | int id = -1; |
10507 | int i; | |
bd2e244f | 10508 | |
a1b2278e CK |
10509 | /* find scaler attached to this pipe */ |
10510 | for (i = 0; i < crtc->num_scalers; i++) { | |
35dd95b4 | 10511 | u32 ctl, pos, size; |
eac9c585 | 10512 | |
35dd95b4 VS |
10513 | ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); |
10514 | if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) | |
eac9c585 VS |
10515 | continue; |
10516 | ||
10517 | id = i; | |
10518 | crtc_state->pch_pfit.enabled = true; | |
35dd95b4 VS |
10519 | |
10520 | pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); | |
10521 | size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); | |
10522 | ||
10523 | ilk_get_pfit_pos_size(crtc_state, pos, size); | |
10524 | ||
eac9c585 VS |
10525 | scaler_state->scalers[i].in_use = true; |
10526 | break; | |
a1b2278e | 10527 | } |
bd2e244f | 10528 | |
a1b2278e | 10529 | scaler_state->scaler_id = id; |
eac9c585 | 10530 | if (id >= 0) |
a1b2278e | 10531 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
eac9c585 | 10532 | else |
a1b2278e | 10533 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
bd2e244f JB |
10534 | } |
10535 | ||
5724dbd1 | 10536 | static void |
f6df4d46 LDM |
10537 | skl_get_initial_plane_config(struct intel_crtc *crtc, |
10538 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
10539 | { |
10540 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10541 | struct drm_i915_private *dev_priv = to_i915(dev); |
282e83ef VS |
10542 | struct intel_plane *plane = to_intel_plane(crtc->base.primary); |
10543 | enum plane_id plane_id = plane->id; | |
eade6c89 | 10544 | enum pipe pipe; |
4036c78c | 10545 | u32 val, base, offset, stride_mult, tiling, alpha; |
bc8d7dff | 10546 | int fourcc, pixel_format; |
6761dd31 | 10547 | unsigned int aligned_height; |
bc8d7dff | 10548 | struct drm_framebuffer *fb; |
1b842c89 | 10549 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 10550 | |
eade6c89 | 10551 | if (!plane->get_hw_state(plane, &pipe)) |
2924b8cc VS |
10552 | return; |
10553 | ||
e57291c2 | 10554 | drm_WARN_ON(dev, pipe != crtc->pipe); |
eade6c89 | 10555 | |
d9806c9f | 10556 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 10557 | if (!intel_fb) { |
cd49f818 | 10558 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); |
bc8d7dff DL |
10559 | return; |
10560 | } | |
10561 | ||
1b842c89 DL |
10562 | fb = &intel_fb->base; |
10563 | ||
d2e9f5fc VS |
10564 | fb->dev = dev; |
10565 | ||
dc008bf0 | 10566 | val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); |
42a7b088 | 10567 | |
b5972776 JA |
10568 | if (INTEL_GEN(dev_priv) >= 11) |
10569 | pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; | |
10570 | else | |
10571 | pixel_format = val & PLANE_CTL_FORMAT_MASK; | |
4036c78c JA |
10572 | |
10573 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { | |
dc008bf0 JN |
10574 | alpha = intel_de_read(dev_priv, |
10575 | PLANE_COLOR_CTL(pipe, plane_id)); | |
4036c78c JA |
10576 | alpha &= PLANE_COLOR_ALPHA_MASK; |
10577 | } else { | |
10578 | alpha = val & PLANE_CTL_ALPHA_MASK; | |
10579 | } | |
10580 | ||
bc8d7dff | 10581 | fourcc = skl_format_to_fourcc(pixel_format, |
4036c78c | 10582 | val & PLANE_CTL_ORDER_RGBX, alpha); |
2f3f4763 | 10583 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 10584 | |
40f46283 DL |
10585 | tiling = val & PLANE_CTL_TILED_MASK; |
10586 | switch (tiling) { | |
10587 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 10588 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
10589 | break; |
10590 | case PLANE_CTL_TILED_X: | |
10591 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 10592 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
10593 | break; |
10594 | case PLANE_CTL_TILED_Y: | |
914a4fd8 | 10595 | plane_config->tiling = I915_TILING_Y; |
53867b46 | 10596 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) |
b3e57bcc DP |
10597 | fb->modifier = INTEL_GEN(dev_priv) >= 12 ? |
10598 | I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : | |
10599 | I915_FORMAT_MOD_Y_TILED_CCS; | |
2dfbf9d2 DP |
10600 | else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) |
10601 | fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; | |
2e2adb05 VS |
10602 | else |
10603 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
10604 | break; |
10605 | case PLANE_CTL_TILED_YF: | |
53867b46 | 10606 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) |
2e2adb05 VS |
10607 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; |
10608 | else | |
10609 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
10610 | break; |
10611 | default: | |
10612 | MISSING_CASE(tiling); | |
10613 | goto error; | |
10614 | } | |
10615 | ||
f43348a3 VS |
10616 | /* |
10617 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
10618 | * while i915 HW rotation is clockwise, thats why this swapping. | |
10619 | */ | |
10620 | switch (val & PLANE_CTL_ROTATE_MASK) { | |
10621 | case PLANE_CTL_ROTATE_0: | |
10622 | plane_config->rotation = DRM_MODE_ROTATE_0; | |
10623 | break; | |
10624 | case PLANE_CTL_ROTATE_90: | |
10625 | plane_config->rotation = DRM_MODE_ROTATE_270; | |
10626 | break; | |
10627 | case PLANE_CTL_ROTATE_180: | |
10628 | plane_config->rotation = DRM_MODE_ROTATE_180; | |
10629 | break; | |
10630 | case PLANE_CTL_ROTATE_270: | |
10631 | plane_config->rotation = DRM_MODE_ROTATE_90; | |
10632 | break; | |
10633 | } | |
10634 | ||
10635 | if (INTEL_GEN(dev_priv) >= 10 && | |
10636 | val & PLANE_CTL_FLIP_HORIZONTAL) | |
10637 | plane_config->rotation |= DRM_MODE_REFLECT_X; | |
10638 | ||
61334ed2 VS |
10639 | /* 90/270 degree rotation would require extra work */ |
10640 | if (drm_rotation_90_or_270(plane_config->rotation)) | |
10641 | goto error; | |
10642 | ||
dc008bf0 | 10643 | base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000; |
bc8d7dff DL |
10644 | plane_config->base = base; |
10645 | ||
dc008bf0 | 10646 | offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); |
bc8d7dff | 10647 | |
dc008bf0 | 10648 | val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); |
e91c8a29 MN |
10649 | fb->height = ((val >> 16) & 0xffff) + 1; |
10650 | fb->width = ((val >> 0) & 0xffff) + 1; | |
bc8d7dff | 10651 | |
dc008bf0 | 10652 | val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); |
b3cf5c06 | 10653 | stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); |
bc8d7dff DL |
10654 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
10655 | ||
d88c4afd | 10656 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 10657 | |
f37b5c2b | 10658 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff | 10659 | |
cd49f818 WK |
10660 | drm_dbg_kms(&dev_priv->drm, |
10661 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
10662 | crtc->base.name, plane->base.name, fb->width, fb->height, | |
10663 | fb->format->cpp[0] * 8, base, fb->pitches[0], | |
10664 | plane_config->size); | |
bc8d7dff | 10665 | |
2d14030b | 10666 | plane_config->fb = intel_fb; |
bc8d7dff DL |
10667 | return; |
10668 | ||
10669 | error: | |
d1a3a036 | 10670 | kfree(intel_fb); |
bc8d7dff DL |
10671 | } |
10672 | ||
eac9c585 | 10673 | static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) |
2fa2fe9a | 10674 | { |
eac9c585 VS |
10675 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
10676 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
35dd95b4 | 10677 | u32 ctl, pos, size; |
2fa2fe9a | 10678 | |
35dd95b4 VS |
10679 | ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); |
10680 | if ((ctl & PF_ENABLE) == 0) | |
eac9c585 | 10681 | return; |
2fa2fe9a | 10682 | |
eac9c585 | 10683 | crtc_state->pch_pfit.enabled = true; |
35dd95b4 VS |
10684 | |
10685 | pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); | |
10686 | size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); | |
10687 | ||
10688 | ilk_get_pfit_pos_size(crtc_state, pos, size); | |
eac9c585 VS |
10689 | |
10690 | /* | |
10691 | * We currently do not free assignements of panel fitters on | |
10692 | * ivb/hsw (since we don't use the higher upscaling modes which | |
10693 | * differentiates them) so just WARN about this case for now. | |
10694 | */ | |
10695 | drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) && | |
35dd95b4 | 10696 | (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); |
79e53945 JB |
10697 | } |
10698 | ||
9eae5e27 LDM |
10699 | static bool ilk_get_pipe_config(struct intel_crtc *crtc, |
10700 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b DV |
10701 | { |
10702 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10703 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 10704 | enum intel_display_power_domain power_domain; |
0e6e0be4 | 10705 | intel_wakeref_t wakeref; |
ba3f4d0a | 10706 | u32 tmp; |
1729050e | 10707 | bool ret; |
0e8ffe1b | 10708 | |
1729050e | 10709 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
0e6e0be4 CW |
10710 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
10711 | if (!wakeref) | |
930e8c9e PZ |
10712 | return false; |
10713 | ||
e143a21c | 10714 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 10715 | pipe_config->shared_dpll = NULL; |
eccb140b | 10716 | |
1729050e | 10717 | ret = false; |
dc008bf0 | 10718 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); |
0e8ffe1b | 10719 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 10720 | goto out; |
0e8ffe1b | 10721 | |
42571aef VS |
10722 | switch (tmp & PIPECONF_BPC_MASK) { |
10723 | case PIPECONF_6BPC: | |
10724 | pipe_config->pipe_bpp = 18; | |
10725 | break; | |
10726 | case PIPECONF_8BPC: | |
10727 | pipe_config->pipe_bpp = 24; | |
10728 | break; | |
10729 | case PIPECONF_10BPC: | |
10730 | pipe_config->pipe_bpp = 30; | |
10731 | break; | |
10732 | case PIPECONF_12BPC: | |
10733 | pipe_config->pipe_bpp = 36; | |
10734 | break; | |
10735 | default: | |
10736 | break; | |
10737 | } | |
10738 | ||
b5a9fa09 DV |
10739 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
10740 | pipe_config->limited_color_range = true; | |
10741 | ||
d1844606 VS |
10742 | switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { |
10743 | case PIPECONF_OUTPUT_COLORSPACE_YUV601: | |
10744 | case PIPECONF_OUTPUT_COLORSPACE_YUV709: | |
10745 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; | |
10746 | break; | |
10747 | default: | |
10748 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | |
10749 | break; | |
10750 | } | |
10751 | ||
9d5441de VS |
10752 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >> |
10753 | PIPECONF_GAMMA_MODE_SHIFT; | |
10754 | ||
dc008bf0 JN |
10755 | pipe_config->csc_mode = intel_de_read(dev_priv, |
10756 | PIPE_CSC_MODE(crtc->pipe)); | |
a1f1e61b | 10757 | |
5f29ab23 | 10758 | i9xx_get_pipe_color_config(pipe_config); |
3633e511 | 10759 | intel_color_get_config(pipe_config); |
5f29ab23 | 10760 | |
dc008bf0 | 10761 | if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 10762 | struct intel_shared_dpll *pll; |
8106ddbd | 10763 | enum intel_dpll_id pll_id; |
66e985c0 | 10764 | |
88adfff1 DV |
10765 | pipe_config->has_pch_encoder = true; |
10766 | ||
dc008bf0 | 10767 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe)); |
627eb5a3 DV |
10768 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
10769 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 | 10770 | |
9eae5e27 | 10771 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
6c49f241 | 10772 | |
2d1fe073 | 10773 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
10774 | /* |
10775 | * The pipe->pch transcoder and pch transcoder->pll | |
10776 | * mapping is fixed. | |
10777 | */ | |
8106ddbd | 10778 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 | 10779 | } else { |
dc008bf0 | 10780 | tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); |
c0d43d62 | 10781 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
8106ddbd | 10782 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 10783 | else |
8106ddbd | 10784 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 10785 | } |
66e985c0 | 10786 | |
8106ddbd ACO |
10787 | pipe_config->shared_dpll = |
10788 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
10789 | pll = pipe_config->shared_dpll; | |
66e985c0 | 10790 | |
e57291c2 PB |
10791 | drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll, |
10792 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
10793 | |
10794 | tmp = pipe_config->dpll_hw_state.dpll; | |
10795 | pipe_config->pixel_multiplier = | |
10796 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
10797 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 | 10798 | |
9eae5e27 | 10799 | ilk_pch_clock_get(crtc, pipe_config); |
6c49f241 DV |
10800 | } else { |
10801 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10802 | } |
10803 | ||
1bd1bd80 | 10804 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 10805 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10806 | |
eac9c585 | 10807 | ilk_get_pfit_config(pipe_config); |
2fa2fe9a | 10808 | |
1729050e ID |
10809 | ret = true; |
10810 | ||
10811 | out: | |
0e6e0be4 | 10812 | intel_display_power_put(dev_priv, power_domain, wakeref); |
1729050e ID |
10813 | |
10814 | return ret; | |
0e8ffe1b | 10815 | } |
1e98f88c LDM |
10816 | |
10817 | static int hsw_crtc_compute_clock(struct intel_crtc *crtc, | |
10818 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10819 | { |
70a057b7 | 10820 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
5a0b385e | 10821 | struct intel_atomic_state *state = |
2225f3c6 | 10822 | to_intel_atomic_state(crtc_state->uapi.state); |
5a0b385e | 10823 | |
70a057b7 | 10824 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || |
2dd24a9c | 10825 | INTEL_GEN(dev_priv) >= 11) { |
44a126ba | 10826 | struct intel_encoder *encoder = |
5a0b385e | 10827 | intel_get_crtc_new_encoder(state, crtc_state); |
44a126ba | 10828 | |
866955fa | 10829 | if (!intel_reserve_shared_dplls(state, crtc, encoder)) { |
cd49f818 WK |
10830 | drm_dbg_kms(&dev_priv->drm, |
10831 | "failed to find PLL for pipe %c\n", | |
10832 | pipe_name(crtc->pipe)); | |
af3997b5 | 10833 | return -EINVAL; |
44a126ba | 10834 | } |
af3997b5 | 10835 | } |
716c2e55 | 10836 | |
c8f7a0db | 10837 | return 0; |
79e53945 JB |
10838 | } |
10839 | ||
8e619820 LDM |
10840 | static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10841 | struct intel_crtc_state *pipe_config) | |
8b0f7e06 KM |
10842 | { |
10843 | enum intel_dpll_id id; | |
10844 | u32 temp; | |
10845 | ||
dc008bf0 | 10846 | temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); |
dfbd4508 | 10847 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); |
8b0f7e06 | 10848 | |
e57291c2 | 10849 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) |
8b0f7e06 KM |
10850 | return; |
10851 | ||
10852 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
10853 | } | |
10854 | ||
95be3484 LDM |
10855 | static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10856 | struct intel_crtc_state *pipe_config) | |
970888e7 | 10857 | { |
d8fe2ab6 | 10858 | enum phy phy = intel_port_to_phy(dev_priv, port); |
eea72c4c | 10859 | enum icl_port_dpll_id port_dpll_id; |
970888e7 PZ |
10860 | enum intel_dpll_id id; |
10861 | u32 temp; | |
10862 | ||
d8fe2ab6 | 10863 | if (intel_phy_is_combo(dev_priv, phy)) { |
cd803bb4 MR |
10864 | u32 mask, shift; |
10865 | ||
10866 | if (IS_ROCKETLAKE(dev_priv)) { | |
10867 | mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
10868 | shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); | |
10869 | } else { | |
10870 | mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); | |
10871 | shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); | |
10872 | } | |
10873 | ||
10874 | temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; | |
10875 | id = temp >> shift; | |
eea72c4c | 10876 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
d8fe2ab6 | 10877 | } else if (intel_phy_is_tc(dev_priv, phy)) { |
dc008bf0 | 10878 | u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; |
39a5883f ID |
10879 | |
10880 | if (clk_sel == DDI_CLK_SEL_MG) { | |
10881 | id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, | |
10882 | port)); | |
eea72c4c | 10883 | port_dpll_id = ICL_PORT_DPLL_MG_PHY; |
39a5883f | 10884 | } else { |
e57291c2 PB |
10885 | drm_WARN_ON(&dev_priv->drm, |
10886 | clk_sel < DDI_CLK_SEL_TBT_162); | |
39a5883f | 10887 | id = DPLL_ID_ICL_TBTPLL; |
eea72c4c | 10888 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
39a5883f | 10889 | } |
8ea59e67 | 10890 | } else { |
e57291c2 | 10891 | drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); |
970888e7 PZ |
10892 | return; |
10893 | } | |
10894 | ||
eea72c4c ID |
10895 | pipe_config->icl_port_dplls[port_dpll_id].pll = |
10896 | intel_get_shared_dpll_by_id(dev_priv, id); | |
10897 | ||
10898 | icl_set_active_port_dpll(pipe_config, port_dpll_id); | |
970888e7 PZ |
10899 | } |
10900 | ||
3760b59c S |
10901 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10902 | enum port port, | |
10903 | struct intel_crtc_state *pipe_config) | |
10904 | { | |
8106ddbd ACO |
10905 | enum intel_dpll_id id; |
10906 | ||
3760b59c S |
10907 | switch (port) { |
10908 | case PORT_A: | |
08250c4b | 10909 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10910 | break; |
10911 | case PORT_B: | |
08250c4b | 10912 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10913 | break; |
10914 | case PORT_C: | |
08250c4b | 10915 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10916 | break; |
10917 | default: | |
cd49f818 | 10918 | drm_err(&dev_priv->drm, "Incorrect port type\n"); |
8106ddbd | 10919 | return; |
3760b59c | 10920 | } |
8106ddbd ACO |
10921 | |
10922 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10923 | } |
10924 | ||
f6df4d46 LDM |
10925 | static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10926 | struct intel_crtc_state *pipe_config) | |
96b7dfb7 | 10927 | { |
8106ddbd | 10928 | enum intel_dpll_id id; |
a3c988ea | 10929 | u32 temp; |
96b7dfb7 | 10930 | |
dc008bf0 | 10931 | temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
c856052a | 10932 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10933 | |
e57291c2 | 10934 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10935 | return; |
8106ddbd ACO |
10936 | |
10937 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10938 | } |
10939 | ||
1e98f88c LDM |
10940 | static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, |
10941 | struct intel_crtc_state *pipe_config) | |
7d2c8175 | 10942 | { |
8106ddbd | 10943 | enum intel_dpll_id id; |
dc008bf0 | 10944 | u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)); |
8106ddbd | 10945 | |
c856052a | 10946 | switch (ddi_pll_sel) { |
7d2c8175 | 10947 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10948 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10949 | break; |
10950 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10951 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10952 | break; |
00490c22 | 10953 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10954 | id = DPLL_ID_SPLL; |
79bd23da | 10955 | break; |
9d16da65 ACO |
10956 | case PORT_CLK_SEL_LCPLL_810: |
10957 | id = DPLL_ID_LCPLL_810; | |
10958 | break; | |
10959 | case PORT_CLK_SEL_LCPLL_1350: | |
10960 | id = DPLL_ID_LCPLL_1350; | |
10961 | break; | |
10962 | case PORT_CLK_SEL_LCPLL_2700: | |
10963 | id = DPLL_ID_LCPLL_2700; | |
10964 | break; | |
8106ddbd | 10965 | default: |
c856052a | 10966 | MISSING_CASE(ddi_pll_sel); |
df561f66 | 10967 | fallthrough; |
8106ddbd | 10968 | case PORT_CLK_SEL_NONE: |
8106ddbd | 10969 | return; |
7d2c8175 | 10970 | } |
8106ddbd ACO |
10971 | |
10972 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10973 | } |
10974 | ||
cf30429e JN |
10975 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10976 | struct intel_crtc_state *pipe_config, | |
513a4c55 CW |
10977 | u64 *power_domain_mask, |
10978 | intel_wakeref_t *wakerefs) | |
cf30429e JN |
10979 | { |
10980 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10981 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e | 10982 | enum intel_display_power_domain power_domain; |
617458cd | 10983 | unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP); |
0716931a JN |
10984 | unsigned long enabled_panel_transcoders = 0; |
10985 | enum transcoder panel_transcoder; | |
513a4c55 | 10986 | intel_wakeref_t wf; |
cf30429e | 10987 | u32 tmp; |
0716931a | 10988 | |
2dd24a9c | 10989 | if (INTEL_GEN(dev_priv) >= 11) |
0716931a JN |
10990 | panel_transcoder_mask |= |
10991 | BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); | |
cf30429e | 10992 | |
d9a7bc67 ID |
10993 | /* |
10994 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
0716931a | 10995 | * and DSI transcoders handled below. |
d9a7bc67 | 10996 | */ |
cf30429e JN |
10997 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10998 | ||
10999 | /* | |
11000 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
11001 | * consistency and less surprising code; it's in always on power). | |
11002 | */ | |
617458cd AS |
11003 | for_each_cpu_transcoder_masked(dev_priv, panel_transcoder, |
11004 | panel_transcoder_mask) { | |
dc0c0bfe | 11005 | bool force_thru = false; |
0716931a | 11006 | enum pipe trans_pipe; |
2ca711ca | 11007 | |
dc008bf0 JN |
11008 | tmp = intel_de_read(dev_priv, |
11009 | TRANS_DDI_FUNC_CTL(panel_transcoder)); | |
0716931a JN |
11010 | if (!(tmp & TRANS_DDI_FUNC_ENABLE)) |
11011 | continue; | |
2ca711ca | 11012 | |
0716931a JN |
11013 | /* |
11014 | * Log all enabled ones, only use the first one. | |
11015 | * | |
11016 | * FIXME: This won't work for two separate DSI displays. | |
11017 | */ | |
11018 | enabled_panel_transcoders |= BIT(panel_transcoder); | |
11019 | if (enabled_panel_transcoders != BIT(panel_transcoder)) | |
11020 | continue; | |
2ca711ca | 11021 | |
cf30429e JN |
11022 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
11023 | default: | |
e57291c2 PB |
11024 | drm_WARN(dev, 1, |
11025 | "unknown pipe linked to transcoder %s\n", | |
11026 | transcoder_name(panel_transcoder)); | |
df561f66 | 11027 | fallthrough; |
cf30429e | 11028 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
dc0c0bfe | 11029 | force_thru = true; |
df561f66 | 11030 | fallthrough; |
cf30429e | 11031 | case TRANS_DDI_EDP_INPUT_A_ON: |
2ca711ca | 11032 | trans_pipe = PIPE_A; |
cf30429e JN |
11033 | break; |
11034 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
2ca711ca | 11035 | trans_pipe = PIPE_B; |
cf30429e JN |
11036 | break; |
11037 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
2ca711ca | 11038 | trans_pipe = PIPE_C; |
cf30429e | 11039 | break; |
9c569784 JN |
11040 | case TRANS_DDI_EDP_INPUT_D_ONOFF: |
11041 | trans_pipe = PIPE_D; | |
11042 | break; | |
cf30429e JN |
11043 | } |
11044 | ||
dc0c0bfe | 11045 | if (trans_pipe == crtc->pipe) { |
0716931a | 11046 | pipe_config->cpu_transcoder = panel_transcoder; |
dc0c0bfe VS |
11047 | pipe_config->pch_pfit.force_thru = force_thru; |
11048 | } | |
cf30429e JN |
11049 | } |
11050 | ||
0716931a JN |
11051 | /* |
11052 | * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1 | |
11053 | */ | |
e57291c2 PB |
11054 | drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && |
11055 | enabled_panel_transcoders != BIT(TRANSCODER_EDP)); | |
0716931a | 11056 | |
cf30429e | 11057 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
e57291c2 | 11058 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11059 | |
11060 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11061 | if (!wf) | |
cf30429e | 11062 | return false; |
04161d64 | 11063 | |
513a4c55 | 11064 | wakerefs[power_domain] = wf; |
d8fc70b7 | 11065 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e | 11066 | |
dc008bf0 | 11067 | tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); |
cf30429e JN |
11068 | |
11069 | return tmp & PIPECONF_ENABLE; | |
11070 | } | |
11071 | ||
4d1de975 JN |
11072 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
11073 | struct intel_crtc_state *pipe_config, | |
513a4c55 CW |
11074 | u64 *power_domain_mask, |
11075 | intel_wakeref_t *wakerefs) | |
4d1de975 JN |
11076 | { |
11077 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11078 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 11079 | enum intel_display_power_domain power_domain; |
4d1de975 | 11080 | enum transcoder cpu_transcoder; |
513a4c55 CW |
11081 | intel_wakeref_t wf; |
11082 | enum port port; | |
4d1de975 JN |
11083 | u32 tmp; |
11084 | ||
4d1de975 JN |
11085 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
11086 | if (port == PORT_A) | |
11087 | cpu_transcoder = TRANSCODER_DSI_A; | |
11088 | else | |
11089 | cpu_transcoder = TRANSCODER_DSI_C; | |
11090 | ||
11091 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
e57291c2 | 11092 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11093 | |
11094 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11095 | if (!wf) | |
4d1de975 | 11096 | continue; |
04161d64 | 11097 | |
513a4c55 | 11098 | wakerefs[power_domain] = wf; |
d8fc70b7 | 11099 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 11100 | |
db18b6a6 ID |
11101 | /* |
11102 | * The PLL needs to be enabled with a valid divider | |
11103 | * configuration, otherwise accessing DSI registers will hang | |
11104 | * the machine. See BSpec North Display Engine | |
11105 | * registers/MIPI[BXT]. We can break out here early, since we | |
11106 | * need the same DSI PLL to be enabled for both DSI ports. | |
11107 | */ | |
e518634b | 11108 | if (!bxt_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
11109 | break; |
11110 | ||
4d1de975 | 11111 | /* XXX: this works for video mode only */ |
dc008bf0 | 11112 | tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); |
4d1de975 JN |
11113 | if (!(tmp & DPI_ENABLE)) |
11114 | continue; | |
11115 | ||
dc008bf0 | 11116 | tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); |
4d1de975 JN |
11117 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) |
11118 | continue; | |
11119 | ||
11120 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
11121 | break; |
11122 | } | |
11123 | ||
d7edc4e5 | 11124 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
11125 | } |
11126 | ||
1e98f88c LDM |
11127 | static void hsw_get_ddi_port_state(struct intel_crtc *crtc, |
11128 | struct intel_crtc_state *pipe_config) | |
26804afd | 11129 | { |
6315b5d3 | 11130 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6d73af27 | 11131 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
d452c5b6 | 11132 | struct intel_shared_dpll *pll; |
26804afd | 11133 | enum port port; |
ba3f4d0a | 11134 | u32 tmp; |
26804afd | 11135 | |
6d73af27 VK |
11136 | if (transcoder_is_dsi(cpu_transcoder)) { |
11137 | port = (cpu_transcoder == TRANSCODER_DSI_A) ? | |
11138 | PORT_A : PORT_B; | |
11139 | } else { | |
dc008bf0 JN |
11140 | tmp = intel_de_read(dev_priv, |
11141 | TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
6d73af27 VK |
11142 | if (INTEL_GEN(dev_priv) >= 12) |
11143 | port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); | |
11144 | else | |
11145 | port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); | |
11146 | } | |
26804afd | 11147 | |
2dd24a9c | 11148 | if (INTEL_GEN(dev_priv) >= 11) |
95be3484 | 11149 | icl_get_ddi_pll(dev_priv, port, pipe_config); |
970888e7 | 11150 | else if (IS_CANNONLAKE(dev_priv)) |
8e619820 | 11151 | cnl_get_ddi_pll(dev_priv, port, pipe_config); |
8b0f7e06 | 11152 | else if (IS_GEN9_BC(dev_priv)) |
f6df4d46 | 11153 | skl_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 11154 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 11155 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 | 11156 | else |
1e98f88c | 11157 | hsw_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 11158 | |
8106ddbd ACO |
11159 | pll = pipe_config->shared_dpll; |
11160 | if (pll) { | |
e57291c2 PB |
11161 | drm_WARN_ON(&dev_priv->drm, |
11162 | !pll->info->funcs->get_hw_state(dev_priv, pll, | |
ee1398ba | 11163 | &pipe_config->dpll_hw_state)); |
d452c5b6 DV |
11164 | } |
11165 | ||
26804afd DV |
11166 | /* |
11167 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
11168 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
11169 | * the PCH transcoder is on. | |
11170 | */ | |
6315b5d3 | 11171 | if (INTEL_GEN(dev_priv) < 9 && |
dc008bf0 | 11172 | (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
11173 | pipe_config->has_pch_encoder = true; |
11174 | ||
dc008bf0 | 11175 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); |
26804afd DV |
11176 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
11177 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
11178 | ||
9eae5e27 | 11179 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
26804afd DV |
11180 | } |
11181 | } | |
11182 | ||
1e98f88c LDM |
11183 | static bool hsw_get_pipe_config(struct intel_crtc *crtc, |
11184 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11185 | { |
6315b5d3 | 11186 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
513a4c55 | 11187 | intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; |
1729050e | 11188 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 11189 | u64 power_domain_mask; |
cf30429e | 11190 | bool active; |
6dcde047 | 11191 | u32 tmp; |
0e8ffe1b | 11192 | |
ba5f1ae9 MN |
11193 | pipe_config->master_transcoder = INVALID_TRANSCODER; |
11194 | ||
1729050e | 11195 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
513a4c55 CW |
11196 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
11197 | if (!wf) | |
b5482bd0 | 11198 | return false; |
513a4c55 CW |
11199 | |
11200 | wakerefs[power_domain] = wf; | |
d8fc70b7 | 11201 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 11202 | |
8106ddbd | 11203 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 11204 | |
513a4c55 CW |
11205 | active = hsw_get_transcoder_state(crtc, pipe_config, |
11206 | &power_domain_mask, wakerefs); | |
eccb140b | 11207 | |
cc3f90f0 | 11208 | if (IS_GEN9_LP(dev_priv) && |
513a4c55 CW |
11209 | bxt_get_dsi_transcoder_state(crtc, pipe_config, |
11210 | &power_domain_mask, wakerefs)) { | |
e57291c2 | 11211 | drm_WARN_ON(&dev_priv->drm, active); |
d7edc4e5 | 11212 | active = true; |
4d1de975 JN |
11213 | } |
11214 | ||
cf30429e | 11215 | if (!active) |
1729050e | 11216 | goto out; |
0e8ffe1b | 11217 | |
2eae5d6b | 11218 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || |
2dd24a9c | 11219 | INTEL_GEN(dev_priv) >= 11) { |
1e98f88c | 11220 | hsw_get_ddi_port_state(crtc, pipe_config); |
4d1de975 JN |
11221 | intel_get_pipe_timings(crtc, pipe_config); |
11222 | } | |
627eb5a3 | 11223 | |
bc58be60 | 11224 | intel_get_pipe_src_size(crtc, pipe_config); |
b10d1173 | 11225 | |
ac0f01ce | 11226 | if (IS_HASWELL(dev_priv)) { |
dc008bf0 JN |
11227 | u32 tmp = intel_de_read(dev_priv, |
11228 | PIPECONF(pipe_config->cpu_transcoder)); | |
ac0f01ce VS |
11229 | |
11230 | if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) | |
11231 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; | |
11232 | else | |
11233 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | |
11234 | } else { | |
b10d1173 VS |
11235 | pipe_config->output_format = |
11236 | bdw_get_pipemisc_output_format(crtc); | |
11237 | ||
11238 | /* | |
11239 | * Currently there is no interface defined to | |
11240 | * check user preference between RGB/YCBCR444 | |
11241 | * or YCBCR420. So the only possible case for | |
11242 | * YCBCR444 usage is driving YCBCR420 output | |
11243 | * with LSPCON, when pipe is configured for | |
11244 | * YCBCR444 output and LSPCON takes care of | |
11245 | * downsampling it. | |
11246 | */ | |
11247 | pipe_config->lspcon_downsampling = | |
11248 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444; | |
11249 | } | |
1bd1bd80 | 11250 | |
dc008bf0 JN |
11251 | pipe_config->gamma_mode = intel_de_read(dev_priv, |
11252 | GAMMA_MODE(crtc->pipe)); | |
05dc698c | 11253 | |
dc008bf0 JN |
11254 | pipe_config->csc_mode = intel_de_read(dev_priv, |
11255 | PIPE_CSC_MODE(crtc->pipe)); | |
a1f1e61b | 11256 | |
5f29ab23 | 11257 | if (INTEL_GEN(dev_priv) >= 9) { |
6dcde047 | 11258 | tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); |
5f29ab23 VS |
11259 | |
11260 | if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) | |
11261 | pipe_config->gamma_enable = true; | |
8271b2ef VS |
11262 | |
11263 | if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) | |
11264 | pipe_config->csc_enable = true; | |
5f29ab23 VS |
11265 | } else { |
11266 | i9xx_get_pipe_color_config(pipe_config); | |
11267 | } | |
11268 | ||
3633e511 SS |
11269 | intel_color_get_config(pipe_config); |
11270 | ||
6dcde047 VS |
11271 | tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); |
11272 | pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); | |
11273 | if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
11274 | pipe_config->ips_linetime = | |
11275 | REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); | |
11276 | ||
1729050e | 11277 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
e57291c2 | 11278 | drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain)); |
513a4c55 CW |
11279 | |
11280 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
11281 | if (wf) { | |
11282 | wakerefs[power_domain] = wf; | |
d8fc70b7 | 11283 | power_domain_mask |= BIT_ULL(power_domain); |
04161d64 | 11284 | |
6315b5d3 | 11285 | if (INTEL_GEN(dev_priv) >= 9) |
eac9c585 | 11286 | skl_get_pfit_config(pipe_config); |
ff6d9f55 | 11287 | else |
eac9c585 | 11288 | ilk_get_pfit_config(pipe_config); |
bd2e244f | 11289 | } |
88adfff1 | 11290 | |
24f28450 ML |
11291 | if (hsw_crtc_supports_ips(crtc)) { |
11292 | if (IS_HASWELL(dev_priv)) | |
dc008bf0 JN |
11293 | pipe_config->ips_enabled = intel_de_read(dev_priv, |
11294 | IPS_CTL) & IPS_ENABLE; | |
24f28450 ML |
11295 | else { |
11296 | /* | |
11297 | * We cannot readout IPS state on broadwell, set to | |
11298 | * true so we can set it to a defined state on first | |
11299 | * commit. | |
11300 | */ | |
11301 | pipe_config->ips_enabled = true; | |
11302 | } | |
11303 | } | |
11304 | ||
4d1de975 JN |
11305 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
11306 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 | 11307 | pipe_config->pixel_multiplier = |
dc008bf0 JN |
11308 | intel_de_read(dev_priv, |
11309 | PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
ebb69c95 CT |
11310 | } else { |
11311 | pipe_config->pixel_multiplier = 1; | |
11312 | } | |
6c49f241 | 11313 | |
1729050e ID |
11314 | out: |
11315 | for_each_power_domain(power_domain, power_domain_mask) | |
513a4c55 CW |
11316 | intel_display_power_put(dev_priv, |
11317 | power_domain, wakerefs[power_domain]); | |
1729050e | 11318 | |
cf30429e | 11319 | return active; |
0e8ffe1b DV |
11320 | } |
11321 | ||
cd5dcbf1 | 11322 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
11323 | { |
11324 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 11325 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 11326 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
1cecc830 VS |
11327 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11328 | u32 base; | |
11329 | ||
d53db442 | 11330 | if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) |
c6790dc2 | 11331 | base = sg_dma_address(obj->mm.pages->sgl); |
1cecc830 VS |
11332 | else |
11333 | base = intel_plane_ggtt_offset(plane_state); | |
11334 | ||
30a027dc | 11335 | return base + plane_state->color_plane[0].offset; |
1cecc830 VS |
11336 | } |
11337 | ||
ed270223 VS |
11338 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
11339 | { | |
f90a85e7 ML |
11340 | int x = plane_state->uapi.dst.x1; |
11341 | int y = plane_state->uapi.dst.y1; | |
ed270223 VS |
11342 | u32 pos = 0; |
11343 | ||
11344 | if (x < 0) { | |
11345 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
11346 | x = -x; | |
11347 | } | |
11348 | pos |= x << CURSOR_X_SHIFT; | |
11349 | ||
11350 | if (y < 0) { | |
11351 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
11352 | y = -y; | |
11353 | } | |
11354 | pos |= y << CURSOR_Y_SHIFT; | |
11355 | ||
11356 | return pos; | |
11357 | } | |
11358 | ||
3637ecf0 VS |
11359 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
11360 | { | |
11361 | const struct drm_mode_config *config = | |
f90a85e7 ML |
11362 | &plane_state->uapi.plane->dev->mode_config; |
11363 | int width = drm_rect_width(&plane_state->uapi.dst); | |
11364 | int height = drm_rect_height(&plane_state->uapi.dst); | |
3637ecf0 VS |
11365 | |
11366 | return width > 0 && width <= config->cursor_width && | |
11367 | height > 0 && height <= config->cursor_height; | |
11368 | } | |
11369 | ||
fce8d235 | 11370 | static int intel_cursor_check_surface(struct intel_plane_state *plane_state) |
659056f2 | 11371 | { |
30a027dc | 11372 | struct drm_i915_private *dev_priv = |
f90a85e7 | 11373 | to_i915(plane_state->uapi.plane->dev); |
7b3cb17a | 11374 | unsigned int rotation = plane_state->hw.rotation; |
1e7b4fd8 VS |
11375 | int src_x, src_y; |
11376 | u32 offset; | |
fc3fed5d | 11377 | int ret; |
fce8d235 | 11378 | |
54d4d719 | 11379 | ret = intel_plane_compute_gtt(plane_state); |
fc3fed5d VS |
11380 | if (ret) |
11381 | return ret; | |
11382 | ||
f90a85e7 | 11383 | if (!plane_state->uapi.visible) |
54d4d719 VS |
11384 | return 0; |
11385 | ||
f90a85e7 ML |
11386 | src_x = plane_state->uapi.src.x1 >> 16; |
11387 | src_y = plane_state->uapi.src.y1 >> 16; | |
fce8d235 VS |
11388 | |
11389 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
11390 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, | |
11391 | plane_state, 0); | |
11392 | ||
11393 | if (src_x != 0 || src_y != 0) { | |
cd49f818 WK |
11394 | drm_dbg_kms(&dev_priv->drm, |
11395 | "Arbitrary cursor panning not supported\n"); | |
fce8d235 VS |
11396 | return -EINVAL; |
11397 | } | |
11398 | ||
30a027dc VS |
11399 | /* |
11400 | * Put the final coordinates back so that the src | |
11401 | * coordinate checks will see the right values. | |
11402 | */ | |
f90a85e7 | 11403 | drm_rect_translate_to(&plane_state->uapi.src, |
30a027dc VS |
11404 | src_x << 16, src_y << 16); |
11405 | ||
11406 | /* ILK+ do this automagically in hardware */ | |
11407 | if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { | |
7b3cb17a | 11408 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
f90a85e7 ML |
11409 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
11410 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
30a027dc VS |
11411 | |
11412 | offset += (src_h * src_w - 1) * fb->format->cpp[0]; | |
11413 | } | |
11414 | ||
fce8d235 | 11415 | plane_state->color_plane[0].offset = offset; |
30a027dc VS |
11416 | plane_state->color_plane[0].x = src_x; |
11417 | plane_state->color_plane[0].y = src_y; | |
fce8d235 VS |
11418 | |
11419 | return 0; | |
11420 | } | |
11421 | ||
11422 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, | |
11423 | struct intel_plane_state *plane_state) | |
11424 | { | |
7b3cb17a | 11425 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
cd49f818 | 11426 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); |
659056f2 VS |
11427 | int ret; |
11428 | ||
4e0b83a5 | 11429 | if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
cd49f818 | 11430 | drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); |
4e0b83a5 VS |
11431 | return -EINVAL; |
11432 | } | |
11433 | ||
f90a85e7 | 11434 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
2225f3c6 | 11435 | &crtc_state->uapi, |
a01cb8ba VS |
11436 | DRM_PLANE_HELPER_NO_SCALING, |
11437 | DRM_PLANE_HELPER_NO_SCALING, | |
11438 | true, true); | |
659056f2 VS |
11439 | if (ret) |
11440 | return ret; | |
11441 | ||
3a612765 | 11442 | /* Use the unclipped src/dst rectangles, which we program to hw */ |
f90a85e7 ML |
11443 | plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi); |
11444 | plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi); | |
3a612765 | 11445 | |
54d4d719 VS |
11446 | ret = intel_cursor_check_surface(plane_state); |
11447 | if (ret) | |
11448 | return ret; | |
11449 | ||
f90a85e7 | 11450 | if (!plane_state->uapi.visible) |
659056f2 VS |
11451 | return 0; |
11452 | ||
4e0b83a5 VS |
11453 | ret = intel_plane_check_src_coordinates(plane_state); |
11454 | if (ret) | |
11455 | return ret; | |
659056f2 VS |
11456 | |
11457 | return 0; | |
11458 | } | |
11459 | ||
ddd5713d VS |
11460 | static unsigned int |
11461 | i845_cursor_max_stride(struct intel_plane *plane, | |
11462 | u32 pixel_format, u64 modifier, | |
11463 | unsigned int rotation) | |
11464 | { | |
11465 | return 2048; | |
11466 | } | |
11467 | ||
7eb31a0b VS |
11468 | static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
11469 | { | |
5f29ab23 VS |
11470 | u32 cntl = 0; |
11471 | ||
11472 | if (crtc_state->gamma_enable) | |
11473 | cntl |= CURSOR_GAMMA_ENABLE; | |
11474 | ||
11475 | return cntl; | |
7eb31a0b VS |
11476 | } |
11477 | ||
292889e1 VS |
11478 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
11479 | const struct intel_plane_state *plane_state) | |
11480 | { | |
292889e1 | 11481 | return CURSOR_ENABLE | |
292889e1 | 11482 | CURSOR_FORMAT_ARGB | |
df79cf44 | 11483 | CURSOR_STRIDE(plane_state->color_plane[0].stride); |
292889e1 VS |
11484 | } |
11485 | ||
659056f2 VS |
11486 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
11487 | { | |
f90a85e7 | 11488 | int width = drm_rect_width(&plane_state->uapi.dst); |
659056f2 VS |
11489 | |
11490 | /* | |
11491 | * 845g/865g are only limited by the width of their cursors, | |
11492 | * the height is arbitrary up to the precision of the register. | |
11493 | */ | |
3637ecf0 | 11494 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
11495 | } |
11496 | ||
eb0f5044 | 11497 | static int i845_check_cursor(struct intel_crtc_state *crtc_state, |
659056f2 VS |
11498 | struct intel_plane_state *plane_state) |
11499 | { | |
7b3cb17a | 11500 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
cd49f818 | 11501 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); |
659056f2 VS |
11502 | int ret; |
11503 | ||
11504 | ret = intel_check_cursor(crtc_state, plane_state); | |
11505 | if (ret) | |
11506 | return ret; | |
11507 | ||
11508 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 11509 | if (!fb) |
659056f2 VS |
11510 | return 0; |
11511 | ||
11512 | /* Check for which cursor types we support */ | |
11513 | if (!i845_cursor_size_ok(plane_state)) { | |
cd49f818 WK |
11514 | drm_dbg_kms(&i915->drm, |
11515 | "Cursor dimension %dx%d not supported\n", | |
11516 | drm_rect_width(&plane_state->uapi.dst), | |
11517 | drm_rect_height(&plane_state->uapi.dst)); | |
659056f2 VS |
11518 | return -EINVAL; |
11519 | } | |
11520 | ||
e57291c2 PB |
11521 | drm_WARN_ON(&i915->drm, plane_state->uapi.visible && |
11522 | plane_state->color_plane[0].stride != fb->pitches[0]); | |
df79cf44 | 11523 | |
1e1bb871 | 11524 | switch (fb->pitches[0]) { |
292889e1 VS |
11525 | case 256: |
11526 | case 512: | |
11527 | case 1024: | |
11528 | case 2048: | |
11529 | break; | |
1e1bb871 | 11530 | default: |
cd49f818 WK |
11531 | drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", |
11532 | fb->pitches[0]); | |
1e1bb871 | 11533 | return -EINVAL; |
292889e1 VS |
11534 | } |
11535 | ||
659056f2 VS |
11536 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
11537 | ||
11538 | return 0; | |
292889e1 VS |
11539 | } |
11540 | ||
b2d03b0d VS |
11541 | static void i845_update_cursor(struct intel_plane *plane, |
11542 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 11543 | const struct intel_plane_state *plane_state) |
560b85bb | 11544 | { |
cd5dcbf1 | 11545 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
11546 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
11547 | unsigned long irqflags; | |
560b85bb | 11548 | |
f90a85e7 ML |
11549 | if (plane_state && plane_state->uapi.visible) { |
11550 | unsigned int width = drm_rect_width(&plane_state->uapi.dst); | |
11551 | unsigned int height = drm_rect_height(&plane_state->uapi.dst); | |
dc41c154 | 11552 | |
7eb31a0b VS |
11553 | cntl = plane_state->ctl | |
11554 | i845_cursor_ctl_crtc(crtc_state); | |
11555 | ||
dc41c154 | 11556 | size = (height << 12) | width; |
560b85bb | 11557 | |
b2d03b0d VS |
11558 | base = intel_cursor_base(plane_state); |
11559 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 11560 | } |
560b85bb | 11561 | |
b2d03b0d | 11562 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 11563 | |
e11ffddb VS |
11564 | /* On these chipsets we can only modify the base/size/stride |
11565 | * whilst the cursor is disabled. | |
11566 | */ | |
11567 | if (plane->cursor.base != base || | |
11568 | plane->cursor.size != size || | |
11569 | plane->cursor.cntl != cntl) { | |
dc008bf0 JN |
11570 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); |
11571 | intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); | |
11572 | intel_de_write_fw(dev_priv, CURSIZE, size); | |
11573 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); | |
11574 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); | |
75343a44 | 11575 | |
e11ffddb VS |
11576 | plane->cursor.base = base; |
11577 | plane->cursor.size = size; | |
11578 | plane->cursor.cntl = cntl; | |
11579 | } else { | |
dc008bf0 | 11580 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); |
560b85bb | 11581 | } |
e11ffddb | 11582 | |
b2d03b0d VS |
11583 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
11584 | } | |
11585 | ||
11586 | static void i845_disable_cursor(struct intel_plane *plane, | |
0dd14be3 | 11587 | const struct intel_crtc_state *crtc_state) |
b2d03b0d | 11588 | { |
0dd14be3 | 11589 | i845_update_cursor(plane, crtc_state, NULL); |
560b85bb CW |
11590 | } |
11591 | ||
eade6c89 VS |
11592 | static bool i845_cursor_get_hw_state(struct intel_plane *plane, |
11593 | enum pipe *pipe) | |
51f5a096 VS |
11594 | { |
11595 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
11596 | enum intel_display_power_domain power_domain; | |
0e6e0be4 | 11597 | intel_wakeref_t wakeref; |
51f5a096 VS |
11598 | bool ret; |
11599 | ||
11600 | power_domain = POWER_DOMAIN_PIPE(PIPE_A); | |
0e6e0be4 CW |
11601 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
11602 | if (!wakeref) | |
51f5a096 VS |
11603 | return false; |
11604 | ||
dc008bf0 | 11605 | ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
51f5a096 | 11606 | |
eade6c89 VS |
11607 | *pipe = PIPE_A; |
11608 | ||
0e6e0be4 | 11609 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
11610 | |
11611 | return ret; | |
11612 | } | |
11613 | ||
ddd5713d VS |
11614 | static unsigned int |
11615 | i9xx_cursor_max_stride(struct intel_plane *plane, | |
11616 | u32 pixel_format, u64 modifier, | |
11617 | unsigned int rotation) | |
11618 | { | |
11619 | return plane->base.dev->mode_config.cursor_width * 4; | |
11620 | } | |
11621 | ||
7eb31a0b | 11622 | static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
292889e1 | 11623 | { |
2225f3c6 | 11624 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7eb31a0b | 11625 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
c894d63c | 11626 | u32 cntl = 0; |
292889e1 | 11627 | |
7eb31a0b VS |
11628 | if (INTEL_GEN(dev_priv) >= 11) |
11629 | return cntl; | |
e876b78c | 11630 | |
5f29ab23 VS |
11631 | if (crtc_state->gamma_enable) |
11632 | cntl = MCURSOR_GAMMA_ENABLE; | |
292889e1 | 11633 | |
8271b2ef | 11634 | if (crtc_state->csc_enable) |
7eb31a0b | 11635 | cntl |= MCURSOR_PIPE_CSC_ENABLE; |
292889e1 | 11636 | |
32ea06b6 VS |
11637 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
11638 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); | |
292889e1 | 11639 | |
7eb31a0b VS |
11640 | return cntl; |
11641 | } | |
11642 | ||
11643 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, | |
11644 | const struct intel_plane_state *plane_state) | |
11645 | { | |
11646 | struct drm_i915_private *dev_priv = | |
f90a85e7 | 11647 | to_i915(plane_state->uapi.plane->dev); |
7eb31a0b VS |
11648 | u32 cntl = 0; |
11649 | ||
11650 | if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) | |
11651 | cntl |= MCURSOR_TRICKLE_FEED_DISABLE; | |
11652 | ||
f90a85e7 | 11653 | switch (drm_rect_width(&plane_state->uapi.dst)) { |
292889e1 | 11654 | case 64: |
b99b9ec1 | 11655 | cntl |= MCURSOR_MODE_64_ARGB_AX; |
292889e1 VS |
11656 | break; |
11657 | case 128: | |
b99b9ec1 | 11658 | cntl |= MCURSOR_MODE_128_ARGB_AX; |
292889e1 VS |
11659 | break; |
11660 | case 256: | |
b99b9ec1 | 11661 | cntl |= MCURSOR_MODE_256_ARGB_AX; |
292889e1 VS |
11662 | break; |
11663 | default: | |
f90a85e7 | 11664 | MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); |
292889e1 VS |
11665 | return 0; |
11666 | } | |
11667 | ||
7b3cb17a | 11668 | if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) |
b99b9ec1 | 11669 | cntl |= MCURSOR_ROTATE_180; |
292889e1 VS |
11670 | |
11671 | return cntl; | |
11672 | } | |
11673 | ||
659056f2 | 11674 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 11675 | { |
024faac7 | 11676 | struct drm_i915_private *dev_priv = |
f90a85e7 ML |
11677 | to_i915(plane_state->uapi.plane->dev); |
11678 | int width = drm_rect_width(&plane_state->uapi.dst); | |
11679 | int height = drm_rect_height(&plane_state->uapi.dst); | |
4b0e333e | 11680 | |
3637ecf0 | 11681 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 11682 | return false; |
4398ad45 | 11683 | |
024faac7 VS |
11684 | /* Cursor width is limited to a few power-of-two sizes */ |
11685 | switch (width) { | |
659056f2 VS |
11686 | case 256: |
11687 | case 128: | |
659056f2 VS |
11688 | case 64: |
11689 | break; | |
11690 | default: | |
11691 | return false; | |
65a21cd6 | 11692 | } |
4b0e333e | 11693 | |
024faac7 VS |
11694 | /* |
11695 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
11696 | * height from 8 lines up to the cursor width, when the | |
11697 | * cursor is not rotated. Everything else requires square | |
11698 | * cursors. | |
11699 | */ | |
11700 | if (HAS_CUR_FBC(dev_priv) && | |
7b3cb17a | 11701 | plane_state->hw.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
11702 | if (height < 8 || height > width) |
11703 | return false; | |
11704 | } else { | |
11705 | if (height != width) | |
11706 | return false; | |
11707 | } | |
99d1f387 | 11708 | |
659056f2 | 11709 | return true; |
65a21cd6 JB |
11710 | } |
11711 | ||
eb0f5044 | 11712 | static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, |
659056f2 | 11713 | struct intel_plane_state *plane_state) |
cda4b7d3 | 11714 | { |
f90a85e7 | 11715 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
659056f2 | 11716 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 11717 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
659056f2 | 11718 | enum pipe pipe = plane->pipe; |
659056f2 | 11719 | int ret; |
cda4b7d3 | 11720 | |
659056f2 VS |
11721 | ret = intel_check_cursor(crtc_state, plane_state); |
11722 | if (ret) | |
11723 | return ret; | |
cda4b7d3 | 11724 | |
659056f2 | 11725 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 11726 | if (!fb) |
659056f2 | 11727 | return 0; |
55a08b3f | 11728 | |
659056f2 VS |
11729 | /* Check for which cursor types we support */ |
11730 | if (!i9xx_cursor_size_ok(plane_state)) { | |
cd49f818 WK |
11731 | drm_dbg(&dev_priv->drm, |
11732 | "Cursor dimension %dx%d not supported\n", | |
11733 | drm_rect_width(&plane_state->uapi.dst), | |
11734 | drm_rect_height(&plane_state->uapi.dst)); | |
659056f2 | 11735 | return -EINVAL; |
cda4b7d3 | 11736 | } |
cda4b7d3 | 11737 | |
e57291c2 PB |
11738 | drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && |
11739 | plane_state->color_plane[0].stride != fb->pitches[0]); | |
df79cf44 | 11740 | |
3a612765 | 11741 | if (fb->pitches[0] != |
f90a85e7 | 11742 | drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { |
cd49f818 WK |
11743 | drm_dbg_kms(&dev_priv->drm, |
11744 | "Invalid cursor stride (%u) (cursor width %d)\n", | |
11745 | fb->pitches[0], | |
11746 | drm_rect_width(&plane_state->uapi.dst)); | |
1e1bb871 | 11747 | return -EINVAL; |
659056f2 | 11748 | } |
dd584fc0 | 11749 | |
659056f2 VS |
11750 | /* |
11751 | * There's something wrong with the cursor on CHV pipe C. | |
11752 | * If it straddles the left edge of the screen then | |
11753 | * moving it away from the edge or disabling it often | |
11754 | * results in a pipe underrun, and often that can lead to | |
11755 | * dead pipe (constant underrun reported, and it scans | |
11756 | * out just a solid color). To recover from that, the | |
11757 | * display power well must be turned off and on again. | |
11758 | * Refuse the put the cursor into that compromised position. | |
11759 | */ | |
11760 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
f90a85e7 | 11761 | plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { |
cd49f818 WK |
11762 | drm_dbg_kms(&dev_priv->drm, |
11763 | "CHV cursor C not allowed to straddle the left screen edge\n"); | |
659056f2 VS |
11764 | return -EINVAL; |
11765 | } | |
5efb3e28 | 11766 | |
659056f2 | 11767 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 11768 | |
659056f2 | 11769 | return 0; |
cda4b7d3 CW |
11770 | } |
11771 | ||
b2d03b0d VS |
11772 | static void i9xx_update_cursor(struct intel_plane *plane, |
11773 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 11774 | const struct intel_plane_state *plane_state) |
dc41c154 | 11775 | { |
cd5dcbf1 VS |
11776 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
11777 | enum pipe pipe = plane->pipe; | |
024faac7 | 11778 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 11779 | unsigned long irqflags; |
dc41c154 | 11780 | |
f90a85e7 ML |
11781 | if (plane_state && plane_state->uapi.visible) { |
11782 | unsigned width = drm_rect_width(&plane_state->uapi.dst); | |
11783 | unsigned height = drm_rect_height(&plane_state->uapi.dst); | |
3a612765 | 11784 | |
7eb31a0b VS |
11785 | cntl = plane_state->ctl | |
11786 | i9xx_cursor_ctl_crtc(crtc_state); | |
dc41c154 | 11787 | |
3a612765 ML |
11788 | if (width != height) |
11789 | fbc_ctl = CUR_FBC_CTL_EN | (height - 1); | |
dc41c154 | 11790 | |
b2d03b0d VS |
11791 | base = intel_cursor_base(plane_state); |
11792 | pos = intel_cursor_position(plane_state); | |
11793 | } | |
11794 | ||
11795 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
11796 | ||
e11ffddb VS |
11797 | /* |
11798 | * On some platforms writing CURCNTR first will also | |
11799 | * cause CURPOS to be armed by the CURBASE write. | |
11800 | * Without the CURCNTR write the CURPOS write would | |
83234d13 VS |
11801 | * arm itself. Thus we always update CURCNTR before |
11802 | * CURPOS. | |
8753d2bc VS |
11803 | * |
11804 | * On other platforms CURPOS always requires the | |
11805 | * CURBASE write to arm the update. Additonally | |
11806 | * a write to any of the cursor register will cancel | |
11807 | * an already armed cursor update. Thus leaving out | |
11808 | * the CURBASE write after CURPOS could lead to a | |
11809 | * cursor that doesn't appear to move, or even change | |
11810 | * shape. Thus we always write CURBASE. | |
e11ffddb | 11811 | * |
83234d13 VS |
11812 | * The other registers are armed by by the CURBASE write |
11813 | * except when the plane is getting enabled at which time | |
11814 | * the CURCNTR write arms the update. | |
e11ffddb | 11815 | */ |
ff43bc37 VS |
11816 | |
11817 | if (INTEL_GEN(dev_priv) >= 9) | |
11818 | skl_write_cursor_wm(plane, crtc_state); | |
11819 | ||
e11ffddb VS |
11820 | if (plane->cursor.base != base || |
11821 | plane->cursor.size != fbc_ctl || | |
11822 | plane->cursor.cntl != cntl) { | |
e11ffddb | 11823 | if (HAS_CUR_FBC(dev_priv)) |
dc008bf0 JN |
11824 | intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), |
11825 | fbc_ctl); | |
11826 | intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); | |
11827 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); | |
11828 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
75343a44 | 11829 | |
e11ffddb VS |
11830 | plane->cursor.base = base; |
11831 | plane->cursor.size = fbc_ctl; | |
11832 | plane->cursor.cntl = cntl; | |
dc41c154 | 11833 | } else { |
dc008bf0 JN |
11834 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); |
11835 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
dc41c154 VS |
11836 | } |
11837 | ||
b2d03b0d | 11838 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
11839 | } |
11840 | ||
b2d03b0d | 11841 | static void i9xx_disable_cursor(struct intel_plane *plane, |
0dd14be3 | 11842 | const struct intel_crtc_state *crtc_state) |
cda4b7d3 | 11843 | { |
0dd14be3 | 11844 | i9xx_update_cursor(plane, crtc_state, NULL); |
dc41c154 VS |
11845 | } |
11846 | ||
eade6c89 VS |
11847 | static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, |
11848 | enum pipe *pipe) | |
51f5a096 VS |
11849 | { |
11850 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
11851 | enum intel_display_power_domain power_domain; | |
0e6e0be4 | 11852 | intel_wakeref_t wakeref; |
51f5a096 | 11853 | bool ret; |
eade6c89 | 11854 | u32 val; |
51f5a096 VS |
11855 | |
11856 | /* | |
11857 | * Not 100% correct for planes that can move between pipes, | |
11858 | * but that's only the case for gen2-3 which don't have any | |
11859 | * display power wells. | |
11860 | */ | |
eade6c89 | 11861 | power_domain = POWER_DOMAIN_PIPE(plane->pipe); |
0e6e0be4 CW |
11862 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
11863 | if (!wakeref) | |
51f5a096 VS |
11864 | return false; |
11865 | ||
dc008bf0 | 11866 | val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); |
eade6c89 | 11867 | |
b99b9ec1 | 11868 | ret = val & MCURSOR_MODE; |
eade6c89 VS |
11869 | |
11870 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) | |
11871 | *pipe = plane->pipe; | |
11872 | else | |
11873 | *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> | |
11874 | MCURSOR_PIPE_SELECT_SHIFT; | |
51f5a096 | 11875 | |
0e6e0be4 | 11876 | intel_display_power_put(dev_priv, power_domain, wakeref); |
51f5a096 VS |
11877 | |
11878 | return ret; | |
11879 | } | |
dc41c154 | 11880 | |
79e53945 | 11881 | /* VESA 640x480x72Hz mode to set on the pipe */ |
bacdcd55 | 11882 | static const struct drm_display_mode load_detect_mode = { |
79e53945 JB |
11883 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
11884 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
11885 | }; | |
11886 | ||
a8bb6818 | 11887 | struct drm_framebuffer * |
24dbf51a CW |
11888 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
11889 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
11890 | { |
11891 | struct intel_framebuffer *intel_fb; | |
11892 | int ret; | |
11893 | ||
11894 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 11895 | if (!intel_fb) |
d2dff872 | 11896 | return ERR_PTR(-ENOMEM); |
d2dff872 | 11897 | |
24dbf51a | 11898 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
11899 | if (ret) |
11900 | goto err; | |
d2dff872 CW |
11901 | |
11902 | return &intel_fb->base; | |
dcb1394e | 11903 | |
dd4916c5 | 11904 | err: |
dd4916c5 | 11905 | kfree(intel_fb); |
dd4916c5 | 11906 | return ERR_PTR(ret); |
d2dff872 CW |
11907 | } |
11908 | ||
20bdc112 VS |
11909 | static int intel_modeset_disable_planes(struct drm_atomic_state *state, |
11910 | struct drm_crtc *crtc) | |
d3a40d1b | 11911 | { |
20bdc112 | 11912 | struct drm_plane *plane; |
d3a40d1b | 11913 | struct drm_plane_state *plane_state; |
20bdc112 | 11914 | int ret, i; |
d3a40d1b | 11915 | |
20bdc112 | 11916 | ret = drm_atomic_add_affected_planes(state, crtc); |
d3a40d1b ACO |
11917 | if (ret) |
11918 | return ret; | |
20bdc112 VS |
11919 | |
11920 | for_each_new_plane_in_state(state, plane, plane_state, i) { | |
11921 | if (plane_state->crtc != crtc) | |
11922 | continue; | |
11923 | ||
11924 | ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); | |
11925 | if (ret) | |
11926 | return ret; | |
11927 | ||
11928 | drm_atomic_set_fb_for_plane(plane_state, NULL); | |
11929 | } | |
d3a40d1b ACO |
11930 | |
11931 | return 0; | |
11932 | } | |
11933 | ||
6c5ed5ae | 11934 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
6c5ed5ae ML |
11935 | struct intel_load_detect_pipe *old, |
11936 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11937 | { |
11938 | struct intel_crtc *intel_crtc; | |
d2434ab7 | 11939 | struct intel_encoder *intel_encoder = |
43a6d19c | 11940 | intel_attached_encoder(to_intel_connector(connector)); |
79e53945 | 11941 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11942 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11943 | struct drm_crtc *crtc = NULL; |
11944 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 11945 | struct drm_i915_private *dev_priv = to_i915(dev); |
51fd371b | 11946 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11947 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11948 | struct drm_connector_state *connector_state; |
4be07317 | 11949 | struct intel_crtc_state *crtc_state; |
51fd371b | 11950 | int ret, i = -1; |
79e53945 | 11951 | |
cd49f818 WK |
11952 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
11953 | connector->base.id, connector->name, | |
11954 | encoder->base.id, encoder->name); | |
d2dff872 | 11955 | |
edde3617 ML |
11956 | old->restore_state = NULL; |
11957 | ||
e57291c2 | 11958 | drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 11959 | |
79e53945 JB |
11960 | /* |
11961 | * Algorithm gets a little messy: | |
7a5e4805 | 11962 | * |
79e53945 JB |
11963 | * - if the connector already has an assigned crtc, use it (but make |
11964 | * sure it's on first) | |
7a5e4805 | 11965 | * |
79e53945 JB |
11966 | * - try to find the first unused crtc that can drive this connector, |
11967 | * and use that if we find one | |
79e53945 JB |
11968 | */ |
11969 | ||
11970 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11971 | if (connector->state->crtc) { |
11972 | crtc = connector->state->crtc; | |
8261b191 | 11973 | |
51fd371b | 11974 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11975 | if (ret) |
ad3c558f | 11976 | goto fail; |
8261b191 CW |
11977 | |
11978 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11979 | goto found; |
79e53945 JB |
11980 | } |
11981 | ||
11982 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11983 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11984 | i++; |
11985 | if (!(encoder->possible_crtcs & (1 << i))) | |
11986 | continue; | |
edde3617 ML |
11987 | |
11988 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11989 | if (ret) | |
11990 | goto fail; | |
11991 | ||
11992 | if (possible_crtc->state->enable) { | |
11993 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11994 | continue; |
edde3617 | 11995 | } |
a459249c VS |
11996 | |
11997 | crtc = possible_crtc; | |
11998 | break; | |
79e53945 JB |
11999 | } |
12000 | ||
12001 | /* | |
12002 | * If we didn't find an unused CRTC, don't use any. | |
12003 | */ | |
12004 | if (!crtc) { | |
cd49f818 WK |
12005 | drm_dbg_kms(&dev_priv->drm, |
12006 | "no pipe available for load-detect\n"); | |
f4bf77b4 | 12007 | ret = -ENODEV; |
ad3c558f | 12008 | goto fail; |
79e53945 JB |
12009 | } |
12010 | ||
edde3617 ML |
12011 | found: |
12012 | intel_crtc = to_intel_crtc(crtc); | |
12013 | ||
83a57153 | 12014 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
12015 | restore_state = drm_atomic_state_alloc(dev); |
12016 | if (!state || !restore_state) { | |
12017 | ret = -ENOMEM; | |
12018 | goto fail; | |
12019 | } | |
83a57153 ACO |
12020 | |
12021 | state->acquire_ctx = ctx; | |
edde3617 | 12022 | restore_state->acquire_ctx = ctx; |
83a57153 | 12023 | |
944b0c76 ACO |
12024 | connector_state = drm_atomic_get_connector_state(state, connector); |
12025 | if (IS_ERR(connector_state)) { | |
12026 | ret = PTR_ERR(connector_state); | |
12027 | goto fail; | |
12028 | } | |
12029 | ||
edde3617 ML |
12030 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
12031 | if (ret) | |
12032 | goto fail; | |
944b0c76 | 12033 | |
4be07317 ACO |
12034 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
12035 | if (IS_ERR(crtc_state)) { | |
12036 | ret = PTR_ERR(crtc_state); | |
12037 | goto fail; | |
12038 | } | |
12039 | ||
aa42a50a | 12040 | crtc_state->uapi.active = true; |
4be07317 | 12041 | |
2225f3c6 | 12042 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, |
25f89954 | 12043 | &load_detect_mode); |
d3a40d1b ACO |
12044 | if (ret) |
12045 | goto fail; | |
12046 | ||
20bdc112 | 12047 | ret = intel_modeset_disable_planes(state, crtc); |
edde3617 ML |
12048 | if (ret) |
12049 | goto fail; | |
12050 | ||
12051 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
12052 | if (!ret) | |
12053 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
be90cc31 VS |
12054 | if (!ret) |
12055 | ret = drm_atomic_add_affected_planes(restore_state, crtc); | |
edde3617 | 12056 | if (ret) { |
cd49f818 WK |
12057 | drm_dbg_kms(&dev_priv->drm, |
12058 | "Failed to create a copy of old state to restore: %i\n", | |
12059 | ret); | |
edde3617 ML |
12060 | goto fail; |
12061 | } | |
8c7b5ccb | 12062 | |
3ba86073 ML |
12063 | ret = drm_atomic_commit(state); |
12064 | if (ret) { | |
cd49f818 WK |
12065 | drm_dbg_kms(&dev_priv->drm, |
12066 | "failed to set mode on load-detect pipe\n"); | |
412b61d8 | 12067 | goto fail; |
79e53945 | 12068 | } |
edde3617 ML |
12069 | |
12070 | old->restore_state = restore_state; | |
7abbd11f | 12071 | drm_atomic_state_put(state); |
7173188d | 12072 | |
79e53945 | 12073 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 12074 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 12075 | return true; |
412b61d8 | 12076 | |
ad3c558f | 12077 | fail: |
7fb71c8f CW |
12078 | if (state) { |
12079 | drm_atomic_state_put(state); | |
12080 | state = NULL; | |
12081 | } | |
12082 | if (restore_state) { | |
12083 | drm_atomic_state_put(restore_state); | |
12084 | restore_state = NULL; | |
12085 | } | |
83a57153 | 12086 | |
6c5ed5ae ML |
12087 | if (ret == -EDEADLK) |
12088 | return ret; | |
51fd371b | 12089 | |
412b61d8 | 12090 | return false; |
79e53945 JB |
12091 | } |
12092 | ||
d2434ab7 | 12093 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
12094 | struct intel_load_detect_pipe *old, |
12095 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 12096 | { |
d2434ab7 | 12097 | struct intel_encoder *intel_encoder = |
43a6d19c | 12098 | intel_attached_encoder(to_intel_connector(connector)); |
cd49f818 | 12099 | struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); |
4ef69c7a | 12100 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 12101 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 12102 | int ret; |
79e53945 | 12103 | |
cd49f818 WK |
12104 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
12105 | connector->base.id, connector->name, | |
12106 | encoder->base.id, encoder->name); | |
d2dff872 | 12107 | |
edde3617 | 12108 | if (!state) |
0622a53c | 12109 | return; |
79e53945 | 12110 | |
581e49fe | 12111 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 12112 | if (ret) |
cd49f818 WK |
12113 | drm_dbg_kms(&i915->drm, |
12114 | "Couldn't release load detect pipe: %i\n", ret); | |
0853695c | 12115 | drm_atomic_state_put(state); |
79e53945 JB |
12116 | } |
12117 | ||
da4a1efa | 12118 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 12119 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 12120 | { |
fac5e23e | 12121 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
12122 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
12123 | ||
12124 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 12125 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 12126 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 12127 | return 120000; |
cf819eff | 12128 | else if (!IS_GEN(dev_priv, 2)) |
da4a1efa VS |
12129 | return 96000; |
12130 | else | |
12131 | return 48000; | |
12132 | } | |
12133 | ||
79e53945 | 12134 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 12135 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 12136 | struct intel_crtc_state *pipe_config) |
79e53945 | 12137 | { |
f1f644dc | 12138 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 12139 | struct drm_i915_private *dev_priv = to_i915(dev); |
d048a268 | 12140 | enum pipe pipe = crtc->pipe; |
293623f7 | 12141 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 12142 | u32 fp; |
9e2c8475 | 12143 | struct dpll clock; |
dccbea3b | 12144 | int port_clock; |
da4a1efa | 12145 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
12146 | |
12147 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 12148 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 12149 | else |
293623f7 | 12150 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
12151 | |
12152 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 12153 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
12154 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
12155 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
12156 | } else { |
12157 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
12158 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
12159 | } | |
12160 | ||
cf819eff | 12161 | if (!IS_GEN(dev_priv, 2)) { |
9b1e14f4 | 12162 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
12163 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
12164 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
12165 | else |
12166 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
12167 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
12168 | ||
12169 | switch (dpll & DPLL_MODE_MASK) { | |
12170 | case DPLLB_MODE_DAC_SERIAL: | |
12171 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
12172 | 5 : 10; | |
12173 | break; | |
12174 | case DPLLB_MODE_LVDS: | |
12175 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
12176 | 7 : 14; | |
12177 | break; | |
12178 | default: | |
cd49f818 WK |
12179 | drm_dbg_kms(&dev_priv->drm, |
12180 | "Unknown DPLL mode %08x in programmed " | |
12181 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
f1f644dc | 12182 | return; |
79e53945 JB |
12183 | } |
12184 | ||
9b1e14f4 | 12185 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 12186 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 12187 | else |
dccbea3b | 12188 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 12189 | } else { |
dc008bf0 JN |
12190 | u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv, |
12191 | LVDS); | |
b1c560d1 | 12192 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
12193 | |
12194 | if (is_lvds) { | |
12195 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
12196 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
12197 | |
12198 | if (lvds & LVDS_CLKB_POWER_UP) | |
12199 | clock.p2 = 7; | |
12200 | else | |
12201 | clock.p2 = 14; | |
79e53945 JB |
12202 | } else { |
12203 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
12204 | clock.p1 = 2; | |
12205 | else { | |
12206 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
12207 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
12208 | } | |
12209 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
12210 | clock.p2 = 4; | |
12211 | else | |
12212 | clock.p2 = 2; | |
79e53945 | 12213 | } |
da4a1efa | 12214 | |
dccbea3b | 12215 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
12216 | } |
12217 | ||
18442d08 VS |
12218 | /* |
12219 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 12220 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
12221 | * encoder's get_config() function. |
12222 | */ | |
dccbea3b | 12223 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
12224 | } |
12225 | ||
6878da05 VS |
12226 | int intel_dotclock_calculate(int link_freq, |
12227 | const struct intel_link_m_n *m_n) | |
f1f644dc | 12228 | { |
f1f644dc JB |
12229 | /* |
12230 | * The calculation for the data clock is: | |
1041a02f | 12231 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 12232 | * But we want to avoid losing precison if possible, so: |
1041a02f | 12233 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
12234 | * |
12235 | * and the link clock is simpler: | |
1041a02f | 12236 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
12237 | */ |
12238 | ||
6878da05 VS |
12239 | if (!m_n->link_n) |
12240 | return 0; | |
f1f644dc | 12241 | |
3123698f | 12242 | return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); |
6878da05 | 12243 | } |
f1f644dc | 12244 | |
9eae5e27 LDM |
12245 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
12246 | struct intel_crtc_state *pipe_config) | |
6878da05 | 12247 | { |
e3b247da | 12248 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 12249 | |
18442d08 VS |
12250 | /* read out port_clock from the DPLL */ |
12251 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 12252 | |
f1f644dc | 12253 | /* |
e3b247da VS |
12254 | * In case there is an active pipe without active ports, |
12255 | * we may need some idea for the dotclock anyway. | |
12256 | * Calculate one based on the FDI configuration. | |
79e53945 | 12257 | */ |
1326a92c | 12258 | pipe_config->hw.adjusted_mode.crtc_clock = |
21a727b3 | 12259 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 12260 | &pipe_config->fdi_m_n); |
79e53945 JB |
12261 | } |
12262 | ||
979e94c1 VS |
12263 | static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, |
12264 | struct intel_crtc *crtc) | |
12265 | { | |
12266 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
12267 | ||
12268 | __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); | |
12269 | ||
12270 | crtc_state->cpu_transcoder = INVALID_TRANSCODER; | |
12271 | crtc_state->master_transcoder = INVALID_TRANSCODER; | |
12272 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; | |
12273 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID; | |
12274 | crtc_state->scaler_state.scaler_id = -1; | |
6671c367 | 12275 | crtc_state->mst_master_transcoder = INVALID_TRANSCODER; |
979e94c1 VS |
12276 | } |
12277 | ||
216383e9 VS |
12278 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) |
12279 | { | |
12280 | struct intel_crtc_state *crtc_state; | |
12281 | ||
12282 | crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); | |
12283 | ||
12284 | if (crtc_state) | |
12285 | intel_crtc_state_reset(crtc_state, crtc); | |
12286 | ||
12287 | return crtc_state; | |
12288 | } | |
12289 | ||
de330815 VS |
12290 | /* Returns the currently programmed mode of the given encoder. */ |
12291 | struct drm_display_mode * | |
12292 | intel_encoder_current_mode(struct intel_encoder *encoder) | |
79e53945 | 12293 | { |
de330815 VS |
12294 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
12295 | struct intel_crtc_state *crtc_state; | |
79e53945 | 12296 | struct drm_display_mode *mode; |
de330815 VS |
12297 | struct intel_crtc *crtc; |
12298 | enum pipe pipe; | |
12299 | ||
12300 | if (!encoder->get_hw_state(encoder, &pipe)) | |
12301 | return NULL; | |
12302 | ||
12303 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
79e53945 JB |
12304 | |
12305 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
12306 | if (!mode) | |
12307 | return NULL; | |
12308 | ||
216383e9 | 12309 | crtc_state = intel_crtc_state_alloc(crtc); |
de330815 | 12310 | if (!crtc_state) { |
3f36b937 TU |
12311 | kfree(mode); |
12312 | return NULL; | |
12313 | } | |
12314 | ||
de330815 VS |
12315 | if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { |
12316 | kfree(crtc_state); | |
12317 | kfree(mode); | |
12318 | return NULL; | |
12319 | } | |
e30a154b | 12320 | |
de330815 | 12321 | encoder->get_config(encoder, crtc_state); |
79e53945 | 12322 | |
de330815 | 12323 | intel_mode_from_pipe_config(mode, crtc_state); |
79e53945 | 12324 | |
de330815 | 12325 | kfree(crtc_state); |
3f36b937 | 12326 | |
79e53945 JB |
12327 | return mode; |
12328 | } | |
12329 | ||
12330 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
12331 | { | |
12332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12333 | ||
12334 | drm_crtc_cleanup(crtc); | |
12335 | kfree(intel_crtc); | |
12336 | } | |
12337 | ||
5a21b665 DV |
12338 | /** |
12339 | * intel_wm_need_update - Check whether watermarks need updating | |
6bf19817 CW |
12340 | * @cur: current plane state |
12341 | * @new: new plane state | |
5a21b665 DV |
12342 | * |
12343 | * Check current plane state versus the new one to determine whether | |
12344 | * watermarks need to be recalculated. | |
12345 | * | |
12346 | * Returns true or false. | |
12347 | */ | |
4f25720b | 12348 | static bool intel_wm_need_update(const struct intel_plane_state *cur, |
cd1d3ee9 | 12349 | struct intel_plane_state *new) |
5a21b665 | 12350 | { |
5a21b665 | 12351 | /* Update watermarks on tiling or size changes. */ |
f90a85e7 | 12352 | if (new->uapi.visible != cur->uapi.visible) |
5a21b665 DV |
12353 | return true; |
12354 | ||
7b3cb17a | 12355 | if (!cur->hw.fb || !new->hw.fb) |
5a21b665 DV |
12356 | return false; |
12357 | ||
7b3cb17a ML |
12358 | if (cur->hw.fb->modifier != new->hw.fb->modifier || |
12359 | cur->hw.rotation != new->hw.rotation || | |
f90a85e7 ML |
12360 | drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) || |
12361 | drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) || | |
12362 | drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) || | |
12363 | drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst)) | |
5a21b665 DV |
12364 | return true; |
12365 | ||
12366 | return false; | |
12367 | } | |
12368 | ||
b2b55502 | 12369 | static bool needs_scaling(const struct intel_plane_state *state) |
5a21b665 | 12370 | { |
f90a85e7 ML |
12371 | int src_w = drm_rect_width(&state->uapi.src) >> 16; |
12372 | int src_h = drm_rect_height(&state->uapi.src) >> 16; | |
12373 | int dst_w = drm_rect_width(&state->uapi.dst); | |
12374 | int dst_h = drm_rect_height(&state->uapi.dst); | |
5a21b665 DV |
12375 | |
12376 | return (src_w != dst_w || src_h != dst_h); | |
12377 | } | |
d21fbe87 | 12378 | |
b2b55502 | 12379 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
4f25720b | 12380 | struct intel_crtc_state *crtc_state, |
b2b55502 | 12381 | const struct intel_plane_state *old_plane_state, |
4f25720b | 12382 | struct intel_plane_state *plane_state) |
da20eabd | 12383 | { |
2225f3c6 | 12384 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f90a85e7 | 12385 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
4f25720b ML |
12386 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
12387 | bool mode_changed = needs_modeset(crtc_state); | |
1326a92c ML |
12388 | bool was_crtc_enabled = old_crtc_state->hw.active; |
12389 | bool is_crtc_enabled = crtc_state->hw.active; | |
da20eabd | 12390 | bool turn_off, turn_on, visible, was_visible; |
78108b7c | 12391 | int ret; |
da20eabd | 12392 | |
e9728bd8 | 12393 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
4f25720b | 12394 | ret = skl_update_scaler_plane(crtc_state, plane_state); |
da20eabd ML |
12395 | if (ret) |
12396 | return ret; | |
12397 | } | |
12398 | ||
f90a85e7 ML |
12399 | was_visible = old_plane_state->uapi.visible; |
12400 | visible = plane_state->uapi.visible; | |
da20eabd | 12401 | |
e57291c2 | 12402 | if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) |
da20eabd ML |
12403 | was_visible = false; |
12404 | ||
35c08f43 ML |
12405 | /* |
12406 | * Visibility is calculated as if the crtc was on, but | |
12407 | * after scaler setup everything depends on it being off | |
12408 | * when the crtc isn't active. | |
f818ffea VS |
12409 | * |
12410 | * FIXME this is wrong for watermarks. Watermarks should also | |
12411 | * be computed as if the pipe would be active. Perhaps move | |
12412 | * per-plane wm computation to the .check_plane() hook, and | |
12413 | * only combine the results from all planes in the current place? | |
35c08f43 | 12414 | */ |
e9728bd8 | 12415 | if (!is_crtc_enabled) { |
cb1824bb VS |
12416 | intel_plane_set_invisible(crtc_state, plane_state); |
12417 | visible = false; | |
e9728bd8 | 12418 | } |
da20eabd ML |
12419 | |
12420 | if (!was_visible && !visible) | |
12421 | return 0; | |
12422 | ||
12423 | turn_off = was_visible && (!visible || mode_changed); | |
12424 | turn_on = visible && (!was_visible || mode_changed); | |
12425 | ||
cd49f818 WK |
12426 | drm_dbg_atomic(&dev_priv->drm, |
12427 | "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", | |
12428 | crtc->base.base.id, crtc->base.name, | |
12429 | plane->base.base.id, plane->base.name, | |
12430 | was_visible, visible, | |
12431 | turn_off, turn_on, mode_changed); | |
da20eabd | 12432 | |
caed361d | 12433 | if (turn_on) { |
04548cba | 12434 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
4f25720b | 12435 | crtc_state->update_wm_pre = true; |
caed361d VS |
12436 | |
12437 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 12438 | if (plane->id != PLANE_CURSOR) |
4f25720b | 12439 | crtc_state->disable_cxsr = true; |
caed361d | 12440 | } else if (turn_off) { |
04548cba | 12441 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
4f25720b | 12442 | crtc_state->update_wm_post = true; |
92826fcd | 12443 | |
852eb00d | 12444 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 12445 | if (plane->id != PLANE_CURSOR) |
4f25720b ML |
12446 | crtc_state->disable_cxsr = true; |
12447 | } else if (intel_wm_need_update(old_plane_state, plane_state)) { | |
04548cba | 12448 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df | 12449 | /* FIXME bollocks */ |
4f25720b ML |
12450 | crtc_state->update_wm_pre = true; |
12451 | crtc_state->update_wm_post = true; | |
b4ede6df | 12452 | } |
852eb00d | 12453 | } |
da20eabd | 12454 | |
8be6ca85 | 12455 | if (visible || was_visible) |
4f25720b | 12456 | crtc_state->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 12457 | |
31ae71fc | 12458 | /* |
8e7a4424 VS |
12459 | * ILK/SNB DVSACNTR/Sprite Enable |
12460 | * IVB SPR_CTL/Sprite Enable | |
12461 | * "When in Self Refresh Big FIFO mode, a write to enable the | |
12462 | * plane will be internally buffered and delayed while Big FIFO | |
12463 | * mode is exiting." | |
12464 | * | |
12465 | * Which means that enabling the sprite can take an extra frame | |
12466 | * when we start in big FIFO mode (LP1+). Thus we need to drop | |
12467 | * down to LP0 and wait for vblank in order to make sure the | |
12468 | * sprite gets enabled on the next vblank after the register write. | |
12469 | * Doing otherwise would risk enabling the sprite one frame after | |
12470 | * we've already signalled flip completion. We can resume LP1+ | |
12471 | * once the sprite has been enabled. | |
12472 | * | |
12473 | * | |
31ae71fc | 12474 | * WaCxSRDisabledForSpriteScaling:ivb |
8e7a4424 VS |
12475 | * IVB SPR_SCALE/Scaling Enable |
12476 | * "Low Power watermarks must be disabled for at least one | |
12477 | * frame before enabling sprite scaling, and kept disabled | |
12478 | * until sprite scaling is disabled." | |
12479 | * | |
12480 | * ILK/SNB DVSASCALE/Scaling Enable | |
12481 | * "When in Self Refresh Big FIFO mode, scaling enable will be | |
12482 | * masked off while Big FIFO mode is exiting." | |
31ae71fc | 12483 | * |
8e7a4424 VS |
12484 | * Despite the w/a only being listed for IVB we assume that |
12485 | * the ILK/SNB note has similar ramifications, hence we apply | |
12486 | * the w/a on all three platforms. | |
d8af3270 JPH |
12487 | * |
12488 | * With experimental results seems this is needed also for primary | |
12489 | * plane, not only sprite plane. | |
31ae71fc | 12490 | */ |
d8af3270 | 12491 | if (plane->id != PLANE_CURSOR && |
f3ce44a0 | 12492 | (IS_GEN_RANGE(dev_priv, 5, 6) || |
8e7a4424 VS |
12493 | IS_IVYBRIDGE(dev_priv)) && |
12494 | (turn_on || (!needs_scaling(old_plane_state) && | |
4f25720b ML |
12495 | needs_scaling(plane_state)))) |
12496 | crtc_state->disable_lp_wm = true; | |
d21fbe87 | 12497 | |
da20eabd ML |
12498 | return 0; |
12499 | } | |
12500 | ||
6d3a1ce7 ML |
12501 | static bool encoders_cloneable(const struct intel_encoder *a, |
12502 | const struct intel_encoder *b) | |
12503 | { | |
12504 | /* masks could be asymmetric, so check both ways */ | |
12505 | return a == b || (a->cloneable & (1 << b->type) && | |
12506 | b->cloneable & (1 << a->type)); | |
12507 | } | |
12508 | ||
12509 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12510 | struct intel_crtc *crtc, | |
12511 | struct intel_encoder *encoder) | |
12512 | { | |
12513 | struct intel_encoder *source_encoder; | |
12514 | struct drm_connector *connector; | |
12515 | struct drm_connector_state *connector_state; | |
12516 | int i; | |
12517 | ||
aa5e9b47 | 12518 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
12519 | if (connector_state->crtc != &crtc->base) |
12520 | continue; | |
12521 | ||
12522 | source_encoder = | |
12523 | to_intel_encoder(connector_state->best_encoder); | |
12524 | if (!encoders_cloneable(encoder, source_encoder)) | |
12525 | return false; | |
12526 | } | |
12527 | ||
12528 | return true; | |
12529 | } | |
12530 | ||
1ab554b0 ML |
12531 | static int icl_add_linked_planes(struct intel_atomic_state *state) |
12532 | { | |
12533 | struct intel_plane *plane, *linked; | |
12534 | struct intel_plane_state *plane_state, *linked_plane_state; | |
12535 | int i; | |
12536 | ||
12537 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
c47b7ddb | 12538 | linked = plane_state->planar_linked_plane; |
1ab554b0 ML |
12539 | |
12540 | if (!linked) | |
12541 | continue; | |
12542 | ||
12543 | linked_plane_state = intel_atomic_get_plane_state(state, linked); | |
12544 | if (IS_ERR(linked_plane_state)) | |
12545 | return PTR_ERR(linked_plane_state); | |
12546 | ||
ce04ecd9 PB |
12547 | drm_WARN_ON(state->base.dev, |
12548 | linked_plane_state->planar_linked_plane != plane); | |
12549 | drm_WARN_ON(state->base.dev, | |
12550 | linked_plane_state->planar_slave == plane_state->planar_slave); | |
1ab554b0 ML |
12551 | } |
12552 | ||
12553 | return 0; | |
12554 | } | |
12555 | ||
12556 | static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) | |
12557 | { | |
2225f3c6 | 12558 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1ab554b0 | 12559 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2225f3c6 | 12560 | struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); |
1ab554b0 ML |
12561 | struct intel_plane *plane, *linked; |
12562 | struct intel_plane_state *plane_state; | |
12563 | int i; | |
12564 | ||
12565 | if (INTEL_GEN(dev_priv) < 11) | |
12566 | return 0; | |
12567 | ||
12568 | /* | |
12569 | * Destroy all old plane links and make the slave plane invisible | |
12570 | * in the crtc_state->active_planes mask. | |
12571 | */ | |
12572 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
c47b7ddb | 12573 | if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) |
1ab554b0 ML |
12574 | continue; |
12575 | ||
c47b7ddb | 12576 | plane_state->planar_linked_plane = NULL; |
f90a85e7 | 12577 | if (plane_state->planar_slave && !plane_state->uapi.visible) { |
1ab554b0 | 12578 | crtc_state->active_planes &= ~BIT(plane->id); |
afbd8a72 VS |
12579 | crtc_state->update_planes |= BIT(plane->id); |
12580 | } | |
1ab554b0 | 12581 | |
c47b7ddb | 12582 | plane_state->planar_slave = false; |
1ab554b0 ML |
12583 | } |
12584 | ||
12585 | if (!crtc_state->nv12_planes) | |
12586 | return 0; | |
12587 | ||
12588 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { | |
12589 | struct intel_plane_state *linked_state = NULL; | |
12590 | ||
12591 | if (plane->pipe != crtc->pipe || | |
12592 | !(crtc_state->nv12_planes & BIT(plane->id))) | |
12593 | continue; | |
12594 | ||
12595 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { | |
99e2d8bc | 12596 | if (!icl_is_nv12_y_plane(dev_priv, linked->id)) |
1ab554b0 ML |
12597 | continue; |
12598 | ||
12599 | if (crtc_state->active_planes & BIT(linked->id)) | |
12600 | continue; | |
12601 | ||
12602 | linked_state = intel_atomic_get_plane_state(state, linked); | |
12603 | if (IS_ERR(linked_state)) | |
12604 | return PTR_ERR(linked_state); | |
12605 | ||
12606 | break; | |
12607 | } | |
12608 | ||
12609 | if (!linked_state) { | |
cd49f818 WK |
12610 | drm_dbg_kms(&dev_priv->drm, |
12611 | "Need %d free Y planes for planar YUV\n", | |
12612 | hweight8(crtc_state->nv12_planes)); | |
1ab554b0 ML |
12613 | |
12614 | return -EINVAL; | |
12615 | } | |
12616 | ||
c47b7ddb | 12617 | plane_state->planar_linked_plane = linked; |
1ab554b0 | 12618 | |
c47b7ddb ML |
12619 | linked_state->planar_slave = true; |
12620 | linked_state->planar_linked_plane = plane; | |
1ab554b0 | 12621 | crtc_state->active_planes |= BIT(linked->id); |
afbd8a72 | 12622 | crtc_state->update_planes |= BIT(linked->id); |
cd49f818 WK |
12623 | drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", |
12624 | linked->base.name, plane->base.name); | |
1f594b20 ML |
12625 | |
12626 | /* Copy parameters to slave plane */ | |
12627 | linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; | |
12628 | linked_state->color_ctl = plane_state->color_ctl; | |
103605e0 | 12629 | linked_state->view = plane_state->view; |
320625aa ID |
12630 | memcpy(linked_state->color_plane, plane_state->color_plane, |
12631 | sizeof(linked_state->color_plane)); | |
1f594b20 ML |
12632 | |
12633 | intel_plane_copy_uapi_to_hw_state(linked_state, plane_state); | |
12634 | linked_state->uapi.src = plane_state->uapi.src; | |
12635 | linked_state->uapi.dst = plane_state->uapi.dst; | |
12636 | ||
12637 | if (icl_is_hdr_plane(dev_priv, plane->id)) { | |
12638 | if (linked->id == PLANE_SPRITE5) | |
12639 | plane_state->cus_ctl |= PLANE_CUS_PLANE_7; | |
12640 | else if (linked->id == PLANE_SPRITE4) | |
12641 | plane_state->cus_ctl |= PLANE_CUS_PLANE_6; | |
99e2d8bc MR |
12642 | else if (linked->id == PLANE_SPRITE3) |
12643 | plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL; | |
12644 | else if (linked->id == PLANE_SPRITE2) | |
12645 | plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL; | |
1f594b20 ML |
12646 | else |
12647 | MISSING_CASE(linked->id); | |
12648 | } | |
1ab554b0 ML |
12649 | } |
12650 | ||
12651 | return 0; | |
12652 | } | |
12653 | ||
638d87c4 VS |
12654 | static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) |
12655 | { | |
2225f3c6 | 12656 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
638d87c4 | 12657 | struct intel_atomic_state *state = |
2225f3c6 | 12658 | to_intel_atomic_state(new_crtc_state->uapi.state); |
638d87c4 VS |
12659 | const struct intel_crtc_state *old_crtc_state = |
12660 | intel_atomic_get_old_crtc_state(state, crtc); | |
12661 | ||
12662 | return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; | |
12663 | } | |
12664 | ||
6dcde047 VS |
12665 | static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) |
12666 | { | |
12667 | const struct drm_display_mode *adjusted_mode = | |
12668 | &crtc_state->hw.adjusted_mode; | |
4003dac1 | 12669 | int linetime_wm; |
6dcde047 VS |
12670 | |
12671 | if (!crtc_state->hw.enable) | |
12672 | return 0; | |
12673 | ||
4003dac1 VS |
12674 | linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
12675 | adjusted_mode->crtc_clock); | |
12676 | ||
12677 | return min(linetime_wm, 0x1ff); | |
6dcde047 VS |
12678 | } |
12679 | ||
28a30b45 VS |
12680 | static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, |
12681 | const struct intel_cdclk_state *cdclk_state) | |
6dcde047 | 12682 | { |
6dcde047 VS |
12683 | const struct drm_display_mode *adjusted_mode = |
12684 | &crtc_state->hw.adjusted_mode; | |
4003dac1 | 12685 | int linetime_wm; |
6dcde047 VS |
12686 | |
12687 | if (!crtc_state->hw.enable) | |
12688 | return 0; | |
12689 | ||
4003dac1 VS |
12690 | linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
12691 | cdclk_state->logical.cdclk); | |
12692 | ||
12693 | return min(linetime_wm, 0x1ff); | |
6dcde047 VS |
12694 | } |
12695 | ||
12696 | static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) | |
12697 | { | |
12698 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
12699 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12700 | const struct drm_display_mode *adjusted_mode = | |
12701 | &crtc_state->hw.adjusted_mode; | |
4003dac1 | 12702 | int linetime_wm; |
6dcde047 VS |
12703 | |
12704 | if (!crtc_state->hw.enable) | |
12705 | return 0; | |
12706 | ||
12707 | linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8, | |
12708 | crtc_state->pixel_rate); | |
12709 | ||
12710 | /* Display WA #1135: BXT:ALL GLK:ALL */ | |
12711 | if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) | |
12712 | linetime_wm /= 2; | |
12713 | ||
4003dac1 | 12714 | return min(linetime_wm, 0x1ff); |
6dcde047 VS |
12715 | } |
12716 | ||
28a30b45 VS |
12717 | static int hsw_compute_linetime_wm(struct intel_atomic_state *state, |
12718 | struct intel_crtc *crtc) | |
12719 | { | |
12720 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12721 | struct intel_crtc_state *crtc_state = | |
12722 | intel_atomic_get_new_crtc_state(state, crtc); | |
12723 | const struct intel_cdclk_state *cdclk_state; | |
12724 | ||
12725 | if (INTEL_GEN(dev_priv) >= 9) | |
12726 | crtc_state->linetime = skl_linetime_wm(crtc_state); | |
12727 | else | |
12728 | crtc_state->linetime = hsw_linetime_wm(crtc_state); | |
12729 | ||
12730 | if (!hsw_crtc_supports_ips(crtc)) | |
12731 | return 0; | |
12732 | ||
12733 | cdclk_state = intel_atomic_get_cdclk_state(state); | |
12734 | if (IS_ERR(cdclk_state)) | |
12735 | return PTR_ERR(cdclk_state); | |
12736 | ||
12737 | crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, | |
12738 | cdclk_state); | |
12739 | ||
12740 | return 0; | |
12741 | } | |
12742 | ||
131d3b1a VS |
12743 | static int intel_crtc_atomic_check(struct intel_atomic_state *state, |
12744 | struct intel_crtc *crtc) | |
6d3a1ce7 | 12745 | { |
2e7f76c1 VS |
12746 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
12747 | struct intel_crtc_state *crtc_state = | |
131d3b1a | 12748 | intel_atomic_get_new_crtc_state(state, crtc); |
2e7f76c1 | 12749 | bool mode_changed = needs_modeset(crtc_state); |
131d3b1a | 12750 | int ret; |
6d3a1ce7 | 12751 | |
440e84a5 | 12752 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) && |
1326a92c | 12753 | mode_changed && !crtc_state->hw.active) |
2e7f76c1 | 12754 | crtc_state->update_wm_post = true; |
eddfcbcd | 12755 | |
1326a92c | 12756 | if (mode_changed && crtc_state->hw.enable && |
ad421372 | 12757 | dev_priv->display.crtc_compute_clock && |
e57291c2 | 12758 | !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { |
2e7f76c1 | 12759 | ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); |
ad421372 ML |
12760 | if (ret) |
12761 | return ret; | |
12762 | } | |
12763 | ||
638d87c4 VS |
12764 | /* |
12765 | * May need to update pipe gamma enable bits | |
12766 | * when C8 planes are getting enabled/disabled. | |
12767 | */ | |
2e7f76c1 | 12768 | if (c8_planes_changed(crtc_state)) |
2225f3c6 | 12769 | crtc_state->uapi.color_mgmt_changed = true; |
638d87c4 | 12770 | |
2e7f76c1 | 12771 | if (mode_changed || crtc_state->update_pipe || |
2225f3c6 | 12772 | crtc_state->uapi.color_mgmt_changed) { |
2e7f76c1 | 12773 | ret = intel_color_check(crtc_state); |
82cf435b LL |
12774 | if (ret) |
12775 | return ret; | |
12776 | } | |
12777 | ||
86c8bbbe | 12778 | if (dev_priv->display.compute_pipe_wm) { |
2e7f76c1 | 12779 | ret = dev_priv->display.compute_pipe_wm(crtc_state); |
ed4a6a7c | 12780 | if (ret) { |
cd49f818 WK |
12781 | drm_dbg_kms(&dev_priv->drm, |
12782 | "Target pipe watermarks are invalid\n"); | |
ed4a6a7c MR |
12783 | return ret; |
12784 | } | |
12785 | } | |
12786 | ||
f255c624 | 12787 | if (dev_priv->display.compute_intermediate_wm) { |
e57291c2 PB |
12788 | if (drm_WARN_ON(&dev_priv->drm, |
12789 | !dev_priv->display.compute_pipe_wm)) | |
ed4a6a7c MR |
12790 | return 0; |
12791 | ||
12792 | /* | |
12793 | * Calculate 'intermediate' watermarks that satisfy both the | |
12794 | * old state and the new state. We can program these | |
12795 | * immediately. | |
12796 | */ | |
2e7f76c1 | 12797 | ret = dev_priv->display.compute_intermediate_wm(crtc_state); |
ed4a6a7c | 12798 | if (ret) { |
cd49f818 WK |
12799 | drm_dbg_kms(&dev_priv->drm, |
12800 | "No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12801 | return ret; |
ed4a6a7c | 12802 | } |
86c8bbbe MR |
12803 | } |
12804 | ||
6315b5d3 | 12805 | if (INTEL_GEN(dev_priv) >= 9) { |
40d42793 | 12806 | if (mode_changed || crtc_state->update_pipe) { |
2e7f76c1 | 12807 | ret = skl_update_scaler_crtc(crtc_state); |
40d42793 VS |
12808 | if (ret) |
12809 | return ret; | |
12810 | } | |
12811 | ||
12812 | ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); | |
28a30b45 VS |
12813 | if (ret) |
12814 | return ret; | |
e435d6e5 ML |
12815 | } |
12816 | ||
28a30b45 VS |
12817 | if (HAS_IPS(dev_priv)) { |
12818 | ret = hsw_compute_ips_config(crtc_state); | |
12819 | if (ret) | |
12820 | return ret; | |
12821 | } | |
12822 | ||
12823 | if (INTEL_GEN(dev_priv) >= 9 || | |
12824 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
12825 | ret = hsw_compute_linetime_wm(state, crtc); | |
12826 | if (ret) | |
12827 | return ret; | |
24f28450 | 12828 | |
6dcde047 VS |
12829 | } |
12830 | ||
6e43e276 JRS |
12831 | if (!mode_changed) |
12832 | intel_psr2_sel_fetch_update(state, crtc); | |
12833 | ||
28a30b45 | 12834 | return 0; |
6d3a1ce7 ML |
12835 | } |
12836 | ||
d29b2f9d ACO |
12837 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12838 | { | |
12839 | struct intel_connector *connector; | |
f9e905ca | 12840 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 12841 | |
f9e905ca DV |
12842 | drm_connector_list_iter_begin(dev, &conn_iter); |
12843 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f | 12844 | if (connector->base.state->crtc) |
ef196b5c | 12845 | drm_connector_put(&connector->base); |
8863dc7f | 12846 | |
d29b2f9d ACO |
12847 | if (connector->base.encoder) { |
12848 | connector->base.state->best_encoder = | |
12849 | connector->base.encoder; | |
12850 | connector->base.state->crtc = | |
12851 | connector->base.encoder->crtc; | |
8863dc7f | 12852 | |
ef196b5c | 12853 | drm_connector_get(&connector->base); |
d29b2f9d ACO |
12854 | } else { |
12855 | connector->base.state->best_encoder = NULL; | |
12856 | connector->base.state->crtc = NULL; | |
12857 | } | |
12858 | } | |
f9e905ca | 12859 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
12860 | } |
12861 | ||
f1a12172 | 12862 | static int |
bcce8d86 VS |
12863 | compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, |
12864 | struct intel_crtc_state *pipe_config) | |
050f7aeb | 12865 | { |
bcce8d86 | 12866 | struct drm_connector *connector = conn_state->connector; |
cd49f818 | 12867 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
bcce8d86 | 12868 | const struct drm_display_info *info = &connector->display_info; |
f1a12172 | 12869 | int bpp; |
050f7aeb | 12870 | |
f1a12172 RS |
12871 | switch (conn_state->max_bpc) { |
12872 | case 6 ... 7: | |
12873 | bpp = 6 * 3; | |
12874 | break; | |
12875 | case 8 ... 9: | |
12876 | bpp = 8 * 3; | |
12877 | break; | |
12878 | case 10 ... 11: | |
12879 | bpp = 10 * 3; | |
12880 | break; | |
d2e3fce9 | 12881 | case 12 ... 16: |
f1a12172 RS |
12882 | bpp = 12 * 3; |
12883 | break; | |
12884 | default: | |
d2e3fce9 | 12885 | MISSING_CASE(conn_state->max_bpc); |
f1a12172 | 12886 | return -EINVAL; |
050f7aeb DV |
12887 | } |
12888 | ||
f1a12172 | 12889 | if (bpp < pipe_config->pipe_bpp) { |
cd49f818 WK |
12890 | drm_dbg_kms(&i915->drm, |
12891 | "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " | |
12892 | "EDID bpp %d, requested bpp %d, max platform bpp %d\n", | |
12893 | connector->base.id, connector->name, | |
12894 | bpp, 3 * info->bpc, | |
12895 | 3 * conn_state->max_requested_bpc, | |
12896 | pipe_config->pipe_bpp); | |
bcce8d86 | 12897 | |
f1a12172 | 12898 | pipe_config->pipe_bpp = bpp; |
050f7aeb | 12899 | } |
bcce8d86 | 12900 | |
f1a12172 | 12901 | return 0; |
050f7aeb DV |
12902 | } |
12903 | ||
4e53c2e0 | 12904 | static int |
050f7aeb | 12905 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12906 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12907 | { |
9beb5fea | 12908 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2225f3c6 | 12909 | struct drm_atomic_state *state = pipe_config->uapi.state; |
da3ced29 ACO |
12910 | struct drm_connector *connector; |
12911 | struct drm_connector_state *connector_state; | |
1486017f | 12912 | int bpp, i; |
4e53c2e0 | 12913 | |
9beb5fea TU |
12914 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12915 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12916 | bpp = 10*3; |
9beb5fea | 12917 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12918 | bpp = 12*3; |
12919 | else | |
12920 | bpp = 8*3; | |
12921 | ||
4e53c2e0 DV |
12922 | pipe_config->pipe_bpp = bpp; |
12923 | ||
bcce8d86 | 12924 | /* Clamp display bpp to connector max bpp */ |
aa5e9b47 | 12925 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
bcce8d86 VS |
12926 | int ret; |
12927 | ||
da3ced29 | 12928 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
12929 | continue; |
12930 | ||
bcce8d86 VS |
12931 | ret = compute_sink_pipe_bpp(connector_state, pipe_config); |
12932 | if (ret) | |
12933 | return ret; | |
4e53c2e0 DV |
12934 | } |
12935 | ||
bcce8d86 | 12936 | return 0; |
4e53c2e0 DV |
12937 | } |
12938 | ||
3dfd8d71 JN |
12939 | static void intel_dump_crtc_timings(struct drm_i915_private *i915, |
12940 | const struct drm_display_mode *mode) | |
644db711 | 12941 | { |
3dfd8d71 JN |
12942 | drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " |
12943 | "type: 0x%x flags: 0x%x\n", | |
12944 | mode->crtc_clock, | |
12945 | mode->crtc_hdisplay, mode->crtc_hsync_start, | |
12946 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12947 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12948 | mode->crtc_vsync_end, mode->crtc_vtotal, | |
12949 | mode->type, mode->flags); | |
644db711 DV |
12950 | } |
12951 | ||
81b55ef1 | 12952 | static void |
926878fb VS |
12953 | intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, |
12954 | const char *id, unsigned int lane_count, | |
12955 | const struct intel_link_m_n *m_n) | |
f6982332 | 12956 | { |
cd49f818 WK |
12957 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
12958 | ||
12959 | drm_dbg_kms(&i915->drm, | |
12960 | "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12961 | id, lane_count, | |
12962 | m_n->gmch_m, m_n->gmch_n, | |
12963 | m_n->link_m, m_n->link_n, m_n->tu); | |
f6982332 TU |
12964 | } |
12965 | ||
69e89032 VS |
12966 | static void |
12967 | intel_dump_infoframe(struct drm_i915_private *dev_priv, | |
12968 | const union hdmi_infoframe *frame) | |
12969 | { | |
bdbf43d7 | 12970 | if (!drm_debug_enabled(DRM_UT_KMS)) |
69e89032 VS |
12971 | return; |
12972 | ||
12973 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); | |
12974 | } | |
12975 | ||
42890250 GM |
12976 | static void |
12977 | intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, | |
12978 | const struct drm_dp_vsc_sdp *vsc) | |
12979 | { | |
12980 | if (!drm_debug_enabled(DRM_UT_KMS)) | |
12981 | return; | |
12982 | ||
12983 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); | |
12984 | } | |
12985 | ||
40b2be41 VS |
12986 | #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x |
12987 | ||
12988 | static const char * const output_type_str[] = { | |
12989 | OUTPUT_TYPE(UNUSED), | |
12990 | OUTPUT_TYPE(ANALOG), | |
12991 | OUTPUT_TYPE(DVO), | |
12992 | OUTPUT_TYPE(SDVO), | |
12993 | OUTPUT_TYPE(LVDS), | |
12994 | OUTPUT_TYPE(TVOUT), | |
12995 | OUTPUT_TYPE(HDMI), | |
12996 | OUTPUT_TYPE(DP), | |
12997 | OUTPUT_TYPE(EDP), | |
12998 | OUTPUT_TYPE(DSI), | |
7e732cac | 12999 | OUTPUT_TYPE(DDI), |
40b2be41 VS |
13000 | OUTPUT_TYPE(DP_MST), |
13001 | }; | |
13002 | ||
13003 | #undef OUTPUT_TYPE | |
13004 | ||
13005 | static void snprintf_output_types(char *buf, size_t len, | |
13006 | unsigned int output_types) | |
13007 | { | |
13008 | char *str = buf; | |
13009 | int i; | |
13010 | ||
13011 | str[0] = '\0'; | |
13012 | ||
13013 | for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { | |
13014 | int r; | |
13015 | ||
13016 | if ((output_types & BIT(i)) == 0) | |
13017 | continue; | |
13018 | ||
13019 | r = snprintf(str, len, "%s%s", | |
13020 | str != buf ? "," : "", output_type_str[i]); | |
13021 | if (r >= len) | |
13022 | break; | |
13023 | str += r; | |
13024 | len -= r; | |
13025 | ||
13026 | output_types &= ~BIT(i); | |
13027 | } | |
13028 | ||
13029 | WARN_ON_ONCE(output_types != 0); | |
13030 | } | |
13031 | ||
d9facae6 SS |
13032 | static const char * const output_format_str[] = { |
13033 | [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid", | |
13034 | [INTEL_OUTPUT_FORMAT_RGB] = "RGB", | |
33b7f3ee | 13035 | [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", |
8c79f844 | 13036 | [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", |
d9facae6 SS |
13037 | }; |
13038 | ||
13039 | static const char *output_formats(enum intel_output_format format) | |
13040 | { | |
33b7f3ee | 13041 | if (format >= ARRAY_SIZE(output_format_str)) |
d9facae6 SS |
13042 | format = INTEL_OUTPUT_FORMAT_INVALID; |
13043 | return output_format_str[format]; | |
13044 | } | |
13045 | ||
10d75f54 VS |
13046 | static void intel_dump_plane_state(const struct intel_plane_state *plane_state) |
13047 | { | |
f90a85e7 | 13048 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
cd49f818 | 13049 | struct drm_i915_private *i915 = to_i915(plane->base.dev); |
7b3cb17a | 13050 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
10d75f54 VS |
13051 | struct drm_format_name_buf format_name; |
13052 | ||
13053 | if (!fb) { | |
cd49f818 WK |
13054 | drm_dbg_kms(&i915->drm, |
13055 | "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", | |
13056 | plane->base.base.id, plane->base.name, | |
13057 | yesno(plane_state->uapi.visible)); | |
10d75f54 VS |
13058 | return; |
13059 | } | |
13060 | ||
cd49f818 WK |
13061 | drm_dbg_kms(&i915->drm, |
13062 | "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n", | |
13063 | plane->base.base.id, plane->base.name, | |
13064 | fb->base.id, fb->width, fb->height, | |
13065 | drm_get_format_name(fb->format->format, &format_name), | |
13066 | yesno(plane_state->uapi.visible)); | |
13067 | drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", | |
13068 | plane_state->hw.rotation, plane_state->scaler_id); | |
f90a85e7 | 13069 | if (plane_state->uapi.visible) |
cd49f818 WK |
13070 | drm_dbg_kms(&i915->drm, |
13071 | "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", | |
13072 | DRM_RECT_FP_ARG(&plane_state->uapi.src), | |
13073 | DRM_RECT_ARG(&plane_state->uapi.dst)); | |
10d75f54 VS |
13074 | } |
13075 | ||
926878fb | 13076 | static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, |
10d75f54 | 13077 | struct intel_atomic_state *state, |
c0b03411 DV |
13078 | const char *context) |
13079 | { | |
2225f3c6 | 13080 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
10d75f54 VS |
13081 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
13082 | const struct intel_plane_state *plane_state; | |
13083 | struct intel_plane *plane; | |
40b2be41 | 13084 | char buf[64]; |
10d75f54 | 13085 | int i; |
6a60cd87 | 13086 | |
cd49f818 WK |
13087 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", |
13088 | crtc->base.base.id, crtc->base.name, | |
13089 | yesno(pipe_config->hw.enable), context); | |
c0b03411 | 13090 | |
1326a92c | 13091 | if (!pipe_config->hw.enable) |
10d75f54 VS |
13092 | goto dump_planes; |
13093 | ||
40b2be41 | 13094 | snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); |
cd49f818 WK |
13095 | drm_dbg_kms(&dev_priv->drm, |
13096 | "active: %s, output_types: %s (0x%x), output format: %s\n", | |
13097 | yesno(pipe_config->hw.active), | |
13098 | buf, pipe_config->output_types, | |
13099 | output_formats(pipe_config->output_format)); | |
d9facae6 | 13100 | |
cd49f818 WK |
13101 | drm_dbg_kms(&dev_priv->drm, |
13102 | "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", | |
13103 | transcoder_name(pipe_config->cpu_transcoder), | |
13104 | pipe_config->pipe_bpp, pipe_config->dither); | |
a4309657 | 13105 | |
05d756b0 VS |
13106 | drm_dbg_kms(&dev_priv->drm, |
13107 | "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", | |
13108 | transcoder_name(pipe_config->master_transcoder), | |
13109 | pipe_config->sync_mode_slaves_mask); | |
13110 | ||
a4309657 TU |
13111 | if (pipe_config->has_pch_encoder) |
13112 | intel_dump_m_n_config(pipe_config, "fdi", | |
13113 | pipe_config->fdi_lanes, | |
13114 | &pipe_config->fdi_m_n); | |
f6982332 TU |
13115 | |
13116 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
13117 | intel_dump_m_n_config(pipe_config, "dp m_n", |
13118 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
13119 | if (pipe_config->has_drrs) |
13120 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
13121 | pipe_config->lane_count, | |
13122 | &pipe_config->dp_m2_n2); | |
f6982332 | 13123 | } |
b95af8be | 13124 | |
cd49f818 WK |
13125 | drm_dbg_kms(&dev_priv->drm, |
13126 | "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", | |
13127 | pipe_config->has_audio, pipe_config->has_infoframe, | |
13128 | pipe_config->infoframes.enable); | |
69e89032 VS |
13129 | |
13130 | if (pipe_config->infoframes.enable & | |
13131 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) | |
cd49f818 WK |
13132 | drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", |
13133 | pipe_config->infoframes.gcp); | |
69e89032 VS |
13134 | if (pipe_config->infoframes.enable & |
13135 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) | |
13136 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); | |
13137 | if (pipe_config->infoframes.enable & | |
13138 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) | |
13139 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); | |
13140 | if (pipe_config->infoframes.enable & | |
13141 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) | |
13142 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); | |
bfbeba29 GM |
13143 | if (pipe_config->infoframes.enable & |
13144 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) | |
13145 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); | |
e274fb32 GM |
13146 | if (pipe_config->infoframes.enable & |
13147 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) | |
13148 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); | |
42890250 GM |
13149 | if (pipe_config->infoframes.enable & |
13150 | intel_hdmi_infoframe_enable(DP_SDP_VSC)) | |
13151 | intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); | |
69e89032 | 13152 | |
cd49f818 | 13153 | drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); |
1326a92c | 13154 | drm_mode_debug_printmodeline(&pipe_config->hw.mode); |
cd49f818 | 13155 | drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); |
1326a92c | 13156 | drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); |
3dfd8d71 | 13157 | intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); |
cd49f818 WK |
13158 | drm_dbg_kms(&dev_priv->drm, |
13159 | "port clock: %d, pipe src size: %dx%d, pixel rate %d\n", | |
13160 | pipe_config->port_clock, | |
13161 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, | |
13162 | pipe_config->pixel_rate); | |
dd2f616d | 13163 | |
6dcde047 VS |
13164 | drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", |
13165 | pipe_config->linetime, pipe_config->ips_linetime); | |
13166 | ||
dd2f616d | 13167 | if (INTEL_GEN(dev_priv) >= 9) |
cd49f818 WK |
13168 | drm_dbg_kms(&dev_priv->drm, |
13169 | "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
13170 | crtc->num_scalers, | |
13171 | pipe_config->scaler_state.scaler_users, | |
13172 | pipe_config->scaler_state.scaler_id); | |
a74f8375 | 13173 | |
b2ae318a | 13174 | if (HAS_GMCH(dev_priv)) |
cd49f818 WK |
13175 | drm_dbg_kms(&dev_priv->drm, |
13176 | "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
13177 | pipe_config->gmch_pfit.control, | |
13178 | pipe_config->gmch_pfit.pgm_ratios, | |
13179 | pipe_config->gmch_pfit.lvds_border_bits); | |
a74f8375 | 13180 | else |
cd49f818 | 13181 | drm_dbg_kms(&dev_priv->drm, |
35dd95b4 VS |
13182 | "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", |
13183 | DRM_RECT_ARG(&pipe_config->pch_pfit.dst), | |
cd49f818 WK |
13184 | enableddisabled(pipe_config->pch_pfit.enabled), |
13185 | yesno(pipe_config->pch_pfit.force_thru)); | |
a74f8375 | 13186 | |
cd49f818 WK |
13187 | drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n", |
13188 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 13189 | |
f50b79f0 | 13190 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 13191 | |
b1a4383d | 13192 | if (IS_CHERRYVIEW(dev_priv)) |
cd49f818 WK |
13193 | drm_dbg_kms(&dev_priv->drm, |
13194 | "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", | |
13195 | pipe_config->cgm_mode, pipe_config->gamma_mode, | |
13196 | pipe_config->gamma_enable, pipe_config->csc_enable); | |
b1a4383d | 13197 | else |
cd49f818 WK |
13198 | drm_dbg_kms(&dev_priv->drm, |
13199 | "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", | |
13200 | pipe_config->csc_mode, pipe_config->gamma_mode, | |
13201 | pipe_config->gamma_enable, pipe_config->csc_enable); | |
b1a4383d | 13202 | |
cd49f818 WK |
13203 | drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", |
13204 | transcoder_name(pipe_config->mst_master_transcoder)); | |
6671c367 | 13205 | |
10d75f54 VS |
13206 | dump_planes: |
13207 | if (!state) | |
13208 | return; | |
6a60cd87 | 13209 | |
10d75f54 VS |
13210 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
13211 | if (plane->pipe == crtc->pipe) | |
13212 | intel_dump_plane_state(plane_state); | |
6a60cd87 | 13213 | } |
c0b03411 DV |
13214 | } |
13215 | ||
85829eb5 | 13216 | static bool check_digital_port_conflicts(struct intel_atomic_state *state) |
00f0b378 | 13217 | { |
85829eb5 | 13218 | struct drm_device *dev = state->base.dev; |
da3ced29 | 13219 | struct drm_connector *connector; |
2fd96b41 | 13220 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 13221 | unsigned int used_ports = 0; |
477321e0 | 13222 | unsigned int used_mst_ports = 0; |
bd67a8c1 | 13223 | bool ret = true; |
00f0b378 | 13224 | |
1d5a95b5 VS |
13225 | /* |
13226 | * We're going to peek into connector->state, | |
13227 | * hence connection_mutex must be held. | |
13228 | */ | |
13229 | drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); | |
13230 | ||
00f0b378 VS |
13231 | /* |
13232 | * Walk the connector list instead of the encoder | |
13233 | * list to detect the problem on ddi platforms | |
13234 | * where there's just one encoder per digital port. | |
13235 | */ | |
2fd96b41 GP |
13236 | drm_connector_list_iter_begin(dev, &conn_iter); |
13237 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
13238 | struct drm_connector_state *connector_state; |
13239 | struct intel_encoder *encoder; | |
13240 | ||
85829eb5 VS |
13241 | connector_state = |
13242 | drm_atomic_get_new_connector_state(&state->base, | |
13243 | connector); | |
0bff4858 VS |
13244 | if (!connector_state) |
13245 | connector_state = connector->state; | |
13246 | ||
5448a00d | 13247 | if (!connector_state->best_encoder) |
00f0b378 VS |
13248 | continue; |
13249 | ||
5448a00d ACO |
13250 | encoder = to_intel_encoder(connector_state->best_encoder); |
13251 | ||
e57291c2 | 13252 | drm_WARN_ON(dev, !connector_state->crtc); |
00f0b378 VS |
13253 | |
13254 | switch (encoder->type) { | |
7e732cac | 13255 | case INTEL_OUTPUT_DDI: |
e57291c2 | 13256 | if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) |
00f0b378 | 13257 | break; |
df561f66 | 13258 | fallthrough; |
cca0502b | 13259 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
13260 | case INTEL_OUTPUT_HDMI: |
13261 | case INTEL_OUTPUT_EDP: | |
00f0b378 | 13262 | /* the same port mustn't appear more than once */ |
2713eb41 | 13263 | if (used_ports & BIT(encoder->port)) |
bd67a8c1 | 13264 | ret = false; |
00f0b378 | 13265 | |
2713eb41 | 13266 | used_ports |= BIT(encoder->port); |
477321e0 VS |
13267 | break; |
13268 | case INTEL_OUTPUT_DP_MST: | |
13269 | used_mst_ports |= | |
8f4f2797 | 13270 | 1 << encoder->port; |
477321e0 | 13271 | break; |
00f0b378 VS |
13272 | default: |
13273 | break; | |
13274 | } | |
13275 | } | |
2fd96b41 | 13276 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 13277 | |
477321e0 VS |
13278 | /* can't mix MST and SST/HDMI on the same port */ |
13279 | if (used_ports & used_mst_ports) | |
13280 | return false; | |
13281 | ||
bd67a8c1 | 13282 | return ret; |
00f0b378 VS |
13283 | } |
13284 | ||
58d124ea ML |
13285 | static void |
13286 | intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state) | |
13287 | { | |
13288 | intel_crtc_copy_color_blobs(crtc_state); | |
13289 | } | |
13290 | ||
13291 | static void | |
13292 | intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state) | |
13293 | { | |
13294 | crtc_state->hw.enable = crtc_state->uapi.enable; | |
13295 | crtc_state->hw.active = crtc_state->uapi.active; | |
13296 | crtc_state->hw.mode = crtc_state->uapi.mode; | |
13297 | crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode; | |
13298 | intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state); | |
13299 | } | |
13300 | ||
13301 | static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) | |
13302 | { | |
13303 | crtc_state->uapi.enable = crtc_state->hw.enable; | |
13304 | crtc_state->uapi.active = crtc_state->hw.active; | |
ce04ecd9 PB |
13305 | drm_WARN_ON(crtc_state->uapi.crtc->dev, |
13306 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); | |
58d124ea ML |
13307 | |
13308 | crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; | |
13309 | ||
13310 | /* copy color blobs to uapi */ | |
13311 | drm_property_replace_blob(&crtc_state->uapi.degamma_lut, | |
13312 | crtc_state->hw.degamma_lut); | |
13313 | drm_property_replace_blob(&crtc_state->uapi.gamma_lut, | |
13314 | crtc_state->hw.gamma_lut); | |
13315 | drm_property_replace_blob(&crtc_state->uapi.ctm, | |
13316 | crtc_state->hw.ctm); | |
13317 | } | |
13318 | ||
f81b845f | 13319 | static int |
58d124ea | 13320 | intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state) |
83a57153 | 13321 | { |
216383e9 VS |
13322 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
13323 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
f81b845f CW |
13324 | struct intel_crtc_state *saved_state; |
13325 | ||
216383e9 | 13326 | saved_state = intel_crtc_state_alloc(crtc); |
f81b845f CW |
13327 | if (!saved_state) |
13328 | return -ENOMEM; | |
83a57153 | 13329 | |
58d124ea ML |
13330 | /* free the old crtc_state->hw members */ |
13331 | intel_crtc_free_hw_state(crtc_state); | |
13332 | ||
7546a384 ACO |
13333 | /* FIXME: before the switch to atomic started, a new pipe_config was |
13334 | * kzalloc'd. Code that depends on any field being zero should be | |
13335 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
13336 | * only fields that are know to not cause problems are preserved. */ | |
13337 | ||
58d124ea | 13338 | saved_state->uapi = crtc_state->uapi; |
f81b845f CW |
13339 | saved_state->scaler_state = crtc_state->scaler_state; |
13340 | saved_state->shared_dpll = crtc_state->shared_dpll; | |
13341 | saved_state->dpll_hw_state = crtc_state->dpll_hw_state; | |
eea72c4c ID |
13342 | memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, |
13343 | sizeof(saved_state->icl_port_dplls)); | |
a8ebf607 | 13344 | saved_state->crc_enabled = crtc_state->crc_enabled; |
04548cba VS |
13345 | if (IS_G4X(dev_priv) || |
13346 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
f81b845f | 13347 | saved_state->wm = crtc_state->wm; |
4978cc93 | 13348 | |
58d124ea | 13349 | memcpy(crtc_state, saved_state, sizeof(*crtc_state)); |
f81b845f | 13350 | kfree(saved_state); |
58d124ea ML |
13351 | |
13352 | intel_crtc_copy_uapi_to_hw_state(crtc_state); | |
13353 | ||
f81b845f | 13354 | return 0; |
83a57153 ACO |
13355 | } |
13356 | ||
548ee15b | 13357 | static int |
f239b799 | 13358 | intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) |
ee7b9f93 | 13359 | { |
2225f3c6 ML |
13360 | struct drm_crtc *crtc = pipe_config->uapi.crtc; |
13361 | struct drm_atomic_state *state = pipe_config->uapi.state; | |
cd49f818 | 13362 | struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); |
da3ced29 | 13363 | struct drm_connector *connector; |
0b901879 | 13364 | struct drm_connector_state *connector_state; |
b50a1aa6 | 13365 | int base_bpp, ret, i; |
e29c22c0 | 13366 | bool retry = true; |
ee7b9f93 | 13367 | |
e143a21c DV |
13368 | pipe_config->cpu_transcoder = |
13369 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 13370 | |
2960bc9c ID |
13371 | /* |
13372 | * Sanitize sync polarity flags based on requested ones. If neither | |
13373 | * positive or negative polarity is requested, treat this as meaning | |
13374 | * negative polarity. | |
13375 | */ | |
1326a92c | 13376 | if (!(pipe_config->hw.adjusted_mode.flags & |
2960bc9c | 13377 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
1326a92c | 13378 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13379 | |
1326a92c | 13380 | if (!(pipe_config->hw.adjusted_mode.flags & |
2960bc9c | 13381 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
1326a92c | 13382 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13383 | |
bcce8d86 VS |
13384 | ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13385 | pipe_config); | |
13386 | if (ret) | |
13387 | return ret; | |
13388 | ||
13389 | base_bpp = pipe_config->pipe_bpp; | |
4e53c2e0 | 13390 | |
e41a56be VS |
13391 | /* |
13392 | * Determine the real pipe dimensions. Note that stereo modes can | |
13393 | * increase the actual pipe size due to the frame doubling and | |
13394 | * insertion of additional space for blanks between the frame. This | |
13395 | * is stored in the crtc timings. We use the requested mode to do this | |
13396 | * computation to clearly distinguish it from the adjusted mode, which | |
13397 | * can be changed by the connectors in the below retry loop. | |
13398 | */ | |
1326a92c | 13399 | drm_mode_get_hv_timing(&pipe_config->hw.mode, |
ecb7e16b GP |
13400 | &pipe_config->pipe_src_w, |
13401 | &pipe_config->pipe_src_h); | |
e41a56be | 13402 | |
aa5e9b47 | 13403 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
691313ea VS |
13404 | struct intel_encoder *encoder = |
13405 | to_intel_encoder(connector_state->best_encoder); | |
13406 | ||
253c84c8 VS |
13407 | if (connector_state->crtc != crtc) |
13408 | continue; | |
13409 | ||
e25148d0 | 13410 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
cd49f818 WK |
13411 | drm_dbg_kms(&i915->drm, |
13412 | "rejecting invalid cloning configuration\n"); | |
d26592c6 | 13413 | return -EINVAL; |
e25148d0 VS |
13414 | } |
13415 | ||
253c84c8 VS |
13416 | /* |
13417 | * Determine output_types before calling the .compute_config() | |
13418 | * hooks so that the hooks can use this information safely. | |
13419 | */ | |
7e732cac VS |
13420 | if (encoder->compute_output_type) |
13421 | pipe_config->output_types |= | |
13422 | BIT(encoder->compute_output_type(encoder, pipe_config, | |
13423 | connector_state)); | |
13424 | else | |
13425 | pipe_config->output_types |= BIT(encoder->type); | |
253c84c8 VS |
13426 | } |
13427 | ||
e29c22c0 | 13428 | encoder_retry: |
ef1b460d | 13429 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13430 | pipe_config->port_clock = 0; |
ef1b460d | 13431 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13432 | |
135c81b8 | 13433 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
1326a92c | 13434 | drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, |
2d112de7 | 13435 | CRTC_STEREO_DOUBLE); |
135c81b8 | 13436 | |
7758a113 DV |
13437 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13438 | * adjust it according to limitations or connector properties, and also | |
13439 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13440 | */ |
aa5e9b47 | 13441 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
691313ea VS |
13442 | struct intel_encoder *encoder = |
13443 | to_intel_encoder(connector_state->best_encoder); | |
13444 | ||
0b901879 | 13445 | if (connector_state->crtc != crtc) |
7758a113 | 13446 | continue; |
7ae89233 | 13447 | |
204474a6 LP |
13448 | ret = encoder->compute_config(encoder, pipe_config, |
13449 | connector_state); | |
13450 | if (ret < 0) { | |
13451 | if (ret != -EDEADLK) | |
cd49f818 WK |
13452 | drm_dbg_kms(&i915->drm, |
13453 | "Encoder config failure: %d\n", | |
13454 | ret); | |
204474a6 | 13455 | return ret; |
7758a113 | 13456 | } |
ee7b9f93 | 13457 | } |
47f1c6c9 | 13458 | |
ff9a6750 DV |
13459 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13460 | * done afterwards in case the encoder adjusts the mode. */ | |
13461 | if (!pipe_config->port_clock) | |
1326a92c | 13462 | pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock |
241bfc38 | 13463 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13464 | |
a43f6e0f | 13465 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
8e2b4dff | 13466 | if (ret == -EDEADLK) |
d26592c6 | 13467 | return ret; |
e29c22c0 | 13468 | if (ret < 0) { |
cd49f818 | 13469 | drm_dbg_kms(&i915->drm, "CRTC fixup failed\n"); |
d26592c6 | 13470 | return ret; |
ee7b9f93 | 13471 | } |
e29c22c0 DV |
13472 | |
13473 | if (ret == RETRY) { | |
e57291c2 PB |
13474 | if (drm_WARN(&i915->drm, !retry, |
13475 | "loop in pipe configuration computation\n")) | |
d26592c6 | 13476 | return -EINVAL; |
e29c22c0 | 13477 | |
cd49f818 | 13478 | drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); |
e29c22c0 DV |
13479 | retry = false; |
13480 | goto encoder_retry; | |
13481 | } | |
13482 | ||
e8fa4270 | 13483 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
13484 | * only enable it on 6bpc panels and when its not a compliance |
13485 | * test requesting 6bpc video pattern. | |
13486 | */ | |
13487 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
13488 | !pipe_config->dither_force_disable; | |
cd49f818 WK |
13489 | drm_dbg_kms(&i915->drm, |
13490 | "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", | |
13491 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
4e53c2e0 | 13492 | |
d26592c6 | 13493 | return 0; |
ee7b9f93 | 13494 | } |
47f1c6c9 | 13495 | |
f2801424 VS |
13496 | static int |
13497 | intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) | |
13498 | { | |
13499 | struct intel_atomic_state *state = | |
13500 | to_intel_atomic_state(crtc_state->uapi.state); | |
13501 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
13502 | struct drm_connector_state *conn_state; | |
13503 | struct drm_connector *connector; | |
13504 | int i; | |
13505 | ||
13506 | for_each_new_connector_in_state(&state->base, connector, | |
13507 | conn_state, i) { | |
13508 | struct intel_encoder *encoder = | |
13509 | to_intel_encoder(conn_state->best_encoder); | |
13510 | int ret; | |
13511 | ||
13512 | if (conn_state->crtc != &crtc->base || | |
13513 | !encoder->compute_config_late) | |
13514 | continue; | |
13515 | ||
13516 | ret = encoder->compute_config_late(encoder, crtc_state, | |
13517 | conn_state); | |
13518 | if (ret) | |
13519 | return ret; | |
13520 | } | |
13521 | ||
13522 | return 0; | |
13523 | } | |
13524 | ||
2c1c5525 | 13525 | bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13526 | { |
3bd26263 | 13527 | int diff; |
f1f644dc JB |
13528 | |
13529 | if (clock1 == clock2) | |
13530 | return true; | |
13531 | ||
13532 | if (!clock1 || !clock2) | |
13533 | return false; | |
13534 | ||
13535 | diff = abs(clock1 - clock2); | |
13536 | ||
13537 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13538 | return true; | |
13539 | ||
13540 | return false; | |
13541 | } | |
13542 | ||
cfb23ed6 ML |
13543 | static bool |
13544 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13545 | unsigned int m2, unsigned int n2, | |
13546 | bool exact) | |
13547 | { | |
13548 | if (m == m2 && n == n2) | |
13549 | return true; | |
13550 | ||
13551 | if (exact || !m || !n || !m2 || !n2) | |
13552 | return false; | |
13553 | ||
13554 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13555 | ||
31d10b57 ML |
13556 | if (n > n2) { |
13557 | while (n > n2) { | |
cfb23ed6 ML |
13558 | m2 <<= 1; |
13559 | n2 <<= 1; | |
13560 | } | |
31d10b57 ML |
13561 | } else if (n < n2) { |
13562 | while (n < n2) { | |
cfb23ed6 ML |
13563 | m <<= 1; |
13564 | n <<= 1; | |
13565 | } | |
13566 | } | |
13567 | ||
31d10b57 ML |
13568 | if (n != n2) |
13569 | return false; | |
13570 | ||
13571 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13572 | } |
13573 | ||
13574 | static bool | |
13575 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
b124ea43 VS |
13576 | const struct intel_link_m_n *m2_n2, |
13577 | bool exact) | |
13578 | { | |
13579 | return m_n->tu == m2_n2->tu && | |
13580 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13581 | m2_n2->gmch_m, m2_n2->gmch_n, exact) && | |
13582 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13583 | m2_n2->link_m, m2_n2->link_n, exact); | |
cfb23ed6 ML |
13584 | } |
13585 | ||
6454cb9f VS |
13586 | static bool |
13587 | intel_compare_infoframe(const union hdmi_infoframe *a, | |
13588 | const union hdmi_infoframe *b) | |
13589 | { | |
13590 | return memcmp(a, b, sizeof(*a)) == 0; | |
13591 | } | |
13592 | ||
2c3928e4 GM |
13593 | static bool |
13594 | intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, | |
13595 | const struct drm_dp_vsc_sdp *b) | |
13596 | { | |
13597 | return memcmp(a, b, sizeof(*a)) == 0; | |
13598 | } | |
13599 | ||
6454cb9f | 13600 | static void |
dde84833 VS |
13601 | pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, |
13602 | bool fastset, const char *name, | |
13603 | const union hdmi_infoframe *a, | |
13604 | const union hdmi_infoframe *b) | |
6454cb9f | 13605 | { |
dde84833 | 13606 | if (fastset) { |
bdbf43d7 | 13607 | if (!drm_debug_enabled(DRM_UT_KMS)) |
6454cb9f VS |
13608 | return; |
13609 | ||
cd49f818 WK |
13610 | drm_dbg_kms(&dev_priv->drm, |
13611 | "fastset mismatch in %s infoframe\n", name); | |
13612 | drm_dbg_kms(&dev_priv->drm, "expected:\n"); | |
6454cb9f | 13613 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); |
cd49f818 | 13614 | drm_dbg_kms(&dev_priv->drm, "found:\n"); |
6454cb9f VS |
13615 | hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); |
13616 | } else { | |
cd49f818 WK |
13617 | drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); |
13618 | drm_err(&dev_priv->drm, "expected:\n"); | |
6454cb9f | 13619 | hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); |
cd49f818 | 13620 | drm_err(&dev_priv->drm, "found:\n"); |
6454cb9f VS |
13621 | hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); |
13622 | } | |
13623 | } | |
13624 | ||
2c3928e4 GM |
13625 | static void |
13626 | pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, | |
13627 | bool fastset, const char *name, | |
13628 | const struct drm_dp_vsc_sdp *a, | |
13629 | const struct drm_dp_vsc_sdp *b) | |
13630 | { | |
13631 | if (fastset) { | |
13632 | if (!drm_debug_enabled(DRM_UT_KMS)) | |
13633 | return; | |
13634 | ||
13635 | drm_dbg_kms(&dev_priv->drm, | |
13636 | "fastset mismatch in %s dp sdp\n", name); | |
13637 | drm_dbg_kms(&dev_priv->drm, "expected:\n"); | |
13638 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); | |
13639 | drm_dbg_kms(&dev_priv->drm, "found:\n"); | |
13640 | drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); | |
13641 | } else { | |
13642 | drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); | |
13643 | drm_err(&dev_priv->drm, "expected:\n"); | |
13644 | drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); | |
13645 | drm_err(&dev_priv->drm, "found:\n"); | |
13646 | drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); | |
13647 | } | |
13648 | } | |
13649 | ||
73cefd90 LDM |
13650 | static void __printf(4, 5) |
13651 | pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, | |
13652 | const char *name, const char *format, ...) | |
4e8048f8 | 13653 | { |
cd49f818 | 13654 | struct drm_i915_private *i915 = to_i915(crtc->base.dev); |
4e8048f8 TU |
13655 | struct va_format vaf; |
13656 | va_list args; | |
13657 | ||
4e8048f8 TU |
13658 | va_start(args, format); |
13659 | vaf.fmt = format; | |
13660 | vaf.va = &args; | |
13661 | ||
dde84833 | 13662 | if (fastset) |
cd49f818 WK |
13663 | drm_dbg_kms(&i915->drm, |
13664 | "[CRTC:%d:%s] fastset mismatch in %s %pV\n", | |
13665 | crtc->base.base.id, crtc->base.name, name, &vaf); | |
99a95487 | 13666 | else |
cd49f818 WK |
13667 | drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", |
13668 | crtc->base.base.id, crtc->base.name, name, &vaf); | |
4e8048f8 TU |
13669 | |
13670 | va_end(args); | |
13671 | } | |
13672 | ||
3d6535cb HG |
13673 | static bool fastboot_enabled(struct drm_i915_private *dev_priv) |
13674 | { | |
8a25c4be JN |
13675 | if (dev_priv->params.fastboot != -1) |
13676 | return dev_priv->params.fastboot; | |
3d6535cb HG |
13677 | |
13678 | /* Enable fastboot by default on Skylake and newer */ | |
7360c9f6 HG |
13679 | if (INTEL_GEN(dev_priv) >= 9) |
13680 | return true; | |
13681 | ||
13682 | /* Enable fastboot by default on VLV and CHV */ | |
13683 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13684 | return true; | |
13685 | ||
13686 | /* Disabled by default on all others */ | |
13687 | return false; | |
3d6535cb HG |
13688 | } |
13689 | ||
0e8ffe1b | 13690 | static bool |
b124ea43 VS |
13691 | intel_pipe_config_compare(const struct intel_crtc_state *current_config, |
13692 | const struct intel_crtc_state *pipe_config, | |
dde84833 | 13693 | bool fastset) |
0e8ffe1b | 13694 | { |
2225f3c6 ML |
13695 | struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); |
13696 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); | |
cfb23ed6 | 13697 | bool ret = true; |
7e764059 | 13698 | u32 bp_gamma = 0; |
dde84833 | 13699 | bool fixup_inherited = fastset && |
a227569d | 13700 | current_config->inherited && !pipe_config->inherited; |
cfb23ed6 | 13701 | |
3d6535cb | 13702 | if (fixup_inherited && !fastboot_enabled(dev_priv)) { |
cd49f818 WK |
13703 | drm_dbg_kms(&dev_priv->drm, |
13704 | "initial modeset and fastboot not set\n"); | |
d19f958d ML |
13705 | ret = false; |
13706 | } | |
13707 | ||
eadd2721 | 13708 | #define PIPE_CONF_CHECK_X(name) do { \ |
66e985c0 | 13709 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13710 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13711 | "(expected 0x%08x, found 0x%08x)", \ |
dde84833 VS |
13712 | current_config->name, \ |
13713 | pipe_config->name); \ | |
cfb23ed6 | 13714 | ret = false; \ |
eadd2721 VS |
13715 | } \ |
13716 | } while (0) | |
66e985c0 | 13717 | |
eadd2721 | 13718 | #define PIPE_CONF_CHECK_I(name) do { \ |
08a24034 | 13719 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13720 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13721 | "(expected %i, found %i)", \ |
dde84833 VS |
13722 | current_config->name, \ |
13723 | pipe_config->name); \ | |
cfb23ed6 | 13724 | ret = false; \ |
eadd2721 VS |
13725 | } \ |
13726 | } while (0) | |
cfb23ed6 | 13727 | |
eadd2721 | 13728 | #define PIPE_CONF_CHECK_BOOL(name) do { \ |
d640bf79 | 13729 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13730 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13731 | "(expected %s, found %s)", \ |
dde84833 VS |
13732 | yesno(current_config->name), \ |
13733 | yesno(pipe_config->name)); \ | |
d640bf79 | 13734 | ret = false; \ |
eadd2721 VS |
13735 | } \ |
13736 | } while (0) | |
d640bf79 | 13737 | |
4493e098 ML |
13738 | /* |
13739 | * Checks state where we only read out the enabling, but not the entire | |
13740 | * state itself (like full infoframes or ELD for audio). These states | |
13741 | * require a full modeset on bootup to fix up. | |
13742 | */ | |
eadd2721 | 13743 | #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ |
4493e098 ML |
13744 | if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ |
13745 | PIPE_CONF_CHECK_BOOL(name); \ | |
13746 | } else { \ | |
73cefd90 | 13747 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13748 | "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ |
dde84833 VS |
13749 | yesno(current_config->name), \ |
13750 | yesno(pipe_config->name)); \ | |
4493e098 | 13751 | ret = false; \ |
eadd2721 VS |
13752 | } \ |
13753 | } while (0) | |
4493e098 | 13754 | |
eadd2721 | 13755 | #define PIPE_CONF_CHECK_P(name) do { \ |
8106ddbd | 13756 | if (current_config->name != pipe_config->name) { \ |
73cefd90 | 13757 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13758 | "(expected %p, found %p)", \ |
dde84833 VS |
13759 | current_config->name, \ |
13760 | pipe_config->name); \ | |
8106ddbd | 13761 | ret = false; \ |
eadd2721 VS |
13762 | } \ |
13763 | } while (0) | |
8106ddbd | 13764 | |
eadd2721 | 13765 | #define PIPE_CONF_CHECK_M_N(name) do { \ |
cfb23ed6 ML |
13766 | if (!intel_compare_link_m_n(¤t_config->name, \ |
13767 | &pipe_config->name,\ | |
dde84833 | 13768 | !fastset)) { \ |
73cefd90 | 13769 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
dde84833 | 13770 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
cbd9b9f2 | 13771 | "found tu %i, gmch %i/%i link %i/%i)", \ |
dde84833 VS |
13772 | current_config->name.tu, \ |
13773 | current_config->name.gmch_m, \ | |
13774 | current_config->name.gmch_n, \ | |
13775 | current_config->name.link_m, \ | |
13776 | current_config->name.link_n, \ | |
13777 | pipe_config->name.tu, \ | |
13778 | pipe_config->name.gmch_m, \ | |
13779 | pipe_config->name.gmch_n, \ | |
13780 | pipe_config->name.link_m, \ | |
13781 | pipe_config->name.link_n); \ | |
cfb23ed6 | 13782 | ret = false; \ |
eadd2721 VS |
13783 | } \ |
13784 | } while (0) | |
cfb23ed6 | 13785 | |
55c561a7 DV |
13786 | /* This is required for BDW+ where there is only one set of registers for |
13787 | * switching between high and low RR. | |
13788 | * This macro can be used whenever a comparison has to be made between one | |
13789 | * hw state and multiple sw state variables. | |
13790 | */ | |
eadd2721 | 13791 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ |
cfb23ed6 | 13792 | if (!intel_compare_link_m_n(¤t_config->name, \ |
dde84833 | 13793 | &pipe_config->name, !fastset) && \ |
cfb23ed6 | 13794 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
dde84833 | 13795 | &pipe_config->name, !fastset)) { \ |
73cefd90 | 13796 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
dde84833 VS |
13797 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
13798 | "or tu %i gmch %i/%i link %i/%i, " \ | |
cbd9b9f2 | 13799 | "found tu %i, gmch %i/%i link %i/%i)", \ |
dde84833 VS |
13800 | current_config->name.tu, \ |
13801 | current_config->name.gmch_m, \ | |
13802 | current_config->name.gmch_n, \ | |
13803 | current_config->name.link_m, \ | |
13804 | current_config->name.link_n, \ | |
13805 | current_config->alt_name.tu, \ | |
13806 | current_config->alt_name.gmch_m, \ | |
13807 | current_config->alt_name.gmch_n, \ | |
13808 | current_config->alt_name.link_m, \ | |
13809 | current_config->alt_name.link_n, \ | |
13810 | pipe_config->name.tu, \ | |
13811 | pipe_config->name.gmch_m, \ | |
13812 | pipe_config->name.gmch_n, \ | |
13813 | pipe_config->name.link_m, \ | |
13814 | pipe_config->name.link_n); \ | |
cfb23ed6 | 13815 | ret = false; \ |
eadd2721 VS |
13816 | } \ |
13817 | } while (0) | |
88adfff1 | 13818 | |
eadd2721 | 13819 | #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ |
1bd1bd80 | 13820 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
73cefd90 | 13821 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13822 | "(%x) (expected %i, found %i)", \ |
dde84833 VS |
13823 | (mask), \ |
13824 | current_config->name & (mask), \ | |
13825 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13826 | ret = false; \ |
eadd2721 VS |
13827 | } \ |
13828 | } while (0) | |
1bd1bd80 | 13829 | |
eadd2721 | 13830 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ |
5e550656 | 13831 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
73cefd90 | 13832 | pipe_config_mismatch(fastset, crtc, __stringify(name), \ |
cbd9b9f2 | 13833 | "(expected %i, found %i)", \ |
dde84833 VS |
13834 | current_config->name, \ |
13835 | pipe_config->name); \ | |
cfb23ed6 | 13836 | ret = false; \ |
eadd2721 VS |
13837 | } \ |
13838 | } while (0) | |
5e550656 | 13839 | |
6454cb9f VS |
13840 | #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ |
13841 | if (!intel_compare_infoframe(¤t_config->infoframes.name, \ | |
13842 | &pipe_config->infoframes.name)) { \ | |
dde84833 VS |
13843 | pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ |
13844 | ¤t_config->infoframes.name, \ | |
13845 | &pipe_config->infoframes.name); \ | |
6454cb9f VS |
13846 | ret = false; \ |
13847 | } \ | |
13848 | } while (0) | |
13849 | ||
2c3928e4 GM |
13850 | #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ |
13851 | if (!current_config->has_psr && !pipe_config->has_psr && \ | |
13852 | !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ | |
13853 | &pipe_config->infoframes.name)) { \ | |
13854 | pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ | |
13855 | ¤t_config->infoframes.name, \ | |
13856 | &pipe_config->infoframes.name); \ | |
13857 | ret = false; \ | |
13858 | } \ | |
13859 | } while (0) | |
13860 | ||
7e764059 SS |
13861 | #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ |
13862 | if (current_config->name1 != pipe_config->name1) { \ | |
73cefd90 | 13863 | pipe_config_mismatch(fastset, crtc, __stringify(name1), \ |
cbd9b9f2 | 13864 | "(expected %i, found %i, won't compare lut values)", \ |
7e764059 SS |
13865 | current_config->name1, \ |
13866 | pipe_config->name1); \ | |
13867 | ret = false;\ | |
13868 | } else { \ | |
13869 | if (!intel_color_lut_equal(current_config->name2, \ | |
13870 | pipe_config->name2, pipe_config->name1, \ | |
13871 | bit_precision)) { \ | |
73cefd90 | 13872 | pipe_config_mismatch(fastset, crtc, __stringify(name2), \ |
cbd9b9f2 | 13873 | "hw_state doesn't match sw_state"); \ |
7e764059 SS |
13874 | ret = false; \ |
13875 | } \ | |
13876 | } \ | |
13877 | } while (0) | |
13878 | ||
6454cb9f | 13879 | #define PIPE_CONF_QUIRK(quirk) \ |
bb760063 DV |
13880 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
13881 | ||
eccb140b DV |
13882 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13883 | ||
d640bf79 | 13884 | PIPE_CONF_CHECK_BOOL(has_pch_encoder); |
08a24034 | 13885 | PIPE_CONF_CHECK_I(fdi_lanes); |
cfb23ed6 | 13886 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13887 | |
90a6b7b0 | 13888 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13889 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 13890 | |
6315b5d3 | 13891 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
13892 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13893 | ||
cfb23ed6 ML |
13894 | if (current_config->has_drrs) |
13895 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13896 | } else | |
13897 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13898 | |
253c84c8 | 13899 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13900 | |
aa42a50a ML |
13901 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); |
13902 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); | |
13903 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); | |
13904 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); | |
13905 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); | |
13906 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13907 | |
aa42a50a ML |
13908 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); |
13909 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); | |
13910 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); | |
13911 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); | |
13912 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); | |
13913 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13914 | |
c93f54cf | 13915 | PIPE_CONF_CHECK_I(pixel_multiplier); |
d9facae6 | 13916 | PIPE_CONF_CHECK_I(output_format); |
d640bf79 | 13917 | PIPE_CONF_CHECK_BOOL(has_hdmi_sink); |
772c2a51 | 13918 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13919 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
d640bf79 | 13920 | PIPE_CONF_CHECK_BOOL(limited_color_range); |
15953637 | 13921 | |
d640bf79 ML |
13922 | PIPE_CONF_CHECK_BOOL(hdmi_scrambling); |
13923 | PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); | |
7afc7f81 | 13924 | PIPE_CONF_CHECK_BOOL(has_infoframe); |
8aa940c8 | 13925 | PIPE_CONF_CHECK_BOOL(fec_enable); |
6c49f241 | 13926 | |
4493e098 | 13927 | PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); |
9ed109a7 | 13928 | |
aa42a50a | 13929 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
1bd1bd80 DV |
13930 | DRM_MODE_FLAG_INTERLACE); |
13931 | ||
bb760063 | 13932 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
aa42a50a | 13933 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 13934 | DRM_MODE_FLAG_PHSYNC); |
aa42a50a | 13935 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 13936 | DRM_MODE_FLAG_NHSYNC); |
aa42a50a | 13937 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 | 13938 | DRM_MODE_FLAG_PVSYNC); |
aa42a50a | 13939 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
bb760063 DV |
13940 | DRM_MODE_FLAG_NVSYNC); |
13941 | } | |
045ac3b5 | 13942 | |
333b8ca8 | 13943 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 13944 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 13945 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 13946 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13947 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13948 | |
13b7648b VS |
13949 | /* |
13950 | * Changing the EDP transcoder input mux | |
13951 | * (A_ONOFF vs. A_ON) requires a full modeset. | |
13952 | */ | |
dc0c0bfe | 13953 | PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); |
13b7648b | 13954 | |
dde84833 | 13955 | if (!fastset) { |
bfd16b2a ML |
13956 | PIPE_CONF_CHECK_I(pipe_src_w); |
13957 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13958 | ||
d640bf79 | 13959 | PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); |
bfd16b2a | 13960 | if (current_config->pch_pfit.enabled) { |
35dd95b4 VS |
13961 | PIPE_CONF_CHECK_I(pch_pfit.dst.x1); |
13962 | PIPE_CONF_CHECK_I(pch_pfit.dst.y1); | |
13963 | PIPE_CONF_CHECK_I(pch_pfit.dst.x2); | |
13964 | PIPE_CONF_CHECK_I(pch_pfit.dst.y2); | |
bfd16b2a | 13965 | } |
2fa2fe9a | 13966 | |
7aefe2b5 | 13967 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 13968 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
9d5441de VS |
13969 | |
13970 | PIPE_CONF_CHECK_X(gamma_mode); | |
9fdfb8e7 VS |
13971 | if (IS_CHERRYVIEW(dev_priv)) |
13972 | PIPE_CONF_CHECK_X(cgm_mode); | |
13973 | else | |
13974 | PIPE_CONF_CHECK_X(csc_mode); | |
5f29ab23 | 13975 | PIPE_CONF_CHECK_BOOL(gamma_enable); |
8271b2ef | 13976 | PIPE_CONF_CHECK_BOOL(csc_enable); |
7e764059 | 13977 | |
6dcde047 VS |
13978 | PIPE_CONF_CHECK_I(linetime); |
13979 | PIPE_CONF_CHECK_I(ips_linetime); | |
13980 | ||
7e764059 SS |
13981 | bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); |
13982 | if (bp_gamma) | |
aa42a50a | 13983 | PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); |
7aefe2b5 | 13984 | } |
a1b2278e | 13985 | |
d640bf79 | 13986 | PIPE_CONF_CHECK_BOOL(double_wide); |
282740f7 | 13987 | |
8106ddbd | 13988 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13989 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13990 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13991 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13992 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13993 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13994 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13995 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13996 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13997 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
2de38138 PZ |
13998 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); |
13999 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); | |
14000 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); | |
14001 | PIPE_CONF_CHECK_X(dpll_hw_state.pll0); | |
14002 | PIPE_CONF_CHECK_X(dpll_hw_state.pll1); | |
14003 | PIPE_CONF_CHECK_X(dpll_hw_state.pll2); | |
14004 | PIPE_CONF_CHECK_X(dpll_hw_state.pll3); | |
14005 | PIPE_CONF_CHECK_X(dpll_hw_state.pll6); | |
14006 | PIPE_CONF_CHECK_X(dpll_hw_state.pll8); | |
14007 | PIPE_CONF_CHECK_X(dpll_hw_state.pll9); | |
14008 | PIPE_CONF_CHECK_X(dpll_hw_state.pll10); | |
14009 | PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); | |
c27e917e PZ |
14010 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); |
14011 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); | |
14012 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); | |
14013 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); | |
14014 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); | |
14015 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); | |
14016 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); | |
14017 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); | |
14018 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); | |
14019 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); | |
c0d43d62 | 14020 | |
47eacbab VS |
14021 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
14022 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
14023 | ||
9beb5fea | 14024 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
14025 | PIPE_CONF_CHECK_I(pipe_bpp); |
14026 | ||
aa42a50a | 14027 | PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); |
a9a7e98a | 14028 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 14029 | |
53e9bf5e VS |
14030 | PIPE_CONF_CHECK_I(min_voltage_level); |
14031 | ||
6454cb9f VS |
14032 | PIPE_CONF_CHECK_X(infoframes.enable); |
14033 | PIPE_CONF_CHECK_X(infoframes.gcp); | |
14034 | PIPE_CONF_CHECK_INFOFRAME(avi); | |
14035 | PIPE_CONF_CHECK_INFOFRAME(spd); | |
14036 | PIPE_CONF_CHECK_INFOFRAME(hdmi); | |
b37f588e | 14037 | PIPE_CONF_CHECK_INFOFRAME(drm); |
2c3928e4 | 14038 | PIPE_CONF_CHECK_DP_VSC_SDP(vsc); |
6454cb9f | 14039 | |
b33950dd | 14040 | PIPE_CONF_CHECK_X(sync_mode_slaves_mask); |
bfb926e3 MN |
14041 | PIPE_CONF_CHECK_I(master_transcoder); |
14042 | ||
fbacb15e JN |
14043 | PIPE_CONF_CHECK_I(dsc.compression_enable); |
14044 | PIPE_CONF_CHECK_I(dsc.dsc_split); | |
14045 | PIPE_CONF_CHECK_I(dsc.compressed_bpp); | |
14046 | ||
6671c367 JRS |
14047 | PIPE_CONF_CHECK_I(mst_master_transcoder); |
14048 | ||
66e985c0 | 14049 | #undef PIPE_CONF_CHECK_X |
08a24034 | 14050 | #undef PIPE_CONF_CHECK_I |
d640bf79 | 14051 | #undef PIPE_CONF_CHECK_BOOL |
4493e098 | 14052 | #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE |
8106ddbd | 14053 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 14054 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 14055 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
7e764059 | 14056 | #undef PIPE_CONF_CHECK_COLOR_LUT |
bb760063 | 14057 | #undef PIPE_CONF_QUIRK |
88adfff1 | 14058 | |
cfb23ed6 | 14059 | return ret; |
0e8ffe1b DV |
14060 | } |
14061 | ||
e3b247da VS |
14062 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
14063 | const struct intel_crtc_state *pipe_config) | |
14064 | { | |
14065 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 14066 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da | 14067 | &pipe_config->fdi_m_n); |
1326a92c | 14068 | int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; |
e3b247da VS |
14069 | |
14070 | /* | |
14071 | * FDI already provided one idea for the dotclock. | |
14072 | * Yell if the encoder disagrees. | |
14073 | */ | |
e57291c2 PB |
14074 | drm_WARN(&dev_priv->drm, |
14075 | !intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
14076 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
14077 | fdi_dotclock, dotclock); | |
e3b247da VS |
14078 | } |
14079 | } | |
14080 | ||
3b4bf24d ML |
14081 | static void verify_wm_state(struct intel_crtc *crtc, |
14082 | struct intel_crtc_state *new_crtc_state) | |
08db6652 | 14083 | { |
3b4bf24d | 14084 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
370d757d CW |
14085 | struct skl_hw_state { |
14086 | struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; | |
14087 | struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; | |
370d757d CW |
14088 | struct skl_pipe_wm wm; |
14089 | } *hw; | |
370d757d | 14090 | struct skl_pipe_wm *sw_wm; |
3de8a14c | 14091 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; |
072fcc30 | 14092 | u8 hw_enabled_slices; |
3b4bf24d | 14093 | const enum pipe pipe = crtc->pipe; |
3de8a14c | 14094 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 14095 | |
1326a92c | 14096 | if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active) |
08db6652 DL |
14097 | return; |
14098 | ||
370d757d CW |
14099 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
14100 | if (!hw) | |
14101 | return; | |
14102 | ||
3b4bf24d ML |
14103 | skl_pipe_wm_get_hw_state(crtc, &hw->wm); |
14104 | sw_wm = &new_crtc_state->wm.skl.optimal; | |
3de8a14c | 14105 | |
3b4bf24d | 14106 | skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); |
ff43bc37 | 14107 | |
0f0f9aee | 14108 | hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); |
08db6652 | 14109 | |
370d757d | 14110 | if (INTEL_GEN(dev_priv) >= 11 && |
3cf43cdc | 14111 | hw_enabled_slices != dev_priv->dbuf.enabled_slices) |
cd49f818 | 14112 | drm_err(&dev_priv->drm, |
0f0f9aee | 14113 | "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", |
3cf43cdc | 14114 | dev_priv->dbuf.enabled_slices, |
072fcc30 | 14115 | hw_enabled_slices); |
370d757d | 14116 | |
e7c84544 | 14117 | /* planes */ |
8b364b41 | 14118 | for_each_universal_plane(dev_priv, pipe, plane) { |
370d757d CW |
14119 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
14120 | ||
14121 | hw_plane_wm = &hw->wm.planes[plane]; | |
3de8a14c | 14122 | sw_plane_wm = &sw_wm->planes[plane]; |
08db6652 | 14123 | |
3de8a14c | 14124 | /* Watermarks */ |
14125 | for (level = 0; level <= max_level; level++) { | |
14126 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
7241c57d SL |
14127 | &sw_plane_wm->wm[level]) || |
14128 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], | |
14129 | &sw_plane_wm->sagv_wm0))) | |
3de8a14c | 14130 | continue; |
14131 | ||
cd49f818 WK |
14132 | drm_err(&dev_priv->drm, |
14133 | "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14134 | pipe_name(pipe), plane + 1, level, | |
14135 | sw_plane_wm->wm[level].plane_en, | |
14136 | sw_plane_wm->wm[level].plane_res_b, | |
14137 | sw_plane_wm->wm[level].plane_res_l, | |
14138 | hw_plane_wm->wm[level].plane_en, | |
14139 | hw_plane_wm->wm[level].plane_res_b, | |
14140 | hw_plane_wm->wm[level].plane_res_l); | |
3de8a14c | 14141 | } |
08db6652 | 14142 | |
3de8a14c | 14143 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
14144 | &sw_plane_wm->trans_wm)) { | |
cd49f818 WK |
14145 | drm_err(&dev_priv->drm, |
14146 | "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14147 | pipe_name(pipe), plane + 1, | |
14148 | sw_plane_wm->trans_wm.plane_en, | |
14149 | sw_plane_wm->trans_wm.plane_res_b, | |
14150 | sw_plane_wm->trans_wm.plane_res_l, | |
14151 | hw_plane_wm->trans_wm.plane_en, | |
14152 | hw_plane_wm->trans_wm.plane_res_b, | |
14153 | hw_plane_wm->trans_wm.plane_res_l); | |
3de8a14c | 14154 | } |
14155 | ||
14156 | /* DDB */ | |
370d757d | 14157 | hw_ddb_entry = &hw->ddb_y[plane]; |
3b4bf24d | 14158 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; |
3de8a14c | 14159 | |
14160 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
cd49f818 WK |
14161 | drm_err(&dev_priv->drm, |
14162 | "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", | |
14163 | pipe_name(pipe), plane + 1, | |
14164 | sw_ddb_entry->start, sw_ddb_entry->end, | |
14165 | hw_ddb_entry->start, hw_ddb_entry->end); | |
3de8a14c | 14166 | } |
e7c84544 | 14167 | } |
08db6652 | 14168 | |
27082493 L |
14169 | /* |
14170 | * cursor | |
14171 | * If the cursor plane isn't active, we may not have updated it's ddb | |
14172 | * allocation. In that case since the ddb allocation will be updated | |
14173 | * once the plane becomes visible, we can skip this check | |
14174 | */ | |
cd5dcbf1 | 14175 | if (1) { |
370d757d CW |
14176 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
14177 | ||
14178 | hw_plane_wm = &hw->wm.planes[PLANE_CURSOR]; | |
3de8a14c | 14179 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; |
14180 | ||
14181 | /* Watermarks */ | |
14182 | for (level = 0; level <= max_level; level++) { | |
14183 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
7241c57d SL |
14184 | &sw_plane_wm->wm[level]) || |
14185 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], | |
14186 | &sw_plane_wm->sagv_wm0))) | |
3de8a14c | 14187 | continue; |
14188 | ||
cd49f818 WK |
14189 | drm_err(&dev_priv->drm, |
14190 | "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14191 | pipe_name(pipe), level, | |
14192 | sw_plane_wm->wm[level].plane_en, | |
14193 | sw_plane_wm->wm[level].plane_res_b, | |
14194 | sw_plane_wm->wm[level].plane_res_l, | |
14195 | hw_plane_wm->wm[level].plane_en, | |
14196 | hw_plane_wm->wm[level].plane_res_b, | |
14197 | hw_plane_wm->wm[level].plane_res_l); | |
3de8a14c | 14198 | } |
14199 | ||
14200 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
14201 | &sw_plane_wm->trans_wm)) { | |
cd49f818 WK |
14202 | drm_err(&dev_priv->drm, |
14203 | "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
14204 | pipe_name(pipe), | |
14205 | sw_plane_wm->trans_wm.plane_en, | |
14206 | sw_plane_wm->trans_wm.plane_res_b, | |
14207 | sw_plane_wm->trans_wm.plane_res_l, | |
14208 | hw_plane_wm->trans_wm.plane_en, | |
14209 | hw_plane_wm->trans_wm.plane_res_b, | |
14210 | hw_plane_wm->trans_wm.plane_res_l); | |
3de8a14c | 14211 | } |
14212 | ||
14213 | /* DDB */ | |
370d757d | 14214 | hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; |
3b4bf24d | 14215 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; |
27082493 | 14216 | |
3de8a14c | 14217 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
cd49f818 WK |
14218 | drm_err(&dev_priv->drm, |
14219 | "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", | |
14220 | pipe_name(pipe), | |
14221 | sw_ddb_entry->start, sw_ddb_entry->end, | |
14222 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 14223 | } |
08db6652 | 14224 | } |
370d757d CW |
14225 | |
14226 | kfree(hw); | |
08db6652 DL |
14227 | } |
14228 | ||
91d1b4bd | 14229 | static void |
3b4bf24d ML |
14230 | verify_connector_state(struct intel_atomic_state *state, |
14231 | struct intel_crtc *crtc) | |
8af6cf88 | 14232 | { |
35dd3c64 | 14233 | struct drm_connector *connector; |
aa5e9b47 | 14234 | struct drm_connector_state *new_conn_state; |
677100ce | 14235 | int i; |
8af6cf88 | 14236 | |
3b4bf24d | 14237 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { |
35dd3c64 | 14238 | struct drm_encoder *encoder = connector->encoder; |
3b4bf24d | 14239 | struct intel_crtc_state *crtc_state = NULL; |
ad3c558f | 14240 | |
3b4bf24d | 14241 | if (new_conn_state->crtc != &crtc->base) |
e7c84544 ML |
14242 | continue; |
14243 | ||
749d98b8 | 14244 | if (crtc) |
3b4bf24d | 14245 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); |
749d98b8 ML |
14246 | |
14247 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 14248 | |
aa5e9b47 | 14249 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 14250 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 14251 | } |
91d1b4bd DV |
14252 | } |
14253 | ||
14254 | static void | |
3b4bf24d | 14255 | verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) |
91d1b4bd DV |
14256 | { |
14257 | struct intel_encoder *encoder; | |
86b04268 DV |
14258 | struct drm_connector *connector; |
14259 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
14260 | int i; | |
8af6cf88 | 14261 | |
3b4bf24d | 14262 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
86b04268 | 14263 | bool enabled = false, found = false; |
4d20cd86 | 14264 | enum pipe pipe; |
8af6cf88 | 14265 | |
cd49f818 WK |
14266 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", |
14267 | encoder->base.base.id, | |
14268 | encoder->base.name); | |
8af6cf88 | 14269 | |
3b4bf24d | 14270 | for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, |
86b04268 DV |
14271 | new_conn_state, i) { |
14272 | if (old_conn_state->best_encoder == &encoder->base) | |
14273 | found = true; | |
14274 | ||
14275 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 14276 | continue; |
86b04268 | 14277 | found = enabled = true; |
ad3c558f | 14278 | |
86b04268 | 14279 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
14280 | encoder->base.crtc, |
14281 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 14282 | } |
86b04268 DV |
14283 | |
14284 | if (!found) | |
14285 | continue; | |
0e32b39c | 14286 | |
e2c719b7 | 14287 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
14288 | "encoder's enabled state mismatch " |
14289 | "(expected %i, found %i)\n", | |
14290 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
14291 | |
14292 | if (!encoder->base.crtc) { | |
4d20cd86 | 14293 | bool active; |
7c60d198 | 14294 | |
4d20cd86 ML |
14295 | active = encoder->get_hw_state(encoder, &pipe); |
14296 | I915_STATE_WARN(active, | |
14297 | "encoder detached but still enabled on pipe %c.\n", | |
14298 | pipe_name(pipe)); | |
7c60d198 | 14299 | } |
8af6cf88 | 14300 | } |
91d1b4bd DV |
14301 | } |
14302 | ||
14303 | static void | |
3b4bf24d ML |
14304 | verify_crtc_state(struct intel_crtc *crtc, |
14305 | struct intel_crtc_state *old_crtc_state, | |
14306 | struct intel_crtc_state *new_crtc_state) | |
91d1b4bd | 14307 | { |
3b4bf24d | 14308 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 14309 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 14310 | struct intel_encoder *encoder; |
979e94c1 VS |
14311 | struct intel_crtc_state *pipe_config = old_crtc_state; |
14312 | struct drm_atomic_state *state = old_crtc_state->uapi.state; | |
045ac3b5 | 14313 | |
2225f3c6 | 14314 | __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); |
58d124ea | 14315 | intel_crtc_free_hw_state(old_crtc_state); |
979e94c1 VS |
14316 | intel_crtc_state_reset(old_crtc_state, crtc); |
14317 | old_crtc_state->uapi.state = state; | |
8af6cf88 | 14318 | |
cd49f818 WK |
14319 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, |
14320 | crtc->base.name); | |
8af6cf88 | 14321 | |
ef80c1a1 VS |
14322 | pipe_config->hw.enable = new_crtc_state->hw.enable; |
14323 | ||
14324 | pipe_config->hw.active = | |
14325 | dev_priv->display.get_pipe_config(crtc, pipe_config); | |
d62cf62a | 14326 | |
e56134bc | 14327 | /* we keep both pipes enabled on 830 */ |
ef80c1a1 VS |
14328 | if (IS_I830(dev_priv) && pipe_config->hw.active) |
14329 | pipe_config->hw.active = new_crtc_state->hw.active; | |
6c49f241 | 14330 | |
ef80c1a1 | 14331 | I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, |
1326a92c ML |
14332 | "crtc active state doesn't match with hw state " |
14333 | "(expected %i, found %i)\n", | |
ef80c1a1 | 14334 | new_crtc_state->hw.active, pipe_config->hw.active); |
0e8ffe1b | 14335 | |
1326a92c ML |
14336 | I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, |
14337 | "transitional active state does not match atomic hw state " | |
14338 | "(expected %i, found %i)\n", | |
14339 | new_crtc_state->hw.active, crtc->active); | |
4d20cd86 | 14340 | |
3b4bf24d | 14341 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
e7c84544 | 14342 | enum pipe pipe; |
ef80c1a1 | 14343 | bool active; |
4d20cd86 | 14344 | |
e7c84544 | 14345 | active = encoder->get_hw_state(encoder, &pipe); |
1326a92c ML |
14346 | I915_STATE_WARN(active != new_crtc_state->hw.active, |
14347 | "[ENCODER:%i] active %i with crtc active %i\n", | |
14348 | encoder->base.base.id, active, | |
14349 | new_crtc_state->hw.active); | |
4d20cd86 | 14350 | |
3b4bf24d | 14351 | I915_STATE_WARN(active && crtc->pipe != pipe, |
e7c84544 ML |
14352 | "Encoder connected to wrong pipe %c\n", |
14353 | pipe_name(pipe)); | |
4d20cd86 | 14354 | |
e1214b95 | 14355 | if (active) |
e7c84544 ML |
14356 | encoder->get_config(encoder, pipe_config); |
14357 | } | |
53d9f4e9 | 14358 | |
a7d1b3f4 VS |
14359 | intel_crtc_compute_pixel_rate(pipe_config); |
14360 | ||
1326a92c | 14361 | if (!new_crtc_state->hw.active) |
e7c84544 | 14362 | return; |
cfb23ed6 | 14363 | |
e7c84544 | 14364 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 14365 | |
3b4bf24d ML |
14366 | if (!intel_pipe_config_compare(new_crtc_state, |
14367 | pipe_config, false)) { | |
e7c84544 | 14368 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
10d75f54 | 14369 | intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); |
3b4bf24d | 14370 | intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); |
8af6cf88 DV |
14371 | } |
14372 | } | |
14373 | ||
cff109f0 VS |
14374 | static void |
14375 | intel_verify_planes(struct intel_atomic_state *state) | |
14376 | { | |
14377 | struct intel_plane *plane; | |
14378 | const struct intel_plane_state *plane_state; | |
14379 | int i; | |
14380 | ||
14381 | for_each_new_intel_plane_in_state(state, plane, | |
14382 | plane_state, i) | |
c47b7ddb | 14383 | assert_plane(plane, plane_state->planar_slave || |
f90a85e7 | 14384 | plane_state->uapi.visible); |
cff109f0 VS |
14385 | } |
14386 | ||
91d1b4bd | 14387 | static void |
c0ead703 ML |
14388 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
14389 | struct intel_shared_dpll *pll, | |
3b4bf24d ML |
14390 | struct intel_crtc *crtc, |
14391 | struct intel_crtc_state *new_crtc_state) | |
91d1b4bd | 14392 | { |
91d1b4bd | 14393 | struct intel_dpll_hw_state dpll_hw_state; |
40560e26 | 14394 | unsigned int crtc_mask; |
e7c84544 | 14395 | bool active; |
5358901f | 14396 | |
e7c84544 | 14397 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 14398 | |
cd49f818 | 14399 | drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); |
5358901f | 14400 | |
ee1398ba | 14401 | active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 14402 | |
5cd281f6 | 14403 | if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { |
e7c84544 ML |
14404 | I915_STATE_WARN(!pll->on && pll->active_mask, |
14405 | "pll in active use but not on in sw tracking\n"); | |
14406 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
14407 | "pll is on but not used by any active crtc\n"); | |
14408 | I915_STATE_WARN(pll->on != active, | |
14409 | "pll on state mismatch (expected %i, found %i)\n", | |
14410 | pll->on, active); | |
14411 | } | |
5358901f | 14412 | |
e7c84544 | 14413 | if (!crtc) { |
2c42e535 | 14414 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 14415 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 14416 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 14417 | |
e7c84544 ML |
14418 | return; |
14419 | } | |
14420 | ||
3b4bf24d | 14421 | crtc_mask = drm_crtc_mask(&crtc->base); |
e7c84544 | 14422 | |
1326a92c | 14423 | if (new_crtc_state->hw.active) |
e7c84544 ML |
14424 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), |
14425 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
aca9310a | 14426 | pipe_name(crtc->pipe), pll->active_mask); |
e7c84544 ML |
14427 | else |
14428 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
14429 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
aca9310a | 14430 | pipe_name(crtc->pipe), pll->active_mask); |
2dd66ebd | 14431 | |
2c42e535 | 14432 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 14433 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 14434 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 14435 | |
2c42e535 | 14436 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
14437 | &dpll_hw_state, |
14438 | sizeof(dpll_hw_state)), | |
14439 | "pll hw state mismatch\n"); | |
14440 | } | |
14441 | ||
14442 | static void | |
3b4bf24d ML |
14443 | verify_shared_dpll_state(struct intel_crtc *crtc, |
14444 | struct intel_crtc_state *old_crtc_state, | |
14445 | struct intel_crtc_state *new_crtc_state) | |
e7c84544 | 14446 | { |
3b4bf24d | 14447 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
e7c84544 | 14448 | |
3b4bf24d ML |
14449 | if (new_crtc_state->shared_dpll) |
14450 | verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); | |
e7c84544 | 14451 | |
3b4bf24d ML |
14452 | if (old_crtc_state->shared_dpll && |
14453 | old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { | |
14454 | unsigned int crtc_mask = drm_crtc_mask(&crtc->base); | |
14455 | struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; | |
e7c84544 ML |
14456 | |
14457 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
14458 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
aca9310a | 14459 | pipe_name(crtc->pipe)); |
2c42e535 | 14460 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 | 14461 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
aca9310a | 14462 | pipe_name(crtc->pipe)); |
5358901f | 14463 | } |
8af6cf88 DV |
14464 | } |
14465 | ||
e7c84544 | 14466 | static void |
855e0d68 ML |
14467 | intel_modeset_verify_crtc(struct intel_crtc *crtc, |
14468 | struct intel_atomic_state *state, | |
3b4bf24d ML |
14469 | struct intel_crtc_state *old_crtc_state, |
14470 | struct intel_crtc_state *new_crtc_state) | |
e7c84544 | 14471 | { |
3b4bf24d | 14472 | if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) |
5a21b665 DV |
14473 | return; |
14474 | ||
3b4bf24d ML |
14475 | verify_wm_state(crtc, new_crtc_state); |
14476 | verify_connector_state(state, crtc); | |
14477 | verify_crtc_state(crtc, old_crtc_state, new_crtc_state); | |
14478 | verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); | |
e7c84544 ML |
14479 | } |
14480 | ||
14481 | static void | |
3b4bf24d | 14482 | verify_disabled_dpll_state(struct drm_i915_private *dev_priv) |
e7c84544 | 14483 | { |
e7c84544 ML |
14484 | int i; |
14485 | ||
353ad959 ID |
14486 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) |
14487 | verify_single_dpll_state(dev_priv, | |
14488 | &dev_priv->dpll.shared_dplls[i], | |
14489 | NULL, NULL); | |
e7c84544 ML |
14490 | } |
14491 | ||
14492 | static void | |
3b4bf24d | 14493 | intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, |
855e0d68 | 14494 | struct intel_atomic_state *state) |
e7c84544 | 14495 | { |
3b4bf24d ML |
14496 | verify_encoder_state(dev_priv, state); |
14497 | verify_connector_state(state, NULL); | |
14498 | verify_disabled_dpll_state(dev_priv); | |
e7c84544 ML |
14499 | } |
14500 | ||
99325429 VS |
14501 | static void |
14502 | intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) | |
80715b2f | 14503 | { |
2225f3c6 | 14504 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
4f8036a2 | 14505 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
99325429 | 14506 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 14507 | &crtc_state->hw.adjusted_mode; |
99325429 VS |
14508 | |
14509 | drm_calc_timestamping_constants(&crtc->base, adjusted_mode); | |
80715b2f | 14510 | |
af157b76 VS |
14511 | crtc->mode_flags = crtc_state->mode_flags; |
14512 | ||
80715b2f VS |
14513 | /* |
14514 | * The scanline counter increments at the leading edge of hsync. | |
14515 | * | |
14516 | * On most platforms it starts counting from vtotal-1 on the | |
14517 | * first active line. That means the scanline counter value is | |
14518 | * always one less than what we would expect. Ie. just after | |
14519 | * start of vblank, which also occurs at start of hsync (on the | |
14520 | * last active line), the scanline counter will read vblank_start-1. | |
14521 | * | |
14522 | * On gen2 the scanline counter starts counting from 1 instead | |
14523 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
14524 | * to keep the value positive), instead of adding one. | |
14525 | * | |
14526 | * On HSW+ the behaviour of the scanline counter depends on the output | |
14527 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
14528 | * there's an extra 1 line difference. So we need to add two instead of | |
14529 | * one to the value. | |
ec1b4ee2 VS |
14530 | * |
14531 | * On VLV/CHV DSI the scanline counter would appear to increment | |
14532 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
14533 | * that means we can't tell whether we're in vblank or not while | |
14534 | * we're on that particular line. We must still set scanline_offset | |
14535 | * to 1 so that the vblank timestamps come out correct when we query | |
14536 | * the scanline counter from within the vblank interrupt handler. | |
14537 | * However if queried just before the start of vblank we'll get an | |
14538 | * answer that's slightly in the future. | |
80715b2f | 14539 | */ |
cf819eff | 14540 | if (IS_GEN(dev_priv, 2)) { |
80715b2f VS |
14541 | int vtotal; |
14542 | ||
124abe07 VS |
14543 | vtotal = adjusted_mode->crtc_vtotal; |
14544 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
14545 | vtotal /= 2; |
14546 | ||
14547 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 14548 | } else if (HAS_DDI(dev_priv) && |
f2bdd112 | 14549 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
80715b2f | 14550 | crtc->scanline_offset = 2; |
99325429 | 14551 | } else { |
80715b2f | 14552 | crtc->scanline_offset = 1; |
99325429 | 14553 | } |
80715b2f VS |
14554 | } |
14555 | ||
c3b1e6c6 | 14556 | static void intel_modeset_clear_plls(struct intel_atomic_state *state) |
ed6739ef | 14557 | { |
c3b1e6c6 | 14558 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
866955fa | 14559 | struct intel_crtc_state *new_crtc_state; |
c3b1e6c6 | 14560 | struct intel_crtc *crtc; |
0a9ab303 | 14561 | int i; |
ed6739ef ACO |
14562 | |
14563 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 14564 | return; |
ed6739ef | 14565 | |
866955fa | 14566 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
69f786ae | 14567 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
14568 | continue; |
14569 | ||
866955fa | 14570 | intel_release_shared_dplls(state, crtc); |
ad421372 | 14571 | } |
ed6739ef ACO |
14572 | } |
14573 | ||
99d736a2 ML |
14574 | /* |
14575 | * This implements the workaround described in the "notes" section of the mode | |
14576 | * set sequence documentation. When going from no pipes or single pipe to | |
14577 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
14578 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
14579 | */ | |
1e98f88c | 14580 | static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) |
99d736a2 | 14581 | { |
bca0bfa3 VS |
14582 | struct intel_crtc_state *crtc_state; |
14583 | struct intel_crtc *crtc; | |
99d736a2 ML |
14584 | struct intel_crtc_state *first_crtc_state = NULL; |
14585 | struct intel_crtc_state *other_crtc_state = NULL; | |
14586 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
14587 | int i; | |
14588 | ||
14589 | /* look at all crtc's that are going to be enabled in during modeset */ | |
bca0bfa3 | 14590 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { |
1326a92c | 14591 | if (!crtc_state->hw.active || |
69f786ae | 14592 | !needs_modeset(crtc_state)) |
99d736a2 ML |
14593 | continue; |
14594 | ||
14595 | if (first_crtc_state) { | |
bca0bfa3 | 14596 | other_crtc_state = crtc_state; |
99d736a2 ML |
14597 | break; |
14598 | } else { | |
bca0bfa3 VS |
14599 | first_crtc_state = crtc_state; |
14600 | first_pipe = crtc->pipe; | |
99d736a2 ML |
14601 | } |
14602 | } | |
14603 | ||
14604 | /* No workaround needed? */ | |
14605 | if (!first_crtc_state) | |
14606 | return 0; | |
14607 | ||
14608 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
bca0bfa3 VS |
14609 | for_each_intel_crtc(state->base.dev, crtc) { |
14610 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
14611 | if (IS_ERR(crtc_state)) | |
14612 | return PTR_ERR(crtc_state); | |
99d736a2 | 14613 | |
bca0bfa3 | 14614 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; |
99d736a2 | 14615 | |
1326a92c | 14616 | if (!crtc_state->hw.active || |
69f786ae | 14617 | needs_modeset(crtc_state)) |
99d736a2 ML |
14618 | continue; |
14619 | ||
14620 | /* 2 or more enabled crtcs means no need for w/a */ | |
14621 | if (enabled_pipe != INVALID_PIPE) | |
14622 | return 0; | |
14623 | ||
bca0bfa3 | 14624 | enabled_pipe = crtc->pipe; |
99d736a2 ML |
14625 | } |
14626 | ||
14627 | if (enabled_pipe != INVALID_PIPE) | |
14628 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
14629 | else if (other_crtc_state) | |
14630 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
14631 | ||
14632 | return 0; | |
14633 | } | |
14634 | ||
aac97871 VS |
14635 | u8 intel_calc_active_pipes(struct intel_atomic_state *state, |
14636 | u8 active_pipes) | |
14637 | { | |
14638 | const struct intel_crtc_state *crtc_state; | |
14639 | struct intel_crtc *crtc; | |
14640 | int i; | |
14641 | ||
14642 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
14643 | if (crtc_state->hw.active) | |
14644 | active_pipes |= BIT(crtc->pipe); | |
14645 | else | |
14646 | active_pipes &= ~BIT(crtc->pipe); | |
14647 | } | |
14648 | ||
14649 | return active_pipes; | |
14650 | } | |
14651 | ||
5643dd9c | 14652 | static int intel_modeset_checks(struct intel_atomic_state *state) |
054518dd | 14653 | { |
5643dd9c | 14654 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
054518dd | 14655 | |
5643dd9c | 14656 | state->modeset = true; |
1d5a95b5 | 14657 | |
565602d7 | 14658 | if (IS_HASWELL(dev_priv)) |
1e98f88c | 14659 | return hsw_mode_set_planes_workaround(state); |
99d736a2 | 14660 | |
ad421372 | 14661 | return 0; |
c347a676 ACO |
14662 | } |
14663 | ||
aa363136 MR |
14664 | /* |
14665 | * Handle calculation of various watermark data at the end of the atomic check | |
14666 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14667 | * handlers to ensure that all derived state has been updated. | |
14668 | */ | |
cd1d3ee9 | 14669 | static int calc_watermark_data(struct intel_atomic_state *state) |
aa363136 | 14670 | { |
cd1d3ee9 | 14671 | struct drm_device *dev = state->base.dev; |
98d39494 | 14672 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14673 | |
14674 | /* Is there platform-specific watermark information to calculate? */ | |
14675 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14676 | return dev_priv->display.compute_global_watermarks(state); |
14677 | ||
14678 | return 0; | |
aa363136 MR |
14679 | } |
14680 | ||
b124ea43 | 14681 | static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, |
f0521558 VS |
14682 | struct intel_crtc_state *new_crtc_state) |
14683 | { | |
b124ea43 | 14684 | if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) |
f0521558 VS |
14685 | return; |
14686 | ||
2225f3c6 | 14687 | new_crtc_state->uapi.mode_changed = false; |
f0521558 | 14688 | new_crtc_state->update_pipe = true; |
5cb5b370 | 14689 | } |
f0521558 | 14690 | |
5cb5b370 JRS |
14691 | static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, |
14692 | struct intel_crtc_state *new_crtc_state) | |
14693 | { | |
f0521558 VS |
14694 | /* |
14695 | * If we're not doing the full modeset we want to | |
14696 | * keep the current M/N values as they may be | |
14697 | * sufficiently different to the computed values | |
14698 | * to cause problems. | |
14699 | * | |
14700 | * FIXME: should really copy more fuzzy state here | |
14701 | */ | |
14702 | new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; | |
14703 | new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; | |
14704 | new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; | |
14705 | new_crtc_state->has_drrs = old_crtc_state->has_drrs; | |
14706 | } | |
14707 | ||
bb6ae9e6 VS |
14708 | static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, |
14709 | struct intel_crtc *crtc, | |
14710 | u8 plane_ids_mask) | |
131d3b1a | 14711 | { |
bb6ae9e6 VS |
14712 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
14713 | struct intel_plane *plane; | |
14714 | ||
14715 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { | |
14716 | struct intel_plane_state *plane_state; | |
14717 | ||
14718 | if ((plane_ids_mask & BIT(plane->id)) == 0) | |
14719 | continue; | |
14720 | ||
14721 | plane_state = intel_atomic_get_plane_state(state, plane); | |
14722 | if (IS_ERR(plane_state)) | |
14723 | return PTR_ERR(plane_state); | |
14724 | } | |
14725 | ||
14726 | return 0; | |
14727 | } | |
14728 | ||
14729 | static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) | |
14730 | { | |
14731 | /* See {hsw,vlv,ivb}_plane_ratio() */ | |
14732 | return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || | |
14733 | IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || | |
cf129762 | 14734 | IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11); |
bb6ae9e6 VS |
14735 | } |
14736 | ||
4f0b4352 | 14737 | static int intel_atomic_check_planes(struct intel_atomic_state *state) |
bb6ae9e6 VS |
14738 | { |
14739 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
14740 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
131d3b1a VS |
14741 | struct intel_plane_state *plane_state; |
14742 | struct intel_plane *plane; | |
bb6ae9e6 | 14743 | struct intel_crtc *crtc; |
131d3b1a VS |
14744 | int i, ret; |
14745 | ||
bb6ae9e6 VS |
14746 | ret = icl_add_linked_planes(state); |
14747 | if (ret) | |
14748 | return ret; | |
14749 | ||
131d3b1a VS |
14750 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
14751 | ret = intel_plane_atomic_check(state, plane); | |
14752 | if (ret) { | |
cd49f818 WK |
14753 | drm_dbg_atomic(&dev_priv->drm, |
14754 | "[PLANE:%d:%s] atomic driver check failed\n", | |
14755 | plane->base.base.id, plane->base.name); | |
131d3b1a VS |
14756 | return ret; |
14757 | } | |
14758 | } | |
14759 | ||
bb6ae9e6 VS |
14760 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
14761 | new_crtc_state, i) { | |
14762 | u8 old_active_planes, new_active_planes; | |
14763 | ||
14764 | ret = icl_check_nv12_planes(new_crtc_state); | |
14765 | if (ret) | |
14766 | return ret; | |
14767 | ||
14768 | /* | |
14769 | * On some platforms the number of active planes affects | |
14770 | * the planes' minimum cdclk calculation. Add such planes | |
14771 | * to the state before we compute the minimum cdclk. | |
14772 | */ | |
14773 | if (!active_planes_affects_min_cdclk(dev_priv)) | |
14774 | continue; | |
14775 | ||
14776 | old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); | |
14777 | new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); | |
14778 | ||
9877c37e SL |
14779 | /* |
14780 | * Not only the number of planes, but if the plane configuration had | |
14781 | * changed might already mean we need to recompute min CDCLK, | |
14782 | * because different planes might consume different amount of Dbuf bandwidth | |
14783 | * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor | |
14784 | */ | |
14785 | if (old_active_planes == new_active_planes) | |
bb6ae9e6 VS |
14786 | continue; |
14787 | ||
14788 | ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); | |
14789 | if (ret) | |
14790 | return ret; | |
14791 | } | |
14792 | ||
4f0b4352 SL |
14793 | return 0; |
14794 | } | |
14795 | ||
14796 | static int intel_atomic_check_cdclk(struct intel_atomic_state *state, | |
14797 | bool *need_cdclk_calc) | |
14798 | { | |
cd191546 | 14799 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
dc98f50f VS |
14800 | const struct intel_cdclk_state *old_cdclk_state; |
14801 | const struct intel_cdclk_state *new_cdclk_state; | |
4f0b4352 | 14802 | struct intel_plane_state *plane_state; |
19aefbc7 | 14803 | struct intel_bw_state *new_bw_state; |
4f0b4352 | 14804 | struct intel_plane *plane; |
19aefbc7 SL |
14805 | int min_cdclk = 0; |
14806 | enum pipe pipe; | |
4f0b4352 | 14807 | int ret; |
19aefbc7 | 14808 | int i; |
bb6ae9e6 VS |
14809 | /* |
14810 | * active_planes bitmask has been updated, and potentially | |
14811 | * affected planes are part of the state. We can now | |
14812 | * compute the minimum cdclk for each plane. | |
14813 | */ | |
28a30b45 VS |
14814 | for_each_new_intel_plane_in_state(state, plane, plane_state, i) { |
14815 | ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); | |
14816 | if (ret) | |
14817 | return ret; | |
14818 | } | |
bb6ae9e6 | 14819 | |
dc98f50f | 14820 | old_cdclk_state = intel_atomic_get_old_cdclk_state(state); |
cd191546 SL |
14821 | new_cdclk_state = intel_atomic_get_new_cdclk_state(state); |
14822 | ||
dc98f50f VS |
14823 | if (new_cdclk_state && |
14824 | old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) | |
cd191546 SL |
14825 | *need_cdclk_calc = true; |
14826 | ||
14827 | ret = dev_priv->display.bw_calc_min_cdclk(state); | |
14828 | if (ret) | |
14829 | return ret; | |
14830 | ||
19aefbc7 | 14831 | new_bw_state = intel_atomic_get_new_bw_state(state); |
cd191546 | 14832 | |
19aefbc7 SL |
14833 | if (!new_cdclk_state || !new_bw_state) |
14834 | return 0; | |
cd191546 | 14835 | |
19aefbc7 SL |
14836 | for_each_pipe(dev_priv, pipe) { |
14837 | min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); | |
cd191546 SL |
14838 | |
14839 | /* | |
14840 | * Currently do this change only if we need to increase | |
14841 | */ | |
19aefbc7 | 14842 | if (new_bw_state->min_cdclk > min_cdclk) |
cd191546 SL |
14843 | *need_cdclk_calc = true; |
14844 | } | |
14845 | ||
131d3b1a VS |
14846 | return 0; |
14847 | } | |
14848 | ||
14849 | static int intel_atomic_check_crtcs(struct intel_atomic_state *state) | |
14850 | { | |
14851 | struct intel_crtc_state *crtc_state; | |
14852 | struct intel_crtc *crtc; | |
14853 | int i; | |
14854 | ||
14855 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
14856 | int ret = intel_crtc_atomic_check(state, crtc); | |
cd49f818 | 14857 | struct drm_i915_private *i915 = to_i915(crtc->base.dev); |
131d3b1a | 14858 | if (ret) { |
cd49f818 WK |
14859 | drm_dbg_atomic(&i915->drm, |
14860 | "[CRTC:%d:%s] atomic driver check failed\n", | |
14861 | crtc->base.base.id, crtc->base.name); | |
131d3b1a VS |
14862 | return ret; |
14863 | } | |
14864 | } | |
14865 | ||
14866 | return 0; | |
14867 | } | |
14868 | ||
d0eed154 VS |
14869 | static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, |
14870 | u8 transcoders) | |
080d47bf | 14871 | { |
d0eed154 | 14872 | const struct intel_crtc_state *new_crtc_state; |
080d47bf JRS |
14873 | struct intel_crtc *crtc; |
14874 | int i; | |
14875 | ||
d0eed154 VS |
14876 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
14877 | if (new_crtc_state->hw.enable && | |
14878 | transcoders & BIT(new_crtc_state->cpu_transcoder) && | |
14879 | needs_modeset(new_crtc_state)) | |
14880 | return true; | |
14881 | } | |
080d47bf JRS |
14882 | |
14883 | return false; | |
14884 | } | |
14885 | ||
74c090b1 ML |
14886 | /** |
14887 | * intel_atomic_check - validate state object | |
14888 | * @dev: drm device | |
70972f51 | 14889 | * @_state: state to validate |
74c090b1 ML |
14890 | */ |
14891 | static int intel_atomic_check(struct drm_device *dev, | |
9a86a07c | 14892 | struct drm_atomic_state *_state) |
c347a676 | 14893 | { |
dd8b3bdb | 14894 | struct drm_i915_private *dev_priv = to_i915(dev); |
9a86a07c VS |
14895 | struct intel_atomic_state *state = to_intel_atomic_state(_state); |
14896 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
14897 | struct intel_crtc *crtc; | |
c347a676 | 14898 | int ret, i; |
1d5a95b5 | 14899 | bool any_ms = false; |
c347a676 | 14900 | |
9a86a07c VS |
14901 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
14902 | new_crtc_state, i) { | |
a227569d | 14903 | if (new_crtc_state->inherited != old_crtc_state->inherited) |
2225f3c6 | 14904 | new_crtc_state->uapi.mode_changed = true; |
8c58f73c ML |
14905 | } |
14906 | ||
9a86a07c | 14907 | ret = drm_atomic_helper_check_modeset(dev, &state->base); |
054518dd | 14908 | if (ret) |
2833920d | 14909 | goto fail; |
054518dd | 14910 | |
9a86a07c VS |
14911 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
14912 | new_crtc_state, i) { | |
58d124ea ML |
14913 | if (!needs_modeset(new_crtc_state)) { |
14914 | /* Light copy */ | |
14915 | intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state); | |
14916 | ||
c347a676 | 14917 | continue; |
58d124ea | 14918 | } |
c347a676 | 14919 | |
58d124ea ML |
14920 | ret = intel_crtc_prepare_cleared_state(new_crtc_state); |
14921 | if (ret) | |
14922 | goto fail; | |
14923 | ||
fff13e63 VS |
14924 | if (!new_crtc_state->hw.enable) |
14925 | continue; | |
14926 | ||
9a86a07c | 14927 | ret = intel_modeset_pipe_config(new_crtc_state); |
2833920d VS |
14928 | if (ret) |
14929 | goto fail; | |
f2801424 VS |
14930 | } |
14931 | ||
14932 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
14933 | new_crtc_state, i) { | |
14934 | if (!needs_modeset(new_crtc_state)) | |
14935 | continue; | |
14936 | ||
14937 | ret = intel_modeset_pipe_config_late(new_crtc_state); | |
14938 | if (ret) | |
14939 | goto fail; | |
c347a676 | 14940 | |
f0521558 | 14941 | intel_crtc_check_fastset(old_crtc_state, new_crtc_state); |
5cb5b370 | 14942 | } |
26495481 | 14943 | |
080d47bf JRS |
14944 | /** |
14945 | * Check if fastset is allowed by external dependencies like other | |
14946 | * pipes and transcoders. | |
14947 | * | |
14948 | * Right now it only forces a fullmodeset when the MST master | |
14949 | * transcoder did not changed but the pipe of the master transcoder | |
05a8e451 JRS |
14950 | * needs a fullmodeset so all slaves also needs to do a fullmodeset or |
14951 | * in case of port synced crtcs, if one of the synced crtcs | |
14952 | * needs a full modeset, all other synced crtcs should be | |
14953 | * forced a full modeset. | |
080d47bf JRS |
14954 | */ |
14955 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { | |
05a8e451 | 14956 | if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state)) |
080d47bf JRS |
14957 | continue; |
14958 | ||
05a8e451 JRS |
14959 | if (intel_dp_mst_is_slave_trans(new_crtc_state)) { |
14960 | enum transcoder master = new_crtc_state->mst_master_transcoder; | |
14961 | ||
d0eed154 | 14962 | if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { |
05a8e451 JRS |
14963 | new_crtc_state->uapi.mode_changed = true; |
14964 | new_crtc_state->update_pipe = false; | |
14965 | } | |
d0eed154 VS |
14966 | } |
14967 | ||
14968 | if (is_trans_port_sync_mode(new_crtc_state)) { | |
8c47eb86 MN |
14969 | u8 trans = new_crtc_state->sync_mode_slaves_mask; |
14970 | ||
14971 | if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) | |
14972 | trans |= BIT(new_crtc_state->master_transcoder); | |
05a8e451 | 14973 | |
d0eed154 VS |
14974 | if (intel_cpu_transcoders_need_modeset(state, trans)) { |
14975 | new_crtc_state->uapi.mode_changed = true; | |
14976 | new_crtc_state->update_pipe = false; | |
14977 | } | |
080d47bf JRS |
14978 | } |
14979 | } | |
14980 | ||
5cb5b370 JRS |
14981 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
14982 | new_crtc_state, i) { | |
14983 | if (needs_modeset(new_crtc_state)) { | |
26495481 | 14984 | any_ms = true; |
5cb5b370 JRS |
14985 | continue; |
14986 | } | |
14987 | ||
14988 | if (!new_crtc_state->update_pipe) | |
14989 | continue; | |
14990 | ||
14991 | intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); | |
c347a676 ACO |
14992 | } |
14993 | ||
bf5da83e | 14994 | if (any_ms && !check_digital_port_conflicts(state)) { |
cd49f818 WK |
14995 | drm_dbg_kms(&dev_priv->drm, |
14996 | "rejecting conflicting digital port configuration\n"); | |
66b51b80 | 14997 | ret = -EINVAL; |
bf5da83e VS |
14998 | goto fail; |
14999 | } | |
15000 | ||
9a86a07c | 15001 | ret = drm_dp_mst_atomic_check(&state->base); |
eceae147 | 15002 | if (ret) |
2833920d | 15003 | goto fail; |
eceae147 | 15004 | |
4f0b4352 | 15005 | ret = intel_atomic_check_planes(state); |
bb6ae9e6 VS |
15006 | if (ret) |
15007 | goto fail; | |
15008 | ||
0f8839f5 VS |
15009 | /* |
15010 | * distrust_bios_wm will force a full dbuf recomputation | |
15011 | * but the hardware state will only get updated accordingly | |
15012 | * if state->modeset==true. Hence distrust_bios_wm==true && | |
15013 | * state->modeset==false is an invalid combination which | |
15014 | * would cause the hardware and software dbuf state to get | |
15015 | * out of sync. We must prevent that. | |
15016 | * | |
15017 | * FIXME clean up this mess and introduce better | |
15018 | * state tracking for dbuf. | |
15019 | */ | |
15020 | if (dev_priv->wm.distrust_bios_wm) | |
15021 | any_ms = true; | |
15022 | ||
9a86a07c VS |
15023 | intel_fbc_choose_crtc(dev_priv, state); |
15024 | ret = calc_watermark_data(state); | |
c457d9cf | 15025 | if (ret) |
2833920d | 15026 | goto fail; |
c457d9cf | 15027 | |
9a86a07c | 15028 | ret = intel_bw_atomic_check(state); |
c457d9cf | 15029 | if (ret) |
2833920d | 15030 | goto fail; |
c457d9cf | 15031 | |
4f0b4352 SL |
15032 | ret = intel_atomic_check_cdclk(state, &any_ms); |
15033 | if (ret) | |
15034 | goto fail; | |
15035 | ||
c93b9b2c | 15036 | if (any_ms) { |
cf696856 KV |
15037 | ret = intel_modeset_checks(state); |
15038 | if (ret) | |
15039 | goto fail; | |
15040 | ||
c93b9b2c SL |
15041 | ret = intel_modeset_calc_cdclk(state); |
15042 | if (ret) | |
15043 | return ret; | |
15044 | ||
15045 | intel_modeset_clear_plls(state); | |
15046 | } | |
15047 | ||
15048 | ret = intel_atomic_check_crtcs(state); | |
15049 | if (ret) | |
15050 | goto fail; | |
15051 | ||
a0e70104 VS |
15052 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15053 | new_crtc_state, i) { | |
69f786ae | 15054 | if (!needs_modeset(new_crtc_state) && |
a0e70104 VS |
15055 | !new_crtc_state->update_pipe) |
15056 | continue; | |
15057 | ||
10d75f54 | 15058 | intel_dump_pipe_config(new_crtc_state, state, |
69f786ae | 15059 | needs_modeset(new_crtc_state) ? |
a0e70104 VS |
15060 | "[modeset]" : "[fastset]"); |
15061 | } | |
15062 | ||
c457d9cf | 15063 | return 0; |
2833920d VS |
15064 | |
15065 | fail: | |
15066 | if (ret == -EDEADLK) | |
15067 | return ret; | |
15068 | ||
15069 | /* | |
15070 | * FIXME would probably be nice to know which crtc specifically | |
15071 | * caused the failure, in cases where we can pinpoint it. | |
15072 | */ | |
15073 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15074 | new_crtc_state, i) | |
10d75f54 | 15075 | intel_dump_pipe_config(new_crtc_state, state, "[failed]"); |
2833920d VS |
15076 | |
15077 | return ret; | |
054518dd ACO |
15078 | } |
15079 | ||
a85fb467 | 15080 | static int intel_atomic_prepare_commit(struct intel_atomic_state *state) |
5008e874 | 15081 | { |
afeda4f3 AM |
15082 | struct intel_crtc_state *crtc_state; |
15083 | struct intel_crtc *crtc; | |
15084 | int i, ret; | |
15085 | ||
15086 | ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); | |
15087 | if (ret < 0) | |
15088 | return ret; | |
15089 | ||
15090 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
15091 | bool mode_changed = needs_modeset(crtc_state); | |
15092 | ||
15093 | if (mode_changed || crtc_state->update_pipe || | |
15094 | crtc_state->uapi.color_mgmt_changed) { | |
15095 | intel_dsb_prepare(crtc_state); | |
15096 | } | |
15097 | } | |
15098 | ||
15099 | return 0; | |
5008e874 ML |
15100 | } |
15101 | ||
a2991414 ML |
15102 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
15103 | { | |
15104 | struct drm_device *dev = crtc->base.dev; | |
32db0b65 | 15105 | struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; |
a2991414 | 15106 | |
32db0b65 | 15107 | if (!vblank->max_vblank_count) |
734cbbf3 | 15108 | return (u32)drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 | 15109 | |
08fa8fd0 | 15110 | return crtc->base.funcs->get_vblank_counter(&crtc->base); |
a2991414 ML |
15111 | } |
15112 | ||
d8bd3e15 ML |
15113 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
15114 | struct intel_crtc_state *crtc_state) | |
15115 | { | |
15116 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
15117 | ||
cfdd1747 | 15118 | if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes) |
d8bd3e15 ML |
15119 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); |
15120 | ||
15121 | if (crtc_state->has_pch_encoder) { | |
15122 | enum pipe pch_transcoder = | |
15123 | intel_crtc_pch_transcoder(crtc); | |
15124 | ||
15125 | intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); | |
15126 | } | |
15127 | } | |
15128 | ||
15129 | static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, | |
15130 | const struct intel_crtc_state *new_crtc_state) | |
15131 | { | |
2225f3c6 | 15132 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
d8bd3e15 ML |
15133 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
15134 | ||
d8bd3e15 ML |
15135 | /* |
15136 | * Update pipe size and adjust fitter if needed: the reason for this is | |
15137 | * that in compute_mode_changes we check the native mode (not the pfit | |
15138 | * mode) to see if we can flip rather than do a full mode set. In the | |
15139 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
15140 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
15141 | * sized surface. | |
15142 | */ | |
15143 | intel_set_pipe_src_size(new_crtc_state); | |
15144 | ||
15145 | /* on skylake this is done by detaching scalers */ | |
15146 | if (INTEL_GEN(dev_priv) >= 9) { | |
15147 | skl_detach_scalers(new_crtc_state); | |
15148 | ||
15149 | if (new_crtc_state->pch_pfit.enabled) | |
f6df4d46 | 15150 | skl_pfit_enable(new_crtc_state); |
d8bd3e15 ML |
15151 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
15152 | if (new_crtc_state->pch_pfit.enabled) | |
9eae5e27 | 15153 | ilk_pfit_enable(new_crtc_state); |
d8bd3e15 | 15154 | else if (old_crtc_state->pch_pfit.enabled) |
9eae5e27 | 15155 | ilk_pfit_disable(old_crtc_state); |
d8bd3e15 ML |
15156 | } |
15157 | ||
6dcde047 VS |
15158 | /* |
15159 | * The register is supposedly single buffered so perhaps | |
15160 | * not 100% correct to do this here. But SKL+ calculate | |
15161 | * this based on the adjust pixel rate so pfit changes do | |
15162 | * affect it and so it must be updated for fastsets. | |
15163 | * HSW/BDW only really need this here for fastboot, after | |
15164 | * that the value should not change without a full modeset. | |
15165 | */ | |
15166 | if (INTEL_GEN(dev_priv) >= 9 || | |
15167 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
15168 | hsw_set_linetime_wm(new_crtc_state); | |
15169 | ||
d8bd3e15 ML |
15170 | if (INTEL_GEN(dev_priv) >= 11) |
15171 | icl_set_pipe_chicken(crtc); | |
15172 | } | |
15173 | ||
15174 | static void commit_pipe_config(struct intel_atomic_state *state, | |
b932da3c | 15175 | struct intel_crtc *crtc) |
d8bd3e15 ML |
15176 | { |
15177 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
b932da3c VS |
15178 | const struct intel_crtc_state *old_crtc_state = |
15179 | intel_atomic_get_old_crtc_state(state, crtc); | |
15180 | const struct intel_crtc_state *new_crtc_state = | |
15181 | intel_atomic_get_new_crtc_state(state, crtc); | |
d8bd3e15 ML |
15182 | bool modeset = needs_modeset(new_crtc_state); |
15183 | ||
15184 | /* | |
15185 | * During modesets pipe configuration was programmed as the | |
15186 | * CRTC was enabled. | |
15187 | */ | |
15188 | if (!modeset) { | |
2225f3c6 | 15189 | if (new_crtc_state->uapi.color_mgmt_changed || |
d8bd3e15 ML |
15190 | new_crtc_state->update_pipe) |
15191 | intel_color_commit(new_crtc_state); | |
15192 | ||
15193 | if (INTEL_GEN(dev_priv) >= 9) | |
15194 | skl_detach_scalers(new_crtc_state); | |
15195 | ||
15196 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) | |
15197 | bdw_set_pipemisc(new_crtc_state); | |
15198 | ||
15199 | if (new_crtc_state->update_pipe) | |
15200 | intel_pipe_fastset(old_crtc_state, new_crtc_state); | |
6e43e276 JRS |
15201 | |
15202 | intel_psr2_program_trans_man_trk_ctl(new_crtc_state); | |
d8bd3e15 ML |
15203 | } |
15204 | ||
15205 | if (dev_priv->display.atomic_update_watermarks) | |
7a8fdb1f | 15206 | dev_priv->display.atomic_update_watermarks(state, crtc); |
d8bd3e15 ML |
15207 | } |
15208 | ||
b932da3c VS |
15209 | static void intel_enable_crtc(struct intel_atomic_state *state, |
15210 | struct intel_crtc *crtc) | |
896e5bb0 | 15211 | { |
d8bd3e15 | 15212 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
b932da3c VS |
15213 | const struct intel_crtc_state *new_crtc_state = |
15214 | intel_atomic_get_new_crtc_state(state, crtc); | |
896e5bb0 | 15215 | |
b932da3c VS |
15216 | if (!needs_modeset(new_crtc_state)) |
15217 | return; | |
99325429 | 15218 | |
b932da3c | 15219 | intel_crtc_update_active_timings(new_crtc_state); |
033b7a23 | 15220 | |
b932da3c VS |
15221 | dev_priv->display.crtc_enable(state, crtc); |
15222 | ||
15223 | /* vblanks work again, re-enable pipe CRC. */ | |
15224 | intel_crtc_enable_pipe_crc(crtc); | |
15225 | } | |
15226 | ||
15227 | static void intel_update_crtc(struct intel_atomic_state *state, | |
15228 | struct intel_crtc *crtc) | |
15229 | { | |
15230 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
15231 | const struct intel_crtc_state *old_crtc_state = | |
15232 | intel_atomic_get_old_crtc_state(state, crtc); | |
15233 | struct intel_crtc_state *new_crtc_state = | |
15234 | intel_atomic_get_new_crtc_state(state, crtc); | |
15235 | bool modeset = needs_modeset(new_crtc_state); | |
15236 | ||
15237 | if (!modeset) { | |
0ccc42a2 VS |
15238 | if (new_crtc_state->preload_luts && |
15239 | (new_crtc_state->uapi.color_mgmt_changed || | |
15240 | new_crtc_state->update_pipe)) | |
15241 | intel_color_load_luts(new_crtc_state); | |
15242 | ||
bee43ca4 | 15243 | intel_pre_plane_update(state, crtc); |
608ed4ab | 15244 | |
855e0d68 | 15245 | if (new_crtc_state->update_pipe) |
021ba100 | 15246 | intel_encoders_update_pipe(state, crtc); |
896e5bb0 L |
15247 | } |
15248 | ||
855e0d68 ML |
15249 | if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) |
15250 | intel_fbc_disable(crtc); | |
9ecc6eab VS |
15251 | else |
15252 | intel_fbc_enable(state, crtc); | |
896e5bb0 | 15253 | |
d8bd3e15 ML |
15254 | /* Perform vblank evasion around commit operation */ |
15255 | intel_pipe_update_start(new_crtc_state); | |
15256 | ||
b932da3c | 15257 | commit_pipe_config(state, crtc); |
6c246b81 | 15258 | |
5f2e5112 | 15259 | if (INTEL_GEN(dev_priv) >= 9) |
855e0d68 | 15260 | skl_update_planes_on_crtc(state, crtc); |
5f2e5112 | 15261 | else |
855e0d68 | 15262 | i9xx_update_planes_on_crtc(state, crtc); |
6c246b81 | 15263 | |
d8bd3e15 ML |
15264 | intel_pipe_update_end(new_crtc_state); |
15265 | ||
15266 | /* | |
15267 | * We usually enable FIFO underrun interrupts as part of the | |
15268 | * CRTC enable sequence during modesets. But when we inherit a | |
15269 | * valid pipe configuration from the BIOS we need to take care | |
15270 | * of enabling them on the CRTC's first fastset. | |
15271 | */ | |
15272 | if (new_crtc_state->update_pipe && !modeset && | |
a227569d | 15273 | old_crtc_state->inherited) |
d8bd3e15 | 15274 | intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); |
896e5bb0 L |
15275 | } |
15276 | ||
eadf6f91 | 15277 | |
66d9cec8 MN |
15278 | static void intel_old_crtc_state_disables(struct intel_atomic_state *state, |
15279 | struct intel_crtc_state *old_crtc_state, | |
15280 | struct intel_crtc_state *new_crtc_state, | |
15281 | struct intel_crtc *crtc) | |
15282 | { | |
15283 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
15284 | ||
15285 | intel_crtc_disable_planes(state, crtc); | |
15286 | ||
15287 | /* | |
15288 | * We need to disable pipe CRC before disabling the pipe, | |
15289 | * or we race against vblank off. | |
15290 | */ | |
15291 | intel_crtc_disable_pipe_crc(crtc); | |
15292 | ||
7451a074 | 15293 | dev_priv->display.crtc_disable(state, crtc); |
66d9cec8 MN |
15294 | crtc->active = false; |
15295 | intel_fbc_disable(crtc); | |
15296 | intel_disable_shared_dpll(old_crtc_state); | |
15297 | ||
66d9cec8 | 15298 | /* FIXME unify this for all platforms */ |
1326a92c | 15299 | if (!new_crtc_state->hw.active && |
66d9cec8 MN |
15300 | !HAS_GMCH(dev_priv) && |
15301 | dev_priv->display.initial_watermarks) | |
7a8fdb1f | 15302 | dev_priv->display.initial_watermarks(state, crtc); |
66d9cec8 MN |
15303 | } |
15304 | ||
15305 | static void intel_commit_modeset_disables(struct intel_atomic_state *state) | |
15306 | { | |
15307 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; | |
15308 | struct intel_crtc *crtc; | |
ad457191 | 15309 | u32 handled = 0; |
66d9cec8 MN |
15310 | int i; |
15311 | ||
6671c367 | 15312 | /* Only disable port sync and MST slaves */ |
ad457191 JRS |
15313 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15314 | new_crtc_state, i) { | |
66d9cec8 MN |
15315 | if (!needs_modeset(new_crtc_state)) |
15316 | continue; | |
15317 | ||
ad457191 JRS |
15318 | if (!old_crtc_state->hw.active) |
15319 | continue; | |
15320 | ||
a6c948f9 MN |
15321 | /* In case of Transcoder port Sync master slave CRTCs can be |
15322 | * assigned in any order and we need to make sure that | |
15323 | * slave CRTCs are disabled first and then master CRTC since | |
15324 | * Slave vblanks are masked till Master Vblanks. | |
15325 | */ | |
6671c367 JRS |
15326 | if (!is_trans_port_sync_slave(old_crtc_state) && |
15327 | !intel_dp_mst_is_slave_trans(old_crtc_state)) | |
ad457191 | 15328 | continue; |
66d9cec8 | 15329 | |
ad457191 JRS |
15330 | intel_pre_plane_update(state, crtc); |
15331 | intel_old_crtc_state_disables(state, old_crtc_state, | |
15332 | new_crtc_state, crtc); | |
15333 | handled |= BIT(crtc->pipe); | |
15334 | } | |
15335 | ||
15336 | /* Disable everything else left on */ | |
15337 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15338 | new_crtc_state, i) { | |
15339 | if (!needs_modeset(new_crtc_state) || | |
15340 | (handled & BIT(crtc->pipe))) | |
15341 | continue; | |
15342 | ||
15343 | intel_pre_plane_update(state, crtc); | |
15344 | if (old_crtc_state->hw.active) | |
15345 | intel_old_crtc_state_disables(state, old_crtc_state, | |
15346 | new_crtc_state, crtc); | |
66d9cec8 MN |
15347 | } |
15348 | } | |
15349 | ||
0c841271 | 15350 | static void intel_commit_modeset_enables(struct intel_atomic_state *state) |
896e5bb0 | 15351 | { |
b932da3c | 15352 | struct intel_crtc_state *new_crtc_state; |
855e0d68 | 15353 | struct intel_crtc *crtc; |
896e5bb0 L |
15354 | int i; |
15355 | ||
b932da3c | 15356 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
1326a92c | 15357 | if (!new_crtc_state->hw.active) |
896e5bb0 L |
15358 | continue; |
15359 | ||
b932da3c VS |
15360 | intel_enable_crtc(state, crtc); |
15361 | intel_update_crtc(state, crtc); | |
896e5bb0 L |
15362 | } |
15363 | } | |
15364 | ||
0c841271 | 15365 | static void skl_commit_modeset_enables(struct intel_atomic_state *state) |
27082493 | 15366 | { |
855e0d68 ML |
15367 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
15368 | struct intel_crtc *crtc; | |
15369 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
53cc6880 | 15370 | struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; |
659f1415 | 15371 | u8 update_pipes = 0, modeset_pipes = 0; |
601a9ee0 | 15372 | int i; |
5eff503b | 15373 | |
601a9ee0 | 15374 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
ee34801c VS |
15375 | enum pipe pipe = crtc->pipe; |
15376 | ||
659f1415 JRS |
15377 | if (!new_crtc_state->hw.active) |
15378 | continue; | |
15379 | ||
5eff503b | 15380 | /* ignore allocations for crtc's that have been turned off. */ |
659f1415 | 15381 | if (!needs_modeset(new_crtc_state)) { |
ee34801c VS |
15382 | entries[pipe] = old_crtc_state->wm.skl.ddb; |
15383 | update_pipes |= BIT(pipe); | |
659f1415 | 15384 | } else { |
ee34801c | 15385 | modeset_pipes |= BIT(pipe); |
659f1415 | 15386 | } |
601a9ee0 | 15387 | } |
27082493 L |
15388 | |
15389 | /* | |
15390 | * Whenever the number of active pipes changes, we need to make sure we | |
15391 | * update the pipes in the right order so that their ddb allocations | |
659f1415 | 15392 | * never overlap with each other between CRTC updates. Otherwise we'll |
27082493 | 15393 | * cause pipe underruns and other bad stuff. |
659f1415 JRS |
15394 | * |
15395 | * So first lets enable all pipes that do not need a fullmodeset as | |
15396 | * those don't have any external dependency. | |
27082493 | 15397 | */ |
659f1415 | 15398 | while (update_pipes) { |
601a9ee0 VS |
15399 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15400 | new_crtc_state, i) { | |
36b53a29 | 15401 | enum pipe pipe = crtc->pipe; |
27082493 | 15402 | |
659f1415 | 15403 | if ((update_pipes & BIT(pipe)) == 0) |
27082493 | 15404 | continue; |
5eff503b | 15405 | |
855e0d68 | 15406 | if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, |
7a0a6ee7 | 15407 | entries, I915_MAX_PIPES, pipe)) |
27082493 L |
15408 | continue; |
15409 | ||
ee34801c | 15410 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
659f1415 JRS |
15411 | update_pipes &= ~BIT(pipe); |
15412 | ||
b932da3c | 15413 | intel_update_crtc(state, crtc); |
27082493 | 15414 | |
601a9ee0 VS |
15415 | /* |
15416 | * If this is an already active pipe, it's DDB changed, | |
15417 | * and this isn't the last pipe that needs updating | |
15418 | * then we need to wait for a vblank to pass for the | |
15419 | * new ddb allocation to take effect. | |
15420 | */ | |
15421 | if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, | |
15422 | &old_crtc_state->wm.skl.ddb) && | |
659f1415 | 15423 | (update_pipes | modeset_pipes)) |
0f0f74bc | 15424 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 | 15425 | } |
601a9ee0 | 15426 | } |
aa9664ff | 15427 | |
1ff241ea VS |
15428 | update_pipes = modeset_pipes; |
15429 | ||
659f1415 JRS |
15430 | /* |
15431 | * Enable all pipes that needs a modeset and do not depends on other | |
15432 | * pipes | |
15433 | */ | |
4f05d7ae | 15434 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
659f1415 JRS |
15435 | enum pipe pipe = crtc->pipe; |
15436 | ||
15437 | if ((modeset_pipes & BIT(pipe)) == 0) | |
15438 | continue; | |
15439 | ||
15440 | if (intel_dp_mst_is_slave_trans(new_crtc_state) || | |
d82a855a | 15441 | is_trans_port_sync_master(new_crtc_state)) |
659f1415 JRS |
15442 | continue; |
15443 | ||
659f1415 JRS |
15444 | modeset_pipes &= ~BIT(pipe); |
15445 | ||
d82a855a | 15446 | intel_enable_crtc(state, crtc); |
659f1415 JRS |
15447 | } |
15448 | ||
15449 | /* | |
1ff241ea | 15450 | * Then we enable all remaining pipes that depend on other |
d82a855a | 15451 | * pipes: MST slaves and port sync masters. |
659f1415 | 15452 | */ |
b932da3c | 15453 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
659f1415 JRS |
15454 | enum pipe pipe = crtc->pipe; |
15455 | ||
15456 | if ((modeset_pipes & BIT(pipe)) == 0) | |
15457 | continue; | |
15458 | ||
1ff241ea VS |
15459 | modeset_pipes &= ~BIT(pipe); |
15460 | ||
15461 | intel_enable_crtc(state, crtc); | |
15462 | } | |
15463 | ||
15464 | /* | |
15465 | * Finally we do the plane updates/etc. for all pipes that got enabled. | |
15466 | */ | |
15467 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { | |
15468 | enum pipe pipe = crtc->pipe; | |
15469 | ||
15470 | if ((update_pipes & BIT(pipe)) == 0) | |
15471 | continue; | |
15472 | ||
e57291c2 | 15473 | drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, |
7a0a6ee7 | 15474 | entries, I915_MAX_PIPES, pipe)); |
659f1415 | 15475 | |
ee34801c | 15476 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
1ff241ea | 15477 | update_pipes &= ~BIT(pipe); |
659f1415 | 15478 | |
b932da3c | 15479 | intel_update_crtc(state, crtc); |
659f1415 JRS |
15480 | } |
15481 | ||
e57291c2 | 15482 | drm_WARN_ON(&dev_priv->drm, modeset_pipes); |
1ff241ea | 15483 | drm_WARN_ON(&dev_priv->drm, update_pipes); |
27082493 L |
15484 | } |
15485 | ||
ba318c61 CW |
15486 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
15487 | { | |
15488 | struct intel_atomic_state *state, *next; | |
15489 | struct llist_node *freed; | |
15490 | ||
15491 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
15492 | llist_for_each_entry_safe(state, next, freed, freed) | |
15493 | drm_atomic_state_put(&state->base); | |
15494 | } | |
15495 | ||
15496 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
15497 | { | |
15498 | struct drm_i915_private *dev_priv = | |
15499 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
15500 | ||
15501 | intel_atomic_helper_free_state(dev_priv); | |
15502 | } | |
15503 | ||
9db529aa DV |
15504 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
15505 | { | |
15506 | struct wait_queue_entry wait_fence, wait_reset; | |
15507 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
15508 | ||
15509 | init_wait_entry(&wait_fence, 0); | |
15510 | init_wait_entry(&wait_reset, 0); | |
15511 | for (;;) { | |
15512 | prepare_to_wait(&intel_state->commit_ready.wait, | |
15513 | &wait_fence, TASK_UNINTERRUPTIBLE); | |
cb823ed9 CW |
15514 | prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
15515 | I915_RESET_MODESET), | |
9db529aa DV |
15516 | &wait_reset, TASK_UNINTERRUPTIBLE); |
15517 | ||
15518 | ||
cb823ed9 CW |
15519 | if (i915_sw_fence_done(&intel_state->commit_ready) || |
15520 | test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) | |
9db529aa DV |
15521 | break; |
15522 | ||
15523 | schedule(); | |
15524 | } | |
15525 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); | |
cb823ed9 CW |
15526 | finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
15527 | I915_RESET_MODESET), | |
15528 | &wait_reset); | |
9db529aa DV |
15529 | } |
15530 | ||
afeda4f3 AM |
15531 | static void intel_cleanup_dsbs(struct intel_atomic_state *state) |
15532 | { | |
15533 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; | |
15534 | struct intel_crtc *crtc; | |
15535 | int i; | |
15536 | ||
15537 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, | |
15538 | new_crtc_state, i) | |
15539 | intel_dsb_cleanup(old_crtc_state); | |
15540 | } | |
15541 | ||
8d52e447 CW |
15542 | static void intel_atomic_cleanup_work(struct work_struct *work) |
15543 | { | |
afeda4f3 AM |
15544 | struct intel_atomic_state *state = |
15545 | container_of(work, struct intel_atomic_state, base.commit_work); | |
15546 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
8d52e447 | 15547 | |
afeda4f3 AM |
15548 | intel_cleanup_dsbs(state); |
15549 | drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); | |
15550 | drm_atomic_helper_commit_cleanup_done(&state->base); | |
15551 | drm_atomic_state_put(&state->base); | |
8d52e447 CW |
15552 | |
15553 | intel_atomic_helper_free_state(i915); | |
15554 | } | |
15555 | ||
855e0d68 | 15556 | static void intel_atomic_commit_tail(struct intel_atomic_state *state) |
a6778b3c | 15557 | { |
855e0d68 | 15558 | struct drm_device *dev = state->base.dev; |
fac5e23e | 15559 | struct drm_i915_private *dev_priv = to_i915(dev); |
855e0d68 ML |
15560 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; |
15561 | struct intel_crtc *crtc; | |
d8fc70b7 | 15562 | u64 put_domains[I915_MAX_PIPES] = {}; |
0e6e0be4 | 15563 | intel_wakeref_t wakeref = 0; |
e95433c7 | 15564 | int i; |
a6778b3c | 15565 | |
855e0d68 | 15566 | intel_atomic_commit_fence_wait(state); |
42b062b0 | 15567 | |
855e0d68 | 15568 | drm_atomic_helper_wait_for_dependencies(&state->base); |
ea0000f0 | 15569 | |
855e0d68 | 15570 | if (state->modeset) |
0e6e0be4 | 15571 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 15572 | |
7bff9779 ML |
15573 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15574 | new_crtc_state, i) { | |
855e0d68 ML |
15575 | if (needs_modeset(new_crtc_state) || |
15576 | new_crtc_state->update_pipe) { | |
a539205a | 15577 | |
855e0d68 | 15578 | put_domains[crtc->pipe] = |
afe0c21b | 15579 | modeset_get_crtc_power_domains(new_crtc_state); |
5a21b665 | 15580 | } |
b8cecdf5 | 15581 | } |
7758a113 | 15582 | |
66d9cec8 MN |
15583 | intel_commit_modeset_disables(state); |
15584 | ||
855e0d68 ML |
15585 | /* FIXME: Eventually get rid of our crtc->config pointer */ |
15586 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) | |
15587 | crtc->config = new_crtc_state; | |
f6e5b160 | 15588 | |
855e0d68 ML |
15589 | if (state->modeset) { |
15590 | drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); | |
33c8df89 | 15591 | |
5604e9ce | 15592 | intel_set_cdclk_pre_plane_update(state); |
f6d1973d | 15593 | |
3b4bf24d | 15594 | intel_modeset_verify_disabled(dev_priv, state); |
4740b0f2 | 15595 | } |
47fab737 | 15596 | |
ecab0f3d SL |
15597 | intel_sagv_pre_plane_update(state); |
15598 | ||
896e5bb0 | 15599 | /* Complete the events for pipes that have now been disabled */ |
855e0d68 ML |
15600 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
15601 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 15602 | |
1f7528c4 | 15603 | /* Complete events for now disable pipes here. */ |
2225f3c6 | 15604 | if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { |
1f7528c4 | 15605 | spin_lock_irq(&dev->event_lock); |
2225f3c6 ML |
15606 | drm_crtc_send_vblank_event(&crtc->base, |
15607 | new_crtc_state->uapi.event); | |
1f7528c4 DV |
15608 | spin_unlock_irq(&dev->event_lock); |
15609 | ||
2225f3c6 | 15610 | new_crtc_state->uapi.event = NULL; |
1f7528c4 | 15611 | } |
177246a8 MR |
15612 | } |
15613 | ||
24a7bfe0 ID |
15614 | if (state->modeset) |
15615 | intel_encoders_update_prepare(state); | |
15616 | ||
c7c0e7eb | 15617 | intel_dbuf_pre_plane_update(state); |
b06cf595 | 15618 | |
896e5bb0 | 15619 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0c841271 | 15620 | dev_priv->display.commit_modeset_enables(state); |
896e5bb0 | 15621 | |
24a7bfe0 ID |
15622 | if (state->modeset) { |
15623 | intel_encoders_update_complete(state); | |
15624 | ||
5604e9ce | 15625 | intel_set_cdclk_post_plane_update(state); |
24a7bfe0 | 15626 | } |
59f9e9ca | 15627 | |
94f05024 DV |
15628 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
15629 | * already, but still need the state for the delayed optimization. To | |
15630 | * fix this: | |
15631 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
15632 | * - schedule that vblank worker _before_ calling hw_done | |
15633 | * - at the start of commit_tail, cancel it _synchrously | |
15634 | * - switch over to the vblank wait helper in the core after that since | |
15635 | * we don't need out special handling any more. | |
15636 | */ | |
855e0d68 | 15637 | drm_atomic_helper_wait_for_flip_done(dev, &state->base); |
5a21b665 | 15638 | |
855e0d68 | 15639 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |
1326a92c | 15640 | if (new_crtc_state->hw.active && |
855e0d68 | 15641 | !needs_modeset(new_crtc_state) && |
0ccc42a2 | 15642 | !new_crtc_state->preload_luts && |
2225f3c6 | 15643 | (new_crtc_state->uapi.color_mgmt_changed || |
855e0d68 ML |
15644 | new_crtc_state->update_pipe)) |
15645 | intel_color_load_luts(new_crtc_state); | |
051a6d8d VS |
15646 | } |
15647 | ||
5a21b665 DV |
15648 | /* |
15649 | * Now that the vblank has passed, we can go ahead and program the | |
15650 | * optimal watermarks on platforms that need two-step watermark | |
15651 | * programming. | |
15652 | * | |
15653 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
15654 | */ | |
7181f5c5 VS |
15655 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, |
15656 | new_crtc_state, i) { | |
15657 | /* | |
15658 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
15659 | * So re-enable underrun reporting after some planes get enabled. | |
15660 | * | |
15661 | * We do this before .optimize_watermarks() so that we have a | |
15662 | * chance of catching underruns with the intermediate watermarks | |
15663 | * vs. the new plane configuration. | |
15664 | */ | |
15665 | if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state)) | |
15666 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
15667 | ||
5a21b665 | 15668 | if (dev_priv->display.optimize_watermarks) |
7a8fdb1f | 15669 | dev_priv->display.optimize_watermarks(state, crtc); |
5a21b665 DV |
15670 | } |
15671 | ||
c7c0e7eb | 15672 | intel_dbuf_post_plane_update(state); |
b06cf595 | 15673 | |
855e0d68 | 15674 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
bee43ca4 | 15675 | intel_post_plane_update(state, crtc); |
5a21b665 DV |
15676 | |
15677 | if (put_domains[i]) | |
15678 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
15679 | ||
aa5e9b47 | 15680 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
afeda4f3 AM |
15681 | |
15682 | /* | |
15683 | * DSB cleanup is done in cleanup_work aligning with framebuffer | |
15684 | * cleanup. So copy and reset the dsb structure to sync with | |
15685 | * commit_done and later do dsb cleanup in cleanup_work. | |
15686 | */ | |
15687 | old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); | |
5a21b665 DV |
15688 | } |
15689 | ||
7181f5c5 VS |
15690 | /* Underruns don't always raise interrupts, so check manually */ |
15691 | intel_check_cpu_fifo_underruns(dev_priv); | |
15692 | intel_check_pch_fifo_underruns(dev_priv); | |
15693 | ||
ecab0f3d | 15694 | if (state->modeset) |
855e0d68 | 15695 | intel_verify_planes(state); |
cff109f0 | 15696 | |
ecab0f3d | 15697 | intel_sagv_post_plane_update(state); |
656d1b89 | 15698 | |
855e0d68 | 15699 | drm_atomic_helper_commit_hw_done(&state->base); |
94f05024 | 15700 | |
855e0d68 | 15701 | if (state->modeset) { |
d5553c09 CW |
15702 | /* As one of the primary mmio accessors, KMS has a high |
15703 | * likelihood of triggering bugs in unclaimed access. After we | |
15704 | * finish modesetting, see if an error has been flagged, and if | |
15705 | * so enable debugging for the next modeset - and hope we catch | |
15706 | * the culprit. | |
15707 | */ | |
2cf7bf6f | 15708 | intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); |
0e6e0be4 | 15709 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); |
d5553c09 | 15710 | } |
855e0d68 | 15711 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); |
5a21b665 | 15712 | |
8d52e447 CW |
15713 | /* |
15714 | * Defer the cleanup of the old state to a separate worker to not | |
15715 | * impede the current task (userspace for blocking modesets) that | |
15716 | * are executed inline. For out-of-line asynchronous modesets/flips, | |
15717 | * deferring to a new worker seems overkill, but we would place a | |
15718 | * schedule point (cond_resched()) here anyway to keep latencies | |
15719 | * down. | |
15720 | */ | |
855e0d68 ML |
15721 | INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); |
15722 | queue_work(system_highpri_wq, &state->base.commit_work); | |
94f05024 DV |
15723 | } |
15724 | ||
15725 | static void intel_atomic_commit_work(struct work_struct *work) | |
15726 | { | |
855e0d68 ML |
15727 | struct intel_atomic_state *state = |
15728 | container_of(work, struct intel_atomic_state, base.commit_work); | |
c004a90b | 15729 | |
94f05024 DV |
15730 | intel_atomic_commit_tail(state); |
15731 | } | |
15732 | ||
c004a90b CW |
15733 | static int __i915_sw_fence_call |
15734 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
15735 | enum i915_sw_fence_notify notify) | |
15736 | { | |
15737 | struct intel_atomic_state *state = | |
15738 | container_of(fence, struct intel_atomic_state, commit_ready); | |
15739 | ||
15740 | switch (notify) { | |
15741 | case FENCE_COMPLETE: | |
42b062b0 | 15742 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 15743 | break; |
c004a90b | 15744 | case FENCE_FREE: |
eb955eee CW |
15745 | { |
15746 | struct intel_atomic_helper *helper = | |
15747 | &to_i915(state->base.dev)->atomic_helper; | |
15748 | ||
15749 | if (llist_add(&state->freed, &helper->free_list)) | |
15750 | schedule_work(&helper->free_work); | |
15751 | break; | |
15752 | } | |
c004a90b CW |
15753 | } |
15754 | ||
15755 | return NOTIFY_DONE; | |
15756 | } | |
15757 | ||
e3b4089c | 15758 | static void intel_atomic_track_fbs(struct intel_atomic_state *state) |
6c9c1b38 | 15759 | { |
e3b4089c VS |
15760 | struct intel_plane_state *old_plane_state, *new_plane_state; |
15761 | struct intel_plane *plane; | |
6c9c1b38 DV |
15762 | int i; |
15763 | ||
e3b4089c VS |
15764 | for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, |
15765 | new_plane_state, i) | |
7b3cb17a ML |
15766 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), |
15767 | to_intel_frontbuffer(new_plane_state->hw.fb), | |
8e7cb179 | 15768 | plane->frontbuffer_bit); |
6c9c1b38 DV |
15769 | } |
15770 | ||
94f05024 | 15771 | static int intel_atomic_commit(struct drm_device *dev, |
a85fb467 | 15772 | struct drm_atomic_state *_state, |
94f05024 DV |
15773 | bool nonblock) |
15774 | { | |
a85fb467 | 15775 | struct intel_atomic_state *state = to_intel_atomic_state(_state); |
fac5e23e | 15776 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
15777 | int ret = 0; |
15778 | ||
a85fb467 | 15779 | state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
2e2f08d0 | 15780 | |
a85fb467 VS |
15781 | drm_atomic_state_get(&state->base); |
15782 | i915_sw_fence_init(&state->commit_ready, | |
c004a90b | 15783 | intel_atomic_commit_ready); |
94f05024 | 15784 | |
440df938 VS |
15785 | /* |
15786 | * The intel_legacy_cursor_update() fast path takes care | |
15787 | * of avoiding the vblank waits for simple cursor | |
15788 | * movement and flips. For cursor on/off and size changes, | |
15789 | * we want to perform the vblank waits so that watermark | |
15790 | * updates happen during the correct frames. Gen9+ have | |
15791 | * double buffered watermarks and so shouldn't need this. | |
15792 | * | |
3cf50c63 ML |
15793 | * Unset state->legacy_cursor_update before the call to |
15794 | * drm_atomic_helper_setup_commit() because otherwise | |
15795 | * drm_atomic_helper_wait_for_flip_done() is a noop and | |
15796 | * we get FIFO underruns because we didn't wait | |
15797 | * for vblank. | |
440df938 VS |
15798 | * |
15799 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
15800 | * (assuming we had any) would solve these problems. | |
15801 | */ | |
a85fb467 | 15802 | if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) { |
213f1bd0 ML |
15803 | struct intel_crtc_state *new_crtc_state; |
15804 | struct intel_crtc *crtc; | |
15805 | int i; | |
15806 | ||
a85fb467 | 15807 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) |
213f1bd0 ML |
15808 | if (new_crtc_state->wm.need_postvbl_update || |
15809 | new_crtc_state->update_wm_post) | |
a85fb467 | 15810 | state->base.legacy_cursor_update = false; |
213f1bd0 | 15811 | } |
440df938 | 15812 | |
a85fb467 | 15813 | ret = intel_atomic_prepare_commit(state); |
3cf50c63 | 15814 | if (ret) { |
cd49f818 WK |
15815 | drm_dbg_atomic(&dev_priv->drm, |
15816 | "Preparing state failed with %i\n", ret); | |
a85fb467 VS |
15817 | i915_sw_fence_commit(&state->commit_ready); |
15818 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); | |
3cf50c63 ML |
15819 | return ret; |
15820 | } | |
15821 | ||
a85fb467 | 15822 | ret = drm_atomic_helper_setup_commit(&state->base, nonblock); |
3cf50c63 | 15823 | if (!ret) |
a85fb467 | 15824 | ret = drm_atomic_helper_swap_state(&state->base, true); |
0ef1905e VS |
15825 | if (!ret) |
15826 | intel_atomic_swap_global_state(state); | |
3cf50c63 | 15827 | |
0806f4ee | 15828 | if (ret) { |
afeda4f3 AM |
15829 | struct intel_crtc_state *new_crtc_state; |
15830 | struct intel_crtc *crtc; | |
15831 | int i; | |
15832 | ||
a85fb467 | 15833 | i915_sw_fence_commit(&state->commit_ready); |
0806f4ee | 15834 | |
afeda4f3 AM |
15835 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) |
15836 | intel_dsb_cleanup(new_crtc_state); | |
15837 | ||
a85fb467 VS |
15838 | drm_atomic_helper_cleanup_planes(dev, &state->base); |
15839 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); | |
0806f4ee ML |
15840 | return ret; |
15841 | } | |
94f05024 | 15842 | dev_priv->wm.distrust_bios_wm = false; |
a85fb467 VS |
15843 | intel_shared_dpll_swap_state(state); |
15844 | intel_atomic_track_fbs(state); | |
94f05024 | 15845 | |
a85fb467 VS |
15846 | drm_atomic_state_get(&state->base); |
15847 | INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); | |
c004a90b | 15848 | |
a85fb467 VS |
15849 | i915_sw_fence_commit(&state->commit_ready); |
15850 | if (nonblock && state->modeset) { | |
15851 | queue_work(dev_priv->modeset_wq, &state->base.commit_work); | |
757fffcf | 15852 | } else if (nonblock) { |
c26a0586 | 15853 | queue_work(dev_priv->flip_wq, &state->base.commit_work); |
757fffcf | 15854 | } else { |
a85fb467 | 15855 | if (state->modeset) |
757fffcf | 15856 | flush_workqueue(dev_priv->modeset_wq); |
a85fb467 | 15857 | intel_atomic_commit_tail(state); |
757fffcf | 15858 | } |
75714940 | 15859 | |
74c090b1 | 15860 | return 0; |
7f27126e JB |
15861 | } |
15862 | ||
74d290f8 CW |
15863 | struct wait_rps_boost { |
15864 | struct wait_queue_entry wait; | |
15865 | ||
15866 | struct drm_crtc *crtc; | |
e61e0f51 | 15867 | struct i915_request *request; |
74d290f8 CW |
15868 | }; |
15869 | ||
15870 | static int do_rps_boost(struct wait_queue_entry *_wait, | |
15871 | unsigned mode, int sync, void *key) | |
15872 | { | |
15873 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); | |
e61e0f51 | 15874 | struct i915_request *rq = wait->request; |
74d290f8 | 15875 | |
e9af4ea2 CW |
15876 | /* |
15877 | * If we missed the vblank, but the request is already running it | |
15878 | * is reasonable to assume that it will complete before the next | |
15879 | * vblank without our intervention, so leave RPS alone. | |
15880 | */ | |
e61e0f51 | 15881 | if (!i915_request_started(rq)) |
3e7abf81 | 15882 | intel_rps_boost(rq); |
e61e0f51 | 15883 | i915_request_put(rq); |
74d290f8 CW |
15884 | |
15885 | drm_crtc_vblank_put(wait->crtc); | |
15886 | ||
15887 | list_del(&wait->wait.entry); | |
15888 | kfree(wait); | |
15889 | return 1; | |
15890 | } | |
15891 | ||
15892 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, | |
15893 | struct dma_fence *fence) | |
15894 | { | |
15895 | struct wait_rps_boost *wait; | |
15896 | ||
15897 | if (!dma_fence_is_i915(fence)) | |
15898 | return; | |
15899 | ||
15900 | if (INTEL_GEN(to_i915(crtc->dev)) < 6) | |
15901 | return; | |
15902 | ||
15903 | if (drm_crtc_vblank_get(crtc)) | |
15904 | return; | |
15905 | ||
15906 | wait = kmalloc(sizeof(*wait), GFP_KERNEL); | |
15907 | if (!wait) { | |
15908 | drm_crtc_vblank_put(crtc); | |
15909 | return; | |
15910 | } | |
15911 | ||
15912 | wait->request = to_request(dma_fence_get(fence)); | |
15913 | wait->crtc = crtc; | |
15914 | ||
15915 | wait->wait.func = do_rps_boost; | |
15916 | wait->wait.flags = 0; | |
15917 | ||
15918 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); | |
15919 | } | |
15920 | ||
ef1a1914 VS |
15921 | static int intel_plane_pin_fb(struct intel_plane_state *plane_state) |
15922 | { | |
f90a85e7 | 15923 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); |
ef1a1914 | 15924 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
7b3cb17a | 15925 | struct drm_framebuffer *fb = plane_state->hw.fb; |
ef1a1914 VS |
15926 | struct i915_vma *vma; |
15927 | ||
15928 | if (plane->id == PLANE_CURSOR && | |
d53db442 | 15929 | INTEL_INFO(dev_priv)->display.cursor_needs_physical) { |
ef1a1914 VS |
15930 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
15931 | const int align = intel_cursor_alignment(dev_priv); | |
4a477651 | 15932 | int err; |
ef1a1914 | 15933 | |
4a477651 CW |
15934 | err = i915_gem_object_attach_phys(obj, align); |
15935 | if (err) | |
15936 | return err; | |
ef1a1914 VS |
15937 | } |
15938 | ||
15939 | vma = intel_pin_and_fence_fb_obj(fb, | |
f5929c53 | 15940 | &plane_state->view, |
ef1a1914 VS |
15941 | intel_plane_uses_fence(plane_state), |
15942 | &plane_state->flags); | |
15943 | if (IS_ERR(vma)) | |
15944 | return PTR_ERR(vma); | |
15945 | ||
15946 | plane_state->vma = vma; | |
15947 | ||
15948 | return 0; | |
15949 | } | |
15950 | ||
15951 | static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) | |
15952 | { | |
15953 | struct i915_vma *vma; | |
15954 | ||
15955 | vma = fetch_and_zero(&old_plane_state->vma); | |
15956 | if (vma) | |
15957 | intel_unpin_fb_vma(vma, old_plane_state->flags); | |
15958 | } | |
15959 | ||
b7268c5e CW |
15960 | static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) |
15961 | { | |
15962 | struct i915_sched_attr attr = { | |
058179e7 | 15963 | .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY), |
b7268c5e CW |
15964 | }; |
15965 | ||
15966 | i915_gem_object_wait_priority(obj, 0, &attr); | |
15967 | } | |
15968 | ||
6beb8c23 MR |
15969 | /** |
15970 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
723196f4 | 15971 | * @_plane: drm plane to prepare for |
1fd37669 | 15972 | * @_new_plane_state: the plane state being prepared |
6beb8c23 MR |
15973 | * |
15974 | * Prepares a framebuffer for usage on a display plane. Generally this | |
15975 | * involves pinning the underlying object and updating the frontbuffer tracking | |
15976 | * bits. Some older platforms need special physical address handling for | |
15977 | * cursor planes. | |
15978 | * | |
15979 | * Returns 0 on success, negative error code on failure. | |
15980 | */ | |
15981 | int | |
b2faf669 | 15982 | intel_prepare_plane_fb(struct drm_plane *_plane, |
04c8b0bf | 15983 | struct drm_plane_state *_new_plane_state) |
465c120c | 15984 | { |
b2faf669 | 15985 | struct intel_plane *plane = to_intel_plane(_plane); |
04c8b0bf ML |
15986 | struct intel_plane_state *new_plane_state = |
15987 | to_intel_plane_state(_new_plane_state); | |
fa528334 | 15988 | struct intel_atomic_state *state = |
f90a85e7 | 15989 | to_intel_atomic_state(new_plane_state->uapi.state); |
b2faf669 VS |
15990 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
15991 | const struct intel_plane_state *old_plane_state = | |
fa528334 | 15992 | intel_atomic_get_old_plane_state(state, plane); |
b2faf669 VS |
15993 | struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb); |
15994 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb); | |
c004a90b | 15995 | int ret; |
465c120c | 15996 | |
5008e874 | 15997 | if (old_obj) { |
b2faf669 | 15998 | const struct intel_crtc_state *crtc_state = |
fa528334 | 15999 | intel_atomic_get_new_crtc_state(state, |
b2faf669 | 16000 | to_intel_crtc(old_plane_state->hw.crtc)); |
5008e874 ML |
16001 | |
16002 | /* Big Hammer, we also need to ensure that any pending | |
16003 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
16004 | * current scanout is retired before unpinning the old | |
16005 | * framebuffer. Note that we rely on userspace rendering | |
16006 | * into the buffer attached to the pipe they are waiting | |
16007 | * on. If not, userspace generates a GPU hang with IPEHR | |
16008 | * point to the MI_WAIT_FOR_EVENT. | |
16009 | * | |
16010 | * This should only fail upon a hung GPU, in which case we | |
16011 | * can safely continue. | |
16012 | */ | |
c004a90b | 16013 | if (needs_modeset(crtc_state)) { |
fa528334 | 16014 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
ef78f7b1 | 16015 | old_obj->base.resv, NULL, |
c004a90b CW |
16016 | false, 0, |
16017 | GFP_KERNEL); | |
16018 | if (ret < 0) | |
16019 | return ret; | |
f4457ae7 | 16020 | } |
5008e874 ML |
16021 | } |
16022 | ||
f90a85e7 | 16023 | if (new_plane_state->uapi.fence) { /* explicit fencing */ |
fa528334 | 16024 | ret = i915_sw_fence_await_dma_fence(&state->commit_ready, |
f90a85e7 | 16025 | new_plane_state->uapi.fence, |
16dc224f | 16026 | i915_fence_timeout(dev_priv), |
c004a90b CW |
16027 | GFP_KERNEL); |
16028 | if (ret < 0) | |
16029 | return ret; | |
16030 | } | |
16031 | ||
c37efb99 CW |
16032 | if (!obj) |
16033 | return 0; | |
16034 | ||
4d3088c7 | 16035 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
16036 | if (ret) |
16037 | return ret; | |
16038 | ||
04c8b0bf | 16039 | ret = intel_plane_pin_fb(new_plane_state); |
fd70075f | 16040 | |
4d3088c7 | 16041 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
16042 | if (ret) |
16043 | return ret; | |
16044 | ||
e2f3496e | 16045 | fb_obj_bump_render_priority(obj); |
da42104f | 16046 | i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB); |
07bcd99b | 16047 | |
f90a85e7 | 16048 | if (!new_plane_state->uapi.fence) { /* implicit fencing */ |
74d290f8 CW |
16049 | struct dma_fence *fence; |
16050 | ||
fa528334 | 16051 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
ef78f7b1 | 16052 | obj->base.resv, NULL, |
16dc224f CW |
16053 | false, |
16054 | i915_fence_timeout(dev_priv), | |
c004a90b CW |
16055 | GFP_KERNEL); |
16056 | if (ret < 0) | |
6fef8510 | 16057 | goto unpin_fb; |
74d290f8 | 16058 | |
52791eee | 16059 | fence = dma_resv_get_excl_rcu(obj->base.resv); |
74d290f8 | 16060 | if (fence) { |
7b3cb17a | 16061 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
04c8b0bf | 16062 | fence); |
74d290f8 CW |
16063 | dma_fence_put(fence); |
16064 | } | |
16065 | } else { | |
7b3cb17a | 16066 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
f90a85e7 | 16067 | new_plane_state->uapi.fence); |
c004a90b | 16068 | } |
5a21b665 | 16069 | |
60548c55 CW |
16070 | /* |
16071 | * We declare pageflips to be interactive and so merit a small bias | |
16072 | * towards upclocking to deliver the frame on time. By only changing | |
16073 | * the RPS thresholds to sample more regularly and aim for higher | |
16074 | * clocks we can hopefully deliver low power workloads (like kodi) | |
16075 | * that are not quite steady state without resorting to forcing | |
16076 | * maximum clocks following a vblank miss (see do_rps_boost()). | |
16077 | */ | |
fa528334 | 16078 | if (!state->rps_interactive) { |
3e7abf81 | 16079 | intel_rps_mark_interactive(&dev_priv->gt.rps, true); |
fa528334 | 16080 | state->rps_interactive = true; |
60548c55 CW |
16081 | } |
16082 | ||
d07f0e59 | 16083 | return 0; |
6fef8510 VS |
16084 | |
16085 | unpin_fb: | |
16086 | intel_plane_unpin_fb(new_plane_state); | |
16087 | ||
16088 | return ret; | |
6beb8c23 MR |
16089 | } |
16090 | ||
38f3ce3a MR |
16091 | /** |
16092 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
16093 | * @plane: drm plane to clean up for | |
1fd37669 | 16094 | * @_old_plane_state: the state from the previous modeset |
38f3ce3a MR |
16095 | * |
16096 | * Cleans up a framebuffer that has just been removed from a plane. | |
16097 | */ | |
16098 | void | |
16099 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
04c8b0bf | 16100 | struct drm_plane_state *_old_plane_state) |
38f3ce3a | 16101 | { |
04c8b0bf ML |
16102 | struct intel_plane_state *old_plane_state = |
16103 | to_intel_plane_state(_old_plane_state); | |
fa528334 | 16104 | struct intel_atomic_state *state = |
f90a85e7 | 16105 | to_intel_atomic_state(old_plane_state->uapi.state); |
ef1a1914 | 16106 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
58fa1760 VS |
16107 | struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb); |
16108 | ||
16109 | if (!obj) | |
16110 | return; | |
38f3ce3a | 16111 | |
fa528334 | 16112 | if (state->rps_interactive) { |
3e7abf81 | 16113 | intel_rps_mark_interactive(&dev_priv->gt.rps, false); |
fa528334 | 16114 | state->rps_interactive = false; |
60548c55 CW |
16115 | } |
16116 | ||
be1e3415 | 16117 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
04c8b0bf | 16118 | intel_plane_unpin_fb(old_plane_state); |
465c120c MR |
16119 | } |
16120 | ||
cf4c7c12 | 16121 | /** |
4a3b8769 MR |
16122 | * intel_plane_destroy - destroy a plane |
16123 | * @plane: plane to destroy | |
cf4c7c12 | 16124 | * |
4a3b8769 MR |
16125 | * Common destruction function for all types of planes (primary, cursor, |
16126 | * sprite). | |
cf4c7c12 | 16127 | */ |
4a3b8769 | 16128 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 16129 | { |
465c120c | 16130 | drm_plane_cleanup(plane); |
69ae561f | 16131 | kfree(to_intel_plane(plane)); |
465c120c MR |
16132 | } |
16133 | ||
a38189c5 VS |
16134 | static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, |
16135 | u32 format, u64 modifier) | |
714244e2 | 16136 | { |
a38189c5 VS |
16137 | switch (modifier) { |
16138 | case DRM_FORMAT_MOD_LINEAR: | |
16139 | case I915_FORMAT_MOD_X_TILED: | |
16140 | break; | |
16141 | default: | |
16142 | return false; | |
16143 | } | |
16144 | ||
714244e2 BW |
16145 | switch (format) { |
16146 | case DRM_FORMAT_C8: | |
16147 | case DRM_FORMAT_RGB565: | |
16148 | case DRM_FORMAT_XRGB1555: | |
16149 | case DRM_FORMAT_XRGB8888: | |
16150 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
16151 | modifier == I915_FORMAT_MOD_X_TILED; | |
16152 | default: | |
16153 | return false; | |
16154 | } | |
16155 | } | |
16156 | ||
a38189c5 VS |
16157 | static bool i965_plane_format_mod_supported(struct drm_plane *_plane, |
16158 | u32 format, u64 modifier) | |
714244e2 | 16159 | { |
a38189c5 VS |
16160 | switch (modifier) { |
16161 | case DRM_FORMAT_MOD_LINEAR: | |
16162 | case I915_FORMAT_MOD_X_TILED: | |
16163 | break; | |
16164 | default: | |
16165 | return false; | |
16166 | } | |
16167 | ||
714244e2 BW |
16168 | switch (format) { |
16169 | case DRM_FORMAT_C8: | |
16170 | case DRM_FORMAT_RGB565: | |
16171 | case DRM_FORMAT_XRGB8888: | |
16172 | case DRM_FORMAT_XBGR8888: | |
73263cb6 VS |
16173 | case DRM_FORMAT_ARGB8888: |
16174 | case DRM_FORMAT_ABGR8888: | |
714244e2 BW |
16175 | case DRM_FORMAT_XRGB2101010: |
16176 | case DRM_FORMAT_XBGR2101010: | |
73263cb6 VS |
16177 | case DRM_FORMAT_ARGB2101010: |
16178 | case DRM_FORMAT_ABGR2101010: | |
03b0ce95 | 16179 | case DRM_FORMAT_XBGR16161616F: |
714244e2 BW |
16180 | return modifier == DRM_FORMAT_MOD_LINEAR || |
16181 | modifier == I915_FORMAT_MOD_X_TILED; | |
16182 | default: | |
16183 | return false; | |
16184 | } | |
16185 | } | |
16186 | ||
a38189c5 VS |
16187 | static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, |
16188 | u32 format, u64 modifier) | |
714244e2 | 16189 | { |
a38189c5 VS |
16190 | return modifier == DRM_FORMAT_MOD_LINEAR && |
16191 | format == DRM_FORMAT_ARGB8888; | |
714244e2 BW |
16192 | } |
16193 | ||
679bfe84 | 16194 | static const struct drm_plane_funcs i965_plane_funcs = { |
a38189c5 VS |
16195 | .update_plane = drm_atomic_helper_update_plane, |
16196 | .disable_plane = drm_atomic_helper_disable_plane, | |
16197 | .destroy = intel_plane_destroy, | |
a38189c5 VS |
16198 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16199 | .atomic_destroy_state = intel_plane_destroy_state, | |
16200 | .format_mod_supported = i965_plane_format_mod_supported, | |
16201 | }; | |
714244e2 | 16202 | |
679bfe84 | 16203 | static const struct drm_plane_funcs i8xx_plane_funcs = { |
70a101f8 MR |
16204 | .update_plane = drm_atomic_helper_update_plane, |
16205 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 16206 | .destroy = intel_plane_destroy, |
ea2c67bb MR |
16207 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16208 | .atomic_destroy_state = intel_plane_destroy_state, | |
a38189c5 | 16209 | .format_mod_supported = i8xx_plane_format_mod_supported, |
465c120c MR |
16210 | }; |
16211 | ||
f79f2692 | 16212 | static int |
4078c983 VS |
16213 | intel_legacy_cursor_update(struct drm_plane *_plane, |
16214 | struct drm_crtc *_crtc, | |
f79f2692 ML |
16215 | struct drm_framebuffer *fb, |
16216 | int crtc_x, int crtc_y, | |
16217 | unsigned int crtc_w, unsigned int crtc_h, | |
ba3f4d0a JN |
16218 | u32 src_x, u32 src_y, |
16219 | u32 src_w, u32 src_h, | |
34a2ab5e | 16220 | struct drm_modeset_acquire_ctx *ctx) |
f79f2692 | 16221 | { |
4078c983 VS |
16222 | struct intel_plane *plane = to_intel_plane(_plane); |
16223 | struct intel_crtc *crtc = to_intel_crtc(_crtc); | |
16224 | struct intel_plane_state *old_plane_state = | |
16225 | to_intel_plane_state(plane->base.state); | |
16226 | struct intel_plane_state *new_plane_state; | |
c249c5f6 | 16227 | struct intel_crtc_state *crtc_state = |
4078c983 | 16228 | to_intel_crtc_state(crtc->base.state); |
c249c5f6 | 16229 | struct intel_crtc_state *new_crtc_state; |
8e7cb179 | 16230 | int ret; |
f79f2692 ML |
16231 | |
16232 | /* | |
16233 | * When crtc is inactive or there is a modeset pending, | |
16234 | * wait for it to complete in the slowpath | |
16235 | */ | |
1326a92c | 16236 | if (!crtc_state->hw.active || needs_modeset(crtc_state) || |
c249c5f6 | 16237 | crtc_state->update_pipe) |
f79f2692 ML |
16238 | goto slow; |
16239 | ||
669c9215 ML |
16240 | /* |
16241 | * Don't do an async update if there is an outstanding commit modifying | |
16242 | * the plane. This prevents our async update's changes from getting | |
16243 | * overridden by a previous synchronous update's state. | |
16244 | */ | |
f90a85e7 ML |
16245 | if (old_plane_state->uapi.commit && |
16246 | !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) | |
669c9215 | 16247 | goto slow; |
f79f2692 ML |
16248 | |
16249 | /* | |
16250 | * If any parameters change that may affect watermarks, | |
16251 | * take the slowpath. Only changing fb or position should be | |
16252 | * in the fastpath. | |
16253 | */ | |
a456f65f ML |
16254 | if (old_plane_state->uapi.crtc != &crtc->base || |
16255 | old_plane_state->uapi.src_w != src_w || | |
16256 | old_plane_state->uapi.src_h != src_h || | |
16257 | old_plane_state->uapi.crtc_w != crtc_w || | |
16258 | old_plane_state->uapi.crtc_h != crtc_h || | |
16259 | !old_plane_state->uapi.fb != !fb) | |
f79f2692 ML |
16260 | goto slow; |
16261 | ||
4078c983 | 16262 | new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); |
f79f2692 ML |
16263 | if (!new_plane_state) |
16264 | return -ENOMEM; | |
16265 | ||
4078c983 | 16266 | new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); |
c249c5f6 ML |
16267 | if (!new_crtc_state) { |
16268 | ret = -ENOMEM; | |
16269 | goto out_free; | |
16270 | } | |
16271 | ||
a456f65f | 16272 | drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); |
f79f2692 | 16273 | |
a456f65f ML |
16274 | new_plane_state->uapi.src_x = src_x; |
16275 | new_plane_state->uapi.src_y = src_y; | |
16276 | new_plane_state->uapi.src_w = src_w; | |
16277 | new_plane_state->uapi.src_h = src_h; | |
16278 | new_plane_state->uapi.crtc_x = crtc_x; | |
16279 | new_plane_state->uapi.crtc_y = crtc_y; | |
16280 | new_plane_state->uapi.crtc_w = crtc_w; | |
16281 | new_plane_state->uapi.crtc_h = crtc_h; | |
f79f2692 | 16282 | |
7d8d2cbc VS |
16283 | intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); |
16284 | ||
c249c5f6 | 16285 | ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, |
4078c983 | 16286 | old_plane_state, new_plane_state); |
f79f2692 ML |
16287 | if (ret) |
16288 | goto out_free; | |
16289 | ||
4078c983 | 16290 | ret = intel_plane_pin_fb(new_plane_state); |
ef1a1914 | 16291 | if (ret) |
2850748e | 16292 | goto out_free; |
f79f2692 | 16293 | |
a456f65f ML |
16294 | intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), |
16295 | ORIGIN_FLIP); | |
16296 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), | |
16297 | to_intel_frontbuffer(new_plane_state->hw.fb), | |
4078c983 | 16298 | plane->frontbuffer_bit); |
f79f2692 ML |
16299 | |
16300 | /* Swap plane state */ | |
a456f65f | 16301 | plane->base.state = &new_plane_state->uapi; |
f79f2692 | 16302 | |
c249c5f6 ML |
16303 | /* |
16304 | * We cannot swap crtc_state as it may be in use by an atomic commit or | |
16305 | * page flip that's running simultaneously. If we swap crtc_state and | |
16306 | * destroy the old state, we will cause a use-after-free there. | |
16307 | * | |
16308 | * Only update active_planes, which is needed for our internal | |
16309 | * bookkeeping. Either value will do the right thing when updating | |
16310 | * planes atomically. If the cursor was part of the atomic update then | |
16311 | * we would have taken the slowpath. | |
16312 | */ | |
16313 | crtc_state->active_planes = new_crtc_state->active_planes; | |
16314 | ||
a456f65f | 16315 | if (new_plane_state->uapi.visible) |
4078c983 | 16316 | intel_update_plane(plane, crtc_state, new_plane_state); |
c48b86f9 | 16317 | else |
4078c983 | 16318 | intel_disable_plane(plane, crtc_state); |
f79f2692 | 16319 | |
4078c983 | 16320 | intel_plane_unpin_fb(old_plane_state); |
f79f2692 | 16321 | |
f79f2692 | 16322 | out_free: |
c249c5f6 | 16323 | if (new_crtc_state) |
2225f3c6 | 16324 | intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); |
669c9215 | 16325 | if (ret) |
a456f65f | 16326 | intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); |
669c9215 | 16327 | else |
a456f65f | 16328 | intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); |
f79f2692 ML |
16329 | return ret; |
16330 | ||
f79f2692 | 16331 | slow: |
4078c983 | 16332 | return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, |
f79f2692 | 16333 | crtc_x, crtc_y, crtc_w, crtc_h, |
34a2ab5e | 16334 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
16335 | } |
16336 | ||
16337 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
16338 | .update_plane = intel_legacy_cursor_update, | |
16339 | .disable_plane = drm_atomic_helper_disable_plane, | |
16340 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
16341 | .atomic_duplicate_state = intel_plane_duplicate_state, |
16342 | .atomic_destroy_state = intel_plane_destroy_state, | |
a38189c5 | 16343 | .format_mod_supported = intel_cursor_format_mod_supported, |
f79f2692 ML |
16344 | }; |
16345 | ||
cf1805e6 VS |
16346 | static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, |
16347 | enum i9xx_plane_id i9xx_plane) | |
16348 | { | |
16349 | if (!HAS_FBC(dev_priv)) | |
16350 | return false; | |
16351 | ||
16352 | if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
16353 | return i9xx_plane == PLANE_A; /* tied to pipe A */ | |
16354 | else if (IS_IVYBRIDGE(dev_priv)) | |
16355 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || | |
16356 | i9xx_plane == PLANE_C; | |
16357 | else if (INTEL_GEN(dev_priv) >= 4) | |
16358 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; | |
16359 | else | |
16360 | return i9xx_plane == PLANE_A; | |
16361 | } | |
16362 | ||
b079bd17 | 16363 | static struct intel_plane * |
580503c7 | 16364 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 16365 | { |
881440a8 | 16366 | struct intel_plane *plane; |
a38189c5 | 16367 | const struct drm_plane_funcs *plane_funcs; |
93ca7e00 | 16368 | unsigned int supported_rotations; |
881440a8 VS |
16369 | const u32 *formats; |
16370 | int num_formats; | |
ca9cab18 | 16371 | int ret, zpos; |
465c120c | 16372 | |
b7c80600 VS |
16373 | if (INTEL_GEN(dev_priv) >= 9) |
16374 | return skl_universal_plane_create(dev_priv, pipe, | |
16375 | PLANE_PRIMARY); | |
16376 | ||
881440a8 VS |
16377 | plane = intel_plane_alloc(); |
16378 | if (IS_ERR(plane)) | |
16379 | return plane; | |
ea2c67bb | 16380 | |
881440a8 | 16381 | plane->pipe = pipe; |
e3c566df VS |
16382 | /* |
16383 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
16384 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
16385 | */ | |
ddf08d32 VS |
16386 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 && |
16387 | INTEL_NUM_PIPES(dev_priv) == 2) | |
881440a8 | 16388 | plane->i9xx_plane = (enum i9xx_plane_id) !pipe; |
e3c566df | 16389 | else |
881440a8 VS |
16390 | plane->i9xx_plane = (enum i9xx_plane_id) pipe; |
16391 | plane->id = PLANE_PRIMARY; | |
16392 | plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); | |
cf1805e6 | 16393 | |
881440a8 VS |
16394 | plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); |
16395 | if (plane->has_fbc) { | |
cf1805e6 VS |
16396 | struct intel_fbc *fbc = &dev_priv->fbc; |
16397 | ||
881440a8 | 16398 | fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; |
cf1805e6 VS |
16399 | } |
16400 | ||
73263cb6 VS |
16401 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
16402 | formats = vlv_primary_formats; | |
16403 | num_formats = ARRAY_SIZE(vlv_primary_formats); | |
73263cb6 | 16404 | } else if (INTEL_GEN(dev_priv) >= 4) { |
03b0ce95 VS |
16405 | /* |
16406 | * WaFP16GammaEnabling:ivb | |
16407 | * "Workaround : When using the 64-bit format, the plane | |
16408 | * output on each color channel has one quarter amplitude. | |
16409 | * It can be brought up to full amplitude by using pipe | |
16410 | * gamma correction or pipe color space conversion to | |
16411 | * multiply the plane output by four." | |
16412 | * | |
16413 | * There is no dedicated plane gamma for the primary plane, | |
16414 | * and using the pipe gamma/csc could conflict with other | |
16415 | * planes, so we choose not to expose fp16 on IVB primary | |
16416 | * planes. HSW primary planes no longer have this problem. | |
16417 | */ | |
16418 | if (IS_IVYBRIDGE(dev_priv)) { | |
16419 | formats = ivb_primary_formats; | |
16420 | num_formats = ARRAY_SIZE(ivb_primary_formats); | |
16421 | } else { | |
16422 | formats = i965_primary_formats; | |
16423 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
16424 | } | |
6c0fd451 | 16425 | } else { |
881440a8 | 16426 | formats = i8xx_primary_formats; |
6c0fd451 | 16427 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
dbb1a6fb | 16428 | } |
a8d201af | 16429 | |
dbb1a6fb VS |
16430 | if (INTEL_GEN(dev_priv) >= 4) |
16431 | plane_funcs = &i965_plane_funcs; | |
16432 | else | |
16433 | plane_funcs = &i8xx_plane_funcs; | |
16434 | ||
16435 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
16436 | plane->min_cdclk = vlv_plane_min_cdclk; | |
16437 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
16438 | plane->min_cdclk = hsw_plane_min_cdclk; | |
16439 | else if (IS_IVYBRIDGE(dev_priv)) | |
16440 | plane->min_cdclk = ivb_plane_min_cdclk; | |
16441 | else | |
bb6ae9e6 | 16442 | plane->min_cdclk = i9xx_plane_min_cdclk; |
a38189c5 | 16443 | |
dbb1a6fb VS |
16444 | plane->max_stride = i9xx_plane_max_stride; |
16445 | plane->update_plane = i9xx_update_plane; | |
16446 | plane->disable_plane = i9xx_disable_plane; | |
16447 | plane->get_hw_state = i9xx_plane_get_hw_state; | |
16448 | plane->check_plane = i9xx_plane_check; | |
465c120c | 16449 | |
b7c80600 | 16450 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
881440a8 | 16451 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
6875eb3f | 16452 | 0, plane_funcs, |
dbb1a6fb VS |
16453 | formats, num_formats, |
16454 | i9xx_format_modifiers, | |
38573dc1 VS |
16455 | DRM_PLANE_TYPE_PRIMARY, |
16456 | "primary %c", pipe_name(pipe)); | |
16457 | else | |
881440a8 | 16458 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
6875eb3f | 16459 | 0, plane_funcs, |
dbb1a6fb VS |
16460 | formats, num_formats, |
16461 | i9xx_format_modifiers, | |
38573dc1 | 16462 | DRM_PLANE_TYPE_PRIMARY, |
ed15030d | 16463 | "plane %c", |
881440a8 | 16464 | plane_name(plane->i9xx_plane)); |
fca0ce2a VS |
16465 | if (ret) |
16466 | goto fail; | |
48404c1e | 16467 | |
b7c80600 | 16468 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
4ea7be2b | 16469 | supported_rotations = |
c2c446ad RF |
16470 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
16471 | DRM_MODE_REFLECT_X; | |
5481e27f | 16472 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 16473 | supported_rotations = |
c2c446ad | 16474 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 16475 | } else { |
c2c446ad | 16476 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
16477 | } |
16478 | ||
5481e27f | 16479 | if (INTEL_GEN(dev_priv) >= 4) |
881440a8 | 16480 | drm_plane_create_rotation_property(&plane->base, |
c2c446ad | 16481 | DRM_MODE_ROTATE_0, |
93ca7e00 | 16482 | supported_rotations); |
48404c1e | 16483 | |
ca9cab18 VS |
16484 | zpos = 0; |
16485 | drm_plane_create_zpos_immutable_property(&plane->base, zpos); | |
16486 | ||
881440a8 | 16487 | drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); |
ea2c67bb | 16488 | |
881440a8 | 16489 | return plane; |
fca0ce2a VS |
16490 | |
16491 | fail: | |
881440a8 | 16492 | intel_plane_free(plane); |
fca0ce2a | 16493 | |
b079bd17 | 16494 | return ERR_PTR(ret); |
465c120c MR |
16495 | } |
16496 | ||
b079bd17 | 16497 | static struct intel_plane * |
b2d03b0d VS |
16498 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
16499 | enum pipe pipe) | |
3d7d6510 | 16500 | { |
c539b579 | 16501 | struct intel_plane *cursor; |
ca9cab18 | 16502 | int ret, zpos; |
3d7d6510 | 16503 | |
c539b579 VS |
16504 | cursor = intel_plane_alloc(); |
16505 | if (IS_ERR(cursor)) | |
16506 | return cursor; | |
ea2c67bb | 16507 | |
3d7d6510 | 16508 | cursor->pipe = pipe; |
ed15030d | 16509 | cursor->i9xx_plane = (enum i9xx_plane_id) pipe; |
b14e5848 | 16510 | cursor->id = PLANE_CURSOR; |
c19e1124 | 16511 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); |
b2d03b0d VS |
16512 | |
16513 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
ddd5713d | 16514 | cursor->max_stride = i845_cursor_max_stride; |
b2d03b0d VS |
16515 | cursor->update_plane = i845_update_cursor; |
16516 | cursor->disable_plane = i845_disable_cursor; | |
51f5a096 | 16517 | cursor->get_hw_state = i845_cursor_get_hw_state; |
659056f2 | 16518 | cursor->check_plane = i845_check_cursor; |
b2d03b0d | 16519 | } else { |
ddd5713d | 16520 | cursor->max_stride = i9xx_cursor_max_stride; |
b2d03b0d VS |
16521 | cursor->update_plane = i9xx_update_cursor; |
16522 | cursor->disable_plane = i9xx_disable_cursor; | |
51f5a096 | 16523 | cursor->get_hw_state = i9xx_cursor_get_hw_state; |
659056f2 | 16524 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 16525 | } |
3d7d6510 | 16526 | |
cd5dcbf1 VS |
16527 | cursor->cursor.base = ~0; |
16528 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
16529 | |
16530 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
16531 | cursor->cursor.size = ~0; | |
3d7d6510 | 16532 | |
580503c7 | 16533 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
6875eb3f | 16534 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
16535 | intel_cursor_formats, |
16536 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
16537 | cursor_format_modifiers, |
16538 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 16539 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
16540 | if (ret) |
16541 | goto fail; | |
4398ad45 | 16542 | |
5481e27f | 16543 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 16544 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
16545 | DRM_MODE_ROTATE_0, |
16546 | DRM_MODE_ROTATE_0 | | |
16547 | DRM_MODE_ROTATE_180); | |
4398ad45 | 16548 | |
ca9cab18 VS |
16549 | zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; |
16550 | drm_plane_create_zpos_immutable_property(&cursor->base, zpos); | |
16551 | ||
093a3a30 JRS |
16552 | if (INTEL_GEN(dev_priv) >= 12) |
16553 | drm_plane_enable_fb_damage_clips(&cursor->base); | |
16554 | ||
ea2c67bb MR |
16555 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
16556 | ||
b079bd17 | 16557 | return cursor; |
fca0ce2a VS |
16558 | |
16559 | fail: | |
c539b579 | 16560 | intel_plane_free(cursor); |
fca0ce2a | 16561 | |
b079bd17 | 16562 | return ERR_PTR(ret); |
3d7d6510 MR |
16563 | } |
16564 | ||
08fa8fd0 VS |
16565 | #define INTEL_CRTC_FUNCS \ |
16566 | .gamma_set = drm_atomic_helper_legacy_gamma_set, \ | |
16567 | .set_config = drm_atomic_helper_set_config, \ | |
16568 | .destroy = intel_crtc_destroy, \ | |
16569 | .page_flip = drm_atomic_helper_page_flip, \ | |
16570 | .atomic_duplicate_state = intel_crtc_duplicate_state, \ | |
16571 | .atomic_destroy_state = intel_crtc_destroy_state, \ | |
16572 | .set_crc_source = intel_crtc_set_crc_source, \ | |
16573 | .verify_crc_source = intel_crtc_verify_crc_source, \ | |
16574 | .get_crc_sources = intel_crtc_get_crc_sources | |
16575 | ||
16576 | static const struct drm_crtc_funcs bdw_crtc_funcs = { | |
16577 | INTEL_CRTC_FUNCS, | |
16578 | ||
16579 | .get_vblank_counter = g4x_get_vblank_counter, | |
16580 | .enable_vblank = bdw_enable_vblank, | |
16581 | .disable_vblank = bdw_disable_vblank, | |
4bbffbf3 | 16582 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16583 | }; |
16584 | ||
16585 | static const struct drm_crtc_funcs ilk_crtc_funcs = { | |
16586 | INTEL_CRTC_FUNCS, | |
16587 | ||
16588 | .get_vblank_counter = g4x_get_vblank_counter, | |
16589 | .enable_vblank = ilk_enable_vblank, | |
16590 | .disable_vblank = ilk_disable_vblank, | |
4bbffbf3 | 16591 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16592 | }; |
16593 | ||
16594 | static const struct drm_crtc_funcs g4x_crtc_funcs = { | |
16595 | INTEL_CRTC_FUNCS, | |
16596 | ||
16597 | .get_vblank_counter = g4x_get_vblank_counter, | |
16598 | .enable_vblank = i965_enable_vblank, | |
16599 | .disable_vblank = i965_disable_vblank, | |
4bbffbf3 | 16600 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16601 | }; |
16602 | ||
16603 | static const struct drm_crtc_funcs i965_crtc_funcs = { | |
16604 | INTEL_CRTC_FUNCS, | |
16605 | ||
16606 | .get_vblank_counter = i915_get_vblank_counter, | |
16607 | .enable_vblank = i965_enable_vblank, | |
16608 | .disable_vblank = i965_disable_vblank, | |
4bbffbf3 | 16609 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16610 | }; |
16611 | ||
7d423af9 | 16612 | static const struct drm_crtc_funcs i915gm_crtc_funcs = { |
08fa8fd0 VS |
16613 | INTEL_CRTC_FUNCS, |
16614 | ||
16615 | .get_vblank_counter = i915_get_vblank_counter, | |
7d423af9 VS |
16616 | .enable_vblank = i915gm_enable_vblank, |
16617 | .disable_vblank = i915gm_disable_vblank, | |
4bbffbf3 | 16618 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16619 | }; |
16620 | ||
16621 | static const struct drm_crtc_funcs i915_crtc_funcs = { | |
16622 | INTEL_CRTC_FUNCS, | |
16623 | ||
16624 | .get_vblank_counter = i915_get_vblank_counter, | |
16625 | .enable_vblank = i8xx_enable_vblank, | |
16626 | .disable_vblank = i8xx_disable_vblank, | |
4bbffbf3 | 16627 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16628 | }; |
16629 | ||
16630 | static const struct drm_crtc_funcs i8xx_crtc_funcs = { | |
16631 | INTEL_CRTC_FUNCS, | |
16632 | ||
16633 | /* no hw vblank counter */ | |
16634 | .enable_vblank = i8xx_enable_vblank, | |
16635 | .disable_vblank = i8xx_disable_vblank, | |
4bbffbf3 | 16636 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
08fa8fd0 VS |
16637 | }; |
16638 | ||
66434539 | 16639 | static struct intel_crtc *intel_crtc_alloc(void) |
79e53945 | 16640 | { |
66434539 | 16641 | struct intel_crtc_state *crtc_state; |
f44bfa7f | 16642 | struct intel_crtc *crtc; |
79e53945 | 16643 | |
f44bfa7f VS |
16644 | crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); |
16645 | if (!crtc) | |
66434539 | 16646 | return ERR_PTR(-ENOMEM); |
79e53945 | 16647 | |
216383e9 | 16648 | crtc_state = intel_crtc_state_alloc(crtc); |
b079bd17 | 16649 | if (!crtc_state) { |
66434539 VS |
16650 | kfree(crtc); |
16651 | return ERR_PTR(-ENOMEM); | |
b079bd17 | 16652 | } |
66434539 | 16653 | |
979e94c1 | 16654 | crtc->base.state = &crtc_state->uapi; |
f44bfa7f | 16655 | crtc->config = crtc_state; |
f5de6e07 | 16656 | |
66434539 VS |
16657 | return crtc; |
16658 | } | |
16659 | ||
16660 | static void intel_crtc_free(struct intel_crtc *crtc) | |
16661 | { | |
16662 | intel_crtc_destroy_state(&crtc->base, crtc->base.state); | |
16663 | kfree(crtc); | |
16664 | } | |
16665 | ||
6875eb3f AG |
16666 | static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) |
16667 | { | |
16668 | struct intel_plane *plane; | |
16669 | ||
16670 | for_each_intel_plane(&dev_priv->drm, plane) { | |
16671 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, | |
16672 | plane->pipe); | |
16673 | ||
16674 | plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); | |
16675 | } | |
16676 | } | |
16677 | ||
66434539 VS |
16678 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
16679 | { | |
16680 | struct intel_plane *primary, *cursor; | |
16681 | const struct drm_crtc_funcs *funcs; | |
16682 | struct intel_crtc *crtc; | |
16683 | int sprite, ret; | |
16684 | ||
16685 | crtc = intel_crtc_alloc(); | |
16686 | if (IS_ERR(crtc)) | |
16687 | return PTR_ERR(crtc); | |
16688 | ||
16689 | crtc->pipe = pipe; | |
16690 | crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe]; | |
16691 | ||
580503c7 | 16692 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
16693 | if (IS_ERR(primary)) { |
16694 | ret = PTR_ERR(primary); | |
3d7d6510 | 16695 | goto fail; |
b079bd17 | 16696 | } |
f44bfa7f | 16697 | crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 16698 | |
a81d6fa0 | 16699 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
16700 | struct intel_plane *plane; |
16701 | ||
580503c7 | 16702 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 16703 | if (IS_ERR(plane)) { |
b079bd17 VS |
16704 | ret = PTR_ERR(plane); |
16705 | goto fail; | |
16706 | } | |
f44bfa7f | 16707 | crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
16708 | } |
16709 | ||
580503c7 | 16710 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 16711 | if (IS_ERR(cursor)) { |
b079bd17 | 16712 | ret = PTR_ERR(cursor); |
3d7d6510 | 16713 | goto fail; |
b079bd17 | 16714 | } |
f44bfa7f | 16715 | crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 16716 | |
08fa8fd0 VS |
16717 | if (HAS_GMCH(dev_priv)) { |
16718 | if (IS_CHERRYVIEW(dev_priv) || | |
16719 | IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) | |
16720 | funcs = &g4x_crtc_funcs; | |
16721 | else if (IS_GEN(dev_priv, 4)) | |
16722 | funcs = &i965_crtc_funcs; | |
7d423af9 VS |
16723 | else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) |
16724 | funcs = &i915gm_crtc_funcs; | |
08fa8fd0 VS |
16725 | else if (IS_GEN(dev_priv, 3)) |
16726 | funcs = &i915_crtc_funcs; | |
16727 | else | |
16728 | funcs = &i8xx_crtc_funcs; | |
16729 | } else { | |
16730 | if (INTEL_GEN(dev_priv) >= 8) | |
16731 | funcs = &bdw_crtc_funcs; | |
16732 | else | |
16733 | funcs = &ilk_crtc_funcs; | |
16734 | } | |
16735 | ||
f44bfa7f | 16736 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, |
b079bd17 | 16737 | &primary->base, &cursor->base, |
08fa8fd0 | 16738 | funcs, "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
16739 | if (ret) |
16740 | goto fail; | |
79e53945 | 16741 | |
1947fd13 VS |
16742 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || |
16743 | dev_priv->pipe_to_crtc_mapping[pipe] != NULL); | |
f44bfa7f | 16744 | dev_priv->pipe_to_crtc_mapping[pipe] = crtc; |
1947fd13 VS |
16745 | |
16746 | if (INTEL_GEN(dev_priv) < 9) { | |
16747 | enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; | |
16748 | ||
16749 | BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || | |
16750 | dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); | |
f44bfa7f | 16751 | dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; |
1947fd13 | 16752 | } |
22fd0fab | 16753 | |
f44bfa7f | 16754 | intel_color_init(crtc); |
8563b1e8 | 16755 | |
00535527 JN |
16756 | intel_crtc_crc_init(crtc); |
16757 | ||
e57291c2 | 16758 | drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); |
b079bd17 VS |
16759 | |
16760 | return 0; | |
3d7d6510 MR |
16761 | |
16762 | fail: | |
66434539 | 16763 | intel_crtc_free(crtc); |
b079bd17 VS |
16764 | |
16765 | return ret; | |
79e53945 JB |
16766 | } |
16767 | ||
6a20fe7b VS |
16768 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
16769 | struct drm_file *file) | |
08d7b3d1 | 16770 | { |
08d7b3d1 | 16771 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 16772 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 16773 | struct intel_crtc *crtc; |
08d7b3d1 | 16774 | |
418da172 | 16775 | drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); |
71240ed2 | 16776 | if (!drmmode_crtc) |
3f2c2057 | 16777 | return -ENOENT; |
08d7b3d1 | 16778 | |
7707e653 | 16779 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 16780 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 16781 | |
c05422d5 | 16782 | return 0; |
08d7b3d1 CW |
16783 | } |
16784 | ||
c08f995a | 16785 | static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) |
79e53945 | 16786 | { |
66a9278e DV |
16787 | struct drm_device *dev = encoder->base.dev; |
16788 | struct intel_encoder *source_encoder; | |
c08f995a | 16789 | u32 possible_clones = 0; |
79e53945 | 16790 | |
b2784e15 | 16791 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 16792 | if (encoders_cloneable(encoder, source_encoder)) |
c08f995a | 16793 | possible_clones |= drm_encoder_mask(&source_encoder->base); |
79e53945 | 16794 | } |
4ef69c7a | 16795 | |
c08f995a | 16796 | return possible_clones; |
79e53945 JB |
16797 | } |
16798 | ||
ed500bf6 VS |
16799 | static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) |
16800 | { | |
16801 | struct drm_device *dev = encoder->base.dev; | |
16802 | struct intel_crtc *crtc; | |
16803 | u32 possible_crtcs = 0; | |
16804 | ||
16805 | for_each_intel_crtc(dev, crtc) { | |
981329ce | 16806 | if (encoder->pipe_mask & BIT(crtc->pipe)) |
ed500bf6 VS |
16807 | possible_crtcs |= drm_crtc_mask(&crtc->base); |
16808 | } | |
16809 | ||
16810 | return possible_crtcs; | |
16811 | } | |
16812 | ||
a5916fd7 | 16813 | static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 16814 | { |
646d5772 | 16815 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
16816 | return false; |
16817 | ||
dc008bf0 | 16818 | if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) |
4d302442 CW |
16819 | return false; |
16820 | ||
dc008bf0 | 16821 | if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
16822 | return false; |
16823 | ||
16824 | return true; | |
16825 | } | |
16826 | ||
63cb4e64 | 16827 | static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 16828 | { |
6315b5d3 | 16829 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
16830 | return false; |
16831 | ||
50a0bc90 | 16832 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
16833 | return false; |
16834 | ||
4f8036a2 | 16835 | if (HAS_PCH_LPT_H(dev_priv) && |
dc008bf0 | 16836 | intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
65e472e4 VS |
16837 | return false; |
16838 | ||
70ac54d0 | 16839 | /* DDI E can't be used if DDI A requires 4 lanes */ |
dc008bf0 | 16840 | if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
16841 | return false; |
16842 | ||
e4abb733 | 16843 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
16844 | return false; |
16845 | ||
16846 | return true; | |
16847 | } | |
16848 | ||
8090ba8c ID |
16849 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
16850 | { | |
16851 | int pps_num; | |
16852 | int pps_idx; | |
16853 | ||
16854 | if (HAS_DDI(dev_priv)) | |
16855 | return; | |
16856 | /* | |
16857 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
16858 | * everywhere where registers can be write protected. | |
16859 | */ | |
16860 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
16861 | pps_num = 2; | |
16862 | else | |
16863 | pps_num = 1; | |
16864 | ||
16865 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
dc008bf0 | 16866 | u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); |
8090ba8c ID |
16867 | |
16868 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
dc008bf0 | 16869 | intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); |
8090ba8c ID |
16870 | } |
16871 | } | |
16872 | ||
44cb734c ID |
16873 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
16874 | { | |
cc3f90f0 | 16875 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
16876 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
16877 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
16878 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
16879 | else | |
16880 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
16881 | |
16882 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
16883 | } |
16884 | ||
c39055b0 | 16885 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 16886 | { |
4ef69c7a | 16887 | struct intel_encoder *encoder; |
cb0953d7 | 16888 | bool dpd_is_edp = false; |
79e53945 | 16889 | |
44cb734c ID |
16890 | intel_pps_init(dev_priv); |
16891 | ||
b81dddb9 | 16892 | if (!HAS_DISPLAY(dev_priv)) |
fc0c5a9d CW |
16893 | return; |
16894 | ||
aefaa1f4 MR |
16895 | if (IS_ROCKETLAKE(dev_priv)) { |
16896 | intel_ddi_init(dev_priv, PORT_A); | |
16897 | intel_ddi_init(dev_priv, PORT_B); | |
16898 | intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ | |
16899 | intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ | |
16900 | } else if (INTEL_GEN(dev_priv) >= 12) { | |
55cd5048 MK |
16901 | intel_ddi_init(dev_priv, PORT_A); |
16902 | intel_ddi_init(dev_priv, PORT_B); | |
f663769a LDM |
16903 | intel_ddi_init(dev_priv, PORT_D); |
16904 | intel_ddi_init(dev_priv, PORT_E); | |
16905 | intel_ddi_init(dev_priv, PORT_F); | |
16906 | intel_ddi_init(dev_priv, PORT_G); | |
16907 | intel_ddi_init(dev_priv, PORT_H); | |
16908 | intel_ddi_init(dev_priv, PORT_I); | |
33365fec | 16909 | icl_dsi_init(dev_priv); |
55cd5048 | 16910 | } else if (IS_ELKHARTLAKE(dev_priv)) { |
759c9ab5 BP |
16911 | intel_ddi_init(dev_priv, PORT_A); |
16912 | intel_ddi_init(dev_priv, PORT_B); | |
16913 | intel_ddi_init(dev_priv, PORT_C); | |
719d2400 | 16914 | intel_ddi_init(dev_priv, PORT_D); |
759c9ab5 | 16915 | icl_dsi_init(dev_priv); |
55cd5048 | 16916 | } else if (IS_GEN(dev_priv, 11)) { |
00c92d92 PZ |
16917 | intel_ddi_init(dev_priv, PORT_A); |
16918 | intel_ddi_init(dev_priv, PORT_B); | |
16919 | intel_ddi_init(dev_priv, PORT_C); | |
16920 | intel_ddi_init(dev_priv, PORT_D); | |
16921 | intel_ddi_init(dev_priv, PORT_E); | |
3f2e9ed0 ID |
16922 | /* |
16923 | * On some ICL SKUs port F is not present. No strap bits for | |
16924 | * this, so rely on VBT. | |
2b34e562 | 16925 | * Work around broken VBTs on SKUs known to have no port F. |
3f2e9ed0 | 16926 | */ |
2b34e562 ID |
16927 | if (IS_ICL_WITH_PORT_F(dev_priv) && |
16928 | intel_bios_is_port_present(dev_priv, PORT_F)) | |
3f2e9ed0 ID |
16929 | intel_ddi_init(dev_priv, PORT_F); |
16930 | ||
bf4d57ff | 16931 | icl_dsi_init(dev_priv); |
00c92d92 | 16932 | } else if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
16933 | /* |
16934 | * FIXME: Broxton doesn't support port detection via the | |
16935 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
16936 | * detect the ports. | |
16937 | */ | |
c39055b0 ACO |
16938 | intel_ddi_init(dev_priv, PORT_A); |
16939 | intel_ddi_init(dev_priv, PORT_B); | |
16940 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 16941 | |
e518634b | 16942 | vlv_dsi_init(dev_priv); |
4f8036a2 | 16943 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
16944 | int found; |
16945 | ||
63cb4e64 JN |
16946 | if (intel_ddi_crt_present(dev_priv)) |
16947 | intel_crt_init(dev_priv); | |
16948 | ||
de31facd JB |
16949 | /* |
16950 | * Haswell uses DDI functions to detect digital outputs. | |
16951 | * On SKL pre-D0 the strap isn't connected, so we assume | |
16952 | * it's there. | |
16953 | */ | |
dc008bf0 | 16954 | found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 16955 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 16956 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 16957 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 | 16958 | |
9787e835 | 16959 | /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP |
0e72a5b5 | 16960 | * register */ |
dc008bf0 | 16961 | found = intel_de_read(dev_priv, SFUSE_STRAP); |
0e72a5b5 ED |
16962 | |
16963 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 16964 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 16965 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 16966 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 16967 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 16968 | intel_ddi_init(dev_priv, PORT_D); |
9787e835 RV |
16969 | if (found & SFUSE_STRAP_DDIF_DETECTED) |
16970 | intel_ddi_init(dev_priv, PORT_F); | |
2800e4c2 RV |
16971 | /* |
16972 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
16973 | */ | |
b976dc53 | 16974 | if (IS_GEN9_BC(dev_priv) && |
e9d49bb7 | 16975 | intel_bios_is_port_present(dev_priv, PORT_E)) |
c39055b0 | 16976 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 16977 | |
6e266956 | 16978 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 16979 | int found; |
63cb4e64 | 16980 | |
0fafa226 JN |
16981 | /* |
16982 | * intel_edp_init_connector() depends on this completing first, | |
16983 | * to prevent the registration of both eDP and LVDS and the | |
16984 | * incorrect sharing of the PPS. | |
16985 | */ | |
16986 | intel_lvds_init(dev_priv); | |
74d021ea | 16987 | intel_crt_init(dev_priv); |
63cb4e64 | 16988 | |
7b91bf7f | 16989 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
270b3042 | 16990 | |
a5916fd7 | 16991 | if (ilk_has_edp_a(dev_priv)) |
c39055b0 | 16992 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 16993 | |
dc008bf0 | 16994 | if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 16995 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 16996 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 16997 | if (!found) |
c39055b0 | 16998 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
dc008bf0 | 16999 | if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 17000 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
17001 | } |
17002 | ||
dc008bf0 | 17003 | if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 17004 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 17005 | |
dc008bf0 | 17006 | if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 17007 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 17008 | |
dc008bf0 | 17009 | if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) |
c39055b0 | 17010 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 17011 | |
dc008bf0 | 17012 | if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) |
c39055b0 | 17013 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 17014 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 17015 | bool has_edp, has_port; |
457c52d8 | 17016 | |
63cb4e64 JN |
17017 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) |
17018 | intel_crt_init(dev_priv); | |
17019 | ||
e17ac6db VS |
17020 | /* |
17021 | * The DP_DETECTED bit is the latched state of the DDC | |
17022 | * SDA pin at boot. However since eDP doesn't require DDC | |
17023 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
17024 | * eDP ports may have been muxed to an alternate function. | |
17025 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
17026 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
17027 | * detect eDP ports. | |
22f35042 VS |
17028 | * |
17029 | * Sadly the straps seem to be missing sometimes even for HDMI | |
17030 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
17031 | * and VBT for the presence of the port. Additionally we can't | |
17032 | * trust the port type the VBT declares as we've seen at least | |
17033 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 17034 | */ |
7b91bf7f | 17035 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
22f35042 | 17036 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
dc008bf0 | 17037 | if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) |
c39055b0 | 17038 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
dc008bf0 | 17039 | if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 17040 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 17041 | |
7b91bf7f | 17042 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
22f35042 | 17043 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
dc008bf0 | 17044 | if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) |
c39055b0 | 17045 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
dc008bf0 | 17046 | if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 17047 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 17048 | |
920a14b2 | 17049 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
17050 | /* |
17051 | * eDP not supported on port D, | |
17052 | * so no need to worry about it | |
17053 | */ | |
17054 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
dc008bf0 | 17055 | if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) |
c39055b0 | 17056 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
dc008bf0 | 17057 | if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 17058 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
17059 | } |
17060 | ||
e518634b | 17061 | vlv_dsi_init(dev_priv); |
63cb4e64 | 17062 | } else if (IS_PINEVIEW(dev_priv)) { |
0fafa226 | 17063 | intel_lvds_init(dev_priv); |
74d021ea | 17064 | intel_crt_init(dev_priv); |
63cb4e64 | 17065 | } else if (IS_GEN_RANGE(dev_priv, 3, 4)) { |
27185ae1 | 17066 | bool found = false; |
7d57382e | 17067 | |
9bedc7ed JN |
17068 | if (IS_MOBILE(dev_priv)) |
17069 | intel_lvds_init(dev_priv); | |
0fafa226 | 17070 | |
74d021ea | 17071 | intel_crt_init(dev_priv); |
63cb4e64 | 17072 | |
dc008bf0 | 17073 | if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { |
cd49f818 | 17074 | drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); |
c39055b0 | 17075 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 17076 | if (!found && IS_G4X(dev_priv)) { |
cd49f818 WK |
17077 | drm_dbg_kms(&dev_priv->drm, |
17078 | "probing HDMI on SDVOB\n"); | |
c39055b0 | 17079 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 17080 | } |
27185ae1 | 17081 | |
9beb5fea | 17082 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 17083 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 17084 | } |
13520b05 KH |
17085 | |
17086 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 17087 | |
dc008bf0 | 17088 | if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { |
cd49f818 | 17089 | drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); |
c39055b0 | 17090 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 17091 | } |
27185ae1 | 17092 | |
dc008bf0 | 17093 | if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 17094 | |
9beb5fea | 17095 | if (IS_G4X(dev_priv)) { |
cd49f818 WK |
17096 | drm_dbg_kms(&dev_priv->drm, |
17097 | "probing HDMI on SDVOC\n"); | |
c39055b0 | 17098 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 17099 | } |
9beb5fea | 17100 | if (IS_G4X(dev_priv)) |
c39055b0 | 17101 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 17102 | } |
27185ae1 | 17103 | |
dc008bf0 | 17104 | if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) |
c39055b0 | 17105 | intel_dp_init(dev_priv, DP_D, PORT_D); |
d6521463 JN |
17106 | |
17107 | if (SUPPORTS_TV(dev_priv)) | |
17108 | intel_tv_init(dev_priv); | |
63cb4e64 | 17109 | } else if (IS_GEN(dev_priv, 2)) { |
346073ce | 17110 | if (IS_I85X(dev_priv)) |
9bedc7ed | 17111 | intel_lvds_init(dev_priv); |
0fafa226 | 17112 | |
74d021ea | 17113 | intel_crt_init(dev_priv); |
c39055b0 | 17114 | intel_dvo_init(dev_priv); |
63cb4e64 | 17115 | } |
79e53945 | 17116 | |
c39055b0 | 17117 | intel_psr_init(dev_priv); |
7c8f8a70 | 17118 | |
c39055b0 | 17119 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
ed500bf6 VS |
17120 | encoder->base.possible_crtcs = |
17121 | intel_encoder_possible_crtcs(encoder); | |
4ef69c7a | 17122 | encoder->base.possible_clones = |
c08f995a | 17123 | intel_encoder_possible_clones(encoder); |
79e53945 | 17124 | } |
47356eb6 | 17125 | |
c39055b0 | 17126 | intel_init_pch_refclk(dev_priv); |
270b3042 | 17127 | |
c39055b0 | 17128 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
17129 | } |
17130 | ||
17131 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
17132 | { | |
17133 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 17134 | |
ef2d633e | 17135 | drm_framebuffer_cleanup(fb); |
8e7cb179 | 17136 | intel_frontbuffer_put(intel_fb->frontbuffer); |
70001cd2 | 17137 | |
79e53945 JB |
17138 | kfree(intel_fb); |
17139 | } | |
17140 | ||
17141 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 17142 | struct drm_file *file, |
79e53945 JB |
17143 | unsigned int *handle) |
17144 | { | |
a5ff7a45 | 17145 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
cd49f818 | 17146 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
79e53945 | 17147 | |
cc917ab4 | 17148 | if (obj->userptr.mm) { |
cd49f818 WK |
17149 | drm_dbg(&i915->drm, |
17150 | "attempting to use a userptr for a framebuffer, denied\n"); | |
cc917ab4 CW |
17151 | return -EINVAL; |
17152 | } | |
17153 | ||
05394f39 | 17154 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
17155 | } |
17156 | ||
86c98588 RV |
17157 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
17158 | struct drm_file *file, | |
17159 | unsigned flags, unsigned color, | |
17160 | struct drm_clip_rect *clips, | |
17161 | unsigned num_clips) | |
17162 | { | |
5a97bcc6 | 17163 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 17164 | |
5a97bcc6 | 17165 | i915_gem_object_flush_if_display(obj); |
8e7cb179 | 17166 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
86c98588 RV |
17167 | |
17168 | return 0; | |
17169 | } | |
17170 | ||
79e53945 JB |
17171 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
17172 | .destroy = intel_user_framebuffer_destroy, | |
17173 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 17174 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
17175 | }; |
17176 | ||
24dbf51a CW |
17177 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
17178 | struct drm_i915_gem_object *obj, | |
17179 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 17180 | { |
24dbf51a | 17181 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 17182 | struct drm_framebuffer *fb = &intel_fb->base; |
a88c40eb | 17183 | u32 max_stride; |
dd689287 | 17184 | unsigned int tiling, stride; |
24dbf51a | 17185 | int ret = -EINVAL; |
2e2adb05 | 17186 | int i; |
79e53945 | 17187 | |
8e7cb179 CW |
17188 | intel_fb->frontbuffer = intel_frontbuffer_get(obj); |
17189 | if (!intel_fb->frontbuffer) | |
17190 | return -ENOMEM; | |
17191 | ||
80f0b679 | 17192 | i915_gem_object_lock(obj, NULL); |
dd689287 CW |
17193 | tiling = i915_gem_object_get_tiling(obj); |
17194 | stride = i915_gem_object_get_stride(obj); | |
17195 | i915_gem_object_unlock(obj); | |
dd4916c5 | 17196 | |
2a80eada | 17197 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
17198 | /* |
17199 | * If there's a fence, enforce that | |
17200 | * the fb modifier and tiling mode match. | |
17201 | */ | |
17202 | if (tiling != I915_TILING_NONE && | |
17203 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
cd49f818 WK |
17204 | drm_dbg_kms(&dev_priv->drm, |
17205 | "tiling_mode doesn't match fb modifier\n"); | |
24dbf51a | 17206 | goto err; |
2a80eada DV |
17207 | } |
17208 | } else { | |
c2ff7370 | 17209 | if (tiling == I915_TILING_X) { |
2a80eada | 17210 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 17211 | } else if (tiling == I915_TILING_Y) { |
cd49f818 WK |
17212 | drm_dbg_kms(&dev_priv->drm, |
17213 | "No Y tiling for legacy addfb\n"); | |
24dbf51a | 17214 | goto err; |
2a80eada DV |
17215 | } |
17216 | } | |
17217 | ||
17e8fd11 VS |
17218 | if (!drm_any_plane_has_format(&dev_priv->drm, |
17219 | mode_cmd->pixel_format, | |
17220 | mode_cmd->modifier[0])) { | |
17221 | struct drm_format_name_buf format_name; | |
17222 | ||
cd49f818 WK |
17223 | drm_dbg_kms(&dev_priv->drm, |
17224 | "unsupported pixel format %s / modifier 0x%llx\n", | |
17225 | drm_get_format_name(mode_cmd->pixel_format, | |
17226 | &format_name), | |
17227 | mode_cmd->modifier[0]); | |
24dbf51a | 17228 | goto err; |
c16ed4be | 17229 | } |
57cd6508 | 17230 | |
c2ff7370 VS |
17231 | /* |
17232 | * gen2/3 display engine uses the fence if present, | |
17233 | * so the tiling mode must match the fb modifier exactly. | |
17234 | */ | |
c56b89f1 | 17235 | if (INTEL_GEN(dev_priv) < 4 && |
c2ff7370 | 17236 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
cd49f818 WK |
17237 | drm_dbg_kms(&dev_priv->drm, |
17238 | "tiling_mode must match fb modifier exactly on gen2/3\n"); | |
9aceb5c1 | 17239 | goto err; |
c2ff7370 VS |
17240 | } |
17241 | ||
a88c40eb VS |
17242 | max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, |
17243 | mode_cmd->modifier[0]); | |
17244 | if (mode_cmd->pitches[0] > max_stride) { | |
cd49f818 WK |
17245 | drm_dbg_kms(&dev_priv->drm, |
17246 | "%s pitch (%u) must be at most %d\n", | |
17247 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? | |
17248 | "tiled" : "linear", | |
17249 | mode_cmd->pitches[0], max_stride); | |
24dbf51a | 17250 | goto err; |
c16ed4be | 17251 | } |
5d7bd705 | 17252 | |
c2ff7370 VS |
17253 | /* |
17254 | * If there's a fence, enforce that | |
17255 | * the fb pitch and fence stride match. | |
17256 | */ | |
144cc143 | 17257 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
cd49f818 WK |
17258 | drm_dbg_kms(&dev_priv->drm, |
17259 | "pitch (%d) must match tiling stride (%d)\n", | |
17260 | mode_cmd->pitches[0], stride); | |
24dbf51a | 17261 | goto err; |
c16ed4be | 17262 | } |
5d7bd705 | 17263 | |
90f9a336 | 17264 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
5cf15dfc | 17265 | if (mode_cmd->offsets[0] != 0) { |
cd49f818 WK |
17266 | drm_dbg_kms(&dev_priv->drm, |
17267 | "plane 0 offset (0x%08x) must be 0\n", | |
17268 | mode_cmd->offsets[0]); | |
24dbf51a | 17269 | goto err; |
5cf15dfc | 17270 | } |
90f9a336 | 17271 | |
2e2adb05 | 17272 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 17273 | |
2e2adb05 VS |
17274 | for (i = 0; i < fb->format->num_planes; i++) { |
17275 | u32 stride_alignment; | |
17276 | ||
17277 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
cd49f818 WK |
17278 | drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", |
17279 | i); | |
37875d6b | 17280 | goto err; |
2e2adb05 VS |
17281 | } |
17282 | ||
17283 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
2e2adb05 | 17284 | if (fb->pitches[i] & (stride_alignment - 1)) { |
cd49f818 WK |
17285 | drm_dbg_kms(&dev_priv->drm, |
17286 | "plane %d pitch (%d) must be at least %u byte aligned\n", | |
17287 | i, fb->pitches[i], stride_alignment); | |
2e2adb05 VS |
17288 | goto err; |
17289 | } | |
d88c4afd | 17290 | |
71df86f0 ID |
17291 | if (is_gen12_ccs_plane(fb, i)) { |
17292 | int ccs_aux_stride = gen12_ccs_aux_stride(fb, i); | |
17293 | ||
17294 | if (fb->pitches[i] != ccs_aux_stride) { | |
cd49f818 WK |
17295 | drm_dbg_kms(&dev_priv->drm, |
17296 | "ccs aux plane %d pitch (%d) must be %d\n", | |
17297 | i, | |
17298 | fb->pitches[i], ccs_aux_stride); | |
71df86f0 ID |
17299 | goto err; |
17300 | } | |
17301 | } | |
17302 | ||
a268bcd7 DS |
17303 | fb->obj[i] = &obj->base; |
17304 | } | |
c7d73f6a | 17305 | |
2e2adb05 | 17306 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 17307 | if (ret) |
9aceb5c1 | 17308 | goto err; |
2d7a215f | 17309 | |
2e2adb05 | 17310 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 | 17311 | if (ret) { |
cd49f818 | 17312 | drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); |
24dbf51a | 17313 | goto err; |
79e53945 JB |
17314 | } |
17315 | ||
79e53945 | 17316 | return 0; |
24dbf51a CW |
17317 | |
17318 | err: | |
8e7cb179 | 17319 | intel_frontbuffer_put(intel_fb->frontbuffer); |
24dbf51a | 17320 | return ret; |
79e53945 JB |
17321 | } |
17322 | ||
79e53945 JB |
17323 | static struct drm_framebuffer * |
17324 | intel_user_framebuffer_create(struct drm_device *dev, | |
17325 | struct drm_file *filp, | |
1eb83451 | 17326 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 17327 | { |
dcb1394e | 17328 | struct drm_framebuffer *fb; |
05394f39 | 17329 | struct drm_i915_gem_object *obj; |
76dc3769 | 17330 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 17331 | |
03ac0642 CW |
17332 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
17333 | if (!obj) | |
cce13ff7 | 17334 | return ERR_PTR(-ENOENT); |
79e53945 | 17335 | |
24dbf51a | 17336 | fb = intel_framebuffer_create(obj, &mode_cmd); |
8e7cb179 | 17337 | i915_gem_object_put(obj); |
dcb1394e LW |
17338 | |
17339 | return fb; | |
79e53945 JB |
17340 | } |
17341 | ||
e995ca0b VS |
17342 | static enum drm_mode_status |
17343 | intel_mode_valid(struct drm_device *dev, | |
17344 | const struct drm_display_mode *mode) | |
17345 | { | |
ad77c537 VS |
17346 | struct drm_i915_private *dev_priv = to_i915(dev); |
17347 | int hdisplay_max, htotal_max; | |
17348 | int vdisplay_max, vtotal_max; | |
17349 | ||
e4dd27aa VS |
17350 | /* |
17351 | * Can't reject DBLSCAN here because Xorg ddxen can add piles | |
17352 | * of DBLSCAN modes to the output's mode list when they detect | |
17353 | * the scaling mode property on the connector. And they don't | |
17354 | * ask the kernel to validate those modes in any way until | |
17355 | * modeset time at which point the client gets a protocol error. | |
17356 | * So in order to not upset those clients we silently ignore the | |
17357 | * DBLSCAN flag on such connectors. For other connectors we will | |
17358 | * reject modes with the DBLSCAN flag in encoder->compute_config(). | |
17359 | * And we always reject DBLSCAN modes in connector->mode_valid() | |
17360 | * as we never want such modes on the connector's mode list. | |
17361 | */ | |
17362 | ||
e995ca0b VS |
17363 | if (mode->vscan > 1) |
17364 | return MODE_NO_VSCAN; | |
17365 | ||
e995ca0b VS |
17366 | if (mode->flags & DRM_MODE_FLAG_HSKEW) |
17367 | return MODE_H_ILLEGAL; | |
17368 | ||
17369 | if (mode->flags & (DRM_MODE_FLAG_CSYNC | | |
17370 | DRM_MODE_FLAG_NCSYNC | | |
17371 | DRM_MODE_FLAG_PCSYNC)) | |
17372 | return MODE_HSYNC; | |
17373 | ||
17374 | if (mode->flags & (DRM_MODE_FLAG_BCAST | | |
17375 | DRM_MODE_FLAG_PIXMUX | | |
17376 | DRM_MODE_FLAG_CLKDIV2)) | |
17377 | return MODE_BAD; | |
17378 | ||
2d20411e | 17379 | /* Transcoder timing limits */ |
12a97df0 MN |
17380 | if (INTEL_GEN(dev_priv) >= 11) { |
17381 | hdisplay_max = 16384; | |
17382 | vdisplay_max = 8192; | |
17383 | htotal_max = 16384; | |
17384 | vtotal_max = 8192; | |
17385 | } else if (INTEL_GEN(dev_priv) >= 9 || | |
17386 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
ad77c537 VS |
17387 | hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ |
17388 | vdisplay_max = 4096; | |
17389 | htotal_max = 8192; | |
17390 | vtotal_max = 8192; | |
17391 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
17392 | hdisplay_max = 4096; | |
17393 | vdisplay_max = 4096; | |
17394 | htotal_max = 8192; | |
17395 | vtotal_max = 8192; | |
17396 | } else { | |
17397 | hdisplay_max = 2048; | |
17398 | vdisplay_max = 2048; | |
17399 | htotal_max = 4096; | |
17400 | vtotal_max = 4096; | |
17401 | } | |
17402 | ||
17403 | if (mode->hdisplay > hdisplay_max || | |
17404 | mode->hsync_start > htotal_max || | |
17405 | mode->hsync_end > htotal_max || | |
17406 | mode->htotal > htotal_max) | |
17407 | return MODE_H_ILLEGAL; | |
17408 | ||
17409 | if (mode->vdisplay > vdisplay_max || | |
17410 | mode->vsync_start > vtotal_max || | |
17411 | mode->vsync_end > vtotal_max || | |
17412 | mode->vtotal > vtotal_max) | |
17413 | return MODE_V_ILLEGAL; | |
17414 | ||
8f4b1068 VS |
17415 | if (INTEL_GEN(dev_priv) >= 5) { |
17416 | if (mode->hdisplay < 64 || | |
17417 | mode->htotal - mode->hdisplay < 32) | |
17418 | return MODE_H_ILLEGAL; | |
17419 | ||
17420 | if (mode->vtotal - mode->vdisplay < 5) | |
17421 | return MODE_V_ILLEGAL; | |
17422 | } else { | |
17423 | if (mode->htotal - mode->hdisplay < 32) | |
17424 | return MODE_H_ILLEGAL; | |
17425 | ||
17426 | if (mode->vtotal - mode->vdisplay < 3) | |
17427 | return MODE_V_ILLEGAL; | |
17428 | } | |
17429 | ||
e995ca0b VS |
17430 | return MODE_OK; |
17431 | } | |
17432 | ||
2d20411e VS |
17433 | enum drm_mode_status |
17434 | intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, | |
17435 | const struct drm_display_mode *mode) | |
17436 | { | |
17437 | int plane_width_max, plane_height_max; | |
17438 | ||
17439 | /* | |
17440 | * intel_mode_valid() should be | |
17441 | * sufficient on older platforms. | |
17442 | */ | |
17443 | if (INTEL_GEN(dev_priv) < 9) | |
17444 | return MODE_OK; | |
17445 | ||
17446 | /* | |
17447 | * Most people will probably want a fullscreen | |
17448 | * plane so let's not advertize modes that are | |
17449 | * too big for that. | |
17450 | */ | |
17451 | if (INTEL_GEN(dev_priv) >= 11) { | |
17452 | plane_width_max = 5120; | |
17453 | plane_height_max = 4320; | |
17454 | } else { | |
17455 | plane_width_max = 5120; | |
17456 | plane_height_max = 4096; | |
17457 | } | |
17458 | ||
17459 | if (mode->hdisplay > plane_width_max) | |
17460 | return MODE_H_ILLEGAL; | |
17461 | ||
17462 | if (mode->vdisplay > plane_height_max) | |
17463 | return MODE_V_ILLEGAL; | |
17464 | ||
17465 | return MODE_OK; | |
17466 | } | |
17467 | ||
79e53945 | 17468 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 17469 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 17470 | .get_format_info = intel_get_format_info, |
0632fef6 | 17471 | .output_poll_changed = intel_fbdev_output_poll_changed, |
e995ca0b | 17472 | .mode_valid = intel_mode_valid, |
5ee67f1c MR |
17473 | .atomic_check = intel_atomic_check, |
17474 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
17475 | .atomic_state_alloc = intel_atomic_state_alloc, |
17476 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 17477 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
17478 | }; |
17479 | ||
88212941 ID |
17480 | /** |
17481 | * intel_init_display_hooks - initialize the display modesetting hooks | |
17482 | * @dev_priv: device private | |
17483 | */ | |
17484 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 17485 | { |
7ff89ca2 VS |
17486 | intel_init_cdclk_hooks(dev_priv); |
17487 | ||
c56b89f1 | 17488 | if (INTEL_GEN(dev_priv) >= 9) { |
1e98f88c | 17489 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
5724dbd1 | 17490 | dev_priv->display.get_initial_plane_config = |
f6df4d46 | 17491 | skl_get_initial_plane_config; |
1e98f88c LDM |
17492 | dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; |
17493 | dev_priv->display.crtc_enable = hsw_crtc_enable; | |
17494 | dev_priv->display.crtc_disable = hsw_crtc_disable; | |
88212941 | 17495 | } else if (HAS_DDI(dev_priv)) { |
1e98f88c | 17496 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
5724dbd1 | 17497 | dev_priv->display.get_initial_plane_config = |
81894b2f | 17498 | i9xx_get_initial_plane_config; |
797d0259 | 17499 | dev_priv->display.crtc_compute_clock = |
1e98f88c LDM |
17500 | hsw_crtc_compute_clock; |
17501 | dev_priv->display.crtc_enable = hsw_crtc_enable; | |
17502 | dev_priv->display.crtc_disable = hsw_crtc_disable; | |
88212941 | 17503 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9eae5e27 | 17504 | dev_priv->display.get_pipe_config = ilk_get_pipe_config; |
5724dbd1 | 17505 | dev_priv->display.get_initial_plane_config = |
81894b2f | 17506 | i9xx_get_initial_plane_config; |
3fb37703 | 17507 | dev_priv->display.crtc_compute_clock = |
9eae5e27 LDM |
17508 | ilk_crtc_compute_clock; |
17509 | dev_priv->display.crtc_enable = ilk_crtc_enable; | |
17510 | dev_priv->display.crtc_disable = ilk_crtc_disable; | |
65b3d6a9 | 17511 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 17512 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
17513 | dev_priv->display.get_initial_plane_config = |
17514 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
17515 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
17516 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
17517 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
17518 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
17519 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17520 | dev_priv->display.get_initial_plane_config = | |
17521 | i9xx_get_initial_plane_config; | |
17522 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
17523 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
17524 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
17525 | } else if (IS_G4X(dev_priv)) { |
17526 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17527 | dev_priv->display.get_initial_plane_config = | |
17528 | i9xx_get_initial_plane_config; | |
17529 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
17530 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17531 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
17532 | } else if (IS_PINEVIEW(dev_priv)) { |
17533 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17534 | dev_priv->display.get_initial_plane_config = | |
17535 | i9xx_get_initial_plane_config; | |
17536 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
17537 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17538 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
cf819eff | 17539 | } else if (!IS_GEN(dev_priv, 2)) { |
0e8ffe1b | 17540 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
17541 | dev_priv->display.get_initial_plane_config = |
17542 | i9xx_get_initial_plane_config; | |
d6dfee7a | 17543 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
17544 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
17545 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
17546 | } else { |
17547 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
17548 | dev_priv->display.get_initial_plane_config = | |
17549 | i9xx_get_initial_plane_config; | |
17550 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
17551 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
17552 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 17553 | } |
e70236a8 | 17554 | |
cf819eff | 17555 | if (IS_GEN(dev_priv, 5)) { |
9eae5e27 | 17556 | dev_priv->display.fdi_link_train = ilk_fdi_link_train; |
cf819eff | 17557 | } else if (IS_GEN(dev_priv, 6)) { |
3bb11b53 | 17558 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 17559 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
17560 | /* FIXME: detect B0+ stepping and use auto training */ |
17561 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
445e780b VS |
17562 | } |
17563 | ||
bd30ca2d | 17564 | if (INTEL_GEN(dev_priv) >= 9) |
0c841271 | 17565 | dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; |
27082493 | 17566 | else |
0c841271 | 17567 | dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; |
66d9cec8 | 17568 | |
e70236a8 JB |
17569 | } |
17570 | ||
6cd02e77 | 17571 | void intel_modeset_init_hw(struct drm_i915_private *i915) |
f817586c | 17572 | { |
1965de63 | 17573 | struct intel_cdclk_state *cdclk_state = |
28a30b45 | 17574 | to_intel_cdclk_state(i915->cdclk.obj.state); |
3cf43cdc VS |
17575 | struct intel_dbuf_state *dbuf_state = |
17576 | to_intel_dbuf_state(i915->dbuf.obj.state); | |
1965de63 | 17577 | |
6cd02e77 | 17578 | intel_update_cdclk(i915); |
0bb94e03 | 17579 | intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); |
1965de63 | 17580 | cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; |
3cf43cdc VS |
17581 | |
17582 | dbuf_state->enabled_slices = i915->dbuf.enabled_slices; | |
f817586c DV |
17583 | } |
17584 | ||
d1b2828a VS |
17585 | static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) |
17586 | { | |
17587 | struct drm_plane *plane; | |
af157b76 | 17588 | struct intel_crtc *crtc; |
d1b2828a | 17589 | |
af157b76 VS |
17590 | for_each_intel_crtc(state->dev, crtc) { |
17591 | struct intel_crtc_state *crtc_state; | |
d1b2828a | 17592 | |
af157b76 | 17593 | crtc_state = intel_atomic_get_crtc_state(state, crtc); |
d1b2828a VS |
17594 | if (IS_ERR(crtc_state)) |
17595 | return PTR_ERR(crtc_state); | |
af157b76 VS |
17596 | |
17597 | if (crtc_state->hw.active) { | |
17598 | /* | |
17599 | * Preserve the inherited flag to avoid | |
17600 | * taking the full modeset path. | |
17601 | */ | |
a227569d | 17602 | crtc_state->inherited = true; |
af157b76 | 17603 | } |
d1b2828a VS |
17604 | } |
17605 | ||
17606 | drm_for_each_plane(plane, state->dev) { | |
17607 | struct drm_plane_state *plane_state; | |
17608 | ||
17609 | plane_state = drm_atomic_get_plane_state(state, plane); | |
17610 | if (IS_ERR(plane_state)) | |
17611 | return PTR_ERR(plane_state); | |
17612 | } | |
17613 | ||
17614 | return 0; | |
17615 | } | |
17616 | ||
d93c0372 MR |
17617 | /* |
17618 | * Calculate what we think the watermarks should be for the state we've read | |
17619 | * out of the hardware and then immediately program those watermarks so that | |
17620 | * we ensure the hardware settings match our internal state. | |
17621 | * | |
17622 | * We can calculate what we think WM's should be by creating a duplicate of the | |
17623 | * current state (which was constructed during hardware readout) and running it | |
17624 | * through the atomic check code to calculate new watermark values in the | |
17625 | * state object. | |
17626 | */ | |
d1b2828a | 17627 | static void sanitize_watermarks(struct drm_i915_private *dev_priv) |
d93c0372 | 17628 | { |
d93c0372 | 17629 | struct drm_atomic_state *state; |
ccf010fb | 17630 | struct intel_atomic_state *intel_state; |
49743e1d ML |
17631 | struct intel_crtc *crtc; |
17632 | struct intel_crtc_state *crtc_state; | |
d93c0372 MR |
17633 | struct drm_modeset_acquire_ctx ctx; |
17634 | int ret; | |
17635 | int i; | |
17636 | ||
17637 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 17638 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
17639 | return; |
17640 | ||
d1b2828a | 17641 | state = drm_atomic_state_alloc(&dev_priv->drm); |
e57291c2 | 17642 | if (drm_WARN_ON(&dev_priv->drm, !state)) |
d1b2828a | 17643 | return; |
d93c0372 | 17644 | |
ccf010fb ML |
17645 | intel_state = to_intel_atomic_state(state); |
17646 | ||
d1b2828a VS |
17647 | drm_modeset_acquire_init(&ctx, 0); |
17648 | ||
17649 | retry: | |
17650 | state->acquire_ctx = &ctx; | |
17651 | ||
ed4a6a7c MR |
17652 | /* |
17653 | * Hardware readout is the only time we don't want to calculate | |
17654 | * intermediate watermarks (since we don't trust the current | |
17655 | * watermarks). | |
17656 | */ | |
b2ae318a | 17657 | if (!HAS_GMCH(dev_priv)) |
602ae835 | 17658 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 17659 | |
d1b2828a VS |
17660 | ret = sanitize_watermarks_add_affected(state); |
17661 | if (ret) | |
17662 | goto fail; | |
17663 | ||
17664 | ret = intel_atomic_check(&dev_priv->drm, state); | |
17665 | if (ret) | |
17666 | goto fail; | |
d93c0372 MR |
17667 | |
17668 | /* Write calculated watermark values back */ | |
49743e1d ML |
17669 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { |
17670 | crtc_state->wm.need_postvbl_update = true; | |
7a8fdb1f | 17671 | dev_priv->display.optimize_watermarks(intel_state, crtc); |
556fe36d | 17672 | |
49743e1d | 17673 | to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; |
d93c0372 MR |
17674 | } |
17675 | ||
0cd1262d | 17676 | fail: |
d1b2828a VS |
17677 | if (ret == -EDEADLK) { |
17678 | drm_atomic_state_clear(state); | |
17679 | drm_modeset_backoff(&ctx); | |
17680 | goto retry; | |
17681 | } | |
17682 | ||
17683 | /* | |
17684 | * If we fail here, it means that the hardware appears to be | |
17685 | * programmed in a way that shouldn't be possible, given our | |
17686 | * understanding of watermark requirements. This might mean a | |
17687 | * mistake in the hardware readout code or a mistake in the | |
17688 | * watermark calculations for a given platform. Raise a WARN | |
17689 | * so that this is noticeable. | |
17690 | * | |
17691 | * If this actually happens, we'll have to just leave the | |
17692 | * BIOS-programmed watermarks untouched and hope for the best. | |
17693 | */ | |
e57291c2 PB |
17694 | drm_WARN(&dev_priv->drm, ret, |
17695 | "Could not determine valid watermarks for inherited state\n"); | |
d1b2828a VS |
17696 | |
17697 | drm_atomic_state_put(state); | |
17698 | ||
d93c0372 MR |
17699 | drm_modeset_drop_locks(&ctx); |
17700 | drm_modeset_acquire_fini(&ctx); | |
17701 | } | |
17702 | ||
58ecd9d5 CW |
17703 | static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) |
17704 | { | |
cf819eff | 17705 | if (IS_GEN(dev_priv, 5)) { |
58ecd9d5 | 17706 | u32 fdi_pll_clk = |
dc008bf0 | 17707 | intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; |
58ecd9d5 CW |
17708 | |
17709 | dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; | |
cf819eff | 17710 | } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { |
58ecd9d5 CW |
17711 | dev_priv->fdi_pll_freq = 270000; |
17712 | } else { | |
17713 | return; | |
17714 | } | |
17715 | ||
cd49f818 | 17716 | drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); |
58ecd9d5 CW |
17717 | } |
17718 | ||
516a49cc AS |
17719 | static int intel_initial_commit(struct drm_device *dev) |
17720 | { | |
17721 | struct drm_atomic_state *state = NULL; | |
17722 | struct drm_modeset_acquire_ctx ctx; | |
3558cafc | 17723 | struct intel_crtc *crtc; |
516a49cc AS |
17724 | int ret = 0; |
17725 | ||
17726 | state = drm_atomic_state_alloc(dev); | |
17727 | if (!state) | |
17728 | return -ENOMEM; | |
17729 | ||
17730 | drm_modeset_acquire_init(&ctx, 0); | |
17731 | ||
17732 | retry: | |
17733 | state->acquire_ctx = &ctx; | |
17734 | ||
3558cafc ML |
17735 | for_each_intel_crtc(dev, crtc) { |
17736 | struct intel_crtc_state *crtc_state = | |
17737 | intel_atomic_get_crtc_state(state, crtc); | |
17738 | ||
516a49cc AS |
17739 | if (IS_ERR(crtc_state)) { |
17740 | ret = PTR_ERR(crtc_state); | |
17741 | goto out; | |
17742 | } | |
17743 | ||
1326a92c | 17744 | if (crtc_state->hw.active) { |
af157b76 VS |
17745 | /* |
17746 | * We've not yet detected sink capabilities | |
17747 | * (audio,infoframes,etc.) and thus we don't want to | |
17748 | * force a full state recomputation yet. We want that to | |
17749 | * happen only for the first real commit from userspace. | |
17750 | * So preserve the inherited flag for the time being. | |
17751 | */ | |
a227569d | 17752 | crtc_state->inherited = true; |
af157b76 | 17753 | |
3558cafc | 17754 | ret = drm_atomic_add_affected_planes(state, &crtc->base); |
516a49cc AS |
17755 | if (ret) |
17756 | goto out; | |
fa6af514 VS |
17757 | |
17758 | /* | |
17759 | * FIXME hack to force a LUT update to avoid the | |
17760 | * plane update forcing the pipe gamma on without | |
17761 | * having a proper LUT loaded. Remove once we | |
17762 | * have readout for pipe gamma enable. | |
17763 | */ | |
2225f3c6 | 17764 | crtc_state->uapi.color_mgmt_changed = true; |
a4277aa3 JN |
17765 | |
17766 | /* | |
17767 | * FIXME hack to force full modeset when DSC is being | |
17768 | * used. | |
17769 | * | |
17770 | * As long as we do not have full state readout and | |
17771 | * config comparison of crtc_state->dsc, we have no way | |
17772 | * to ensure reliable fastset. Remove once we have | |
17773 | * readout for DSC. | |
17774 | */ | |
17775 | if (crtc_state->dsc.compression_enable) { | |
17776 | ret = drm_atomic_add_affected_connectors(state, | |
17777 | &crtc->base); | |
17778 | if (ret) | |
17779 | goto out; | |
17780 | crtc_state->uapi.mode_changed = true; | |
17781 | drm_dbg_kms(dev, "Force full modeset for DSC\n"); | |
17782 | } | |
516a49cc AS |
17783 | } |
17784 | } | |
17785 | ||
17786 | ret = drm_atomic_commit(state); | |
17787 | ||
17788 | out: | |
17789 | if (ret == -EDEADLK) { | |
17790 | drm_atomic_state_clear(state); | |
17791 | drm_modeset_backoff(&ctx); | |
17792 | goto retry; | |
17793 | } | |
17794 | ||
17795 | drm_atomic_state_put(state); | |
17796 | ||
17797 | drm_modeset_drop_locks(&ctx); | |
17798 | drm_modeset_acquire_fini(&ctx); | |
17799 | ||
17800 | return ret; | |
17801 | } | |
17802 | ||
e1a3d989 JN |
17803 | static void intel_mode_config_init(struct drm_i915_private *i915) |
17804 | { | |
17805 | struct drm_mode_config *mode_config = &i915->drm.mode_config; | |
17806 | ||
17807 | drm_mode_config_init(&i915->drm); | |
0ef1905e | 17808 | INIT_LIST_HEAD(&i915->global_obj_list); |
e1a3d989 JN |
17809 | |
17810 | mode_config->min_width = 0; | |
17811 | mode_config->min_height = 0; | |
17812 | ||
17813 | mode_config->preferred_depth = 24; | |
17814 | mode_config->prefer_shadow = 1; | |
17815 | ||
17816 | mode_config->allow_fb_modifiers = true; | |
17817 | ||
17818 | mode_config->funcs = &intel_mode_funcs; | |
17819 | ||
17820 | /* | |
17821 | * Maximum framebuffer dimensions, chosen to match | |
17822 | * the maximum render engine surface size on gen4+. | |
17823 | */ | |
17824 | if (INTEL_GEN(i915) >= 7) { | |
17825 | mode_config->max_width = 16384; | |
17826 | mode_config->max_height = 16384; | |
17827 | } else if (INTEL_GEN(i915) >= 4) { | |
17828 | mode_config->max_width = 8192; | |
17829 | mode_config->max_height = 8192; | |
17830 | } else if (IS_GEN(i915, 3)) { | |
17831 | mode_config->max_width = 4096; | |
17832 | mode_config->max_height = 4096; | |
17833 | } else { | |
17834 | mode_config->max_width = 2048; | |
17835 | mode_config->max_height = 2048; | |
17836 | } | |
17837 | ||
17838 | if (IS_I845G(i915) || IS_I865G(i915)) { | |
17839 | mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; | |
17840 | mode_config->cursor_height = 1023; | |
5e9e0a3a VS |
17841 | } else if (IS_I830(i915) || IS_I85X(i915) || |
17842 | IS_I915G(i915) || IS_I915GM(i915)) { | |
e1a3d989 JN |
17843 | mode_config->cursor_width = 64; |
17844 | mode_config->cursor_height = 64; | |
17845 | } else { | |
17846 | mode_config->cursor_width = 256; | |
17847 | mode_config->cursor_height = 256; | |
17848 | } | |
17849 | } | |
17850 | ||
0ef1905e VS |
17851 | static void intel_mode_config_cleanup(struct drm_i915_private *i915) |
17852 | { | |
17853 | intel_atomic_global_obj_cleanup(i915); | |
17854 | drm_mode_config_cleanup(&i915->drm); | |
17855 | } | |
17856 | ||
1586f620 CW |
17857 | static void plane_config_fini(struct intel_initial_plane_config *plane_config) |
17858 | { | |
17859 | if (plane_config->fb) { | |
17860 | struct drm_framebuffer *fb = &plane_config->fb->base; | |
17861 | ||
17862 | /* We may only have the stub and not a full framebuffer */ | |
17863 | if (drm_framebuffer_read_refcount(fb)) | |
17864 | drm_framebuffer_put(fb); | |
17865 | else | |
17866 | kfree(fb); | |
17867 | } | |
9c4ce97d CW |
17868 | |
17869 | if (plane_config->vma) | |
17870 | i915_vma_put(plane_config->vma); | |
1586f620 CW |
17871 | } |
17872 | ||
80f286a5 JN |
17873 | /* part #1: call before irq install */ |
17874 | int intel_modeset_init_noirq(struct drm_i915_private *i915) | |
79e53945 | 17875 | { |
516a49cc | 17876 | int ret; |
79e53945 | 17877 | |
24d98a54 JN |
17878 | if (i915_inject_probe_failure(i915)) |
17879 | return -ENODEV; | |
17880 | ||
da27bd41 | 17881 | if (HAS_DISPLAY(i915)) { |
24d98a54 JN |
17882 | ret = drm_vblank_init(&i915->drm, |
17883 | INTEL_NUM_PIPES(i915)); | |
17884 | if (ret) | |
17885 | return ret; | |
17886 | } | |
17887 | ||
17888 | intel_bios_init(i915); | |
17889 | ||
17890 | ret = intel_vga_register(i915); | |
17891 | if (ret) | |
17892 | goto cleanup_bios; | |
17893 | ||
17894 | /* FIXME: completely on the wrong abstraction layer */ | |
17895 | intel_power_domains_init_hw(i915, false); | |
17896 | ||
17897 | intel_csr_ucode_init(i915); | |
17898 | ||
6cd02e77 JN |
17899 | i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); |
17900 | i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | | |
17901 | WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); | |
757fffcf | 17902 | |
6cd02e77 | 17903 | intel_mode_config_init(i915); |
79e53945 | 17904 | |
28a30b45 VS |
17905 | ret = intel_cdclk_init(i915); |
17906 | if (ret) | |
24d98a54 | 17907 | goto cleanup_vga_client_pw_domain_csr; |
28a30b45 | 17908 | |
3cf43cdc VS |
17909 | ret = intel_dbuf_init(i915); |
17910 | if (ret) | |
24d98a54 | 17911 | goto cleanup_vga_client_pw_domain_csr; |
3cf43cdc | 17912 | |
6cd02e77 | 17913 | ret = intel_bw_init(i915); |
c457d9cf | 17914 | if (ret) |
24d98a54 | 17915 | goto cleanup_vga_client_pw_domain_csr; |
c457d9cf | 17916 | |
6cd02e77 JN |
17917 | init_llist_head(&i915->atomic_helper.free_list); |
17918 | INIT_WORK(&i915->atomic_helper.free_work, | |
ba318c61 | 17919 | intel_atomic_helper_free_state_worker); |
eb955eee | 17920 | |
6cd02e77 | 17921 | intel_init_quirks(i915); |
b690e96c | 17922 | |
6cd02e77 | 17923 | intel_fbc_init(i915); |
acde44b5 | 17924 | |
80f286a5 | 17925 | return 0; |
24d98a54 JN |
17926 | |
17927 | cleanup_vga_client_pw_domain_csr: | |
17928 | intel_csr_ucode_fini(i915); | |
17929 | intel_power_domains_driver_remove(i915); | |
17930 | intel_vga_unregister(i915); | |
17931 | cleanup_bios: | |
17932 | intel_bios_driver_remove(i915); | |
17933 | ||
17934 | return ret; | |
80f286a5 JN |
17935 | } |
17936 | ||
a5f2488f JN |
17937 | /* part #2: call after irq install, but before gem init */ |
17938 | int intel_modeset_init_nogem(struct drm_i915_private *i915) | |
80f286a5 JN |
17939 | { |
17940 | struct drm_device *dev = &i915->drm; | |
17941 | enum pipe pipe; | |
17942 | struct intel_crtc *crtc; | |
17943 | int ret; | |
17944 | ||
6cd02e77 | 17945 | intel_init_pm(i915); |
1fa61106 | 17946 | |
6cd02e77 | 17947 | intel_panel_sanitize_ssc(i915); |
69f92f67 | 17948 | |
9bfcf194 JN |
17949 | intel_gmbus_setup(i915); |
17950 | ||
cd49f818 WK |
17951 | drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", |
17952 | INTEL_NUM_PIPES(i915), | |
17953 | INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); | |
79e53945 | 17954 | |
da27bd41 | 17955 | if (HAS_DISPLAY(i915)) { |
6cd02e77 JN |
17956 | for_each_pipe(i915, pipe) { |
17957 | ret = intel_crtc_init(i915, pipe); | |
ef404bc6 | 17958 | if (ret) { |
0ef1905e | 17959 | intel_mode_config_cleanup(i915); |
ef404bc6 JN |
17960 | return ret; |
17961 | } | |
b079bd17 | 17962 | } |
79e53945 JB |
17963 | } |
17964 | ||
6875eb3f | 17965 | intel_plane_possible_crtcs_init(i915); |
e72f9fbf | 17966 | intel_shared_dpll_init(dev); |
6cd02e77 | 17967 | intel_update_fdi_pll_freq(i915); |
ee7b9f93 | 17968 | |
6cd02e77 JN |
17969 | intel_update_czclk(i915); |
17970 | intel_modeset_init_hw(i915); | |
5be6e334 | 17971 | |
6cd02e77 | 17972 | intel_hdcp_component_init(i915); |
9055aac7 | 17973 | |
6cd02e77 JN |
17974 | if (i915->max_cdclk_freq == 0) |
17975 | intel_update_max_cdclk(i915); | |
b2045352 | 17976 | |
ddff9a60 MR |
17977 | /* |
17978 | * If the platform has HTI, we need to find out whether it has reserved | |
17979 | * any display resources before we create our display outputs. | |
17980 | */ | |
17981 | if (INTEL_INFO(i915)->display.has_hti) | |
17982 | i915->hti_state = intel_de_read(i915, HDPORT_STATE); | |
17983 | ||
9cce37f4 | 17984 | /* Just disable it once at startup */ |
4fb87831 | 17985 | intel_vga_disable(i915); |
6cd02e77 | 17986 | intel_setup_outputs(i915); |
11be49eb | 17987 | |
6e9f798d | 17988 | drm_modeset_lock_all(dev); |
aecd36b8 | 17989 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 17990 | drm_modeset_unlock_all(dev); |
46f297fb | 17991 | |
d3fcc808 | 17992 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
17993 | struct intel_initial_plane_config plane_config = {}; |
17994 | ||
46f297fb JB |
17995 | if (!crtc->active) |
17996 | continue; | |
17997 | ||
46f297fb | 17998 | /* |
46f297fb JB |
17999 | * Note that reserving the BIOS fb up front prevents us |
18000 | * from stuffing other stolen allocations like the ring | |
18001 | * on top. This prevents some ugliness at boot time, and | |
18002 | * can even allow for smooth boot transitions if the BIOS | |
18003 | * fb is large enough for the active pipe configuration. | |
18004 | */ | |
6cd02e77 | 18005 | i915->display.get_initial_plane_config(crtc, &plane_config); |
eeebeac5 ML |
18006 | |
18007 | /* | |
18008 | * If the fb is shared between multiple heads, we'll | |
18009 | * just get the first one. | |
18010 | */ | |
18011 | intel_find_initial_plane_obj(crtc, &plane_config); | |
1586f620 CW |
18012 | |
18013 | plane_config_fini(&plane_config); | |
46f297fb | 18014 | } |
d93c0372 MR |
18015 | |
18016 | /* | |
18017 | * Make sure hardware watermarks really match the state we read out. | |
18018 | * Note that we need to do this after reconstructing the BIOS fb's | |
18019 | * since the watermark calculation done here will use pstate->fb. | |
18020 | */ | |
6cd02e77 | 18021 | if (!HAS_GMCH(i915)) |
d1b2828a | 18022 | sanitize_watermarks(i915); |
b079bd17 | 18023 | |
516a49cc AS |
18024 | /* |
18025 | * Force all active planes to recompute their states. So that on | |
18026 | * mode_setcrtc after probe, all the intel_plane_state variables | |
18027 | * are already calculated and there is no assert_plane warnings | |
18028 | * during bootup. | |
18029 | */ | |
18030 | ret = intel_initial_commit(dev); | |
18031 | if (ret) | |
cd49f818 | 18032 | drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n"); |
516a49cc | 18033 | |
b079bd17 | 18034 | return 0; |
2c7111db CW |
18035 | } |
18036 | ||
a5f2488f JN |
18037 | /* part #3: call after gem init */ |
18038 | int intel_modeset_init(struct drm_i915_private *i915) | |
18039 | { | |
18040 | int ret; | |
18041 | ||
18042 | intel_overlay_setup(i915); | |
18043 | ||
da27bd41 | 18044 | if (!HAS_DISPLAY(i915)) |
a5f2488f JN |
18045 | return 0; |
18046 | ||
18047 | ret = intel_fbdev_init(&i915->drm); | |
18048 | if (ret) | |
18049 | return ret; | |
18050 | ||
18051 | /* Only enable hotplug handling once the fbdev is fully set up. */ | |
18052 | intel_hpd_init(i915); | |
18053 | ||
18054 | intel_init_ipc(i915); | |
18055 | ||
18056 | intel_psr_set_force_mode_changed(i915->psr.dp); | |
18057 | ||
18058 | return 0; | |
18059 | } | |
18060 | ||
2ee0da16 VS |
18061 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
18062 | { | |
d5fb43cb | 18063 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
2ee0da16 VS |
18064 | /* 640x480@60Hz, ~25175 kHz */ |
18065 | struct dpll clock = { | |
18066 | .m1 = 18, | |
18067 | .m2 = 7, | |
18068 | .p1 = 13, | |
18069 | .p2 = 4, | |
18070 | .n = 2, | |
18071 | }; | |
18072 | u32 dpll, fp; | |
18073 | int i; | |
18074 | ||
e57291c2 PB |
18075 | drm_WARN_ON(&dev_priv->drm, |
18076 | i9xx_calc_dpll_params(48000, &clock) != 25154); | |
2ee0da16 | 18077 | |
cd49f818 WK |
18078 | drm_dbg_kms(&dev_priv->drm, |
18079 | "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
18080 | pipe_name(pipe), clock.vco, clock.dot); | |
2ee0da16 VS |
18081 | |
18082 | fp = i9xx_dpll_compute_fp(&clock); | |
171d1562 | 18083 | dpll = DPLL_DVO_2X_MODE | |
2ee0da16 VS |
18084 | DPLL_VGA_MODE_DIS | |
18085 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
18086 | PLL_P2_DIVIDE_BY_4 | | |
18087 | PLL_REF_INPUT_DREFCLK | | |
18088 | DPLL_VCO_ENABLE; | |
18089 | ||
dc008bf0 JN |
18090 | intel_de_write(dev_priv, FP0(pipe), fp); |
18091 | intel_de_write(dev_priv, FP1(pipe), fp); | |
2ee0da16 | 18092 | |
dc008bf0 JN |
18093 | intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); |
18094 | intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
18095 | intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
18096 | intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
18097 | intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
18098 | intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
18099 | intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
2ee0da16 VS |
18100 | |
18101 | /* | |
18102 | * Apparently we need to have VGA mode enabled prior to changing | |
18103 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
18104 | * dividers, even though the register value does change. | |
18105 | */ | |
dc008bf0 JN |
18106 | intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); |
18107 | intel_de_write(dev_priv, DPLL(pipe), dpll); | |
2ee0da16 VS |
18108 | |
18109 | /* Wait for the clocks to stabilize. */ | |
dc008bf0 | 18110 | intel_de_posting_read(dev_priv, DPLL(pipe)); |
2ee0da16 VS |
18111 | udelay(150); |
18112 | ||
18113 | /* The pixel multiplier can only be updated once the | |
18114 | * DPLL is enabled and the clocks are stable. | |
18115 | * | |
18116 | * So write it again. | |
18117 | */ | |
dc008bf0 | 18118 | intel_de_write(dev_priv, DPLL(pipe), dpll); |
2ee0da16 VS |
18119 | |
18120 | /* We do this three times for luck */ | |
18121 | for (i = 0; i < 3 ; i++) { | |
dc008bf0 JN |
18122 | intel_de_write(dev_priv, DPLL(pipe), dpll); |
18123 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
2ee0da16 VS |
18124 | udelay(150); /* wait for warmup */ |
18125 | } | |
18126 | ||
dc008bf0 JN |
18127 | intel_de_write(dev_priv, PIPECONF(pipe), |
18128 | PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
18129 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
d5fb43cb VS |
18130 | |
18131 | intel_wait_for_pipe_scanline_moving(crtc); | |
2ee0da16 VS |
18132 | } |
18133 | ||
18134 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
18135 | { | |
8fedd64d VS |
18136 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
18137 | ||
cd49f818 WK |
18138 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", |
18139 | pipe_name(pipe)); | |
2ee0da16 | 18140 | |
e57291c2 PB |
18141 | drm_WARN_ON(&dev_priv->drm, |
18142 | intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & | |
18143 | DISPLAY_PLANE_ENABLE); | |
18144 | drm_WARN_ON(&dev_priv->drm, | |
18145 | intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & | |
18146 | DISPLAY_PLANE_ENABLE); | |
18147 | drm_WARN_ON(&dev_priv->drm, | |
18148 | intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & | |
18149 | DISPLAY_PLANE_ENABLE); | |
18150 | drm_WARN_ON(&dev_priv->drm, | |
18151 | intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); | |
18152 | drm_WARN_ON(&dev_priv->drm, | |
18153 | intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE); | |
2ee0da16 | 18154 | |
dc008bf0 JN |
18155 | intel_de_write(dev_priv, PIPECONF(pipe), 0); |
18156 | intel_de_posting_read(dev_priv, PIPECONF(pipe)); | |
2ee0da16 | 18157 | |
8fedd64d | 18158 | intel_wait_for_pipe_scanline_stopped(crtc); |
2ee0da16 | 18159 | |
dc008bf0 JN |
18160 | intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); |
18161 | intel_de_posting_read(dev_priv, DPLL(pipe)); | |
2ee0da16 VS |
18162 | } |
18163 | ||
b1e01595 VS |
18164 | static void |
18165 | intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) | |
18166 | { | |
18167 | struct intel_crtc *crtc; | |
fa555837 | 18168 | |
b1e01595 VS |
18169 | if (INTEL_GEN(dev_priv) >= 4) |
18170 | return; | |
fa555837 | 18171 | |
b1e01595 VS |
18172 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
18173 | struct intel_plane *plane = | |
18174 | to_intel_plane(crtc->base.primary); | |
62358aa4 VS |
18175 | struct intel_crtc *plane_crtc; |
18176 | enum pipe pipe; | |
b1e01595 | 18177 | |
62358aa4 VS |
18178 | if (!plane->get_hw_state(plane, &pipe)) |
18179 | continue; | |
18180 | ||
18181 | if (pipe == crtc->pipe) | |
b1e01595 VS |
18182 | continue; |
18183 | ||
cd49f818 WK |
18184 | drm_dbg_kms(&dev_priv->drm, |
18185 | "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", | |
18186 | plane->base.base.id, plane->base.name); | |
62358aa4 VS |
18187 | |
18188 | plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
18189 | intel_plane_disable_noatomic(plane_crtc, plane); | |
b1e01595 | 18190 | } |
fa555837 DV |
18191 | } |
18192 | ||
02e93c35 VS |
18193 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
18194 | { | |
18195 | struct drm_device *dev = crtc->base.dev; | |
18196 | struct intel_encoder *encoder; | |
18197 | ||
18198 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
18199 | return true; | |
18200 | ||
18201 | return false; | |
18202 | } | |
18203 | ||
496b0fc3 ML |
18204 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
18205 | { | |
18206 | struct drm_device *dev = encoder->base.dev; | |
18207 | struct intel_connector *connector; | |
18208 | ||
18209 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
18210 | return connector; | |
18211 | ||
18212 | return NULL; | |
18213 | } | |
18214 | ||
a168f5b3 | 18215 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
ecf837d9 | 18216 | enum pipe pch_transcoder) |
a168f5b3 VS |
18217 | { |
18218 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
ecf837d9 | 18219 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); |
a168f5b3 VS |
18220 | } |
18221 | ||
cc7a4cff | 18222 | static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state) |
24929352 | 18223 | { |
cc7a4cff VS |
18224 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
18225 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1b52ad46 | 18226 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
24929352 | 18227 | |
cc7a4cff VS |
18228 | if (INTEL_GEN(dev_priv) >= 9 || |
18229 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { | |
18230 | i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); | |
18231 | u32 val; | |
18232 | ||
18233 | if (transcoder_is_dsi(cpu_transcoder)) | |
18234 | return; | |
18235 | ||
dc008bf0 | 18236 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18237 | val &= ~HSW_FRAME_START_DELAY_MASK; |
18238 | val |= HSW_FRAME_START_DELAY(0); | |
dc008bf0 | 18239 | intel_de_write(dev_priv, reg, val); |
cc7a4cff | 18240 | } else { |
4d1de975 | 18241 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
cc7a4cff VS |
18242 | u32 val; |
18243 | ||
dc008bf0 | 18244 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18245 | val &= ~PIPECONF_FRAME_START_DELAY_MASK; |
18246 | val |= PIPECONF_FRAME_START_DELAY(0); | |
dc008bf0 | 18247 | intel_de_write(dev_priv, reg, val); |
cc7a4cff VS |
18248 | } |
18249 | ||
18250 | if (!crtc_state->has_pch_encoder) | |
18251 | return; | |
18252 | ||
18253 | if (HAS_PCH_IBX(dev_priv)) { | |
18254 | i915_reg_t reg = PCH_TRANSCONF(crtc->pipe); | |
18255 | u32 val; | |
18256 | ||
dc008bf0 | 18257 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18258 | val &= ~TRANS_FRAME_START_DELAY_MASK; |
18259 | val |= TRANS_FRAME_START_DELAY(0); | |
dc008bf0 | 18260 | intel_de_write(dev_priv, reg, val); |
cc7a4cff | 18261 | } else { |
7df49149 VS |
18262 | enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); |
18263 | i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder); | |
cc7a4cff | 18264 | u32 val; |
4d1de975 | 18265 | |
dc008bf0 | 18266 | val = intel_de_read(dev_priv, reg); |
cc7a4cff VS |
18267 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
18268 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); | |
dc008bf0 | 18269 | intel_de_write(dev_priv, reg, val); |
4d1de975 | 18270 | } |
cc7a4cff VS |
18271 | } |
18272 | ||
18273 | static void intel_sanitize_crtc(struct intel_crtc *crtc, | |
18274 | struct drm_modeset_acquire_ctx *ctx) | |
18275 | { | |
18276 | struct drm_device *dev = crtc->base.dev; | |
18277 | struct drm_i915_private *dev_priv = to_i915(dev); | |
18278 | struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); | |
24929352 | 18279 | |
1326a92c | 18280 | if (crtc_state->hw.active) { |
f9cd7b88 VS |
18281 | struct intel_plane *plane; |
18282 | ||
cc7a4cff VS |
18283 | /* Clear any frame start delays used for debugging left by the BIOS */ |
18284 | intel_sanitize_frame_start_delay(crtc_state); | |
18285 | ||
f9cd7b88 VS |
18286 | /* Disable everything but the primary plane */ |
18287 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
b1e01595 VS |
18288 | const struct intel_plane_state *plane_state = |
18289 | to_intel_plane_state(plane->base.state); | |
f9cd7b88 | 18290 | |
f90a85e7 | 18291 | if (plane_state->uapi.visible && |
b1e01595 VS |
18292 | plane->base.type != DRM_PLANE_TYPE_PRIMARY) |
18293 | intel_plane_disable_noatomic(crtc, plane); | |
f9cd7b88 | 18294 | } |
c0550305 MR |
18295 | |
18296 | /* | |
18297 | * Disable any background color set by the BIOS, but enable the | |
18298 | * gamma and CSC to match how we program our planes. | |
18299 | */ | |
18300 | if (INTEL_GEN(dev_priv) >= 9) | |
dc008bf0 JN |
18301 | intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe), |
18302 | SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE); | |
9625604c | 18303 | } |
d3eaf884 | 18304 | |
24929352 DV |
18305 | /* Adjust the state of the output pipe according to whether we |
18306 | * have active connectors/encoders. */ | |
1326a92c | 18307 | if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc)) |
56273062 | 18308 | intel_crtc_disable_noatomic(crtc, ctx); |
24929352 | 18309 | |
1326a92c | 18310 | if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { |
4cc31489 DV |
18311 | /* |
18312 | * We start out with underrun reporting disabled to avoid races. | |
18313 | * For correct bookkeeping mark this on active crtcs. | |
18314 | * | |
c5ab3bc0 DV |
18315 | * Also on gmch platforms we dont have any hardware bits to |
18316 | * disable the underrun reporting. Which means we need to start | |
18317 | * out with underrun reporting disabled also on inactive pipes, | |
18318 | * since otherwise we'll complain about the garbage we read when | |
18319 | * e.g. coming up after runtime pm. | |
18320 | * | |
4cc31489 DV |
18321 | * No protection against concurrent access is required - at |
18322 | * worst a fifo underrun happens which also sets this to false. | |
18323 | */ | |
18324 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
18325 | /* |
18326 | * We track the PCH trancoder underrun reporting state | |
18327 | * within the crtc. With crtc for pipe A housing the underrun | |
18328 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
18329 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
18330 | * and marking underrun reporting as disabled for the non-existing | |
18331 | * PCH transcoders B and C would prevent enabling the south | |
18332 | * error interrupt (see cpt_can_enable_serr_int()). | |
18333 | */ | |
ecf837d9 | 18334 | if (has_pch_trancoder(dev_priv, crtc->pipe)) |
a168f5b3 | 18335 | crtc->pch_fifo_underrun_disabled = true; |
4cc31489 | 18336 | } |
24929352 DV |
18337 | } |
18338 | ||
7bed8adc VS |
18339 | static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) |
18340 | { | |
2225f3c6 | 18341 | struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
7bed8adc VS |
18342 | |
18343 | /* | |
18344 | * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram | |
18345 | * the hardware when a high res displays plugged in. DPLL P | |
18346 | * divider is zero, and the pipe timings are bonkers. We'll | |
18347 | * try to disable everything in that case. | |
18348 | * | |
18349 | * FIXME would be nice to be able to sanitize this state | |
18350 | * without several WARNs, but for now let's take the easy | |
18351 | * road. | |
18352 | */ | |
18353 | return IS_GEN(dev_priv, 6) && | |
1326a92c | 18354 | crtc_state->hw.active && |
7bed8adc VS |
18355 | crtc_state->shared_dpll && |
18356 | crtc_state->port_clock == 0; | |
18357 | } | |
18358 | ||
24929352 DV |
18359 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
18360 | { | |
70332ac5 | 18361 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24929352 | 18362 | struct intel_connector *connector; |
7bed8adc VS |
18363 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
18364 | struct intel_crtc_state *crtc_state = crtc ? | |
18365 | to_intel_crtc_state(crtc->base.state) : NULL; | |
24929352 DV |
18366 | |
18367 | /* We need to check both for a crtc link (meaning that the | |
18368 | * encoder is active and trying to read from a pipe) and the | |
18369 | * pipe itself being active. */ | |
7bed8adc | 18370 | bool has_active_crtc = crtc_state && |
1326a92c | 18371 | crtc_state->hw.active; |
7bed8adc VS |
18372 | |
18373 | if (crtc_state && has_bogus_dpll_config(crtc_state)) { | |
cd49f818 WK |
18374 | drm_dbg_kms(&dev_priv->drm, |
18375 | "BIOS has misprogrammed the hardware. Disabling pipe %c\n", | |
18376 | pipe_name(crtc->pipe)); | |
7bed8adc VS |
18377 | has_active_crtc = false; |
18378 | } | |
24929352 | 18379 | |
496b0fc3 ML |
18380 | connector = intel_encoder_find_connector(encoder); |
18381 | if (connector && !has_active_crtc) { | |
cd49f818 WK |
18382 | drm_dbg_kms(&dev_priv->drm, |
18383 | "[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
18384 | encoder->base.base.id, | |
18385 | encoder->base.name); | |
24929352 DV |
18386 | |
18387 | /* Connector is active, but has no active pipe. This is | |
18388 | * fallout from our resume register restoring. Disable | |
18389 | * the encoder manually again. */ | |
7bed8adc VS |
18390 | if (crtc_state) { |
18391 | struct drm_encoder *best_encoder; | |
fd6bbda9 | 18392 | |
cd49f818 WK |
18393 | drm_dbg_kms(&dev_priv->drm, |
18394 | "[ENCODER:%d:%s] manually disabled\n", | |
18395 | encoder->base.base.id, | |
18396 | encoder->base.name); | |
7bed8adc VS |
18397 | |
18398 | /* avoid oopsing in case the hooks consult best_encoder */ | |
18399 | best_encoder = connector->base.state->best_encoder; | |
18400 | connector->base.state->best_encoder = &encoder->base; | |
18401 | ||
ede9771d | 18402 | /* FIXME NULL atomic state passed! */ |
c84c6fe3 | 18403 | if (encoder->disable) |
ede9771d | 18404 | encoder->disable(NULL, encoder, crtc_state, |
7bed8adc | 18405 | connector->base.state); |
a62d1497 | 18406 | if (encoder->post_disable) |
ede9771d | 18407 | encoder->post_disable(NULL, encoder, crtc_state, |
7bed8adc VS |
18408 | connector->base.state); |
18409 | ||
18410 | connector->base.state->best_encoder = best_encoder; | |
24929352 | 18411 | } |
7f1950fb | 18412 | encoder->base.crtc = NULL; |
24929352 DV |
18413 | |
18414 | /* Inconsistent output/port/pipe state happens presumably due to | |
18415 | * a bug in one of the get_hw_state functions. Or someplace else | |
18416 | * in our code, like the register restore mess on resume. Clamp | |
18417 | * things to off as a safer default. */ | |
fd6bbda9 ML |
18418 | |
18419 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
18420 | connector->base.encoder = NULL; | |
24929352 | 18421 | } |
d6cae4aa ML |
18422 | |
18423 | /* notify opregion of the sanitized encoder state */ | |
18424 | intel_opregion_notify_encoder(encoder, connector && has_active_crtc); | |
70332ac5 ID |
18425 | |
18426 | if (INTEL_GEN(dev_priv) >= 11) | |
18427 | icl_sanitize_encoder_pll_mapping(encoder); | |
24929352 DV |
18428 | } |
18429 | ||
f9cd7b88 | 18430 | /* FIXME read out full plane state for all planes */ |
62358aa4 | 18431 | static void readout_plane_state(struct drm_i915_private *dev_priv) |
d032ffa0 | 18432 | { |
b1e01595 | 18433 | struct intel_plane *plane; |
62358aa4 | 18434 | struct intel_crtc *crtc; |
d032ffa0 | 18435 | |
62358aa4 | 18436 | for_each_intel_plane(&dev_priv->drm, plane) { |
b1e01595 VS |
18437 | struct intel_plane_state *plane_state = |
18438 | to_intel_plane_state(plane->base.state); | |
62358aa4 VS |
18439 | struct intel_crtc_state *crtc_state; |
18440 | enum pipe pipe = PIPE_A; | |
eade6c89 VS |
18441 | bool visible; |
18442 | ||
18443 | visible = plane->get_hw_state(plane, &pipe); | |
b26d3ea3 | 18444 | |
62358aa4 VS |
18445 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
18446 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
18447 | ||
b1e01595 | 18448 | intel_set_plane_visible(crtc_state, plane_state, visible); |
7a4a2a46 | 18449 | |
cd49f818 WK |
18450 | drm_dbg_kms(&dev_priv->drm, |
18451 | "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", | |
18452 | plane->base.base.id, plane->base.name, | |
18453 | enableddisabled(visible), pipe_name(pipe)); | |
b1e01595 | 18454 | } |
62358aa4 VS |
18455 | |
18456 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
18457 | struct intel_crtc_state *crtc_state = | |
18458 | to_intel_crtc_state(crtc->base.state); | |
18459 | ||
18460 | fixup_active_planes(crtc_state); | |
18461 | } | |
98ec7739 VS |
18462 | } |
18463 | ||
30e984df | 18464 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 18465 | { |
fac5e23e | 18466 | struct drm_i915_private *dev_priv = to_i915(dev); |
28a30b45 VS |
18467 | struct intel_cdclk_state *cdclk_state = |
18468 | to_intel_cdclk_state(dev_priv->cdclk.obj.state); | |
3cf43cdc VS |
18469 | struct intel_dbuf_state *dbuf_state = |
18470 | to_intel_dbuf_state(dev_priv->dbuf.obj.state); | |
24929352 | 18471 | enum pipe pipe; |
24929352 DV |
18472 | struct intel_crtc *crtc; |
18473 | struct intel_encoder *encoder; | |
18474 | struct intel_connector *connector; | |
f9e905ca | 18475 | struct drm_connector_list_iter conn_iter; |
0c2d5512 | 18476 | u8 active_pipes = 0; |
24929352 | 18477 | |
d3fcc808 | 18478 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
18479 | struct intel_crtc_state *crtc_state = |
18480 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 18481 | |
2225f3c6 | 18482 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); |
58d124ea | 18483 | intel_crtc_free_hw_state(crtc_state); |
979e94c1 | 18484 | intel_crtc_state_reset(crtc_state, crtc); |
24929352 | 18485 | |
1326a92c | 18486 | crtc_state->hw.active = crtc_state->hw.enable = |
565602d7 ML |
18487 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
18488 | ||
1326a92c ML |
18489 | crtc->base.enabled = crtc_state->hw.enable; |
18490 | crtc->active = crtc_state->hw.active; | |
565602d7 | 18491 | |
1326a92c | 18492 | if (crtc_state->hw.active) |
0c2d5512 | 18493 | active_pipes |= BIT(crtc->pipe); |
565602d7 | 18494 | |
cd49f818 WK |
18495 | drm_dbg_kms(&dev_priv->drm, |
18496 | "[CRTC:%d:%s] hw state readout: %s\n", | |
18497 | crtc->base.base.id, crtc->base.name, | |
18498 | enableddisabled(crtc_state->hw.active)); | |
24929352 DV |
18499 | } |
18500 | ||
3cf43cdc VS |
18501 | dev_priv->active_pipes = cdclk_state->active_pipes = |
18502 | dbuf_state->active_pipes = active_pipes; | |
0c2d5512 | 18503 | |
62358aa4 VS |
18504 | readout_plane_state(dev_priv); |
18505 | ||
830b2cdc | 18506 | intel_dpll_readout_hw_state(dev_priv); |
5358901f | 18507 | |
b2784e15 | 18508 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
18509 | pipe = 0; |
18510 | ||
18511 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
18512 | struct intel_crtc_state *crtc_state; |
18513 | ||
98187836 | 18514 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 18515 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 18516 | |
045ac3b5 | 18517 | encoder->base.crtc = &crtc->base; |
a8cd6da0 | 18518 | encoder->get_config(encoder, crtc_state); |
24929352 DV |
18519 | } else { |
18520 | encoder->base.crtc = NULL; | |
18521 | } | |
18522 | ||
cd49f818 WK |
18523 | drm_dbg_kms(&dev_priv->drm, |
18524 | "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", | |
18525 | encoder->base.base.id, encoder->base.name, | |
18526 | enableddisabled(encoder->base.crtc), | |
18527 | pipe_name(pipe)); | |
24929352 DV |
18528 | } |
18529 | ||
f9e905ca DV |
18530 | drm_connector_list_iter_begin(dev, &conn_iter); |
18531 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 | 18532 | if (connector->get_hw_state(connector)) { |
de3b67af VS |
18533 | struct intel_crtc_state *crtc_state; |
18534 | struct intel_crtc *crtc; | |
18535 | ||
24929352 | 18536 | connector->base.dpms = DRM_MODE_DPMS_ON; |
2aa974c9 | 18537 | |
fa7edcd2 | 18538 | encoder = intel_attached_encoder(connector); |
2aa974c9 ML |
18539 | connector->base.encoder = &encoder->base; |
18540 | ||
de3b67af VS |
18541 | crtc = to_intel_crtc(encoder->base.crtc); |
18542 | crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; | |
18543 | ||
1326a92c | 18544 | if (crtc_state && crtc_state->hw.active) { |
2aa974c9 ML |
18545 | /* |
18546 | * This has to be done during hardware readout | |
18547 | * because anything calling .crtc_disable may | |
18548 | * rely on the connector_mask being accurate. | |
18549 | */ | |
2225f3c6 | 18550 | crtc_state->uapi.connector_mask |= |
40560e26 | 18551 | drm_connector_mask(&connector->base); |
2225f3c6 | 18552 | crtc_state->uapi.encoder_mask |= |
40560e26 | 18553 | drm_encoder_mask(&encoder->base); |
2aa974c9 | 18554 | } |
24929352 DV |
18555 | } else { |
18556 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
18557 | connector->base.encoder = NULL; | |
18558 | } | |
cd49f818 WK |
18559 | drm_dbg_kms(&dev_priv->drm, |
18560 | "[CONNECTOR:%d:%s] hw state readout: %s\n", | |
18561 | connector->base.base.id, connector->base.name, | |
18562 | enableddisabled(connector->base.encoder)); | |
24929352 | 18563 | } |
f9e905ca | 18564 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
18565 | |
18566 | for_each_intel_crtc(dev, crtc) { | |
c457d9cf VS |
18567 | struct intel_bw_state *bw_state = |
18568 | to_intel_bw_state(dev_priv->bw_obj.state); | |
a8cd6da0 VS |
18569 | struct intel_crtc_state *crtc_state = |
18570 | to_intel_crtc_state(crtc->base.state); | |
c457d9cf | 18571 | struct intel_plane *plane; |
d305e061 | 18572 | int min_cdclk = 0; |
aca1ebf4 | 18573 | |
1326a92c | 18574 | if (crtc_state->hw.active) { |
58d124ea | 18575 | struct drm_display_mode *mode = &crtc_state->hw.mode; |
4e380d08 | 18576 | |
1326a92c | 18577 | intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode, |
4e380d08 VS |
18578 | crtc_state); |
18579 | ||
58d124ea ML |
18580 | *mode = crtc_state->hw.adjusted_mode; |
18581 | mode->hdisplay = crtc_state->pipe_src_w; | |
18582 | mode->vdisplay = crtc_state->pipe_src_h; | |
7f4c6284 VS |
18583 | |
18584 | /* | |
18585 | * The initial mode needs to be set in order to keep | |
18586 | * the atomic core happy. It wants a valid mode if the | |
18587 | * crtc's enabled, so we do the above call. | |
18588 | * | |
7800fb69 DV |
18589 | * But we don't set all the derived state fully, hence |
18590 | * set a flag to indicate that a full recalculation is | |
18591 | * needed on the next commit. | |
7f4c6284 | 18592 | */ |
a227569d | 18593 | crtc_state->inherited = true; |
9eca6832 | 18594 | |
a7d1b3f4 VS |
18595 | intel_crtc_compute_pixel_rate(crtc_state); |
18596 | ||
99325429 | 18597 | intel_crtc_update_active_timings(crtc_state); |
58d124ea ML |
18598 | |
18599 | intel_crtc_copy_hw_to_uapi_state(crtc_state); | |
7f4c6284 | 18600 | } |
e3b247da | 18601 | |
c457d9cf VS |
18602 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { |
18603 | const struct intel_plane_state *plane_state = | |
18604 | to_intel_plane_state(plane->base.state); | |
18605 | ||
18606 | /* | |
18607 | * FIXME don't have the fb yet, so can't | |
18608 | * use intel_plane_data_rate() :( | |
18609 | */ | |
f90a85e7 | 18610 | if (plane_state->uapi.visible) |
c457d9cf VS |
18611 | crtc_state->data_rate[plane->id] = |
18612 | 4 * crtc_state->pixel_rate; | |
bb6ae9e6 VS |
18613 | /* |
18614 | * FIXME don't have the fb yet, so can't | |
18615 | * use plane->min_cdclk() :( | |
18616 | */ | |
f90a85e7 | 18617 | if (plane_state->uapi.visible && plane->min_cdclk) { |
bb6ae9e6 VS |
18618 | if (crtc_state->double_wide || |
18619 | INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
18620 | crtc_state->min_cdclk[plane->id] = | |
18621 | DIV_ROUND_UP(crtc_state->pixel_rate, 2); | |
18622 | else | |
18623 | crtc_state->min_cdclk[plane->id] = | |
18624 | crtc_state->pixel_rate; | |
18625 | } | |
cd49f818 WK |
18626 | drm_dbg_kms(&dev_priv->drm, |
18627 | "[PLANE:%d:%s] min_cdclk %d kHz\n", | |
18628 | plane->base.base.id, plane->base.name, | |
18629 | crtc_state->min_cdclk[plane->id]); | |
bb6ae9e6 VS |
18630 | } |
18631 | ||
1326a92c | 18632 | if (crtc_state->hw.active) { |
bb6ae9e6 | 18633 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
e57291c2 | 18634 | if (drm_WARN_ON(dev, min_cdclk < 0)) |
bb6ae9e6 | 18635 | min_cdclk = 0; |
c457d9cf VS |
18636 | } |
18637 | ||
1965de63 VS |
18638 | cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; |
18639 | cdclk_state->min_voltage_level[crtc->pipe] = | |
bb6ae9e6 VS |
18640 | crtc_state->min_voltage_level; |
18641 | ||
c457d9cf VS |
18642 | intel_bw_crtc_update(bw_state, crtc_state); |
18643 | ||
a8cd6da0 | 18644 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 18645 | } |
30e984df DV |
18646 | } |
18647 | ||
62b69566 ACO |
18648 | static void |
18649 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
18650 | { | |
18651 | struct intel_encoder *encoder; | |
18652 | ||
18653 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
52528055 | 18654 | struct intel_crtc_state *crtc_state; |
62b69566 ACO |
18655 | |
18656 | if (!encoder->get_power_domains) | |
18657 | continue; | |
18658 | ||
52528055 | 18659 | /* |
b79ebe74 ID |
18660 | * MST-primary and inactive encoders don't have a crtc state |
18661 | * and neither of these require any power domain references. | |
52528055 | 18662 | */ |
b79ebe74 ID |
18663 | if (!encoder->base.crtc) |
18664 | continue; | |
52528055 | 18665 | |
b79ebe74 | 18666 | crtc_state = to_intel_crtc_state(encoder->base.crtc->state); |
3a52fb7e | 18667 | encoder->get_power_domains(encoder, crtc_state); |
62b69566 ACO |
18668 | } |
18669 | } | |
18670 | ||
df49ec82 RV |
18671 | static void intel_early_display_was(struct drm_i915_private *dev_priv) |
18672 | { | |
1e1a139d MR |
18673 | /* |
18674 | * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl | |
18675 | * Also known as Wa_14010480278. | |
18676 | */ | |
18677 | if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv)) | |
dc008bf0 JN |
18678 | intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, |
18679 | intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); | |
df49ec82 RV |
18680 | |
18681 | if (IS_HASWELL(dev_priv)) { | |
18682 | /* | |
18683 | * WaRsPkgCStateDisplayPMReq:hsw | |
18684 | * System hang if this isn't done before disabling all planes! | |
18685 | */ | |
dc008bf0 JN |
18686 | intel_de_write(dev_priv, CHICKEN_PAR1_1, |
18687 | intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
df49ec82 RV |
18688 | } |
18689 | } | |
18690 | ||
3aefb67f VS |
18691 | static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, |
18692 | enum port port, i915_reg_t hdmi_reg) | |
18693 | { | |
dc008bf0 | 18694 | u32 val = intel_de_read(dev_priv, hdmi_reg); |
3aefb67f VS |
18695 | |
18696 | if (val & SDVO_ENABLE || | |
18697 | (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) | |
18698 | return; | |
18699 | ||
cd49f818 WK |
18700 | drm_dbg_kms(&dev_priv->drm, |
18701 | "Sanitizing transcoder select for HDMI %c\n", | |
18702 | port_name(port)); | |
3aefb67f VS |
18703 | |
18704 | val &= ~SDVO_PIPE_SEL_MASK; | |
18705 | val |= SDVO_PIPE_SEL(PIPE_A); | |
18706 | ||
dc008bf0 | 18707 | intel_de_write(dev_priv, hdmi_reg, val); |
3aefb67f VS |
18708 | } |
18709 | ||
18710 | static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, | |
18711 | enum port port, i915_reg_t dp_reg) | |
18712 | { | |
dc008bf0 | 18713 | u32 val = intel_de_read(dev_priv, dp_reg); |
3aefb67f VS |
18714 | |
18715 | if (val & DP_PORT_EN || | |
18716 | (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) | |
18717 | return; | |
18718 | ||
cd49f818 WK |
18719 | drm_dbg_kms(&dev_priv->drm, |
18720 | "Sanitizing transcoder select for DP %c\n", | |
18721 | port_name(port)); | |
3aefb67f VS |
18722 | |
18723 | val &= ~DP_PIPE_SEL_MASK; | |
18724 | val |= DP_PIPE_SEL(PIPE_A); | |
18725 | ||
dc008bf0 | 18726 | intel_de_write(dev_priv, dp_reg, val); |
3aefb67f VS |
18727 | } |
18728 | ||
18729 | static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) | |
18730 | { | |
18731 | /* | |
18732 | * The BIOS may select transcoder B on some of the PCH | |
18733 | * ports even it doesn't enable the port. This would trip | |
18734 | * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). | |
18735 | * Sanitize the transcoder select bits to prevent that. We | |
18736 | * assume that the BIOS never actually enabled the port, | |
18737 | * because if it did we'd actually have to toggle the port | |
18738 | * on and back off to make the transcoder A select stick | |
18739 | * (see. intel_dp_link_down(), intel_disable_hdmi(), | |
18740 | * intel_disable_sdvo()). | |
18741 | */ | |
18742 | ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); | |
18743 | ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); | |
18744 | ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); | |
18745 | ||
18746 | /* PCH SDVOB multiplex with HDMIB */ | |
18747 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); | |
18748 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); | |
18749 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); | |
18750 | } | |
18751 | ||
043e9bda ML |
18752 | /* Scan out the current hw modeset state, |
18753 | * and sanitizes it to the current state | |
18754 | */ | |
18755 | static void | |
aecd36b8 VS |
18756 | intel_modeset_setup_hw_state(struct drm_device *dev, |
18757 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 18758 | { |
fac5e23e | 18759 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 18760 | struct intel_encoder *encoder; |
0e6e0be4 CW |
18761 | struct intel_crtc *crtc; |
18762 | intel_wakeref_t wakeref; | |
30e984df | 18763 | |
0e6e0be4 | 18764 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
2cd9a689 | 18765 | |
df49ec82 | 18766 | intel_early_display_was(dev_priv); |
30e984df | 18767 | intel_modeset_readout_hw_state(dev); |
24929352 DV |
18768 | |
18769 | /* HW state is read out, now we need to sanitize this mess. */ | |
32691b58 ID |
18770 | |
18771 | /* Sanitize the TypeC port mode upfront, encoders depend on this */ | |
18772 | for_each_intel_encoder(dev, encoder) { | |
d8fe2ab6 MR |
18773 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
18774 | ||
32691b58 ID |
18775 | /* We need to sanitize only the MST primary port. */ |
18776 | if (encoder->type != INTEL_OUTPUT_DP_MST && | |
d8fe2ab6 | 18777 | intel_phy_is_tc(dev_priv, phy)) |
b7d02c3a | 18778 | intel_tc_port_sanitize(enc_to_dig_port(encoder)); |
32691b58 ID |
18779 | } |
18780 | ||
62b69566 | 18781 | get_encoder_power_domains(dev_priv); |
3aefb67f VS |
18782 | |
18783 | if (HAS_PCH_IBX(dev_priv)) | |
18784 | ibx_sanitize_pch_ports(dev_priv); | |
62b69566 | 18785 | |
68bc30de VS |
18786 | /* |
18787 | * intel_sanitize_plane_mapping() may need to do vblank | |
18788 | * waits, so we need vblank interrupts restored beforehand. | |
18789 | */ | |
18790 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
777bf6d7 VS |
18791 | struct intel_crtc_state *crtc_state = |
18792 | to_intel_crtc_state(crtc->base.state); | |
32db0b65 | 18793 | |
68bc30de | 18794 | drm_crtc_vblank_reset(&crtc->base); |
b1e01595 | 18795 | |
1326a92c | 18796 | if (crtc_state->hw.active) |
32db0b65 | 18797 | intel_crtc_vblank_on(crtc_state); |
24929352 DV |
18798 | } |
18799 | ||
68bc30de | 18800 | intel_sanitize_plane_mapping(dev_priv); |
e2af48c6 | 18801 | |
68bc30de VS |
18802 | for_each_intel_encoder(dev, encoder) |
18803 | intel_sanitize_encoder(encoder); | |
18804 | ||
18805 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
777bf6d7 | 18806 | struct intel_crtc_state *crtc_state = |
7b0bcead | 18807 | to_intel_crtc_state(crtc->base.state); |
777bf6d7 | 18808 | |
aecd36b8 | 18809 | intel_sanitize_crtc(crtc, ctx); |
10d75f54 | 18810 | intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); |
24929352 | 18811 | } |
9a935856 | 18812 | |
d29b2f9d ACO |
18813 | intel_modeset_update_connector_atomic_state(dev); |
18814 | ||
830b2cdc | 18815 | intel_dpll_sanitize_state(dev_priv); |
35c95375 | 18816 | |
04548cba | 18817 | if (IS_G4X(dev_priv)) { |
cd1d3ee9 | 18818 | g4x_wm_get_hw_state(dev_priv); |
04548cba VS |
18819 | g4x_wm_sanitize(dev_priv); |
18820 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
cd1d3ee9 | 18821 | vlv_wm_get_hw_state(dev_priv); |
602ae835 | 18822 | vlv_wm_sanitize(dev_priv); |
a029fa4d | 18823 | } else if (INTEL_GEN(dev_priv) >= 9) { |
cd1d3ee9 | 18824 | skl_wm_get_hw_state(dev_priv); |
602ae835 | 18825 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cd1d3ee9 | 18826 | ilk_wm_get_hw_state(dev_priv); |
602ae835 | 18827 | } |
292b990e ML |
18828 | |
18829 | for_each_intel_crtc(dev, crtc) { | |
777bf6d7 VS |
18830 | struct intel_crtc_state *crtc_state = |
18831 | to_intel_crtc_state(crtc->base.state); | |
d8fc70b7 | 18832 | u64 put_domains; |
292b990e | 18833 | |
afe0c21b | 18834 | put_domains = modeset_get_crtc_power_domains(crtc_state); |
e57291c2 | 18835 | if (drm_WARN_ON(dev, put_domains)) |
292b990e ML |
18836 | modeset_put_power_domains(dev_priv, put_domains); |
18837 | } | |
2cd9a689 | 18838 | |
0e6e0be4 | 18839 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); |
043e9bda | 18840 | } |
7d0bc1ea | 18841 | |
043e9bda ML |
18842 | void intel_display_resume(struct drm_device *dev) |
18843 | { | |
e2c8b870 ML |
18844 | struct drm_i915_private *dev_priv = to_i915(dev); |
18845 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
18846 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 18847 | int ret; |
f30da187 | 18848 | |
e2c8b870 | 18849 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
18850 | if (state) |
18851 | state->acquire_ctx = &ctx; | |
043e9bda | 18852 | |
e2c8b870 | 18853 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 18854 | |
73974893 ML |
18855 | while (1) { |
18856 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
18857 | if (ret != -EDEADLK) | |
18858 | break; | |
043e9bda | 18859 | |
e2c8b870 | 18860 | drm_modeset_backoff(&ctx); |
e2c8b870 | 18861 | } |
043e9bda | 18862 | |
73974893 | 18863 | if (!ret) |
581e49fe | 18864 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 18865 | |
2503a0fe | 18866 | intel_enable_ipc(dev_priv); |
e2c8b870 ML |
18867 | drm_modeset_drop_locks(&ctx); |
18868 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 18869 | |
0853695c | 18870 | if (ret) |
cd49f818 WK |
18871 | drm_err(&dev_priv->drm, |
18872 | "Restoring old state failed with %i\n", ret); | |
3c5e37f1 CW |
18873 | if (state) |
18874 | drm_atomic_state_put(state); | |
2c7111db CW |
18875 | } |
18876 | ||
9980c3c1 | 18877 | static void intel_hpd_poll_fini(struct drm_i915_private *i915) |
886c6b86 MN |
18878 | { |
18879 | struct intel_connector *connector; | |
18880 | struct drm_connector_list_iter conn_iter; | |
18881 | ||
448aa911 | 18882 | /* Kill all the work that may have been queued by hpd. */ |
9980c3c1 | 18883 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); |
886c6b86 MN |
18884 | for_each_intel_connector_iter(connector, &conn_iter) { |
18885 | if (connector->modeset_retry_work.func) | |
18886 | cancel_work_sync(&connector->modeset_retry_work); | |
d3dacc70 R |
18887 | if (connector->hdcp.shim) { |
18888 | cancel_delayed_work_sync(&connector->hdcp.check_work); | |
18889 | cancel_work_sync(&connector->hdcp.prop_work); | |
ee5e5e7a | 18890 | } |
886c6b86 MN |
18891 | } |
18892 | drm_connector_list_iter_end(&conn_iter); | |
18893 | } | |
18894 | ||
93a0ed6c | 18895 | /* part #1: call before irq uninstall */ |
9980c3c1 | 18896 | void intel_modeset_driver_remove(struct drm_i915_private *i915) |
79e53945 | 18897 | { |
9980c3c1 JN |
18898 | flush_workqueue(i915->flip_wq); |
18899 | flush_workqueue(i915->modeset_wq); | |
8bcf9f70 | 18900 | |
9980c3c1 | 18901 | flush_work(&i915->atomic_helper.free_work); |
e57291c2 | 18902 | drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); |
93a0ed6c | 18903 | } |
eb955eee | 18904 | |
93a0ed6c JN |
18905 | /* part #2: call after irq uninstall */ |
18906 | void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) | |
18907 | { | |
fd0c0642 DV |
18908 | /* |
18909 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
18910 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
18911 | */ | |
9980c3c1 | 18912 | intel_hpd_poll_fini(i915); |
fd0c0642 | 18913 | |
d5746bf2 JRS |
18914 | /* |
18915 | * MST topology needs to be suspended so we don't have any calls to | |
18916 | * fbdev after it's finalized. MST will be destroyed later as part of | |
18917 | * drm_mode_config_cleanup() | |
18918 | */ | |
18919 | intel_dp_mst_suspend(i915); | |
18920 | ||
4f256d82 | 18921 | /* poll work can call into fbdev, hence clean that up afterwards */ |
9980c3c1 | 18922 | intel_fbdev_fini(i915); |
4f256d82 | 18923 | |
723bfd70 JB |
18924 | intel_unregister_dsm_handler(); |
18925 | ||
9980c3c1 | 18926 | intel_fbc_global_disable(i915); |
69341a5e | 18927 | |
1630fe75 CW |
18928 | /* flush any delayed tasks or pending work */ |
18929 | flush_scheduled_work(); | |
18930 | ||
9980c3c1 | 18931 | intel_hdcp_component_fini(i915); |
9055aac7 | 18932 | |
0ef1905e | 18933 | intel_mode_config_cleanup(i915); |
4d7bb011 | 18934 | |
9980c3c1 | 18935 | intel_overlay_cleanup(i915); |
ae48434c | 18936 | |
9980c3c1 | 18937 | intel_gmbus_teardown(i915); |
757fffcf | 18938 | |
9980c3c1 JN |
18939 | destroy_workqueue(i915->flip_wq); |
18940 | destroy_workqueue(i915->modeset_wq); | |
acde44b5 | 18941 | |
9980c3c1 | 18942 | intel_fbc_cleanup_cfb(i915); |
79e53945 JB |
18943 | } |
18944 | ||
eb4612d8 JN |
18945 | /* part #3: call after gem init */ |
18946 | void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) | |
18947 | { | |
18948 | intel_csr_ucode_fini(i915); | |
18949 | ||
18950 | intel_power_domains_driver_remove(i915); | |
18951 | ||
18952 | intel_vga_unregister(i915); | |
18953 | ||
18954 | intel_bios_driver_remove(i915); | |
18955 | } | |
18956 | ||
98a2f411 CW |
18957 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
18958 | ||
c4a1d9e4 | 18959 | struct intel_display_error_state { |
ff57f1b0 PZ |
18960 | |
18961 | u32 power_well_driver; | |
18962 | ||
c4a1d9e4 CW |
18963 | struct intel_cursor_error_state { |
18964 | u32 control; | |
18965 | u32 position; | |
18966 | u32 base; | |
18967 | u32 size; | |
52331309 | 18968 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
18969 | |
18970 | struct intel_pipe_error_state { | |
ddf9c536 | 18971 | bool power_domain_on; |
c4a1d9e4 | 18972 | u32 source; |
f301b1e1 | 18973 | u32 stat; |
52331309 | 18974 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
18975 | |
18976 | struct intel_plane_error_state { | |
18977 | u32 control; | |
18978 | u32 stride; | |
18979 | u32 size; | |
18980 | u32 pos; | |
18981 | u32 addr; | |
18982 | u32 surface; | |
18983 | u32 tile_offset; | |
52331309 | 18984 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
18985 | |
18986 | struct intel_transcoder_error_state { | |
062de72b | 18987 | bool available; |
ddf9c536 | 18988 | bool power_domain_on; |
63b66e5b CW |
18989 | enum transcoder cpu_transcoder; |
18990 | ||
18991 | u32 conf; | |
18992 | ||
18993 | u32 htotal; | |
18994 | u32 hblank; | |
18995 | u32 hsync; | |
18996 | u32 vtotal; | |
18997 | u32 vblank; | |
18998 | u32 vsync; | |
f1f1d4fa | 18999 | } transcoder[5]; |
c4a1d9e4 CW |
19000 | }; |
19001 | ||
19002 | struct intel_display_error_state * | |
c033666a | 19003 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 19004 | { |
c4a1d9e4 | 19005 | struct intel_display_error_state *error; |
63b66e5b CW |
19006 | int transcoders[] = { |
19007 | TRANSCODER_A, | |
19008 | TRANSCODER_B, | |
19009 | TRANSCODER_C, | |
f1f1d4fa | 19010 | TRANSCODER_D, |
63b66e5b CW |
19011 | TRANSCODER_EDP, |
19012 | }; | |
c4a1d9e4 CW |
19013 | int i; |
19014 | ||
062de72b LDM |
19015 | BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder)); |
19016 | ||
da27bd41 | 19017 | if (!HAS_DISPLAY(dev_priv)) |
63b66e5b CW |
19018 | return NULL; |
19019 | ||
9d1cb914 | 19020 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
19021 | if (error == NULL) |
19022 | return NULL; | |
19023 | ||
c033666a | 19024 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
dc008bf0 JN |
19025 | error->power_well_driver = intel_de_read(dev_priv, |
19026 | HSW_PWR_WELL_CTL2); | |
ff57f1b0 | 19027 | |
055e393f | 19028 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 19029 | error->pipe[i].power_domain_on = |
f458ebbc DV |
19030 | __intel_display_power_is_enabled(dev_priv, |
19031 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 19032 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
19033 | continue; |
19034 | ||
dc008bf0 JN |
19035 | error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i)); |
19036 | error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i)); | |
19037 | error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i)); | |
c4a1d9e4 | 19038 | |
dc008bf0 JN |
19039 | error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)); |
19040 | error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i)); | |
c033666a | 19041 | if (INTEL_GEN(dev_priv) <= 3) { |
dc008bf0 JN |
19042 | error->plane[i].size = intel_de_read(dev_priv, |
19043 | DSPSIZE(i)); | |
19044 | error->plane[i].pos = intel_de_read(dev_priv, | |
19045 | DSPPOS(i)); | |
80ca378b | 19046 | } |
c033666a | 19047 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
dc008bf0 JN |
19048 | error->plane[i].addr = intel_de_read(dev_priv, |
19049 | DSPADDR(i)); | |
c033666a | 19050 | if (INTEL_GEN(dev_priv) >= 4) { |
dc008bf0 JN |
19051 | error->plane[i].surface = intel_de_read(dev_priv, |
19052 | DSPSURF(i)); | |
19053 | error->plane[i].tile_offset = intel_de_read(dev_priv, | |
19054 | DSPTILEOFF(i)); | |
c4a1d9e4 CW |
19055 | } |
19056 | ||
dc008bf0 | 19057 | error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)); |
f301b1e1 | 19058 | |
b2ae318a | 19059 | if (HAS_GMCH(dev_priv)) |
dc008bf0 JN |
19060 | error->pipe[i].stat = intel_de_read(dev_priv, |
19061 | PIPESTAT(i)); | |
63b66e5b CW |
19062 | } |
19063 | ||
062de72b | 19064 | for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { |
63b66e5b CW |
19065 | enum transcoder cpu_transcoder = transcoders[i]; |
19066 | ||
10cf8e75 | 19067 | if (!HAS_TRANSCODER(dev_priv, cpu_transcoder)) |
062de72b LDM |
19068 | continue; |
19069 | ||
19070 | error->transcoder[i].available = true; | |
ddf9c536 | 19071 | error->transcoder[i].power_domain_on = |
f458ebbc | 19072 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 19073 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 19074 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
19075 | continue; |
19076 | ||
63b66e5b CW |
19077 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
19078 | ||
dc008bf0 JN |
19079 | error->transcoder[i].conf = intel_de_read(dev_priv, |
19080 | PIPECONF(cpu_transcoder)); | |
19081 | error->transcoder[i].htotal = intel_de_read(dev_priv, | |
19082 | HTOTAL(cpu_transcoder)); | |
19083 | error->transcoder[i].hblank = intel_de_read(dev_priv, | |
19084 | HBLANK(cpu_transcoder)); | |
19085 | error->transcoder[i].hsync = intel_de_read(dev_priv, | |
19086 | HSYNC(cpu_transcoder)); | |
19087 | error->transcoder[i].vtotal = intel_de_read(dev_priv, | |
19088 | VTOTAL(cpu_transcoder)); | |
19089 | error->transcoder[i].vblank = intel_de_read(dev_priv, | |
19090 | VBLANK(cpu_transcoder)); | |
19091 | error->transcoder[i].vsync = intel_de_read(dev_priv, | |
19092 | VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
19093 | } |
19094 | ||
19095 | return error; | |
19096 | } | |
19097 | ||
edc3d884 MK |
19098 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
19099 | ||
c4a1d9e4 | 19100 | void |
edc3d884 | 19101 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
19102 | struct intel_display_error_state *error) |
19103 | { | |
5a4c6f1b | 19104 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
19105 | int i; |
19106 | ||
63b66e5b CW |
19107 | if (!error) |
19108 | return; | |
19109 | ||
24977870 | 19110 | err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv)); |
8652744b | 19111 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 19112 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 19113 | error->power_well_driver); |
055e393f | 19114 | for_each_pipe(dev_priv, i) { |
edc3d884 | 19115 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 19116 | err_printf(m, " Power: %s\n", |
87ad3212 | 19117 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 19118 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 19119 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
19120 | |
19121 | err_printf(m, "Plane [%d]:\n", i); | |
19122 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
19123 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 19124 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
19125 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
19126 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 19127 | } |
772c2a51 | 19128 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 19129 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 19130 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
19131 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
19132 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
19133 | } |
19134 | ||
edc3d884 MK |
19135 | err_printf(m, "Cursor [%d]:\n", i); |
19136 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
19137 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
19138 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 19139 | } |
63b66e5b | 19140 | |
062de72b LDM |
19141 | for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { |
19142 | if (!error->transcoder[i].available) | |
19143 | continue; | |
19144 | ||
da205630 | 19145 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 19146 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 19147 | err_printf(m, " Power: %s\n", |
87ad3212 | 19148 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
19149 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
19150 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
19151 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
19152 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
19153 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
19154 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
19155 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
19156 | } | |
c4a1d9e4 | 19157 | } |
98a2f411 CW |
19158 | |
19159 | #endif |