]>
Commit | Line | Data |
---|---|---|
0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
55367a27 JN |
24 | #include <drm/drm_atomic_helper.h> |
25 | ||
379bc100 JN |
26 | #include "display/intel_dp.h" |
27 | ||
55367a27 | 28 | #include "i915_drv.h" |
3558cafc | 29 | #include "intel_atomic.h" |
1d455f8d | 30 | #include "intel_display_types.h" |
55367a27 | 31 | #include "intel_psr.h" |
f9a79f9a | 32 | #include "intel_sprite.h" |
55367a27 | 33 | |
b2b89f55 RV |
34 | /** |
35 | * DOC: Panel Self Refresh (PSR/SRD) | |
36 | * | |
37 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
38 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
39 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
40 | * when system is idle but display is on as it eliminates display refresh | |
41 | * request to DDR memory completely as long as the frame buffer for that | |
42 | * display is unchanged. | |
43 | * | |
44 | * Panel Self Refresh must be supported by both Hardware (source) and | |
45 | * Panel (sink). | |
46 | * | |
47 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
48 | * to power down the link and memory controller. For DSI panels the same idea | |
49 | * is called "manual mode". | |
50 | * | |
51 | * The implementation uses the hardware-based PSR support which automatically | |
52 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
53 | * required DP aux message and could even retrain the link (that part isn't | |
54 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
55 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
56 | * part doesn't work too well, hence why the i915 PSR support uses the | |
57 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
58 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
59 | * get called by the frontbuffer tracking code. Note that because of locking | |
60 | * issues the self-refresh re-enable code is done from a work queue, which | |
61 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
62 | */ | |
63 | ||
c44301fc ML |
64 | static bool psr_global_enabled(u32 debug) |
65 | { | |
66 | switch (debug & I915_PSR_DEBUG_MODE_MASK) { | |
67 | case I915_PSR_DEBUG_DEFAULT: | |
68 | return i915_modparams.enable_psr; | |
69 | case I915_PSR_DEBUG_DISABLE: | |
70 | return false; | |
71 | default: | |
72 | return true; | |
73 | } | |
74 | } | |
75 | ||
2ac45bdd ML |
76 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
77 | const struct intel_crtc_state *crtc_state) | |
78 | { | |
8228c42f | 79 | /* Cannot enable DSC and PSR2 simultaneously */ |
010663a6 | 80 | WARN_ON(crtc_state->dsc.compression_enable && |
8228c42f MN |
81 | crtc_state->has_psr2); |
82 | ||
2ac45bdd | 83 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
235ca26f | 84 | case I915_PSR_DEBUG_DISABLE: |
2ac45bdd ML |
85 | case I915_PSR_DEBUG_FORCE_PSR1: |
86 | return false; | |
87 | default: | |
88 | return crtc_state->has_psr2; | |
89 | } | |
90 | } | |
91 | ||
2f3b8712 | 92 | static void psr_irq_control(struct drm_i915_private *dev_priv) |
c0871805 | 93 | { |
8241cfbe JRS |
94 | enum transcoder trans_shift; |
95 | u32 mask, val; | |
96 | i915_reg_t imr_reg; | |
2f3b8712 | 97 | |
8241cfbe JRS |
98 | /* |
99 | * gen12+ has registers relative to transcoder and one per transcoder | |
100 | * using the same bit definition: handle it as TRANSCODER_EDP to force | |
101 | * 0 shift in bit definition | |
102 | */ | |
103 | if (INTEL_GEN(dev_priv) >= 12) { | |
104 | trans_shift = 0; | |
105 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
106 | } else { | |
107 | trans_shift = dev_priv->psr.transcoder; | |
108 | imr_reg = EDP_PSR_IMR; | |
109 | } | |
110 | ||
111 | mask = EDP_PSR_ERROR(trans_shift); | |
2f3b8712 | 112 | if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) |
8241cfbe JRS |
113 | mask |= EDP_PSR_POST_EXIT(trans_shift) | |
114 | EDP_PSR_PRE_ENTRY(trans_shift); | |
2f3b8712 JRS |
115 | |
116 | /* Warning: it is masking/setting reserved bits too */ | |
8241cfbe JRS |
117 | val = I915_READ(imr_reg); |
118 | val &= ~EDP_PSR_TRANS_MASK(trans_shift); | |
2f3b8712 | 119 | val |= ~mask; |
8241cfbe | 120 | I915_WRITE(imr_reg, val); |
54fd3149 DP |
121 | } |
122 | ||
bc18b4df JRS |
123 | static void psr_event_print(u32 val, bool psr2_enabled) |
124 | { | |
125 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
126 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
127 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
128 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
129 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
130 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
131 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
132 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
133 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
134 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
135 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
136 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
137 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
138 | if (val & PSR_EVENT_MEMORY_UP) | |
139 | DRM_DEBUG_KMS("\tMemory up\n"); | |
140 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
141 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
142 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
143 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
144 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
145 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
146 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
147 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
148 | if (val & PSR_EVENT_HDCP_ENABLE) | |
149 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
150 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
151 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
152 | if (val & PSR_EVENT_VBI_ENABLE) | |
153 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
154 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
155 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
156 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
157 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
158 | } | |
159 | ||
54fd3149 DP |
160 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
161 | { | |
2f3b8712 | 162 | enum transcoder cpu_transcoder = dev_priv->psr.transcoder; |
8241cfbe JRS |
163 | enum transcoder trans_shift; |
164 | i915_reg_t imr_reg; | |
3f983e54 | 165 | ktime_t time_ns = ktime_get(); |
c0871805 | 166 | |
8241cfbe JRS |
167 | if (INTEL_GEN(dev_priv) >= 12) { |
168 | trans_shift = 0; | |
169 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
170 | } else { | |
171 | trans_shift = dev_priv->psr.transcoder; | |
172 | imr_reg = EDP_PSR_IMR; | |
173 | } | |
174 | ||
175 | if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { | |
2f3b8712 JRS |
176 | dev_priv->psr.last_entry_attempt = time_ns; |
177 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", | |
178 | transcoder_name(cpu_transcoder)); | |
179 | } | |
183b8e67 | 180 | |
8241cfbe | 181 | if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { |
2f3b8712 JRS |
182 | dev_priv->psr.last_exit = time_ns; |
183 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", | |
184 | transcoder_name(cpu_transcoder)); | |
183b8e67 | 185 | |
2f3b8712 JRS |
186 | if (INTEL_GEN(dev_priv) >= 9) { |
187 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
188 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
54fd3149 | 189 | |
2f3b8712 JRS |
190 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); |
191 | psr_event_print(val, psr2_enabled); | |
3f983e54 | 192 | } |
2f3b8712 | 193 | } |
54fd3149 | 194 | |
8241cfbe | 195 | if (psr_iir & EDP_PSR_ERROR(trans_shift)) { |
2f3b8712 | 196 | u32 val; |
bc18b4df | 197 | |
2f3b8712 JRS |
198 | DRM_WARN("[transcoder %s] PSR aux error\n", |
199 | transcoder_name(cpu_transcoder)); | |
bc18b4df | 200 | |
2f3b8712 | 201 | dev_priv->psr.irq_aux_error = true; |
183b8e67 | 202 | |
2f3b8712 JRS |
203 | /* |
204 | * If this interruption is not masked it will keep | |
205 | * interrupting so fast that it prevents the scheduled | |
206 | * work to run. | |
207 | * Also after a PSR error, we don't want to arm PSR | |
208 | * again so we don't care about unmask the interruption | |
209 | * or unset irq_aux_error. | |
210 | */ | |
8241cfbe JRS |
211 | val = I915_READ(imr_reg); |
212 | val |= EDP_PSR_ERROR(trans_shift); | |
213 | I915_WRITE(imr_reg, val); | |
183b8e67 JRS |
214 | |
215 | schedule_work(&dev_priv->psr.work); | |
216 | } | |
54fd3149 DP |
217 | } |
218 | ||
77fe36ff DP |
219 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
220 | { | |
739f3abd | 221 | u8 alpm_caps = 0; |
77fe36ff DP |
222 | |
223 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
224 | &alpm_caps) != 1) | |
225 | return false; | |
226 | return alpm_caps & DP_ALPM_CAP; | |
227 | } | |
228 | ||
26e5378d JRS |
229 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
230 | { | |
264ff016 | 231 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
232 | |
233 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
234 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
235 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
236 | else | |
264ff016 | 237 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
238 | return val; |
239 | } | |
240 | ||
8c0d2c29 JRS |
241 | static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) |
242 | { | |
243 | u16 val; | |
244 | ssize_t r; | |
245 | ||
246 | /* | |
247 | * Returning the default X granularity if granularity not required or | |
248 | * if DPCD read fails | |
249 | */ | |
250 | if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) | |
251 | return 4; | |
252 | ||
253 | r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); | |
254 | if (r != 2) | |
255 | DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n"); | |
256 | ||
257 | /* | |
258 | * Spec says that if the value read is 0 the default granularity should | |
259 | * be used instead. | |
260 | */ | |
261 | if (r != 2 || val == 0) | |
262 | val = 4; | |
263 | ||
264 | return val; | |
265 | } | |
266 | ||
77fe36ff DP |
267 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
268 | { | |
269 | struct drm_i915_private *dev_priv = | |
270 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
271 | ||
6056517a JRS |
272 | if (dev_priv->psr.dp) { |
273 | DRM_WARN("More than one eDP panel found, PSR support should be extended\n"); | |
274 | return; | |
275 | } | |
276 | ||
77fe36ff DP |
277 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, |
278 | sizeof(intel_dp->psr_dpcd)); | |
279 | ||
8cf6da7e DP |
280 | if (!intel_dp->psr_dpcd[0]) |
281 | return; | |
8cf6da7e DP |
282 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
283 | intel_dp->psr_dpcd[0]); | |
84bb2916 | 284 | |
7c5c641a JRS |
285 | if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { |
286 | DRM_DEBUG_KMS("PSR support not currently available for this panel\n"); | |
287 | return; | |
288 | } | |
289 | ||
84bb2916 DP |
290 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
291 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
292 | return; | |
293 | } | |
7c5c641a | 294 | |
8cf6da7e | 295 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
296 | dev_priv->psr.sink_sync_latency = |
297 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 298 | |
c44301fc ML |
299 | dev_priv->psr.dp = intel_dp; |
300 | ||
77fe36ff | 301 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 302 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
303 | bool y_req = intel_dp->psr_dpcd[1] & |
304 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
305 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
306 | ||
aee3bac0 JRS |
307 | /* |
308 | * All panels that supports PSR version 03h (PSR2 + | |
309 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
310 | * only sure that it is going to be used when required by the | |
311 | * panel. This way panel is capable to do selective update | |
312 | * without a aux frame sync. | |
313 | * | |
314 | * To support PSR version 02h and PSR version 03h without | |
315 | * Y-coordinate requirement panels we would need to enable | |
316 | * GTC first. | |
317 | */ | |
97c9de66 | 318 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
319 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
320 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 321 | |
95f28d2e | 322 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
323 | dev_priv->psr.colorimetry_support = |
324 | intel_dp_get_colorimetry_status(intel_dp); | |
8c0d2c29 JRS |
325 | dev_priv->psr.su_x_granularity = |
326 | intel_dp_get_su_x_granulartiy(intel_dp); | |
77fe36ff DP |
327 | } |
328 | } | |
329 | } | |
330 | ||
cf5d862d RV |
331 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
332 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 333 | { |
97da2ef4 | 334 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 335 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d432f95 | 336 | struct dp_sdp psr_vsc; |
474d1ec4 | 337 | |
95f28d2e | 338 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
339 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
340 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
341 | psr_vsc.sdp_header.HB0 = 0; | |
342 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 343 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
344 | psr_vsc.sdp_header.HB2 = 0x5; |
345 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 346 | } else { |
2ce4df87 RV |
347 | psr_vsc.sdp_header.HB2 = 0x4; |
348 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 349 | } |
97da2ef4 | 350 | } else { |
2ce4df87 RV |
351 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
352 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
353 | psr_vsc.sdp_header.HB0 = 0; | |
354 | psr_vsc.sdp_header.HB1 = 0x7; | |
355 | psr_vsc.sdp_header.HB2 = 0x2; | |
356 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
357 | } |
358 | ||
790ea70c VS |
359 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
360 | crtc_state, | |
1d776538 | 361 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
362 | } |
363 | ||
b90eed08 | 364 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 365 | { |
1895759e | 366 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
367 | u32 aux_clock_divider, aux_ctl; |
368 | int i; | |
739f3abd | 369 | static const u8 aux_msg[] = { |
0bc12bcb RV |
370 | [0] = DP_AUX_NATIVE_WRITE << 4, |
371 | [1] = DP_SET_POWER >> 8, | |
372 | [2] = DP_SET_POWER & 0xff, | |
373 | [3] = 1 - 1, | |
374 | [4] = DP_SET_POWER_D0, | |
375 | }; | |
d544e918 DP |
376 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
377 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
378 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
379 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
380 | |
381 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 382 | for (i = 0; i < sizeof(aux_msg); i += 4) |
4ab4fa10 | 383 | I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), |
b90eed08 DP |
384 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
385 | ||
d544e918 DP |
386 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
387 | ||
388 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 389 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 390 | aux_clock_divider); |
d544e918 DP |
391 | |
392 | /* Select only valid bits for SRD_AUX_CTL */ | |
393 | aux_ctl &= psr_aux_mask; | |
4ab4fa10 | 394 | I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl); |
b90eed08 DP |
395 | } |
396 | ||
cf5d862d | 397 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 398 | { |
1895759e | 399 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 400 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 401 | |
340c93c0 | 402 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
403 | if (dev_priv->psr.psr2_enabled) { |
404 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
405 | DP_ALPM_ENABLE); | |
98751b8c | 406 | dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; |
60cae442 JRS |
407 | } else { |
408 | if (dev_priv->psr.link_standby) | |
409 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; | |
de570946 JRS |
410 | |
411 | if (INTEL_GEN(dev_priv) >= 8) | |
412 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
97c9de66 DP |
413 | } |
414 | ||
4df4925b | 415 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 416 | |
d544e918 | 417 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
418 | } |
419 | ||
1e0c05c0 | 420 | static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) |
0bc12bcb | 421 | { |
1895759e | 422 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1e0c05c0 | 423 | u32 val = 0; |
60e5ffe3 | 424 | |
8a9a5608 JRS |
425 | if (INTEL_GEN(dev_priv) >= 11) |
426 | val |= EDP_PSR_TP4_TIME_0US; | |
427 | ||
77312ae8 | 428 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
1e0c05c0 | 429 | val |= EDP_PSR_TP1_TIME_0us; |
77312ae8 | 430 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) |
50db1390 | 431 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
432 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
433 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 434 | else |
77312ae8 | 435 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 436 | |
77312ae8 | 437 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
1e0c05c0 | 438 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
77312ae8 | 439 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) |
50db1390 | 440 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
441 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
442 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 443 | else |
77312ae8 | 444 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
445 | |
446 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
447 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
448 | val |= EDP_PSR_TP1_TP3_SEL; | |
449 | else | |
450 | val |= EDP_PSR_TP1_TP2_SEL; | |
451 | ||
1e0c05c0 JRS |
452 | return val; |
453 | } | |
454 | ||
455 | static void hsw_activate_psr1(struct intel_dp *intel_dp) | |
456 | { | |
457 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
458 | u32 max_sleep_time = 0x1f; | |
459 | u32 val = EDP_PSR_ENABLE; | |
460 | ||
461 | /* Let's use 6 as the minimum to cover all known cases including the | |
462 | * off-by-one issue that HW has in some cases. | |
463 | */ | |
464 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
465 | ||
466 | /* sink_sync_latency of 8 means source has to wait for more than 8 | |
467 | * frames, we'll go with 9 frames for now | |
468 | */ | |
469 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
470 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
471 | ||
472 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
473 | if (IS_HASWELL(dev_priv)) | |
474 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
475 | ||
476 | if (dev_priv->psr.link_standby) | |
477 | val |= EDP_PSR_LINK_STANDBY; | |
478 | ||
479 | val |= intel_psr1_get_tp_time(intel_dp); | |
480 | ||
00c8f194 JRS |
481 | if (INTEL_GEN(dev_priv) >= 8) |
482 | val |= EDP_PSR_CRC_ENABLE; | |
483 | ||
4ab4fa10 JRS |
484 | val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & |
485 | EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); | |
486 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
3fcb0ca1 | 487 | } |
50db1390 | 488 | |
ed63d24b | 489 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 490 | { |
1895759e | 491 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
492 | u32 val; |
493 | ||
494 | /* Let's use 6 as the minimum to cover all known cases including the | |
495 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 496 | */ |
a3db1428 DP |
497 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
498 | ||
499 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
500 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 | 501 | |
5e87325f | 502 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
503 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
504 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 505 | |
26e5378d | 506 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 507 | |
88a0d960 JRS |
508 | if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && |
509 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) | |
77312ae8 | 510 | val |= EDP_PSR2_TP2_TIME_50us; |
88a0d960 | 511 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) |
77312ae8 | 512 | val |= EDP_PSR2_TP2_TIME_100us; |
88a0d960 | 513 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) |
77312ae8 | 514 | val |= EDP_PSR2_TP2_TIME_500us; |
50db1390 | 515 | else |
77312ae8 | 516 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 517 | |
06dd94cc | 518 | /* |
15b7dae0 JRS |
519 | * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is |
520 | * recommending keep this bit unset while PSR2 is enabled. | |
06dd94cc | 521 | */ |
4ab4fa10 | 522 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0); |
06dd94cc | 523 | |
4ab4fa10 | 524 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); |
0bc12bcb RV |
525 | } |
526 | ||
99fc38b1 JRS |
527 | static bool |
528 | transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) | |
529 | { | |
0f81e645 JRS |
530 | if (INTEL_GEN(dev_priv) < 9) |
531 | return false; | |
532 | else if (INTEL_GEN(dev_priv) >= 12) | |
99fc38b1 JRS |
533 | return trans == TRANSCODER_A; |
534 | else | |
535 | return trans == TRANSCODER_EDP; | |
536 | } | |
537 | ||
1c4d821d AG |
538 | static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) |
539 | { | |
540 | if (!cstate || !cstate->base.active) | |
541 | return 0; | |
542 | ||
543 | return DIV_ROUND_UP(1000 * 1000, | |
544 | drm_mode_vrefresh(&cstate->base.adjusted_mode)); | |
545 | } | |
546 | ||
547 | static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, | |
548 | u32 idle_frames) | |
549 | { | |
550 | u32 val; | |
551 | ||
552 | idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; | |
553 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); | |
554 | val &= ~EDP_PSR2_IDLE_FRAME_MASK; | |
555 | val |= idle_frames; | |
556 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
557 | } | |
558 | ||
559 | static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) | |
560 | { | |
561 | psr2_program_idle_frames(dev_priv, 0); | |
562 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); | |
563 | } | |
564 | ||
565 | static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) | |
566 | { | |
567 | int idle_frames; | |
568 | ||
569 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); | |
570 | /* | |
571 | * Restore PSR2 idle frame let's use 6 as the minimum to cover all known | |
572 | * cases including the off-by-one issue that HW has in some cases. | |
573 | */ | |
574 | idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
575 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
576 | psr2_program_idle_frames(dev_priv, idle_frames); | |
577 | } | |
578 | ||
579 | static void tgl_dc5_idle_thread(struct work_struct *work) | |
580 | { | |
581 | struct drm_i915_private *dev_priv = | |
582 | container_of(work, typeof(*dev_priv), psr.idle_work.work); | |
583 | ||
584 | mutex_lock(&dev_priv->psr.lock); | |
585 | /* If delayed work is pending, it is not idle */ | |
586 | if (delayed_work_pending(&dev_priv->psr.idle_work)) | |
587 | goto unlock; | |
588 | ||
589 | DRM_DEBUG_KMS("DC5/6 idle thread\n"); | |
590 | tgl_psr2_disable_dc3co(dev_priv); | |
591 | unlock: | |
592 | mutex_unlock(&dev_priv->psr.lock); | |
593 | } | |
594 | ||
595 | static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) | |
596 | { | |
597 | if (!dev_priv->psr.dc3co_enabled) | |
598 | return; | |
599 | ||
600 | cancel_delayed_work(&dev_priv->psr.idle_work); | |
601 | /* Before PSR2 exit disallow dc3co*/ | |
602 | tgl_psr2_disable_dc3co(dev_priv); | |
603 | } | |
604 | ||
c4932d79 RV |
605 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
606 | struct intel_crtc_state *crtc_state) | |
607 | { | |
1895759e | 608 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c90c275c DP |
609 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
610 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
611 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 | 612 | |
95f28d2e | 613 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
614 | return false; |
615 | ||
99fc38b1 JRS |
616 | if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { |
617 | DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n", | |
618 | transcoder_name(crtc_state->cpu_transcoder)); | |
619 | return false; | |
620 | } | |
621 | ||
8228c42f MN |
622 | /* |
623 | * DSC and PSR2 cannot be enabled simultaneously. If a requested | |
624 | * resolution requires DSC to be enabled, priority is given to DSC | |
625 | * over PSR2. | |
626 | */ | |
010663a6 | 627 | if (crtc_state->dsc.compression_enable) { |
8228c42f MN |
628 | DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); |
629 | return false; | |
630 | } | |
631 | ||
f7b3c226 JRS |
632 | if (INTEL_GEN(dev_priv) >= 12) { |
633 | psr_max_h = 5120; | |
634 | psr_max_v = 3200; | |
635 | } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { | |
c90c275c DP |
636 | psr_max_h = 4096; |
637 | psr_max_v = 2304; | |
cf819eff | 638 | } else if (IS_GEN(dev_priv, 9)) { |
c90c275c DP |
639 | psr_max_h = 3640; |
640 | psr_max_v = 2304; | |
641 | } | |
642 | ||
643 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
644 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
645 | crtc_hdisplay, crtc_vdisplay, | |
646 | psr_max_h, psr_max_v); | |
c4932d79 RV |
647 | return false; |
648 | } | |
649 | ||
bef5e5b3 JRS |
650 | /* |
651 | * HW sends SU blocks of size four scan lines, which means the starting | |
652 | * X coordinate and Y granularity requirements will always be met. We | |
8c0d2c29 JRS |
653 | * only need to validate the SU block width is a multiple of |
654 | * x granularity. | |
bef5e5b3 | 655 | */ |
8c0d2c29 JRS |
656 | if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { |
657 | DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", | |
658 | crtc_hdisplay, dev_priv->psr.su_x_granularity); | |
bef5e5b3 JRS |
659 | return false; |
660 | } | |
661 | ||
618cf883 JRS |
662 | if (crtc_state->crc_enabled) { |
663 | DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n"); | |
664 | return false; | |
665 | } | |
666 | ||
c4932d79 RV |
667 | return true; |
668 | } | |
669 | ||
4d90f2d5 VS |
670 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
671 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
672 | { |
673 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 674 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 675 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 676 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 677 | int psr_setup_time; |
0bc12bcb | 678 | |
4371d896 | 679 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
680 | return; |
681 | ||
c44301fc | 682 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 683 | return; |
0bc12bcb | 684 | |
dc9b5a0c RV |
685 | /* |
686 | * HSW spec explicitly says PSR is tied to port A. | |
4ab4fa10 JRS |
687 | * BDW+ platforms have a instance of PSR registers per transcoder but |
688 | * for now it only supports one instance of PSR, so lets keep it | |
689 | * hardcoded to PORT_A | |
dc9b5a0c | 690 | */ |
ce3508fd | 691 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 692 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 693 | return; |
0bc12bcb RV |
694 | } |
695 | ||
50a12d8f JRS |
696 | if (dev_priv->psr.sink_not_reliable) { |
697 | DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); | |
698 | return; | |
699 | } | |
700 | ||
7ae6ad6f JRS |
701 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
702 | DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n"); | |
4d90f2d5 | 703 | return; |
0bc12bcb RV |
704 | } |
705 | ||
dfd2e9ab VS |
706 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
707 | if (psr_setup_time < 0) { | |
708 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
709 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 710 | return; |
dfd2e9ab VS |
711 | } |
712 | ||
713 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
714 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
715 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
716 | psr_setup_time); | |
4d90f2d5 VS |
717 | return; |
718 | } | |
719 | ||
4d90f2d5 | 720 | crtc_state->has_psr = true; |
c4932d79 | 721 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
722 | } |
723 | ||
e2bbc343 | 724 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 725 | { |
1895759e | 726 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 727 | |
0f81e645 | 728 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) |
4ab4fa10 | 729 | WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); |
0f81e645 | 730 | |
4ab4fa10 | 731 | WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); |
0bc12bcb RV |
732 | WARN_ON(dev_priv->psr.active); |
733 | lockdep_assert_held(&dev_priv->psr.lock); | |
734 | ||
cf5d862d RV |
735 | /* psr1 and psr2 are mutually exclusive.*/ |
736 | if (dev_priv->psr.psr2_enabled) | |
737 | hsw_activate_psr2(intel_dp); | |
738 | else | |
739 | hsw_activate_psr1(intel_dp); | |
740 | ||
0bc12bcb RV |
741 | dev_priv->psr.active = true; |
742 | } | |
743 | ||
cf5d862d RV |
744 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
745 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 746 | { |
1895759e | 747 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 748 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 749 | u32 mask; |
4d1fa22f | 750 | |
d544e918 DP |
751 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
752 | * use hardcoded values PSR AUX transactions | |
753 | */ | |
754 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
755 | hsw_psr_setup_aux(intel_dp); | |
756 | ||
cf819eff | 757 | if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && |
d15f9cdd | 758 | !IS_GEMINILAKE(dev_priv))) { |
12c4d4c1 | 759 | i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); |
8f19b401 | 760 | u32 chicken = I915_READ(reg); |
5e87325f | 761 | |
d15f9cdd JRS |
762 | chicken |= PSR2_VSC_ENABLE_PROG_HEADER | |
763 | PSR2_ADD_VERTICAL_LINE_COUNT; | |
8f19b401 | 764 | I915_WRITE(reg, chicken); |
4d1fa22f | 765 | } |
bf80928f JRS |
766 | |
767 | /* | |
768 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
769 | * mask LPSP to avoid dependency on other drivers that might block | |
770 | * runtime_pm besides preventing other hw tracking issues now we | |
771 | * can rely on frontbuffer tracking. | |
772 | */ | |
fc6ff9dc JRS |
773 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
774 | EDP_PSR_DEBUG_MASK_HPD | | |
775 | EDP_PSR_DEBUG_MASK_LPSP | | |
776 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
777 | ||
778 | if (INTEL_GEN(dev_priv) < 11) | |
779 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
780 | ||
4ab4fa10 | 781 | I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); |
df7415bf | 782 | |
2f3b8712 | 783 | psr_irq_control(dev_priv); |
4d1fa22f RV |
784 | } |
785 | ||
c44301fc ML |
786 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
787 | const struct intel_crtc_state *crtc_state) | |
788 | { | |
789 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
4ab4fa10 | 790 | u32 val; |
c44301fc | 791 | |
23ec9f52 JRS |
792 | WARN_ON(dev_priv->psr.enabled); |
793 | ||
794 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
795 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
796 | dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; | |
1c4d821d AG |
797 | dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; |
798 | dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state); | |
4ab4fa10 JRS |
799 | dev_priv->psr.transcoder = crtc_state->cpu_transcoder; |
800 | ||
801 | /* | |
802 | * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR | |
803 | * will still keep the error set even after the reset done in the | |
804 | * irq_preinstall and irq_uninstall hooks. | |
805 | * And enabling in this situation cause the screen to freeze in the | |
806 | * first time that PSR HW tries to activate so lets keep PSR disabled | |
807 | * to avoid any rendering problems. | |
808 | */ | |
8241cfbe JRS |
809 | if (INTEL_GEN(dev_priv) >= 12) { |
810 | val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder)); | |
811 | val &= EDP_PSR_ERROR(0); | |
812 | } else { | |
813 | val = I915_READ(EDP_PSR_IIR); | |
814 | val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); | |
815 | } | |
4ab4fa10 JRS |
816 | if (val) { |
817 | dev_priv->psr.sink_not_reliable = true; | |
818 | DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n"); | |
819 | return; | |
820 | } | |
c44301fc ML |
821 | |
822 | DRM_DEBUG_KMS("Enabling PSR%s\n", | |
823 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
824 | intel_psr_setup_vsc(intel_dp, crtc_state); | |
825 | intel_psr_enable_sink(intel_dp); | |
826 | intel_psr_enable_source(intel_dp, crtc_state); | |
827 | dev_priv->psr.enabled = true; | |
828 | ||
829 | intel_psr_activate(intel_dp); | |
830 | } | |
831 | ||
b2b89f55 RV |
832 | /** |
833 | * intel_psr_enable - Enable PSR | |
834 | * @intel_dp: Intel DP | |
d2419ffc | 835 | * @crtc_state: new CRTC state |
b2b89f55 RV |
836 | * |
837 | * This function can only be called after the pipe is fully trained and enabled. | |
838 | */ | |
d2419ffc VS |
839 | void intel_psr_enable(struct intel_dp *intel_dp, |
840 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 841 | { |
1895759e | 842 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 843 | |
4d90f2d5 | 844 | if (!crtc_state->has_psr) |
0bc12bcb | 845 | return; |
0bc12bcb | 846 | |
c9ef291a DP |
847 | if (WARN_ON(!CAN_PSR(dev_priv))) |
848 | return; | |
849 | ||
da83ef85 | 850 | WARN_ON(dev_priv->drrs.dp); |
c44301fc | 851 | |
0bc12bcb | 852 | mutex_lock(&dev_priv->psr.lock); |
23ec9f52 JRS |
853 | |
854 | if (!psr_global_enabled(dev_priv->psr.debug)) { | |
855 | DRM_DEBUG_KMS("PSR disabled by flag\n"); | |
0bc12bcb RV |
856 | goto unlock; |
857 | } | |
858 | ||
23ec9f52 | 859 | intel_psr_enable_locked(dev_priv, crtc_state); |
d0ac896a | 860 | |
0bc12bcb RV |
861 | unlock: |
862 | mutex_unlock(&dev_priv->psr.lock); | |
863 | } | |
864 | ||
26f9ec9a JRS |
865 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
866 | { | |
867 | u32 val; | |
868 | ||
b2fc2252 | 869 | if (!dev_priv->psr.active) { |
0f81e645 | 870 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { |
4ab4fa10 JRS |
871 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
872 | WARN_ON(val & EDP_PSR2_ENABLE); | |
873 | } | |
874 | ||
875 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); | |
876 | WARN_ON(val & EDP_PSR_ENABLE); | |
877 | ||
26f9ec9a | 878 | return; |
b2fc2252 | 879 | } |
26f9ec9a JRS |
880 | |
881 | if (dev_priv->psr.psr2_enabled) { | |
1c4d821d | 882 | tgl_disallow_dc3co_on_psr2_exit(dev_priv); |
4ab4fa10 | 883 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 884 | WARN_ON(!(val & EDP_PSR2_ENABLE)); |
4ab4fa10 JRS |
885 | val &= ~EDP_PSR2_ENABLE; |
886 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a | 887 | } else { |
4ab4fa10 | 888 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 889 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
4ab4fa10 JRS |
890 | val &= ~EDP_PSR_ENABLE; |
891 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a JRS |
892 | } |
893 | dev_priv->psr.active = false; | |
894 | } | |
895 | ||
2ee936e3 | 896 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 897 | { |
1895759e | 898 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
899 | i915_reg_t psr_status; |
900 | u32 psr_status_mask; | |
0bc12bcb | 901 | |
2ee936e3 JRS |
902 | lockdep_assert_held(&dev_priv->psr.lock); |
903 | ||
904 | if (!dev_priv->psr.enabled) | |
905 | return; | |
906 | ||
907 | DRM_DEBUG_KMS("Disabling PSR%s\n", | |
908 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
909 | ||
b2fc2252 | 910 | intel_psr_exit(dev_priv); |
77affa31 | 911 | |
b2fc2252 | 912 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 913 | psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 914 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
0bc12bcb | 915 | } else { |
4ab4fa10 | 916 | psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 917 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 918 | } |
b2fc2252 JRS |
919 | |
920 | /* Wait till PSR is idle */ | |
4cb3b44d DCS |
921 | if (intel_de_wait_for_clear(dev_priv, psr_status, |
922 | psr_status_mask, 2000)) | |
b2fc2252 | 923 | DRM_ERROR("Timed out waiting PSR idle state\n"); |
cc3054ff JRS |
924 | |
925 | /* Disable PSR on Sink */ | |
926 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
927 | ||
c44301fc | 928 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
929 | } |
930 | ||
e2bbc343 RV |
931 | /** |
932 | * intel_psr_disable - Disable PSR | |
933 | * @intel_dp: Intel DP | |
d2419ffc | 934 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
935 | * |
936 | * This function needs to be called before disabling pipe. | |
937 | */ | |
d2419ffc VS |
938 | void intel_psr_disable(struct intel_dp *intel_dp, |
939 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 940 | { |
1895759e | 941 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 942 | |
4d90f2d5 | 943 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
944 | return; |
945 | ||
c9ef291a DP |
946 | if (WARN_ON(!CAN_PSR(dev_priv))) |
947 | return; | |
948 | ||
e2bbc343 | 949 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 950 | |
cc3054ff | 951 | intel_psr_disable_locked(intel_dp); |
c44301fc | 952 | |
0bc12bcb | 953 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 954 | cancel_work_sync(&dev_priv->psr.work); |
1c4d821d | 955 | cancel_delayed_work_sync(&dev_priv->psr.idle_work); |
0bc12bcb RV |
956 | } |
957 | ||
88e05aff JRS |
958 | static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) |
959 | { | |
381f8a20 JRS |
960 | if (INTEL_GEN(dev_priv) >= 9) |
961 | /* | |
962 | * Display WA #0884: skl+ | |
963 | * This documented WA for bxt can be safely applied | |
964 | * broadly so we can force HW tracking to exit PSR | |
965 | * instead of disabling and re-enabling. | |
966 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
967 | * but it makes more sense write to the current active | |
968 | * pipe. | |
969 | */ | |
970 | I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); | |
971 | else | |
972 | /* | |
973 | * A write to CURSURFLIVE do not cause HW tracking to exit PSR | |
974 | * on older gens so doing the manual exit instead. | |
975 | */ | |
976 | intel_psr_exit(dev_priv); | |
88e05aff JRS |
977 | } |
978 | ||
23ec9f52 JRS |
979 | /** |
980 | * intel_psr_update - Update PSR state | |
981 | * @intel_dp: Intel DP | |
982 | * @crtc_state: new CRTC state | |
983 | * | |
984 | * This functions will update PSR states, disabling, enabling or switching PSR | |
985 | * version when executing fastsets. For full modeset, intel_psr_disable() and | |
986 | * intel_psr_enable() should be called instead. | |
987 | */ | |
988 | void intel_psr_update(struct intel_dp *intel_dp, | |
989 | const struct intel_crtc_state *crtc_state) | |
990 | { | |
991 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
992 | struct i915_psr *psr = &dev_priv->psr; | |
993 | bool enable, psr2_enable; | |
994 | ||
995 | if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) | |
996 | return; | |
997 | ||
998 | mutex_lock(&dev_priv->psr.lock); | |
999 | ||
1000 | enable = crtc_state->has_psr && psr_global_enabled(psr->debug); | |
1001 | psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); | |
1002 | ||
88e05aff JRS |
1003 | if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { |
1004 | /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ | |
1005 | if (crtc_state->crc_enabled && psr->enabled) | |
1006 | psr_force_hw_tracking_exit(dev_priv); | |
381f8a20 JRS |
1007 | else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { |
1008 | /* | |
1009 | * Activate PSR again after a force exit when enabling | |
1010 | * CRC in older gens | |
1011 | */ | |
1012 | if (!dev_priv->psr.active && | |
1013 | !dev_priv->psr.busy_frontbuffer_bits) | |
1014 | schedule_work(&dev_priv->psr.work); | |
1015 | } | |
88e05aff | 1016 | |
23ec9f52 | 1017 | goto unlock; |
88e05aff | 1018 | } |
23ec9f52 | 1019 | |
9f952664 JRS |
1020 | if (psr->enabled) |
1021 | intel_psr_disable_locked(intel_dp); | |
23ec9f52 | 1022 | |
9f952664 JRS |
1023 | if (enable) |
1024 | intel_psr_enable_locked(dev_priv, crtc_state); | |
23ec9f52 JRS |
1025 | |
1026 | unlock: | |
1027 | mutex_unlock(&dev_priv->psr.lock); | |
1028 | } | |
1029 | ||
65df9c79 DP |
1030 | /** |
1031 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
1032 | * @new_crtc_state: new CRTC state | |
1033 | * @out_value: PSR status in case of failure | |
1034 | * | |
1035 | * This function is expected to be called from pipe_update_start() where it is | |
1036 | * not expected to race with PSR enable or disable. | |
1037 | * | |
1038 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
1039 | */ | |
63ec132d DP |
1040 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
1041 | u32 *out_value) | |
c43dbcbb | 1042 | { |
c3d43361 TV |
1043 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
1044 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
c43dbcbb | 1045 | |
c44301fc | 1046 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
1047 | return 0; |
1048 | ||
fd255f6e DP |
1049 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
1050 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
1051 | return 0; | |
c43dbcbb TV |
1052 | |
1053 | /* | |
65df9c79 DP |
1054 | * From bspec: Panel Self Refresh (BDW+) |
1055 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
1056 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
1057 | * defensive enough to cover everything. | |
c43dbcbb | 1058 | */ |
63ec132d | 1059 | |
4ab4fa10 JRS |
1060 | return __intel_wait_for_register(&dev_priv->uncore, |
1061 | EDP_PSR_STATUS(dev_priv->psr.transcoder), | |
fd255f6e | 1062 | EDP_PSR_STATUS_STATE_MASK, |
63ec132d DP |
1063 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
1064 | out_value); | |
c43dbcbb TV |
1065 | } |
1066 | ||
1067 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 1068 | { |
daeb725e CW |
1069 | i915_reg_t reg; |
1070 | u32 mask; | |
1071 | int err; | |
1072 | ||
c44301fc | 1073 | if (!dev_priv->psr.enabled) |
daeb725e | 1074 | return false; |
0bc12bcb | 1075 | |
ce3508fd | 1076 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 1077 | reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1078 | mask = EDP_PSR2_STATUS_STATE_MASK; |
995d3047 | 1079 | } else { |
4ab4fa10 | 1080 | reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1081 | mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 1082 | } |
daeb725e CW |
1083 | |
1084 | mutex_unlock(&dev_priv->psr.lock); | |
1085 | ||
4cb3b44d | 1086 | err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); |
daeb725e CW |
1087 | if (err) |
1088 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
1089 | ||
1090 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 1091 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
1092 | return err == 0 && dev_priv->psr.enabled; |
1093 | } | |
0bc12bcb | 1094 | |
23ec9f52 | 1095 | static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) |
2ac45bdd | 1096 | { |
23ec9f52 JRS |
1097 | struct drm_device *dev = &dev_priv->drm; |
1098 | struct drm_modeset_acquire_ctx ctx; | |
1099 | struct drm_atomic_state *state; | |
3558cafc | 1100 | struct intel_crtc *crtc; |
23ec9f52 | 1101 | int err; |
2ac45bdd | 1102 | |
23ec9f52 JRS |
1103 | state = drm_atomic_state_alloc(dev); |
1104 | if (!state) | |
1105 | return -ENOMEM; | |
2ac45bdd | 1106 | |
23ec9f52 JRS |
1107 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
1108 | state->acquire_ctx = &ctx; | |
1109 | ||
1110 | retry: | |
3558cafc ML |
1111 | for_each_intel_crtc(dev, crtc) { |
1112 | struct intel_crtc_state *crtc_state = | |
1113 | intel_atomic_get_crtc_state(state, crtc); | |
23ec9f52 | 1114 | |
23ec9f52 JRS |
1115 | if (IS_ERR(crtc_state)) { |
1116 | err = PTR_ERR(crtc_state); | |
1117 | goto error; | |
1118 | } | |
1119 | ||
3558cafc | 1120 | if (crtc_state->base.active && crtc_state->has_psr) { |
23ec9f52 | 1121 | /* Mark mode as changed to trigger a pipe->update() */ |
3558cafc | 1122 | crtc_state->base.mode_changed = true; |
23ec9f52 JRS |
1123 | break; |
1124 | } | |
1125 | } | |
1126 | ||
1127 | err = drm_atomic_commit(state); | |
2ac45bdd | 1128 | |
23ec9f52 JRS |
1129 | error: |
1130 | if (err == -EDEADLK) { | |
1131 | drm_atomic_state_clear(state); | |
1132 | err = drm_modeset_backoff(&ctx); | |
1133 | if (!err) | |
1134 | goto retry; | |
1135 | } | |
1136 | ||
1137 | drm_modeset_drop_locks(&ctx); | |
1138 | drm_modeset_acquire_fini(&ctx); | |
1139 | drm_atomic_state_put(state); | |
1140 | ||
1141 | return err; | |
2ac45bdd ML |
1142 | } |
1143 | ||
23ec9f52 | 1144 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) |
c44301fc | 1145 | { |
23ec9f52 JRS |
1146 | const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
1147 | u32 old_mode; | |
c44301fc | 1148 | int ret; |
c44301fc ML |
1149 | |
1150 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 1151 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
c44301fc ML |
1152 | DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
c44301fc ML |
1156 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); |
1157 | if (ret) | |
1158 | return ret; | |
1159 | ||
23ec9f52 | 1160 | old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; |
c44301fc | 1161 | dev_priv->psr.debug = val; |
2f3b8712 JRS |
1162 | |
1163 | /* | |
1164 | * Do it right away if it's already enabled, otherwise it will be done | |
1165 | * when enabling the source. | |
1166 | */ | |
1167 | if (dev_priv->psr.enabled) | |
1168 | psr_irq_control(dev_priv); | |
c44301fc | 1169 | |
c44301fc | 1170 | mutex_unlock(&dev_priv->psr.lock); |
23ec9f52 JRS |
1171 | |
1172 | if (old_mode != mode) | |
1173 | ret = intel_psr_fastset_force(dev_priv); | |
1174 | ||
c44301fc ML |
1175 | return ret; |
1176 | } | |
1177 | ||
183b8e67 JRS |
1178 | static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) |
1179 | { | |
1180 | struct i915_psr *psr = &dev_priv->psr; | |
1181 | ||
1182 | intel_psr_disable_locked(psr->dp); | |
1183 | psr->sink_not_reliable = true; | |
1184 | /* let's make sure that sink is awaken */ | |
1185 | drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); | |
1186 | } | |
1187 | ||
daeb725e CW |
1188 | static void intel_psr_work(struct work_struct *work) |
1189 | { | |
1190 | struct drm_i915_private *dev_priv = | |
5422b37c | 1191 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
1192 | |
1193 | mutex_lock(&dev_priv->psr.lock); | |
1194 | ||
5422b37c RV |
1195 | if (!dev_priv->psr.enabled) |
1196 | goto unlock; | |
1197 | ||
183b8e67 JRS |
1198 | if (READ_ONCE(dev_priv->psr.irq_aux_error)) |
1199 | intel_psr_handle_irq(dev_priv); | |
1200 | ||
daeb725e CW |
1201 | /* |
1202 | * We have to make sure PSR is ready for re-enable | |
1203 | * otherwise it keeps disabled until next full enable/disable cycle. | |
1204 | * PSR might take some time to get fully disabled | |
1205 | * and be ready for re-enable. | |
1206 | */ | |
c43dbcbb | 1207 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
1208 | goto unlock; |
1209 | ||
1210 | /* | |
1211 | * The delayed work can race with an invalidate hence we need to | |
1212 | * recheck. Since psr_flush first clears this and then reschedules we | |
1213 | * won't ever miss a flush when bailing out here. | |
1214 | */ | |
c12e0643 | 1215 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
1216 | goto unlock; |
1217 | ||
c44301fc | 1218 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
1219 | unlock: |
1220 | mutex_unlock(&dev_priv->psr.lock); | |
1221 | } | |
1222 | ||
b2b89f55 RV |
1223 | /** |
1224 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 1225 | * @dev_priv: i915 device |
b2b89f55 | 1226 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 1227 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
1228 | * |
1229 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1230 | * with the software frontbuffer tracking. This function gets called every | |
1231 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
1232 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
1233 | * | |
1234 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
1235 | */ | |
5748b6a1 | 1236 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 1237 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1238 | { |
4371d896 | 1239 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1240 | return; |
1241 | ||
ce3508fd | 1242 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1243 | return; |
1244 | ||
0bc12bcb RV |
1245 | mutex_lock(&dev_priv->psr.lock); |
1246 | if (!dev_priv->psr.enabled) { | |
1247 | mutex_unlock(&dev_priv->psr.lock); | |
1248 | return; | |
1249 | } | |
1250 | ||
f0ad62a6 | 1251 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb | 1252 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
1253 | |
1254 | if (frontbuffer_bits) | |
5748b6a1 | 1255 | intel_psr_exit(dev_priv); |
ec76d629 | 1256 | |
0bc12bcb RV |
1257 | mutex_unlock(&dev_priv->psr.lock); |
1258 | } | |
1259 | ||
1c4d821d AG |
1260 | /* |
1261 | * When we will be completely rely on PSR2 S/W tracking in future, | |
1262 | * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP | |
1263 | * event also therefore tgl_dc3co_flush() require to be changed | |
1264 | * accrodingly in future. | |
1265 | */ | |
1266 | static void | |
1267 | tgl_dc3co_flush(struct drm_i915_private *dev_priv, | |
1268 | unsigned int frontbuffer_bits, enum fb_op_origin origin) | |
1269 | { | |
1270 | u32 delay; | |
1271 | ||
1272 | mutex_lock(&dev_priv->psr.lock); | |
1273 | ||
1274 | if (!dev_priv->psr.dc3co_enabled) | |
1275 | goto unlock; | |
1276 | ||
1277 | if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) | |
1278 | goto unlock; | |
1279 | ||
1280 | /* | |
1281 | * At every frontbuffer flush flip event modified delay of delayed work, | |
1282 | * when delayed work schedules that means display has been idle. | |
1283 | */ | |
1284 | if (!(frontbuffer_bits & | |
1285 | INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) | |
1286 | goto unlock; | |
1287 | ||
1288 | tgl_psr2_enable_dc3co(dev_priv); | |
1289 | /* DC5/DC6 required idle frames = 6 */ | |
1290 | delay = 6 * dev_priv->psr.dc3co_exit_delay; | |
1291 | mod_delayed_work(system_wq, &dev_priv->psr.idle_work, | |
1292 | usecs_to_jiffies(delay)); | |
1293 | ||
1294 | unlock: | |
1295 | mutex_unlock(&dev_priv->psr.lock); | |
1296 | } | |
1297 | ||
b2b89f55 RV |
1298 | /** |
1299 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 1300 | * @dev_priv: i915 device |
b2b89f55 | 1301 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 1302 | * @origin: which operation caused the flush |
b2b89f55 RV |
1303 | * |
1304 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1305 | * with the software frontbuffer tracking. This function gets called every | |
1306 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
1307 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
1308 | * | |
1309 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
1310 | */ | |
5748b6a1 | 1311 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 1312 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1313 | { |
4371d896 | 1314 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1315 | return; |
1316 | ||
1c4d821d AG |
1317 | if (origin == ORIGIN_FLIP) { |
1318 | tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); | |
5baf63cc | 1319 | return; |
1c4d821d | 1320 | } |
5baf63cc | 1321 | |
0bc12bcb RV |
1322 | mutex_lock(&dev_priv->psr.lock); |
1323 | if (!dev_priv->psr.enabled) { | |
1324 | mutex_unlock(&dev_priv->psr.lock); | |
1325 | return; | |
1326 | } | |
1327 | ||
f0ad62a6 | 1328 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb RV |
1329 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1330 | ||
921ec285 | 1331 | /* By definition flush = invalidate + flush */ |
88e05aff JRS |
1332 | if (frontbuffer_bits) |
1333 | psr_force_hw_tracking_exit(dev_priv); | |
995d3047 | 1334 | |
0bc12bcb | 1335 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1336 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1337 | mutex_unlock(&dev_priv->psr.lock); |
1338 | } | |
1339 | ||
b2b89f55 RV |
1340 | /** |
1341 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1342 | * @dev_priv: i915 device private |
b2b89f55 RV |
1343 | * |
1344 | * This function is called only once at driver load to initialize basic | |
1345 | * PSR stuff. | |
1346 | */ | |
c39055b0 | 1347 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1348 | { |
0f328da6 RV |
1349 | if (!HAS_PSR(dev_priv)) |
1350 | return; | |
1351 | ||
c9ef291a DP |
1352 | if (!dev_priv->psr.sink_support) |
1353 | return; | |
1354 | ||
4ab4fa10 JRS |
1355 | if (IS_HASWELL(dev_priv)) |
1356 | /* | |
1357 | * HSW don't have PSR registers on the same space as transcoder | |
1358 | * so set this to a value that when subtract to the register | |
1359 | * in transcoder space results in the right offset for HSW | |
1360 | */ | |
1361 | dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; | |
1362 | ||
598c6cfe DP |
1363 | if (i915_modparams.enable_psr == -1) |
1364 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1365 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1366 | |
65f61b42 | 1367 | /* Set link_standby x link_off defaults */ |
8652744b | 1368 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1369 | /* HSW and BDW require workarounds that we don't implement. */ |
1370 | dev_priv->psr.link_standby = false; | |
99d7a741 JRS |
1371 | else if (INTEL_GEN(dev_priv) < 12) |
1372 | /* For new platforms up to TGL let's respect VBT back again */ | |
60e5ffe3 RV |
1373 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; |
1374 | ||
5422b37c | 1375 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
1c4d821d | 1376 | INIT_DELAYED_WORK(&dev_priv->psr.idle_work, tgl_dc5_idle_thread); |
0bc12bcb RV |
1377 | mutex_init(&dev_priv->psr.lock); |
1378 | } | |
cc3054ff JRS |
1379 | |
1380 | void intel_psr_short_pulse(struct intel_dp *intel_dp) | |
1381 | { | |
1895759e | 1382 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff JRS |
1383 | struct i915_psr *psr = &dev_priv->psr; |
1384 | u8 val; | |
93bf76ed | 1385 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1386 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1387 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1388 | |
1389 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1390 | return; | |
1391 | ||
1392 | mutex_lock(&psr->lock); | |
1393 | ||
c44301fc | 1394 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1395 | goto exit; |
1396 | ||
1397 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { | |
1398 | DRM_ERROR("PSR_STATUS dpcd read failed\n"); | |
1399 | goto exit; | |
1400 | } | |
1401 | ||
1402 | if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { | |
1403 | DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); | |
1404 | intel_psr_disable_locked(intel_dp); | |
50a12d8f | 1405 | psr->sink_not_reliable = true; |
cc3054ff JRS |
1406 | } |
1407 | ||
93bf76ed JRS |
1408 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { |
1409 | DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n"); | |
1410 | goto exit; | |
1411 | } | |
1412 | ||
1413 | if (val & DP_PSR_RFB_STORAGE_ERROR) | |
1414 | DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); | |
1415 | if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) | |
1416 | DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
00c8f194 | 1417 | if (val & DP_PSR_LINK_CRC_ERROR) |
5063f48b | 1418 | DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n"); |
93bf76ed JRS |
1419 | |
1420 | if (val & ~errors) | |
1421 | DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", | |
1422 | val & ~errors); | |
50a12d8f | 1423 | if (val & errors) { |
93bf76ed | 1424 | intel_psr_disable_locked(intel_dp); |
50a12d8f JRS |
1425 | psr->sink_not_reliable = true; |
1426 | } | |
93bf76ed JRS |
1427 | /* clear status register */ |
1428 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); | |
cc3054ff JRS |
1429 | exit: |
1430 | mutex_unlock(&psr->lock); | |
1431 | } | |
2f8e7ea9 JRS |
1432 | |
1433 | bool intel_psr_enabled(struct intel_dp *intel_dp) | |
1434 | { | |
1435 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1436 | bool ret; | |
1437 | ||
1438 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1439 | return false; | |
1440 | ||
1441 | mutex_lock(&dev_priv->psr.lock); | |
1442 | ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); | |
1443 | mutex_unlock(&dev_priv->psr.lock); | |
1444 | ||
1445 | return ret; | |
1446 | } |