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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
55367a27 JN |
24 | #include <drm/drm_atomic_helper.h> |
25 | ||
379bc100 JN |
26 | #include "display/intel_dp.h" |
27 | ||
55367a27 | 28 | #include "i915_drv.h" |
3558cafc | 29 | #include "intel_atomic.h" |
1d455f8d | 30 | #include "intel_display_types.h" |
55367a27 | 31 | #include "intel_psr.h" |
f9a79f9a | 32 | #include "intel_sprite.h" |
55367a27 | 33 | |
b2b89f55 RV |
34 | /** |
35 | * DOC: Panel Self Refresh (PSR/SRD) | |
36 | * | |
37 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
38 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
39 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
40 | * when system is idle but display is on as it eliminates display refresh | |
41 | * request to DDR memory completely as long as the frame buffer for that | |
42 | * display is unchanged. | |
43 | * | |
44 | * Panel Self Refresh must be supported by both Hardware (source) and | |
45 | * Panel (sink). | |
46 | * | |
47 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
48 | * to power down the link and memory controller. For DSI panels the same idea | |
49 | * is called "manual mode". | |
50 | * | |
51 | * The implementation uses the hardware-based PSR support which automatically | |
52 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
53 | * required DP aux message and could even retrain the link (that part isn't | |
54 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
55 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
56 | * part doesn't work too well, hence why the i915 PSR support uses the | |
57 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
58 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
59 | * get called by the frontbuffer tracking code. Note that because of locking | |
60 | * issues the self-refresh re-enable code is done from a work queue, which | |
61 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
ceaaf530 JRS |
62 | * |
63 | * DC3CO (DC3 clock off) | |
64 | * | |
65 | * On top of PSR2, GEN12 adds a intermediate power savings state that turns | |
66 | * clock off automatically during PSR2 idle state. | |
67 | * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep | |
68 | * entry/exit allows the HW to enter a low-power state even when page flipping | |
69 | * periodically (for instance a 30fps video playback scenario). | |
70 | * | |
71 | * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), | |
72 | * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 | |
73 | * frames, if no other flip occurs and the function above is executed, DC3CO is | |
74 | * disabled and PSR2 is configured to enter deep sleep, resetting again in case | |
75 | * of another flip. | |
76 | * Front buffer modifications do not trigger DC3CO activation on purpose as it | |
77 | * would bring a lot of complexity and most of the moderns systems will only | |
78 | * use page flips. | |
b2b89f55 RV |
79 | */ |
80 | ||
58d4ad50 | 81 | static bool psr_global_enabled(struct drm_i915_private *i915) |
c44301fc | 82 | { |
58d4ad50 | 83 | switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
c44301fc ML |
84 | case I915_PSR_DEBUG_DEFAULT: |
85 | return i915_modparams.enable_psr; | |
86 | case I915_PSR_DEBUG_DISABLE: | |
87 | return false; | |
88 | default: | |
89 | return true; | |
90 | } | |
91 | } | |
92 | ||
2ac45bdd ML |
93 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
94 | const struct intel_crtc_state *crtc_state) | |
95 | { | |
8228c42f | 96 | /* Cannot enable DSC and PSR2 simultaneously */ |
16c56083 PB |
97 | drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && |
98 | crtc_state->has_psr2); | |
8228c42f | 99 | |
2ac45bdd | 100 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
235ca26f | 101 | case I915_PSR_DEBUG_DISABLE: |
2ac45bdd ML |
102 | case I915_PSR_DEBUG_FORCE_PSR1: |
103 | return false; | |
104 | default: | |
105 | return crtc_state->has_psr2; | |
106 | } | |
107 | } | |
108 | ||
2f3b8712 | 109 | static void psr_irq_control(struct drm_i915_private *dev_priv) |
c0871805 | 110 | { |
8241cfbe JRS |
111 | enum transcoder trans_shift; |
112 | u32 mask, val; | |
113 | i915_reg_t imr_reg; | |
2f3b8712 | 114 | |
8241cfbe JRS |
115 | /* |
116 | * gen12+ has registers relative to transcoder and one per transcoder | |
117 | * using the same bit definition: handle it as TRANSCODER_EDP to force | |
118 | * 0 shift in bit definition | |
119 | */ | |
120 | if (INTEL_GEN(dev_priv) >= 12) { | |
121 | trans_shift = 0; | |
122 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
123 | } else { | |
124 | trans_shift = dev_priv->psr.transcoder; | |
125 | imr_reg = EDP_PSR_IMR; | |
126 | } | |
127 | ||
128 | mask = EDP_PSR_ERROR(trans_shift); | |
2f3b8712 | 129 | if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) |
8241cfbe JRS |
130 | mask |= EDP_PSR_POST_EXIT(trans_shift) | |
131 | EDP_PSR_PRE_ENTRY(trans_shift); | |
2f3b8712 JRS |
132 | |
133 | /* Warning: it is masking/setting reserved bits too */ | |
c51e7138 | 134 | val = intel_de_read(dev_priv, imr_reg); |
8241cfbe | 135 | val &= ~EDP_PSR_TRANS_MASK(trans_shift); |
2f3b8712 | 136 | val |= ~mask; |
c51e7138 | 137 | intel_de_write(dev_priv, imr_reg, val); |
54fd3149 DP |
138 | } |
139 | ||
85f691d3 JN |
140 | static void psr_event_print(struct drm_i915_private *i915, |
141 | u32 val, bool psr2_enabled) | |
bc18b4df | 142 | { |
85f691d3 | 143 | drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); |
bc18b4df | 144 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) |
85f691d3 | 145 | drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); |
bc18b4df | 146 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) |
85f691d3 | 147 | drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); |
bc18b4df | 148 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) |
85f691d3 | 149 | drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); |
bc18b4df | 150 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) |
85f691d3 | 151 | drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); |
bc18b4df | 152 | if (val & PSR_EVENT_GRAPHICS_RESET) |
85f691d3 | 153 | drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); |
bc18b4df | 154 | if (val & PSR_EVENT_PCH_INTERRUPT) |
85f691d3 | 155 | drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); |
bc18b4df | 156 | if (val & PSR_EVENT_MEMORY_UP) |
85f691d3 | 157 | drm_dbg_kms(&i915->drm, "\tMemory up\n"); |
bc18b4df | 158 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) |
85f691d3 | 159 | drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); |
bc18b4df | 160 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) |
85f691d3 | 161 | drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); |
bc18b4df | 162 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) |
85f691d3 | 163 | drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); |
bc18b4df | 164 | if (val & PSR_EVENT_REGISTER_UPDATE) |
85f691d3 | 165 | drm_dbg_kms(&i915->drm, "\tRegister updated\n"); |
bc18b4df | 166 | if (val & PSR_EVENT_HDCP_ENABLE) |
85f691d3 | 167 | drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); |
bc18b4df | 168 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) |
85f691d3 | 169 | drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); |
bc18b4df | 170 | if (val & PSR_EVENT_VBI_ENABLE) |
85f691d3 | 171 | drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); |
bc18b4df | 172 | if (val & PSR_EVENT_LPSP_MODE_EXIT) |
85f691d3 | 173 | drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); |
bc18b4df | 174 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) |
85f691d3 | 175 | drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); |
bc18b4df JRS |
176 | } |
177 | ||
54fd3149 DP |
178 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
179 | { | |
2f3b8712 | 180 | enum transcoder cpu_transcoder = dev_priv->psr.transcoder; |
8241cfbe JRS |
181 | enum transcoder trans_shift; |
182 | i915_reg_t imr_reg; | |
3f983e54 | 183 | ktime_t time_ns = ktime_get(); |
c0871805 | 184 | |
8241cfbe JRS |
185 | if (INTEL_GEN(dev_priv) >= 12) { |
186 | trans_shift = 0; | |
187 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
188 | } else { | |
189 | trans_shift = dev_priv->psr.transcoder; | |
190 | imr_reg = EDP_PSR_IMR; | |
191 | } | |
192 | ||
193 | if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { | |
2f3b8712 | 194 | dev_priv->psr.last_entry_attempt = time_ns; |
6471bd74 WK |
195 | drm_dbg_kms(&dev_priv->drm, |
196 | "[transcoder %s] PSR entry attempt in 2 vblanks\n", | |
197 | transcoder_name(cpu_transcoder)); | |
2f3b8712 | 198 | } |
183b8e67 | 199 | |
8241cfbe | 200 | if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { |
2f3b8712 | 201 | dev_priv->psr.last_exit = time_ns; |
6471bd74 WK |
202 | drm_dbg_kms(&dev_priv->drm, |
203 | "[transcoder %s] PSR exit completed\n", | |
204 | transcoder_name(cpu_transcoder)); | |
183b8e67 | 205 | |
2f3b8712 | 206 | if (INTEL_GEN(dev_priv) >= 9) { |
c51e7138 JN |
207 | u32 val = intel_de_read(dev_priv, |
208 | PSR_EVENT(cpu_transcoder)); | |
2f3b8712 | 209 | bool psr2_enabled = dev_priv->psr.psr2_enabled; |
54fd3149 | 210 | |
c51e7138 JN |
211 | intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), |
212 | val); | |
85f691d3 | 213 | psr_event_print(dev_priv, val, psr2_enabled); |
3f983e54 | 214 | } |
2f3b8712 | 215 | } |
54fd3149 | 216 | |
8241cfbe | 217 | if (psr_iir & EDP_PSR_ERROR(trans_shift)) { |
2f3b8712 | 218 | u32 val; |
bc18b4df | 219 | |
6471bd74 | 220 | drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", |
2f3b8712 | 221 | transcoder_name(cpu_transcoder)); |
bc18b4df | 222 | |
2f3b8712 | 223 | dev_priv->psr.irq_aux_error = true; |
183b8e67 | 224 | |
2f3b8712 JRS |
225 | /* |
226 | * If this interruption is not masked it will keep | |
227 | * interrupting so fast that it prevents the scheduled | |
228 | * work to run. | |
229 | * Also after a PSR error, we don't want to arm PSR | |
230 | * again so we don't care about unmask the interruption | |
231 | * or unset irq_aux_error. | |
232 | */ | |
c51e7138 | 233 | val = intel_de_read(dev_priv, imr_reg); |
8241cfbe | 234 | val |= EDP_PSR_ERROR(trans_shift); |
c51e7138 | 235 | intel_de_write(dev_priv, imr_reg, val); |
183b8e67 JRS |
236 | |
237 | schedule_work(&dev_priv->psr.work); | |
238 | } | |
54fd3149 DP |
239 | } |
240 | ||
77fe36ff DP |
241 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
242 | { | |
739f3abd | 243 | u8 alpm_caps = 0; |
77fe36ff DP |
244 | |
245 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
246 | &alpm_caps) != 1) | |
247 | return false; | |
248 | return alpm_caps & DP_ALPM_CAP; | |
249 | } | |
250 | ||
26e5378d JRS |
251 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
252 | { | |
85f691d3 | 253 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
264ff016 | 254 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
255 | |
256 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
257 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
258 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
259 | else | |
85f691d3 JN |
260 | drm_dbg_kms(&i915->drm, |
261 | "Unable to get sink synchronization latency, assuming 8 frames\n"); | |
26e5378d JRS |
262 | return val; |
263 | } | |
264 | ||
8c0d2c29 JRS |
265 | static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) |
266 | { | |
85f691d3 | 267 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8c0d2c29 JRS |
268 | u16 val; |
269 | ssize_t r; | |
270 | ||
271 | /* | |
272 | * Returning the default X granularity if granularity not required or | |
273 | * if DPCD read fails | |
274 | */ | |
275 | if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) | |
276 | return 4; | |
277 | ||
278 | r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); | |
279 | if (r != 2) | |
85f691d3 JN |
280 | drm_dbg_kms(&i915->drm, |
281 | "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); | |
8c0d2c29 JRS |
282 | |
283 | /* | |
284 | * Spec says that if the value read is 0 the default granularity should | |
285 | * be used instead. | |
286 | */ | |
287 | if (r != 2 || val == 0) | |
288 | val = 4; | |
289 | ||
290 | return val; | |
291 | } | |
292 | ||
77fe36ff DP |
293 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
294 | { | |
295 | struct drm_i915_private *dev_priv = | |
296 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
297 | ||
6056517a | 298 | if (dev_priv->psr.dp) { |
6471bd74 WK |
299 | drm_warn(&dev_priv->drm, |
300 | "More than one eDP panel found, PSR support should be extended\n"); | |
6056517a JRS |
301 | return; |
302 | } | |
303 | ||
77fe36ff DP |
304 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, |
305 | sizeof(intel_dp->psr_dpcd)); | |
306 | ||
8cf6da7e DP |
307 | if (!intel_dp->psr_dpcd[0]) |
308 | return; | |
6471bd74 WK |
309 | drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", |
310 | intel_dp->psr_dpcd[0]); | |
84bb2916 | 311 | |
0883ce81 | 312 | if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) { |
6471bd74 WK |
313 | drm_dbg_kms(&dev_priv->drm, |
314 | "PSR support not currently available for this panel\n"); | |
7c5c641a JRS |
315 | return; |
316 | } | |
317 | ||
84bb2916 | 318 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
6471bd74 WK |
319 | drm_dbg_kms(&dev_priv->drm, |
320 | "Panel lacks power state control, PSR cannot be enabled\n"); | |
84bb2916 DP |
321 | return; |
322 | } | |
7c5c641a | 323 | |
8cf6da7e | 324 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
325 | dev_priv->psr.sink_sync_latency = |
326 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 327 | |
c44301fc ML |
328 | dev_priv->psr.dp = intel_dp; |
329 | ||
77fe36ff | 330 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 331 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
332 | bool y_req = intel_dp->psr_dpcd[1] & |
333 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
334 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
335 | ||
aee3bac0 JRS |
336 | /* |
337 | * All panels that supports PSR version 03h (PSR2 + | |
338 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
339 | * only sure that it is going to be used when required by the | |
340 | * panel. This way panel is capable to do selective update | |
341 | * without a aux frame sync. | |
342 | * | |
343 | * To support PSR version 02h and PSR version 03h without | |
344 | * Y-coordinate requirement panels we would need to enable | |
345 | * GTC first. | |
346 | */ | |
97c9de66 | 347 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
6471bd74 WK |
348 | drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", |
349 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 350 | |
95f28d2e | 351 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
352 | dev_priv->psr.colorimetry_support = |
353 | intel_dp_get_colorimetry_status(intel_dp); | |
8c0d2c29 JRS |
354 | dev_priv->psr.su_x_granularity = |
355 | intel_dp_get_su_x_granulartiy(intel_dp); | |
77fe36ff DP |
356 | } |
357 | } | |
358 | } | |
359 | ||
cf5d862d RV |
360 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
361 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 362 | { |
97da2ef4 | 363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 364 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d432f95 | 365 | struct dp_sdp psr_vsc; |
474d1ec4 | 366 | |
95f28d2e | 367 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
368 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
369 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
370 | psr_vsc.sdp_header.HB0 = 0; | |
371 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 372 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
373 | psr_vsc.sdp_header.HB2 = 0x5; |
374 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 375 | } else { |
2ce4df87 RV |
376 | psr_vsc.sdp_header.HB2 = 0x4; |
377 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 378 | } |
97da2ef4 | 379 | } else { |
2ce4df87 RV |
380 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
381 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
382 | psr_vsc.sdp_header.HB0 = 0; | |
383 | psr_vsc.sdp_header.HB1 = 0x7; | |
384 | psr_vsc.sdp_header.HB2 = 0x2; | |
385 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
386 | } |
387 | ||
790ea70c VS |
388 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
389 | crtc_state, | |
1d776538 | 390 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
391 | } |
392 | ||
b90eed08 | 393 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 394 | { |
1895759e | 395 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
396 | u32 aux_clock_divider, aux_ctl; |
397 | int i; | |
739f3abd | 398 | static const u8 aux_msg[] = { |
0bc12bcb RV |
399 | [0] = DP_AUX_NATIVE_WRITE << 4, |
400 | [1] = DP_SET_POWER >> 8, | |
401 | [2] = DP_SET_POWER & 0xff, | |
402 | [3] = 1 - 1, | |
403 | [4] = DP_SET_POWER_D0, | |
404 | }; | |
d544e918 DP |
405 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
406 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
407 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
408 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
409 | |
410 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 411 | for (i = 0; i < sizeof(aux_msg); i += 4) |
c51e7138 JN |
412 | intel_de_write(dev_priv, |
413 | EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), | |
414 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); | |
b90eed08 | 415 | |
d544e918 DP |
416 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
417 | ||
418 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 419 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 420 | aux_clock_divider); |
d544e918 DP |
421 | |
422 | /* Select only valid bits for SRD_AUX_CTL */ | |
423 | aux_ctl &= psr_aux_mask; | |
c51e7138 JN |
424 | intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), |
425 | aux_ctl); | |
b90eed08 DP |
426 | } |
427 | ||
cf5d862d | 428 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 429 | { |
1895759e | 430 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 431 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 432 | |
340c93c0 | 433 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
434 | if (dev_priv->psr.psr2_enabled) { |
435 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
700355af JRS |
436 | DP_ALPM_ENABLE | |
437 | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); | |
438 | ||
98751b8c | 439 | dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; |
60cae442 JRS |
440 | } else { |
441 | if (dev_priv->psr.link_standby) | |
442 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; | |
de570946 JRS |
443 | |
444 | if (INTEL_GEN(dev_priv) >= 8) | |
445 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
97c9de66 DP |
446 | } |
447 | ||
4df4925b | 448 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 449 | |
d544e918 | 450 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
451 | } |
452 | ||
1e0c05c0 | 453 | static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) |
0bc12bcb | 454 | { |
1895759e | 455 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1e0c05c0 | 456 | u32 val = 0; |
60e5ffe3 | 457 | |
8a9a5608 JRS |
458 | if (INTEL_GEN(dev_priv) >= 11) |
459 | val |= EDP_PSR_TP4_TIME_0US; | |
460 | ||
77312ae8 | 461 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
1e0c05c0 | 462 | val |= EDP_PSR_TP1_TIME_0us; |
77312ae8 | 463 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) |
50db1390 | 464 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
465 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
466 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 467 | else |
77312ae8 | 468 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 469 | |
77312ae8 | 470 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
1e0c05c0 | 471 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
77312ae8 | 472 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) |
50db1390 | 473 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
474 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
475 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 476 | else |
77312ae8 | 477 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
478 | |
479 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
480 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
481 | val |= EDP_PSR_TP1_TP3_SEL; | |
482 | else | |
483 | val |= EDP_PSR_TP1_TP2_SEL; | |
484 | ||
1e0c05c0 JRS |
485 | return val; |
486 | } | |
487 | ||
9e83713a | 488 | static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) |
1e0c05c0 JRS |
489 | { |
490 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
9e83713a | 491 | int idle_frames; |
1e0c05c0 JRS |
492 | |
493 | /* Let's use 6 as the minimum to cover all known cases including the | |
494 | * off-by-one issue that HW has in some cases. | |
495 | */ | |
9e83713a | 496 | idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
1e0c05c0 | 497 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); |
9e83713a | 498 | |
16c56083 | 499 | if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) |
9e83713a JRS |
500 | idle_frames = 0xf; |
501 | ||
502 | return idle_frames; | |
503 | } | |
504 | ||
505 | static void hsw_activate_psr1(struct intel_dp *intel_dp) | |
506 | { | |
507 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
508 | u32 max_sleep_time = 0x1f; | |
509 | u32 val = EDP_PSR_ENABLE; | |
510 | ||
511 | val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; | |
1e0c05c0 JRS |
512 | |
513 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
514 | if (IS_HASWELL(dev_priv)) | |
515 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
516 | ||
517 | if (dev_priv->psr.link_standby) | |
518 | val |= EDP_PSR_LINK_STANDBY; | |
519 | ||
520 | val |= intel_psr1_get_tp_time(intel_dp); | |
521 | ||
00c8f194 JRS |
522 | if (INTEL_GEN(dev_priv) >= 8) |
523 | val |= EDP_PSR_CRC_ENABLE; | |
524 | ||
c51e7138 | 525 | val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & |
4ab4fa10 | 526 | EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); |
c51e7138 | 527 | intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); |
3fcb0ca1 | 528 | } |
50db1390 | 529 | |
ed63d24b | 530 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 531 | { |
1895759e | 532 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
533 | u32 val; |
534 | ||
9e83713a | 535 | val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; |
50db1390 | 536 | |
5e87325f | 537 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
538 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
539 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 540 | |
26e5378d | 541 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 542 | |
88a0d960 JRS |
543 | if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && |
544 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) | |
77312ae8 | 545 | val |= EDP_PSR2_TP2_TIME_50us; |
88a0d960 | 546 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) |
77312ae8 | 547 | val |= EDP_PSR2_TP2_TIME_100us; |
88a0d960 | 548 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) |
77312ae8 | 549 | val |= EDP_PSR2_TP2_TIME_500us; |
50db1390 | 550 | else |
77312ae8 | 551 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 552 | |
06dd94cc | 553 | /* |
15b7dae0 JRS |
554 | * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is |
555 | * recommending keep this bit unset while PSR2 is enabled. | |
06dd94cc | 556 | */ |
c51e7138 | 557 | intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); |
06dd94cc | 558 | |
c51e7138 | 559 | intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); |
0bc12bcb RV |
560 | } |
561 | ||
99fc38b1 JRS |
562 | static bool |
563 | transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) | |
564 | { | |
0f81e645 JRS |
565 | if (INTEL_GEN(dev_priv) < 9) |
566 | return false; | |
567 | else if (INTEL_GEN(dev_priv) >= 12) | |
99fc38b1 JRS |
568 | return trans == TRANSCODER_A; |
569 | else | |
570 | return trans == TRANSCODER_EDP; | |
571 | } | |
572 | ||
1c4d821d AG |
573 | static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) |
574 | { | |
1326a92c | 575 | if (!cstate || !cstate->hw.active) |
1c4d821d AG |
576 | return 0; |
577 | ||
578 | return DIV_ROUND_UP(1000 * 1000, | |
1326a92c | 579 | drm_mode_vrefresh(&cstate->hw.adjusted_mode)); |
1c4d821d AG |
580 | } |
581 | ||
582 | static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, | |
583 | u32 idle_frames) | |
584 | { | |
585 | u32 val; | |
586 | ||
587 | idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; | |
c51e7138 | 588 | val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
1c4d821d AG |
589 | val &= ~EDP_PSR2_IDLE_FRAME_MASK; |
590 | val |= idle_frames; | |
c51e7138 | 591 | intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); |
1c4d821d AG |
592 | } |
593 | ||
594 | static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) | |
595 | { | |
596 | psr2_program_idle_frames(dev_priv, 0); | |
597 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); | |
598 | } | |
599 | ||
600 | static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) | |
601 | { | |
9e83713a | 602 | struct intel_dp *intel_dp = dev_priv->psr.dp; |
1c4d821d AG |
603 | |
604 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); | |
9e83713a | 605 | psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp)); |
1c4d821d AG |
606 | } |
607 | ||
ceaaf530 | 608 | static void tgl_dc3co_disable_work(struct work_struct *work) |
1c4d821d AG |
609 | { |
610 | struct drm_i915_private *dev_priv = | |
ceaaf530 | 611 | container_of(work, typeof(*dev_priv), psr.dc3co_work.work); |
1c4d821d AG |
612 | |
613 | mutex_lock(&dev_priv->psr.lock); | |
614 | /* If delayed work is pending, it is not idle */ | |
ceaaf530 | 615 | if (delayed_work_pending(&dev_priv->psr.dc3co_work)) |
1c4d821d AG |
616 | goto unlock; |
617 | ||
1c4d821d AG |
618 | tgl_psr2_disable_dc3co(dev_priv); |
619 | unlock: | |
620 | mutex_unlock(&dev_priv->psr.lock); | |
621 | } | |
622 | ||
623 | static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) | |
624 | { | |
625 | if (!dev_priv->psr.dc3co_enabled) | |
626 | return; | |
627 | ||
ceaaf530 | 628 | cancel_delayed_work(&dev_priv->psr.dc3co_work); |
1c4d821d AG |
629 | /* Before PSR2 exit disallow dc3co*/ |
630 | tgl_psr2_disable_dc3co(dev_priv); | |
631 | } | |
632 | ||
c5c772cf JRS |
633 | static void |
634 | tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, | |
635 | struct intel_crtc_state *crtc_state) | |
636 | { | |
637 | const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; | |
638 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
639 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
640 | u32 exit_scanlines; | |
641 | ||
642 | if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) | |
643 | return; | |
644 | ||
645 | /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ | |
646 | if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || | |
647 | dig_port->base.port != PORT_A) | |
648 | return; | |
649 | ||
650 | /* | |
651 | * DC3CO Exit time 200us B.Spec 49196 | |
652 | * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 | |
653 | */ | |
654 | exit_scanlines = | |
655 | intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; | |
656 | ||
16c56083 | 657 | if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) |
c5c772cf JRS |
658 | return; |
659 | ||
660 | crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; | |
661 | } | |
662 | ||
c4932d79 RV |
663 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
664 | struct intel_crtc_state *crtc_state) | |
665 | { | |
1895759e | 666 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1326a92c ML |
667 | int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; |
668 | int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; | |
f98837e8 | 669 | int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; |
c4932d79 | 670 | |
95f28d2e | 671 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
672 | return false; |
673 | ||
99fc38b1 | 674 | if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { |
6471bd74 WK |
675 | drm_dbg_kms(&dev_priv->drm, |
676 | "PSR2 not supported in transcoder %s\n", | |
677 | transcoder_name(crtc_state->cpu_transcoder)); | |
99fc38b1 JRS |
678 | return false; |
679 | } | |
680 | ||
8228c42f MN |
681 | /* |
682 | * DSC and PSR2 cannot be enabled simultaneously. If a requested | |
683 | * resolution requires DSC to be enabled, priority is given to DSC | |
684 | * over PSR2. | |
685 | */ | |
010663a6 | 686 | if (crtc_state->dsc.compression_enable) { |
6471bd74 WK |
687 | drm_dbg_kms(&dev_priv->drm, |
688 | "PSR2 cannot be enabled since DSC is enabled\n"); | |
8228c42f MN |
689 | return false; |
690 | } | |
691 | ||
f7b3c226 JRS |
692 | if (INTEL_GEN(dev_priv) >= 12) { |
693 | psr_max_h = 5120; | |
694 | psr_max_v = 3200; | |
f98837e8 | 695 | max_bpp = 30; |
f7b3c226 | 696 | } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
c90c275c DP |
697 | psr_max_h = 4096; |
698 | psr_max_v = 2304; | |
f98837e8 | 699 | max_bpp = 24; |
cf819eff | 700 | } else if (IS_GEN(dev_priv, 9)) { |
c90c275c DP |
701 | psr_max_h = 3640; |
702 | psr_max_v = 2304; | |
f98837e8 | 703 | max_bpp = 24; |
c90c275c DP |
704 | } |
705 | ||
706 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
6471bd74 WK |
707 | drm_dbg_kms(&dev_priv->drm, |
708 | "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
709 | crtc_hdisplay, crtc_vdisplay, | |
710 | psr_max_h, psr_max_v); | |
c4932d79 RV |
711 | return false; |
712 | } | |
713 | ||
f98837e8 | 714 | if (crtc_state->pipe_bpp > max_bpp) { |
6471bd74 WK |
715 | drm_dbg_kms(&dev_priv->drm, |
716 | "PSR2 not enabled, pipe bpp %d > max supported %d\n", | |
717 | crtc_state->pipe_bpp, max_bpp); | |
f98837e8 JRS |
718 | return false; |
719 | } | |
720 | ||
bef5e5b3 JRS |
721 | /* |
722 | * HW sends SU blocks of size four scan lines, which means the starting | |
723 | * X coordinate and Y granularity requirements will always be met. We | |
8c0d2c29 JRS |
724 | * only need to validate the SU block width is a multiple of |
725 | * x granularity. | |
bef5e5b3 | 726 | */ |
8c0d2c29 | 727 | if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { |
6471bd74 WK |
728 | drm_dbg_kms(&dev_priv->drm, |
729 | "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", | |
730 | crtc_hdisplay, dev_priv->psr.su_x_granularity); | |
bef5e5b3 JRS |
731 | return false; |
732 | } | |
733 | ||
618cf883 | 734 | if (crtc_state->crc_enabled) { |
6471bd74 WK |
735 | drm_dbg_kms(&dev_priv->drm, |
736 | "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); | |
618cf883 JRS |
737 | return false; |
738 | } | |
739 | ||
c5c772cf | 740 | tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); |
c4932d79 RV |
741 | return true; |
742 | } | |
743 | ||
4d90f2d5 VS |
744 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
745 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
746 | { |
747 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 748 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 749 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 750 | &crtc_state->hw.adjusted_mode; |
dfd2e9ab | 751 | int psr_setup_time; |
0bc12bcb | 752 | |
4371d896 | 753 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
754 | return; |
755 | ||
c44301fc | 756 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 757 | return; |
0bc12bcb | 758 | |
dc9b5a0c RV |
759 | /* |
760 | * HSW spec explicitly says PSR is tied to port A. | |
4ab4fa10 JRS |
761 | * BDW+ platforms have a instance of PSR registers per transcoder but |
762 | * for now it only supports one instance of PSR, so lets keep it | |
763 | * hardcoded to PORT_A | |
dc9b5a0c | 764 | */ |
ce3508fd | 765 | if (dig_port->base.port != PORT_A) { |
6471bd74 WK |
766 | drm_dbg_kms(&dev_priv->drm, |
767 | "PSR condition failed: Port not supported\n"); | |
4d90f2d5 | 768 | return; |
0bc12bcb RV |
769 | } |
770 | ||
50a12d8f | 771 | if (dev_priv->psr.sink_not_reliable) { |
6471bd74 WK |
772 | drm_dbg_kms(&dev_priv->drm, |
773 | "PSR sink implementation is not reliable\n"); | |
50a12d8f JRS |
774 | return; |
775 | } | |
776 | ||
7ae6ad6f | 777 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
6471bd74 WK |
778 | drm_dbg_kms(&dev_priv->drm, |
779 | "PSR condition failed: Interlaced mode enabled\n"); | |
4d90f2d5 | 780 | return; |
0bc12bcb RV |
781 | } |
782 | ||
dfd2e9ab VS |
783 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
784 | if (psr_setup_time < 0) { | |
6471bd74 WK |
785 | drm_dbg_kms(&dev_priv->drm, |
786 | "PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
787 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 788 | return; |
dfd2e9ab VS |
789 | } |
790 | ||
791 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
792 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
6471bd74 WK |
793 | drm_dbg_kms(&dev_priv->drm, |
794 | "PSR condition failed: PSR setup time (%d us) too long\n", | |
795 | psr_setup_time); | |
4d90f2d5 VS |
796 | return; |
797 | } | |
798 | ||
4d90f2d5 | 799 | crtc_state->has_psr = true; |
c4932d79 | 800 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
801 | } |
802 | ||
e2bbc343 | 803 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 804 | { |
1895759e | 805 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 806 | |
0f81e645 | 807 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) |
16c56083 PB |
808 | drm_WARN_ON(&dev_priv->drm, |
809 | intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); | |
0f81e645 | 810 | |
16c56083 PB |
811 | drm_WARN_ON(&dev_priv->drm, |
812 | intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); | |
813 | drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active); | |
0bc12bcb RV |
814 | lockdep_assert_held(&dev_priv->psr.lock); |
815 | ||
cf5d862d RV |
816 | /* psr1 and psr2 are mutually exclusive.*/ |
817 | if (dev_priv->psr.psr2_enabled) | |
818 | hsw_activate_psr2(intel_dp); | |
819 | else | |
820 | hsw_activate_psr1(intel_dp); | |
821 | ||
0bc12bcb RV |
822 | dev_priv->psr.active = true; |
823 | } | |
824 | ||
cf5d862d RV |
825 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
826 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 827 | { |
1895759e | 828 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 829 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 830 | u32 mask; |
4d1fa22f | 831 | |
d544e918 DP |
832 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
833 | * use hardcoded values PSR AUX transactions | |
834 | */ | |
835 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
836 | hsw_psr_setup_aux(intel_dp); | |
837 | ||
cf819eff | 838 | if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && |
d15f9cdd | 839 | !IS_GEMINILAKE(dev_priv))) { |
12c4d4c1 | 840 | i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); |
c51e7138 | 841 | u32 chicken = intel_de_read(dev_priv, reg); |
5e87325f | 842 | |
d15f9cdd JRS |
843 | chicken |= PSR2_VSC_ENABLE_PROG_HEADER | |
844 | PSR2_ADD_VERTICAL_LINE_COUNT; | |
c51e7138 | 845 | intel_de_write(dev_priv, reg, chicken); |
4d1fa22f | 846 | } |
bf80928f JRS |
847 | |
848 | /* | |
849 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
850 | * mask LPSP to avoid dependency on other drivers that might block | |
851 | * runtime_pm besides preventing other hw tracking issues now we | |
852 | * can rely on frontbuffer tracking. | |
853 | */ | |
fc6ff9dc JRS |
854 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
855 | EDP_PSR_DEBUG_MASK_HPD | | |
856 | EDP_PSR_DEBUG_MASK_LPSP | | |
857 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
858 | ||
859 | if (INTEL_GEN(dev_priv) < 11) | |
860 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
861 | ||
c51e7138 JN |
862 | intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder), |
863 | mask); | |
df7415bf | 864 | |
2f3b8712 | 865 | psr_irq_control(dev_priv); |
c5c772cf JRS |
866 | |
867 | if (crtc_state->dc3co_exitline) { | |
868 | u32 val; | |
869 | ||
870 | /* | |
871 | * TODO: if future platforms supports DC3CO in more than one | |
872 | * transcoder, EXITLINE will need to be unset when disabling PSR | |
873 | */ | |
ddfa21bc | 874 | val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); |
c5c772cf JRS |
875 | val &= ~EXITLINE_MASK; |
876 | val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; | |
877 | val |= EXITLINE_ENABLE; | |
ddfa21bc | 878 | intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); |
c5c772cf | 879 | } |
4d1fa22f RV |
880 | } |
881 | ||
c44301fc ML |
882 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
883 | const struct intel_crtc_state *crtc_state) | |
884 | { | |
885 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
4ab4fa10 | 886 | u32 val; |
c44301fc | 887 | |
16c56083 | 888 | drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); |
23ec9f52 JRS |
889 | |
890 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
891 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
2225f3c6 | 892 | dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; |
1c4d821d | 893 | dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; |
4ab4fa10 | 894 | dev_priv->psr.transcoder = crtc_state->cpu_transcoder; |
58c34c4c JRS |
895 | /* DC5/DC6 requires at least 6 idle frames */ |
896 | val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); | |
897 | dev_priv->psr.dc3co_exit_delay = val; | |
4ab4fa10 JRS |
898 | |
899 | /* | |
900 | * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR | |
901 | * will still keep the error set even after the reset done in the | |
902 | * irq_preinstall and irq_uninstall hooks. | |
903 | * And enabling in this situation cause the screen to freeze in the | |
904 | * first time that PSR HW tries to activate so lets keep PSR disabled | |
905 | * to avoid any rendering problems. | |
906 | */ | |
8241cfbe | 907 | if (INTEL_GEN(dev_priv) >= 12) { |
c51e7138 JN |
908 | val = intel_de_read(dev_priv, |
909 | TRANS_PSR_IIR(dev_priv->psr.transcoder)); | |
8241cfbe JRS |
910 | val &= EDP_PSR_ERROR(0); |
911 | } else { | |
c51e7138 | 912 | val = intel_de_read(dev_priv, EDP_PSR_IIR); |
8241cfbe JRS |
913 | val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); |
914 | } | |
4ab4fa10 JRS |
915 | if (val) { |
916 | dev_priv->psr.sink_not_reliable = true; | |
6471bd74 WK |
917 | drm_dbg_kms(&dev_priv->drm, |
918 | "PSR interruption error set, not enabling PSR\n"); | |
4ab4fa10 JRS |
919 | return; |
920 | } | |
c44301fc | 921 | |
6471bd74 WK |
922 | drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", |
923 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
c44301fc ML |
924 | intel_psr_setup_vsc(intel_dp, crtc_state); |
925 | intel_psr_enable_sink(intel_dp); | |
926 | intel_psr_enable_source(intel_dp, crtc_state); | |
927 | dev_priv->psr.enabled = true; | |
928 | ||
929 | intel_psr_activate(intel_dp); | |
930 | } | |
931 | ||
b2b89f55 RV |
932 | /** |
933 | * intel_psr_enable - Enable PSR | |
934 | * @intel_dp: Intel DP | |
d2419ffc | 935 | * @crtc_state: new CRTC state |
b2b89f55 RV |
936 | * |
937 | * This function can only be called after the pipe is fully trained and enabled. | |
938 | */ | |
d2419ffc VS |
939 | void intel_psr_enable(struct intel_dp *intel_dp, |
940 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 941 | { |
1895759e | 942 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 943 | |
df1a5bfc | 944 | if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) |
0bc12bcb | 945 | return; |
0bc12bcb | 946 | |
df1a5bfc JRS |
947 | dev_priv->psr.force_mode_changed = false; |
948 | ||
949 | if (!crtc_state->has_psr) | |
c9ef291a DP |
950 | return; |
951 | ||
16c56083 | 952 | drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); |
c44301fc | 953 | |
0bc12bcb | 954 | mutex_lock(&dev_priv->psr.lock); |
23ec9f52 | 955 | |
58d4ad50 | 956 | if (!psr_global_enabled(dev_priv)) { |
6471bd74 | 957 | drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); |
0bc12bcb RV |
958 | goto unlock; |
959 | } | |
960 | ||
23ec9f52 | 961 | intel_psr_enable_locked(dev_priv, crtc_state); |
d0ac896a | 962 | |
0bc12bcb RV |
963 | unlock: |
964 | mutex_unlock(&dev_priv->psr.lock); | |
965 | } | |
966 | ||
26f9ec9a JRS |
967 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
968 | { | |
969 | u32 val; | |
970 | ||
b2fc2252 | 971 | if (!dev_priv->psr.active) { |
0f81e645 | 972 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { |
c51e7138 JN |
973 | val = intel_de_read(dev_priv, |
974 | EDP_PSR2_CTL(dev_priv->psr.transcoder)); | |
16c56083 | 975 | drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); |
4ab4fa10 JRS |
976 | } |
977 | ||
c51e7138 JN |
978 | val = intel_de_read(dev_priv, |
979 | EDP_PSR_CTL(dev_priv->psr.transcoder)); | |
16c56083 | 980 | drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); |
4ab4fa10 | 981 | |
26f9ec9a | 982 | return; |
b2fc2252 | 983 | } |
26f9ec9a JRS |
984 | |
985 | if (dev_priv->psr.psr2_enabled) { | |
1c4d821d | 986 | tgl_disallow_dc3co_on_psr2_exit(dev_priv); |
c51e7138 JN |
987 | val = intel_de_read(dev_priv, |
988 | EDP_PSR2_CTL(dev_priv->psr.transcoder)); | |
16c56083 | 989 | drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); |
4ab4fa10 | 990 | val &= ~EDP_PSR2_ENABLE; |
c51e7138 JN |
991 | intel_de_write(dev_priv, |
992 | EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a | 993 | } else { |
c51e7138 JN |
994 | val = intel_de_read(dev_priv, |
995 | EDP_PSR_CTL(dev_priv->psr.transcoder)); | |
16c56083 | 996 | drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); |
4ab4fa10 | 997 | val &= ~EDP_PSR_ENABLE; |
c51e7138 JN |
998 | intel_de_write(dev_priv, |
999 | EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a JRS |
1000 | } |
1001 | dev_priv->psr.active = false; | |
1002 | } | |
1003 | ||
2ee936e3 | 1004 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 1005 | { |
1895759e | 1006 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
1007 | i915_reg_t psr_status; |
1008 | u32 psr_status_mask; | |
0bc12bcb | 1009 | |
2ee936e3 JRS |
1010 | lockdep_assert_held(&dev_priv->psr.lock); |
1011 | ||
1012 | if (!dev_priv->psr.enabled) | |
1013 | return; | |
1014 | ||
6471bd74 WK |
1015 | drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", |
1016 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
2ee936e3 | 1017 | |
b2fc2252 | 1018 | intel_psr_exit(dev_priv); |
77affa31 | 1019 | |
b2fc2252 | 1020 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 1021 | psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 1022 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
0bc12bcb | 1023 | } else { |
4ab4fa10 | 1024 | psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 1025 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 1026 | } |
b2fc2252 JRS |
1027 | |
1028 | /* Wait till PSR is idle */ | |
4cb3b44d DCS |
1029 | if (intel_de_wait_for_clear(dev_priv, psr_status, |
1030 | psr_status_mask, 2000)) | |
6471bd74 | 1031 | drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); |
cc3054ff JRS |
1032 | |
1033 | /* Disable PSR on Sink */ | |
1034 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
1035 | ||
700355af JRS |
1036 | if (dev_priv->psr.psr2_enabled) |
1037 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); | |
1038 | ||
c44301fc | 1039 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
1040 | } |
1041 | ||
e2bbc343 RV |
1042 | /** |
1043 | * intel_psr_disable - Disable PSR | |
1044 | * @intel_dp: Intel DP | |
d2419ffc | 1045 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
1046 | * |
1047 | * This function needs to be called before disabling pipe. | |
1048 | */ | |
d2419ffc VS |
1049 | void intel_psr_disable(struct intel_dp *intel_dp, |
1050 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 1051 | { |
1895759e | 1052 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 1053 | |
4d90f2d5 | 1054 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
1055 | return; |
1056 | ||
16c56083 | 1057 | if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) |
c9ef291a DP |
1058 | return; |
1059 | ||
e2bbc343 | 1060 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 1061 | |
cc3054ff | 1062 | intel_psr_disable_locked(intel_dp); |
c44301fc | 1063 | |
0bc12bcb | 1064 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 1065 | cancel_work_sync(&dev_priv->psr.work); |
ceaaf530 | 1066 | cancel_delayed_work_sync(&dev_priv->psr.dc3co_work); |
0bc12bcb RV |
1067 | } |
1068 | ||
88e05aff JRS |
1069 | static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) |
1070 | { | |
381f8a20 JRS |
1071 | if (INTEL_GEN(dev_priv) >= 9) |
1072 | /* | |
1073 | * Display WA #0884: skl+ | |
1074 | * This documented WA for bxt can be safely applied | |
1075 | * broadly so we can force HW tracking to exit PSR | |
1076 | * instead of disabling and re-enabling. | |
1077 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
1078 | * but it makes more sense write to the current active | |
1079 | * pipe. | |
1080 | */ | |
c51e7138 | 1081 | intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0); |
381f8a20 JRS |
1082 | else |
1083 | /* | |
1084 | * A write to CURSURFLIVE do not cause HW tracking to exit PSR | |
1085 | * on older gens so doing the manual exit instead. | |
1086 | */ | |
1087 | intel_psr_exit(dev_priv); | |
88e05aff JRS |
1088 | } |
1089 | ||
23ec9f52 JRS |
1090 | /** |
1091 | * intel_psr_update - Update PSR state | |
1092 | * @intel_dp: Intel DP | |
1093 | * @crtc_state: new CRTC state | |
1094 | * | |
1095 | * This functions will update PSR states, disabling, enabling or switching PSR | |
1096 | * version when executing fastsets. For full modeset, intel_psr_disable() and | |
1097 | * intel_psr_enable() should be called instead. | |
1098 | */ | |
1099 | void intel_psr_update(struct intel_dp *intel_dp, | |
1100 | const struct intel_crtc_state *crtc_state) | |
1101 | { | |
1102 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1103 | struct i915_psr *psr = &dev_priv->psr; | |
1104 | bool enable, psr2_enable; | |
1105 | ||
1106 | if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) | |
1107 | return; | |
1108 | ||
df1a5bfc JRS |
1109 | dev_priv->psr.force_mode_changed = false; |
1110 | ||
23ec9f52 JRS |
1111 | mutex_lock(&dev_priv->psr.lock); |
1112 | ||
58d4ad50 | 1113 | enable = crtc_state->has_psr && psr_global_enabled(dev_priv); |
23ec9f52 JRS |
1114 | psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); |
1115 | ||
88e05aff JRS |
1116 | if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { |
1117 | /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ | |
1118 | if (crtc_state->crc_enabled && psr->enabled) | |
1119 | psr_force_hw_tracking_exit(dev_priv); | |
381f8a20 JRS |
1120 | else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { |
1121 | /* | |
1122 | * Activate PSR again after a force exit when enabling | |
1123 | * CRC in older gens | |
1124 | */ | |
1125 | if (!dev_priv->psr.active && | |
1126 | !dev_priv->psr.busy_frontbuffer_bits) | |
1127 | schedule_work(&dev_priv->psr.work); | |
1128 | } | |
88e05aff | 1129 | |
23ec9f52 | 1130 | goto unlock; |
88e05aff | 1131 | } |
23ec9f52 | 1132 | |
9f952664 JRS |
1133 | if (psr->enabled) |
1134 | intel_psr_disable_locked(intel_dp); | |
23ec9f52 | 1135 | |
9f952664 JRS |
1136 | if (enable) |
1137 | intel_psr_enable_locked(dev_priv, crtc_state); | |
23ec9f52 JRS |
1138 | |
1139 | unlock: | |
1140 | mutex_unlock(&dev_priv->psr.lock); | |
1141 | } | |
1142 | ||
65df9c79 DP |
1143 | /** |
1144 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
1145 | * @new_crtc_state: new CRTC state | |
1146 | * @out_value: PSR status in case of failure | |
1147 | * | |
1148 | * This function is expected to be called from pipe_update_start() where it is | |
1149 | * not expected to race with PSR enable or disable. | |
1150 | * | |
1151 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
1152 | */ | |
63ec132d DP |
1153 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
1154 | u32 *out_value) | |
c43dbcbb | 1155 | { |
2225f3c6 | 1156 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); |
c3d43361 | 1157 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
c43dbcbb | 1158 | |
c44301fc | 1159 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
1160 | return 0; |
1161 | ||
fd255f6e DP |
1162 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
1163 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
1164 | return 0; | |
c43dbcbb TV |
1165 | |
1166 | /* | |
65df9c79 DP |
1167 | * From bspec: Panel Self Refresh (BDW+) |
1168 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
1169 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
1170 | * defensive enough to cover everything. | |
c43dbcbb | 1171 | */ |
63ec132d | 1172 | |
4ab4fa10 JRS |
1173 | return __intel_wait_for_register(&dev_priv->uncore, |
1174 | EDP_PSR_STATUS(dev_priv->psr.transcoder), | |
fd255f6e | 1175 | EDP_PSR_STATUS_STATE_MASK, |
63ec132d DP |
1176 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
1177 | out_value); | |
c43dbcbb TV |
1178 | } |
1179 | ||
1180 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 1181 | { |
daeb725e CW |
1182 | i915_reg_t reg; |
1183 | u32 mask; | |
1184 | int err; | |
1185 | ||
c44301fc | 1186 | if (!dev_priv->psr.enabled) |
daeb725e | 1187 | return false; |
0bc12bcb | 1188 | |
ce3508fd | 1189 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 1190 | reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1191 | mask = EDP_PSR2_STATUS_STATE_MASK; |
995d3047 | 1192 | } else { |
4ab4fa10 | 1193 | reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1194 | mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 1195 | } |
daeb725e CW |
1196 | |
1197 | mutex_unlock(&dev_priv->psr.lock); | |
1198 | ||
4cb3b44d | 1199 | err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); |
daeb725e | 1200 | if (err) |
6471bd74 WK |
1201 | drm_err(&dev_priv->drm, |
1202 | "Timed out waiting for PSR Idle for re-enable\n"); | |
daeb725e CW |
1203 | |
1204 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 1205 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
1206 | return err == 0 && dev_priv->psr.enabled; |
1207 | } | |
0bc12bcb | 1208 | |
23ec9f52 | 1209 | static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) |
2ac45bdd | 1210 | { |
23ec9f52 JRS |
1211 | struct drm_device *dev = &dev_priv->drm; |
1212 | struct drm_modeset_acquire_ctx ctx; | |
1213 | struct drm_atomic_state *state; | |
3558cafc | 1214 | struct intel_crtc *crtc; |
23ec9f52 | 1215 | int err; |
2ac45bdd | 1216 | |
23ec9f52 JRS |
1217 | state = drm_atomic_state_alloc(dev); |
1218 | if (!state) | |
1219 | return -ENOMEM; | |
2ac45bdd | 1220 | |
23ec9f52 JRS |
1221 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
1222 | state->acquire_ctx = &ctx; | |
1223 | ||
1224 | retry: | |
3558cafc ML |
1225 | for_each_intel_crtc(dev, crtc) { |
1226 | struct intel_crtc_state *crtc_state = | |
1227 | intel_atomic_get_crtc_state(state, crtc); | |
23ec9f52 | 1228 | |
23ec9f52 JRS |
1229 | if (IS_ERR(crtc_state)) { |
1230 | err = PTR_ERR(crtc_state); | |
1231 | goto error; | |
1232 | } | |
1233 | ||
1326a92c | 1234 | if (crtc_state->hw.active && crtc_state->has_psr) { |
23ec9f52 | 1235 | /* Mark mode as changed to trigger a pipe->update() */ |
2225f3c6 | 1236 | crtc_state->uapi.mode_changed = true; |
23ec9f52 JRS |
1237 | break; |
1238 | } | |
1239 | } | |
1240 | ||
1241 | err = drm_atomic_commit(state); | |
2ac45bdd | 1242 | |
23ec9f52 JRS |
1243 | error: |
1244 | if (err == -EDEADLK) { | |
1245 | drm_atomic_state_clear(state); | |
1246 | err = drm_modeset_backoff(&ctx); | |
1247 | if (!err) | |
1248 | goto retry; | |
1249 | } | |
1250 | ||
1251 | drm_modeset_drop_locks(&ctx); | |
1252 | drm_modeset_acquire_fini(&ctx); | |
1253 | drm_atomic_state_put(state); | |
1254 | ||
1255 | return err; | |
2ac45bdd ML |
1256 | } |
1257 | ||
23ec9f52 | 1258 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) |
c44301fc | 1259 | { |
23ec9f52 JRS |
1260 | const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
1261 | u32 old_mode; | |
c44301fc | 1262 | int ret; |
c44301fc ML |
1263 | |
1264 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 1265 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
6471bd74 | 1266 | drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); |
c44301fc ML |
1267 | return -EINVAL; |
1268 | } | |
1269 | ||
c44301fc ML |
1270 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); |
1271 | if (ret) | |
1272 | return ret; | |
1273 | ||
23ec9f52 | 1274 | old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; |
c44301fc | 1275 | dev_priv->psr.debug = val; |
2f3b8712 JRS |
1276 | |
1277 | /* | |
1278 | * Do it right away if it's already enabled, otherwise it will be done | |
1279 | * when enabling the source. | |
1280 | */ | |
1281 | if (dev_priv->psr.enabled) | |
1282 | psr_irq_control(dev_priv); | |
c44301fc | 1283 | |
c44301fc | 1284 | mutex_unlock(&dev_priv->psr.lock); |
23ec9f52 JRS |
1285 | |
1286 | if (old_mode != mode) | |
1287 | ret = intel_psr_fastset_force(dev_priv); | |
1288 | ||
c44301fc ML |
1289 | return ret; |
1290 | } | |
1291 | ||
183b8e67 JRS |
1292 | static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) |
1293 | { | |
1294 | struct i915_psr *psr = &dev_priv->psr; | |
1295 | ||
1296 | intel_psr_disable_locked(psr->dp); | |
1297 | psr->sink_not_reliable = true; | |
1298 | /* let's make sure that sink is awaken */ | |
1299 | drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); | |
1300 | } | |
1301 | ||
daeb725e CW |
1302 | static void intel_psr_work(struct work_struct *work) |
1303 | { | |
1304 | struct drm_i915_private *dev_priv = | |
5422b37c | 1305 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
1306 | |
1307 | mutex_lock(&dev_priv->psr.lock); | |
1308 | ||
5422b37c RV |
1309 | if (!dev_priv->psr.enabled) |
1310 | goto unlock; | |
1311 | ||
183b8e67 JRS |
1312 | if (READ_ONCE(dev_priv->psr.irq_aux_error)) |
1313 | intel_psr_handle_irq(dev_priv); | |
1314 | ||
daeb725e CW |
1315 | /* |
1316 | * We have to make sure PSR is ready for re-enable | |
1317 | * otherwise it keeps disabled until next full enable/disable cycle. | |
1318 | * PSR might take some time to get fully disabled | |
1319 | * and be ready for re-enable. | |
1320 | */ | |
c43dbcbb | 1321 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
1322 | goto unlock; |
1323 | ||
1324 | /* | |
1325 | * The delayed work can race with an invalidate hence we need to | |
1326 | * recheck. Since psr_flush first clears this and then reschedules we | |
1327 | * won't ever miss a flush when bailing out here. | |
1328 | */ | |
c12e0643 | 1329 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
1330 | goto unlock; |
1331 | ||
c44301fc | 1332 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
1333 | unlock: |
1334 | mutex_unlock(&dev_priv->psr.lock); | |
1335 | } | |
1336 | ||
b2b89f55 RV |
1337 | /** |
1338 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 1339 | * @dev_priv: i915 device |
b2b89f55 | 1340 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 1341 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
1342 | * |
1343 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1344 | * with the software frontbuffer tracking. This function gets called every | |
1345 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
1346 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
1347 | * | |
1348 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
1349 | */ | |
5748b6a1 | 1350 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 1351 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1352 | { |
4371d896 | 1353 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1354 | return; |
1355 | ||
ce3508fd | 1356 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1357 | return; |
1358 | ||
0bc12bcb RV |
1359 | mutex_lock(&dev_priv->psr.lock); |
1360 | if (!dev_priv->psr.enabled) { | |
1361 | mutex_unlock(&dev_priv->psr.lock); | |
1362 | return; | |
1363 | } | |
1364 | ||
f0ad62a6 | 1365 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb | 1366 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
1367 | |
1368 | if (frontbuffer_bits) | |
5748b6a1 | 1369 | intel_psr_exit(dev_priv); |
ec76d629 | 1370 | |
0bc12bcb RV |
1371 | mutex_unlock(&dev_priv->psr.lock); |
1372 | } | |
1373 | ||
1c4d821d AG |
1374 | /* |
1375 | * When we will be completely rely on PSR2 S/W tracking in future, | |
1376 | * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP | |
1377 | * event also therefore tgl_dc3co_flush() require to be changed | |
ceaaf530 | 1378 | * accordingly in future. |
1c4d821d AG |
1379 | */ |
1380 | static void | |
1381 | tgl_dc3co_flush(struct drm_i915_private *dev_priv, | |
1382 | unsigned int frontbuffer_bits, enum fb_op_origin origin) | |
1383 | { | |
1c4d821d AG |
1384 | mutex_lock(&dev_priv->psr.lock); |
1385 | ||
1386 | if (!dev_priv->psr.dc3co_enabled) | |
1387 | goto unlock; | |
1388 | ||
1389 | if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) | |
1390 | goto unlock; | |
1391 | ||
1392 | /* | |
1393 | * At every frontbuffer flush flip event modified delay of delayed work, | |
1394 | * when delayed work schedules that means display has been idle. | |
1395 | */ | |
1396 | if (!(frontbuffer_bits & | |
1397 | INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) | |
1398 | goto unlock; | |
1399 | ||
1400 | tgl_psr2_enable_dc3co(dev_priv); | |
ceaaf530 | 1401 | mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work, |
58c34c4c | 1402 | dev_priv->psr.dc3co_exit_delay); |
1c4d821d AG |
1403 | |
1404 | unlock: | |
1405 | mutex_unlock(&dev_priv->psr.lock); | |
1406 | } | |
1407 | ||
b2b89f55 RV |
1408 | /** |
1409 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 1410 | * @dev_priv: i915 device |
b2b89f55 | 1411 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 1412 | * @origin: which operation caused the flush |
b2b89f55 RV |
1413 | * |
1414 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1415 | * with the software frontbuffer tracking. This function gets called every | |
1416 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
1417 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
1418 | * | |
1419 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
1420 | */ | |
5748b6a1 | 1421 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 1422 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1423 | { |
4371d896 | 1424 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1425 | return; |
1426 | ||
1c4d821d AG |
1427 | if (origin == ORIGIN_FLIP) { |
1428 | tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); | |
5baf63cc | 1429 | return; |
1c4d821d | 1430 | } |
5baf63cc | 1431 | |
0bc12bcb RV |
1432 | mutex_lock(&dev_priv->psr.lock); |
1433 | if (!dev_priv->psr.enabled) { | |
1434 | mutex_unlock(&dev_priv->psr.lock); | |
1435 | return; | |
1436 | } | |
1437 | ||
f0ad62a6 | 1438 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb RV |
1439 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1440 | ||
921ec285 | 1441 | /* By definition flush = invalidate + flush */ |
88e05aff JRS |
1442 | if (frontbuffer_bits) |
1443 | psr_force_hw_tracking_exit(dev_priv); | |
995d3047 | 1444 | |
0bc12bcb | 1445 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1446 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1447 | mutex_unlock(&dev_priv->psr.lock); |
1448 | } | |
1449 | ||
b2b89f55 RV |
1450 | /** |
1451 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1452 | * @dev_priv: i915 device private |
b2b89f55 RV |
1453 | * |
1454 | * This function is called only once at driver load to initialize basic | |
1455 | * PSR stuff. | |
1456 | */ | |
c39055b0 | 1457 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1458 | { |
0f328da6 RV |
1459 | if (!HAS_PSR(dev_priv)) |
1460 | return; | |
1461 | ||
c9ef291a DP |
1462 | if (!dev_priv->psr.sink_support) |
1463 | return; | |
1464 | ||
4ab4fa10 JRS |
1465 | if (IS_HASWELL(dev_priv)) |
1466 | /* | |
1467 | * HSW don't have PSR registers on the same space as transcoder | |
1468 | * so set this to a value that when subtract to the register | |
1469 | * in transcoder space results in the right offset for HSW | |
1470 | */ | |
1471 | dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; | |
1472 | ||
598c6cfe DP |
1473 | if (i915_modparams.enable_psr == -1) |
1474 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1475 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1476 | |
65f61b42 | 1477 | /* Set link_standby x link_off defaults */ |
8652744b | 1478 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1479 | /* HSW and BDW require workarounds that we don't implement. */ |
1480 | dev_priv->psr.link_standby = false; | |
99d7a741 JRS |
1481 | else if (INTEL_GEN(dev_priv) < 12) |
1482 | /* For new platforms up to TGL let's respect VBT back again */ | |
60e5ffe3 RV |
1483 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; |
1484 | ||
5422b37c | 1485 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
ceaaf530 | 1486 | INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work); |
0bc12bcb RV |
1487 | mutex_init(&dev_priv->psr.lock); |
1488 | } | |
cc3054ff | 1489 | |
95851205 JRS |
1490 | static int psr_get_status_and_error_status(struct intel_dp *intel_dp, |
1491 | u8 *status, u8 *error_status) | |
1492 | { | |
1493 | struct drm_dp_aux *aux = &intel_dp->aux; | |
1494 | int ret; | |
1495 | ||
1496 | ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); | |
1497 | if (ret != 1) | |
1498 | return ret; | |
1499 | ||
1500 | ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); | |
1501 | if (ret != 1) | |
1502 | return ret; | |
1503 | ||
1504 | *status = *status & DP_PSR_SINK_STATE_MASK; | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
700355af JRS |
1509 | static void psr_alpm_check(struct intel_dp *intel_dp) |
1510 | { | |
1511 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1512 | struct drm_dp_aux *aux = &intel_dp->aux; | |
1513 | struct i915_psr *psr = &dev_priv->psr; | |
1514 | u8 val; | |
1515 | int r; | |
1516 | ||
1517 | if (!psr->psr2_enabled) | |
1518 | return; | |
1519 | ||
1520 | r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); | |
1521 | if (r != 1) { | |
6471bd74 | 1522 | drm_err(&dev_priv->drm, "Error reading ALPM status\n"); |
700355af JRS |
1523 | return; |
1524 | } | |
1525 | ||
1526 | if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { | |
1527 | intel_psr_disable_locked(intel_dp); | |
1528 | psr->sink_not_reliable = true; | |
6471bd74 WK |
1529 | drm_dbg_kms(&dev_priv->drm, |
1530 | "ALPM lock timeout error, disabling PSR\n"); | |
700355af JRS |
1531 | |
1532 | /* Clearing error */ | |
1533 | drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); | |
1534 | } | |
1535 | } | |
1536 | ||
ba0af30d JRS |
1537 | static void psr_capability_changed_check(struct intel_dp *intel_dp) |
1538 | { | |
1539 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1540 | struct i915_psr *psr = &dev_priv->psr; | |
1541 | u8 val; | |
1542 | int r; | |
1543 | ||
1544 | r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); | |
1545 | if (r != 1) { | |
6471bd74 | 1546 | drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); |
ba0af30d JRS |
1547 | return; |
1548 | } | |
1549 | ||
1550 | if (val & DP_PSR_CAPS_CHANGE) { | |
1551 | intel_psr_disable_locked(intel_dp); | |
1552 | psr->sink_not_reliable = true; | |
6471bd74 WK |
1553 | drm_dbg_kms(&dev_priv->drm, |
1554 | "Sink PSR capability changed, disabling PSR\n"); | |
ba0af30d JRS |
1555 | |
1556 | /* Clearing it */ | |
1557 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); | |
1558 | } | |
1559 | } | |
1560 | ||
cc3054ff JRS |
1561 | void intel_psr_short_pulse(struct intel_dp *intel_dp) |
1562 | { | |
1895759e | 1563 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff | 1564 | struct i915_psr *psr = &dev_priv->psr; |
95851205 | 1565 | u8 status, error_status; |
93bf76ed | 1566 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1567 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1568 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1569 | |
1570 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1571 | return; | |
1572 | ||
1573 | mutex_lock(&psr->lock); | |
1574 | ||
c44301fc | 1575 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1576 | goto exit; |
1577 | ||
95851205 | 1578 | if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { |
6471bd74 WK |
1579 | drm_err(&dev_priv->drm, |
1580 | "Error reading PSR status or error status\n"); | |
cc3054ff JRS |
1581 | goto exit; |
1582 | } | |
1583 | ||
95851205 | 1584 | if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { |
cc3054ff | 1585 | intel_psr_disable_locked(intel_dp); |
50a12d8f | 1586 | psr->sink_not_reliable = true; |
cc3054ff JRS |
1587 | } |
1588 | ||
95851205 | 1589 | if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) |
6471bd74 WK |
1590 | drm_dbg_kms(&dev_priv->drm, |
1591 | "PSR sink internal error, disabling PSR\n"); | |
95851205 | 1592 | if (error_status & DP_PSR_RFB_STORAGE_ERROR) |
6471bd74 WK |
1593 | drm_dbg_kms(&dev_priv->drm, |
1594 | "PSR RFB storage error, disabling PSR\n"); | |
95851205 | 1595 | if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) |
6471bd74 WK |
1596 | drm_dbg_kms(&dev_priv->drm, |
1597 | "PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
95851205 | 1598 | if (error_status & DP_PSR_LINK_CRC_ERROR) |
6471bd74 WK |
1599 | drm_dbg_kms(&dev_priv->drm, |
1600 | "PSR Link CRC error, disabling PSR\n"); | |
93bf76ed | 1601 | |
95851205 | 1602 | if (error_status & ~errors) |
6471bd74 WK |
1603 | drm_err(&dev_priv->drm, |
1604 | "PSR_ERROR_STATUS unhandled errors %x\n", | |
1605 | error_status & ~errors); | |
93bf76ed | 1606 | /* clear status register */ |
95851205 | 1607 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); |
700355af JRS |
1608 | |
1609 | psr_alpm_check(intel_dp); | |
ba0af30d | 1610 | psr_capability_changed_check(intel_dp); |
700355af | 1611 | |
cc3054ff JRS |
1612 | exit: |
1613 | mutex_unlock(&psr->lock); | |
1614 | } | |
2f8e7ea9 JRS |
1615 | |
1616 | bool intel_psr_enabled(struct intel_dp *intel_dp) | |
1617 | { | |
1618 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1619 | bool ret; | |
1620 | ||
1621 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1622 | return false; | |
1623 | ||
1624 | mutex_lock(&dev_priv->psr.lock); | |
1625 | ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); | |
1626 | mutex_unlock(&dev_priv->psr.lock); | |
1627 | ||
1628 | return ret; | |
1629 | } | |
60c6a14b JRS |
1630 | |
1631 | void intel_psr_atomic_check(struct drm_connector *connector, | |
1632 | struct drm_connector_state *old_state, | |
1633 | struct drm_connector_state *new_state) | |
1634 | { | |
1635 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1636 | struct intel_connector *intel_connector; | |
1637 | struct intel_digital_port *dig_port; | |
1638 | struct drm_crtc_state *crtc_state; | |
1639 | ||
1640 | if (!CAN_PSR(dev_priv) || !new_state->crtc || | |
df1a5bfc | 1641 | !dev_priv->psr.force_mode_changed) |
60c6a14b JRS |
1642 | return; |
1643 | ||
1644 | intel_connector = to_intel_connector(connector); | |
fa7edcd2 | 1645 | dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector)); |
60c6a14b JRS |
1646 | if (dev_priv->psr.dp != &dig_port->dp) |
1647 | return; | |
1648 | ||
1649 | crtc_state = drm_atomic_get_new_crtc_state(new_state->state, | |
1650 | new_state->crtc); | |
1651 | crtc_state->mode_changed = true; | |
df1a5bfc JRS |
1652 | } |
1653 | ||
1654 | void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp) | |
1655 | { | |
1656 | struct drm_i915_private *dev_priv; | |
1657 | ||
1658 | if (!intel_dp) | |
1659 | return; | |
1660 | ||
1661 | dev_priv = dp_to_i915(intel_dp); | |
1662 | if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp) | |
1663 | return; | |
1664 | ||
1665 | dev_priv->psr.force_mode_changed = true; | |
60c6a14b | 1666 | } |