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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
55367a27 JN |
24 | #include <drm/drm_atomic_helper.h> |
25 | ||
379bc100 JN |
26 | #include "display/intel_dp.h" |
27 | ||
55367a27 | 28 | #include "i915_drv.h" |
1d455f8d | 29 | #include "intel_display_types.h" |
55367a27 | 30 | #include "intel_psr.h" |
f9a79f9a | 31 | #include "intel_sprite.h" |
55367a27 | 32 | |
b2b89f55 RV |
33 | /** |
34 | * DOC: Panel Self Refresh (PSR/SRD) | |
35 | * | |
36 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
37 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
38 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
39 | * when system is idle but display is on as it eliminates display refresh | |
40 | * request to DDR memory completely as long as the frame buffer for that | |
41 | * display is unchanged. | |
42 | * | |
43 | * Panel Self Refresh must be supported by both Hardware (source) and | |
44 | * Panel (sink). | |
45 | * | |
46 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
47 | * to power down the link and memory controller. For DSI panels the same idea | |
48 | * is called "manual mode". | |
49 | * | |
50 | * The implementation uses the hardware-based PSR support which automatically | |
51 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
52 | * required DP aux message and could even retrain the link (that part isn't | |
53 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
54 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
55 | * part doesn't work too well, hence why the i915 PSR support uses the | |
56 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
57 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
58 | * get called by the frontbuffer tracking code. Note that because of locking | |
59 | * issues the self-refresh re-enable code is done from a work queue, which | |
60 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
61 | */ | |
62 | ||
c44301fc ML |
63 | static bool psr_global_enabled(u32 debug) |
64 | { | |
65 | switch (debug & I915_PSR_DEBUG_MODE_MASK) { | |
66 | case I915_PSR_DEBUG_DEFAULT: | |
67 | return i915_modparams.enable_psr; | |
68 | case I915_PSR_DEBUG_DISABLE: | |
69 | return false; | |
70 | default: | |
71 | return true; | |
72 | } | |
73 | } | |
74 | ||
2ac45bdd ML |
75 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
76 | const struct intel_crtc_state *crtc_state) | |
77 | { | |
8228c42f MN |
78 | /* Cannot enable DSC and PSR2 simultaneously */ |
79 | WARN_ON(crtc_state->dsc_params.compression_enable && | |
80 | crtc_state->has_psr2); | |
81 | ||
2ac45bdd | 82 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
235ca26f | 83 | case I915_PSR_DEBUG_DISABLE: |
2ac45bdd ML |
84 | case I915_PSR_DEBUG_FORCE_PSR1: |
85 | return false; | |
86 | default: | |
87 | return crtc_state->has_psr2; | |
88 | } | |
89 | } | |
90 | ||
c0871805 ID |
91 | static int edp_psr_shift(enum transcoder cpu_transcoder) |
92 | { | |
93 | switch (cpu_transcoder) { | |
94 | case TRANSCODER_A: | |
95 | return EDP_PSR_TRANSCODER_A_SHIFT; | |
96 | case TRANSCODER_B: | |
97 | return EDP_PSR_TRANSCODER_B_SHIFT; | |
98 | case TRANSCODER_C: | |
99 | return EDP_PSR_TRANSCODER_C_SHIFT; | |
100 | default: | |
101 | MISSING_CASE(cpu_transcoder); | |
102 | /* fallthrough */ | |
103 | case TRANSCODER_EDP: | |
104 | return EDP_PSR_TRANSCODER_EDP_SHIFT; | |
105 | } | |
106 | } | |
107 | ||
df7415bf | 108 | static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) |
54fd3149 DP |
109 | { |
110 | u32 debug_mask, mask; | |
c0871805 ID |
111 | enum transcoder cpu_transcoder; |
112 | u32 transcoders = BIT(TRANSCODER_EDP); | |
54fd3149 | 113 | |
c0871805 ID |
114 | if (INTEL_GEN(dev_priv) >= 8) |
115 | transcoders |= BIT(TRANSCODER_A) | | |
116 | BIT(TRANSCODER_B) | | |
117 | BIT(TRANSCODER_C); | |
118 | ||
119 | debug_mask = 0; | |
120 | mask = 0; | |
121 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
122 | int shift = edp_psr_shift(cpu_transcoder); | |
123 | ||
124 | mask |= EDP_PSR_ERROR(shift); | |
125 | debug_mask |= EDP_PSR_POST_EXIT(shift) | | |
126 | EDP_PSR_PRE_ENTRY(shift); | |
54fd3149 DP |
127 | } |
128 | ||
1aeb1b5f | 129 | if (debug & I915_PSR_DEBUG_IRQ) |
54fd3149 DP |
130 | mask |= debug_mask; |
131 | ||
54fd3149 DP |
132 | I915_WRITE(EDP_PSR_IMR, ~mask); |
133 | } | |
134 | ||
bc18b4df JRS |
135 | static void psr_event_print(u32 val, bool psr2_enabled) |
136 | { | |
137 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
138 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
139 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
140 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
141 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
142 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
143 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
144 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
145 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
146 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
147 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
148 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
149 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
150 | if (val & PSR_EVENT_MEMORY_UP) | |
151 | DRM_DEBUG_KMS("\tMemory up\n"); | |
152 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
153 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
154 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
155 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
156 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
157 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
158 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
159 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
160 | if (val & PSR_EVENT_HDCP_ENABLE) | |
161 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
162 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
163 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
164 | if (val & PSR_EVENT_VBI_ENABLE) | |
165 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
166 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
167 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
168 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
169 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
170 | } | |
171 | ||
54fd3149 DP |
172 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
173 | { | |
174 | u32 transcoders = BIT(TRANSCODER_EDP); | |
175 | enum transcoder cpu_transcoder; | |
3f983e54 | 176 | ktime_t time_ns = ktime_get(); |
183b8e67 | 177 | u32 mask = 0; |
54fd3149 DP |
178 | |
179 | if (INTEL_GEN(dev_priv) >= 8) | |
180 | transcoders |= BIT(TRANSCODER_A) | | |
181 | BIT(TRANSCODER_B) | | |
182 | BIT(TRANSCODER_C); | |
183 | ||
184 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
c0871805 ID |
185 | int shift = edp_psr_shift(cpu_transcoder); |
186 | ||
183b8e67 JRS |
187 | if (psr_iir & EDP_PSR_ERROR(shift)) { |
188 | DRM_WARN("[transcoder %s] PSR aux error\n", | |
189 | transcoder_name(cpu_transcoder)); | |
190 | ||
191 | dev_priv->psr.irq_aux_error = true; | |
192 | ||
193 | /* | |
194 | * If this interruption is not masked it will keep | |
195 | * interrupting so fast that it prevents the scheduled | |
196 | * work to run. | |
197 | * Also after a PSR error, we don't want to arm PSR | |
198 | * again so we don't care about unmask the interruption | |
199 | * or unset irq_aux_error. | |
200 | */ | |
201 | mask |= EDP_PSR_ERROR(shift); | |
202 | } | |
54fd3149 | 203 | |
c0871805 | 204 | if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) { |
3f983e54 | 205 | dev_priv->psr.last_entry_attempt = time_ns; |
54fd3149 DP |
206 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", |
207 | transcoder_name(cpu_transcoder)); | |
3f983e54 | 208 | } |
54fd3149 | 209 | |
c0871805 | 210 | if (psr_iir & EDP_PSR_POST_EXIT(shift)) { |
3f983e54 | 211 | dev_priv->psr.last_exit = time_ns; |
54fd3149 DP |
212 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", |
213 | transcoder_name(cpu_transcoder)); | |
bc18b4df JRS |
214 | |
215 | if (INTEL_GEN(dev_priv) >= 9) { | |
216 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
217 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
218 | ||
219 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); | |
220 | psr_event_print(val, psr2_enabled); | |
221 | } | |
3f983e54 | 222 | } |
54fd3149 | 223 | } |
183b8e67 JRS |
224 | |
225 | if (mask) { | |
226 | mask |= I915_READ(EDP_PSR_IMR); | |
227 | I915_WRITE(EDP_PSR_IMR, mask); | |
228 | ||
229 | schedule_work(&dev_priv->psr.work); | |
230 | } | |
54fd3149 DP |
231 | } |
232 | ||
77fe36ff DP |
233 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
234 | { | |
739f3abd | 235 | u8 alpm_caps = 0; |
77fe36ff DP |
236 | |
237 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
238 | &alpm_caps) != 1) | |
239 | return false; | |
240 | return alpm_caps & DP_ALPM_CAP; | |
241 | } | |
242 | ||
26e5378d JRS |
243 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
244 | { | |
264ff016 | 245 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
246 | |
247 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
248 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
249 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
250 | else | |
264ff016 | 251 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
252 | return val; |
253 | } | |
254 | ||
8c0d2c29 JRS |
255 | static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) |
256 | { | |
257 | u16 val; | |
258 | ssize_t r; | |
259 | ||
260 | /* | |
261 | * Returning the default X granularity if granularity not required or | |
262 | * if DPCD read fails | |
263 | */ | |
264 | if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) | |
265 | return 4; | |
266 | ||
267 | r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); | |
268 | if (r != 2) | |
269 | DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n"); | |
270 | ||
271 | /* | |
272 | * Spec says that if the value read is 0 the default granularity should | |
273 | * be used instead. | |
274 | */ | |
275 | if (r != 2 || val == 0) | |
276 | val = 4; | |
277 | ||
278 | return val; | |
279 | } | |
280 | ||
77fe36ff DP |
281 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
282 | { | |
283 | struct drm_i915_private *dev_priv = | |
284 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
285 | ||
286 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, | |
287 | sizeof(intel_dp->psr_dpcd)); | |
288 | ||
8cf6da7e DP |
289 | if (!intel_dp->psr_dpcd[0]) |
290 | return; | |
8cf6da7e DP |
291 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
292 | intel_dp->psr_dpcd[0]); | |
84bb2916 | 293 | |
7c5c641a JRS |
294 | if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { |
295 | DRM_DEBUG_KMS("PSR support not currently available for this panel\n"); | |
296 | return; | |
297 | } | |
298 | ||
84bb2916 DP |
299 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
300 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
301 | return; | |
302 | } | |
7c5c641a | 303 | |
8cf6da7e | 304 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
305 | dev_priv->psr.sink_sync_latency = |
306 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 307 | |
c44301fc ML |
308 | WARN_ON(dev_priv->psr.dp); |
309 | dev_priv->psr.dp = intel_dp; | |
310 | ||
77fe36ff | 311 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 312 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
313 | bool y_req = intel_dp->psr_dpcd[1] & |
314 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
315 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
316 | ||
aee3bac0 JRS |
317 | /* |
318 | * All panels that supports PSR version 03h (PSR2 + | |
319 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
320 | * only sure that it is going to be used when required by the | |
321 | * panel. This way panel is capable to do selective update | |
322 | * without a aux frame sync. | |
323 | * | |
324 | * To support PSR version 02h and PSR version 03h without | |
325 | * Y-coordinate requirement panels we would need to enable | |
326 | * GTC first. | |
327 | */ | |
97c9de66 | 328 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
329 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
330 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 331 | |
95f28d2e | 332 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
333 | dev_priv->psr.colorimetry_support = |
334 | intel_dp_get_colorimetry_status(intel_dp); | |
8c0d2c29 JRS |
335 | dev_priv->psr.su_x_granularity = |
336 | intel_dp_get_su_x_granulartiy(intel_dp); | |
77fe36ff DP |
337 | } |
338 | } | |
339 | } | |
340 | ||
cf5d862d RV |
341 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
342 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 343 | { |
97da2ef4 | 344 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 345 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d432f95 | 346 | struct dp_sdp psr_vsc; |
474d1ec4 | 347 | |
95f28d2e | 348 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
349 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
350 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
351 | psr_vsc.sdp_header.HB0 = 0; | |
352 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 353 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
354 | psr_vsc.sdp_header.HB2 = 0x5; |
355 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 356 | } else { |
2ce4df87 RV |
357 | psr_vsc.sdp_header.HB2 = 0x4; |
358 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 359 | } |
97da2ef4 | 360 | } else { |
2ce4df87 RV |
361 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
362 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
363 | psr_vsc.sdp_header.HB0 = 0; | |
364 | psr_vsc.sdp_header.HB1 = 0x7; | |
365 | psr_vsc.sdp_header.HB2 = 0x2; | |
366 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
367 | } |
368 | ||
790ea70c VS |
369 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
370 | crtc_state, | |
1d776538 | 371 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
372 | } |
373 | ||
b90eed08 | 374 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 375 | { |
1895759e | 376 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
377 | u32 aux_clock_divider, aux_ctl; |
378 | int i; | |
739f3abd | 379 | static const u8 aux_msg[] = { |
0bc12bcb RV |
380 | [0] = DP_AUX_NATIVE_WRITE << 4, |
381 | [1] = DP_SET_POWER >> 8, | |
382 | [2] = DP_SET_POWER & 0xff, | |
383 | [3] = 1 - 1, | |
384 | [4] = DP_SET_POWER_D0, | |
385 | }; | |
d544e918 DP |
386 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
387 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
388 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
389 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
390 | |
391 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 392 | for (i = 0; i < sizeof(aux_msg); i += 4) |
4ab4fa10 | 393 | I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), |
b90eed08 DP |
394 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
395 | ||
d544e918 DP |
396 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
397 | ||
398 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 399 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 400 | aux_clock_divider); |
d544e918 DP |
401 | |
402 | /* Select only valid bits for SRD_AUX_CTL */ | |
403 | aux_ctl &= psr_aux_mask; | |
4ab4fa10 | 404 | I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl); |
b90eed08 DP |
405 | } |
406 | ||
cf5d862d | 407 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 408 | { |
1895759e | 409 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 410 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 411 | |
340c93c0 | 412 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
413 | if (dev_priv->psr.psr2_enabled) { |
414 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
415 | DP_ALPM_ENABLE); | |
98751b8c | 416 | dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; |
60cae442 JRS |
417 | } else { |
418 | if (dev_priv->psr.link_standby) | |
419 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; | |
de570946 JRS |
420 | |
421 | if (INTEL_GEN(dev_priv) >= 8) | |
422 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
97c9de66 DP |
423 | } |
424 | ||
4df4925b | 425 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 426 | |
d544e918 | 427 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
428 | } |
429 | ||
1e0c05c0 | 430 | static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) |
0bc12bcb | 431 | { |
1895759e | 432 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1e0c05c0 | 433 | u32 val = 0; |
60e5ffe3 | 434 | |
8a9a5608 JRS |
435 | if (INTEL_GEN(dev_priv) >= 11) |
436 | val |= EDP_PSR_TP4_TIME_0US; | |
437 | ||
77312ae8 | 438 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
1e0c05c0 | 439 | val |= EDP_PSR_TP1_TIME_0us; |
77312ae8 | 440 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) |
50db1390 | 441 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
442 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
443 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 444 | else |
77312ae8 | 445 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 446 | |
77312ae8 | 447 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
1e0c05c0 | 448 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
77312ae8 | 449 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) |
50db1390 | 450 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
451 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
452 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 453 | else |
77312ae8 | 454 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
455 | |
456 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
457 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
458 | val |= EDP_PSR_TP1_TP3_SEL; | |
459 | else | |
460 | val |= EDP_PSR_TP1_TP2_SEL; | |
461 | ||
1e0c05c0 JRS |
462 | return val; |
463 | } | |
464 | ||
465 | static void hsw_activate_psr1(struct intel_dp *intel_dp) | |
466 | { | |
467 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
468 | u32 max_sleep_time = 0x1f; | |
469 | u32 val = EDP_PSR_ENABLE; | |
470 | ||
471 | /* Let's use 6 as the minimum to cover all known cases including the | |
472 | * off-by-one issue that HW has in some cases. | |
473 | */ | |
474 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
475 | ||
476 | /* sink_sync_latency of 8 means source has to wait for more than 8 | |
477 | * frames, we'll go with 9 frames for now | |
478 | */ | |
479 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
480 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
481 | ||
482 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
483 | if (IS_HASWELL(dev_priv)) | |
484 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
485 | ||
486 | if (dev_priv->psr.link_standby) | |
487 | val |= EDP_PSR_LINK_STANDBY; | |
488 | ||
489 | val |= intel_psr1_get_tp_time(intel_dp); | |
490 | ||
00c8f194 JRS |
491 | if (INTEL_GEN(dev_priv) >= 8) |
492 | val |= EDP_PSR_CRC_ENABLE; | |
493 | ||
4ab4fa10 JRS |
494 | val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & |
495 | EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); | |
496 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
3fcb0ca1 | 497 | } |
50db1390 | 498 | |
ed63d24b | 499 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 500 | { |
1895759e | 501 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
502 | u32 val; |
503 | ||
504 | /* Let's use 6 as the minimum to cover all known cases including the | |
505 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 506 | */ |
a3db1428 DP |
507 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
508 | ||
509 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
510 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 | 511 | |
5e87325f | 512 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
513 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
514 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 515 | |
26e5378d | 516 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 517 | |
88a0d960 JRS |
518 | if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && |
519 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) | |
77312ae8 | 520 | val |= EDP_PSR2_TP2_TIME_50us; |
88a0d960 | 521 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) |
77312ae8 | 522 | val |= EDP_PSR2_TP2_TIME_100us; |
88a0d960 | 523 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) |
77312ae8 | 524 | val |= EDP_PSR2_TP2_TIME_500us; |
50db1390 | 525 | else |
77312ae8 | 526 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 527 | |
06dd94cc | 528 | /* |
15b7dae0 JRS |
529 | * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is |
530 | * recommending keep this bit unset while PSR2 is enabled. | |
06dd94cc | 531 | */ |
4ab4fa10 | 532 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0); |
06dd94cc | 533 | |
4ab4fa10 | 534 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); |
0bc12bcb RV |
535 | } |
536 | ||
99fc38b1 JRS |
537 | static bool |
538 | transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) | |
539 | { | |
540 | if (INTEL_GEN(dev_priv) >= 12) | |
541 | return trans == TRANSCODER_A; | |
542 | else | |
543 | return trans == TRANSCODER_EDP; | |
544 | } | |
545 | ||
c4932d79 RV |
546 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
547 | struct intel_crtc_state *crtc_state) | |
548 | { | |
1895759e | 549 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c90c275c DP |
550 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
551 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
552 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 | 553 | |
95f28d2e | 554 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
555 | return false; |
556 | ||
99fc38b1 JRS |
557 | if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { |
558 | DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n", | |
559 | transcoder_name(crtc_state->cpu_transcoder)); | |
560 | return false; | |
561 | } | |
562 | ||
8228c42f MN |
563 | /* |
564 | * DSC and PSR2 cannot be enabled simultaneously. If a requested | |
565 | * resolution requires DSC to be enabled, priority is given to DSC | |
566 | * over PSR2. | |
567 | */ | |
568 | if (crtc_state->dsc_params.compression_enable) { | |
569 | DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); | |
570 | return false; | |
571 | } | |
572 | ||
c90c275c DP |
573 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
574 | psr_max_h = 4096; | |
575 | psr_max_v = 2304; | |
cf819eff | 576 | } else if (IS_GEN(dev_priv, 9)) { |
c90c275c DP |
577 | psr_max_h = 3640; |
578 | psr_max_v = 2304; | |
579 | } | |
580 | ||
581 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
582 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
583 | crtc_hdisplay, crtc_vdisplay, | |
584 | psr_max_h, psr_max_v); | |
c4932d79 RV |
585 | return false; |
586 | } | |
587 | ||
bef5e5b3 JRS |
588 | /* |
589 | * HW sends SU blocks of size four scan lines, which means the starting | |
590 | * X coordinate and Y granularity requirements will always be met. We | |
8c0d2c29 JRS |
591 | * only need to validate the SU block width is a multiple of |
592 | * x granularity. | |
bef5e5b3 | 593 | */ |
8c0d2c29 JRS |
594 | if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { |
595 | DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", | |
596 | crtc_hdisplay, dev_priv->psr.su_x_granularity); | |
bef5e5b3 JRS |
597 | return false; |
598 | } | |
599 | ||
618cf883 JRS |
600 | if (crtc_state->crc_enabled) { |
601 | DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n"); | |
602 | return false; | |
603 | } | |
604 | ||
c4932d79 RV |
605 | return true; |
606 | } | |
607 | ||
4d90f2d5 VS |
608 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
609 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
610 | { |
611 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 612 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 613 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 614 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 615 | int psr_setup_time; |
0bc12bcb | 616 | |
4371d896 | 617 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
618 | return; |
619 | ||
c44301fc | 620 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 621 | return; |
0bc12bcb | 622 | |
dc9b5a0c RV |
623 | /* |
624 | * HSW spec explicitly says PSR is tied to port A. | |
4ab4fa10 JRS |
625 | * BDW+ platforms have a instance of PSR registers per transcoder but |
626 | * for now it only supports one instance of PSR, so lets keep it | |
627 | * hardcoded to PORT_A | |
dc9b5a0c | 628 | */ |
ce3508fd | 629 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 630 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 631 | return; |
0bc12bcb RV |
632 | } |
633 | ||
50a12d8f JRS |
634 | if (dev_priv->psr.sink_not_reliable) { |
635 | DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); | |
636 | return; | |
637 | } | |
638 | ||
7ae6ad6f JRS |
639 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
640 | DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n"); | |
4d90f2d5 | 641 | return; |
0bc12bcb RV |
642 | } |
643 | ||
dfd2e9ab VS |
644 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
645 | if (psr_setup_time < 0) { | |
646 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
647 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 648 | return; |
dfd2e9ab VS |
649 | } |
650 | ||
651 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
652 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
653 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
654 | psr_setup_time); | |
4d90f2d5 VS |
655 | return; |
656 | } | |
657 | ||
4d90f2d5 | 658 | crtc_state->has_psr = true; |
c4932d79 | 659 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
660 | } |
661 | ||
e2bbc343 | 662 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 663 | { |
1895759e | 664 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 665 | |
bcc233b2 | 666 | if (INTEL_GEN(dev_priv) >= 9) |
4ab4fa10 JRS |
667 | WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); |
668 | WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); | |
0bc12bcb RV |
669 | WARN_ON(dev_priv->psr.active); |
670 | lockdep_assert_held(&dev_priv->psr.lock); | |
671 | ||
cf5d862d RV |
672 | /* psr1 and psr2 are mutually exclusive.*/ |
673 | if (dev_priv->psr.psr2_enabled) | |
674 | hsw_activate_psr2(intel_dp); | |
675 | else | |
676 | hsw_activate_psr1(intel_dp); | |
677 | ||
0bc12bcb RV |
678 | dev_priv->psr.active = true; |
679 | } | |
680 | ||
8f19b401 ID |
681 | static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv, |
682 | enum transcoder cpu_transcoder) | |
683 | { | |
684 | static const i915_reg_t regs[] = { | |
685 | [TRANSCODER_A] = CHICKEN_TRANS_A, | |
686 | [TRANSCODER_B] = CHICKEN_TRANS_B, | |
687 | [TRANSCODER_C] = CHICKEN_TRANS_C, | |
688 | [TRANSCODER_EDP] = CHICKEN_TRANS_EDP, | |
689 | }; | |
690 | ||
691 | WARN_ON(INTEL_GEN(dev_priv) < 9); | |
692 | ||
693 | if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) || | |
694 | !regs[cpu_transcoder].reg)) | |
695 | cpu_transcoder = TRANSCODER_A; | |
696 | ||
697 | return regs[cpu_transcoder]; | |
698 | } | |
699 | ||
cf5d862d RV |
700 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
701 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 702 | { |
1895759e | 703 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 704 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 705 | u32 mask; |
4d1fa22f | 706 | |
d544e918 DP |
707 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
708 | * use hardcoded values PSR AUX transactions | |
709 | */ | |
710 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
711 | hsw_psr_setup_aux(intel_dp); | |
712 | ||
cf819eff | 713 | if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && |
d15f9cdd | 714 | !IS_GEMINILAKE(dev_priv))) { |
8f19b401 ID |
715 | i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, |
716 | cpu_transcoder); | |
717 | u32 chicken = I915_READ(reg); | |
5e87325f | 718 | |
d15f9cdd JRS |
719 | chicken |= PSR2_VSC_ENABLE_PROG_HEADER | |
720 | PSR2_ADD_VERTICAL_LINE_COUNT; | |
8f19b401 | 721 | I915_WRITE(reg, chicken); |
4d1fa22f | 722 | } |
bf80928f JRS |
723 | |
724 | /* | |
725 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
726 | * mask LPSP to avoid dependency on other drivers that might block | |
727 | * runtime_pm besides preventing other hw tracking issues now we | |
728 | * can rely on frontbuffer tracking. | |
729 | */ | |
fc6ff9dc JRS |
730 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
731 | EDP_PSR_DEBUG_MASK_HPD | | |
732 | EDP_PSR_DEBUG_MASK_LPSP | | |
733 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
734 | ||
735 | if (INTEL_GEN(dev_priv) < 11) | |
736 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
737 | ||
4ab4fa10 | 738 | I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); |
df7415bf JRS |
739 | |
740 | psr_irq_control(dev_priv, dev_priv->psr.debug); | |
4d1fa22f RV |
741 | } |
742 | ||
c44301fc ML |
743 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
744 | const struct intel_crtc_state *crtc_state) | |
745 | { | |
746 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
4ab4fa10 | 747 | u32 val; |
c44301fc | 748 | |
23ec9f52 JRS |
749 | WARN_ON(dev_priv->psr.enabled); |
750 | ||
751 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
752 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
753 | dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; | |
4ab4fa10 JRS |
754 | dev_priv->psr.transcoder = crtc_state->cpu_transcoder; |
755 | ||
756 | /* | |
757 | * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR | |
758 | * will still keep the error set even after the reset done in the | |
759 | * irq_preinstall and irq_uninstall hooks. | |
760 | * And enabling in this situation cause the screen to freeze in the | |
761 | * first time that PSR HW tries to activate so lets keep PSR disabled | |
762 | * to avoid any rendering problems. | |
763 | */ | |
764 | val = I915_READ(EDP_PSR_IIR); | |
765 | val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder)); | |
766 | if (val) { | |
767 | dev_priv->psr.sink_not_reliable = true; | |
768 | DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n"); | |
769 | return; | |
770 | } | |
c44301fc ML |
771 | |
772 | DRM_DEBUG_KMS("Enabling PSR%s\n", | |
773 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
774 | intel_psr_setup_vsc(intel_dp, crtc_state); | |
775 | intel_psr_enable_sink(intel_dp); | |
776 | intel_psr_enable_source(intel_dp, crtc_state); | |
777 | dev_priv->psr.enabled = true; | |
778 | ||
779 | intel_psr_activate(intel_dp); | |
780 | } | |
781 | ||
b2b89f55 RV |
782 | /** |
783 | * intel_psr_enable - Enable PSR | |
784 | * @intel_dp: Intel DP | |
d2419ffc | 785 | * @crtc_state: new CRTC state |
b2b89f55 RV |
786 | * |
787 | * This function can only be called after the pipe is fully trained and enabled. | |
788 | */ | |
d2419ffc VS |
789 | void intel_psr_enable(struct intel_dp *intel_dp, |
790 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 791 | { |
1895759e | 792 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 793 | |
4d90f2d5 | 794 | if (!crtc_state->has_psr) |
0bc12bcb | 795 | return; |
0bc12bcb | 796 | |
c9ef291a DP |
797 | if (WARN_ON(!CAN_PSR(dev_priv))) |
798 | return; | |
799 | ||
da83ef85 | 800 | WARN_ON(dev_priv->drrs.dp); |
c44301fc | 801 | |
0bc12bcb | 802 | mutex_lock(&dev_priv->psr.lock); |
23ec9f52 JRS |
803 | |
804 | if (!psr_global_enabled(dev_priv->psr.debug)) { | |
805 | DRM_DEBUG_KMS("PSR disabled by flag\n"); | |
0bc12bcb RV |
806 | goto unlock; |
807 | } | |
808 | ||
23ec9f52 | 809 | intel_psr_enable_locked(dev_priv, crtc_state); |
d0ac896a | 810 | |
0bc12bcb RV |
811 | unlock: |
812 | mutex_unlock(&dev_priv->psr.lock); | |
813 | } | |
814 | ||
26f9ec9a JRS |
815 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
816 | { | |
817 | u32 val; | |
818 | ||
b2fc2252 | 819 | if (!dev_priv->psr.active) { |
4ab4fa10 JRS |
820 | if (INTEL_GEN(dev_priv) >= 9) { |
821 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); | |
822 | WARN_ON(val & EDP_PSR2_ENABLE); | |
823 | } | |
824 | ||
825 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); | |
826 | WARN_ON(val & EDP_PSR_ENABLE); | |
827 | ||
26f9ec9a | 828 | return; |
b2fc2252 | 829 | } |
26f9ec9a JRS |
830 | |
831 | if (dev_priv->psr.psr2_enabled) { | |
4ab4fa10 | 832 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 833 | WARN_ON(!(val & EDP_PSR2_ENABLE)); |
4ab4fa10 JRS |
834 | val &= ~EDP_PSR2_ENABLE; |
835 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a | 836 | } else { |
4ab4fa10 | 837 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 838 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
4ab4fa10 JRS |
839 | val &= ~EDP_PSR_ENABLE; |
840 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a JRS |
841 | } |
842 | dev_priv->psr.active = false; | |
843 | } | |
844 | ||
2ee936e3 | 845 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 846 | { |
1895759e | 847 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
848 | i915_reg_t psr_status; |
849 | u32 psr_status_mask; | |
0bc12bcb | 850 | |
2ee936e3 JRS |
851 | lockdep_assert_held(&dev_priv->psr.lock); |
852 | ||
853 | if (!dev_priv->psr.enabled) | |
854 | return; | |
855 | ||
856 | DRM_DEBUG_KMS("Disabling PSR%s\n", | |
857 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
858 | ||
b2fc2252 | 859 | intel_psr_exit(dev_priv); |
77affa31 | 860 | |
b2fc2252 | 861 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 862 | psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 863 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
0bc12bcb | 864 | } else { |
4ab4fa10 | 865 | psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 866 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 867 | } |
b2fc2252 JRS |
868 | |
869 | /* Wait till PSR is idle */ | |
4cb3b44d DCS |
870 | if (intel_de_wait_for_clear(dev_priv, psr_status, |
871 | psr_status_mask, 2000)) | |
b2fc2252 | 872 | DRM_ERROR("Timed out waiting PSR idle state\n"); |
cc3054ff JRS |
873 | |
874 | /* Disable PSR on Sink */ | |
875 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
876 | ||
c44301fc | 877 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
878 | } |
879 | ||
e2bbc343 RV |
880 | /** |
881 | * intel_psr_disable - Disable PSR | |
882 | * @intel_dp: Intel DP | |
d2419ffc | 883 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
884 | * |
885 | * This function needs to be called before disabling pipe. | |
886 | */ | |
d2419ffc VS |
887 | void intel_psr_disable(struct intel_dp *intel_dp, |
888 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 889 | { |
1895759e | 890 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 891 | |
4d90f2d5 | 892 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
893 | return; |
894 | ||
c9ef291a DP |
895 | if (WARN_ON(!CAN_PSR(dev_priv))) |
896 | return; | |
897 | ||
e2bbc343 | 898 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 899 | |
cc3054ff | 900 | intel_psr_disable_locked(intel_dp); |
c44301fc | 901 | |
0bc12bcb | 902 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 903 | cancel_work_sync(&dev_priv->psr.work); |
0bc12bcb RV |
904 | } |
905 | ||
88e05aff JRS |
906 | static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) |
907 | { | |
381f8a20 JRS |
908 | if (INTEL_GEN(dev_priv) >= 9) |
909 | /* | |
910 | * Display WA #0884: skl+ | |
911 | * This documented WA for bxt can be safely applied | |
912 | * broadly so we can force HW tracking to exit PSR | |
913 | * instead of disabling and re-enabling. | |
914 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
915 | * but it makes more sense write to the current active | |
916 | * pipe. | |
917 | */ | |
918 | I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); | |
919 | else | |
920 | /* | |
921 | * A write to CURSURFLIVE do not cause HW tracking to exit PSR | |
922 | * on older gens so doing the manual exit instead. | |
923 | */ | |
924 | intel_psr_exit(dev_priv); | |
88e05aff JRS |
925 | } |
926 | ||
23ec9f52 JRS |
927 | /** |
928 | * intel_psr_update - Update PSR state | |
929 | * @intel_dp: Intel DP | |
930 | * @crtc_state: new CRTC state | |
931 | * | |
932 | * This functions will update PSR states, disabling, enabling or switching PSR | |
933 | * version when executing fastsets. For full modeset, intel_psr_disable() and | |
934 | * intel_psr_enable() should be called instead. | |
935 | */ | |
936 | void intel_psr_update(struct intel_dp *intel_dp, | |
937 | const struct intel_crtc_state *crtc_state) | |
938 | { | |
939 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
940 | struct i915_psr *psr = &dev_priv->psr; | |
941 | bool enable, psr2_enable; | |
942 | ||
943 | if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) | |
944 | return; | |
945 | ||
946 | mutex_lock(&dev_priv->psr.lock); | |
947 | ||
948 | enable = crtc_state->has_psr && psr_global_enabled(psr->debug); | |
949 | psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); | |
950 | ||
88e05aff JRS |
951 | if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { |
952 | /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ | |
953 | if (crtc_state->crc_enabled && psr->enabled) | |
954 | psr_force_hw_tracking_exit(dev_priv); | |
381f8a20 JRS |
955 | else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { |
956 | /* | |
957 | * Activate PSR again after a force exit when enabling | |
958 | * CRC in older gens | |
959 | */ | |
960 | if (!dev_priv->psr.active && | |
961 | !dev_priv->psr.busy_frontbuffer_bits) | |
962 | schedule_work(&dev_priv->psr.work); | |
963 | } | |
88e05aff | 964 | |
23ec9f52 | 965 | goto unlock; |
88e05aff | 966 | } |
23ec9f52 | 967 | |
9f952664 JRS |
968 | if (psr->enabled) |
969 | intel_psr_disable_locked(intel_dp); | |
23ec9f52 | 970 | |
9f952664 JRS |
971 | if (enable) |
972 | intel_psr_enable_locked(dev_priv, crtc_state); | |
23ec9f52 JRS |
973 | |
974 | unlock: | |
975 | mutex_unlock(&dev_priv->psr.lock); | |
976 | } | |
977 | ||
65df9c79 DP |
978 | /** |
979 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
980 | * @new_crtc_state: new CRTC state | |
981 | * @out_value: PSR status in case of failure | |
982 | * | |
983 | * This function is expected to be called from pipe_update_start() where it is | |
984 | * not expected to race with PSR enable or disable. | |
985 | * | |
986 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
987 | */ | |
63ec132d DP |
988 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
989 | u32 *out_value) | |
c43dbcbb | 990 | { |
c3d43361 TV |
991 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
992 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
c43dbcbb | 993 | |
c44301fc | 994 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
995 | return 0; |
996 | ||
fd255f6e DP |
997 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
998 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
999 | return 0; | |
c43dbcbb TV |
1000 | |
1001 | /* | |
65df9c79 DP |
1002 | * From bspec: Panel Self Refresh (BDW+) |
1003 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
1004 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
1005 | * defensive enough to cover everything. | |
c43dbcbb | 1006 | */ |
63ec132d | 1007 | |
4ab4fa10 JRS |
1008 | return __intel_wait_for_register(&dev_priv->uncore, |
1009 | EDP_PSR_STATUS(dev_priv->psr.transcoder), | |
fd255f6e | 1010 | EDP_PSR_STATUS_STATE_MASK, |
63ec132d DP |
1011 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
1012 | out_value); | |
c43dbcbb TV |
1013 | } |
1014 | ||
1015 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 1016 | { |
daeb725e CW |
1017 | i915_reg_t reg; |
1018 | u32 mask; | |
1019 | int err; | |
1020 | ||
c44301fc | 1021 | if (!dev_priv->psr.enabled) |
daeb725e | 1022 | return false; |
0bc12bcb | 1023 | |
ce3508fd | 1024 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 1025 | reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1026 | mask = EDP_PSR2_STATUS_STATE_MASK; |
995d3047 | 1027 | } else { |
4ab4fa10 | 1028 | reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1029 | mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 1030 | } |
daeb725e CW |
1031 | |
1032 | mutex_unlock(&dev_priv->psr.lock); | |
1033 | ||
4cb3b44d | 1034 | err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); |
daeb725e CW |
1035 | if (err) |
1036 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
1037 | ||
1038 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 1039 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
1040 | return err == 0 && dev_priv->psr.enabled; |
1041 | } | |
0bc12bcb | 1042 | |
23ec9f52 | 1043 | static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) |
2ac45bdd | 1044 | { |
23ec9f52 JRS |
1045 | struct drm_device *dev = &dev_priv->drm; |
1046 | struct drm_modeset_acquire_ctx ctx; | |
1047 | struct drm_atomic_state *state; | |
1048 | struct drm_crtc *crtc; | |
1049 | int err; | |
2ac45bdd | 1050 | |
23ec9f52 JRS |
1051 | state = drm_atomic_state_alloc(dev); |
1052 | if (!state) | |
1053 | return -ENOMEM; | |
2ac45bdd | 1054 | |
23ec9f52 JRS |
1055 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
1056 | state->acquire_ctx = &ctx; | |
1057 | ||
1058 | retry: | |
1059 | drm_for_each_crtc(crtc, dev) { | |
1060 | struct drm_crtc_state *crtc_state; | |
1061 | struct intel_crtc_state *intel_crtc_state; | |
1062 | ||
1063 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
1064 | if (IS_ERR(crtc_state)) { | |
1065 | err = PTR_ERR(crtc_state); | |
1066 | goto error; | |
1067 | } | |
1068 | ||
1069 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
1070 | ||
458e0977 | 1071 | if (crtc_state->active && intel_crtc_state->has_psr) { |
23ec9f52 JRS |
1072 | /* Mark mode as changed to trigger a pipe->update() */ |
1073 | crtc_state->mode_changed = true; | |
1074 | break; | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | err = drm_atomic_commit(state); | |
2ac45bdd | 1079 | |
23ec9f52 JRS |
1080 | error: |
1081 | if (err == -EDEADLK) { | |
1082 | drm_atomic_state_clear(state); | |
1083 | err = drm_modeset_backoff(&ctx); | |
1084 | if (!err) | |
1085 | goto retry; | |
1086 | } | |
1087 | ||
1088 | drm_modeset_drop_locks(&ctx); | |
1089 | drm_modeset_acquire_fini(&ctx); | |
1090 | drm_atomic_state_put(state); | |
1091 | ||
1092 | return err; | |
2ac45bdd ML |
1093 | } |
1094 | ||
23ec9f52 | 1095 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) |
c44301fc | 1096 | { |
23ec9f52 JRS |
1097 | const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
1098 | u32 old_mode; | |
c44301fc | 1099 | int ret; |
c44301fc ML |
1100 | |
1101 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 1102 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
c44301fc ML |
1103 | DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); |
1104 | return -EINVAL; | |
1105 | } | |
1106 | ||
c44301fc ML |
1107 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); |
1108 | if (ret) | |
1109 | return ret; | |
1110 | ||
23ec9f52 | 1111 | old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; |
c44301fc | 1112 | dev_priv->psr.debug = val; |
df7415bf | 1113 | psr_irq_control(dev_priv, dev_priv->psr.debug); |
c44301fc | 1114 | |
c44301fc | 1115 | mutex_unlock(&dev_priv->psr.lock); |
23ec9f52 JRS |
1116 | |
1117 | if (old_mode != mode) | |
1118 | ret = intel_psr_fastset_force(dev_priv); | |
1119 | ||
c44301fc ML |
1120 | return ret; |
1121 | } | |
1122 | ||
183b8e67 JRS |
1123 | static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) |
1124 | { | |
1125 | struct i915_psr *psr = &dev_priv->psr; | |
1126 | ||
1127 | intel_psr_disable_locked(psr->dp); | |
1128 | psr->sink_not_reliable = true; | |
1129 | /* let's make sure that sink is awaken */ | |
1130 | drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); | |
1131 | } | |
1132 | ||
daeb725e CW |
1133 | static void intel_psr_work(struct work_struct *work) |
1134 | { | |
1135 | struct drm_i915_private *dev_priv = | |
5422b37c | 1136 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
1137 | |
1138 | mutex_lock(&dev_priv->psr.lock); | |
1139 | ||
5422b37c RV |
1140 | if (!dev_priv->psr.enabled) |
1141 | goto unlock; | |
1142 | ||
183b8e67 JRS |
1143 | if (READ_ONCE(dev_priv->psr.irq_aux_error)) |
1144 | intel_psr_handle_irq(dev_priv); | |
1145 | ||
daeb725e CW |
1146 | /* |
1147 | * We have to make sure PSR is ready for re-enable | |
1148 | * otherwise it keeps disabled until next full enable/disable cycle. | |
1149 | * PSR might take some time to get fully disabled | |
1150 | * and be ready for re-enable. | |
1151 | */ | |
c43dbcbb | 1152 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
1153 | goto unlock; |
1154 | ||
1155 | /* | |
1156 | * The delayed work can race with an invalidate hence we need to | |
1157 | * recheck. Since psr_flush first clears this and then reschedules we | |
1158 | * won't ever miss a flush when bailing out here. | |
1159 | */ | |
c12e0643 | 1160 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
1161 | goto unlock; |
1162 | ||
c44301fc | 1163 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
1164 | unlock: |
1165 | mutex_unlock(&dev_priv->psr.lock); | |
1166 | } | |
1167 | ||
b2b89f55 RV |
1168 | /** |
1169 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 1170 | * @dev_priv: i915 device |
b2b89f55 | 1171 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 1172 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
1173 | * |
1174 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1175 | * with the software frontbuffer tracking. This function gets called every | |
1176 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
1177 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
1178 | * | |
1179 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
1180 | */ | |
5748b6a1 | 1181 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 1182 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1183 | { |
4371d896 | 1184 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1185 | return; |
1186 | ||
ce3508fd | 1187 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1188 | return; |
1189 | ||
0bc12bcb RV |
1190 | mutex_lock(&dev_priv->psr.lock); |
1191 | if (!dev_priv->psr.enabled) { | |
1192 | mutex_unlock(&dev_priv->psr.lock); | |
1193 | return; | |
1194 | } | |
1195 | ||
f0ad62a6 | 1196 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb | 1197 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
1198 | |
1199 | if (frontbuffer_bits) | |
5748b6a1 | 1200 | intel_psr_exit(dev_priv); |
ec76d629 | 1201 | |
0bc12bcb RV |
1202 | mutex_unlock(&dev_priv->psr.lock); |
1203 | } | |
1204 | ||
b2b89f55 RV |
1205 | /** |
1206 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 1207 | * @dev_priv: i915 device |
b2b89f55 | 1208 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 1209 | * @origin: which operation caused the flush |
b2b89f55 RV |
1210 | * |
1211 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1212 | * with the software frontbuffer tracking. This function gets called every | |
1213 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
1214 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
1215 | * | |
1216 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
1217 | */ | |
5748b6a1 | 1218 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 1219 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1220 | { |
4371d896 | 1221 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1222 | return; |
1223 | ||
ce3508fd | 1224 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1225 | return; |
1226 | ||
0bc12bcb RV |
1227 | mutex_lock(&dev_priv->psr.lock); |
1228 | if (!dev_priv->psr.enabled) { | |
1229 | mutex_unlock(&dev_priv->psr.lock); | |
1230 | return; | |
1231 | } | |
1232 | ||
f0ad62a6 | 1233 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb RV |
1234 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1235 | ||
921ec285 | 1236 | /* By definition flush = invalidate + flush */ |
88e05aff JRS |
1237 | if (frontbuffer_bits) |
1238 | psr_force_hw_tracking_exit(dev_priv); | |
995d3047 | 1239 | |
0bc12bcb | 1240 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1241 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1242 | mutex_unlock(&dev_priv->psr.lock); |
1243 | } | |
1244 | ||
b2b89f55 RV |
1245 | /** |
1246 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1247 | * @dev_priv: i915 device private |
b2b89f55 RV |
1248 | * |
1249 | * This function is called only once at driver load to initialize basic | |
1250 | * PSR stuff. | |
1251 | */ | |
c39055b0 | 1252 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1253 | { |
0f328da6 RV |
1254 | if (!HAS_PSR(dev_priv)) |
1255 | return; | |
1256 | ||
c9ef291a DP |
1257 | if (!dev_priv->psr.sink_support) |
1258 | return; | |
1259 | ||
4ab4fa10 JRS |
1260 | if (IS_HASWELL(dev_priv)) |
1261 | /* | |
1262 | * HSW don't have PSR registers on the same space as transcoder | |
1263 | * so set this to a value that when subtract to the register | |
1264 | * in transcoder space results in the right offset for HSW | |
1265 | */ | |
1266 | dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; | |
1267 | ||
598c6cfe DP |
1268 | if (i915_modparams.enable_psr == -1) |
1269 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1270 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1271 | |
65f61b42 | 1272 | /* Set link_standby x link_off defaults */ |
8652744b | 1273 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1274 | /* HSW and BDW require workarounds that we don't implement. */ |
1275 | dev_priv->psr.link_standby = false; | |
60e5ffe3 RV |
1276 | else |
1277 | /* For new platforms let's respect VBT back again */ | |
1278 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
1279 | ||
5422b37c | 1280 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
0bc12bcb RV |
1281 | mutex_init(&dev_priv->psr.lock); |
1282 | } | |
cc3054ff JRS |
1283 | |
1284 | void intel_psr_short_pulse(struct intel_dp *intel_dp) | |
1285 | { | |
1895759e | 1286 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff JRS |
1287 | struct i915_psr *psr = &dev_priv->psr; |
1288 | u8 val; | |
93bf76ed | 1289 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1290 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1291 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1292 | |
1293 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1294 | return; | |
1295 | ||
1296 | mutex_lock(&psr->lock); | |
1297 | ||
c44301fc | 1298 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1299 | goto exit; |
1300 | ||
1301 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { | |
1302 | DRM_ERROR("PSR_STATUS dpcd read failed\n"); | |
1303 | goto exit; | |
1304 | } | |
1305 | ||
1306 | if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { | |
1307 | DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); | |
1308 | intel_psr_disable_locked(intel_dp); | |
50a12d8f | 1309 | psr->sink_not_reliable = true; |
cc3054ff JRS |
1310 | } |
1311 | ||
93bf76ed JRS |
1312 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { |
1313 | DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n"); | |
1314 | goto exit; | |
1315 | } | |
1316 | ||
1317 | if (val & DP_PSR_RFB_STORAGE_ERROR) | |
1318 | DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); | |
1319 | if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) | |
1320 | DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
00c8f194 JRS |
1321 | if (val & DP_PSR_LINK_CRC_ERROR) |
1322 | DRM_ERROR("PSR Link CRC error, disabling PSR\n"); | |
93bf76ed JRS |
1323 | |
1324 | if (val & ~errors) | |
1325 | DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", | |
1326 | val & ~errors); | |
50a12d8f | 1327 | if (val & errors) { |
93bf76ed | 1328 | intel_psr_disable_locked(intel_dp); |
50a12d8f JRS |
1329 | psr->sink_not_reliable = true; |
1330 | } | |
93bf76ed JRS |
1331 | /* clear status register */ |
1332 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); | |
cc3054ff JRS |
1333 | exit: |
1334 | mutex_unlock(&psr->lock); | |
1335 | } | |
2f8e7ea9 JRS |
1336 | |
1337 | bool intel_psr_enabled(struct intel_dp *intel_dp) | |
1338 | { | |
1339 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1340 | bool ret; | |
1341 | ||
1342 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1343 | return false; | |
1344 | ||
1345 | mutex_lock(&dev_priv->psr.lock); | |
1346 | ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); | |
1347 | mutex_unlock(&dev_priv->psr.lock); | |
1348 | ||
1349 | return ret; | |
1350 | } |