]>
Commit | Line | Data |
---|---|---|
0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
55367a27 JN |
24 | #include <drm/drm_atomic_helper.h> |
25 | ||
379bc100 JN |
26 | #include "display/intel_dp.h" |
27 | ||
55367a27 | 28 | #include "i915_drv.h" |
1d455f8d | 29 | #include "intel_display_types.h" |
55367a27 | 30 | #include "intel_psr.h" |
f9a79f9a | 31 | #include "intel_sprite.h" |
55367a27 | 32 | |
b2b89f55 RV |
33 | /** |
34 | * DOC: Panel Self Refresh (PSR/SRD) | |
35 | * | |
36 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
37 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
38 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
39 | * when system is idle but display is on as it eliminates display refresh | |
40 | * request to DDR memory completely as long as the frame buffer for that | |
41 | * display is unchanged. | |
42 | * | |
43 | * Panel Self Refresh must be supported by both Hardware (source) and | |
44 | * Panel (sink). | |
45 | * | |
46 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
47 | * to power down the link and memory controller. For DSI panels the same idea | |
48 | * is called "manual mode". | |
49 | * | |
50 | * The implementation uses the hardware-based PSR support which automatically | |
51 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
52 | * required DP aux message and could even retrain the link (that part isn't | |
53 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
54 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
55 | * part doesn't work too well, hence why the i915 PSR support uses the | |
56 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
57 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
58 | * get called by the frontbuffer tracking code. Note that because of locking | |
59 | * issues the self-refresh re-enable code is done from a work queue, which | |
60 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
61 | */ | |
62 | ||
c44301fc ML |
63 | static bool psr_global_enabled(u32 debug) |
64 | { | |
65 | switch (debug & I915_PSR_DEBUG_MODE_MASK) { | |
66 | case I915_PSR_DEBUG_DEFAULT: | |
67 | return i915_modparams.enable_psr; | |
68 | case I915_PSR_DEBUG_DISABLE: | |
69 | return false; | |
70 | default: | |
71 | return true; | |
72 | } | |
73 | } | |
74 | ||
2ac45bdd ML |
75 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
76 | const struct intel_crtc_state *crtc_state) | |
77 | { | |
8228c42f | 78 | /* Cannot enable DSC and PSR2 simultaneously */ |
010663a6 | 79 | WARN_ON(crtc_state->dsc.compression_enable && |
8228c42f MN |
80 | crtc_state->has_psr2); |
81 | ||
2ac45bdd | 82 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
235ca26f | 83 | case I915_PSR_DEBUG_DISABLE: |
2ac45bdd ML |
84 | case I915_PSR_DEBUG_FORCE_PSR1: |
85 | return false; | |
86 | default: | |
87 | return crtc_state->has_psr2; | |
88 | } | |
89 | } | |
90 | ||
2f3b8712 | 91 | static void psr_irq_control(struct drm_i915_private *dev_priv) |
c0871805 | 92 | { |
8241cfbe JRS |
93 | enum transcoder trans_shift; |
94 | u32 mask, val; | |
95 | i915_reg_t imr_reg; | |
2f3b8712 | 96 | |
8241cfbe JRS |
97 | /* |
98 | * gen12+ has registers relative to transcoder and one per transcoder | |
99 | * using the same bit definition: handle it as TRANSCODER_EDP to force | |
100 | * 0 shift in bit definition | |
101 | */ | |
102 | if (INTEL_GEN(dev_priv) >= 12) { | |
103 | trans_shift = 0; | |
104 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
105 | } else { | |
106 | trans_shift = dev_priv->psr.transcoder; | |
107 | imr_reg = EDP_PSR_IMR; | |
108 | } | |
109 | ||
110 | mask = EDP_PSR_ERROR(trans_shift); | |
2f3b8712 | 111 | if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) |
8241cfbe JRS |
112 | mask |= EDP_PSR_POST_EXIT(trans_shift) | |
113 | EDP_PSR_PRE_ENTRY(trans_shift); | |
2f3b8712 JRS |
114 | |
115 | /* Warning: it is masking/setting reserved bits too */ | |
8241cfbe JRS |
116 | val = I915_READ(imr_reg); |
117 | val &= ~EDP_PSR_TRANS_MASK(trans_shift); | |
2f3b8712 | 118 | val |= ~mask; |
8241cfbe | 119 | I915_WRITE(imr_reg, val); |
54fd3149 DP |
120 | } |
121 | ||
bc18b4df JRS |
122 | static void psr_event_print(u32 val, bool psr2_enabled) |
123 | { | |
124 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
125 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
126 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
127 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
128 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
129 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
130 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
131 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
132 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
133 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
134 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
135 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
136 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
137 | if (val & PSR_EVENT_MEMORY_UP) | |
138 | DRM_DEBUG_KMS("\tMemory up\n"); | |
139 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
140 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
141 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
142 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
143 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
144 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
145 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
146 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
147 | if (val & PSR_EVENT_HDCP_ENABLE) | |
148 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
149 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
150 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
151 | if (val & PSR_EVENT_VBI_ENABLE) | |
152 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
153 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
154 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
155 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
156 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
157 | } | |
158 | ||
54fd3149 DP |
159 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
160 | { | |
2f3b8712 | 161 | enum transcoder cpu_transcoder = dev_priv->psr.transcoder; |
8241cfbe JRS |
162 | enum transcoder trans_shift; |
163 | i915_reg_t imr_reg; | |
3f983e54 | 164 | ktime_t time_ns = ktime_get(); |
c0871805 | 165 | |
8241cfbe JRS |
166 | if (INTEL_GEN(dev_priv) >= 12) { |
167 | trans_shift = 0; | |
168 | imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); | |
169 | } else { | |
170 | trans_shift = dev_priv->psr.transcoder; | |
171 | imr_reg = EDP_PSR_IMR; | |
172 | } | |
173 | ||
174 | if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { | |
2f3b8712 JRS |
175 | dev_priv->psr.last_entry_attempt = time_ns; |
176 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", | |
177 | transcoder_name(cpu_transcoder)); | |
178 | } | |
183b8e67 | 179 | |
8241cfbe | 180 | if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { |
2f3b8712 JRS |
181 | dev_priv->psr.last_exit = time_ns; |
182 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", | |
183 | transcoder_name(cpu_transcoder)); | |
183b8e67 | 184 | |
2f3b8712 JRS |
185 | if (INTEL_GEN(dev_priv) >= 9) { |
186 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
187 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
54fd3149 | 188 | |
2f3b8712 JRS |
189 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); |
190 | psr_event_print(val, psr2_enabled); | |
3f983e54 | 191 | } |
2f3b8712 | 192 | } |
54fd3149 | 193 | |
8241cfbe | 194 | if (psr_iir & EDP_PSR_ERROR(trans_shift)) { |
2f3b8712 | 195 | u32 val; |
bc18b4df | 196 | |
2f3b8712 JRS |
197 | DRM_WARN("[transcoder %s] PSR aux error\n", |
198 | transcoder_name(cpu_transcoder)); | |
bc18b4df | 199 | |
2f3b8712 | 200 | dev_priv->psr.irq_aux_error = true; |
183b8e67 | 201 | |
2f3b8712 JRS |
202 | /* |
203 | * If this interruption is not masked it will keep | |
204 | * interrupting so fast that it prevents the scheduled | |
205 | * work to run. | |
206 | * Also after a PSR error, we don't want to arm PSR | |
207 | * again so we don't care about unmask the interruption | |
208 | * or unset irq_aux_error. | |
209 | */ | |
8241cfbe JRS |
210 | val = I915_READ(imr_reg); |
211 | val |= EDP_PSR_ERROR(trans_shift); | |
212 | I915_WRITE(imr_reg, val); | |
183b8e67 JRS |
213 | |
214 | schedule_work(&dev_priv->psr.work); | |
215 | } | |
54fd3149 DP |
216 | } |
217 | ||
77fe36ff DP |
218 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
219 | { | |
739f3abd | 220 | u8 alpm_caps = 0; |
77fe36ff DP |
221 | |
222 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
223 | &alpm_caps) != 1) | |
224 | return false; | |
225 | return alpm_caps & DP_ALPM_CAP; | |
226 | } | |
227 | ||
26e5378d JRS |
228 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
229 | { | |
264ff016 | 230 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
231 | |
232 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
233 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
234 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
235 | else | |
264ff016 | 236 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
237 | return val; |
238 | } | |
239 | ||
8c0d2c29 JRS |
240 | static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) |
241 | { | |
242 | u16 val; | |
243 | ssize_t r; | |
244 | ||
245 | /* | |
246 | * Returning the default X granularity if granularity not required or | |
247 | * if DPCD read fails | |
248 | */ | |
249 | if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) | |
250 | return 4; | |
251 | ||
252 | r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); | |
253 | if (r != 2) | |
254 | DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n"); | |
255 | ||
256 | /* | |
257 | * Spec says that if the value read is 0 the default granularity should | |
258 | * be used instead. | |
259 | */ | |
260 | if (r != 2 || val == 0) | |
261 | val = 4; | |
262 | ||
263 | return val; | |
264 | } | |
265 | ||
77fe36ff DP |
266 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
267 | { | |
268 | struct drm_i915_private *dev_priv = | |
269 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
270 | ||
6056517a JRS |
271 | if (dev_priv->psr.dp) { |
272 | DRM_WARN("More than one eDP panel found, PSR support should be extended\n"); | |
273 | return; | |
274 | } | |
275 | ||
77fe36ff DP |
276 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, |
277 | sizeof(intel_dp->psr_dpcd)); | |
278 | ||
8cf6da7e DP |
279 | if (!intel_dp->psr_dpcd[0]) |
280 | return; | |
8cf6da7e DP |
281 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
282 | intel_dp->psr_dpcd[0]); | |
84bb2916 | 283 | |
7c5c641a JRS |
284 | if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { |
285 | DRM_DEBUG_KMS("PSR support not currently available for this panel\n"); | |
286 | return; | |
287 | } | |
288 | ||
84bb2916 DP |
289 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
290 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
291 | return; | |
292 | } | |
7c5c641a | 293 | |
8cf6da7e | 294 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
295 | dev_priv->psr.sink_sync_latency = |
296 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 297 | |
c44301fc ML |
298 | dev_priv->psr.dp = intel_dp; |
299 | ||
77fe36ff | 300 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 301 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
302 | bool y_req = intel_dp->psr_dpcd[1] & |
303 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
304 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
305 | ||
aee3bac0 JRS |
306 | /* |
307 | * All panels that supports PSR version 03h (PSR2 + | |
308 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
309 | * only sure that it is going to be used when required by the | |
310 | * panel. This way panel is capable to do selective update | |
311 | * without a aux frame sync. | |
312 | * | |
313 | * To support PSR version 02h and PSR version 03h without | |
314 | * Y-coordinate requirement panels we would need to enable | |
315 | * GTC first. | |
316 | */ | |
97c9de66 | 317 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
318 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
319 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 320 | |
95f28d2e | 321 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
322 | dev_priv->psr.colorimetry_support = |
323 | intel_dp_get_colorimetry_status(intel_dp); | |
8c0d2c29 JRS |
324 | dev_priv->psr.su_x_granularity = |
325 | intel_dp_get_su_x_granulartiy(intel_dp); | |
77fe36ff DP |
326 | } |
327 | } | |
328 | } | |
329 | ||
cf5d862d RV |
330 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
331 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 332 | { |
97da2ef4 | 333 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 334 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d432f95 | 335 | struct dp_sdp psr_vsc; |
474d1ec4 | 336 | |
95f28d2e | 337 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
338 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
339 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
340 | psr_vsc.sdp_header.HB0 = 0; | |
341 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 342 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
343 | psr_vsc.sdp_header.HB2 = 0x5; |
344 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 345 | } else { |
2ce4df87 RV |
346 | psr_vsc.sdp_header.HB2 = 0x4; |
347 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 348 | } |
97da2ef4 | 349 | } else { |
2ce4df87 RV |
350 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
351 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
352 | psr_vsc.sdp_header.HB0 = 0; | |
353 | psr_vsc.sdp_header.HB1 = 0x7; | |
354 | psr_vsc.sdp_header.HB2 = 0x2; | |
355 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
356 | } |
357 | ||
790ea70c VS |
358 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
359 | crtc_state, | |
1d776538 | 360 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
361 | } |
362 | ||
b90eed08 | 363 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 364 | { |
1895759e | 365 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
366 | u32 aux_clock_divider, aux_ctl; |
367 | int i; | |
739f3abd | 368 | static const u8 aux_msg[] = { |
0bc12bcb RV |
369 | [0] = DP_AUX_NATIVE_WRITE << 4, |
370 | [1] = DP_SET_POWER >> 8, | |
371 | [2] = DP_SET_POWER & 0xff, | |
372 | [3] = 1 - 1, | |
373 | [4] = DP_SET_POWER_D0, | |
374 | }; | |
d544e918 DP |
375 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
376 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
377 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
378 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
379 | |
380 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 381 | for (i = 0; i < sizeof(aux_msg); i += 4) |
4ab4fa10 | 382 | I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), |
b90eed08 DP |
383 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
384 | ||
d544e918 DP |
385 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
386 | ||
387 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 388 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 389 | aux_clock_divider); |
d544e918 DP |
390 | |
391 | /* Select only valid bits for SRD_AUX_CTL */ | |
392 | aux_ctl &= psr_aux_mask; | |
4ab4fa10 | 393 | I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl); |
b90eed08 DP |
394 | } |
395 | ||
cf5d862d | 396 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 397 | { |
1895759e | 398 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 399 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 400 | |
340c93c0 | 401 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
402 | if (dev_priv->psr.psr2_enabled) { |
403 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
404 | DP_ALPM_ENABLE); | |
98751b8c | 405 | dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; |
60cae442 JRS |
406 | } else { |
407 | if (dev_priv->psr.link_standby) | |
408 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; | |
de570946 JRS |
409 | |
410 | if (INTEL_GEN(dev_priv) >= 8) | |
411 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
97c9de66 DP |
412 | } |
413 | ||
4df4925b | 414 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 415 | |
d544e918 | 416 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
417 | } |
418 | ||
1e0c05c0 | 419 | static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) |
0bc12bcb | 420 | { |
1895759e | 421 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1e0c05c0 | 422 | u32 val = 0; |
60e5ffe3 | 423 | |
8a9a5608 JRS |
424 | if (INTEL_GEN(dev_priv) >= 11) |
425 | val |= EDP_PSR_TP4_TIME_0US; | |
426 | ||
77312ae8 | 427 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
1e0c05c0 | 428 | val |= EDP_PSR_TP1_TIME_0us; |
77312ae8 | 429 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) |
50db1390 | 430 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
431 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
432 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 433 | else |
77312ae8 | 434 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 435 | |
77312ae8 | 436 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
1e0c05c0 | 437 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
77312ae8 | 438 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) |
50db1390 | 439 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
440 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
441 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 442 | else |
77312ae8 | 443 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
444 | |
445 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
446 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
447 | val |= EDP_PSR_TP1_TP3_SEL; | |
448 | else | |
449 | val |= EDP_PSR_TP1_TP2_SEL; | |
450 | ||
1e0c05c0 JRS |
451 | return val; |
452 | } | |
453 | ||
454 | static void hsw_activate_psr1(struct intel_dp *intel_dp) | |
455 | { | |
456 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
457 | u32 max_sleep_time = 0x1f; | |
458 | u32 val = EDP_PSR_ENABLE; | |
459 | ||
460 | /* Let's use 6 as the minimum to cover all known cases including the | |
461 | * off-by-one issue that HW has in some cases. | |
462 | */ | |
463 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
464 | ||
465 | /* sink_sync_latency of 8 means source has to wait for more than 8 | |
466 | * frames, we'll go with 9 frames for now | |
467 | */ | |
468 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
469 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
470 | ||
471 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
472 | if (IS_HASWELL(dev_priv)) | |
473 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; | |
474 | ||
475 | if (dev_priv->psr.link_standby) | |
476 | val |= EDP_PSR_LINK_STANDBY; | |
477 | ||
478 | val |= intel_psr1_get_tp_time(intel_dp); | |
479 | ||
00c8f194 JRS |
480 | if (INTEL_GEN(dev_priv) >= 8) |
481 | val |= EDP_PSR_CRC_ENABLE; | |
482 | ||
4ab4fa10 JRS |
483 | val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & |
484 | EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); | |
485 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
3fcb0ca1 | 486 | } |
50db1390 | 487 | |
ed63d24b | 488 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 489 | { |
1895759e | 490 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
491 | u32 val; |
492 | ||
493 | /* Let's use 6 as the minimum to cover all known cases including the | |
494 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 495 | */ |
a3db1428 DP |
496 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
497 | ||
498 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
499 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 | 500 | |
5e87325f | 501 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
502 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
503 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 504 | |
26e5378d | 505 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 506 | |
88a0d960 JRS |
507 | if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && |
508 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) | |
77312ae8 | 509 | val |= EDP_PSR2_TP2_TIME_50us; |
88a0d960 | 510 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) |
77312ae8 | 511 | val |= EDP_PSR2_TP2_TIME_100us; |
88a0d960 | 512 | else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) |
77312ae8 | 513 | val |= EDP_PSR2_TP2_TIME_500us; |
50db1390 | 514 | else |
77312ae8 | 515 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 516 | |
06dd94cc | 517 | /* |
15b7dae0 JRS |
518 | * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is |
519 | * recommending keep this bit unset while PSR2 is enabled. | |
06dd94cc | 520 | */ |
4ab4fa10 | 521 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0); |
06dd94cc | 522 | |
4ab4fa10 | 523 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); |
0bc12bcb RV |
524 | } |
525 | ||
99fc38b1 JRS |
526 | static bool |
527 | transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) | |
528 | { | |
0f81e645 JRS |
529 | if (INTEL_GEN(dev_priv) < 9) |
530 | return false; | |
531 | else if (INTEL_GEN(dev_priv) >= 12) | |
99fc38b1 JRS |
532 | return trans == TRANSCODER_A; |
533 | else | |
534 | return trans == TRANSCODER_EDP; | |
535 | } | |
536 | ||
1c4d821d AG |
537 | static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) |
538 | { | |
539 | if (!cstate || !cstate->base.active) | |
540 | return 0; | |
541 | ||
542 | return DIV_ROUND_UP(1000 * 1000, | |
543 | drm_mode_vrefresh(&cstate->base.adjusted_mode)); | |
544 | } | |
545 | ||
546 | static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, | |
547 | u32 idle_frames) | |
548 | { | |
549 | u32 val; | |
550 | ||
551 | idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; | |
552 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); | |
553 | val &= ~EDP_PSR2_IDLE_FRAME_MASK; | |
554 | val |= idle_frames; | |
555 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
556 | } | |
557 | ||
558 | static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) | |
559 | { | |
560 | psr2_program_idle_frames(dev_priv, 0); | |
561 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); | |
562 | } | |
563 | ||
564 | static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) | |
565 | { | |
566 | int idle_frames; | |
567 | ||
568 | intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); | |
569 | /* | |
570 | * Restore PSR2 idle frame let's use 6 as the minimum to cover all known | |
571 | * cases including the off-by-one issue that HW has in some cases. | |
572 | */ | |
573 | idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
574 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
575 | psr2_program_idle_frames(dev_priv, idle_frames); | |
576 | } | |
577 | ||
578 | static void tgl_dc5_idle_thread(struct work_struct *work) | |
579 | { | |
580 | struct drm_i915_private *dev_priv = | |
581 | container_of(work, typeof(*dev_priv), psr.idle_work.work); | |
582 | ||
583 | mutex_lock(&dev_priv->psr.lock); | |
584 | /* If delayed work is pending, it is not idle */ | |
585 | if (delayed_work_pending(&dev_priv->psr.idle_work)) | |
586 | goto unlock; | |
587 | ||
588 | DRM_DEBUG_KMS("DC5/6 idle thread\n"); | |
589 | tgl_psr2_disable_dc3co(dev_priv); | |
590 | unlock: | |
591 | mutex_unlock(&dev_priv->psr.lock); | |
592 | } | |
593 | ||
594 | static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) | |
595 | { | |
596 | if (!dev_priv->psr.dc3co_enabled) | |
597 | return; | |
598 | ||
599 | cancel_delayed_work(&dev_priv->psr.idle_work); | |
600 | /* Before PSR2 exit disallow dc3co*/ | |
601 | tgl_psr2_disable_dc3co(dev_priv); | |
602 | } | |
603 | ||
c4932d79 RV |
604 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
605 | struct intel_crtc_state *crtc_state) | |
606 | { | |
1895759e | 607 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c90c275c DP |
608 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
609 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
610 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 | 611 | |
95f28d2e | 612 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
613 | return false; |
614 | ||
99fc38b1 JRS |
615 | if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { |
616 | DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n", | |
617 | transcoder_name(crtc_state->cpu_transcoder)); | |
618 | return false; | |
619 | } | |
620 | ||
8228c42f MN |
621 | /* |
622 | * DSC and PSR2 cannot be enabled simultaneously. If a requested | |
623 | * resolution requires DSC to be enabled, priority is given to DSC | |
624 | * over PSR2. | |
625 | */ | |
010663a6 | 626 | if (crtc_state->dsc.compression_enable) { |
8228c42f MN |
627 | DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); |
628 | return false; | |
629 | } | |
630 | ||
f7b3c226 JRS |
631 | if (INTEL_GEN(dev_priv) >= 12) { |
632 | psr_max_h = 5120; | |
633 | psr_max_v = 3200; | |
634 | } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { | |
c90c275c DP |
635 | psr_max_h = 4096; |
636 | psr_max_v = 2304; | |
cf819eff | 637 | } else if (IS_GEN(dev_priv, 9)) { |
c90c275c DP |
638 | psr_max_h = 3640; |
639 | psr_max_v = 2304; | |
640 | } | |
641 | ||
642 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
643 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
644 | crtc_hdisplay, crtc_vdisplay, | |
645 | psr_max_h, psr_max_v); | |
c4932d79 RV |
646 | return false; |
647 | } | |
648 | ||
bef5e5b3 JRS |
649 | /* |
650 | * HW sends SU blocks of size four scan lines, which means the starting | |
651 | * X coordinate and Y granularity requirements will always be met. We | |
8c0d2c29 JRS |
652 | * only need to validate the SU block width is a multiple of |
653 | * x granularity. | |
bef5e5b3 | 654 | */ |
8c0d2c29 JRS |
655 | if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { |
656 | DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", | |
657 | crtc_hdisplay, dev_priv->psr.su_x_granularity); | |
bef5e5b3 JRS |
658 | return false; |
659 | } | |
660 | ||
618cf883 JRS |
661 | if (crtc_state->crc_enabled) { |
662 | DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n"); | |
663 | return false; | |
664 | } | |
665 | ||
c4932d79 RV |
666 | return true; |
667 | } | |
668 | ||
4d90f2d5 VS |
669 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
670 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
671 | { |
672 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 673 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 674 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 675 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 676 | int psr_setup_time; |
0bc12bcb | 677 | |
4371d896 | 678 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
679 | return; |
680 | ||
c44301fc | 681 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 682 | return; |
0bc12bcb | 683 | |
dc9b5a0c RV |
684 | /* |
685 | * HSW spec explicitly says PSR is tied to port A. | |
4ab4fa10 JRS |
686 | * BDW+ platforms have a instance of PSR registers per transcoder but |
687 | * for now it only supports one instance of PSR, so lets keep it | |
688 | * hardcoded to PORT_A | |
dc9b5a0c | 689 | */ |
ce3508fd | 690 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 691 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 692 | return; |
0bc12bcb RV |
693 | } |
694 | ||
50a12d8f JRS |
695 | if (dev_priv->psr.sink_not_reliable) { |
696 | DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); | |
697 | return; | |
698 | } | |
699 | ||
7ae6ad6f JRS |
700 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
701 | DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n"); | |
4d90f2d5 | 702 | return; |
0bc12bcb RV |
703 | } |
704 | ||
dfd2e9ab VS |
705 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
706 | if (psr_setup_time < 0) { | |
707 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
708 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 709 | return; |
dfd2e9ab VS |
710 | } |
711 | ||
712 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
713 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
714 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
715 | psr_setup_time); | |
4d90f2d5 VS |
716 | return; |
717 | } | |
718 | ||
4d90f2d5 | 719 | crtc_state->has_psr = true; |
c4932d79 | 720 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
721 | } |
722 | ||
e2bbc343 | 723 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 724 | { |
1895759e | 725 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 726 | |
0f81e645 | 727 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) |
4ab4fa10 | 728 | WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); |
0f81e645 | 729 | |
4ab4fa10 | 730 | WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); |
0bc12bcb RV |
731 | WARN_ON(dev_priv->psr.active); |
732 | lockdep_assert_held(&dev_priv->psr.lock); | |
733 | ||
cf5d862d RV |
734 | /* psr1 and psr2 are mutually exclusive.*/ |
735 | if (dev_priv->psr.psr2_enabled) | |
736 | hsw_activate_psr2(intel_dp); | |
737 | else | |
738 | hsw_activate_psr1(intel_dp); | |
739 | ||
0bc12bcb RV |
740 | dev_priv->psr.active = true; |
741 | } | |
742 | ||
8f19b401 ID |
743 | static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv, |
744 | enum transcoder cpu_transcoder) | |
745 | { | |
746 | static const i915_reg_t regs[] = { | |
747 | [TRANSCODER_A] = CHICKEN_TRANS_A, | |
748 | [TRANSCODER_B] = CHICKEN_TRANS_B, | |
749 | [TRANSCODER_C] = CHICKEN_TRANS_C, | |
750 | [TRANSCODER_EDP] = CHICKEN_TRANS_EDP, | |
751 | }; | |
752 | ||
753 | WARN_ON(INTEL_GEN(dev_priv) < 9); | |
754 | ||
755 | if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) || | |
756 | !regs[cpu_transcoder].reg)) | |
757 | cpu_transcoder = TRANSCODER_A; | |
758 | ||
759 | return regs[cpu_transcoder]; | |
760 | } | |
761 | ||
cf5d862d RV |
762 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
763 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 764 | { |
1895759e | 765 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 766 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 767 | u32 mask; |
4d1fa22f | 768 | |
d544e918 DP |
769 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
770 | * use hardcoded values PSR AUX transactions | |
771 | */ | |
772 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
773 | hsw_psr_setup_aux(intel_dp); | |
774 | ||
cf819eff | 775 | if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && |
d15f9cdd | 776 | !IS_GEMINILAKE(dev_priv))) { |
8f19b401 ID |
777 | i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, |
778 | cpu_transcoder); | |
779 | u32 chicken = I915_READ(reg); | |
5e87325f | 780 | |
d15f9cdd JRS |
781 | chicken |= PSR2_VSC_ENABLE_PROG_HEADER | |
782 | PSR2_ADD_VERTICAL_LINE_COUNT; | |
8f19b401 | 783 | I915_WRITE(reg, chicken); |
4d1fa22f | 784 | } |
bf80928f JRS |
785 | |
786 | /* | |
787 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
788 | * mask LPSP to avoid dependency on other drivers that might block | |
789 | * runtime_pm besides preventing other hw tracking issues now we | |
790 | * can rely on frontbuffer tracking. | |
791 | */ | |
fc6ff9dc JRS |
792 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
793 | EDP_PSR_DEBUG_MASK_HPD | | |
794 | EDP_PSR_DEBUG_MASK_LPSP | | |
795 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
796 | ||
797 | if (INTEL_GEN(dev_priv) < 11) | |
798 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
799 | ||
4ab4fa10 | 800 | I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); |
df7415bf | 801 | |
2f3b8712 | 802 | psr_irq_control(dev_priv); |
4d1fa22f RV |
803 | } |
804 | ||
c44301fc ML |
805 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
806 | const struct intel_crtc_state *crtc_state) | |
807 | { | |
808 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
4ab4fa10 | 809 | u32 val; |
c44301fc | 810 | |
23ec9f52 JRS |
811 | WARN_ON(dev_priv->psr.enabled); |
812 | ||
813 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
814 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
815 | dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; | |
1c4d821d AG |
816 | dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; |
817 | dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state); | |
4ab4fa10 JRS |
818 | dev_priv->psr.transcoder = crtc_state->cpu_transcoder; |
819 | ||
820 | /* | |
821 | * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR | |
822 | * will still keep the error set even after the reset done in the | |
823 | * irq_preinstall and irq_uninstall hooks. | |
824 | * And enabling in this situation cause the screen to freeze in the | |
825 | * first time that PSR HW tries to activate so lets keep PSR disabled | |
826 | * to avoid any rendering problems. | |
827 | */ | |
8241cfbe JRS |
828 | if (INTEL_GEN(dev_priv) >= 12) { |
829 | val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder)); | |
830 | val &= EDP_PSR_ERROR(0); | |
831 | } else { | |
832 | val = I915_READ(EDP_PSR_IIR); | |
833 | val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); | |
834 | } | |
4ab4fa10 JRS |
835 | if (val) { |
836 | dev_priv->psr.sink_not_reliable = true; | |
837 | DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n"); | |
838 | return; | |
839 | } | |
c44301fc ML |
840 | |
841 | DRM_DEBUG_KMS("Enabling PSR%s\n", | |
842 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
843 | intel_psr_setup_vsc(intel_dp, crtc_state); | |
844 | intel_psr_enable_sink(intel_dp); | |
845 | intel_psr_enable_source(intel_dp, crtc_state); | |
846 | dev_priv->psr.enabled = true; | |
847 | ||
848 | intel_psr_activate(intel_dp); | |
849 | } | |
850 | ||
b2b89f55 RV |
851 | /** |
852 | * intel_psr_enable - Enable PSR | |
853 | * @intel_dp: Intel DP | |
d2419ffc | 854 | * @crtc_state: new CRTC state |
b2b89f55 RV |
855 | * |
856 | * This function can only be called after the pipe is fully trained and enabled. | |
857 | */ | |
d2419ffc VS |
858 | void intel_psr_enable(struct intel_dp *intel_dp, |
859 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 860 | { |
1895759e | 861 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 862 | |
4d90f2d5 | 863 | if (!crtc_state->has_psr) |
0bc12bcb | 864 | return; |
0bc12bcb | 865 | |
c9ef291a DP |
866 | if (WARN_ON(!CAN_PSR(dev_priv))) |
867 | return; | |
868 | ||
da83ef85 | 869 | WARN_ON(dev_priv->drrs.dp); |
c44301fc | 870 | |
0bc12bcb | 871 | mutex_lock(&dev_priv->psr.lock); |
23ec9f52 JRS |
872 | |
873 | if (!psr_global_enabled(dev_priv->psr.debug)) { | |
874 | DRM_DEBUG_KMS("PSR disabled by flag\n"); | |
0bc12bcb RV |
875 | goto unlock; |
876 | } | |
877 | ||
23ec9f52 | 878 | intel_psr_enable_locked(dev_priv, crtc_state); |
d0ac896a | 879 | |
0bc12bcb RV |
880 | unlock: |
881 | mutex_unlock(&dev_priv->psr.lock); | |
882 | } | |
883 | ||
26f9ec9a JRS |
884 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
885 | { | |
886 | u32 val; | |
887 | ||
b2fc2252 | 888 | if (!dev_priv->psr.active) { |
0f81e645 | 889 | if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { |
4ab4fa10 JRS |
890 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
891 | WARN_ON(val & EDP_PSR2_ENABLE); | |
892 | } | |
893 | ||
894 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); | |
895 | WARN_ON(val & EDP_PSR_ENABLE); | |
896 | ||
26f9ec9a | 897 | return; |
b2fc2252 | 898 | } |
26f9ec9a JRS |
899 | |
900 | if (dev_priv->psr.psr2_enabled) { | |
1c4d821d | 901 | tgl_disallow_dc3co_on_psr2_exit(dev_priv); |
4ab4fa10 | 902 | val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 903 | WARN_ON(!(val & EDP_PSR2_ENABLE)); |
4ab4fa10 JRS |
904 | val &= ~EDP_PSR2_ENABLE; |
905 | I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a | 906 | } else { |
4ab4fa10 | 907 | val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); |
26f9ec9a | 908 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
4ab4fa10 JRS |
909 | val &= ~EDP_PSR_ENABLE; |
910 | I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); | |
26f9ec9a JRS |
911 | } |
912 | dev_priv->psr.active = false; | |
913 | } | |
914 | ||
2ee936e3 | 915 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 916 | { |
1895759e | 917 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
918 | i915_reg_t psr_status; |
919 | u32 psr_status_mask; | |
0bc12bcb | 920 | |
2ee936e3 JRS |
921 | lockdep_assert_held(&dev_priv->psr.lock); |
922 | ||
923 | if (!dev_priv->psr.enabled) | |
924 | return; | |
925 | ||
926 | DRM_DEBUG_KMS("Disabling PSR%s\n", | |
927 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
928 | ||
b2fc2252 | 929 | intel_psr_exit(dev_priv); |
77affa31 | 930 | |
b2fc2252 | 931 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 932 | psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 933 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
0bc12bcb | 934 | } else { |
4ab4fa10 | 935 | psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
b2fc2252 | 936 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 937 | } |
b2fc2252 JRS |
938 | |
939 | /* Wait till PSR is idle */ | |
4cb3b44d DCS |
940 | if (intel_de_wait_for_clear(dev_priv, psr_status, |
941 | psr_status_mask, 2000)) | |
b2fc2252 | 942 | DRM_ERROR("Timed out waiting PSR idle state\n"); |
cc3054ff JRS |
943 | |
944 | /* Disable PSR on Sink */ | |
945 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
946 | ||
c44301fc | 947 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
948 | } |
949 | ||
e2bbc343 RV |
950 | /** |
951 | * intel_psr_disable - Disable PSR | |
952 | * @intel_dp: Intel DP | |
d2419ffc | 953 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
954 | * |
955 | * This function needs to be called before disabling pipe. | |
956 | */ | |
d2419ffc VS |
957 | void intel_psr_disable(struct intel_dp *intel_dp, |
958 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 959 | { |
1895759e | 960 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 961 | |
4d90f2d5 | 962 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
963 | return; |
964 | ||
c9ef291a DP |
965 | if (WARN_ON(!CAN_PSR(dev_priv))) |
966 | return; | |
967 | ||
e2bbc343 | 968 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 969 | |
cc3054ff | 970 | intel_psr_disable_locked(intel_dp); |
c44301fc | 971 | |
0bc12bcb | 972 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 973 | cancel_work_sync(&dev_priv->psr.work); |
1c4d821d | 974 | cancel_delayed_work_sync(&dev_priv->psr.idle_work); |
0bc12bcb RV |
975 | } |
976 | ||
88e05aff JRS |
977 | static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) |
978 | { | |
381f8a20 JRS |
979 | if (INTEL_GEN(dev_priv) >= 9) |
980 | /* | |
981 | * Display WA #0884: skl+ | |
982 | * This documented WA for bxt can be safely applied | |
983 | * broadly so we can force HW tracking to exit PSR | |
984 | * instead of disabling and re-enabling. | |
985 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
986 | * but it makes more sense write to the current active | |
987 | * pipe. | |
988 | */ | |
989 | I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); | |
990 | else | |
991 | /* | |
992 | * A write to CURSURFLIVE do not cause HW tracking to exit PSR | |
993 | * on older gens so doing the manual exit instead. | |
994 | */ | |
995 | intel_psr_exit(dev_priv); | |
88e05aff JRS |
996 | } |
997 | ||
23ec9f52 JRS |
998 | /** |
999 | * intel_psr_update - Update PSR state | |
1000 | * @intel_dp: Intel DP | |
1001 | * @crtc_state: new CRTC state | |
1002 | * | |
1003 | * This functions will update PSR states, disabling, enabling or switching PSR | |
1004 | * version when executing fastsets. For full modeset, intel_psr_disable() and | |
1005 | * intel_psr_enable() should be called instead. | |
1006 | */ | |
1007 | void intel_psr_update(struct intel_dp *intel_dp, | |
1008 | const struct intel_crtc_state *crtc_state) | |
1009 | { | |
1010 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1011 | struct i915_psr *psr = &dev_priv->psr; | |
1012 | bool enable, psr2_enable; | |
1013 | ||
1014 | if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) | |
1015 | return; | |
1016 | ||
1017 | mutex_lock(&dev_priv->psr.lock); | |
1018 | ||
1019 | enable = crtc_state->has_psr && psr_global_enabled(psr->debug); | |
1020 | psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); | |
1021 | ||
88e05aff JRS |
1022 | if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { |
1023 | /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ | |
1024 | if (crtc_state->crc_enabled && psr->enabled) | |
1025 | psr_force_hw_tracking_exit(dev_priv); | |
381f8a20 JRS |
1026 | else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { |
1027 | /* | |
1028 | * Activate PSR again after a force exit when enabling | |
1029 | * CRC in older gens | |
1030 | */ | |
1031 | if (!dev_priv->psr.active && | |
1032 | !dev_priv->psr.busy_frontbuffer_bits) | |
1033 | schedule_work(&dev_priv->psr.work); | |
1034 | } | |
88e05aff | 1035 | |
23ec9f52 | 1036 | goto unlock; |
88e05aff | 1037 | } |
23ec9f52 | 1038 | |
9f952664 JRS |
1039 | if (psr->enabled) |
1040 | intel_psr_disable_locked(intel_dp); | |
23ec9f52 | 1041 | |
9f952664 JRS |
1042 | if (enable) |
1043 | intel_psr_enable_locked(dev_priv, crtc_state); | |
23ec9f52 JRS |
1044 | |
1045 | unlock: | |
1046 | mutex_unlock(&dev_priv->psr.lock); | |
1047 | } | |
1048 | ||
65df9c79 DP |
1049 | /** |
1050 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
1051 | * @new_crtc_state: new CRTC state | |
1052 | * @out_value: PSR status in case of failure | |
1053 | * | |
1054 | * This function is expected to be called from pipe_update_start() where it is | |
1055 | * not expected to race with PSR enable or disable. | |
1056 | * | |
1057 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
1058 | */ | |
63ec132d DP |
1059 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
1060 | u32 *out_value) | |
c43dbcbb | 1061 | { |
c3d43361 TV |
1062 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
1063 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
c43dbcbb | 1064 | |
c44301fc | 1065 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
1066 | return 0; |
1067 | ||
fd255f6e DP |
1068 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
1069 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
1070 | return 0; | |
c43dbcbb TV |
1071 | |
1072 | /* | |
65df9c79 DP |
1073 | * From bspec: Panel Self Refresh (BDW+) |
1074 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
1075 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
1076 | * defensive enough to cover everything. | |
c43dbcbb | 1077 | */ |
63ec132d | 1078 | |
4ab4fa10 JRS |
1079 | return __intel_wait_for_register(&dev_priv->uncore, |
1080 | EDP_PSR_STATUS(dev_priv->psr.transcoder), | |
fd255f6e | 1081 | EDP_PSR_STATUS_STATE_MASK, |
63ec132d DP |
1082 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
1083 | out_value); | |
c43dbcbb TV |
1084 | } |
1085 | ||
1086 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 1087 | { |
daeb725e CW |
1088 | i915_reg_t reg; |
1089 | u32 mask; | |
1090 | int err; | |
1091 | ||
c44301fc | 1092 | if (!dev_priv->psr.enabled) |
daeb725e | 1093 | return false; |
0bc12bcb | 1094 | |
ce3508fd | 1095 | if (dev_priv->psr.psr2_enabled) { |
4ab4fa10 | 1096 | reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1097 | mask = EDP_PSR2_STATUS_STATE_MASK; |
995d3047 | 1098 | } else { |
4ab4fa10 | 1099 | reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); |
ce3508fd | 1100 | mask = EDP_PSR_STATUS_STATE_MASK; |
0bc12bcb | 1101 | } |
daeb725e CW |
1102 | |
1103 | mutex_unlock(&dev_priv->psr.lock); | |
1104 | ||
4cb3b44d | 1105 | err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); |
daeb725e CW |
1106 | if (err) |
1107 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
1108 | ||
1109 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 1110 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
1111 | return err == 0 && dev_priv->psr.enabled; |
1112 | } | |
0bc12bcb | 1113 | |
23ec9f52 | 1114 | static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) |
2ac45bdd | 1115 | { |
23ec9f52 JRS |
1116 | struct drm_device *dev = &dev_priv->drm; |
1117 | struct drm_modeset_acquire_ctx ctx; | |
1118 | struct drm_atomic_state *state; | |
1119 | struct drm_crtc *crtc; | |
1120 | int err; | |
2ac45bdd | 1121 | |
23ec9f52 JRS |
1122 | state = drm_atomic_state_alloc(dev); |
1123 | if (!state) | |
1124 | return -ENOMEM; | |
2ac45bdd | 1125 | |
23ec9f52 JRS |
1126 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
1127 | state->acquire_ctx = &ctx; | |
1128 | ||
1129 | retry: | |
1130 | drm_for_each_crtc(crtc, dev) { | |
1131 | struct drm_crtc_state *crtc_state; | |
1132 | struct intel_crtc_state *intel_crtc_state; | |
1133 | ||
1134 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
1135 | if (IS_ERR(crtc_state)) { | |
1136 | err = PTR_ERR(crtc_state); | |
1137 | goto error; | |
1138 | } | |
1139 | ||
1140 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
1141 | ||
458e0977 | 1142 | if (crtc_state->active && intel_crtc_state->has_psr) { |
23ec9f52 JRS |
1143 | /* Mark mode as changed to trigger a pipe->update() */ |
1144 | crtc_state->mode_changed = true; | |
1145 | break; | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | err = drm_atomic_commit(state); | |
2ac45bdd | 1150 | |
23ec9f52 JRS |
1151 | error: |
1152 | if (err == -EDEADLK) { | |
1153 | drm_atomic_state_clear(state); | |
1154 | err = drm_modeset_backoff(&ctx); | |
1155 | if (!err) | |
1156 | goto retry; | |
1157 | } | |
1158 | ||
1159 | drm_modeset_drop_locks(&ctx); | |
1160 | drm_modeset_acquire_fini(&ctx); | |
1161 | drm_atomic_state_put(state); | |
1162 | ||
1163 | return err; | |
2ac45bdd ML |
1164 | } |
1165 | ||
23ec9f52 | 1166 | int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) |
c44301fc | 1167 | { |
23ec9f52 JRS |
1168 | const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
1169 | u32 old_mode; | |
c44301fc | 1170 | int ret; |
c44301fc ML |
1171 | |
1172 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 1173 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
c44301fc ML |
1174 | DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); |
1175 | return -EINVAL; | |
1176 | } | |
1177 | ||
c44301fc ML |
1178 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); |
1179 | if (ret) | |
1180 | return ret; | |
1181 | ||
23ec9f52 | 1182 | old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; |
c44301fc | 1183 | dev_priv->psr.debug = val; |
2f3b8712 JRS |
1184 | |
1185 | /* | |
1186 | * Do it right away if it's already enabled, otherwise it will be done | |
1187 | * when enabling the source. | |
1188 | */ | |
1189 | if (dev_priv->psr.enabled) | |
1190 | psr_irq_control(dev_priv); | |
c44301fc | 1191 | |
c44301fc | 1192 | mutex_unlock(&dev_priv->psr.lock); |
23ec9f52 JRS |
1193 | |
1194 | if (old_mode != mode) | |
1195 | ret = intel_psr_fastset_force(dev_priv); | |
1196 | ||
c44301fc ML |
1197 | return ret; |
1198 | } | |
1199 | ||
183b8e67 JRS |
1200 | static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) |
1201 | { | |
1202 | struct i915_psr *psr = &dev_priv->psr; | |
1203 | ||
1204 | intel_psr_disable_locked(psr->dp); | |
1205 | psr->sink_not_reliable = true; | |
1206 | /* let's make sure that sink is awaken */ | |
1207 | drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); | |
1208 | } | |
1209 | ||
daeb725e CW |
1210 | static void intel_psr_work(struct work_struct *work) |
1211 | { | |
1212 | struct drm_i915_private *dev_priv = | |
5422b37c | 1213 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
1214 | |
1215 | mutex_lock(&dev_priv->psr.lock); | |
1216 | ||
5422b37c RV |
1217 | if (!dev_priv->psr.enabled) |
1218 | goto unlock; | |
1219 | ||
183b8e67 JRS |
1220 | if (READ_ONCE(dev_priv->psr.irq_aux_error)) |
1221 | intel_psr_handle_irq(dev_priv); | |
1222 | ||
daeb725e CW |
1223 | /* |
1224 | * We have to make sure PSR is ready for re-enable | |
1225 | * otherwise it keeps disabled until next full enable/disable cycle. | |
1226 | * PSR might take some time to get fully disabled | |
1227 | * and be ready for re-enable. | |
1228 | */ | |
c43dbcbb | 1229 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
1230 | goto unlock; |
1231 | ||
1232 | /* | |
1233 | * The delayed work can race with an invalidate hence we need to | |
1234 | * recheck. Since psr_flush first clears this and then reschedules we | |
1235 | * won't ever miss a flush when bailing out here. | |
1236 | */ | |
c12e0643 | 1237 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
1238 | goto unlock; |
1239 | ||
c44301fc | 1240 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
1241 | unlock: |
1242 | mutex_unlock(&dev_priv->psr.lock); | |
1243 | } | |
1244 | ||
b2b89f55 RV |
1245 | /** |
1246 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 1247 | * @dev_priv: i915 device |
b2b89f55 | 1248 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 1249 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
1250 | * |
1251 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1252 | * with the software frontbuffer tracking. This function gets called every | |
1253 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
1254 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
1255 | * | |
1256 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
1257 | */ | |
5748b6a1 | 1258 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 1259 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1260 | { |
4371d896 | 1261 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1262 | return; |
1263 | ||
ce3508fd | 1264 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
1265 | return; |
1266 | ||
0bc12bcb RV |
1267 | mutex_lock(&dev_priv->psr.lock); |
1268 | if (!dev_priv->psr.enabled) { | |
1269 | mutex_unlock(&dev_priv->psr.lock); | |
1270 | return; | |
1271 | } | |
1272 | ||
f0ad62a6 | 1273 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb | 1274 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
1275 | |
1276 | if (frontbuffer_bits) | |
5748b6a1 | 1277 | intel_psr_exit(dev_priv); |
ec76d629 | 1278 | |
0bc12bcb RV |
1279 | mutex_unlock(&dev_priv->psr.lock); |
1280 | } | |
1281 | ||
1c4d821d AG |
1282 | /* |
1283 | * When we will be completely rely on PSR2 S/W tracking in future, | |
1284 | * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP | |
1285 | * event also therefore tgl_dc3co_flush() require to be changed | |
1286 | * accrodingly in future. | |
1287 | */ | |
1288 | static void | |
1289 | tgl_dc3co_flush(struct drm_i915_private *dev_priv, | |
1290 | unsigned int frontbuffer_bits, enum fb_op_origin origin) | |
1291 | { | |
1292 | u32 delay; | |
1293 | ||
1294 | mutex_lock(&dev_priv->psr.lock); | |
1295 | ||
1296 | if (!dev_priv->psr.dc3co_enabled) | |
1297 | goto unlock; | |
1298 | ||
1299 | if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) | |
1300 | goto unlock; | |
1301 | ||
1302 | /* | |
1303 | * At every frontbuffer flush flip event modified delay of delayed work, | |
1304 | * when delayed work schedules that means display has been idle. | |
1305 | */ | |
1306 | if (!(frontbuffer_bits & | |
1307 | INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) | |
1308 | goto unlock; | |
1309 | ||
1310 | tgl_psr2_enable_dc3co(dev_priv); | |
1311 | /* DC5/DC6 required idle frames = 6 */ | |
1312 | delay = 6 * dev_priv->psr.dc3co_exit_delay; | |
1313 | mod_delayed_work(system_wq, &dev_priv->psr.idle_work, | |
1314 | usecs_to_jiffies(delay)); | |
1315 | ||
1316 | unlock: | |
1317 | mutex_unlock(&dev_priv->psr.lock); | |
1318 | } | |
1319 | ||
b2b89f55 RV |
1320 | /** |
1321 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 1322 | * @dev_priv: i915 device |
b2b89f55 | 1323 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 1324 | * @origin: which operation caused the flush |
b2b89f55 RV |
1325 | * |
1326 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
1327 | * with the software frontbuffer tracking. This function gets called every | |
1328 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
1329 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
1330 | * | |
1331 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
1332 | */ | |
5748b6a1 | 1333 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 1334 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 1335 | { |
4371d896 | 1336 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
1337 | return; |
1338 | ||
1c4d821d AG |
1339 | if (origin == ORIGIN_FLIP) { |
1340 | tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); | |
5baf63cc | 1341 | return; |
1c4d821d | 1342 | } |
5baf63cc | 1343 | |
0bc12bcb RV |
1344 | mutex_lock(&dev_priv->psr.lock); |
1345 | if (!dev_priv->psr.enabled) { | |
1346 | mutex_unlock(&dev_priv->psr.lock); | |
1347 | return; | |
1348 | } | |
1349 | ||
f0ad62a6 | 1350 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); |
0bc12bcb RV |
1351 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1352 | ||
921ec285 | 1353 | /* By definition flush = invalidate + flush */ |
88e05aff JRS |
1354 | if (frontbuffer_bits) |
1355 | psr_force_hw_tracking_exit(dev_priv); | |
995d3047 | 1356 | |
0bc12bcb | 1357 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1358 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1359 | mutex_unlock(&dev_priv->psr.lock); |
1360 | } | |
1361 | ||
b2b89f55 RV |
1362 | /** |
1363 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1364 | * @dev_priv: i915 device private |
b2b89f55 RV |
1365 | * |
1366 | * This function is called only once at driver load to initialize basic | |
1367 | * PSR stuff. | |
1368 | */ | |
c39055b0 | 1369 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1370 | { |
0f328da6 RV |
1371 | if (!HAS_PSR(dev_priv)) |
1372 | return; | |
1373 | ||
c9ef291a DP |
1374 | if (!dev_priv->psr.sink_support) |
1375 | return; | |
1376 | ||
4ab4fa10 JRS |
1377 | if (IS_HASWELL(dev_priv)) |
1378 | /* | |
1379 | * HSW don't have PSR registers on the same space as transcoder | |
1380 | * so set this to a value that when subtract to the register | |
1381 | * in transcoder space results in the right offset for HSW | |
1382 | */ | |
1383 | dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; | |
1384 | ||
598c6cfe DP |
1385 | if (i915_modparams.enable_psr == -1) |
1386 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1387 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1388 | |
65f61b42 | 1389 | /* Set link_standby x link_off defaults */ |
8652744b | 1390 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1391 | /* HSW and BDW require workarounds that we don't implement. */ |
1392 | dev_priv->psr.link_standby = false; | |
99d7a741 JRS |
1393 | else if (INTEL_GEN(dev_priv) < 12) |
1394 | /* For new platforms up to TGL let's respect VBT back again */ | |
60e5ffe3 RV |
1395 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; |
1396 | ||
5422b37c | 1397 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
1c4d821d | 1398 | INIT_DELAYED_WORK(&dev_priv->psr.idle_work, tgl_dc5_idle_thread); |
0bc12bcb RV |
1399 | mutex_init(&dev_priv->psr.lock); |
1400 | } | |
cc3054ff JRS |
1401 | |
1402 | void intel_psr_short_pulse(struct intel_dp *intel_dp) | |
1403 | { | |
1895759e | 1404 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff JRS |
1405 | struct i915_psr *psr = &dev_priv->psr; |
1406 | u8 val; | |
93bf76ed | 1407 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1408 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1409 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1410 | |
1411 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1412 | return; | |
1413 | ||
1414 | mutex_lock(&psr->lock); | |
1415 | ||
c44301fc | 1416 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1417 | goto exit; |
1418 | ||
1419 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { | |
1420 | DRM_ERROR("PSR_STATUS dpcd read failed\n"); | |
1421 | goto exit; | |
1422 | } | |
1423 | ||
1424 | if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { | |
1425 | DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); | |
1426 | intel_psr_disable_locked(intel_dp); | |
50a12d8f | 1427 | psr->sink_not_reliable = true; |
cc3054ff JRS |
1428 | } |
1429 | ||
93bf76ed JRS |
1430 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { |
1431 | DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n"); | |
1432 | goto exit; | |
1433 | } | |
1434 | ||
1435 | if (val & DP_PSR_RFB_STORAGE_ERROR) | |
1436 | DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); | |
1437 | if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) | |
1438 | DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
00c8f194 | 1439 | if (val & DP_PSR_LINK_CRC_ERROR) |
5063f48b | 1440 | DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n"); |
93bf76ed JRS |
1441 | |
1442 | if (val & ~errors) | |
1443 | DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", | |
1444 | val & ~errors); | |
50a12d8f | 1445 | if (val & errors) { |
93bf76ed | 1446 | intel_psr_disable_locked(intel_dp); |
50a12d8f JRS |
1447 | psr->sink_not_reliable = true; |
1448 | } | |
93bf76ed JRS |
1449 | /* clear status register */ |
1450 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); | |
cc3054ff JRS |
1451 | exit: |
1452 | mutex_unlock(&psr->lock); | |
1453 | } | |
2f8e7ea9 JRS |
1454 | |
1455 | bool intel_psr_enabled(struct intel_dp *intel_dp) | |
1456 | { | |
1457 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1458 | bool ret; | |
1459 | ||
1460 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1461 | return false; | |
1462 | ||
1463 | mutex_lock(&dev_priv->psr.lock); | |
1464 | ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); | |
1465 | mutex_unlock(&dev_priv->psr.lock); | |
1466 | ||
1467 | return ret; | |
1468 | } |