[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / gt / intel_ring_types.h

/*
 * SPDX-License-Identifier: MIT
 *
 * Copyright © 2019 Intel Corporation
 */

#ifndef INTEL_RING_TYPES_H
#define INTEL_RING_TYPES_H

#include <linux/atomic.h>
#include <linux/kref.h>
#include <linux/types.h>

/*
 * Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))

struct i915_vma;

struct intel_ring {
	struct kref ref;
	struct i915_vma *vma;
	void *vaddr;

	/*
	 * As we have two types of rings, one global to the engine used
	 * by ringbuffer submission and those that are exclusive to a
	 * context used by execlists, we have to play safe and allow
	 * atomic updates to the pin_count. However, the actual pinning
	 * of the context is either done during initialisation for
	 * ringbuffer submission or serialised as part of the context
	 * pinning for execlists, and so we do not need a mutex ourselves
	 * to serialise intel_ring_pin/intel_ring_unpin.
	 */
	atomic_t pin_count;

	u32 head; /* updated during retire, loosely tracks RING_HEAD */
	u32 tail; /* updated on submission, used for RING_TAIL */
	u32 emit; /* updated during request construction */

	u32 space;
	u32 size;
	u32 wrap;
	u32 effective_size;
};

#endif /* INTEL_RING_TYPES_H */
Commit	Line	Data
2871ea85 CW	1	/*
	2	* SPDX-License-Identifier: MIT
	3	*
	4	* Copyright © 2019 Intel Corporation
	5	*/
	6
	7	#ifndef INTEL_RING_TYPES_H
	8	#define INTEL_RING_TYPES_H
	9
	10	#include <linux/atomic.h>
	11	#include <linux/kref.h>
	12	#include <linux/types.h>
	13
	14	/*
	15	* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
	16	* but keeps the logic simple. Indeed, the whole purpose of this macro is just
	17	* to give some inclination as to some of the magic values used in the various
	18	* workarounds!
	19	*/
	20	#define CACHELINE_BYTES 64
	21	#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
	22
	23	struct i915_vma;
	24
	25	struct intel_ring {
	26	struct kref ref;
	27	struct i915_vma *vma;
	28	void *vaddr;
	29
	30	/*
	31	* As we have two types of rings, one global to the engine used
	32	* by ringbuffer submission and those that are exclusive to a
	33	* context used by execlists, we have to play safe and allow
	34	* atomic updates to the pin_count. However, the actual pinning
	35	* of the context is either done during initialisation for
	36	* ringbuffer submission or serialised as part of the context
	37	* pinning for execlists, and so we do not need a mutex ourselves
	38	* to serialise intel_ring_pin/intel_ring_unpin.
	39	*/
	40	atomic_t pin_count;
	41
15de9cb5 CW	42	u32 head; /* updated during retire, loosely tracks RING_HEAD */
	43	u32 tail; /* updated on submission, used for RING_TAIL */
	44	u32 emit; /* updated during request construction */
2871ea85 CW	45
	46	u32 space;
	47	u32 size;
b1339eca	48	u32 wrap;
2871ea85 CW	49	u32 effective_size;
	50	};
	51
	52	#endif /* INTEL_RING_TYPES_H */