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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa | 33 | |
10be98a7 CW |
34 | #include "gem/i915_gem_context.h" |
35 | ||
db56f974 TU |
36 | #include "gt/intel_gt.h" |
37 | ||
7c2fa7fa CW |
38 | #include "i915_drv.h" |
39 | #include "i915_gem_render_state.h" | |
62fdfeaf | 40 | #include "i915_trace.h" |
10be98a7 | 41 | #include "intel_context.h" |
112ed2d3 | 42 | #include "intel_reset.h" |
7d3c425f | 43 | #include "intel_workarounds.h" |
62fdfeaf | 44 | |
a0442461 CW |
45 | /* Rough estimate of the typical request size, performing a flush, |
46 | * set-context and then emitting the batch. | |
47 | */ | |
48 | #define LEGACY_REQUEST_SIZE 200 | |
49 | ||
95aebcb2 | 50 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
95aebcb2 CW |
52 | unsigned int space; |
53 | ||
54 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
55 | ||
56 | ring->space = space; | |
57 | return space; | |
ebd0fd4b DG |
58 | } |
59 | ||
b72f3acb | 60 | static int |
e61e0f51 | 61 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 62 | { |
a889580c | 63 | unsigned int num_store_dw; |
73dec95e | 64 | u32 cmd, *cs; |
46f0f8d1 CW |
65 | |
66 | cmd = MI_FLUSH; | |
a889580c | 67 | num_store_dw = 0; |
7c9cf4e3 | 68 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 69 | cmd |= MI_READ_FLUSH; |
a889580c CW |
70 | if (mode & EMIT_FLUSH) |
71 | num_store_dw = 4; | |
46f0f8d1 | 72 | |
a889580c | 73 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
74 | if (IS_ERR(cs)) |
75 | return PTR_ERR(cs); | |
46f0f8d1 | 76 | |
73dec95e | 77 | *cs++ = cmd; |
a889580c CW |
78 | while (num_store_dw--) { |
79 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
db56f974 | 80 | *cs++ = intel_gt_scratch_offset(rq->engine->gt); |
a889580c CW |
81 | *cs++ = 0; |
82 | } | |
83 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
84 | ||
e61e0f51 | 85 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static int | |
e61e0f51 | 91 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 92 | { |
73dec95e | 93 | u32 cmd, *cs; |
55f99bf2 | 94 | int i; |
6f392d54 | 95 | |
36d527de CW |
96 | /* |
97 | * read/write caches: | |
98 | * | |
99 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
100 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
101 | * also flushed at 2d versus 3d pipeline switches. | |
102 | * | |
103 | * read-only caches: | |
104 | * | |
105 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
106 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
107 | * | |
108 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
109 | * | |
110 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
111 | * invalidated when MI_EXE_FLUSH is set. | |
112 | * | |
113 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
114 | * invalidated with every MI_FLUSH. | |
115 | * | |
116 | * TLBs: | |
117 | * | |
118 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
119 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
120 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
121 | * are flushed at any MI_FLUSH. | |
122 | */ | |
123 | ||
b5321f30 | 124 | cmd = MI_FLUSH; |
7c9cf4e3 | 125 | if (mode & EMIT_INVALIDATE) { |
36d527de | 126 | cmd |= MI_EXE_FLUSH; |
cf819eff | 127 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
128 | cmd |= MI_INVALIDATE_ISP; |
129 | } | |
70eac33e | 130 | |
55f99bf2 CW |
131 | i = 2; |
132 | if (mode & EMIT_INVALIDATE) | |
133 | i += 20; | |
134 | ||
135 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
136 | if (IS_ERR(cs)) |
137 | return PTR_ERR(cs); | |
b72f3acb | 138 | |
73dec95e | 139 | *cs++ = cmd; |
55f99bf2 CW |
140 | |
141 | /* | |
142 | * A random delay to let the CS invalidate take effect? Without this | |
143 | * delay, the GPU relocation path fails as the CS does not see | |
144 | * the updated contents. Just as important, if we apply the flushes | |
145 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
146 | * write and before the invalidate on the next batch), the relocations | |
147 | * still fail. This implies that is a delay following invalidation | |
148 | * that is required to reset the caches as opposed to a delay to | |
149 | * ensure the memory is written. | |
150 | */ | |
151 | if (mode & EMIT_INVALIDATE) { | |
152 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
db56f974 TU |
153 | *cs++ = intel_gt_scratch_offset(rq->engine->gt) | |
154 | PIPE_CONTROL_GLOBAL_GTT; | |
55f99bf2 CW |
155 | *cs++ = 0; |
156 | *cs++ = 0; | |
157 | ||
158 | for (i = 0; i < 12; i++) | |
159 | *cs++ = MI_FLUSH; | |
160 | ||
161 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
db56f974 TU |
162 | *cs++ = intel_gt_scratch_offset(rq->engine->gt) | |
163 | PIPE_CONTROL_GLOBAL_GTT; | |
55f99bf2 CW |
164 | *cs++ = 0; |
165 | *cs++ = 0; | |
166 | } | |
167 | ||
168 | *cs++ = cmd; | |
169 | ||
e61e0f51 | 170 | intel_ring_advance(rq, cs); |
b72f3acb CW |
171 | |
172 | return 0; | |
8187a2b7 ZN |
173 | } |
174 | ||
179f4025 | 175 | /* |
8d315287 JB |
176 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
177 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
178 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
179 | * | |
180 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
181 | * produced by non-pipelined state commands), software needs to first | |
182 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
183 | * 0. | |
184 | * | |
185 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
186 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
187 | * | |
188 | * And the workaround for these two requires this workaround first: | |
189 | * | |
190 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
191 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
192 | * flushes. | |
193 | * | |
194 | * And this last workaround is tricky because of the requirements on | |
195 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
196 | * volume 2 part 1: | |
197 | * | |
198 | * "1 of the following must also be set: | |
199 | * - Render Target Cache Flush Enable ([12] of DW1) | |
200 | * - Depth Cache Flush Enable ([0] of DW1) | |
201 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
202 | * - Depth Stall ([13] of DW1) | |
203 | * - Post-Sync Operation ([13] of DW1) | |
204 | * - Notify Enable ([8] of DW1)" | |
205 | * | |
206 | * The cache flushes require the workaround flush that triggered this | |
207 | * one, so we can't use it. Depth stall would trigger the same. | |
208 | * Post-sync nonzero is what triggered this second workaround, so we | |
209 | * can't use that one either. Notify enable is IRQs, which aren't | |
210 | * really our business. That leaves only stall at scoreboard. | |
211 | */ | |
212 | static int | |
caa5915b | 213 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 214 | { |
db56f974 TU |
215 | u32 scratch_addr = |
216 | intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES; | |
73dec95e TU |
217 | u32 *cs; |
218 | ||
e61e0f51 | 219 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
220 | if (IS_ERR(cs)) |
221 | return PTR_ERR(cs); | |
222 | ||
223 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
224 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
225 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
226 | *cs++ = 0; /* low dword */ | |
227 | *cs++ = 0; /* high dword */ | |
228 | *cs++ = MI_NOOP; | |
e61e0f51 | 229 | intel_ring_advance(rq, cs); |
73dec95e | 230 | |
e61e0f51 | 231 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
232 | if (IS_ERR(cs)) |
233 | return PTR_ERR(cs); | |
234 | ||
235 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
236 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
237 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
238 | *cs++ = 0; | |
239 | *cs++ = 0; | |
240 | *cs++ = MI_NOOP; | |
e61e0f51 | 241 | intel_ring_advance(rq, cs); |
8d315287 JB |
242 | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int | |
e61e0f51 | 247 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 248 | { |
db56f974 TU |
249 | u32 scratch_addr = |
250 | intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES; | |
73dec95e | 251 | u32 *cs, flags = 0; |
8d315287 JB |
252 | int ret; |
253 | ||
b3111509 | 254 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 255 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
256 | if (ret) |
257 | return ret; | |
258 | ||
8d315287 JB |
259 | /* Just flush everything. Experiments have shown that reducing the |
260 | * number of bits based on the write domains has little performance | |
261 | * impact. | |
262 | */ | |
7c9cf4e3 | 263 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
264 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
265 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
266 | /* | |
267 | * Ensure that any following seqno writes only happen | |
268 | * when the render cache is indeed flushed. | |
269 | */ | |
97f209bc | 270 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 271 | } |
7c9cf4e3 | 272 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
273 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
274 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
275 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
276 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
278 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
279 | /* | |
280 | * TLB invalidate requires a post-sync write. | |
281 | */ | |
3ac78313 | 282 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 283 | } |
8d315287 | 284 | |
e61e0f51 | 285 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
286 | if (IS_ERR(cs)) |
287 | return PTR_ERR(cs); | |
8d315287 | 288 | |
73dec95e TU |
289 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
290 | *cs++ = flags; | |
291 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
292 | *cs++ = 0; | |
e61e0f51 | 293 | intel_ring_advance(rq, cs); |
8d315287 JB |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
e1a73a54 | 298 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
299 | { |
300 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
301 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
302 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
303 | *cs++ = 0; | |
304 | *cs++ = 0; | |
305 | ||
306 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
307 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
db56f974 TU |
308 | *cs++ = intel_gt_scratch_offset(rq->engine->gt) | |
309 | PIPE_CONTROL_GLOBAL_GTT; | |
caa5915b CW |
310 | *cs++ = 0; |
311 | ||
312 | /* Finally we can flush and with it emit the breadcrumb */ | |
313 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
314 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
315 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
316 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
317 | PIPE_CONTROL_QW_WRITE | | |
318 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
319 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
320 | *cs++ = rq->fence.seqno; | |
321 | ||
caa5915b CW |
322 | *cs++ = MI_USER_INTERRUPT; |
323 | *cs++ = MI_NOOP; | |
324 | ||
325 | rq->tail = intel_ring_offset(rq, cs); | |
326 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
327 | |
328 | return cs; | |
caa5915b | 329 | } |
caa5915b | 330 | |
f3987631 | 331 | static int |
e61e0f51 | 332 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 333 | { |
73dec95e | 334 | u32 *cs; |
f3987631 | 335 | |
e61e0f51 | 336 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
337 | if (IS_ERR(cs)) |
338 | return PTR_ERR(cs); | |
f3987631 | 339 | |
73dec95e TU |
340 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
341 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
342 | *cs++ = 0; | |
343 | *cs++ = 0; | |
e61e0f51 | 344 | intel_ring_advance(rq, cs); |
f3987631 PZ |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
4772eaeb | 349 | static int |
e61e0f51 | 350 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 351 | { |
db56f974 TU |
352 | u32 scratch_addr = |
353 | intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES; | |
73dec95e | 354 | u32 *cs, flags = 0; |
4772eaeb | 355 | |
f3987631 PZ |
356 | /* |
357 | * Ensure that any following seqno writes only happen when the render | |
358 | * cache is indeed flushed. | |
359 | * | |
360 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
361 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
362 | * don't try to be clever and just set it unconditionally. | |
363 | */ | |
364 | flags |= PIPE_CONTROL_CS_STALL; | |
365 | ||
4772eaeb PZ |
366 | /* Just flush everything. Experiments have shown that reducing the |
367 | * number of bits based on the write domains has little performance | |
368 | * impact. | |
369 | */ | |
7c9cf4e3 | 370 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
371 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
372 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 373 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 374 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 375 | } |
7c9cf4e3 | 376 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
377 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
378 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
379 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
380 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
381 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
382 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 383 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
384 | /* |
385 | * TLB invalidate requires a post-sync write. | |
386 | */ | |
387 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 388 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 389 | |
add284a3 CW |
390 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
391 | ||
f3987631 PZ |
392 | /* Workaround: we must issue a pipe_control with CS-stall bit |
393 | * set before a pipe_control command that has the state cache | |
394 | * invalidate bit set. */ | |
e61e0f51 | 395 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
396 | } |
397 | ||
e61e0f51 | 398 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
399 | if (IS_ERR(cs)) |
400 | return PTR_ERR(cs); | |
4772eaeb | 401 | |
73dec95e TU |
402 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
403 | *cs++ = flags; | |
404 | *cs++ = scratch_addr; | |
405 | *cs++ = 0; | |
e61e0f51 | 406 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
e1a73a54 | 411 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
412 | { |
413 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
414 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
415 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
416 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
417 | PIPE_CONTROL_FLUSH_ENABLE | | |
418 | PIPE_CONTROL_QW_WRITE | | |
419 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
420 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
421 | *cs++ = rq->timeline->hwsp_offset; |
422 | *cs++ = rq->fence.seqno; | |
423 | ||
caa5915b CW |
424 | *cs++ = MI_USER_INTERRUPT; |
425 | *cs++ = MI_NOOP; | |
426 | ||
427 | rq->tail = intel_ring_offset(rq, cs); | |
428 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
429 | |
430 | return cs; | |
caa5915b | 431 | } |
caa5915b | 432 | |
e1a73a54 | 433 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 434 | { |
5013eb8c CW |
435 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
436 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
437 | ||
438 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
439 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
440 | *cs++ = rq->fence.seqno; | |
441 | ||
caa5915b CW |
442 | *cs++ = MI_USER_INTERRUPT; |
443 | ||
444 | rq->tail = intel_ring_offset(rq, cs); | |
445 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
446 | |
447 | return cs; | |
caa5915b | 448 | } |
caa5915b | 449 | |
1212bd82 | 450 | #define GEN7_XCS_WA 32 |
e1a73a54 | 451 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
452 | { |
453 | int i; | |
454 | ||
5013eb8c CW |
455 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
456 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
457 | ||
458 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
459 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
460 | *cs++ = rq->fence.seqno; | |
461 | ||
1212bd82 CW |
462 | for (i = 0; i < GEN7_XCS_WA; i++) { |
463 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
464 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
465 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
466 | } |
467 | ||
468 | *cs++ = MI_FLUSH_DW; | |
469 | *cs++ = 0; | |
470 | *cs++ = 0; | |
471 | ||
472 | *cs++ = MI_USER_INTERRUPT; | |
519a0194 | 473 | *cs++ = MI_NOOP; |
1212bd82 CW |
474 | |
475 | rq->tail = intel_ring_offset(rq, cs); | |
476 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
477 | |
478 | return cs; | |
1212bd82 | 479 | } |
1212bd82 CW |
480 | #undef GEN7_XCS_WA |
481 | ||
060f2322 CW |
482 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
483 | { | |
484 | /* | |
485 | * Keep the render interrupt unmasked as this papers over | |
486 | * lost interrupts following a reset. | |
487 | */ | |
488 | if (engine->class == RENDER_CLASS) { | |
489 | if (INTEL_GEN(engine->i915) >= 6) | |
490 | mask &= ~BIT(0); | |
491 | else | |
492 | mask &= ~I915_USER_INTERRUPT; | |
493 | } | |
494 | ||
495 | intel_engine_set_hwsp_writemask(engine, mask); | |
496 | } | |
497 | ||
498 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 499 | { |
c033666a | 500 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
501 | u32 addr; |
502 | ||
d6acae36 | 503 | addr = lower_32_bits(phys); |
c033666a | 504 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
505 | addr |= (phys >> 28) & 0xf0; |
506 | ||
035dc1e0 DV |
507 | I915_WRITE(HWS_PGA, addr); |
508 | } | |
509 | ||
0ca88ba0 | 510 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 511 | { |
0ca88ba0 | 512 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 513 | |
0ca88ba0 CW |
514 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
515 | return sg_page(obj->mm.pages->sgl); | |
516 | } | |
517 | ||
518 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
519 | { | |
520 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
521 | set_hwstam(engine, ~0u); |
522 | } | |
523 | ||
524 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 525 | { |
c033666a | 526 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 527 | i915_reg_t hwsp; |
af75f269 | 528 | |
060f2322 CW |
529 | /* |
530 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
531 | * the ring registers as of gen7. |
532 | */ | |
cf819eff | 533 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 534 | switch (engine->id) { |
a2d3d265 MT |
535 | /* |
536 | * No more rings exist on Gen7. Default case is only to shut up | |
537 | * gcc switch check warning. | |
538 | */ | |
539 | default: | |
540 | GEM_BUG_ON(engine->id); | |
8a68d464 CW |
541 | /* fallthrough */ |
542 | case RCS0: | |
060f2322 | 543 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 | 544 | break; |
8a68d464 | 545 | case BCS0: |
060f2322 | 546 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 547 | break; |
8a68d464 | 548 | case VCS0: |
060f2322 | 549 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 | 550 | break; |
8a68d464 | 551 | case VECS0: |
060f2322 | 552 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
553 | break; |
554 | } | |
cf819eff | 555 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 556 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 557 | } else { |
060f2322 | 558 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 559 | } |
c5498089 | 560 | |
060f2322 CW |
561 | I915_WRITE(hwsp, offset); |
562 | POSTING_READ(hwsp); | |
563 | } | |
af75f269 | 564 | |
060f2322 CW |
565 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
566 | { | |
567 | struct drm_i915_private *dev_priv = engine->i915; | |
060f2322 CW |
568 | |
569 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
570 | return; | |
571 | ||
572 | /* ring should be idle before issuing a sync flush*/ | |
baba6e57 DCS |
573 | WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); |
574 | ||
575 | ENGINE_WRITE(engine, RING_INSTPM, | |
576 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
577 | INSTPM_SYNC_FLUSH)); | |
578 | if (intel_wait_for_register(engine->uncore, | |
579 | RING_INSTPM(engine->mmio_base), | |
580 | INSTPM_SYNC_FLUSH, 0, | |
060f2322 CW |
581 | 1000)) |
582 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
583 | engine->name); | |
584 | } | |
af75f269 | 585 | |
060f2322 CW |
586 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
587 | { | |
0ca88ba0 | 588 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 589 | set_hwstam(engine, ~0u); |
af75f269 | 590 | |
060f2322 | 591 | flush_cs_tlb(engine); |
af75f269 DL |
592 | } |
593 | ||
0bc40be8 | 594 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 595 | { |
c033666a | 596 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 597 | |
21a2c58a | 598 | if (INTEL_GEN(dev_priv) > 2) { |
baba6e57 DCS |
599 | ENGINE_WRITE(engine, |
600 | RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); | |
601 | if (intel_wait_for_register(engine->uncore, | |
3d808eb1 CW |
602 | RING_MI_MODE(engine->mmio_base), |
603 | MODE_IDLE, | |
604 | MODE_IDLE, | |
605 | 1000)) { | |
0bc40be8 TU |
606 | DRM_ERROR("%s : timed out trying to stop ring\n", |
607 | engine->name); | |
baba6e57 DCS |
608 | |
609 | /* | |
610 | * Sometimes we observe that the idle flag is not | |
9bec9b13 CW |
611 | * set even though the ring is empty. So double |
612 | * check before giving up. | |
613 | */ | |
baba6e57 DCS |
614 | if (ENGINE_READ(engine, RING_HEAD) != |
615 | ENGINE_READ(engine, RING_TAIL)) | |
9bec9b13 | 616 | return false; |
9991ae78 CW |
617 | } |
618 | } | |
b7884eb4 | 619 | |
baba6e57 | 620 | ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); |
11caf551 | 621 | |
baba6e57 DCS |
622 | ENGINE_WRITE(engine, RING_HEAD, 0); |
623 | ENGINE_WRITE(engine, RING_TAIL, 0); | |
8187a2b7 | 624 | |
11caf551 | 625 | /* The ring must be empty before it is disabled */ |
baba6e57 | 626 | ENGINE_WRITE(engine, RING_CTL, 0); |
11caf551 | 627 | |
baba6e57 | 628 | return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; |
9991ae78 | 629 | } |
8187a2b7 | 630 | |
79ffac85 | 631 | static int xcs_resume(struct intel_engine_cs *engine) |
9991ae78 | 632 | { |
c033666a | 633 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 634 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
635 | int ret = 0; |
636 | ||
79ffac85 CW |
637 | GEM_TRACE("%s: ring:{HEAD:%04x, TAIL:%04x}\n", |
638 | engine->name, ring->head, ring->tail); | |
639 | ||
baba6e57 | 640 | intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); |
9991ae78 | 641 | |
0bc40be8 | 642 | if (!stop_ring(engine)) { |
9991ae78 | 643 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
644 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
645 | "ctl %08x head %08x tail %08x start %08x\n", | |
646 | engine->name, | |
baba6e57 DCS |
647 | ENGINE_READ(engine, RING_CTL), |
648 | ENGINE_READ(engine, RING_HEAD), | |
649 | ENGINE_READ(engine, RING_TAIL), | |
650 | ENGINE_READ(engine, RING_START)); | |
8187a2b7 | 651 | |
0bc40be8 | 652 | if (!stop_ring(engine)) { |
6fd0d56e CW |
653 | DRM_ERROR("failed to set %s head to zero " |
654 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 | 655 | engine->name, |
baba6e57 DCS |
656 | ENGINE_READ(engine, RING_CTL), |
657 | ENGINE_READ(engine, RING_HEAD), | |
658 | ENGINE_READ(engine, RING_TAIL), | |
659 | ENGINE_READ(engine, RING_START)); | |
9991ae78 CW |
660 | ret = -EIO; |
661 | goto out; | |
6fd0d56e | 662 | } |
8187a2b7 ZN |
663 | } |
664 | ||
3177659a | 665 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 666 | ring_setup_phys_status_page(engine); |
3177659a | 667 | else |
060f2322 | 668 | ring_setup_status_page(engine); |
9991ae78 | 669 | |
ad07dfcd | 670 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 671 | |
ece4a17d | 672 | /* Enforce ordering by reading HEAD register back */ |
baba6e57 | 673 | ENGINE_READ(engine, RING_HEAD); |
ece4a17d | 674 | |
0d8957c8 DV |
675 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
676 | * registers with the above sequence (the readback of the HEAD registers | |
677 | * also enforces ordering), otherwise the hw might lose the new ring | |
678 | * register values. */ | |
baba6e57 | 679 | ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); |
95468892 CW |
680 | |
681 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
baba6e57 | 682 | if (ENGINE_READ(engine, RING_HEAD)) |
8177e112 | 683 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
baba6e57 | 684 | engine->name, ENGINE_READ(engine, RING_HEAD)); |
821ed7df | 685 | |
41d37680 CW |
686 | /* Check that the ring offsets point within the ring! */ |
687 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
688 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 689 | intel_ring_update_space(ring); |
b7f21899 CW |
690 | |
691 | /* First wake the ring up to an empty/idle ring */ | |
baba6e57 DCS |
692 | ENGINE_WRITE(engine, RING_HEAD, ring->head); |
693 | ENGINE_WRITE(engine, RING_TAIL, ring->head); | |
694 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
95468892 | 695 | |
baba6e57 | 696 | ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 697 | |
8187a2b7 | 698 | /* If the head is still not zero, the ring is dead */ |
baba6e57 | 699 | if (intel_wait_for_register(engine->uncore, |
97a04e0d | 700 | RING_CTL(engine->mmio_base), |
f42bb651 CW |
701 | RING_VALID, RING_VALID, |
702 | 50)) { | |
e74cfed5 | 703 | DRM_ERROR("%s initialization failed " |
821ed7df | 704 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 | 705 | engine->name, |
baba6e57 DCS |
706 | ENGINE_READ(engine, RING_CTL), |
707 | ENGINE_READ(engine, RING_CTL) & RING_VALID, | |
708 | ENGINE_READ(engine, RING_HEAD), ring->head, | |
709 | ENGINE_READ(engine, RING_TAIL), ring->tail, | |
710 | ENGINE_READ(engine, RING_START), | |
bde13ebd | 711 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
712 | ret = -EIO; |
713 | goto out; | |
8187a2b7 ZN |
714 | } |
715 | ||
7836cd02 | 716 | if (INTEL_GEN(dev_priv) > 2) |
baba6e57 DCS |
717 | ENGINE_WRITE(engine, |
718 | RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); | |
7836cd02 | 719 | |
b7f21899 CW |
720 | /* Now awake, let it get started */ |
721 | if (ring->tail != ring->head) { | |
baba6e57 DCS |
722 | ENGINE_WRITE(engine, RING_TAIL, ring->tail); |
723 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
b7f21899 CW |
724 | } |
725 | ||
d6fee0de | 726 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 727 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 728 | out: |
baba6e57 | 729 | intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); |
b7884eb4 DV |
730 | |
731 | return ret; | |
8187a2b7 ZN |
732 | } |
733 | ||
eb8d0f5a | 734 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 735 | { |
3f6e9822 | 736 | intel_engine_stop_cs(engine); |
5adfb772 CW |
737 | } |
738 | ||
eb8d0f5a | 739 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 740 | { |
eb8d0f5a CW |
741 | struct i915_request *pos, *rq; |
742 | unsigned long flags; | |
b3ee09a4 | 743 | u32 head; |
5adfb772 | 744 | |
eb8d0f5a | 745 | rq = NULL; |
422d7df4 CW |
746 | spin_lock_irqsave(&engine->active.lock, flags); |
747 | list_for_each_entry(pos, &engine->active.requests, sched.link) { | |
5013eb8c | 748 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
749 | rq = pos; |
750 | break; | |
751 | } | |
b3ee09a4 | 752 | } |
67e64564 CW |
753 | |
754 | /* | |
eb8d0f5a | 755 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 756 | * |
eb8d0f5a CW |
757 | * Users of client default contexts do not rely on logical |
758 | * state preserved between batches so it is safe to execute | |
759 | * queued requests following the hang. Non default contexts | |
760 | * rely on preserved state, so skipping a batch loses the | |
761 | * evolution of the state and it needs to be considered corrupted. | |
762 | * Executing more queued batches on top of corrupted state is | |
763 | * risky. But we take the risk by trying to advance through | |
764 | * the queued requests in order to make the client behaviour | |
765 | * more predictable around resets, by not throwing away random | |
766 | * amount of batches it has prepared for execution. Sophisticated | |
767 | * clients can use gem_reset_stats_ioctl and dma fence status | |
768 | * (exported via sync_file info ioctl on explicit fences) to observe | |
769 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 770 | * |
eb8d0f5a CW |
771 | * The context ban, and ultimately the client ban, mechanism are safety |
772 | * valves if client submission ends up resulting in nothing more than | |
773 | * subsequent hangs. | |
c0dcb203 | 774 | */ |
eb8d0f5a | 775 | |
b3ee09a4 | 776 | if (rq) { |
eb8d0f5a CW |
777 | /* |
778 | * Try to restore the logical GPU state to match the | |
779 | * continuation of the request queue. If we skip the | |
780 | * context/PD restore, then the next request may try to execute | |
781 | * assuming that its context is valid and loaded on the GPU and | |
782 | * so may try to access invalid memory, prompting repeated GPU | |
783 | * hangs. | |
784 | * | |
785 | * If the request was guilty, we still restore the logical | |
786 | * state in case the next request requires it (e.g. the | |
787 | * aliasing ppgtt), but skip over the hung batch. | |
788 | * | |
789 | * If the request was innocent, we try to replay the request | |
790 | * with the restored context. | |
791 | */ | |
792 | i915_reset_request(rq, stalled); | |
793 | ||
794 | GEM_BUG_ON(rq->ring != engine->buffer); | |
795 | head = rq->head; | |
796 | } else { | |
797 | head = engine->buffer->tail; | |
c0dcb203 | 798 | } |
eb8d0f5a CW |
799 | engine->buffer->head = intel_ring_wrap(engine->buffer, head); |
800 | ||
422d7df4 | 801 | spin_unlock_irqrestore(&engine->active.lock, flags); |
821ed7df CW |
802 | } |
803 | ||
5adfb772 CW |
804 | static void reset_finish(struct intel_engine_cs *engine) |
805 | { | |
806 | } | |
807 | ||
e61e0f51 | 808 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
809 | { |
810 | int ret; | |
811 | ||
452420d2 | 812 | ret = intel_engine_emit_ctx_wa(rq); |
8f0e2b9d DV |
813 | if (ret != 0) |
814 | return ret; | |
815 | ||
e61e0f51 | 816 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 817 | if (ret) |
e26e1b97 | 818 | return ret; |
8f0e2b9d | 819 | |
e26e1b97 | 820 | return 0; |
8f0e2b9d DV |
821 | } |
822 | ||
79ffac85 | 823 | static int rcs_resume(struct intel_engine_cs *engine) |
8187a2b7 | 824 | { |
c033666a | 825 | struct drm_i915_private *dev_priv = engine->i915; |
a69ffdbf | 826 | |
9ce9bdb0 CW |
827 | /* |
828 | * Disable CONSTANT_BUFFER before it is loaded from the context | |
829 | * image. For as it is loaded, it is executed and the stored | |
830 | * address may no longer be valid, leading to a GPU hang. | |
831 | * | |
832 | * This imposes the requirement that userspace reload their | |
833 | * CONSTANT_BUFFER on every batch, fortunately a requirement | |
834 | * they are already accustomed to from before contexts were | |
835 | * enabled. | |
836 | */ | |
837 | if (IS_GEN(dev_priv, 4)) | |
838 | I915_WRITE(ECOSKPD, | |
839 | _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); | |
840 | ||
61a563a2 | 841 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 842 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 843 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
844 | |
845 | /* We need to disable the AsyncFlip performance optimisations in order | |
846 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
847 | * programmed to '1' on all products. | |
8693a824 | 848 | * |
2441f877 | 849 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 850 | */ |
00690008 | 851 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
852 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
853 | ||
f05bb0c7 | 854 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 855 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 856 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 857 | I915_WRITE(GFX_MODE, |
aa83e30d | 858 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 859 | |
01fa0302 | 860 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 861 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 862 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 863 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 864 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 865 | |
cf819eff | 866 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
867 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
868 | * "If this bit is set, STCunit will have LRA as replacement | |
869 | * policy. [...] This bit must be reset. LRA replacement | |
870 | * policy is not supported." | |
871 | */ | |
872 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 873 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
874 | } |
875 | ||
00690008 | 876 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 877 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 878 | |
79ffac85 | 879 | return xcs_resume(engine); |
8187a2b7 ZN |
880 | } |
881 | ||
27a5f61b CW |
882 | static void cancel_requests(struct intel_engine_cs *engine) |
883 | { | |
e61e0f51 | 884 | struct i915_request *request; |
27a5f61b CW |
885 | unsigned long flags; |
886 | ||
422d7df4 | 887 | spin_lock_irqsave(&engine->active.lock, flags); |
27a5f61b CW |
888 | |
889 | /* Mark all submitted requests as skipped. */ | |
422d7df4 | 890 | list_for_each_entry(request, &engine->active.requests, sched.link) { |
5013eb8c CW |
891 | if (!i915_request_signaled(request)) |
892 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 893 | |
5013eb8c | 894 | i915_request_mark_complete(request); |
27a5f61b | 895 | } |
3800960a | 896 | |
27a5f61b CW |
897 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
898 | ||
422d7df4 | 899 | spin_unlock_irqrestore(&engine->active.lock, flags); |
27a5f61b CW |
900 | } |
901 | ||
e61e0f51 | 902 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d | 903 | { |
e61e0f51 | 904 | i915_request_submit(request); |
d55ac5bf | 905 | |
baba6e57 DCS |
906 | ENGINE_WRITE(request->engine, RING_TAIL, |
907 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
908 | } |
909 | ||
e1a73a54 | 910 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 911 | { |
5013eb8c CW |
912 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
913 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
914 | ||
caa5915b CW |
915 | *cs++ = MI_FLUSH; |
916 | ||
5013eb8c CW |
917 | *cs++ = MI_STORE_DWORD_INDEX; |
918 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
919 | *cs++ = rq->fence.seqno; | |
920 | ||
73dec95e | 921 | *cs++ = MI_USER_INTERRUPT; |
519a0194 | 922 | *cs++ = MI_NOOP; |
1ec14ad3 | 923 | |
e61e0f51 CW |
924 | rq->tail = intel_ring_offset(rq, cs); |
925 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
926 | |
927 | return cs; | |
1ec14ad3 | 928 | } |
98f29e8d | 929 | |
835051d3 | 930 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 931 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 932 | { |
835051d3 CW |
933 | int i; |
934 | ||
5013eb8c CW |
935 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
936 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
937 | ||
835051d3 CW |
938 | *cs++ = MI_FLUSH; |
939 | ||
940 | BUILD_BUG_ON(GEN5_WA_STORES < 1); | |
941 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
942 | *cs++ = MI_STORE_DWORD_INDEX; | |
b300fde8 CW |
943 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
944 | *cs++ = rq->fence.seqno; | |
835051d3 CW |
945 | } |
946 | ||
947 | *cs++ = MI_USER_INTERRUPT; | |
948 | ||
949 | rq->tail = intel_ring_offset(rq, cs); | |
950 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
951 | |
952 | return cs; | |
c6df541c | 953 | } |
835051d3 | 954 | #undef GEN5_WA_STORES |
c6df541c | 955 | |
31bb59cc CW |
956 | static void |
957 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 958 | { |
31bb59cc | 959 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
960 | } |
961 | ||
962 | static void | |
31bb59cc | 963 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 964 | { |
31bb59cc | 965 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
966 | } |
967 | ||
31bb59cc CW |
968 | static void |
969 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 970 | { |
baba6e57 | 971 | engine->i915->irq_mask &= ~engine->irq_enable_mask; |
9d9523d8 PZ |
972 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
973 | intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); | |
62fdfeaf EA |
974 | } |
975 | ||
8187a2b7 | 976 | static void |
31bb59cc | 977 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 978 | { |
baba6e57 | 979 | engine->i915->irq_mask |= engine->irq_enable_mask; |
9d9523d8 | 980 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
62fdfeaf EA |
981 | } |
982 | ||
31bb59cc CW |
983 | static void |
984 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 985 | { |
e44d62d1 | 986 | struct drm_i915_private *i915 = engine->i915; |
c2798b19 | 987 | |
e44d62d1 TU |
988 | i915->irq_mask &= ~engine->irq_enable_mask; |
989 | intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); | |
990 | ENGINE_POSTING_READ16(engine, RING_IMR); | |
c2798b19 CW |
991 | } |
992 | ||
993 | static void | |
31bb59cc | 994 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 995 | { |
4f5fd91f | 996 | struct drm_i915_private *i915 = engine->i915; |
c2798b19 | 997 | |
4f5fd91f TU |
998 | i915->irq_mask |= engine->irq_enable_mask; |
999 | intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); | |
c2798b19 CW |
1000 | } |
1001 | ||
b72f3acb | 1002 | static int |
e61e0f51 | 1003 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 1004 | { |
73dec95e | 1005 | u32 *cs; |
b72f3acb | 1006 | |
e61e0f51 | 1007 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1008 | if (IS_ERR(cs)) |
1009 | return PTR_ERR(cs); | |
b72f3acb | 1010 | |
73dec95e TU |
1011 | *cs++ = MI_FLUSH; |
1012 | *cs++ = MI_NOOP; | |
e61e0f51 | 1013 | intel_ring_advance(rq, cs); |
b72f3acb | 1014 | return 0; |
d1b851fc ZN |
1015 | } |
1016 | ||
31bb59cc CW |
1017 | static void |
1018 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1019 | { |
baba6e57 DCS |
1020 | ENGINE_WRITE(engine, RING_IMR, |
1021 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
476af9c2 CW |
1022 | |
1023 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1024 | ENGINE_POSTING_READ(engine, RING_IMR); |
476af9c2 | 1025 | |
baba6e57 | 1026 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
0f46832f CW |
1027 | } |
1028 | ||
1029 | static void | |
31bb59cc | 1030 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1031 | { |
baba6e57 DCS |
1032 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); |
1033 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); | |
d1b851fc ZN |
1034 | } |
1035 | ||
31bb59cc CW |
1036 | static void |
1037 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1038 | { |
baba6e57 | 1039 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1040 | |
1041 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1042 | ENGINE_POSTING_READ(engine, RING_IMR); |
e4fc69f2 | 1043 | |
baba6e57 | 1044 | gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask); |
a19d2933 BW |
1045 | } |
1046 | ||
1047 | static void | |
31bb59cc | 1048 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1049 | { |
baba6e57 DCS |
1050 | ENGINE_WRITE(engine, RING_IMR, ~0); |
1051 | gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask); | |
a19d2933 BW |
1052 | } |
1053 | ||
d1b851fc | 1054 | static int |
e61e0f51 | 1055 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1056 | u64 offset, u32 length, |
1057 | unsigned int dispatch_flags) | |
d1b851fc | 1058 | { |
73dec95e | 1059 | u32 *cs; |
78501eac | 1060 | |
e61e0f51 | 1061 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1062 | if (IS_ERR(cs)) |
1063 | return PTR_ERR(cs); | |
e1f99ce6 | 1064 | |
73dec95e TU |
1065 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1066 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1067 | *cs++ = offset; | |
e61e0f51 | 1068 | intel_ring_advance(rq, cs); |
78501eac | 1069 | |
d1b851fc ZN |
1070 | return 0; |
1071 | } | |
1072 | ||
b45305fc | 1073 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1074 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1075 | #define I830_TLB_ENTRIES (2) |
1076 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1077 | static int |
e61e0f51 | 1078 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1079 | u64 offset, u32 len, |
1080 | unsigned int dispatch_flags) | |
62fdfeaf | 1081 | { |
db56f974 | 1082 | u32 *cs, cs_offset = intel_gt_scratch_offset(rq->engine->gt); |
51797499 | 1083 | |
db56f974 | 1084 | GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); |
62fdfeaf | 1085 | |
e61e0f51 | 1086 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1087 | if (IS_ERR(cs)) |
1088 | return PTR_ERR(cs); | |
62fdfeaf | 1089 | |
c4d69da1 | 1090 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1091 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1092 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1093 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1094 | *cs++ = cs_offset; | |
1095 | *cs++ = 0xdeadbeef; | |
1096 | *cs++ = MI_NOOP; | |
e61e0f51 | 1097 | intel_ring_advance(rq, cs); |
b45305fc | 1098 | |
8e004efc | 1099 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1100 | if (len > I830_BATCH_LIMIT) |
1101 | return -ENOSPC; | |
1102 | ||
e61e0f51 | 1103 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1104 | if (IS_ERR(cs)) |
1105 | return PTR_ERR(cs); | |
c4d69da1 CW |
1106 | |
1107 | /* Blit the batch (which has now all relocs applied) to the | |
1108 | * stable batch scratch bo area (so that the CS never | |
1109 | * stumbles over its tlb invalidation bug) ... | |
1110 | */ | |
73dec95e TU |
1111 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1112 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1113 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1114 | *cs++ = cs_offset; | |
1115 | *cs++ = 4096; | |
1116 | *cs++ = offset; | |
1117 | ||
1118 | *cs++ = MI_FLUSH; | |
1119 | *cs++ = MI_NOOP; | |
e61e0f51 | 1120 | intel_ring_advance(rq, cs); |
b45305fc DV |
1121 | |
1122 | /* ... and execute it. */ | |
c4d69da1 | 1123 | offset = cs_offset; |
b45305fc | 1124 | } |
e1f99ce6 | 1125 | |
e61e0f51 | 1126 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1127 | if (IS_ERR(cs)) |
1128 | return PTR_ERR(cs); | |
c4d69da1 | 1129 | |
73dec95e TU |
1130 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1131 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1132 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1133 | intel_ring_advance(rq, cs); |
c4d69da1 | 1134 | |
fb3256da DV |
1135 | return 0; |
1136 | } | |
1137 | ||
1138 | static int | |
e61e0f51 | 1139 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1140 | u64 offset, u32 len, |
1141 | unsigned int dispatch_flags) | |
fb3256da | 1142 | { |
73dec95e | 1143 | u32 *cs; |
fb3256da | 1144 | |
e61e0f51 | 1145 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1146 | if (IS_ERR(cs)) |
1147 | return PTR_ERR(cs); | |
fb3256da | 1148 | |
73dec95e TU |
1149 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1150 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1151 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1152 | intel_ring_advance(rq, cs); |
62fdfeaf | 1153 | |
62fdfeaf EA |
1154 | return 0; |
1155 | } | |
1156 | ||
5503cb0d | 1157 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1158 | { |
57e88531 | 1159 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1160 | unsigned int flags; |
8305216f | 1161 | void *addr; |
7ba717cf TD |
1162 | int ret; |
1163 | ||
09c5ab38 CW |
1164 | if (atomic_fetch_inc(&ring->pin_count)) |
1165 | return 0; | |
7ba717cf | 1166 | |
f0c02c1b | 1167 | ret = intel_timeline_pin(ring->timeline); |
5013eb8c | 1168 | if (ret) |
09c5ab38 | 1169 | goto err_unpin; |
5013eb8c | 1170 | |
d3ef1af6 | 1171 | flags = PIN_GLOBAL; |
496bcce3 JB |
1172 | |
1173 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1174 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1175 | ||
9d80841e | 1176 | if (vma->obj->stolen) |
57e88531 | 1177 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1178 | else |
1179 | flags |= PIN_HIGH; | |
def0c5f6 | 1180 | |
7a859c65 | 1181 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1182 | if (unlikely(ret)) |
09c5ab38 | 1183 | goto err_timeline; |
def0c5f6 | 1184 | |
9d80841e | 1185 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1186 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1187 | else | |
09c5ab38 CW |
1188 | addr = i915_gem_object_pin_map(vma->obj, |
1189 | i915_coherent_map_type(vma->vm->i915)); | |
5013eb8c CW |
1190 | if (IS_ERR(addr)) { |
1191 | ret = PTR_ERR(addr); | |
09c5ab38 | 1192 | goto err_ring; |
5013eb8c | 1193 | } |
7ba717cf | 1194 | |
3d574a6b CW |
1195 | vma->obj->pin_global++; |
1196 | ||
09c5ab38 | 1197 | GEM_BUG_ON(ring->vaddr); |
32c04f16 | 1198 | ring->vaddr = addr; |
09c5ab38 | 1199 | |
cba17e5d | 1200 | GEM_TRACE("ring:%llx pin\n", ring->timeline->fence_context); |
7ba717cf | 1201 | return 0; |
d2cad535 | 1202 | |
09c5ab38 | 1203 | err_ring: |
57e88531 | 1204 | i915_vma_unpin(vma); |
09c5ab38 | 1205 | err_timeline: |
f0c02c1b | 1206 | intel_timeline_unpin(ring->timeline); |
09c5ab38 CW |
1207 | err_unpin: |
1208 | atomic_dec(&ring->pin_count); | |
5013eb8c | 1209 | return ret; |
7ba717cf TD |
1210 | } |
1211 | ||
e6ba9992 CW |
1212 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1213 | { | |
41d37680 CW |
1214 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1215 | ||
e6ba9992 CW |
1216 | ring->tail = tail; |
1217 | ring->head = tail; | |
1218 | ring->emit = tail; | |
1219 | intel_ring_update_space(ring); | |
1220 | } | |
1221 | ||
aad29fbb CW |
1222 | void intel_ring_unpin(struct intel_ring *ring) |
1223 | { | |
09c5ab38 CW |
1224 | if (!atomic_dec_and_test(&ring->pin_count)) |
1225 | return; | |
aad29fbb | 1226 | |
cba17e5d CW |
1227 | GEM_TRACE("ring:%llx unpin\n", ring->timeline->fence_context); |
1228 | ||
e6ba9992 CW |
1229 | /* Discard any unused bytes beyond that submitted to hw. */ |
1230 | intel_ring_reset(ring, ring->tail); | |
1231 | ||
09c5ab38 | 1232 | GEM_BUG_ON(!ring->vma); |
cffa1eb8 | 1233 | i915_vma_unset_ggtt_write(ring->vma); |
9d80841e | 1234 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1235 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1236 | else |
1237 | i915_gem_object_unpin_map(ring->vma->obj); | |
09c5ab38 CW |
1238 | |
1239 | GEM_BUG_ON(!ring->vaddr); | |
aad29fbb CW |
1240 | ring->vaddr = NULL; |
1241 | ||
3d574a6b | 1242 | ring->vma->obj->pin_global--; |
57e88531 | 1243 | i915_vma_unpin(ring->vma); |
5013eb8c | 1244 | |
f0c02c1b | 1245 | intel_timeline_unpin(ring->timeline); |
2919d291 OM |
1246 | } |
1247 | ||
db45fb5b | 1248 | static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) |
62fdfeaf | 1249 | { |
db45fb5b TU |
1250 | struct i915_address_space *vm = &ggtt->vm; |
1251 | struct drm_i915_private *i915 = vm->i915; | |
05394f39 | 1252 | struct drm_i915_gem_object *obj; |
57e88531 | 1253 | struct i915_vma *vma; |
62fdfeaf | 1254 | |
db45fb5b | 1255 | obj = i915_gem_object_create_stolen(i915, size); |
c58b735f | 1256 | if (!obj) |
db45fb5b | 1257 | obj = i915_gem_object_create_internal(i915, size); |
57e88531 CW |
1258 | if (IS_ERR(obj)) |
1259 | return ERR_CAST(obj); | |
8187a2b7 | 1260 | |
250f8c81 JB |
1261 | /* |
1262 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1263 | * if supported by the platform's GGTT. | |
1264 | */ | |
1265 | if (vm->has_read_only) | |
3e977ac6 | 1266 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1267 | |
250f8c81 | 1268 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1269 | if (IS_ERR(vma)) |
1270 | goto err; | |
1271 | ||
1272 | return vma; | |
e3efda49 | 1273 | |
57e88531 CW |
1274 | err: |
1275 | i915_gem_object_put(obj); | |
1276 | return vma; | |
e3efda49 CW |
1277 | } |
1278 | ||
7e37f889 | 1279 | struct intel_ring * |
65fcb806 | 1280 | intel_engine_create_ring(struct intel_engine_cs *engine, |
f0c02c1b | 1281 | struct intel_timeline *timeline, |
65fcb806 | 1282 | int size) |
01101fa7 | 1283 | { |
db45fb5b | 1284 | struct drm_i915_private *i915 = engine->i915; |
7e37f889 | 1285 | struct intel_ring *ring; |
57e88531 | 1286 | struct i915_vma *vma; |
01101fa7 | 1287 | |
8f942018 | 1288 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1289 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1290 | |
01101fa7 | 1291 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1292 | if (!ring) |
01101fa7 CW |
1293 | return ERR_PTR(-ENOMEM); |
1294 | ||
65baf0ef | 1295 | kref_init(&ring->ref); |
675d9ad7 | 1296 | INIT_LIST_HEAD(&ring->request_list); |
f0c02c1b | 1297 | ring->timeline = intel_timeline_get(timeline); |
675d9ad7 | 1298 | |
01101fa7 CW |
1299 | ring->size = size; |
1300 | /* Workaround an erratum on the i830 which causes a hang if | |
1301 | * the TAIL pointer points to within the last 2 cachelines | |
1302 | * of the buffer. | |
1303 | */ | |
1304 | ring->effective_size = size; | |
db45fb5b | 1305 | if (IS_I830(i915) || IS_I845G(i915)) |
01101fa7 CW |
1306 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1307 | ||
01101fa7 CW |
1308 | intel_ring_update_space(ring); |
1309 | ||
db45fb5b | 1310 | vma = create_ring_vma(engine->gt->ggtt, size); |
57e88531 | 1311 | if (IS_ERR(vma)) { |
01101fa7 | 1312 | kfree(ring); |
57e88531 | 1313 | return ERR_CAST(vma); |
01101fa7 | 1314 | } |
57e88531 | 1315 | ring->vma = vma; |
01101fa7 CW |
1316 | |
1317 | return ring; | |
1318 | } | |
1319 | ||
65baf0ef | 1320 | void intel_ring_free(struct kref *ref) |
01101fa7 | 1321 | { |
65baf0ef | 1322 | struct intel_ring *ring = container_of(ref, typeof(*ring), ref); |
f8a7fde4 CW |
1323 | |
1324 | i915_vma_close(ring->vma); | |
c017cf6b | 1325 | i915_vma_put(ring->vma); |
f8a7fde4 | 1326 | |
f0c02c1b | 1327 | intel_timeline_put(ring->timeline); |
01101fa7 CW |
1328 | kfree(ring); |
1329 | } | |
1330 | ||
c4d52feb CW |
1331 | static void __ring_context_fini(struct intel_context *ce) |
1332 | { | |
c4d52feb CW |
1333 | i915_gem_object_put(ce->state->obj); |
1334 | } | |
1335 | ||
4c5896dc | 1336 | static void ring_context_destroy(struct kref *ref) |
1fc44d9b | 1337 | { |
4c5896dc CW |
1338 | struct intel_context *ce = container_of(ref, typeof(*ce), ref); |
1339 | ||
08819549 | 1340 | GEM_BUG_ON(intel_context_is_pinned(ce)); |
1fc44d9b | 1341 | |
c4d52feb CW |
1342 | if (ce->state) |
1343 | __ring_context_fini(ce); | |
efe79d48 | 1344 | |
c4d52feb | 1345 | intel_context_free(ce); |
1fc44d9b CW |
1346 | } |
1347 | ||
a2bbf714 CW |
1348 | static int __context_pin_ppgtt(struct i915_gem_context *ctx) |
1349 | { | |
e568ac38 | 1350 | struct i915_address_space *vm; |
a2bbf714 CW |
1351 | int err = 0; |
1352 | ||
e568ac38 CW |
1353 | vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm; |
1354 | if (vm) | |
1355 | err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); | |
a2bbf714 CW |
1356 | |
1357 | return err; | |
1358 | } | |
1359 | ||
1360 | static void __context_unpin_ppgtt(struct i915_gem_context *ctx) | |
1361 | { | |
e568ac38 | 1362 | struct i915_address_space *vm; |
a2bbf714 | 1363 | |
e568ac38 CW |
1364 | vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm; |
1365 | if (vm) | |
1366 | gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); | |
a2bbf714 CW |
1367 | } |
1368 | ||
4dc84b77 | 1369 | static void ring_context_unpin(struct intel_context *ce) |
d901e8e6 | 1370 | { |
a2bbf714 | 1371 | __context_unpin_ppgtt(ce->gem_context); |
e8a9c58f CW |
1372 | } |
1373 | ||
3204c343 CW |
1374 | static struct i915_vma * |
1375 | alloc_context_vma(struct intel_engine_cs *engine) | |
1376 | { | |
1377 | struct drm_i915_private *i915 = engine->i915; | |
1378 | struct drm_i915_gem_object *obj; | |
1379 | struct i915_vma *vma; | |
d2b4b979 | 1380 | int err; |
3204c343 | 1381 | |
8475355f | 1382 | obj = i915_gem_object_create_shmem(i915, engine->context_size); |
3204c343 CW |
1383 | if (IS_ERR(obj)) |
1384 | return ERR_CAST(obj); | |
1385 | ||
a679f58d CW |
1386 | /* |
1387 | * Try to make the context utilize L3 as well as LLC. | |
1388 | * | |
1389 | * On VLV we don't have L3 controls in the PTEs so we | |
1390 | * shouldn't touch the cache level, especially as that | |
1391 | * would make the object snooped which might have a | |
1392 | * negative performance impact. | |
1393 | * | |
1394 | * Snooping is required on non-llc platforms in execlist | |
1395 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1396 | * get snooping anyway regardless of cache_level. | |
1397 | * | |
1398 | * This is only applicable for Ivy Bridge devices since | |
1399 | * later platforms don't have L3 control bits in the PTE. | |
1400 | */ | |
1401 | if (IS_IVYBRIDGE(i915)) | |
1402 | i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); | |
1403 | ||
d2b4b979 CW |
1404 | if (engine->default_state) { |
1405 | void *defaults, *vaddr; | |
1406 | ||
1407 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1408 | if (IS_ERR(vaddr)) { | |
1409 | err = PTR_ERR(vaddr); | |
1410 | goto err_obj; | |
1411 | } | |
1412 | ||
1413 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1414 | I915_MAP_WB); | |
1415 | if (IS_ERR(defaults)) { | |
1416 | err = PTR_ERR(defaults); | |
1417 | goto err_map; | |
1418 | } | |
1419 | ||
1420 | memcpy(vaddr, defaults, engine->context_size); | |
d2b4b979 | 1421 | i915_gem_object_unpin_map(engine->default_state); |
d2b4b979 | 1422 | |
a679f58d CW |
1423 | i915_gem_object_flush_map(obj); |
1424 | i915_gem_object_unpin_map(obj); | |
3204c343 CW |
1425 | } |
1426 | ||
ba4134a4 | 1427 | vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); |
d2b4b979 CW |
1428 | if (IS_ERR(vma)) { |
1429 | err = PTR_ERR(vma); | |
1430 | goto err_obj; | |
1431 | } | |
3204c343 CW |
1432 | |
1433 | return vma; | |
d2b4b979 CW |
1434 | |
1435 | err_map: | |
1436 | i915_gem_object_unpin_map(obj); | |
1437 | err_obj: | |
1438 | i915_gem_object_put(obj); | |
1439 | return ERR_PTR(err); | |
3204c343 CW |
1440 | } |
1441 | ||
95f697eb | 1442 | static int ring_context_pin(struct intel_context *ce) |
0cb26a8e | 1443 | { |
95f697eb | 1444 | struct intel_engine_cs *engine = ce->engine; |
1fc44d9b | 1445 | int err; |
0cb26a8e | 1446 | |
7e3d9a59 CW |
1447 | /* One ringbuffer to rule them all */ |
1448 | GEM_BUG_ON(!engine->buffer); | |
1449 | ce->ring = engine->buffer; | |
1450 | ||
63ffbcda | 1451 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1452 | struct i915_vma *vma; |
1453 | ||
1454 | vma = alloc_context_vma(engine); | |
95f697eb CW |
1455 | if (IS_ERR(vma)) |
1456 | return PTR_ERR(vma); | |
3204c343 CW |
1457 | |
1458 | ce->state = vma; | |
1459 | } | |
1460 | ||
12c255b5 | 1461 | err = intel_context_active_acquire(ce); |
d901e8e6 | 1462 | if (err) |
95f697eb | 1463 | return err; |
0cb26a8e | 1464 | |
a2bbf714 CW |
1465 | err = __context_pin_ppgtt(ce->gem_context); |
1466 | if (err) | |
ce476c80 | 1467 | goto err_active; |
a2bbf714 | 1468 | |
95f697eb | 1469 | return 0; |
266a240b | 1470 | |
ce476c80 CW |
1471 | err_active: |
1472 | intel_context_active_release(ce); | |
95f697eb | 1473 | return err; |
0cb26a8e CW |
1474 | } |
1475 | ||
9726920b CW |
1476 | static void ring_context_reset(struct intel_context *ce) |
1477 | { | |
1478 | intel_ring_reset(ce->ring, 0); | |
1479 | } | |
1480 | ||
4dc84b77 | 1481 | static const struct intel_context_ops ring_context_ops = { |
95f697eb | 1482 | .pin = ring_context_pin, |
4dc84b77 | 1483 | .unpin = ring_context_unpin, |
9726920b | 1484 | |
6eee33e8 CW |
1485 | .enter = intel_context_enter_engine, |
1486 | .exit = intel_context_exit_engine, | |
1487 | ||
9726920b | 1488 | .reset = ring_context_reset, |
4dc84b77 CW |
1489 | .destroy = ring_context_destroy, |
1490 | }; | |
1491 | ||
ab53497b | 1492 | static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt) |
b3ee09a4 CW |
1493 | { |
1494 | const struct intel_engine_cs * const engine = rq->engine; | |
1495 | u32 *cs; | |
1496 | ||
1497 | cs = intel_ring_begin(rq, 6); | |
1498 | if (IS_ERR(cs)) | |
1499 | return PTR_ERR(cs); | |
1500 | ||
1501 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1502 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); |
b3ee09a4 CW |
1503 | *cs++ = PP_DIR_DCLV_2G; |
1504 | ||
1505 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1506 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
b5b7bef9 | 1507 | *cs++ = ppgtt->pd->base.ggtt_offset << 10; |
b3ee09a4 CW |
1508 | |
1509 | intel_ring_advance(rq, cs); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
d9d117e4 CW |
1514 | static int flush_pd_dir(struct i915_request *rq) |
1515 | { | |
1516 | const struct intel_engine_cs * const engine = rq->engine; | |
1517 | u32 *cs; | |
1518 | ||
1519 | cs = intel_ring_begin(rq, 4); | |
1520 | if (IS_ERR(cs)) | |
1521 | return PTR_ERR(cs); | |
1522 | ||
1523 | /* Stall until the page table load is complete */ | |
1524 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
baba6e57 | 1525 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
db56f974 | 1526 | *cs++ = intel_gt_scratch_offset(rq->engine->gt); |
d9d117e4 CW |
1527 | *cs++ = MI_NOOP; |
1528 | ||
1529 | intel_ring_advance(rq, cs); | |
1530 | return 0; | |
1531 | } | |
1532 | ||
e61e0f51 | 1533 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1534 | { |
1535 | struct drm_i915_private *i915 = rq->i915; | |
1536 | struct intel_engine_cs *engine = rq->engine; | |
1537 | enum intel_engine_id id; | |
8a68d464 CW |
1538 | const int num_engines = |
1539 | IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; | |
1fc719d1 | 1540 | bool force_restore = false; |
8911a31c CW |
1541 | int len; |
1542 | u32 *cs; | |
1543 | ||
1544 | flags |= MI_MM_SPACE_GTT; | |
1545 | if (IS_HASWELL(i915)) | |
1546 | /* These flags are for resource streamer on HSW+ */ | |
1547 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1548 | else | |
1215d28e | 1549 | /* We need to save the extended state for powersaving modes */ |
8911a31c CW |
1550 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; |
1551 | ||
1552 | len = 4; | |
cf819eff | 1553 | if (IS_GEN(i915, 7)) |
8a68d464 | 1554 | len += 2 + (num_engines ? 4 * num_engines + 6 : 0); |
1215d28e CW |
1555 | else if (IS_GEN(i915, 5)) |
1556 | len += 2; | |
1fc719d1 CW |
1557 | if (flags & MI_FORCE_RESTORE) { |
1558 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1559 | flags &= ~MI_FORCE_RESTORE; | |
1560 | force_restore = true; | |
1561 | len += 2; | |
1562 | } | |
8911a31c CW |
1563 | |
1564 | cs = intel_ring_begin(rq, len); | |
1565 | if (IS_ERR(cs)) | |
1566 | return PTR_ERR(cs); | |
1567 | ||
1568 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1569 | if (IS_GEN(i915, 7)) { |
8911a31c | 1570 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
8a68d464 | 1571 | if (num_engines) { |
8911a31c CW |
1572 | struct intel_engine_cs *signaller; |
1573 | ||
8a68d464 | 1574 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1575 | for_each_engine(signaller, i915, id) { |
1576 | if (signaller == engine) | |
1577 | continue; | |
1578 | ||
1579 | *cs++ = i915_mmio_reg_offset( | |
1580 | RING_PSMI_CTL(signaller->mmio_base)); | |
1581 | *cs++ = _MASKED_BIT_ENABLE( | |
1582 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1583 | } | |
1584 | } | |
1215d28e CW |
1585 | } else if (IS_GEN(i915, 5)) { |
1586 | /* | |
1587 | * This w/a is only listed for pre-production ilk a/b steppings, | |
1588 | * but is also mentioned for programming the powerctx. To be | |
1589 | * safe, just apply the workaround; we do not use SyncFlush so | |
1590 | * this should never take effect and so be a no-op! | |
1591 | */ | |
1592 | *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; | |
8911a31c CW |
1593 | } |
1594 | ||
1fc719d1 CW |
1595 | if (force_restore) { |
1596 | /* | |
1597 | * The HW doesn't handle being told to restore the current | |
1598 | * context very well. Quite often it likes goes to go off and | |
1599 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1600 | * A very simple fix to force the reload is to simply switch | |
1601 | * away from the current context and back again. | |
1602 | * | |
1603 | * Note that the kernel_context will contain random state | |
1604 | * following the INHIBIT_RESTORE. We accept this since we | |
1605 | * never use the kernel_context state; it is merely a | |
1606 | * placeholder we use to flush other contexts. | |
1607 | */ | |
1608 | *cs++ = MI_SET_CONTEXT; | |
9dbfea98 | 1609 | *cs++ = i915_ggtt_offset(engine->kernel_context->state) | |
1fc719d1 CW |
1610 | MI_MM_SPACE_GTT | |
1611 | MI_RESTORE_INHIBIT; | |
1612 | } | |
1613 | ||
8911a31c CW |
1614 | *cs++ = MI_NOOP; |
1615 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1616 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1617 | /* |
1618 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1619 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1620 | */ | |
1621 | *cs++ = MI_NOOP; | |
1622 | ||
cf819eff | 1623 | if (IS_GEN(i915, 7)) { |
8a68d464 | 1624 | if (num_engines) { |
8911a31c CW |
1625 | struct intel_engine_cs *signaller; |
1626 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1627 | ||
8a68d464 | 1628 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1629 | for_each_engine(signaller, i915, id) { |
1630 | if (signaller == engine) | |
1631 | continue; | |
1632 | ||
1633 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1634 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1635 | *cs++ = _MASKED_BIT_DISABLE( | |
1636 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1637 | } | |
1638 | ||
1639 | /* Insert a delay before the next switch! */ | |
1640 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1641 | *cs++ = i915_mmio_reg_offset(last_reg); | |
db56f974 | 1642 | *cs++ = intel_gt_scratch_offset(rq->engine->gt); |
8911a31c CW |
1643 | *cs++ = MI_NOOP; |
1644 | } | |
1645 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1215d28e CW |
1646 | } else if (IS_GEN(i915, 5)) { |
1647 | *cs++ = MI_SUSPEND_FLUSH; | |
8911a31c CW |
1648 | } |
1649 | ||
1650 | intel_ring_advance(rq, cs); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
e61e0f51 | 1655 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1656 | { |
1657 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1658 | int i; | |
1659 | ||
1660 | if (!remap_info) | |
1661 | return 0; | |
1662 | ||
1663 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1664 | if (IS_ERR(cs)) | |
1665 | return PTR_ERR(cs); | |
1666 | ||
1667 | /* | |
1668 | * Note: We do not worry about the concurrent register cacheline hang | |
1669 | * here because no other code should access these registers other than | |
1670 | * at initialization time. | |
1671 | */ | |
1672 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1673 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1674 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1675 | *cs++ = remap_info[i]; | |
1676 | } | |
1677 | *cs++ = MI_NOOP; | |
1678 | intel_ring_advance(rq, cs); | |
1679 | ||
1680 | return 0; | |
1681 | } | |
1682 | ||
e61e0f51 | 1683 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1684 | { |
1685 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 | 1686 | struct i915_gem_context *ctx = rq->gem_context; |
e568ac38 CW |
1687 | struct i915_address_space *vm = |
1688 | ctx->vm ?: &rq->i915->mm.aliasing_ppgtt->vm; | |
b3ee09a4 | 1689 | unsigned int unwind_mm = 0; |
8911a31c CW |
1690 | u32 hw_flags = 0; |
1691 | int ret, i; | |
1692 | ||
8911a31c CW |
1693 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); |
1694 | ||
e568ac38 | 1695 | if (vm) { |
ab53497b | 1696 | struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
e2a13d1b CW |
1697 | int loops; |
1698 | ||
1699 | /* | |
1700 | * Baytail takes a little more convincing that it really needs | |
1701 | * to reload the PD between contexts. It is not just a little | |
1702 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1703 | * adding a long loop around flush_pd_dir) is not as effective | |
1704 | * as reloading the PD umpteen times. 32 is derived from | |
1705 | * experimentation (gem_exec_parallel/fds) and has no good | |
1706 | * explanation. | |
1707 | */ | |
1708 | loops = 1; | |
8a68d464 | 1709 | if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) |
e2a13d1b CW |
1710 | loops = 32; |
1711 | ||
1712 | do { | |
1713 | ret = load_pd_dir(rq, ppgtt); | |
1714 | if (ret) | |
1715 | goto err; | |
1716 | } while (--loops); | |
8911a31c | 1717 | |
8a68d464 CW |
1718 | if (ppgtt->pd_dirty_engines & engine->mask) { |
1719 | unwind_mm = engine->mask; | |
1720 | ppgtt->pd_dirty_engines &= ~unwind_mm; | |
b3ee09a4 CW |
1721 | hw_flags = MI_FORCE_RESTORE; |
1722 | } | |
8911a31c CW |
1723 | } |
1724 | ||
b3ee09a4 | 1725 | if (rq->hw_context->state) { |
8a68d464 | 1726 | GEM_BUG_ON(engine->id != RCS0); |
8911a31c CW |
1727 | |
1728 | /* | |
1729 | * The kernel context(s) is treated as pure scratch and is not | |
1730 | * expected to retain any state (as we sacrifice it during | |
1731 | * suspend and on resume it may be corrupted). This is ok, | |
1732 | * as nothing actually executes using the kernel context; it | |
1733 | * is purely used for flushing user contexts. | |
1734 | */ | |
b3ee09a4 | 1735 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1736 | hw_flags = MI_RESTORE_INHIBIT; |
1737 | ||
1738 | ret = mi_set_context(rq, hw_flags); | |
1739 | if (ret) | |
1740 | goto err_mm; | |
8911a31c | 1741 | } |
8911a31c | 1742 | |
e568ac38 | 1743 | if (vm) { |
06348d30 CW |
1744 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1745 | if (ret) | |
1746 | goto err_mm; | |
1747 | ||
d9d117e4 CW |
1748 | ret = flush_pd_dir(rq); |
1749 | if (ret) | |
1750 | goto err_mm; | |
06348d30 CW |
1751 | |
1752 | /* | |
1753 | * Not only do we need a full barrier (post-sync write) after | |
1754 | * invalidating the TLBs, but we need to wait a little bit | |
1755 | * longer. Whether this is merely delaying us, or the | |
1756 | * subsequent flush is a key part of serialising with the | |
1757 | * post-sync op, this extra pass appears vital before a | |
1758 | * mm switch! | |
1759 | */ | |
1760 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1761 | if (ret) | |
1762 | goto err_mm; | |
1763 | ||
1764 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1765 | if (ret) | |
1766 | goto err_mm; | |
8911a31c CW |
1767 | } |
1768 | ||
b3ee09a4 | 1769 | if (ctx->remap_slice) { |
8911a31c | 1770 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1771 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1772 | continue; |
1773 | ||
1774 | ret = remap_l3(rq, i); | |
1775 | if (ret) | |
b3ee09a4 | 1776 | goto err_mm; |
8911a31c CW |
1777 | } |
1778 | ||
b3ee09a4 | 1779 | ctx->remap_slice = 0; |
8911a31c CW |
1780 | } |
1781 | ||
1782 | return 0; | |
1783 | ||
8911a31c | 1784 | err_mm: |
b3ee09a4 | 1785 | if (unwind_mm) |
e568ac38 | 1786 | i915_vm_to_ppgtt(vm)->pd_dirty_engines |= unwind_mm; |
8911a31c CW |
1787 | err: |
1788 | return ret; | |
1789 | } | |
1790 | ||
e61e0f51 | 1791 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1792 | { |
fd138212 | 1793 | int ret; |
6310346e | 1794 | |
08819549 | 1795 | GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); |
85474441 | 1796 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1797 | |
5f5800a7 CW |
1798 | /* |
1799 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1800 | * we start building the request - in which case we will just |
1801 | * have to repeat work. | |
1802 | */ | |
a0442461 | 1803 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1804 | |
928f8f42 CW |
1805 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1806 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
fd138212 CW |
1807 | if (ret) |
1808 | return ret; | |
6310346e | 1809 | |
928f8f42 | 1810 | ret = switch_context(request); |
3fef5cda CW |
1811 | if (ret) |
1812 | return ret; | |
1813 | ||
a0442461 | 1814 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1815 | return 0; |
9d773091 CW |
1816 | } |
1817 | ||
fd138212 | 1818 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1819 | { |
e61e0f51 | 1820 | struct i915_request *target; |
e95433c7 CW |
1821 | long timeout; |
1822 | ||
95aebcb2 | 1823 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1824 | return 0; |
1825 | ||
36620032 | 1826 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1827 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1828 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1829 | if (bytes <= __intel_ring_space(target->postfix, |
1830 | ring->emit, ring->size)) | |
987046ad | 1831 | break; |
79bbcc29 | 1832 | } |
29b1b415 | 1833 | |
675d9ad7 | 1834 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1835 | return -ENOSPC; |
1836 | ||
e61e0f51 | 1837 | timeout = i915_request_wait(target, |
2f530945 | 1838 | I915_WAIT_INTERRUPTIBLE, |
e95433c7 CW |
1839 | MAX_SCHEDULE_TIMEOUT); |
1840 | if (timeout < 0) | |
1841 | return timeout; | |
7da844c5 | 1842 | |
e61e0f51 | 1843 | i915_request_retire_upto(target); |
7da844c5 CW |
1844 | |
1845 | intel_ring_update_space(ring); | |
1846 | GEM_BUG_ON(ring->space < bytes); | |
1847 | return 0; | |
29b1b415 JH |
1848 | } |
1849 | ||
e61e0f51 | 1850 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1851 | { |
e61e0f51 | 1852 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1853 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1854 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1855 | unsigned int need_wrap = 0; | |
1856 | unsigned int total_bytes; | |
73dec95e | 1857 | u32 *cs; |
29b1b415 | 1858 | |
6492ca79 CW |
1859 | /* Packets must be qword aligned. */ |
1860 | GEM_BUG_ON(num_dwords & 1); | |
1861 | ||
e61e0f51 | 1862 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1863 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1864 | |
5e5655c3 CW |
1865 | if (unlikely(total_bytes > remain_usable)) { |
1866 | const int remain_actual = ring->size - ring->emit; | |
1867 | ||
1868 | if (bytes > remain_usable) { | |
1869 | /* | |
1870 | * Not enough space for the basic request. So need to | |
1871 | * flush out the remainder and then wait for | |
1872 | * base + reserved. | |
1873 | */ | |
1874 | total_bytes += remain_actual; | |
1875 | need_wrap = remain_actual | 1; | |
1876 | } else { | |
1877 | /* | |
1878 | * The base request will fit but the reserved space | |
1879 | * falls off the end. So we don't need an immediate | |
1880 | * wrap and only need to effectively wait for the | |
1881 | * reserved size from the start of ringbuffer. | |
1882 | */ | |
e61e0f51 | 1883 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 1884 | } |
cbcc80df MK |
1885 | } |
1886 | ||
5e5655c3 | 1887 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1888 | int ret; |
1889 | ||
1890 | /* | |
1891 | * Space is reserved in the ringbuffer for finalising the | |
1892 | * request, as that cannot be allowed to fail. During request | |
1893 | * finalisation, reserved_space is set to 0 to stop the | |
1894 | * overallocation and the assumption is that then we never need | |
1895 | * to wait (which has the risk of failing with EINTR). | |
1896 | * | |
e61e0f51 | 1897 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 1898 | */ |
e61e0f51 | 1899 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
1900 | |
1901 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 1902 | if (unlikely(ret)) |
73dec95e | 1903 | return ERR_PTR(ret); |
cbcc80df MK |
1904 | } |
1905 | ||
987046ad | 1906 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1907 | need_wrap &= ~1; |
1908 | GEM_BUG_ON(need_wrap > ring->space); | |
1909 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 1910 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 1911 | |
987046ad | 1912 | /* Fill the tail with MI_NOOP */ |
46b86332 | 1913 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 1914 | ring->space -= need_wrap; |
46b86332 | 1915 | ring->emit = 0; |
987046ad | 1916 | } |
304d695c | 1917 | |
e6ba9992 | 1918 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1919 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1920 | cs = ring->vaddr + ring->emit; |
46b86332 | 1921 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 1922 | ring->emit += bytes; |
1dae2dfb | 1923 | ring->space -= bytes; |
73dec95e TU |
1924 | |
1925 | return cs; | |
8187a2b7 | 1926 | } |
78501eac | 1927 | |
753b1ad4 | 1928 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 1929 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 1930 | { |
1f177a13 CW |
1931 | int num_dwords; |
1932 | void *cs; | |
753b1ad4 | 1933 | |
1f177a13 | 1934 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
1935 | if (num_dwords == 0) |
1936 | return 0; | |
1937 | ||
1f177a13 CW |
1938 | num_dwords = CACHELINE_DWORDS - num_dwords; |
1939 | GEM_BUG_ON(num_dwords & 1); | |
1940 | ||
e61e0f51 | 1941 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
1942 | if (IS_ERR(cs)) |
1943 | return PTR_ERR(cs); | |
753b1ad4 | 1944 | |
1f177a13 | 1945 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 1946 | intel_ring_advance(rq, cs); |
753b1ad4 | 1947 | |
1f177a13 | 1948 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
1949 | return 0; |
1950 | } | |
1951 | ||
e61e0f51 | 1952 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 1953 | { |
baba6e57 | 1954 | struct intel_uncore *uncore = request->engine->uncore; |
881f47b6 | 1955 | |
d2d551c0 | 1956 | intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); |
76f8421f | 1957 | |
881f47b6 | 1958 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1959 | |
1960 | /* Disable notification that the ring is IDLE. The GT | |
1961 | * will then assume that it is busy and bring it out of rc6. | |
1962 | */ | |
d2d551c0 DCS |
1963 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
1964 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1965 | |
1966 | /* Clear the context id. Here be magic! */ | |
d2d551c0 | 1967 | intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); |
0206e353 | 1968 | |
12f55818 | 1969 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
d2d551c0 | 1970 | if (__intel_wait_for_register_fw(uncore, |
02b312d0 CW |
1971 | GEN6_BSD_SLEEP_PSMI_CONTROL, |
1972 | GEN6_BSD_SLEEP_INDICATOR, | |
1973 | 0, | |
1974 | 1000, 0, NULL)) | |
12f55818 | 1975 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1976 | |
12f55818 | 1977 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1978 | i9xx_submit_request(request); |
12f55818 CW |
1979 | |
1980 | /* Let the ring send IDLE messages to the GT again, | |
1981 | * and so let it sleep to conserve power when idle. | |
1982 | */ | |
d2d551c0 DCS |
1983 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
1984 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
76f8421f | 1985 | |
d2d551c0 | 1986 | intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); |
881f47b6 XH |
1987 | } |
1988 | ||
06348d30 | 1989 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 1990 | { |
73dec95e | 1991 | u32 cmd, *cs; |
b72f3acb | 1992 | |
e61e0f51 | 1993 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
1994 | if (IS_ERR(cs)) |
1995 | return PTR_ERR(cs); | |
b72f3acb | 1996 | |
71a77e07 | 1997 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 1998 | |
70b73f9a CW |
1999 | /* |
2000 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2001 | * commands, such as breadcrumb interrupts, are strictly ordered |
2002 | * wrt the contents of the write cache being flushed to memory | |
2003 | * (and thus being coherent from the CPU). | |
2004 | */ | |
2005 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2006 | ||
9a289771 | 2007 | /* |
70b73f9a | 2008 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2009 | * "If ENABLED, all TLBs will be invalidated once the flush |
2010 | * operation is complete. This bit is only valid when the | |
2011 | * Post-Sync Operation field is a value of 1h or 3h." | |
2012 | */ | |
70b73f9a | 2013 | cmd |= flags; |
f0a1fb10 | 2014 | |
73dec95e TU |
2015 | *cs++ = cmd; |
2016 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2017 | *cs++ = 0; |
73dec95e | 2018 | *cs++ = MI_NOOP; |
70b73f9a | 2019 | |
e61e0f51 | 2020 | intel_ring_advance(rq, cs); |
70b73f9a | 2021 | |
1c7a0623 BW |
2022 | return 0; |
2023 | } | |
2024 | ||
70b73f9a CW |
2025 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2026 | { | |
06348d30 | 2027 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2028 | } |
2029 | ||
2030 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2031 | { | |
2032 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2033 | } | |
2034 | ||
d7d4eedd | 2035 | static int |
e61e0f51 | 2036 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2037 | u64 offset, u32 len, |
2038 | unsigned int dispatch_flags) | |
d7d4eedd | 2039 | { |
73dec95e | 2040 | u32 *cs; |
d7d4eedd | 2041 | |
e61e0f51 | 2042 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2043 | if (IS_ERR(cs)) |
2044 | return PTR_ERR(cs); | |
d7d4eedd | 2045 | |
73dec95e | 2046 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2047 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2048 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2049 | *cs++ = offset; |
e61e0f51 | 2050 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2051 | |
2052 | return 0; | |
2053 | } | |
2054 | ||
881f47b6 | 2055 | static int |
e61e0f51 | 2056 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2057 | u64 offset, u32 len, |
2058 | unsigned int dispatch_flags) | |
881f47b6 | 2059 | { |
73dec95e | 2060 | u32 *cs; |
ab6f8e32 | 2061 | |
e61e0f51 | 2062 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2063 | if (IS_ERR(cs)) |
2064 | return PTR_ERR(cs); | |
e1f99ce6 | 2065 | |
73dec95e TU |
2066 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2067 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2068 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2069 | *cs++ = offset; |
e61e0f51 | 2070 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2071 | |
0206e353 | 2072 | return 0; |
881f47b6 XH |
2073 | } |
2074 | ||
549f7365 CW |
2075 | /* Blitter support (SandyBridge+) */ |
2076 | ||
e61e0f51 | 2077 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2078 | { |
70b73f9a | 2079 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2080 | } |
2081 | ||
ff44ad51 CW |
2082 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2083 | { | |
2084 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2085 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2086 | |
2087 | engine->park = NULL; | |
2088 | engine->unpark = NULL; | |
ff44ad51 CW |
2089 | } |
2090 | ||
2091 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2092 | { | |
aba5e278 | 2093 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2094 | engine->submit_request = gen6_bsd_submit_request; |
2095 | } | |
2096 | ||
45b9c968 CW |
2097 | static void ring_destroy(struct intel_engine_cs *engine) |
2098 | { | |
2099 | struct drm_i915_private *dev_priv = engine->i915; | |
2100 | ||
2101 | WARN_ON(INTEL_GEN(dev_priv) > 2 && | |
2102 | (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); | |
2103 | ||
09c5ab38 CW |
2104 | intel_engine_cleanup_common(engine); |
2105 | ||
45b9c968 CW |
2106 | intel_ring_unpin(engine->buffer); |
2107 | intel_ring_put(engine->buffer); | |
2108 | ||
45b9c968 CW |
2109 | kfree(engine); |
2110 | } | |
2111 | ||
11334c6a CW |
2112 | static void setup_irq(struct intel_engine_cs *engine) |
2113 | { | |
2114 | struct drm_i915_private *i915 = engine->i915; | |
2115 | ||
2116 | if (INTEL_GEN(i915) >= 6) { | |
2117 | engine->irq_enable = gen6_irq_enable; | |
2118 | engine->irq_disable = gen6_irq_disable; | |
2119 | } else if (INTEL_GEN(i915) >= 5) { | |
2120 | engine->irq_enable = gen5_irq_enable; | |
2121 | engine->irq_disable = gen5_irq_disable; | |
2122 | } else if (INTEL_GEN(i915) >= 3) { | |
2123 | engine->irq_enable = i9xx_irq_enable; | |
2124 | engine->irq_disable = i9xx_irq_disable; | |
2125 | } else { | |
2126 | engine->irq_enable = i8xx_irq_enable; | |
2127 | engine->irq_disable = i8xx_irq_disable; | |
2128 | } | |
2129 | } | |
2130 | ||
2131 | static void setup_common(struct intel_engine_cs *engine) | |
06a2fe22 | 2132 | { |
11334c6a CW |
2133 | struct drm_i915_private *i915 = engine->i915; |
2134 | ||
79e6770c | 2135 | /* gen8+ are only supported with execlists */ |
11334c6a | 2136 | GEM_BUG_ON(INTEL_GEN(i915) >= 8); |
79e6770c | 2137 | |
11334c6a | 2138 | setup_irq(engine); |
618e4ca7 | 2139 | |
45b9c968 CW |
2140 | engine->destroy = ring_destroy; |
2141 | ||
79ffac85 | 2142 | engine->resume = xcs_resume; |
5adfb772 CW |
2143 | engine->reset.prepare = reset_prepare; |
2144 | engine->reset.reset = reset_ring; | |
2145 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2146 | |
4dc84b77 | 2147 | engine->cops = &ring_context_ops; |
f73e7399 CW |
2148 | engine->request_alloc = ring_request_alloc; |
2149 | ||
85474441 CW |
2150 | /* |
2151 | * Using a global execution timeline; the previous final breadcrumb is | |
2152 | * equivalent to our next initial bread so we can elide | |
2153 | * engine->emit_init_breadcrumb(). | |
2154 | */ | |
2155 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
11334c6a | 2156 | if (IS_GEN(i915, 5)) |
85474441 | 2157 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2158 | |
2159 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2160 | |
11334c6a | 2161 | if (INTEL_GEN(i915) >= 6) |
803688ba | 2162 | engine->emit_bb_start = gen6_emit_bb_start; |
11334c6a | 2163 | else if (INTEL_GEN(i915) >= 4) |
803688ba | 2164 | engine->emit_bb_start = i965_emit_bb_start; |
11334c6a | 2165 | else if (IS_I830(i915) || IS_I845G(i915)) |
803688ba | 2166 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2167 | else |
803688ba | 2168 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2169 | } |
2170 | ||
11334c6a | 2171 | static void setup_rcs(struct intel_engine_cs *engine) |
5c1143bb | 2172 | { |
11334c6a | 2173 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2174 | |
11334c6a | 2175 | if (HAS_L3_DPF(i915)) |
61ff75ac | 2176 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
f8973c21 | 2177 | |
fa6f071d DCS |
2178 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2179 | ||
11334c6a | 2180 | if (INTEL_GEN(i915) >= 7) { |
e2f80391 | 2181 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2182 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2183 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
11334c6a | 2184 | } else if (IS_GEN(i915, 6)) { |
caa5915b CW |
2185 | engine->init_context = intel_rcs_ctx_init; |
2186 | engine->emit_flush = gen6_render_ring_flush; | |
85474441 | 2187 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
11334c6a | 2188 | } else if (IS_GEN(i915, 5)) { |
c7fe7d25 | 2189 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2190 | } else { |
11334c6a | 2191 | if (INTEL_GEN(i915) < 4) |
c7fe7d25 | 2192 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2193 | else |
c7fe7d25 | 2194 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2195 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2196 | } |
707d9cf9 | 2197 | |
11334c6a | 2198 | if (IS_HASWELL(i915)) |
803688ba | 2199 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2200 | |
79ffac85 | 2201 | engine->resume = rcs_resume; |
5c1143bb XH |
2202 | } |
2203 | ||
11334c6a | 2204 | static void setup_vcs(struct intel_engine_cs *engine) |
5c1143bb | 2205 | { |
11334c6a | 2206 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2207 | |
11334c6a | 2208 | if (INTEL_GEN(i915) >= 6) { |
0fd2c201 | 2209 | /* gen6 bsd needs a special wa for tail updates */ |
11334c6a | 2210 | if (IS_GEN(i915, 6)) |
ff44ad51 | 2211 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2212 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2213 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2214 | |
11334c6a | 2215 | if (IS_GEN(i915, 6)) |
85474441 | 2216 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2217 | else |
85474441 | 2218 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2219 | } else { |
c7fe7d25 | 2220 | engine->emit_flush = bsd_ring_flush; |
11334c6a | 2221 | if (IS_GEN(i915, 5)) |
e2f80391 | 2222 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2223 | else |
e2f80391 | 2224 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2225 | } |
5c1143bb | 2226 | } |
549f7365 | 2227 | |
11334c6a | 2228 | static void setup_bcs(struct intel_engine_cs *engine) |
549f7365 | 2229 | { |
11334c6a | 2230 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2231 | |
c7fe7d25 | 2232 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2233 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2234 | |
11334c6a | 2235 | if (IS_GEN(i915, 6)) |
85474441 | 2236 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2237 | else |
85474441 | 2238 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
549f7365 | 2239 | } |
a7b9761d | 2240 | |
11334c6a | 2241 | static void setup_vecs(struct intel_engine_cs *engine) |
9a8a2213 | 2242 | { |
11334c6a | 2243 | struct drm_i915_private *i915 = engine->i915; |
caa5915b | 2244 | |
11334c6a | 2245 | GEM_BUG_ON(INTEL_GEN(i915) < 7); |
06a2fe22 | 2246 | |
c7fe7d25 | 2247 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2248 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2249 | engine->irq_enable = hsw_vebox_irq_enable; | |
2250 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2251 | |
85474441 | 2252 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
11334c6a CW |
2253 | } |
2254 | ||
2255 | int intel_ring_submission_setup(struct intel_engine_cs *engine) | |
2256 | { | |
2257 | setup_common(engine); | |
2258 | ||
2259 | switch (engine->class) { | |
2260 | case RENDER_CLASS: | |
2261 | setup_rcs(engine); | |
2262 | break; | |
2263 | case VIDEO_DECODE_CLASS: | |
2264 | setup_vcs(engine); | |
2265 | break; | |
2266 | case COPY_ENGINE_CLASS: | |
2267 | setup_bcs(engine); | |
2268 | break; | |
2269 | case VIDEO_ENHANCEMENT_CLASS: | |
2270 | setup_vecs(engine); | |
2271 | break; | |
2272 | default: | |
2273 | MISSING_CASE(engine->class); | |
2274 | return -ENODEV; | |
2275 | } | |
2276 | ||
2277 | return 0; | |
2278 | } | |
2279 | ||
2280 | int intel_ring_submission_init(struct intel_engine_cs *engine) | |
2281 | { | |
f0c02c1b | 2282 | struct intel_timeline *timeline; |
11334c6a CW |
2283 | struct intel_ring *ring; |
2284 | int err; | |
2285 | ||
f0c02c1b | 2286 | timeline = intel_timeline_create(engine->gt, engine->status_page.vma); |
11334c6a CW |
2287 | if (IS_ERR(timeline)) { |
2288 | err = PTR_ERR(timeline); | |
2289 | goto err; | |
2290 | } | |
2291 | GEM_BUG_ON(timeline->has_initial_breadcrumb); | |
2292 | ||
2293 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
f0c02c1b | 2294 | intel_timeline_put(timeline); |
11334c6a CW |
2295 | if (IS_ERR(ring)) { |
2296 | err = PTR_ERR(ring); | |
2297 | goto err; | |
2298 | } | |
2299 | ||
2300 | err = intel_ring_pin(ring); | |
2301 | if (err) | |
2302 | goto err_ring; | |
caa5915b | 2303 | |
11334c6a CW |
2304 | GEM_BUG_ON(engine->buffer); |
2305 | engine->buffer = ring; | |
2306 | ||
2307 | err = intel_engine_init_common(engine); | |
2308 | if (err) | |
2309 | goto err_unpin; | |
2310 | ||
2311 | GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma); | |
2312 | ||
2313 | return 0; | |
2314 | ||
2315 | err_unpin: | |
2316 | intel_ring_unpin(ring); | |
2317 | err_ring: | |
2318 | intel_ring_put(ring); | |
2319 | err: | |
2320 | intel_engine_cleanup_common(engine); | |
2321 | return err; | |
9a8a2213 | 2322 | } |