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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa | 33 | |
10be98a7 CW |
34 | #include "gem/i915_gem_context.h" |
35 | ||
7c2fa7fa CW |
36 | #include "i915_drv.h" |
37 | #include "i915_gem_render_state.h" | |
62fdfeaf | 38 | #include "i915_trace.h" |
10be98a7 | 39 | #include "intel_context.h" |
112ed2d3 | 40 | #include "intel_reset.h" |
7d3c425f | 41 | #include "intel_workarounds.h" |
62fdfeaf | 42 | |
a0442461 CW |
43 | /* Rough estimate of the typical request size, performing a flush, |
44 | * set-context and then emitting the batch. | |
45 | */ | |
46 | #define LEGACY_REQUEST_SIZE 200 | |
47 | ||
95aebcb2 | 48 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 49 | { |
95aebcb2 CW |
50 | unsigned int space; |
51 | ||
52 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
53 | ||
54 | ring->space = space; | |
55 | return space; | |
ebd0fd4b DG |
56 | } |
57 | ||
b72f3acb | 58 | static int |
e61e0f51 | 59 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 60 | { |
a889580c | 61 | unsigned int num_store_dw; |
73dec95e | 62 | u32 cmd, *cs; |
46f0f8d1 CW |
63 | |
64 | cmd = MI_FLUSH; | |
a889580c | 65 | num_store_dw = 0; |
7c9cf4e3 | 66 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 67 | cmd |= MI_READ_FLUSH; |
a889580c CW |
68 | if (mode & EMIT_FLUSH) |
69 | num_store_dw = 4; | |
46f0f8d1 | 70 | |
a889580c | 71 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
72 | if (IS_ERR(cs)) |
73 | return PTR_ERR(cs); | |
46f0f8d1 | 74 | |
73dec95e | 75 | *cs++ = cmd; |
a889580c CW |
76 | while (num_store_dw--) { |
77 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
78 | *cs++ = i915_scratch_offset(rq->i915); | |
79 | *cs++ = 0; | |
80 | } | |
81 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
82 | ||
e61e0f51 | 83 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static int | |
e61e0f51 | 89 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 90 | { |
73dec95e | 91 | u32 cmd, *cs; |
55f99bf2 | 92 | int i; |
6f392d54 | 93 | |
36d527de CW |
94 | /* |
95 | * read/write caches: | |
96 | * | |
97 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
98 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
99 | * also flushed at 2d versus 3d pipeline switches. | |
100 | * | |
101 | * read-only caches: | |
102 | * | |
103 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
104 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
105 | * | |
106 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
107 | * | |
108 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
109 | * invalidated when MI_EXE_FLUSH is set. | |
110 | * | |
111 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
112 | * invalidated with every MI_FLUSH. | |
113 | * | |
114 | * TLBs: | |
115 | * | |
116 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
117 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
118 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
119 | * are flushed at any MI_FLUSH. | |
120 | */ | |
121 | ||
b5321f30 | 122 | cmd = MI_FLUSH; |
7c9cf4e3 | 123 | if (mode & EMIT_INVALIDATE) { |
36d527de | 124 | cmd |= MI_EXE_FLUSH; |
cf819eff | 125 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
126 | cmd |= MI_INVALIDATE_ISP; |
127 | } | |
70eac33e | 128 | |
55f99bf2 CW |
129 | i = 2; |
130 | if (mode & EMIT_INVALIDATE) | |
131 | i += 20; | |
132 | ||
133 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
134 | if (IS_ERR(cs)) |
135 | return PTR_ERR(cs); | |
b72f3acb | 136 | |
73dec95e | 137 | *cs++ = cmd; |
55f99bf2 CW |
138 | |
139 | /* | |
140 | * A random delay to let the CS invalidate take effect? Without this | |
141 | * delay, the GPU relocation path fails as the CS does not see | |
142 | * the updated contents. Just as important, if we apply the flushes | |
143 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
144 | * write and before the invalidate on the next batch), the relocations | |
145 | * still fail. This implies that is a delay following invalidation | |
146 | * that is required to reset the caches as opposed to a delay to | |
147 | * ensure the memory is written. | |
148 | */ | |
149 | if (mode & EMIT_INVALIDATE) { | |
150 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 151 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
152 | *cs++ = 0; |
153 | *cs++ = 0; | |
154 | ||
155 | for (i = 0; i < 12; i++) | |
156 | *cs++ = MI_FLUSH; | |
157 | ||
158 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 159 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
160 | *cs++ = 0; |
161 | *cs++ = 0; | |
162 | } | |
163 | ||
164 | *cs++ = cmd; | |
165 | ||
e61e0f51 | 166 | intel_ring_advance(rq, cs); |
b72f3acb CW |
167 | |
168 | return 0; | |
8187a2b7 ZN |
169 | } |
170 | ||
179f4025 | 171 | /* |
8d315287 JB |
172 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
173 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
174 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
175 | * | |
176 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
177 | * produced by non-pipelined state commands), software needs to first | |
178 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
179 | * 0. | |
180 | * | |
181 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
182 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
183 | * | |
184 | * And the workaround for these two requires this workaround first: | |
185 | * | |
186 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
187 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
188 | * flushes. | |
189 | * | |
190 | * And this last workaround is tricky because of the requirements on | |
191 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
192 | * volume 2 part 1: | |
193 | * | |
194 | * "1 of the following must also be set: | |
195 | * - Render Target Cache Flush Enable ([12] of DW1) | |
196 | * - Depth Cache Flush Enable ([0] of DW1) | |
197 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
198 | * - Depth Stall ([13] of DW1) | |
199 | * - Post-Sync Operation ([13] of DW1) | |
200 | * - Notify Enable ([8] of DW1)" | |
201 | * | |
202 | * The cache flushes require the workaround flush that triggered this | |
203 | * one, so we can't use it. Depth stall would trigger the same. | |
204 | * Post-sync nonzero is what triggered this second workaround, so we | |
205 | * can't use that one either. Notify enable is IRQs, which aren't | |
206 | * really our business. That leaves only stall at scoreboard. | |
207 | */ | |
208 | static int | |
caa5915b | 209 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 210 | { |
51797499 | 211 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e TU |
212 | u32 *cs; |
213 | ||
e61e0f51 | 214 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
215 | if (IS_ERR(cs)) |
216 | return PTR_ERR(cs); | |
217 | ||
218 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
219 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
220 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
221 | *cs++ = 0; /* low dword */ | |
222 | *cs++ = 0; /* high dword */ | |
223 | *cs++ = MI_NOOP; | |
e61e0f51 | 224 | intel_ring_advance(rq, cs); |
73dec95e | 225 | |
e61e0f51 | 226 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
227 | if (IS_ERR(cs)) |
228 | return PTR_ERR(cs); | |
229 | ||
230 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
231 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
232 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
233 | *cs++ = 0; | |
234 | *cs++ = 0; | |
235 | *cs++ = MI_NOOP; | |
e61e0f51 | 236 | intel_ring_advance(rq, cs); |
8d315287 JB |
237 | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static int | |
e61e0f51 | 242 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 243 | { |
51797499 | 244 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 245 | u32 *cs, flags = 0; |
8d315287 JB |
246 | int ret; |
247 | ||
b3111509 | 248 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 249 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
250 | if (ret) |
251 | return ret; | |
252 | ||
8d315287 JB |
253 | /* Just flush everything. Experiments have shown that reducing the |
254 | * number of bits based on the write domains has little performance | |
255 | * impact. | |
256 | */ | |
7c9cf4e3 | 257 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
258 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
259 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
260 | /* | |
261 | * Ensure that any following seqno writes only happen | |
262 | * when the render cache is indeed flushed. | |
263 | */ | |
97f209bc | 264 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 265 | } |
7c9cf4e3 | 266 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
267 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
268 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
269 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
270 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
271 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
272 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
273 | /* | |
274 | * TLB invalidate requires a post-sync write. | |
275 | */ | |
3ac78313 | 276 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 277 | } |
8d315287 | 278 | |
e61e0f51 | 279 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
280 | if (IS_ERR(cs)) |
281 | return PTR_ERR(cs); | |
8d315287 | 282 | |
73dec95e TU |
283 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
284 | *cs++ = flags; | |
285 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
286 | *cs++ = 0; | |
e61e0f51 | 287 | intel_ring_advance(rq, cs); |
8d315287 JB |
288 | |
289 | return 0; | |
290 | } | |
291 | ||
e1a73a54 | 292 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
293 | { |
294 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
295 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
296 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
297 | *cs++ = 0; | |
298 | *cs++ = 0; | |
299 | ||
300 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
301 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
302 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; | |
303 | *cs++ = 0; | |
304 | ||
305 | /* Finally we can flush and with it emit the breadcrumb */ | |
306 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
307 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
308 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
309 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
310 | PIPE_CONTROL_QW_WRITE | | |
311 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
312 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
313 | *cs++ = rq->fence.seqno; | |
314 | ||
caa5915b CW |
315 | *cs++ = MI_USER_INTERRUPT; |
316 | *cs++ = MI_NOOP; | |
317 | ||
318 | rq->tail = intel_ring_offset(rq, cs); | |
319 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
320 | |
321 | return cs; | |
caa5915b | 322 | } |
caa5915b | 323 | |
f3987631 | 324 | static int |
e61e0f51 | 325 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 326 | { |
73dec95e | 327 | u32 *cs; |
f3987631 | 328 | |
e61e0f51 | 329 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
330 | if (IS_ERR(cs)) |
331 | return PTR_ERR(cs); | |
f3987631 | 332 | |
73dec95e TU |
333 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
334 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
335 | *cs++ = 0; | |
336 | *cs++ = 0; | |
e61e0f51 | 337 | intel_ring_advance(rq, cs); |
f3987631 PZ |
338 | |
339 | return 0; | |
340 | } | |
341 | ||
4772eaeb | 342 | static int |
e61e0f51 | 343 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 344 | { |
51797499 | 345 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 346 | u32 *cs, flags = 0; |
4772eaeb | 347 | |
f3987631 PZ |
348 | /* |
349 | * Ensure that any following seqno writes only happen when the render | |
350 | * cache is indeed flushed. | |
351 | * | |
352 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
353 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
354 | * don't try to be clever and just set it unconditionally. | |
355 | */ | |
356 | flags |= PIPE_CONTROL_CS_STALL; | |
357 | ||
4772eaeb PZ |
358 | /* Just flush everything. Experiments have shown that reducing the |
359 | * number of bits based on the write domains has little performance | |
360 | * impact. | |
361 | */ | |
7c9cf4e3 | 362 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
363 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
364 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 365 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 366 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 367 | } |
7c9cf4e3 | 368 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
369 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
370 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
372 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
373 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 375 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
376 | /* |
377 | * TLB invalidate requires a post-sync write. | |
378 | */ | |
379 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 380 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 381 | |
add284a3 CW |
382 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
383 | ||
f3987631 PZ |
384 | /* Workaround: we must issue a pipe_control with CS-stall bit |
385 | * set before a pipe_control command that has the state cache | |
386 | * invalidate bit set. */ | |
e61e0f51 | 387 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
388 | } |
389 | ||
e61e0f51 | 390 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
391 | if (IS_ERR(cs)) |
392 | return PTR_ERR(cs); | |
4772eaeb | 393 | |
73dec95e TU |
394 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
395 | *cs++ = flags; | |
396 | *cs++ = scratch_addr; | |
397 | *cs++ = 0; | |
e61e0f51 | 398 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
e1a73a54 | 403 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
404 | { |
405 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
406 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
407 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
408 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
409 | PIPE_CONTROL_FLUSH_ENABLE | | |
410 | PIPE_CONTROL_QW_WRITE | | |
411 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
412 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
413 | *cs++ = rq->timeline->hwsp_offset; |
414 | *cs++ = rq->fence.seqno; | |
415 | ||
caa5915b CW |
416 | *cs++ = MI_USER_INTERRUPT; |
417 | *cs++ = MI_NOOP; | |
418 | ||
419 | rq->tail = intel_ring_offset(rq, cs); | |
420 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
421 | |
422 | return cs; | |
caa5915b | 423 | } |
caa5915b | 424 | |
e1a73a54 | 425 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 426 | { |
5013eb8c CW |
427 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
428 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
429 | ||
430 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
431 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
432 | *cs++ = rq->fence.seqno; | |
433 | ||
caa5915b CW |
434 | *cs++ = MI_USER_INTERRUPT; |
435 | ||
436 | rq->tail = intel_ring_offset(rq, cs); | |
437 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
438 | |
439 | return cs; | |
caa5915b | 440 | } |
caa5915b | 441 | |
1212bd82 | 442 | #define GEN7_XCS_WA 32 |
e1a73a54 | 443 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
444 | { |
445 | int i; | |
446 | ||
5013eb8c CW |
447 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
448 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
449 | ||
450 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
451 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
452 | *cs++ = rq->fence.seqno; | |
453 | ||
1212bd82 CW |
454 | for (i = 0; i < GEN7_XCS_WA; i++) { |
455 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
456 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
457 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
458 | } |
459 | ||
460 | *cs++ = MI_FLUSH_DW; | |
461 | *cs++ = 0; | |
462 | *cs++ = 0; | |
463 | ||
464 | *cs++ = MI_USER_INTERRUPT; | |
519a0194 | 465 | *cs++ = MI_NOOP; |
1212bd82 CW |
466 | |
467 | rq->tail = intel_ring_offset(rq, cs); | |
468 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
469 | |
470 | return cs; | |
1212bd82 | 471 | } |
1212bd82 CW |
472 | #undef GEN7_XCS_WA |
473 | ||
060f2322 CW |
474 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
475 | { | |
476 | /* | |
477 | * Keep the render interrupt unmasked as this papers over | |
478 | * lost interrupts following a reset. | |
479 | */ | |
480 | if (engine->class == RENDER_CLASS) { | |
481 | if (INTEL_GEN(engine->i915) >= 6) | |
482 | mask &= ~BIT(0); | |
483 | else | |
484 | mask &= ~I915_USER_INTERRUPT; | |
485 | } | |
486 | ||
487 | intel_engine_set_hwsp_writemask(engine, mask); | |
488 | } | |
489 | ||
490 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 491 | { |
c033666a | 492 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
493 | u32 addr; |
494 | ||
d6acae36 | 495 | addr = lower_32_bits(phys); |
c033666a | 496 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
497 | addr |= (phys >> 28) & 0xf0; |
498 | ||
035dc1e0 DV |
499 | I915_WRITE(HWS_PGA, addr); |
500 | } | |
501 | ||
0ca88ba0 | 502 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 503 | { |
0ca88ba0 | 504 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 505 | |
0ca88ba0 CW |
506 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
507 | return sg_page(obj->mm.pages->sgl); | |
508 | } | |
509 | ||
510 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
511 | { | |
512 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
513 | set_hwstam(engine, ~0u); |
514 | } | |
515 | ||
516 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 517 | { |
c033666a | 518 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 519 | i915_reg_t hwsp; |
af75f269 | 520 | |
060f2322 CW |
521 | /* |
522 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
523 | * the ring registers as of gen7. |
524 | */ | |
cf819eff | 525 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 526 | switch (engine->id) { |
a2d3d265 MT |
527 | /* |
528 | * No more rings exist on Gen7. Default case is only to shut up | |
529 | * gcc switch check warning. | |
530 | */ | |
531 | default: | |
532 | GEM_BUG_ON(engine->id); | |
8a68d464 CW |
533 | /* fallthrough */ |
534 | case RCS0: | |
060f2322 | 535 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 | 536 | break; |
8a68d464 | 537 | case BCS0: |
060f2322 | 538 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 539 | break; |
8a68d464 | 540 | case VCS0: |
060f2322 | 541 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 | 542 | break; |
8a68d464 | 543 | case VECS0: |
060f2322 | 544 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
545 | break; |
546 | } | |
cf819eff | 547 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 548 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 549 | } else { |
060f2322 | 550 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 551 | } |
c5498089 | 552 | |
060f2322 CW |
553 | I915_WRITE(hwsp, offset); |
554 | POSTING_READ(hwsp); | |
555 | } | |
af75f269 | 556 | |
060f2322 CW |
557 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
558 | { | |
559 | struct drm_i915_private *dev_priv = engine->i915; | |
060f2322 CW |
560 | |
561 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
562 | return; | |
563 | ||
564 | /* ring should be idle before issuing a sync flush*/ | |
baba6e57 DCS |
565 | WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); |
566 | ||
567 | ENGINE_WRITE(engine, RING_INSTPM, | |
568 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
569 | INSTPM_SYNC_FLUSH)); | |
570 | if (intel_wait_for_register(engine->uncore, | |
571 | RING_INSTPM(engine->mmio_base), | |
572 | INSTPM_SYNC_FLUSH, 0, | |
060f2322 CW |
573 | 1000)) |
574 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
575 | engine->name); | |
576 | } | |
af75f269 | 577 | |
060f2322 CW |
578 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
579 | { | |
0ca88ba0 | 580 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 581 | set_hwstam(engine, ~0u); |
af75f269 | 582 | |
060f2322 | 583 | flush_cs_tlb(engine); |
af75f269 DL |
584 | } |
585 | ||
0bc40be8 | 586 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 587 | { |
c033666a | 588 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 589 | |
21a2c58a | 590 | if (INTEL_GEN(dev_priv) > 2) { |
baba6e57 DCS |
591 | ENGINE_WRITE(engine, |
592 | RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); | |
593 | if (intel_wait_for_register(engine->uncore, | |
3d808eb1 CW |
594 | RING_MI_MODE(engine->mmio_base), |
595 | MODE_IDLE, | |
596 | MODE_IDLE, | |
597 | 1000)) { | |
0bc40be8 TU |
598 | DRM_ERROR("%s : timed out trying to stop ring\n", |
599 | engine->name); | |
baba6e57 DCS |
600 | |
601 | /* | |
602 | * Sometimes we observe that the idle flag is not | |
9bec9b13 CW |
603 | * set even though the ring is empty. So double |
604 | * check before giving up. | |
605 | */ | |
baba6e57 DCS |
606 | if (ENGINE_READ(engine, RING_HEAD) != |
607 | ENGINE_READ(engine, RING_TAIL)) | |
9bec9b13 | 608 | return false; |
9991ae78 CW |
609 | } |
610 | } | |
b7884eb4 | 611 | |
baba6e57 | 612 | ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); |
11caf551 | 613 | |
baba6e57 DCS |
614 | ENGINE_WRITE(engine, RING_HEAD, 0); |
615 | ENGINE_WRITE(engine, RING_TAIL, 0); | |
8187a2b7 | 616 | |
11caf551 | 617 | /* The ring must be empty before it is disabled */ |
baba6e57 | 618 | ENGINE_WRITE(engine, RING_CTL, 0); |
11caf551 | 619 | |
baba6e57 | 620 | return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; |
9991ae78 | 621 | } |
8187a2b7 | 622 | |
79ffac85 | 623 | static int xcs_resume(struct intel_engine_cs *engine) |
9991ae78 | 624 | { |
c033666a | 625 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 626 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
627 | int ret = 0; |
628 | ||
79ffac85 CW |
629 | GEM_TRACE("%s: ring:{HEAD:%04x, TAIL:%04x}\n", |
630 | engine->name, ring->head, ring->tail); | |
631 | ||
baba6e57 | 632 | intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); |
9991ae78 | 633 | |
0bc40be8 | 634 | if (!stop_ring(engine)) { |
9991ae78 | 635 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
636 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
637 | "ctl %08x head %08x tail %08x start %08x\n", | |
638 | engine->name, | |
baba6e57 DCS |
639 | ENGINE_READ(engine, RING_CTL), |
640 | ENGINE_READ(engine, RING_HEAD), | |
641 | ENGINE_READ(engine, RING_TAIL), | |
642 | ENGINE_READ(engine, RING_START)); | |
8187a2b7 | 643 | |
0bc40be8 | 644 | if (!stop_ring(engine)) { |
6fd0d56e CW |
645 | DRM_ERROR("failed to set %s head to zero " |
646 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 | 647 | engine->name, |
baba6e57 DCS |
648 | ENGINE_READ(engine, RING_CTL), |
649 | ENGINE_READ(engine, RING_HEAD), | |
650 | ENGINE_READ(engine, RING_TAIL), | |
651 | ENGINE_READ(engine, RING_START)); | |
9991ae78 CW |
652 | ret = -EIO; |
653 | goto out; | |
6fd0d56e | 654 | } |
8187a2b7 ZN |
655 | } |
656 | ||
3177659a | 657 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 658 | ring_setup_phys_status_page(engine); |
3177659a | 659 | else |
060f2322 | 660 | ring_setup_status_page(engine); |
9991ae78 | 661 | |
ad07dfcd | 662 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 663 | |
ece4a17d | 664 | /* Enforce ordering by reading HEAD register back */ |
baba6e57 | 665 | ENGINE_READ(engine, RING_HEAD); |
ece4a17d | 666 | |
0d8957c8 DV |
667 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
668 | * registers with the above sequence (the readback of the HEAD registers | |
669 | * also enforces ordering), otherwise the hw might lose the new ring | |
670 | * register values. */ | |
baba6e57 | 671 | ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); |
95468892 CW |
672 | |
673 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
baba6e57 | 674 | if (ENGINE_READ(engine, RING_HEAD)) |
8177e112 | 675 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
baba6e57 | 676 | engine->name, ENGINE_READ(engine, RING_HEAD)); |
821ed7df | 677 | |
41d37680 CW |
678 | /* Check that the ring offsets point within the ring! */ |
679 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
680 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 681 | intel_ring_update_space(ring); |
b7f21899 CW |
682 | |
683 | /* First wake the ring up to an empty/idle ring */ | |
baba6e57 DCS |
684 | ENGINE_WRITE(engine, RING_HEAD, ring->head); |
685 | ENGINE_WRITE(engine, RING_TAIL, ring->head); | |
686 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
95468892 | 687 | |
baba6e57 | 688 | ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 689 | |
8187a2b7 | 690 | /* If the head is still not zero, the ring is dead */ |
baba6e57 | 691 | if (intel_wait_for_register(engine->uncore, |
97a04e0d | 692 | RING_CTL(engine->mmio_base), |
f42bb651 CW |
693 | RING_VALID, RING_VALID, |
694 | 50)) { | |
e74cfed5 | 695 | DRM_ERROR("%s initialization failed " |
821ed7df | 696 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 | 697 | engine->name, |
baba6e57 DCS |
698 | ENGINE_READ(engine, RING_CTL), |
699 | ENGINE_READ(engine, RING_CTL) & RING_VALID, | |
700 | ENGINE_READ(engine, RING_HEAD), ring->head, | |
701 | ENGINE_READ(engine, RING_TAIL), ring->tail, | |
702 | ENGINE_READ(engine, RING_START), | |
bde13ebd | 703 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
704 | ret = -EIO; |
705 | goto out; | |
8187a2b7 ZN |
706 | } |
707 | ||
7836cd02 | 708 | if (INTEL_GEN(dev_priv) > 2) |
baba6e57 DCS |
709 | ENGINE_WRITE(engine, |
710 | RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); | |
7836cd02 | 711 | |
b7f21899 CW |
712 | /* Now awake, let it get started */ |
713 | if (ring->tail != ring->head) { | |
baba6e57 DCS |
714 | ENGINE_WRITE(engine, RING_TAIL, ring->tail); |
715 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
b7f21899 CW |
716 | } |
717 | ||
d6fee0de | 718 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 719 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 720 | out: |
baba6e57 | 721 | intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); |
b7884eb4 DV |
722 | |
723 | return ret; | |
8187a2b7 ZN |
724 | } |
725 | ||
eb8d0f5a | 726 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 727 | { |
3f6e9822 | 728 | intel_engine_stop_cs(engine); |
5adfb772 CW |
729 | } |
730 | ||
eb8d0f5a | 731 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 732 | { |
eb8d0f5a CW |
733 | struct i915_timeline *tl = &engine->timeline; |
734 | struct i915_request *pos, *rq; | |
735 | unsigned long flags; | |
b3ee09a4 | 736 | u32 head; |
5adfb772 | 737 | |
eb8d0f5a CW |
738 | rq = NULL; |
739 | spin_lock_irqsave(&tl->lock, flags); | |
740 | list_for_each_entry(pos, &tl->requests, link) { | |
5013eb8c | 741 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
742 | rq = pos; |
743 | break; | |
744 | } | |
b3ee09a4 | 745 | } |
67e64564 CW |
746 | |
747 | /* | |
eb8d0f5a | 748 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 749 | * |
eb8d0f5a CW |
750 | * Users of client default contexts do not rely on logical |
751 | * state preserved between batches so it is safe to execute | |
752 | * queued requests following the hang. Non default contexts | |
753 | * rely on preserved state, so skipping a batch loses the | |
754 | * evolution of the state and it needs to be considered corrupted. | |
755 | * Executing more queued batches on top of corrupted state is | |
756 | * risky. But we take the risk by trying to advance through | |
757 | * the queued requests in order to make the client behaviour | |
758 | * more predictable around resets, by not throwing away random | |
759 | * amount of batches it has prepared for execution. Sophisticated | |
760 | * clients can use gem_reset_stats_ioctl and dma fence status | |
761 | * (exported via sync_file info ioctl on explicit fences) to observe | |
762 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 763 | * |
eb8d0f5a CW |
764 | * The context ban, and ultimately the client ban, mechanism are safety |
765 | * valves if client submission ends up resulting in nothing more than | |
766 | * subsequent hangs. | |
c0dcb203 | 767 | */ |
eb8d0f5a | 768 | |
b3ee09a4 | 769 | if (rq) { |
eb8d0f5a CW |
770 | /* |
771 | * Try to restore the logical GPU state to match the | |
772 | * continuation of the request queue. If we skip the | |
773 | * context/PD restore, then the next request may try to execute | |
774 | * assuming that its context is valid and loaded on the GPU and | |
775 | * so may try to access invalid memory, prompting repeated GPU | |
776 | * hangs. | |
777 | * | |
778 | * If the request was guilty, we still restore the logical | |
779 | * state in case the next request requires it (e.g. the | |
780 | * aliasing ppgtt), but skip over the hung batch. | |
781 | * | |
782 | * If the request was innocent, we try to replay the request | |
783 | * with the restored context. | |
784 | */ | |
785 | i915_reset_request(rq, stalled); | |
786 | ||
787 | GEM_BUG_ON(rq->ring != engine->buffer); | |
788 | head = rq->head; | |
789 | } else { | |
790 | head = engine->buffer->tail; | |
c0dcb203 | 791 | } |
eb8d0f5a CW |
792 | engine->buffer->head = intel_ring_wrap(engine->buffer, head); |
793 | ||
794 | spin_unlock_irqrestore(&tl->lock, flags); | |
821ed7df CW |
795 | } |
796 | ||
5adfb772 CW |
797 | static void reset_finish(struct intel_engine_cs *engine) |
798 | { | |
799 | } | |
800 | ||
e61e0f51 | 801 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
802 | { |
803 | int ret; | |
804 | ||
452420d2 | 805 | ret = intel_engine_emit_ctx_wa(rq); |
8f0e2b9d DV |
806 | if (ret != 0) |
807 | return ret; | |
808 | ||
e61e0f51 | 809 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 810 | if (ret) |
e26e1b97 | 811 | return ret; |
8f0e2b9d | 812 | |
e26e1b97 | 813 | return 0; |
8f0e2b9d DV |
814 | } |
815 | ||
79ffac85 | 816 | static int rcs_resume(struct intel_engine_cs *engine) |
8187a2b7 | 817 | { |
c033666a | 818 | struct drm_i915_private *dev_priv = engine->i915; |
a69ffdbf | 819 | |
9ce9bdb0 CW |
820 | /* |
821 | * Disable CONSTANT_BUFFER before it is loaded from the context | |
822 | * image. For as it is loaded, it is executed and the stored | |
823 | * address may no longer be valid, leading to a GPU hang. | |
824 | * | |
825 | * This imposes the requirement that userspace reload their | |
826 | * CONSTANT_BUFFER on every batch, fortunately a requirement | |
827 | * they are already accustomed to from before contexts were | |
828 | * enabled. | |
829 | */ | |
830 | if (IS_GEN(dev_priv, 4)) | |
831 | I915_WRITE(ECOSKPD, | |
832 | _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); | |
833 | ||
61a563a2 | 834 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 835 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 836 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
837 | |
838 | /* We need to disable the AsyncFlip performance optimisations in order | |
839 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
840 | * programmed to '1' on all products. | |
8693a824 | 841 | * |
2441f877 | 842 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 843 | */ |
00690008 | 844 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
845 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
846 | ||
f05bb0c7 | 847 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 848 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 849 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 850 | I915_WRITE(GFX_MODE, |
aa83e30d | 851 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 852 | |
01fa0302 | 853 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 854 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 855 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 856 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 857 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 858 | |
cf819eff | 859 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
860 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
861 | * "If this bit is set, STCunit will have LRA as replacement | |
862 | * policy. [...] This bit must be reset. LRA replacement | |
863 | * policy is not supported." | |
864 | */ | |
865 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 866 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
867 | } |
868 | ||
00690008 | 869 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 870 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 871 | |
79ffac85 | 872 | return xcs_resume(engine); |
8187a2b7 ZN |
873 | } |
874 | ||
27a5f61b CW |
875 | static void cancel_requests(struct intel_engine_cs *engine) |
876 | { | |
e61e0f51 | 877 | struct i915_request *request; |
27a5f61b CW |
878 | unsigned long flags; |
879 | ||
a89d1f92 | 880 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
881 | |
882 | /* Mark all submitted requests as skipped. */ | |
a89d1f92 | 883 | list_for_each_entry(request, &engine->timeline.requests, link) { |
5013eb8c CW |
884 | if (!i915_request_signaled(request)) |
885 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 886 | |
5013eb8c | 887 | i915_request_mark_complete(request); |
27a5f61b | 888 | } |
3800960a | 889 | |
27a5f61b CW |
890 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
891 | ||
a89d1f92 | 892 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
893 | } |
894 | ||
e61e0f51 | 895 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d | 896 | { |
e61e0f51 | 897 | i915_request_submit(request); |
d55ac5bf | 898 | |
baba6e57 DCS |
899 | ENGINE_WRITE(request->engine, RING_TAIL, |
900 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
901 | } |
902 | ||
e1a73a54 | 903 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 904 | { |
5013eb8c CW |
905 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
906 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
907 | ||
caa5915b CW |
908 | *cs++ = MI_FLUSH; |
909 | ||
5013eb8c CW |
910 | *cs++ = MI_STORE_DWORD_INDEX; |
911 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
912 | *cs++ = rq->fence.seqno; | |
913 | ||
73dec95e | 914 | *cs++ = MI_USER_INTERRUPT; |
519a0194 | 915 | *cs++ = MI_NOOP; |
1ec14ad3 | 916 | |
e61e0f51 CW |
917 | rq->tail = intel_ring_offset(rq, cs); |
918 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
919 | |
920 | return cs; | |
1ec14ad3 | 921 | } |
98f29e8d | 922 | |
835051d3 | 923 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 924 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 925 | { |
835051d3 CW |
926 | int i; |
927 | ||
5013eb8c CW |
928 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
929 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
930 | ||
835051d3 CW |
931 | *cs++ = MI_FLUSH; |
932 | ||
933 | BUILD_BUG_ON(GEN5_WA_STORES < 1); | |
934 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
935 | *cs++ = MI_STORE_DWORD_INDEX; | |
b300fde8 CW |
936 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
937 | *cs++ = rq->fence.seqno; | |
835051d3 CW |
938 | } |
939 | ||
940 | *cs++ = MI_USER_INTERRUPT; | |
941 | ||
942 | rq->tail = intel_ring_offset(rq, cs); | |
943 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
944 | |
945 | return cs; | |
c6df541c | 946 | } |
835051d3 | 947 | #undef GEN5_WA_STORES |
c6df541c | 948 | |
31bb59cc CW |
949 | static void |
950 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 951 | { |
31bb59cc | 952 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
953 | } |
954 | ||
955 | static void | |
31bb59cc | 956 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 957 | { |
31bb59cc | 958 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
959 | } |
960 | ||
31bb59cc CW |
961 | static void |
962 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 963 | { |
baba6e57 | 964 | engine->i915->irq_mask &= ~engine->irq_enable_mask; |
9d9523d8 PZ |
965 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
966 | intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); | |
62fdfeaf EA |
967 | } |
968 | ||
8187a2b7 | 969 | static void |
31bb59cc | 970 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 971 | { |
baba6e57 | 972 | engine->i915->irq_mask |= engine->irq_enable_mask; |
9d9523d8 | 973 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
62fdfeaf EA |
974 | } |
975 | ||
31bb59cc CW |
976 | static void |
977 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 978 | { |
c033666a | 979 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 980 | |
31bb59cc | 981 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
9d9523d8 | 982 | I915_WRITE16(GEN2_IMR, dev_priv->irq_mask); |
31bb59cc | 983 | POSTING_READ16(RING_IMR(engine->mmio_base)); |
c2798b19 CW |
984 | } |
985 | ||
986 | static void | |
31bb59cc | 987 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 988 | { |
c033666a | 989 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 990 | |
31bb59cc | 991 | dev_priv->irq_mask |= engine->irq_enable_mask; |
9d9523d8 | 992 | I915_WRITE16(GEN2_IMR, dev_priv->irq_mask); |
c2798b19 CW |
993 | } |
994 | ||
b72f3acb | 995 | static int |
e61e0f51 | 996 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 997 | { |
73dec95e | 998 | u32 *cs; |
b72f3acb | 999 | |
e61e0f51 | 1000 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1001 | if (IS_ERR(cs)) |
1002 | return PTR_ERR(cs); | |
b72f3acb | 1003 | |
73dec95e TU |
1004 | *cs++ = MI_FLUSH; |
1005 | *cs++ = MI_NOOP; | |
e61e0f51 | 1006 | intel_ring_advance(rq, cs); |
b72f3acb | 1007 | return 0; |
d1b851fc ZN |
1008 | } |
1009 | ||
31bb59cc CW |
1010 | static void |
1011 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1012 | { |
baba6e57 DCS |
1013 | ENGINE_WRITE(engine, RING_IMR, |
1014 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
476af9c2 CW |
1015 | |
1016 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1017 | ENGINE_POSTING_READ(engine, RING_IMR); |
476af9c2 | 1018 | |
baba6e57 | 1019 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
0f46832f CW |
1020 | } |
1021 | ||
1022 | static void | |
31bb59cc | 1023 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1024 | { |
baba6e57 DCS |
1025 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); |
1026 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); | |
d1b851fc ZN |
1027 | } |
1028 | ||
31bb59cc CW |
1029 | static void |
1030 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1031 | { |
baba6e57 | 1032 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1033 | |
1034 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1035 | ENGINE_POSTING_READ(engine, RING_IMR); |
e4fc69f2 | 1036 | |
baba6e57 | 1037 | gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask); |
a19d2933 BW |
1038 | } |
1039 | ||
1040 | static void | |
31bb59cc | 1041 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1042 | { |
baba6e57 DCS |
1043 | ENGINE_WRITE(engine, RING_IMR, ~0); |
1044 | gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask); | |
a19d2933 BW |
1045 | } |
1046 | ||
d1b851fc | 1047 | static int |
e61e0f51 | 1048 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1049 | u64 offset, u32 length, |
1050 | unsigned int dispatch_flags) | |
d1b851fc | 1051 | { |
73dec95e | 1052 | u32 *cs; |
78501eac | 1053 | |
e61e0f51 | 1054 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1055 | if (IS_ERR(cs)) |
1056 | return PTR_ERR(cs); | |
e1f99ce6 | 1057 | |
73dec95e TU |
1058 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1059 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1060 | *cs++ = offset; | |
e61e0f51 | 1061 | intel_ring_advance(rq, cs); |
78501eac | 1062 | |
d1b851fc ZN |
1063 | return 0; |
1064 | } | |
1065 | ||
b45305fc | 1066 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1067 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1068 | #define I830_TLB_ENTRIES (2) |
1069 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1070 | static int |
e61e0f51 | 1071 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1072 | u64 offset, u32 len, |
1073 | unsigned int dispatch_flags) | |
62fdfeaf | 1074 | { |
51797499 CW |
1075 | u32 *cs, cs_offset = i915_scratch_offset(rq->i915); |
1076 | ||
1077 | GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE); | |
62fdfeaf | 1078 | |
e61e0f51 | 1079 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1080 | if (IS_ERR(cs)) |
1081 | return PTR_ERR(cs); | |
62fdfeaf | 1082 | |
c4d69da1 | 1083 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1084 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1085 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1086 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1087 | *cs++ = cs_offset; | |
1088 | *cs++ = 0xdeadbeef; | |
1089 | *cs++ = MI_NOOP; | |
e61e0f51 | 1090 | intel_ring_advance(rq, cs); |
b45305fc | 1091 | |
8e004efc | 1092 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1093 | if (len > I830_BATCH_LIMIT) |
1094 | return -ENOSPC; | |
1095 | ||
e61e0f51 | 1096 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1097 | if (IS_ERR(cs)) |
1098 | return PTR_ERR(cs); | |
c4d69da1 CW |
1099 | |
1100 | /* Blit the batch (which has now all relocs applied) to the | |
1101 | * stable batch scratch bo area (so that the CS never | |
1102 | * stumbles over its tlb invalidation bug) ... | |
1103 | */ | |
73dec95e TU |
1104 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1105 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1106 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1107 | *cs++ = cs_offset; | |
1108 | *cs++ = 4096; | |
1109 | *cs++ = offset; | |
1110 | ||
1111 | *cs++ = MI_FLUSH; | |
1112 | *cs++ = MI_NOOP; | |
e61e0f51 | 1113 | intel_ring_advance(rq, cs); |
b45305fc DV |
1114 | |
1115 | /* ... and execute it. */ | |
c4d69da1 | 1116 | offset = cs_offset; |
b45305fc | 1117 | } |
e1f99ce6 | 1118 | |
e61e0f51 | 1119 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1120 | if (IS_ERR(cs)) |
1121 | return PTR_ERR(cs); | |
c4d69da1 | 1122 | |
73dec95e TU |
1123 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1124 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1125 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1126 | intel_ring_advance(rq, cs); |
c4d69da1 | 1127 | |
fb3256da DV |
1128 | return 0; |
1129 | } | |
1130 | ||
1131 | static int | |
e61e0f51 | 1132 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1133 | u64 offset, u32 len, |
1134 | unsigned int dispatch_flags) | |
fb3256da | 1135 | { |
73dec95e | 1136 | u32 *cs; |
fb3256da | 1137 | |
e61e0f51 | 1138 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1139 | if (IS_ERR(cs)) |
1140 | return PTR_ERR(cs); | |
fb3256da | 1141 | |
73dec95e TU |
1142 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1143 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1144 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1145 | intel_ring_advance(rq, cs); |
62fdfeaf | 1146 | |
62fdfeaf EA |
1147 | return 0; |
1148 | } | |
1149 | ||
5503cb0d | 1150 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1151 | { |
57e88531 | 1152 | struct i915_vma *vma = ring->vma; |
89d5efcc | 1153 | enum i915_map_type map = i915_coherent_map_type(vma->vm->i915); |
d822bb18 | 1154 | unsigned int flags; |
8305216f | 1155 | void *addr; |
7ba717cf TD |
1156 | int ret; |
1157 | ||
57e88531 | 1158 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1159 | |
5013eb8c CW |
1160 | ret = i915_timeline_pin(ring->timeline); |
1161 | if (ret) | |
1162 | return ret; | |
1163 | ||
d3ef1af6 | 1164 | flags = PIN_GLOBAL; |
496bcce3 JB |
1165 | |
1166 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1167 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1168 | ||
9d80841e | 1169 | if (vma->obj->stolen) |
57e88531 | 1170 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1171 | else |
1172 | flags |= PIN_HIGH; | |
def0c5f6 | 1173 | |
7a859c65 | 1174 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1175 | if (unlikely(ret)) |
5013eb8c | 1176 | goto unpin_timeline; |
def0c5f6 | 1177 | |
9d80841e | 1178 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1179 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1180 | else | |
9d80841e | 1181 | addr = i915_gem_object_pin_map(vma->obj, map); |
5013eb8c CW |
1182 | if (IS_ERR(addr)) { |
1183 | ret = PTR_ERR(addr); | |
1184 | goto unpin_ring; | |
1185 | } | |
7ba717cf | 1186 | |
3d574a6b CW |
1187 | vma->obj->pin_global++; |
1188 | ||
32c04f16 | 1189 | ring->vaddr = addr; |
7ba717cf | 1190 | return 0; |
d2cad535 | 1191 | |
5013eb8c | 1192 | unpin_ring: |
57e88531 | 1193 | i915_vma_unpin(vma); |
5013eb8c CW |
1194 | unpin_timeline: |
1195 | i915_timeline_unpin(ring->timeline); | |
1196 | return ret; | |
7ba717cf TD |
1197 | } |
1198 | ||
e6ba9992 CW |
1199 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1200 | { | |
41d37680 CW |
1201 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1202 | ||
e6ba9992 CW |
1203 | ring->tail = tail; |
1204 | ring->head = tail; | |
1205 | ring->emit = tail; | |
1206 | intel_ring_update_space(ring); | |
1207 | } | |
1208 | ||
aad29fbb CW |
1209 | void intel_ring_unpin(struct intel_ring *ring) |
1210 | { | |
1211 | GEM_BUG_ON(!ring->vma); | |
1212 | GEM_BUG_ON(!ring->vaddr); | |
1213 | ||
e6ba9992 CW |
1214 | /* Discard any unused bytes beyond that submitted to hw. */ |
1215 | intel_ring_reset(ring, ring->tail); | |
1216 | ||
9d80841e | 1217 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1218 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1219 | else |
1220 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1221 | ring->vaddr = NULL; |
1222 | ||
3d574a6b | 1223 | ring->vma->obj->pin_global--; |
57e88531 | 1224 | i915_vma_unpin(ring->vma); |
5013eb8c CW |
1225 | |
1226 | i915_timeline_unpin(ring->timeline); | |
2919d291 OM |
1227 | } |
1228 | ||
57e88531 CW |
1229 | static struct i915_vma * |
1230 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1231 | { |
250f8c81 | 1232 | struct i915_address_space *vm = &dev_priv->ggtt.vm; |
05394f39 | 1233 | struct drm_i915_gem_object *obj; |
57e88531 | 1234 | struct i915_vma *vma; |
62fdfeaf | 1235 | |
187685cb | 1236 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1237 | if (!obj) |
2d6c4c84 | 1238 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1239 | if (IS_ERR(obj)) |
1240 | return ERR_CAST(obj); | |
8187a2b7 | 1241 | |
250f8c81 JB |
1242 | /* |
1243 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1244 | * if supported by the platform's GGTT. | |
1245 | */ | |
1246 | if (vm->has_read_only) | |
3e977ac6 | 1247 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1248 | |
250f8c81 | 1249 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1250 | if (IS_ERR(vma)) |
1251 | goto err; | |
1252 | ||
1253 | return vma; | |
e3efda49 | 1254 | |
57e88531 CW |
1255 | err: |
1256 | i915_gem_object_put(obj); | |
1257 | return vma; | |
e3efda49 CW |
1258 | } |
1259 | ||
7e37f889 | 1260 | struct intel_ring * |
65fcb806 | 1261 | intel_engine_create_ring(struct intel_engine_cs *engine, |
a89d1f92 | 1262 | struct i915_timeline *timeline, |
65fcb806 | 1263 | int size) |
01101fa7 | 1264 | { |
7e37f889 | 1265 | struct intel_ring *ring; |
57e88531 | 1266 | struct i915_vma *vma; |
01101fa7 | 1267 | |
8f942018 | 1268 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1269 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
a89d1f92 | 1270 | GEM_BUG_ON(timeline == &engine->timeline); |
b887d615 | 1271 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
8f942018 | 1272 | |
01101fa7 | 1273 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1274 | if (!ring) |
01101fa7 CW |
1275 | return ERR_PTR(-ENOMEM); |
1276 | ||
65baf0ef | 1277 | kref_init(&ring->ref); |
675d9ad7 | 1278 | INIT_LIST_HEAD(&ring->request_list); |
a89d1f92 | 1279 | ring->timeline = i915_timeline_get(timeline); |
675d9ad7 | 1280 | |
01101fa7 CW |
1281 | ring->size = size; |
1282 | /* Workaround an erratum on the i830 which causes a hang if | |
1283 | * the TAIL pointer points to within the last 2 cachelines | |
1284 | * of the buffer. | |
1285 | */ | |
1286 | ring->effective_size = size; | |
2a307c2e | 1287 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1288 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1289 | ||
01101fa7 CW |
1290 | intel_ring_update_space(ring); |
1291 | ||
57e88531 CW |
1292 | vma = intel_ring_create_vma(engine->i915, size); |
1293 | if (IS_ERR(vma)) { | |
01101fa7 | 1294 | kfree(ring); |
57e88531 | 1295 | return ERR_CAST(vma); |
01101fa7 | 1296 | } |
57e88531 | 1297 | ring->vma = vma; |
01101fa7 CW |
1298 | |
1299 | return ring; | |
1300 | } | |
1301 | ||
65baf0ef | 1302 | void intel_ring_free(struct kref *ref) |
01101fa7 | 1303 | { |
65baf0ef | 1304 | struct intel_ring *ring = container_of(ref, typeof(*ring), ref); |
f8a7fde4 CW |
1305 | |
1306 | i915_vma_close(ring->vma); | |
c017cf6b | 1307 | i915_vma_put(ring->vma); |
f8a7fde4 | 1308 | |
a89d1f92 | 1309 | i915_timeline_put(ring->timeline); |
01101fa7 CW |
1310 | kfree(ring); |
1311 | } | |
1312 | ||
c4d52feb CW |
1313 | static void __ring_context_fini(struct intel_context *ce) |
1314 | { | |
1315 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1316 | i915_gem_object_put(ce->state->obj); | |
1317 | } | |
1318 | ||
4c5896dc | 1319 | static void ring_context_destroy(struct kref *ref) |
1fc44d9b | 1320 | { |
4c5896dc CW |
1321 | struct intel_context *ce = container_of(ref, typeof(*ce), ref); |
1322 | ||
08819549 | 1323 | GEM_BUG_ON(intel_context_is_pinned(ce)); |
1fc44d9b | 1324 | |
c4d52feb CW |
1325 | if (ce->state) |
1326 | __ring_context_fini(ce); | |
efe79d48 | 1327 | |
c4d52feb | 1328 | intel_context_free(ce); |
1fc44d9b CW |
1329 | } |
1330 | ||
a2bbf714 CW |
1331 | static int __context_pin_ppgtt(struct i915_gem_context *ctx) |
1332 | { | |
e568ac38 | 1333 | struct i915_address_space *vm; |
a2bbf714 CW |
1334 | int err = 0; |
1335 | ||
e568ac38 CW |
1336 | vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm; |
1337 | if (vm) | |
1338 | err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); | |
a2bbf714 CW |
1339 | |
1340 | return err; | |
1341 | } | |
1342 | ||
1343 | static void __context_unpin_ppgtt(struct i915_gem_context *ctx) | |
1344 | { | |
e568ac38 | 1345 | struct i915_address_space *vm; |
a2bbf714 | 1346 | |
e568ac38 CW |
1347 | vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm; |
1348 | if (vm) | |
1349 | gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); | |
a2bbf714 CW |
1350 | } |
1351 | ||
1fc44d9b | 1352 | static int __context_pin(struct intel_context *ce) |
e8a9c58f | 1353 | { |
d901e8e6 CW |
1354 | struct i915_vma *vma; |
1355 | int err; | |
1356 | ||
1357 | vma = ce->state; | |
1358 | if (!vma) | |
1359 | return 0; | |
e8a9c58f | 1360 | |
7a859c65 | 1361 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
d901e8e6 CW |
1362 | if (err) |
1363 | return err; | |
1364 | ||
1365 | /* | |
1366 | * And mark is as a globally pinned object to let the shrinker know | |
1367 | * it cannot reclaim the object until we release it. | |
1368 | */ | |
1369 | vma->obj->pin_global++; | |
a679f58d | 1370 | vma->obj->mm.dirty = true; |
d901e8e6 CW |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | static void __context_unpin(struct intel_context *ce) | |
1376 | { | |
1377 | struct i915_vma *vma; | |
1378 | ||
1379 | vma = ce->state; | |
1380 | if (!vma) | |
1381 | return; | |
1382 | ||
1383 | vma->obj->pin_global--; | |
1384 | i915_vma_unpin(vma); | |
1385 | } | |
1386 | ||
4dc84b77 | 1387 | static void ring_context_unpin(struct intel_context *ce) |
d901e8e6 | 1388 | { |
a2bbf714 | 1389 | __context_unpin_ppgtt(ce->gem_context); |
d901e8e6 | 1390 | __context_unpin(ce); |
e8a9c58f CW |
1391 | } |
1392 | ||
3204c343 CW |
1393 | static struct i915_vma * |
1394 | alloc_context_vma(struct intel_engine_cs *engine) | |
1395 | { | |
1396 | struct drm_i915_private *i915 = engine->i915; | |
1397 | struct drm_i915_gem_object *obj; | |
1398 | struct i915_vma *vma; | |
d2b4b979 | 1399 | int err; |
3204c343 | 1400 | |
8475355f | 1401 | obj = i915_gem_object_create_shmem(i915, engine->context_size); |
3204c343 CW |
1402 | if (IS_ERR(obj)) |
1403 | return ERR_CAST(obj); | |
1404 | ||
a679f58d CW |
1405 | /* |
1406 | * Try to make the context utilize L3 as well as LLC. | |
1407 | * | |
1408 | * On VLV we don't have L3 controls in the PTEs so we | |
1409 | * shouldn't touch the cache level, especially as that | |
1410 | * would make the object snooped which might have a | |
1411 | * negative performance impact. | |
1412 | * | |
1413 | * Snooping is required on non-llc platforms in execlist | |
1414 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1415 | * get snooping anyway regardless of cache_level. | |
1416 | * | |
1417 | * This is only applicable for Ivy Bridge devices since | |
1418 | * later platforms don't have L3 control bits in the PTE. | |
1419 | */ | |
1420 | if (IS_IVYBRIDGE(i915)) | |
1421 | i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); | |
1422 | ||
d2b4b979 CW |
1423 | if (engine->default_state) { |
1424 | void *defaults, *vaddr; | |
1425 | ||
1426 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1427 | if (IS_ERR(vaddr)) { | |
1428 | err = PTR_ERR(vaddr); | |
1429 | goto err_obj; | |
1430 | } | |
1431 | ||
1432 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1433 | I915_MAP_WB); | |
1434 | if (IS_ERR(defaults)) { | |
1435 | err = PTR_ERR(defaults); | |
1436 | goto err_map; | |
1437 | } | |
1438 | ||
1439 | memcpy(vaddr, defaults, engine->context_size); | |
d2b4b979 | 1440 | i915_gem_object_unpin_map(engine->default_state); |
d2b4b979 | 1441 | |
a679f58d CW |
1442 | i915_gem_object_flush_map(obj); |
1443 | i915_gem_object_unpin_map(obj); | |
3204c343 CW |
1444 | } |
1445 | ||
82ad6443 | 1446 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); |
d2b4b979 CW |
1447 | if (IS_ERR(vma)) { |
1448 | err = PTR_ERR(vma); | |
1449 | goto err_obj; | |
1450 | } | |
3204c343 CW |
1451 | |
1452 | return vma; | |
d2b4b979 CW |
1453 | |
1454 | err_map: | |
1455 | i915_gem_object_unpin_map(obj); | |
1456 | err_obj: | |
1457 | i915_gem_object_put(obj); | |
1458 | return ERR_PTR(err); | |
3204c343 CW |
1459 | } |
1460 | ||
95f697eb | 1461 | static int ring_context_pin(struct intel_context *ce) |
0cb26a8e | 1462 | { |
95f697eb | 1463 | struct intel_engine_cs *engine = ce->engine; |
1fc44d9b | 1464 | int err; |
0cb26a8e | 1465 | |
7e3d9a59 CW |
1466 | /* One ringbuffer to rule them all */ |
1467 | GEM_BUG_ON(!engine->buffer); | |
1468 | ce->ring = engine->buffer; | |
1469 | ||
63ffbcda | 1470 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1471 | struct i915_vma *vma; |
1472 | ||
1473 | vma = alloc_context_vma(engine); | |
95f697eb CW |
1474 | if (IS_ERR(vma)) |
1475 | return PTR_ERR(vma); | |
3204c343 CW |
1476 | |
1477 | ce->state = vma; | |
1478 | } | |
1479 | ||
d901e8e6 CW |
1480 | err = __context_pin(ce); |
1481 | if (err) | |
95f697eb | 1482 | return err; |
0cb26a8e | 1483 | |
a2bbf714 CW |
1484 | err = __context_pin_ppgtt(ce->gem_context); |
1485 | if (err) | |
1486 | goto err_unpin; | |
1487 | ||
95f697eb | 1488 | return 0; |
266a240b | 1489 | |
a2bbf714 CW |
1490 | err_unpin: |
1491 | __context_unpin(ce); | |
95f697eb | 1492 | return err; |
0cb26a8e CW |
1493 | } |
1494 | ||
9726920b CW |
1495 | static void ring_context_reset(struct intel_context *ce) |
1496 | { | |
1497 | intel_ring_reset(ce->ring, 0); | |
1498 | } | |
1499 | ||
4dc84b77 | 1500 | static const struct intel_context_ops ring_context_ops = { |
95f697eb | 1501 | .pin = ring_context_pin, |
4dc84b77 | 1502 | .unpin = ring_context_unpin, |
9726920b | 1503 | |
6eee33e8 CW |
1504 | .enter = intel_context_enter_engine, |
1505 | .exit = intel_context_exit_engine, | |
1506 | ||
9726920b | 1507 | .reset = ring_context_reset, |
4dc84b77 CW |
1508 | .destroy = ring_context_destroy, |
1509 | }; | |
1510 | ||
ab53497b | 1511 | static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt) |
b3ee09a4 CW |
1512 | { |
1513 | const struct intel_engine_cs * const engine = rq->engine; | |
1514 | u32 *cs; | |
1515 | ||
1516 | cs = intel_ring_begin(rq, 6); | |
1517 | if (IS_ERR(cs)) | |
1518 | return PTR_ERR(cs); | |
1519 | ||
1520 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1521 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); |
b3ee09a4 CW |
1522 | *cs++ = PP_DIR_DCLV_2G; |
1523 | ||
1524 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1525 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
b3ee09a4 CW |
1526 | *cs++ = ppgtt->pd.base.ggtt_offset << 10; |
1527 | ||
1528 | intel_ring_advance(rq, cs); | |
1529 | ||
1530 | return 0; | |
1531 | } | |
1532 | ||
d9d117e4 CW |
1533 | static int flush_pd_dir(struct i915_request *rq) |
1534 | { | |
1535 | const struct intel_engine_cs * const engine = rq->engine; | |
1536 | u32 *cs; | |
1537 | ||
1538 | cs = intel_ring_begin(rq, 4); | |
1539 | if (IS_ERR(cs)) | |
1540 | return PTR_ERR(cs); | |
1541 | ||
1542 | /* Stall until the page table load is complete */ | |
1543 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
baba6e57 | 1544 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
51797499 | 1545 | *cs++ = i915_scratch_offset(rq->i915); |
d9d117e4 CW |
1546 | *cs++ = MI_NOOP; |
1547 | ||
1548 | intel_ring_advance(rq, cs); | |
1549 | return 0; | |
1550 | } | |
1551 | ||
e61e0f51 | 1552 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1553 | { |
1554 | struct drm_i915_private *i915 = rq->i915; | |
1555 | struct intel_engine_cs *engine = rq->engine; | |
1556 | enum intel_engine_id id; | |
8a68d464 CW |
1557 | const int num_engines = |
1558 | IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; | |
1fc719d1 | 1559 | bool force_restore = false; |
8911a31c CW |
1560 | int len; |
1561 | u32 *cs; | |
1562 | ||
1563 | flags |= MI_MM_SPACE_GTT; | |
1564 | if (IS_HASWELL(i915)) | |
1565 | /* These flags are for resource streamer on HSW+ */ | |
1566 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1567 | else | |
1215d28e | 1568 | /* We need to save the extended state for powersaving modes */ |
8911a31c CW |
1569 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; |
1570 | ||
1571 | len = 4; | |
cf819eff | 1572 | if (IS_GEN(i915, 7)) |
8a68d464 | 1573 | len += 2 + (num_engines ? 4 * num_engines + 6 : 0); |
1215d28e CW |
1574 | else if (IS_GEN(i915, 5)) |
1575 | len += 2; | |
1fc719d1 CW |
1576 | if (flags & MI_FORCE_RESTORE) { |
1577 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1578 | flags &= ~MI_FORCE_RESTORE; | |
1579 | force_restore = true; | |
1580 | len += 2; | |
1581 | } | |
8911a31c CW |
1582 | |
1583 | cs = intel_ring_begin(rq, len); | |
1584 | if (IS_ERR(cs)) | |
1585 | return PTR_ERR(cs); | |
1586 | ||
1587 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1588 | if (IS_GEN(i915, 7)) { |
8911a31c | 1589 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
8a68d464 | 1590 | if (num_engines) { |
8911a31c CW |
1591 | struct intel_engine_cs *signaller; |
1592 | ||
8a68d464 | 1593 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1594 | for_each_engine(signaller, i915, id) { |
1595 | if (signaller == engine) | |
1596 | continue; | |
1597 | ||
1598 | *cs++ = i915_mmio_reg_offset( | |
1599 | RING_PSMI_CTL(signaller->mmio_base)); | |
1600 | *cs++ = _MASKED_BIT_ENABLE( | |
1601 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1602 | } | |
1603 | } | |
1215d28e CW |
1604 | } else if (IS_GEN(i915, 5)) { |
1605 | /* | |
1606 | * This w/a is only listed for pre-production ilk a/b steppings, | |
1607 | * but is also mentioned for programming the powerctx. To be | |
1608 | * safe, just apply the workaround; we do not use SyncFlush so | |
1609 | * this should never take effect and so be a no-op! | |
1610 | */ | |
1611 | *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; | |
8911a31c CW |
1612 | } |
1613 | ||
1fc719d1 CW |
1614 | if (force_restore) { |
1615 | /* | |
1616 | * The HW doesn't handle being told to restore the current | |
1617 | * context very well. Quite often it likes goes to go off and | |
1618 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1619 | * A very simple fix to force the reload is to simply switch | |
1620 | * away from the current context and back again. | |
1621 | * | |
1622 | * Note that the kernel_context will contain random state | |
1623 | * following the INHIBIT_RESTORE. We accept this since we | |
1624 | * never use the kernel_context state; it is merely a | |
1625 | * placeholder we use to flush other contexts. | |
1626 | */ | |
1627 | *cs++ = MI_SET_CONTEXT; | |
9dbfea98 | 1628 | *cs++ = i915_ggtt_offset(engine->kernel_context->state) | |
1fc719d1 CW |
1629 | MI_MM_SPACE_GTT | |
1630 | MI_RESTORE_INHIBIT; | |
1631 | } | |
1632 | ||
8911a31c CW |
1633 | *cs++ = MI_NOOP; |
1634 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1635 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1636 | /* |
1637 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1638 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1639 | */ | |
1640 | *cs++ = MI_NOOP; | |
1641 | ||
cf819eff | 1642 | if (IS_GEN(i915, 7)) { |
8a68d464 | 1643 | if (num_engines) { |
8911a31c CW |
1644 | struct intel_engine_cs *signaller; |
1645 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1646 | ||
8a68d464 | 1647 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1648 | for_each_engine(signaller, i915, id) { |
1649 | if (signaller == engine) | |
1650 | continue; | |
1651 | ||
1652 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1653 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1654 | *cs++ = _MASKED_BIT_DISABLE( | |
1655 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1656 | } | |
1657 | ||
1658 | /* Insert a delay before the next switch! */ | |
1659 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1660 | *cs++ = i915_mmio_reg_offset(last_reg); | |
51797499 | 1661 | *cs++ = i915_scratch_offset(rq->i915); |
8911a31c CW |
1662 | *cs++ = MI_NOOP; |
1663 | } | |
1664 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1215d28e CW |
1665 | } else if (IS_GEN(i915, 5)) { |
1666 | *cs++ = MI_SUSPEND_FLUSH; | |
8911a31c CW |
1667 | } |
1668 | ||
1669 | intel_ring_advance(rq, cs); | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
e61e0f51 | 1674 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1675 | { |
1676 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1677 | int i; | |
1678 | ||
1679 | if (!remap_info) | |
1680 | return 0; | |
1681 | ||
1682 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1683 | if (IS_ERR(cs)) | |
1684 | return PTR_ERR(cs); | |
1685 | ||
1686 | /* | |
1687 | * Note: We do not worry about the concurrent register cacheline hang | |
1688 | * here because no other code should access these registers other than | |
1689 | * at initialization time. | |
1690 | */ | |
1691 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1692 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1693 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1694 | *cs++ = remap_info[i]; | |
1695 | } | |
1696 | *cs++ = MI_NOOP; | |
1697 | intel_ring_advance(rq, cs); | |
1698 | ||
1699 | return 0; | |
1700 | } | |
1701 | ||
e61e0f51 | 1702 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1703 | { |
1704 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 | 1705 | struct i915_gem_context *ctx = rq->gem_context; |
e568ac38 CW |
1706 | struct i915_address_space *vm = |
1707 | ctx->vm ?: &rq->i915->mm.aliasing_ppgtt->vm; | |
b3ee09a4 | 1708 | unsigned int unwind_mm = 0; |
8911a31c CW |
1709 | u32 hw_flags = 0; |
1710 | int ret, i; | |
1711 | ||
8911a31c CW |
1712 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); |
1713 | ||
e568ac38 | 1714 | if (vm) { |
ab53497b | 1715 | struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
e2a13d1b CW |
1716 | int loops; |
1717 | ||
1718 | /* | |
1719 | * Baytail takes a little more convincing that it really needs | |
1720 | * to reload the PD between contexts. It is not just a little | |
1721 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1722 | * adding a long loop around flush_pd_dir) is not as effective | |
1723 | * as reloading the PD umpteen times. 32 is derived from | |
1724 | * experimentation (gem_exec_parallel/fds) and has no good | |
1725 | * explanation. | |
1726 | */ | |
1727 | loops = 1; | |
8a68d464 | 1728 | if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) |
e2a13d1b CW |
1729 | loops = 32; |
1730 | ||
1731 | do { | |
1732 | ret = load_pd_dir(rq, ppgtt); | |
1733 | if (ret) | |
1734 | goto err; | |
1735 | } while (--loops); | |
8911a31c | 1736 | |
8a68d464 CW |
1737 | if (ppgtt->pd_dirty_engines & engine->mask) { |
1738 | unwind_mm = engine->mask; | |
1739 | ppgtt->pd_dirty_engines &= ~unwind_mm; | |
b3ee09a4 CW |
1740 | hw_flags = MI_FORCE_RESTORE; |
1741 | } | |
8911a31c CW |
1742 | } |
1743 | ||
b3ee09a4 | 1744 | if (rq->hw_context->state) { |
8a68d464 | 1745 | GEM_BUG_ON(engine->id != RCS0); |
8911a31c CW |
1746 | |
1747 | /* | |
1748 | * The kernel context(s) is treated as pure scratch and is not | |
1749 | * expected to retain any state (as we sacrifice it during | |
1750 | * suspend and on resume it may be corrupted). This is ok, | |
1751 | * as nothing actually executes using the kernel context; it | |
1752 | * is purely used for flushing user contexts. | |
1753 | */ | |
b3ee09a4 | 1754 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1755 | hw_flags = MI_RESTORE_INHIBIT; |
1756 | ||
1757 | ret = mi_set_context(rq, hw_flags); | |
1758 | if (ret) | |
1759 | goto err_mm; | |
8911a31c | 1760 | } |
8911a31c | 1761 | |
e568ac38 | 1762 | if (vm) { |
06348d30 CW |
1763 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1764 | if (ret) | |
1765 | goto err_mm; | |
1766 | ||
d9d117e4 CW |
1767 | ret = flush_pd_dir(rq); |
1768 | if (ret) | |
1769 | goto err_mm; | |
06348d30 CW |
1770 | |
1771 | /* | |
1772 | * Not only do we need a full barrier (post-sync write) after | |
1773 | * invalidating the TLBs, but we need to wait a little bit | |
1774 | * longer. Whether this is merely delaying us, or the | |
1775 | * subsequent flush is a key part of serialising with the | |
1776 | * post-sync op, this extra pass appears vital before a | |
1777 | * mm switch! | |
1778 | */ | |
1779 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1780 | if (ret) | |
1781 | goto err_mm; | |
1782 | ||
1783 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1784 | if (ret) | |
1785 | goto err_mm; | |
8911a31c CW |
1786 | } |
1787 | ||
b3ee09a4 | 1788 | if (ctx->remap_slice) { |
8911a31c | 1789 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1790 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1791 | continue; |
1792 | ||
1793 | ret = remap_l3(rq, i); | |
1794 | if (ret) | |
b3ee09a4 | 1795 | goto err_mm; |
8911a31c CW |
1796 | } |
1797 | ||
b3ee09a4 | 1798 | ctx->remap_slice = 0; |
8911a31c CW |
1799 | } |
1800 | ||
1801 | return 0; | |
1802 | ||
8911a31c | 1803 | err_mm: |
b3ee09a4 | 1804 | if (unwind_mm) |
e568ac38 | 1805 | i915_vm_to_ppgtt(vm)->pd_dirty_engines |= unwind_mm; |
8911a31c CW |
1806 | err: |
1807 | return ret; | |
1808 | } | |
1809 | ||
e61e0f51 | 1810 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1811 | { |
fd138212 | 1812 | int ret; |
6310346e | 1813 | |
08819549 | 1814 | GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); |
85474441 | 1815 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1816 | |
5f5800a7 CW |
1817 | /* |
1818 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1819 | * we start building the request - in which case we will just |
1820 | * have to repeat work. | |
1821 | */ | |
a0442461 | 1822 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1823 | |
928f8f42 CW |
1824 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1825 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
fd138212 CW |
1826 | if (ret) |
1827 | return ret; | |
6310346e | 1828 | |
928f8f42 | 1829 | ret = switch_context(request); |
3fef5cda CW |
1830 | if (ret) |
1831 | return ret; | |
1832 | ||
a0442461 | 1833 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1834 | return 0; |
9d773091 CW |
1835 | } |
1836 | ||
fd138212 | 1837 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1838 | { |
e61e0f51 | 1839 | struct i915_request *target; |
e95433c7 CW |
1840 | long timeout; |
1841 | ||
95aebcb2 | 1842 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1843 | return 0; |
1844 | ||
36620032 | 1845 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1846 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1847 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1848 | if (bytes <= __intel_ring_space(target->postfix, |
1849 | ring->emit, ring->size)) | |
987046ad | 1850 | break; |
79bbcc29 | 1851 | } |
29b1b415 | 1852 | |
675d9ad7 | 1853 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1854 | return -ENOSPC; |
1855 | ||
e61e0f51 | 1856 | timeout = i915_request_wait(target, |
e95433c7 CW |
1857 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
1858 | MAX_SCHEDULE_TIMEOUT); | |
1859 | if (timeout < 0) | |
1860 | return timeout; | |
7da844c5 | 1861 | |
e61e0f51 | 1862 | i915_request_retire_upto(target); |
7da844c5 CW |
1863 | |
1864 | intel_ring_update_space(ring); | |
1865 | GEM_BUG_ON(ring->space < bytes); | |
1866 | return 0; | |
29b1b415 JH |
1867 | } |
1868 | ||
e61e0f51 | 1869 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1870 | { |
e61e0f51 | 1871 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1872 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1873 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1874 | unsigned int need_wrap = 0; | |
1875 | unsigned int total_bytes; | |
73dec95e | 1876 | u32 *cs; |
29b1b415 | 1877 | |
6492ca79 CW |
1878 | /* Packets must be qword aligned. */ |
1879 | GEM_BUG_ON(num_dwords & 1); | |
1880 | ||
e61e0f51 | 1881 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1882 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1883 | |
5e5655c3 CW |
1884 | if (unlikely(total_bytes > remain_usable)) { |
1885 | const int remain_actual = ring->size - ring->emit; | |
1886 | ||
1887 | if (bytes > remain_usable) { | |
1888 | /* | |
1889 | * Not enough space for the basic request. So need to | |
1890 | * flush out the remainder and then wait for | |
1891 | * base + reserved. | |
1892 | */ | |
1893 | total_bytes += remain_actual; | |
1894 | need_wrap = remain_actual | 1; | |
1895 | } else { | |
1896 | /* | |
1897 | * The base request will fit but the reserved space | |
1898 | * falls off the end. So we don't need an immediate | |
1899 | * wrap and only need to effectively wait for the | |
1900 | * reserved size from the start of ringbuffer. | |
1901 | */ | |
e61e0f51 | 1902 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 1903 | } |
cbcc80df MK |
1904 | } |
1905 | ||
5e5655c3 | 1906 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1907 | int ret; |
1908 | ||
1909 | /* | |
1910 | * Space is reserved in the ringbuffer for finalising the | |
1911 | * request, as that cannot be allowed to fail. During request | |
1912 | * finalisation, reserved_space is set to 0 to stop the | |
1913 | * overallocation and the assumption is that then we never need | |
1914 | * to wait (which has the risk of failing with EINTR). | |
1915 | * | |
e61e0f51 | 1916 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 1917 | */ |
e61e0f51 | 1918 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
1919 | |
1920 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 1921 | if (unlikely(ret)) |
73dec95e | 1922 | return ERR_PTR(ret); |
cbcc80df MK |
1923 | } |
1924 | ||
987046ad | 1925 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1926 | need_wrap &= ~1; |
1927 | GEM_BUG_ON(need_wrap > ring->space); | |
1928 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 1929 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 1930 | |
987046ad | 1931 | /* Fill the tail with MI_NOOP */ |
46b86332 | 1932 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 1933 | ring->space -= need_wrap; |
46b86332 | 1934 | ring->emit = 0; |
987046ad | 1935 | } |
304d695c | 1936 | |
e6ba9992 | 1937 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1938 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1939 | cs = ring->vaddr + ring->emit; |
46b86332 | 1940 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 1941 | ring->emit += bytes; |
1dae2dfb | 1942 | ring->space -= bytes; |
73dec95e TU |
1943 | |
1944 | return cs; | |
8187a2b7 | 1945 | } |
78501eac | 1946 | |
753b1ad4 | 1947 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 1948 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 1949 | { |
1f177a13 CW |
1950 | int num_dwords; |
1951 | void *cs; | |
753b1ad4 | 1952 | |
1f177a13 | 1953 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
1954 | if (num_dwords == 0) |
1955 | return 0; | |
1956 | ||
1f177a13 CW |
1957 | num_dwords = CACHELINE_DWORDS - num_dwords; |
1958 | GEM_BUG_ON(num_dwords & 1); | |
1959 | ||
e61e0f51 | 1960 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
1961 | if (IS_ERR(cs)) |
1962 | return PTR_ERR(cs); | |
753b1ad4 | 1963 | |
1f177a13 | 1964 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 1965 | intel_ring_advance(rq, cs); |
753b1ad4 | 1966 | |
1f177a13 | 1967 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
1968 | return 0; |
1969 | } | |
1970 | ||
e61e0f51 | 1971 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 1972 | { |
baba6e57 | 1973 | struct intel_uncore *uncore = request->engine->uncore; |
881f47b6 | 1974 | |
d2d551c0 | 1975 | intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); |
76f8421f | 1976 | |
881f47b6 | 1977 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1978 | |
1979 | /* Disable notification that the ring is IDLE. The GT | |
1980 | * will then assume that it is busy and bring it out of rc6. | |
1981 | */ | |
d2d551c0 DCS |
1982 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
1983 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1984 | |
1985 | /* Clear the context id. Here be magic! */ | |
d2d551c0 | 1986 | intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); |
0206e353 | 1987 | |
12f55818 | 1988 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
d2d551c0 | 1989 | if (__intel_wait_for_register_fw(uncore, |
02b312d0 CW |
1990 | GEN6_BSD_SLEEP_PSMI_CONTROL, |
1991 | GEN6_BSD_SLEEP_INDICATOR, | |
1992 | 0, | |
1993 | 1000, 0, NULL)) | |
12f55818 | 1994 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1995 | |
12f55818 | 1996 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1997 | i9xx_submit_request(request); |
12f55818 CW |
1998 | |
1999 | /* Let the ring send IDLE messages to the GT again, | |
2000 | * and so let it sleep to conserve power when idle. | |
2001 | */ | |
d2d551c0 DCS |
2002 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
2003 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
76f8421f | 2004 | |
d2d551c0 | 2005 | intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); |
881f47b6 XH |
2006 | } |
2007 | ||
06348d30 | 2008 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 2009 | { |
73dec95e | 2010 | u32 cmd, *cs; |
b72f3acb | 2011 | |
e61e0f51 | 2012 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
2013 | if (IS_ERR(cs)) |
2014 | return PTR_ERR(cs); | |
b72f3acb | 2015 | |
71a77e07 | 2016 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 2017 | |
70b73f9a CW |
2018 | /* |
2019 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2020 | * commands, such as breadcrumb interrupts, are strictly ordered |
2021 | * wrt the contents of the write cache being flushed to memory | |
2022 | * (and thus being coherent from the CPU). | |
2023 | */ | |
2024 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2025 | ||
9a289771 | 2026 | /* |
70b73f9a | 2027 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2028 | * "If ENABLED, all TLBs will be invalidated once the flush |
2029 | * operation is complete. This bit is only valid when the | |
2030 | * Post-Sync Operation field is a value of 1h or 3h." | |
2031 | */ | |
70b73f9a | 2032 | cmd |= flags; |
f0a1fb10 | 2033 | |
73dec95e TU |
2034 | *cs++ = cmd; |
2035 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2036 | *cs++ = 0; |
73dec95e | 2037 | *cs++ = MI_NOOP; |
70b73f9a | 2038 | |
e61e0f51 | 2039 | intel_ring_advance(rq, cs); |
70b73f9a | 2040 | |
1c7a0623 BW |
2041 | return 0; |
2042 | } | |
2043 | ||
70b73f9a CW |
2044 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2045 | { | |
06348d30 | 2046 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2047 | } |
2048 | ||
2049 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2050 | { | |
2051 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2052 | } | |
2053 | ||
d7d4eedd | 2054 | static int |
e61e0f51 | 2055 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2056 | u64 offset, u32 len, |
2057 | unsigned int dispatch_flags) | |
d7d4eedd | 2058 | { |
73dec95e | 2059 | u32 *cs; |
d7d4eedd | 2060 | |
e61e0f51 | 2061 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2062 | if (IS_ERR(cs)) |
2063 | return PTR_ERR(cs); | |
d7d4eedd | 2064 | |
73dec95e | 2065 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2066 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2067 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2068 | *cs++ = offset; |
e61e0f51 | 2069 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2070 | |
2071 | return 0; | |
2072 | } | |
2073 | ||
881f47b6 | 2074 | static int |
e61e0f51 | 2075 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2076 | u64 offset, u32 len, |
2077 | unsigned int dispatch_flags) | |
881f47b6 | 2078 | { |
73dec95e | 2079 | u32 *cs; |
ab6f8e32 | 2080 | |
e61e0f51 | 2081 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2082 | if (IS_ERR(cs)) |
2083 | return PTR_ERR(cs); | |
e1f99ce6 | 2084 | |
73dec95e TU |
2085 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2086 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2087 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2088 | *cs++ = offset; |
e61e0f51 | 2089 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2090 | |
0206e353 | 2091 | return 0; |
881f47b6 XH |
2092 | } |
2093 | ||
549f7365 CW |
2094 | /* Blitter support (SandyBridge+) */ |
2095 | ||
e61e0f51 | 2096 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2097 | { |
70b73f9a | 2098 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2099 | } |
2100 | ||
ff44ad51 CW |
2101 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2102 | { | |
2103 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2104 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2105 | |
2106 | engine->park = NULL; | |
2107 | engine->unpark = NULL; | |
ff44ad51 CW |
2108 | } |
2109 | ||
2110 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2111 | { | |
aba5e278 | 2112 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2113 | engine->submit_request = gen6_bsd_submit_request; |
2114 | } | |
2115 | ||
45b9c968 CW |
2116 | static void ring_destroy(struct intel_engine_cs *engine) |
2117 | { | |
2118 | struct drm_i915_private *dev_priv = engine->i915; | |
2119 | ||
2120 | WARN_ON(INTEL_GEN(dev_priv) > 2 && | |
2121 | (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); | |
2122 | ||
2123 | intel_ring_unpin(engine->buffer); | |
2124 | intel_ring_put(engine->buffer); | |
2125 | ||
2126 | intel_engine_cleanup_common(engine); | |
2127 | kfree(engine); | |
2128 | } | |
2129 | ||
11334c6a CW |
2130 | static void setup_irq(struct intel_engine_cs *engine) |
2131 | { | |
2132 | struct drm_i915_private *i915 = engine->i915; | |
2133 | ||
2134 | if (INTEL_GEN(i915) >= 6) { | |
2135 | engine->irq_enable = gen6_irq_enable; | |
2136 | engine->irq_disable = gen6_irq_disable; | |
2137 | } else if (INTEL_GEN(i915) >= 5) { | |
2138 | engine->irq_enable = gen5_irq_enable; | |
2139 | engine->irq_disable = gen5_irq_disable; | |
2140 | } else if (INTEL_GEN(i915) >= 3) { | |
2141 | engine->irq_enable = i9xx_irq_enable; | |
2142 | engine->irq_disable = i9xx_irq_disable; | |
2143 | } else { | |
2144 | engine->irq_enable = i8xx_irq_enable; | |
2145 | engine->irq_disable = i8xx_irq_disable; | |
2146 | } | |
2147 | } | |
2148 | ||
2149 | static void setup_common(struct intel_engine_cs *engine) | |
06a2fe22 | 2150 | { |
11334c6a CW |
2151 | struct drm_i915_private *i915 = engine->i915; |
2152 | ||
79e6770c | 2153 | /* gen8+ are only supported with execlists */ |
11334c6a | 2154 | GEM_BUG_ON(INTEL_GEN(i915) >= 8); |
79e6770c | 2155 | |
11334c6a | 2156 | setup_irq(engine); |
618e4ca7 | 2157 | |
45b9c968 CW |
2158 | engine->destroy = ring_destroy; |
2159 | ||
79ffac85 | 2160 | engine->resume = xcs_resume; |
5adfb772 CW |
2161 | engine->reset.prepare = reset_prepare; |
2162 | engine->reset.reset = reset_ring; | |
2163 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2164 | |
4dc84b77 | 2165 | engine->cops = &ring_context_ops; |
f73e7399 CW |
2166 | engine->request_alloc = ring_request_alloc; |
2167 | ||
85474441 CW |
2168 | /* |
2169 | * Using a global execution timeline; the previous final breadcrumb is | |
2170 | * equivalent to our next initial bread so we can elide | |
2171 | * engine->emit_init_breadcrumb(). | |
2172 | */ | |
2173 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
11334c6a | 2174 | if (IS_GEN(i915, 5)) |
85474441 | 2175 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2176 | |
2177 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2178 | |
11334c6a | 2179 | if (INTEL_GEN(i915) >= 6) |
803688ba | 2180 | engine->emit_bb_start = gen6_emit_bb_start; |
11334c6a | 2181 | else if (INTEL_GEN(i915) >= 4) |
803688ba | 2182 | engine->emit_bb_start = i965_emit_bb_start; |
11334c6a | 2183 | else if (IS_I830(i915) || IS_I845G(i915)) |
803688ba | 2184 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2185 | else |
803688ba | 2186 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2187 | } |
2188 | ||
11334c6a | 2189 | static void setup_rcs(struct intel_engine_cs *engine) |
5c1143bb | 2190 | { |
11334c6a | 2191 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2192 | |
11334c6a | 2193 | if (HAS_L3_DPF(i915)) |
61ff75ac | 2194 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
f8973c21 | 2195 | |
fa6f071d DCS |
2196 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2197 | ||
11334c6a | 2198 | if (INTEL_GEN(i915) >= 7) { |
e2f80391 | 2199 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2200 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2201 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
11334c6a | 2202 | } else if (IS_GEN(i915, 6)) { |
caa5915b CW |
2203 | engine->init_context = intel_rcs_ctx_init; |
2204 | engine->emit_flush = gen6_render_ring_flush; | |
85474441 | 2205 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
11334c6a | 2206 | } else if (IS_GEN(i915, 5)) { |
c7fe7d25 | 2207 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2208 | } else { |
11334c6a | 2209 | if (INTEL_GEN(i915) < 4) |
c7fe7d25 | 2210 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2211 | else |
c7fe7d25 | 2212 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2213 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2214 | } |
707d9cf9 | 2215 | |
11334c6a | 2216 | if (IS_HASWELL(i915)) |
803688ba | 2217 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2218 | |
79ffac85 | 2219 | engine->resume = rcs_resume; |
5c1143bb XH |
2220 | } |
2221 | ||
11334c6a | 2222 | static void setup_vcs(struct intel_engine_cs *engine) |
5c1143bb | 2223 | { |
11334c6a | 2224 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2225 | |
11334c6a | 2226 | if (INTEL_GEN(i915) >= 6) { |
0fd2c201 | 2227 | /* gen6 bsd needs a special wa for tail updates */ |
11334c6a | 2228 | if (IS_GEN(i915, 6)) |
ff44ad51 | 2229 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2230 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2231 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2232 | |
11334c6a | 2233 | if (IS_GEN(i915, 6)) |
85474441 | 2234 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2235 | else |
85474441 | 2236 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2237 | } else { |
c7fe7d25 | 2238 | engine->emit_flush = bsd_ring_flush; |
11334c6a | 2239 | if (IS_GEN(i915, 5)) |
e2f80391 | 2240 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2241 | else |
e2f80391 | 2242 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2243 | } |
5c1143bb | 2244 | } |
549f7365 | 2245 | |
11334c6a | 2246 | static void setup_bcs(struct intel_engine_cs *engine) |
549f7365 | 2247 | { |
11334c6a | 2248 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2249 | |
c7fe7d25 | 2250 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2251 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2252 | |
11334c6a | 2253 | if (IS_GEN(i915, 6)) |
85474441 | 2254 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2255 | else |
85474441 | 2256 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
549f7365 | 2257 | } |
a7b9761d | 2258 | |
11334c6a | 2259 | static void setup_vecs(struct intel_engine_cs *engine) |
9a8a2213 | 2260 | { |
11334c6a | 2261 | struct drm_i915_private *i915 = engine->i915; |
caa5915b | 2262 | |
11334c6a | 2263 | GEM_BUG_ON(INTEL_GEN(i915) < 7); |
06a2fe22 | 2264 | |
c7fe7d25 | 2265 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2266 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2267 | engine->irq_enable = hsw_vebox_irq_enable; | |
2268 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2269 | |
85474441 | 2270 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
11334c6a CW |
2271 | } |
2272 | ||
2273 | int intel_ring_submission_setup(struct intel_engine_cs *engine) | |
2274 | { | |
2275 | setup_common(engine); | |
2276 | ||
2277 | switch (engine->class) { | |
2278 | case RENDER_CLASS: | |
2279 | setup_rcs(engine); | |
2280 | break; | |
2281 | case VIDEO_DECODE_CLASS: | |
2282 | setup_vcs(engine); | |
2283 | break; | |
2284 | case COPY_ENGINE_CLASS: | |
2285 | setup_bcs(engine); | |
2286 | break; | |
2287 | case VIDEO_ENHANCEMENT_CLASS: | |
2288 | setup_vecs(engine); | |
2289 | break; | |
2290 | default: | |
2291 | MISSING_CASE(engine->class); | |
2292 | return -ENODEV; | |
2293 | } | |
2294 | ||
2295 | return 0; | |
2296 | } | |
2297 | ||
2298 | int intel_ring_submission_init(struct intel_engine_cs *engine) | |
2299 | { | |
2300 | struct i915_timeline *timeline; | |
2301 | struct intel_ring *ring; | |
2302 | int err; | |
2303 | ||
2304 | timeline = i915_timeline_create(engine->i915, engine->status_page.vma); | |
2305 | if (IS_ERR(timeline)) { | |
2306 | err = PTR_ERR(timeline); | |
2307 | goto err; | |
2308 | } | |
2309 | GEM_BUG_ON(timeline->has_initial_breadcrumb); | |
2310 | ||
2311 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
2312 | i915_timeline_put(timeline); | |
2313 | if (IS_ERR(ring)) { | |
2314 | err = PTR_ERR(ring); | |
2315 | goto err; | |
2316 | } | |
2317 | ||
2318 | err = intel_ring_pin(ring); | |
2319 | if (err) | |
2320 | goto err_ring; | |
caa5915b | 2321 | |
11334c6a CW |
2322 | GEM_BUG_ON(engine->buffer); |
2323 | engine->buffer = ring; | |
2324 | ||
2325 | err = intel_engine_init_common(engine); | |
2326 | if (err) | |
2327 | goto err_unpin; | |
2328 | ||
2329 | GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma); | |
2330 | ||
2331 | return 0; | |
2332 | ||
2333 | err_unpin: | |
2334 | intel_ring_unpin(ring); | |
2335 | err_ring: | |
2336 | intel_ring_put(ring); | |
2337 | err: | |
2338 | intel_engine_cleanup_common(engine); | |
2339 | return err; | |
9a8a2213 | 2340 | } |