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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa | 33 | |
10be98a7 CW |
34 | #include "gem/i915_gem_context.h" |
35 | ||
7c2fa7fa | 36 | #include "i915_drv.h" |
62fdfeaf | 37 | #include "i915_trace.h" |
10be98a7 | 38 | #include "intel_context.h" |
2006058e | 39 | #include "intel_gt.h" |
cf1c97dc | 40 | #include "intel_gt_irq.h" |
d762043f | 41 | #include "intel_gt_pm_irq.h" |
112ed2d3 | 42 | #include "intel_reset.h" |
7d3c425f | 43 | #include "intel_workarounds.h" |
62fdfeaf | 44 | |
a0442461 CW |
45 | /* Rough estimate of the typical request size, performing a flush, |
46 | * set-context and then emitting the batch. | |
47 | */ | |
48 | #define LEGACY_REQUEST_SIZE 200 | |
49 | ||
95aebcb2 | 50 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
95aebcb2 CW |
52 | unsigned int space; |
53 | ||
54 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
55 | ||
56 | ring->space = space; | |
57 | return space; | |
ebd0fd4b DG |
58 | } |
59 | ||
b72f3acb | 60 | static int |
e61e0f51 | 61 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 62 | { |
a889580c | 63 | unsigned int num_store_dw; |
73dec95e | 64 | u32 cmd, *cs; |
46f0f8d1 CW |
65 | |
66 | cmd = MI_FLUSH; | |
a889580c | 67 | num_store_dw = 0; |
7c9cf4e3 | 68 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 69 | cmd |= MI_READ_FLUSH; |
a889580c CW |
70 | if (mode & EMIT_FLUSH) |
71 | num_store_dw = 4; | |
46f0f8d1 | 72 | |
a889580c | 73 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
74 | if (IS_ERR(cs)) |
75 | return PTR_ERR(cs); | |
46f0f8d1 | 76 | |
73dec95e | 77 | *cs++ = cmd; |
a889580c CW |
78 | while (num_store_dw--) { |
79 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
46c5847e LL |
80 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
81 | INTEL_GT_SCRATCH_FIELD_DEFAULT); | |
a889580c CW |
82 | *cs++ = 0; |
83 | } | |
84 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
85 | ||
e61e0f51 | 86 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
91 | static int | |
e61e0f51 | 92 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 93 | { |
73dec95e | 94 | u32 cmd, *cs; |
55f99bf2 | 95 | int i; |
6f392d54 | 96 | |
36d527de CW |
97 | /* |
98 | * read/write caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
101 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
102 | * also flushed at 2d versus 3d pipeline switches. | |
103 | * | |
104 | * read-only caches: | |
105 | * | |
106 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
107 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
108 | * | |
109 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
110 | * | |
111 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
112 | * invalidated when MI_EXE_FLUSH is set. | |
113 | * | |
114 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
115 | * invalidated with every MI_FLUSH. | |
116 | * | |
117 | * TLBs: | |
118 | * | |
119 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
120 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
121 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
122 | * are flushed at any MI_FLUSH. | |
123 | */ | |
124 | ||
b5321f30 | 125 | cmd = MI_FLUSH; |
7c9cf4e3 | 126 | if (mode & EMIT_INVALIDATE) { |
36d527de | 127 | cmd |= MI_EXE_FLUSH; |
cf819eff | 128 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
129 | cmd |= MI_INVALIDATE_ISP; |
130 | } | |
70eac33e | 131 | |
55f99bf2 CW |
132 | i = 2; |
133 | if (mode & EMIT_INVALIDATE) | |
134 | i += 20; | |
135 | ||
136 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
137 | if (IS_ERR(cs)) |
138 | return PTR_ERR(cs); | |
b72f3acb | 139 | |
73dec95e | 140 | *cs++ = cmd; |
55f99bf2 CW |
141 | |
142 | /* | |
143 | * A random delay to let the CS invalidate take effect? Without this | |
144 | * delay, the GPU relocation path fails as the CS does not see | |
145 | * the updated contents. Just as important, if we apply the flushes | |
146 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
147 | * write and before the invalidate on the next batch), the relocations | |
148 | * still fail. This implies that is a delay following invalidation | |
149 | * that is required to reset the caches as opposed to a delay to | |
150 | * ensure the memory is written. | |
151 | */ | |
152 | if (mode & EMIT_INVALIDATE) { | |
153 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
46c5847e LL |
154 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
155 | INTEL_GT_SCRATCH_FIELD_DEFAULT) | | |
db56f974 | 156 | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
157 | *cs++ = 0; |
158 | *cs++ = 0; | |
159 | ||
160 | for (i = 0; i < 12; i++) | |
161 | *cs++ = MI_FLUSH; | |
162 | ||
163 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
46c5847e LL |
164 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
165 | INTEL_GT_SCRATCH_FIELD_DEFAULT) | | |
db56f974 | 166 | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
167 | *cs++ = 0; |
168 | *cs++ = 0; | |
169 | } | |
170 | ||
171 | *cs++ = cmd; | |
172 | ||
e61e0f51 | 173 | intel_ring_advance(rq, cs); |
b72f3acb CW |
174 | |
175 | return 0; | |
8187a2b7 ZN |
176 | } |
177 | ||
179f4025 | 178 | /* |
8d315287 JB |
179 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
180 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
181 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
182 | * | |
183 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
184 | * produced by non-pipelined state commands), software needs to first | |
185 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
186 | * 0. | |
187 | * | |
188 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
189 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
190 | * | |
191 | * And the workaround for these two requires this workaround first: | |
192 | * | |
193 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
194 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
195 | * flushes. | |
196 | * | |
197 | * And this last workaround is tricky because of the requirements on | |
198 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
199 | * volume 2 part 1: | |
200 | * | |
201 | * "1 of the following must also be set: | |
202 | * - Render Target Cache Flush Enable ([12] of DW1) | |
203 | * - Depth Cache Flush Enable ([0] of DW1) | |
204 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
205 | * - Depth Stall ([13] of DW1) | |
206 | * - Post-Sync Operation ([13] of DW1) | |
207 | * - Notify Enable ([8] of DW1)" | |
208 | * | |
209 | * The cache flushes require the workaround flush that triggered this | |
210 | * one, so we can't use it. Depth stall would trigger the same. | |
211 | * Post-sync nonzero is what triggered this second workaround, so we | |
212 | * can't use that one either. Notify enable is IRQs, which aren't | |
213 | * really our business. That leaves only stall at scoreboard. | |
214 | */ | |
215 | static int | |
caa5915b | 216 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 217 | { |
db56f974 | 218 | u32 scratch_addr = |
46c5847e LL |
219 | intel_gt_scratch_offset(rq->engine->gt, |
220 | INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); | |
73dec95e TU |
221 | u32 *cs; |
222 | ||
e61e0f51 | 223 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
224 | if (IS_ERR(cs)) |
225 | return PTR_ERR(cs); | |
226 | ||
227 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
228 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
229 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
230 | *cs++ = 0; /* low dword */ | |
231 | *cs++ = 0; /* high dword */ | |
232 | *cs++ = MI_NOOP; | |
e61e0f51 | 233 | intel_ring_advance(rq, cs); |
73dec95e | 234 | |
e61e0f51 | 235 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
236 | if (IS_ERR(cs)) |
237 | return PTR_ERR(cs); | |
238 | ||
239 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
240 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
241 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
242 | *cs++ = 0; | |
243 | *cs++ = 0; | |
244 | *cs++ = MI_NOOP; | |
e61e0f51 | 245 | intel_ring_advance(rq, cs); |
8d315287 JB |
246 | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int | |
e61e0f51 | 251 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 252 | { |
db56f974 | 253 | u32 scratch_addr = |
46c5847e LL |
254 | intel_gt_scratch_offset(rq->engine->gt, |
255 | INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); | |
73dec95e | 256 | u32 *cs, flags = 0; |
8d315287 JB |
257 | int ret; |
258 | ||
b3111509 | 259 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 260 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
261 | if (ret) |
262 | return ret; | |
263 | ||
8d315287 JB |
264 | /* Just flush everything. Experiments have shown that reducing the |
265 | * number of bits based on the write domains has little performance | |
266 | * impact. | |
267 | */ | |
7c9cf4e3 | 268 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
269 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
270 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
271 | /* | |
272 | * Ensure that any following seqno writes only happen | |
273 | * when the render cache is indeed flushed. | |
274 | */ | |
97f209bc | 275 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 276 | } |
7c9cf4e3 | 277 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
278 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
279 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
282 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
283 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
284 | /* | |
285 | * TLB invalidate requires a post-sync write. | |
286 | */ | |
3ac78313 | 287 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 288 | } |
8d315287 | 289 | |
e61e0f51 | 290 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
291 | if (IS_ERR(cs)) |
292 | return PTR_ERR(cs); | |
8d315287 | 293 | |
73dec95e TU |
294 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
295 | *cs++ = flags; | |
296 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
297 | *cs++ = 0; | |
e61e0f51 | 298 | intel_ring_advance(rq, cs); |
8d315287 JB |
299 | |
300 | return 0; | |
301 | } | |
302 | ||
e1a73a54 | 303 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
304 | { |
305 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
306 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
307 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
308 | *cs++ = 0; | |
309 | *cs++ = 0; | |
310 | ||
311 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
312 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
46c5847e LL |
313 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
314 | INTEL_GT_SCRATCH_FIELD_DEFAULT) | | |
db56f974 | 315 | PIPE_CONTROL_GLOBAL_GTT; |
caa5915b CW |
316 | *cs++ = 0; |
317 | ||
318 | /* Finally we can flush and with it emit the breadcrumb */ | |
319 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
320 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
321 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
322 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
323 | PIPE_CONTROL_QW_WRITE | | |
324 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
325 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
326 | *cs++ = rq->fence.seqno; | |
327 | ||
caa5915b CW |
328 | *cs++ = MI_USER_INTERRUPT; |
329 | *cs++ = MI_NOOP; | |
330 | ||
331 | rq->tail = intel_ring_offset(rq, cs); | |
332 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
333 | |
334 | return cs; | |
caa5915b | 335 | } |
caa5915b | 336 | |
f3987631 | 337 | static int |
e61e0f51 | 338 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 339 | { |
73dec95e | 340 | u32 *cs; |
f3987631 | 341 | |
e61e0f51 | 342 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
343 | if (IS_ERR(cs)) |
344 | return PTR_ERR(cs); | |
f3987631 | 345 | |
73dec95e TU |
346 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
347 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
348 | *cs++ = 0; | |
349 | *cs++ = 0; | |
e61e0f51 | 350 | intel_ring_advance(rq, cs); |
f3987631 PZ |
351 | |
352 | return 0; | |
353 | } | |
354 | ||
4772eaeb | 355 | static int |
e61e0f51 | 356 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 357 | { |
db56f974 | 358 | u32 scratch_addr = |
46c5847e LL |
359 | intel_gt_scratch_offset(rq->engine->gt, |
360 | INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); | |
73dec95e | 361 | u32 *cs, flags = 0; |
4772eaeb | 362 | |
f3987631 PZ |
363 | /* |
364 | * Ensure that any following seqno writes only happen when the render | |
365 | * cache is indeed flushed. | |
366 | * | |
367 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
368 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
369 | * don't try to be clever and just set it unconditionally. | |
370 | */ | |
371 | flags |= PIPE_CONTROL_CS_STALL; | |
372 | ||
4772eaeb PZ |
373 | /* Just flush everything. Experiments have shown that reducing the |
374 | * number of bits based on the write domains has little performance | |
375 | * impact. | |
376 | */ | |
7c9cf4e3 | 377 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
378 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
379 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 380 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 381 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 382 | } |
7c9cf4e3 | 383 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
384 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
385 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
386 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
387 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
388 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
389 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 390 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
391 | /* |
392 | * TLB invalidate requires a post-sync write. | |
393 | */ | |
394 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 395 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 396 | |
add284a3 CW |
397 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
398 | ||
f3987631 PZ |
399 | /* Workaround: we must issue a pipe_control with CS-stall bit |
400 | * set before a pipe_control command that has the state cache | |
401 | * invalidate bit set. */ | |
e61e0f51 | 402 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
403 | } |
404 | ||
e61e0f51 | 405 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
406 | if (IS_ERR(cs)) |
407 | return PTR_ERR(cs); | |
4772eaeb | 408 | |
73dec95e TU |
409 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
410 | *cs++ = flags; | |
411 | *cs++ = scratch_addr; | |
412 | *cs++ = 0; | |
e61e0f51 | 413 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
e1a73a54 | 418 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
419 | { |
420 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
421 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
422 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
423 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
424 | PIPE_CONTROL_FLUSH_ENABLE | | |
425 | PIPE_CONTROL_QW_WRITE | | |
426 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
427 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
428 | *cs++ = rq->timeline->hwsp_offset; |
429 | *cs++ = rq->fence.seqno; | |
430 | ||
caa5915b CW |
431 | *cs++ = MI_USER_INTERRUPT; |
432 | *cs++ = MI_NOOP; | |
433 | ||
434 | rq->tail = intel_ring_offset(rq, cs); | |
435 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
436 | |
437 | return cs; | |
caa5915b | 438 | } |
caa5915b | 439 | |
e1a73a54 | 440 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 441 | { |
5013eb8c CW |
442 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
443 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
444 | ||
445 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
446 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
447 | *cs++ = rq->fence.seqno; | |
448 | ||
caa5915b CW |
449 | *cs++ = MI_USER_INTERRUPT; |
450 | ||
451 | rq->tail = intel_ring_offset(rq, cs); | |
452 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
453 | |
454 | return cs; | |
caa5915b | 455 | } |
caa5915b | 456 | |
1212bd82 | 457 | #define GEN7_XCS_WA 32 |
e1a73a54 | 458 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
459 | { |
460 | int i; | |
461 | ||
5013eb8c CW |
462 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
463 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
464 | ||
465 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
466 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
467 | *cs++ = rq->fence.seqno; | |
468 | ||
1212bd82 CW |
469 | for (i = 0; i < GEN7_XCS_WA; i++) { |
470 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
471 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
472 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
473 | } |
474 | ||
475 | *cs++ = MI_FLUSH_DW; | |
476 | *cs++ = 0; | |
477 | *cs++ = 0; | |
478 | ||
479 | *cs++ = MI_USER_INTERRUPT; | |
519a0194 | 480 | *cs++ = MI_NOOP; |
1212bd82 CW |
481 | |
482 | rq->tail = intel_ring_offset(rq, cs); | |
483 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
484 | |
485 | return cs; | |
1212bd82 | 486 | } |
1212bd82 CW |
487 | #undef GEN7_XCS_WA |
488 | ||
060f2322 CW |
489 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
490 | { | |
491 | /* | |
492 | * Keep the render interrupt unmasked as this papers over | |
493 | * lost interrupts following a reset. | |
494 | */ | |
495 | if (engine->class == RENDER_CLASS) { | |
496 | if (INTEL_GEN(engine->i915) >= 6) | |
497 | mask &= ~BIT(0); | |
498 | else | |
499 | mask &= ~I915_USER_INTERRUPT; | |
500 | } | |
501 | ||
502 | intel_engine_set_hwsp_writemask(engine, mask); | |
503 | } | |
504 | ||
505 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 506 | { |
c033666a | 507 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
508 | u32 addr; |
509 | ||
d6acae36 | 510 | addr = lower_32_bits(phys); |
c033666a | 511 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
512 | addr |= (phys >> 28) & 0xf0; |
513 | ||
035dc1e0 DV |
514 | I915_WRITE(HWS_PGA, addr); |
515 | } | |
516 | ||
0ca88ba0 | 517 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 518 | { |
0ca88ba0 | 519 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 520 | |
0ca88ba0 CW |
521 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
522 | return sg_page(obj->mm.pages->sgl); | |
523 | } | |
524 | ||
525 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
526 | { | |
527 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
528 | set_hwstam(engine, ~0u); |
529 | } | |
530 | ||
531 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 532 | { |
c033666a | 533 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 534 | i915_reg_t hwsp; |
af75f269 | 535 | |
060f2322 CW |
536 | /* |
537 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
538 | * the ring registers as of gen7. |
539 | */ | |
cf819eff | 540 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 541 | switch (engine->id) { |
a2d3d265 MT |
542 | /* |
543 | * No more rings exist on Gen7. Default case is only to shut up | |
544 | * gcc switch check warning. | |
545 | */ | |
546 | default: | |
547 | GEM_BUG_ON(engine->id); | |
8a68d464 CW |
548 | /* fallthrough */ |
549 | case RCS0: | |
060f2322 | 550 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 | 551 | break; |
8a68d464 | 552 | case BCS0: |
060f2322 | 553 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 554 | break; |
8a68d464 | 555 | case VCS0: |
060f2322 | 556 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 | 557 | break; |
8a68d464 | 558 | case VECS0: |
060f2322 | 559 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
560 | break; |
561 | } | |
cf819eff | 562 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 563 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 564 | } else { |
060f2322 | 565 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 566 | } |
c5498089 | 567 | |
060f2322 CW |
568 | I915_WRITE(hwsp, offset); |
569 | POSTING_READ(hwsp); | |
570 | } | |
af75f269 | 571 | |
060f2322 CW |
572 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
573 | { | |
574 | struct drm_i915_private *dev_priv = engine->i915; | |
060f2322 CW |
575 | |
576 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
577 | return; | |
578 | ||
579 | /* ring should be idle before issuing a sync flush*/ | |
baba6e57 DCS |
580 | WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); |
581 | ||
582 | ENGINE_WRITE(engine, RING_INSTPM, | |
583 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
584 | INSTPM_SYNC_FLUSH)); | |
585 | if (intel_wait_for_register(engine->uncore, | |
586 | RING_INSTPM(engine->mmio_base), | |
587 | INSTPM_SYNC_FLUSH, 0, | |
060f2322 CW |
588 | 1000)) |
589 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
590 | engine->name); | |
591 | } | |
af75f269 | 592 | |
060f2322 CW |
593 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
594 | { | |
0ca88ba0 | 595 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 596 | set_hwstam(engine, ~0u); |
af75f269 | 597 | |
060f2322 | 598 | flush_cs_tlb(engine); |
af75f269 DL |
599 | } |
600 | ||
0bc40be8 | 601 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 602 | { |
c033666a | 603 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 604 | |
21a2c58a | 605 | if (INTEL_GEN(dev_priv) > 2) { |
baba6e57 DCS |
606 | ENGINE_WRITE(engine, |
607 | RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); | |
608 | if (intel_wait_for_register(engine->uncore, | |
3d808eb1 CW |
609 | RING_MI_MODE(engine->mmio_base), |
610 | MODE_IDLE, | |
611 | MODE_IDLE, | |
612 | 1000)) { | |
0bc40be8 TU |
613 | DRM_ERROR("%s : timed out trying to stop ring\n", |
614 | engine->name); | |
baba6e57 DCS |
615 | |
616 | /* | |
617 | * Sometimes we observe that the idle flag is not | |
9bec9b13 CW |
618 | * set even though the ring is empty. So double |
619 | * check before giving up. | |
620 | */ | |
baba6e57 DCS |
621 | if (ENGINE_READ(engine, RING_HEAD) != |
622 | ENGINE_READ(engine, RING_TAIL)) | |
9bec9b13 | 623 | return false; |
9991ae78 CW |
624 | } |
625 | } | |
b7884eb4 | 626 | |
baba6e57 | 627 | ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); |
11caf551 | 628 | |
baba6e57 DCS |
629 | ENGINE_WRITE(engine, RING_HEAD, 0); |
630 | ENGINE_WRITE(engine, RING_TAIL, 0); | |
8187a2b7 | 631 | |
11caf551 | 632 | /* The ring must be empty before it is disabled */ |
baba6e57 | 633 | ENGINE_WRITE(engine, RING_CTL, 0); |
11caf551 | 634 | |
baba6e57 | 635 | return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; |
9991ae78 | 636 | } |
8187a2b7 | 637 | |
79ffac85 | 638 | static int xcs_resume(struct intel_engine_cs *engine) |
9991ae78 | 639 | { |
c033666a | 640 | struct drm_i915_private *dev_priv = engine->i915; |
75d0a7f3 | 641 | struct intel_ring *ring = engine->legacy.ring; |
9991ae78 CW |
642 | int ret = 0; |
643 | ||
79ffac85 CW |
644 | GEM_TRACE("%s: ring:{HEAD:%04x, TAIL:%04x}\n", |
645 | engine->name, ring->head, ring->tail); | |
646 | ||
baba6e57 | 647 | intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); |
9991ae78 | 648 | |
31483107 | 649 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
0bc40be8 | 650 | if (!stop_ring(engine)) { |
9991ae78 | 651 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
652 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
653 | "ctl %08x head %08x tail %08x start %08x\n", | |
654 | engine->name, | |
baba6e57 DCS |
655 | ENGINE_READ(engine, RING_CTL), |
656 | ENGINE_READ(engine, RING_HEAD), | |
657 | ENGINE_READ(engine, RING_TAIL), | |
658 | ENGINE_READ(engine, RING_START)); | |
8187a2b7 | 659 | |
0bc40be8 | 660 | if (!stop_ring(engine)) { |
6fd0d56e CW |
661 | DRM_ERROR("failed to set %s head to zero " |
662 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 | 663 | engine->name, |
baba6e57 DCS |
664 | ENGINE_READ(engine, RING_CTL), |
665 | ENGINE_READ(engine, RING_HEAD), | |
666 | ENGINE_READ(engine, RING_TAIL), | |
667 | ENGINE_READ(engine, RING_START)); | |
9991ae78 CW |
668 | ret = -EIO; |
669 | goto out; | |
6fd0d56e | 670 | } |
8187a2b7 ZN |
671 | } |
672 | ||
3177659a | 673 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 674 | ring_setup_phys_status_page(engine); |
3177659a | 675 | else |
060f2322 | 676 | ring_setup_status_page(engine); |
9991ae78 | 677 | |
ad07dfcd | 678 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 679 | |
ece4a17d | 680 | /* Enforce ordering by reading HEAD register back */ |
31483107 | 681 | ENGINE_POSTING_READ(engine, RING_HEAD); |
ece4a17d | 682 | |
31483107 CW |
683 | /* |
684 | * Initialize the ring. This must happen _after_ we've cleared the ring | |
0d8957c8 DV |
685 | * registers with the above sequence (the readback of the HEAD registers |
686 | * also enforces ordering), otherwise the hw might lose the new ring | |
31483107 CW |
687 | * register values. |
688 | */ | |
baba6e57 | 689 | ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); |
95468892 | 690 | |
41d37680 CW |
691 | /* Check that the ring offsets point within the ring! */ |
692 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
693 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 694 | intel_ring_update_space(ring); |
b7f21899 CW |
695 | |
696 | /* First wake the ring up to an empty/idle ring */ | |
baba6e57 DCS |
697 | ENGINE_WRITE(engine, RING_HEAD, ring->head); |
698 | ENGINE_WRITE(engine, RING_TAIL, ring->head); | |
699 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
95468892 | 700 | |
baba6e57 | 701 | ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 702 | |
8187a2b7 | 703 | /* If the head is still not zero, the ring is dead */ |
baba6e57 | 704 | if (intel_wait_for_register(engine->uncore, |
97a04e0d | 705 | RING_CTL(engine->mmio_base), |
f42bb651 CW |
706 | RING_VALID, RING_VALID, |
707 | 50)) { | |
e74cfed5 | 708 | DRM_ERROR("%s initialization failed " |
821ed7df | 709 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 | 710 | engine->name, |
baba6e57 DCS |
711 | ENGINE_READ(engine, RING_CTL), |
712 | ENGINE_READ(engine, RING_CTL) & RING_VALID, | |
713 | ENGINE_READ(engine, RING_HEAD), ring->head, | |
714 | ENGINE_READ(engine, RING_TAIL), ring->tail, | |
715 | ENGINE_READ(engine, RING_START), | |
bde13ebd | 716 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
717 | ret = -EIO; |
718 | goto out; | |
8187a2b7 ZN |
719 | } |
720 | ||
7836cd02 | 721 | if (INTEL_GEN(dev_priv) > 2) |
baba6e57 DCS |
722 | ENGINE_WRITE(engine, |
723 | RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); | |
7836cd02 | 724 | |
b7f21899 CW |
725 | /* Now awake, let it get started */ |
726 | if (ring->tail != ring->head) { | |
baba6e57 DCS |
727 | ENGINE_WRITE(engine, RING_TAIL, ring->tail); |
728 | ENGINE_POSTING_READ(engine, RING_TAIL); | |
b7f21899 CW |
729 | } |
730 | ||
d6fee0de | 731 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 732 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 733 | out: |
baba6e57 | 734 | intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); |
b7884eb4 DV |
735 | |
736 | return ret; | |
8187a2b7 ZN |
737 | } |
738 | ||
eb8d0f5a | 739 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 740 | { |
c30d5dc6 CW |
741 | struct intel_uncore *uncore = engine->uncore; |
742 | const u32 base = engine->mmio_base; | |
743 | ||
744 | /* | |
745 | * We stop engines, otherwise we might get failed reset and a | |
746 | * dead gpu (on elk). Also as modern gpu as kbl can suffer | |
747 | * from system hang if batchbuffer is progressing when | |
748 | * the reset is issued, regardless of READY_TO_RESET ack. | |
749 | * Thus assume it is best to stop engines on all gens | |
750 | * where we have a gpu reset. | |
751 | * | |
752 | * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES) | |
753 | * | |
754 | * WaMediaResetMainRingCleanup:ctg,elk (presumably) | |
755 | * | |
756 | * FIXME: Wa for more modern gens needs to be validated | |
757 | */ | |
758 | GEM_TRACE("%s\n", engine->name); | |
759 | ||
760 | if (intel_engine_stop_cs(engine)) | |
761 | GEM_TRACE("%s: timed out on STOP_RING\n", engine->name); | |
762 | ||
763 | intel_uncore_write_fw(uncore, | |
764 | RING_HEAD(base), | |
765 | intel_uncore_read_fw(uncore, RING_TAIL(base))); | |
766 | intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */ | |
767 | ||
768 | intel_uncore_write_fw(uncore, RING_HEAD(base), 0); | |
769 | intel_uncore_write_fw(uncore, RING_TAIL(base), 0); | |
770 | intel_uncore_posting_read_fw(uncore, RING_TAIL(base)); | |
771 | ||
772 | /* The ring must be empty before it is disabled */ | |
773 | intel_uncore_write_fw(uncore, RING_CTL(base), 0); | |
774 | ||
775 | /* Check acts as a post */ | |
776 | if (intel_uncore_read_fw(uncore, RING_HEAD(base))) | |
777 | GEM_TRACE("%s: ring head [%x] not parked\n", | |
778 | engine->name, | |
779 | intel_uncore_read_fw(uncore, RING_HEAD(base))); | |
5adfb772 CW |
780 | } |
781 | ||
eb8d0f5a | 782 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 783 | { |
eb8d0f5a CW |
784 | struct i915_request *pos, *rq; |
785 | unsigned long flags; | |
b3ee09a4 | 786 | u32 head; |
5adfb772 | 787 | |
eb8d0f5a | 788 | rq = NULL; |
422d7df4 CW |
789 | spin_lock_irqsave(&engine->active.lock, flags); |
790 | list_for_each_entry(pos, &engine->active.requests, sched.link) { | |
5013eb8c | 791 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
792 | rq = pos; |
793 | break; | |
794 | } | |
b3ee09a4 | 795 | } |
67e64564 CW |
796 | |
797 | /* | |
eb8d0f5a | 798 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 799 | * |
eb8d0f5a CW |
800 | * Users of client default contexts do not rely on logical |
801 | * state preserved between batches so it is safe to execute | |
802 | * queued requests following the hang. Non default contexts | |
803 | * rely on preserved state, so skipping a batch loses the | |
804 | * evolution of the state and it needs to be considered corrupted. | |
805 | * Executing more queued batches on top of corrupted state is | |
806 | * risky. But we take the risk by trying to advance through | |
807 | * the queued requests in order to make the client behaviour | |
808 | * more predictable around resets, by not throwing away random | |
809 | * amount of batches it has prepared for execution. Sophisticated | |
810 | * clients can use gem_reset_stats_ioctl and dma fence status | |
811 | * (exported via sync_file info ioctl on explicit fences) to observe | |
812 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 813 | * |
eb8d0f5a CW |
814 | * The context ban, and ultimately the client ban, mechanism are safety |
815 | * valves if client submission ends up resulting in nothing more than | |
816 | * subsequent hangs. | |
c0dcb203 | 817 | */ |
eb8d0f5a | 818 | |
b3ee09a4 | 819 | if (rq) { |
eb8d0f5a CW |
820 | /* |
821 | * Try to restore the logical GPU state to match the | |
822 | * continuation of the request queue. If we skip the | |
823 | * context/PD restore, then the next request may try to execute | |
824 | * assuming that its context is valid and loaded on the GPU and | |
825 | * so may try to access invalid memory, prompting repeated GPU | |
826 | * hangs. | |
827 | * | |
828 | * If the request was guilty, we still restore the logical | |
829 | * state in case the next request requires it (e.g. the | |
830 | * aliasing ppgtt), but skip over the hung batch. | |
831 | * | |
832 | * If the request was innocent, we try to replay the request | |
833 | * with the restored context. | |
834 | */ | |
cb823ed9 | 835 | __i915_request_reset(rq, stalled); |
eb8d0f5a | 836 | |
75d0a7f3 | 837 | GEM_BUG_ON(rq->ring != engine->legacy.ring); |
eb8d0f5a CW |
838 | head = rq->head; |
839 | } else { | |
75d0a7f3 | 840 | head = engine->legacy.ring->tail; |
c0dcb203 | 841 | } |
75d0a7f3 | 842 | engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); |
eb8d0f5a | 843 | |
422d7df4 | 844 | spin_unlock_irqrestore(&engine->active.lock, flags); |
821ed7df CW |
845 | } |
846 | ||
5adfb772 CW |
847 | static void reset_finish(struct intel_engine_cs *engine) |
848 | { | |
849 | } | |
850 | ||
79ffac85 | 851 | static int rcs_resume(struct intel_engine_cs *engine) |
8187a2b7 | 852 | { |
c033666a | 853 | struct drm_i915_private *dev_priv = engine->i915; |
a69ffdbf | 854 | |
9ce9bdb0 CW |
855 | /* |
856 | * Disable CONSTANT_BUFFER before it is loaded from the context | |
857 | * image. For as it is loaded, it is executed and the stored | |
858 | * address may no longer be valid, leading to a GPU hang. | |
859 | * | |
860 | * This imposes the requirement that userspace reload their | |
861 | * CONSTANT_BUFFER on every batch, fortunately a requirement | |
862 | * they are already accustomed to from before contexts were | |
863 | * enabled. | |
864 | */ | |
865 | if (IS_GEN(dev_priv, 4)) | |
866 | I915_WRITE(ECOSKPD, | |
867 | _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); | |
868 | ||
61a563a2 | 869 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 870 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 871 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
872 | |
873 | /* We need to disable the AsyncFlip performance optimisations in order | |
874 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
875 | * programmed to '1' on all products. | |
8693a824 | 876 | * |
2441f877 | 877 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 878 | */ |
00690008 | 879 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
880 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
881 | ||
f05bb0c7 | 882 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 883 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 884 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 885 | I915_WRITE(GFX_MODE, |
aa83e30d | 886 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 887 | |
01fa0302 | 888 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 889 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 890 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 891 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 892 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 893 | |
cf819eff | 894 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
895 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
896 | * "If this bit is set, STCunit will have LRA as replacement | |
897 | * policy. [...] This bit must be reset. LRA replacement | |
898 | * policy is not supported." | |
899 | */ | |
900 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 901 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
902 | } |
903 | ||
00690008 | 904 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 905 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 906 | |
79ffac85 | 907 | return xcs_resume(engine); |
8187a2b7 ZN |
908 | } |
909 | ||
27a5f61b CW |
910 | static void cancel_requests(struct intel_engine_cs *engine) |
911 | { | |
e61e0f51 | 912 | struct i915_request *request; |
27a5f61b CW |
913 | unsigned long flags; |
914 | ||
422d7df4 | 915 | spin_lock_irqsave(&engine->active.lock, flags); |
27a5f61b CW |
916 | |
917 | /* Mark all submitted requests as skipped. */ | |
422d7df4 | 918 | list_for_each_entry(request, &engine->active.requests, sched.link) { |
5013eb8c CW |
919 | if (!i915_request_signaled(request)) |
920 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 921 | |
5013eb8c | 922 | i915_request_mark_complete(request); |
27a5f61b | 923 | } |
3800960a | 924 | |
27a5f61b CW |
925 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
926 | ||
422d7df4 | 927 | spin_unlock_irqrestore(&engine->active.lock, flags); |
27a5f61b CW |
928 | } |
929 | ||
e61e0f51 | 930 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d | 931 | { |
e61e0f51 | 932 | i915_request_submit(request); |
d55ac5bf | 933 | |
baba6e57 DCS |
934 | ENGINE_WRITE(request->engine, RING_TAIL, |
935 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
936 | } |
937 | ||
e1a73a54 | 938 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 939 | { |
5013eb8c CW |
940 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
941 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
942 | ||
caa5915b CW |
943 | *cs++ = MI_FLUSH; |
944 | ||
5013eb8c CW |
945 | *cs++ = MI_STORE_DWORD_INDEX; |
946 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
947 | *cs++ = rq->fence.seqno; | |
948 | ||
73dec95e | 949 | *cs++ = MI_USER_INTERRUPT; |
519a0194 | 950 | *cs++ = MI_NOOP; |
1ec14ad3 | 951 | |
e61e0f51 CW |
952 | rq->tail = intel_ring_offset(rq, cs); |
953 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
954 | |
955 | return cs; | |
1ec14ad3 | 956 | } |
98f29e8d | 957 | |
835051d3 | 958 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 959 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 960 | { |
835051d3 CW |
961 | int i; |
962 | ||
5013eb8c CW |
963 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
964 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
965 | ||
835051d3 CW |
966 | *cs++ = MI_FLUSH; |
967 | ||
968 | BUILD_BUG_ON(GEN5_WA_STORES < 1); | |
969 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
970 | *cs++ = MI_STORE_DWORD_INDEX; | |
b300fde8 CW |
971 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
972 | *cs++ = rq->fence.seqno; | |
835051d3 CW |
973 | } |
974 | ||
975 | *cs++ = MI_USER_INTERRUPT; | |
976 | ||
977 | rq->tail = intel_ring_offset(rq, cs); | |
978 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
979 | |
980 | return cs; | |
c6df541c | 981 | } |
835051d3 | 982 | #undef GEN5_WA_STORES |
c6df541c | 983 | |
31bb59cc CW |
984 | static void |
985 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 986 | { |
cf1c97dc | 987 | gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); |
e48d8634 DV |
988 | } |
989 | ||
990 | static void | |
31bb59cc | 991 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 992 | { |
cf1c97dc | 993 | gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); |
e48d8634 DV |
994 | } |
995 | ||
31bb59cc CW |
996 | static void |
997 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 998 | { |
baba6e57 | 999 | engine->i915->irq_mask &= ~engine->irq_enable_mask; |
9d9523d8 PZ |
1000 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
1001 | intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); | |
62fdfeaf EA |
1002 | } |
1003 | ||
8187a2b7 | 1004 | static void |
31bb59cc | 1005 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1006 | { |
baba6e57 | 1007 | engine->i915->irq_mask |= engine->irq_enable_mask; |
9d9523d8 | 1008 | intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); |
62fdfeaf EA |
1009 | } |
1010 | ||
31bb59cc CW |
1011 | static void |
1012 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1013 | { |
e44d62d1 | 1014 | struct drm_i915_private *i915 = engine->i915; |
c2798b19 | 1015 | |
e44d62d1 TU |
1016 | i915->irq_mask &= ~engine->irq_enable_mask; |
1017 | intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); | |
1018 | ENGINE_POSTING_READ16(engine, RING_IMR); | |
c2798b19 CW |
1019 | } |
1020 | ||
1021 | static void | |
31bb59cc | 1022 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1023 | { |
4f5fd91f | 1024 | struct drm_i915_private *i915 = engine->i915; |
c2798b19 | 1025 | |
4f5fd91f TU |
1026 | i915->irq_mask |= engine->irq_enable_mask; |
1027 | intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); | |
c2798b19 CW |
1028 | } |
1029 | ||
b72f3acb | 1030 | static int |
e61e0f51 | 1031 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 1032 | { |
73dec95e | 1033 | u32 *cs; |
b72f3acb | 1034 | |
e61e0f51 | 1035 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1036 | if (IS_ERR(cs)) |
1037 | return PTR_ERR(cs); | |
b72f3acb | 1038 | |
73dec95e TU |
1039 | *cs++ = MI_FLUSH; |
1040 | *cs++ = MI_NOOP; | |
e61e0f51 | 1041 | intel_ring_advance(rq, cs); |
b72f3acb | 1042 | return 0; |
d1b851fc ZN |
1043 | } |
1044 | ||
31bb59cc CW |
1045 | static void |
1046 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1047 | { |
baba6e57 DCS |
1048 | ENGINE_WRITE(engine, RING_IMR, |
1049 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
476af9c2 CW |
1050 | |
1051 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1052 | ENGINE_POSTING_READ(engine, RING_IMR); |
476af9c2 | 1053 | |
cf1c97dc | 1054 | gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); |
0f46832f CW |
1055 | } |
1056 | ||
1057 | static void | |
31bb59cc | 1058 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1059 | { |
baba6e57 | 1060 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); |
cf1c97dc | 1061 | gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); |
d1b851fc ZN |
1062 | } |
1063 | ||
31bb59cc CW |
1064 | static void |
1065 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1066 | { |
baba6e57 | 1067 | ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1068 | |
1069 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
baba6e57 | 1070 | ENGINE_POSTING_READ(engine, RING_IMR); |
e4fc69f2 | 1071 | |
d762043f | 1072 | gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); |
a19d2933 BW |
1073 | } |
1074 | ||
1075 | static void | |
31bb59cc | 1076 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1077 | { |
baba6e57 | 1078 | ENGINE_WRITE(engine, RING_IMR, ~0); |
d762043f | 1079 | gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); |
a19d2933 BW |
1080 | } |
1081 | ||
d1b851fc | 1082 | static int |
e61e0f51 | 1083 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1084 | u64 offset, u32 length, |
1085 | unsigned int dispatch_flags) | |
d1b851fc | 1086 | { |
73dec95e | 1087 | u32 *cs; |
78501eac | 1088 | |
e61e0f51 | 1089 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1090 | if (IS_ERR(cs)) |
1091 | return PTR_ERR(cs); | |
e1f99ce6 | 1092 | |
73dec95e TU |
1093 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1094 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1095 | *cs++ = offset; | |
e61e0f51 | 1096 | intel_ring_advance(rq, cs); |
78501eac | 1097 | |
d1b851fc ZN |
1098 | return 0; |
1099 | } | |
1100 | ||
b45305fc | 1101 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1102 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1103 | #define I830_TLB_ENTRIES (2) |
1104 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1105 | static int |
e61e0f51 | 1106 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1107 | u64 offset, u32 len, |
1108 | unsigned int dispatch_flags) | |
62fdfeaf | 1109 | { |
46c5847e LL |
1110 | u32 *cs, cs_offset = |
1111 | intel_gt_scratch_offset(rq->engine->gt, | |
1112 | INTEL_GT_SCRATCH_FIELD_DEFAULT); | |
51797499 | 1113 | |
db56f974 | 1114 | GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); |
62fdfeaf | 1115 | |
e61e0f51 | 1116 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1117 | if (IS_ERR(cs)) |
1118 | return PTR_ERR(cs); | |
62fdfeaf | 1119 | |
c4d69da1 | 1120 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1121 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1122 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1123 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1124 | *cs++ = cs_offset; | |
1125 | *cs++ = 0xdeadbeef; | |
1126 | *cs++ = MI_NOOP; | |
e61e0f51 | 1127 | intel_ring_advance(rq, cs); |
b45305fc | 1128 | |
8e004efc | 1129 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1130 | if (len > I830_BATCH_LIMIT) |
1131 | return -ENOSPC; | |
1132 | ||
e61e0f51 | 1133 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1134 | if (IS_ERR(cs)) |
1135 | return PTR_ERR(cs); | |
c4d69da1 CW |
1136 | |
1137 | /* Blit the batch (which has now all relocs applied) to the | |
1138 | * stable batch scratch bo area (so that the CS never | |
1139 | * stumbles over its tlb invalidation bug) ... | |
1140 | */ | |
05f219d7 | 1141 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); |
73dec95e TU |
1142 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; |
1143 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1144 | *cs++ = cs_offset; | |
1145 | *cs++ = 4096; | |
1146 | *cs++ = offset; | |
1147 | ||
1148 | *cs++ = MI_FLUSH; | |
1149 | *cs++ = MI_NOOP; | |
e61e0f51 | 1150 | intel_ring_advance(rq, cs); |
b45305fc DV |
1151 | |
1152 | /* ... and execute it. */ | |
c4d69da1 | 1153 | offset = cs_offset; |
b45305fc | 1154 | } |
e1f99ce6 | 1155 | |
e61e0f51 | 1156 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1157 | if (IS_ERR(cs)) |
1158 | return PTR_ERR(cs); | |
c4d69da1 | 1159 | |
73dec95e TU |
1160 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1161 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1162 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1163 | intel_ring_advance(rq, cs); |
c4d69da1 | 1164 | |
fb3256da DV |
1165 | return 0; |
1166 | } | |
1167 | ||
1168 | static int | |
e61e0f51 | 1169 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1170 | u64 offset, u32 len, |
1171 | unsigned int dispatch_flags) | |
fb3256da | 1172 | { |
73dec95e | 1173 | u32 *cs; |
fb3256da | 1174 | |
e61e0f51 | 1175 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1176 | if (IS_ERR(cs)) |
1177 | return PTR_ERR(cs); | |
fb3256da | 1178 | |
73dec95e TU |
1179 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1180 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1181 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1182 | intel_ring_advance(rq, cs); |
62fdfeaf | 1183 | |
62fdfeaf EA |
1184 | return 0; |
1185 | } | |
1186 | ||
5503cb0d | 1187 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1188 | { |
57e88531 | 1189 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1190 | unsigned int flags; |
8305216f | 1191 | void *addr; |
7ba717cf TD |
1192 | int ret; |
1193 | ||
09c5ab38 CW |
1194 | if (atomic_fetch_inc(&ring->pin_count)) |
1195 | return 0; | |
7ba717cf | 1196 | |
d3ef1af6 | 1197 | flags = PIN_GLOBAL; |
496bcce3 JB |
1198 | |
1199 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1200 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1201 | ||
9d80841e | 1202 | if (vma->obj->stolen) |
57e88531 | 1203 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1204 | else |
1205 | flags |= PIN_HIGH; | |
def0c5f6 | 1206 | |
7a859c65 | 1207 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1208 | if (unlikely(ret)) |
75d0a7f3 | 1209 | goto err_unpin; |
def0c5f6 | 1210 | |
9d80841e | 1211 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1212 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1213 | else | |
09c5ab38 CW |
1214 | addr = i915_gem_object_pin_map(vma->obj, |
1215 | i915_coherent_map_type(vma->vm->i915)); | |
5013eb8c CW |
1216 | if (IS_ERR(addr)) { |
1217 | ret = PTR_ERR(addr); | |
09c5ab38 | 1218 | goto err_ring; |
5013eb8c | 1219 | } |
7ba717cf | 1220 | |
1aff1903 | 1221 | i915_vma_make_unshrinkable(vma); |
3d574a6b | 1222 | |
a5c6d35c CW |
1223 | /* Discard any unused bytes beyond that submitted to hw. */ |
1224 | intel_ring_reset(ring, ring->emit); | |
09c5ab38 | 1225 | |
a5c6d35c | 1226 | ring->vaddr = addr; |
7ba717cf | 1227 | return 0; |
d2cad535 | 1228 | |
09c5ab38 | 1229 | err_ring: |
57e88531 | 1230 | i915_vma_unpin(vma); |
09c5ab38 CW |
1231 | err_unpin: |
1232 | atomic_dec(&ring->pin_count); | |
5013eb8c | 1233 | return ret; |
7ba717cf TD |
1234 | } |
1235 | ||
e6ba9992 CW |
1236 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1237 | { | |
6a736ebf | 1238 | tail = intel_ring_wrap(ring, tail); |
e6ba9992 CW |
1239 | ring->tail = tail; |
1240 | ring->head = tail; | |
1241 | ring->emit = tail; | |
1242 | intel_ring_update_space(ring); | |
1243 | } | |
1244 | ||
aad29fbb CW |
1245 | void intel_ring_unpin(struct intel_ring *ring) |
1246 | { | |
1aff1903 CW |
1247 | struct i915_vma *vma = ring->vma; |
1248 | ||
09c5ab38 CW |
1249 | if (!atomic_dec_and_test(&ring->pin_count)) |
1250 | return; | |
aad29fbb | 1251 | |
1aff1903 CW |
1252 | i915_vma_unset_ggtt_write(vma); |
1253 | if (i915_vma_is_map_and_fenceable(vma)) | |
1254 | i915_vma_unpin_iomap(vma); | |
57e88531 | 1255 | else |
1aff1903 | 1256 | i915_gem_object_unpin_map(vma->obj); |
09c5ab38 | 1257 | |
1aff1903 | 1258 | i915_vma_make_purgeable(vma); |
a5c6d35c | 1259 | i915_vma_unpin(vma); |
2919d291 OM |
1260 | } |
1261 | ||
db45fb5b | 1262 | static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) |
62fdfeaf | 1263 | { |
db45fb5b TU |
1264 | struct i915_address_space *vm = &ggtt->vm; |
1265 | struct drm_i915_private *i915 = vm->i915; | |
05394f39 | 1266 | struct drm_i915_gem_object *obj; |
57e88531 | 1267 | struct i915_vma *vma; |
62fdfeaf | 1268 | |
db45fb5b | 1269 | obj = i915_gem_object_create_stolen(i915, size); |
c58b735f | 1270 | if (!obj) |
db45fb5b | 1271 | obj = i915_gem_object_create_internal(i915, size); |
57e88531 CW |
1272 | if (IS_ERR(obj)) |
1273 | return ERR_CAST(obj); | |
8187a2b7 | 1274 | |
250f8c81 JB |
1275 | /* |
1276 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1277 | * if supported by the platform's GGTT. | |
1278 | */ | |
1279 | if (vm->has_read_only) | |
3e977ac6 | 1280 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1281 | |
250f8c81 | 1282 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1283 | if (IS_ERR(vma)) |
1284 | goto err; | |
1285 | ||
1286 | return vma; | |
e3efda49 | 1287 | |
57e88531 CW |
1288 | err: |
1289 | i915_gem_object_put(obj); | |
1290 | return vma; | |
e3efda49 CW |
1291 | } |
1292 | ||
7e37f889 | 1293 | struct intel_ring * |
75d0a7f3 | 1294 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) |
01101fa7 | 1295 | { |
db45fb5b | 1296 | struct drm_i915_private *i915 = engine->i915; |
7e37f889 | 1297 | struct intel_ring *ring; |
57e88531 | 1298 | struct i915_vma *vma; |
01101fa7 | 1299 | |
8f942018 | 1300 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1301 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1302 | |
01101fa7 | 1303 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1304 | if (!ring) |
01101fa7 CW |
1305 | return ERR_PTR(-ENOMEM); |
1306 | ||
65baf0ef | 1307 | kref_init(&ring->ref); |
01101fa7 | 1308 | ring->size = size; |
526ac95b CW |
1309 | ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(size); |
1310 | ||
01101fa7 CW |
1311 | /* Workaround an erratum on the i830 which causes a hang if |
1312 | * the TAIL pointer points to within the last 2 cachelines | |
1313 | * of the buffer. | |
1314 | */ | |
1315 | ring->effective_size = size; | |
db45fb5b | 1316 | if (IS_I830(i915) || IS_I845G(i915)) |
01101fa7 CW |
1317 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1318 | ||
01101fa7 CW |
1319 | intel_ring_update_space(ring); |
1320 | ||
db45fb5b | 1321 | vma = create_ring_vma(engine->gt->ggtt, size); |
57e88531 | 1322 | if (IS_ERR(vma)) { |
01101fa7 | 1323 | kfree(ring); |
57e88531 | 1324 | return ERR_CAST(vma); |
01101fa7 | 1325 | } |
57e88531 | 1326 | ring->vma = vma; |
01101fa7 CW |
1327 | |
1328 | return ring; | |
1329 | } | |
1330 | ||
65baf0ef | 1331 | void intel_ring_free(struct kref *ref) |
01101fa7 | 1332 | { |
65baf0ef | 1333 | struct intel_ring *ring = container_of(ref, typeof(*ring), ref); |
f8a7fde4 CW |
1334 | |
1335 | i915_vma_close(ring->vma); | |
c017cf6b | 1336 | i915_vma_put(ring->vma); |
f8a7fde4 | 1337 | |
01101fa7 CW |
1338 | kfree(ring); |
1339 | } | |
1340 | ||
c4d52feb CW |
1341 | static void __ring_context_fini(struct intel_context *ce) |
1342 | { | |
c4d52feb CW |
1343 | i915_gem_object_put(ce->state->obj); |
1344 | } | |
1345 | ||
4c5896dc | 1346 | static void ring_context_destroy(struct kref *ref) |
1fc44d9b | 1347 | { |
4c5896dc CW |
1348 | struct intel_context *ce = container_of(ref, typeof(*ce), ref); |
1349 | ||
08819549 | 1350 | GEM_BUG_ON(intel_context_is_pinned(ce)); |
1fc44d9b | 1351 | |
c4d52feb CW |
1352 | if (ce->state) |
1353 | __ring_context_fini(ce); | |
efe79d48 | 1354 | |
df8cf31e | 1355 | intel_context_fini(ce); |
c4d52feb | 1356 | intel_context_free(ce); |
1fc44d9b CW |
1357 | } |
1358 | ||
c082afac CW |
1359 | static struct i915_address_space *vm_alias(struct intel_context *ce) |
1360 | { | |
1361 | struct i915_address_space *vm; | |
1362 | ||
f5d974f9 CW |
1363 | vm = ce->vm; |
1364 | if (i915_is_ggtt(vm)) | |
1365 | vm = &i915_vm_to_ggtt(vm)->alias->vm; | |
c082afac CW |
1366 | |
1367 | return vm; | |
1368 | } | |
1369 | ||
1370 | static int __context_pin_ppgtt(struct intel_context *ce) | |
a2bbf714 | 1371 | { |
e568ac38 | 1372 | struct i915_address_space *vm; |
a2bbf714 CW |
1373 | int err = 0; |
1374 | ||
c082afac | 1375 | vm = vm_alias(ce); |
e568ac38 CW |
1376 | if (vm) |
1377 | err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); | |
a2bbf714 CW |
1378 | |
1379 | return err; | |
1380 | } | |
1381 | ||
c082afac | 1382 | static void __context_unpin_ppgtt(struct intel_context *ce) |
a2bbf714 | 1383 | { |
e568ac38 | 1384 | struct i915_address_space *vm; |
a2bbf714 | 1385 | |
c082afac | 1386 | vm = vm_alias(ce); |
e568ac38 CW |
1387 | if (vm) |
1388 | gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); | |
a2bbf714 CW |
1389 | } |
1390 | ||
4dc84b77 | 1391 | static void ring_context_unpin(struct intel_context *ce) |
d901e8e6 | 1392 | { |
c082afac | 1393 | __context_unpin_ppgtt(ce); |
e8a9c58f CW |
1394 | } |
1395 | ||
3204c343 CW |
1396 | static struct i915_vma * |
1397 | alloc_context_vma(struct intel_engine_cs *engine) | |
1398 | { | |
1399 | struct drm_i915_private *i915 = engine->i915; | |
1400 | struct drm_i915_gem_object *obj; | |
1401 | struct i915_vma *vma; | |
d2b4b979 | 1402 | int err; |
3204c343 | 1403 | |
8475355f | 1404 | obj = i915_gem_object_create_shmem(i915, engine->context_size); |
3204c343 CW |
1405 | if (IS_ERR(obj)) |
1406 | return ERR_CAST(obj); | |
1407 | ||
a679f58d CW |
1408 | /* |
1409 | * Try to make the context utilize L3 as well as LLC. | |
1410 | * | |
1411 | * On VLV we don't have L3 controls in the PTEs so we | |
1412 | * shouldn't touch the cache level, especially as that | |
1413 | * would make the object snooped which might have a | |
1414 | * negative performance impact. | |
1415 | * | |
1416 | * Snooping is required on non-llc platforms in execlist | |
1417 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1418 | * get snooping anyway regardless of cache_level. | |
1419 | * | |
1420 | * This is only applicable for Ivy Bridge devices since | |
1421 | * later platforms don't have L3 control bits in the PTE. | |
1422 | */ | |
1423 | if (IS_IVYBRIDGE(i915)) | |
1424 | i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); | |
1425 | ||
d2b4b979 CW |
1426 | if (engine->default_state) { |
1427 | void *defaults, *vaddr; | |
1428 | ||
1429 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1430 | if (IS_ERR(vaddr)) { | |
1431 | err = PTR_ERR(vaddr); | |
1432 | goto err_obj; | |
1433 | } | |
1434 | ||
1435 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1436 | I915_MAP_WB); | |
1437 | if (IS_ERR(defaults)) { | |
1438 | err = PTR_ERR(defaults); | |
1439 | goto err_map; | |
1440 | } | |
1441 | ||
1442 | memcpy(vaddr, defaults, engine->context_size); | |
d2b4b979 | 1443 | i915_gem_object_unpin_map(engine->default_state); |
d2b4b979 | 1444 | |
a679f58d CW |
1445 | i915_gem_object_flush_map(obj); |
1446 | i915_gem_object_unpin_map(obj); | |
3204c343 CW |
1447 | } |
1448 | ||
ba4134a4 | 1449 | vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); |
d2b4b979 CW |
1450 | if (IS_ERR(vma)) { |
1451 | err = PTR_ERR(vma); | |
1452 | goto err_obj; | |
1453 | } | |
3204c343 CW |
1454 | |
1455 | return vma; | |
d2b4b979 CW |
1456 | |
1457 | err_map: | |
1458 | i915_gem_object_unpin_map(obj); | |
1459 | err_obj: | |
1460 | i915_gem_object_put(obj); | |
1461 | return ERR_PTR(err); | |
3204c343 CW |
1462 | } |
1463 | ||
4c60b1aa | 1464 | static int ring_context_alloc(struct intel_context *ce) |
0cb26a8e | 1465 | { |
95f697eb | 1466 | struct intel_engine_cs *engine = ce->engine; |
0cb26a8e | 1467 | |
7e3d9a59 | 1468 | /* One ringbuffer to rule them all */ |
75d0a7f3 CW |
1469 | GEM_BUG_ON(!engine->legacy.ring); |
1470 | ce->ring = engine->legacy.ring; | |
1471 | ce->timeline = intel_timeline_get(engine->legacy.timeline); | |
7e3d9a59 | 1472 | |
4c60b1aa CW |
1473 | GEM_BUG_ON(ce->state); |
1474 | if (engine->context_size) { | |
3204c343 CW |
1475 | struct i915_vma *vma; |
1476 | ||
1477 | vma = alloc_context_vma(engine); | |
95f697eb CW |
1478 | if (IS_ERR(vma)) |
1479 | return PTR_ERR(vma); | |
3204c343 CW |
1480 | |
1481 | ce->state = vma; | |
1482 | } | |
1483 | ||
4c60b1aa CW |
1484 | return 0; |
1485 | } | |
1486 | ||
1487 | static int ring_context_pin(struct intel_context *ce) | |
1488 | { | |
1489 | int err; | |
1490 | ||
12c255b5 | 1491 | err = intel_context_active_acquire(ce); |
d901e8e6 | 1492 | if (err) |
95f697eb | 1493 | return err; |
0cb26a8e | 1494 | |
c082afac | 1495 | err = __context_pin_ppgtt(ce); |
a2bbf714 | 1496 | if (err) |
ce476c80 | 1497 | goto err_active; |
a2bbf714 | 1498 | |
95f697eb | 1499 | return 0; |
266a240b | 1500 | |
ce476c80 CW |
1501 | err_active: |
1502 | intel_context_active_release(ce); | |
95f697eb | 1503 | return err; |
0cb26a8e CW |
1504 | } |
1505 | ||
9726920b CW |
1506 | static void ring_context_reset(struct intel_context *ce) |
1507 | { | |
1508 | intel_ring_reset(ce->ring, 0); | |
1509 | } | |
1510 | ||
4dc84b77 | 1511 | static const struct intel_context_ops ring_context_ops = { |
4c60b1aa CW |
1512 | .alloc = ring_context_alloc, |
1513 | ||
95f697eb | 1514 | .pin = ring_context_pin, |
4dc84b77 | 1515 | .unpin = ring_context_unpin, |
9726920b | 1516 | |
6eee33e8 CW |
1517 | .enter = intel_context_enter_engine, |
1518 | .exit = intel_context_exit_engine, | |
1519 | ||
9726920b | 1520 | .reset = ring_context_reset, |
4dc84b77 CW |
1521 | .destroy = ring_context_destroy, |
1522 | }; | |
1523 | ||
ab53497b | 1524 | static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt) |
b3ee09a4 CW |
1525 | { |
1526 | const struct intel_engine_cs * const engine = rq->engine; | |
1527 | u32 *cs; | |
1528 | ||
1529 | cs = intel_ring_begin(rq, 6); | |
1530 | if (IS_ERR(cs)) | |
1531 | return PTR_ERR(cs); | |
1532 | ||
1533 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1534 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); |
b3ee09a4 CW |
1535 | *cs++ = PP_DIR_DCLV_2G; |
1536 | ||
1537 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
baba6e57 | 1538 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
57a7e305 | 1539 | *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; |
b3ee09a4 CW |
1540 | |
1541 | intel_ring_advance(rq, cs); | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
d9d117e4 CW |
1546 | static int flush_pd_dir(struct i915_request *rq) |
1547 | { | |
1548 | const struct intel_engine_cs * const engine = rq->engine; | |
1549 | u32 *cs; | |
1550 | ||
1551 | cs = intel_ring_begin(rq, 4); | |
1552 | if (IS_ERR(cs)) | |
1553 | return PTR_ERR(cs); | |
1554 | ||
1555 | /* Stall until the page table load is complete */ | |
1556 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
baba6e57 | 1557 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); |
46c5847e LL |
1558 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
1559 | INTEL_GT_SCRATCH_FIELD_DEFAULT); | |
d9d117e4 CW |
1560 | *cs++ = MI_NOOP; |
1561 | ||
1562 | intel_ring_advance(rq, cs); | |
1563 | return 0; | |
1564 | } | |
1565 | ||
e61e0f51 | 1566 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1567 | { |
1568 | struct drm_i915_private *i915 = rq->i915; | |
1569 | struct intel_engine_cs *engine = rq->engine; | |
1570 | enum intel_engine_id id; | |
8a68d464 | 1571 | const int num_engines = |
c73cdbf8 | 1572 | IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; |
1fc719d1 | 1573 | bool force_restore = false; |
8911a31c CW |
1574 | int len; |
1575 | u32 *cs; | |
1576 | ||
1577 | flags |= MI_MM_SPACE_GTT; | |
1578 | if (IS_HASWELL(i915)) | |
1579 | /* These flags are for resource streamer on HSW+ */ | |
1580 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1581 | else | |
1215d28e | 1582 | /* We need to save the extended state for powersaving modes */ |
8911a31c CW |
1583 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; |
1584 | ||
1585 | len = 4; | |
cf819eff | 1586 | if (IS_GEN(i915, 7)) |
8a68d464 | 1587 | len += 2 + (num_engines ? 4 * num_engines + 6 : 0); |
1215d28e CW |
1588 | else if (IS_GEN(i915, 5)) |
1589 | len += 2; | |
1fc719d1 CW |
1590 | if (flags & MI_FORCE_RESTORE) { |
1591 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1592 | flags &= ~MI_FORCE_RESTORE; | |
1593 | force_restore = true; | |
1594 | len += 2; | |
1595 | } | |
8911a31c CW |
1596 | |
1597 | cs = intel_ring_begin(rq, len); | |
1598 | if (IS_ERR(cs)) | |
1599 | return PTR_ERR(cs); | |
1600 | ||
1601 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1602 | if (IS_GEN(i915, 7)) { |
8911a31c | 1603 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
8a68d464 | 1604 | if (num_engines) { |
8911a31c CW |
1605 | struct intel_engine_cs *signaller; |
1606 | ||
8a68d464 | 1607 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1608 | for_each_engine(signaller, i915, id) { |
1609 | if (signaller == engine) | |
1610 | continue; | |
1611 | ||
1612 | *cs++ = i915_mmio_reg_offset( | |
1613 | RING_PSMI_CTL(signaller->mmio_base)); | |
1614 | *cs++ = _MASKED_BIT_ENABLE( | |
1615 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1616 | } | |
1617 | } | |
1215d28e CW |
1618 | } else if (IS_GEN(i915, 5)) { |
1619 | /* | |
1620 | * This w/a is only listed for pre-production ilk a/b steppings, | |
1621 | * but is also mentioned for programming the powerctx. To be | |
1622 | * safe, just apply the workaround; we do not use SyncFlush so | |
1623 | * this should never take effect and so be a no-op! | |
1624 | */ | |
1625 | *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; | |
8911a31c CW |
1626 | } |
1627 | ||
1fc719d1 CW |
1628 | if (force_restore) { |
1629 | /* | |
1630 | * The HW doesn't handle being told to restore the current | |
1631 | * context very well. Quite often it likes goes to go off and | |
1632 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1633 | * A very simple fix to force the reload is to simply switch | |
1634 | * away from the current context and back again. | |
1635 | * | |
1636 | * Note that the kernel_context will contain random state | |
1637 | * following the INHIBIT_RESTORE. We accept this since we | |
1638 | * never use the kernel_context state; it is merely a | |
1639 | * placeholder we use to flush other contexts. | |
1640 | */ | |
1641 | *cs++ = MI_SET_CONTEXT; | |
9dbfea98 | 1642 | *cs++ = i915_ggtt_offset(engine->kernel_context->state) | |
1fc719d1 CW |
1643 | MI_MM_SPACE_GTT | |
1644 | MI_RESTORE_INHIBIT; | |
1645 | } | |
1646 | ||
8911a31c CW |
1647 | *cs++ = MI_NOOP; |
1648 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1649 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1650 | /* |
1651 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1652 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1653 | */ | |
1654 | *cs++ = MI_NOOP; | |
1655 | ||
cf819eff | 1656 | if (IS_GEN(i915, 7)) { |
8a68d464 | 1657 | if (num_engines) { |
8911a31c CW |
1658 | struct intel_engine_cs *signaller; |
1659 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1660 | ||
8a68d464 | 1661 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1662 | for_each_engine(signaller, i915, id) { |
1663 | if (signaller == engine) | |
1664 | continue; | |
1665 | ||
1666 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1667 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1668 | *cs++ = _MASKED_BIT_DISABLE( | |
1669 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1670 | } | |
1671 | ||
1672 | /* Insert a delay before the next switch! */ | |
1673 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1674 | *cs++ = i915_mmio_reg_offset(last_reg); | |
46c5847e LL |
1675 | *cs++ = intel_gt_scratch_offset(rq->engine->gt, |
1676 | INTEL_GT_SCRATCH_FIELD_DEFAULT); | |
8911a31c CW |
1677 | *cs++ = MI_NOOP; |
1678 | } | |
1679 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1215d28e CW |
1680 | } else if (IS_GEN(i915, 5)) { |
1681 | *cs++ = MI_SUSPEND_FLUSH; | |
8911a31c CW |
1682 | } |
1683 | ||
1684 | intel_ring_advance(rq, cs); | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
c082afac | 1689 | static int remap_l3_slice(struct i915_request *rq, int slice) |
8911a31c CW |
1690 | { |
1691 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1692 | int i; | |
1693 | ||
1694 | if (!remap_info) | |
1695 | return 0; | |
1696 | ||
1697 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1698 | if (IS_ERR(cs)) | |
1699 | return PTR_ERR(cs); | |
1700 | ||
1701 | /* | |
1702 | * Note: We do not worry about the concurrent register cacheline hang | |
1703 | * here because no other code should access these registers other than | |
1704 | * at initialization time. | |
1705 | */ | |
1706 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1707 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1708 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1709 | *cs++ = remap_info[i]; | |
1710 | } | |
1711 | *cs++ = MI_NOOP; | |
1712 | intel_ring_advance(rq, cs); | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
c082afac CW |
1717 | static int remap_l3(struct i915_request *rq) |
1718 | { | |
1719 | struct i915_gem_context *ctx = rq->gem_context; | |
1720 | int i, err; | |
1721 | ||
1722 | if (!ctx->remap_slice) | |
1723 | return 0; | |
1724 | ||
1725 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
1726 | if (!(ctx->remap_slice & BIT(i))) | |
1727 | continue; | |
1728 | ||
1729 | err = remap_l3_slice(rq, i); | |
1730 | if (err) | |
1731 | return err; | |
1732 | } | |
1733 | ||
1734 | ctx->remap_slice = 0; | |
1735 | return 0; | |
1736 | } | |
1737 | ||
e61e0f51 | 1738 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1739 | { |
1740 | struct intel_engine_cs *engine = rq->engine; | |
c082afac | 1741 | struct i915_address_space *vm = vm_alias(rq->hw_context); |
b3ee09a4 | 1742 | unsigned int unwind_mm = 0; |
8911a31c | 1743 | u32 hw_flags = 0; |
c082afac | 1744 | int ret; |
8911a31c | 1745 | |
8911a31c CW |
1746 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); |
1747 | ||
e568ac38 | 1748 | if (vm) { |
ab53497b | 1749 | struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
e2a13d1b CW |
1750 | int loops; |
1751 | ||
1752 | /* | |
1753 | * Baytail takes a little more convincing that it really needs | |
1754 | * to reload the PD between contexts. It is not just a little | |
1755 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1756 | * adding a long loop around flush_pd_dir) is not as effective | |
1757 | * as reloading the PD umpteen times. 32 is derived from | |
1758 | * experimentation (gem_exec_parallel/fds) and has no good | |
1759 | * explanation. | |
1760 | */ | |
1761 | loops = 1; | |
8a68d464 | 1762 | if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) |
e2a13d1b CW |
1763 | loops = 32; |
1764 | ||
1765 | do { | |
1766 | ret = load_pd_dir(rq, ppgtt); | |
1767 | if (ret) | |
1768 | goto err; | |
1769 | } while (--loops); | |
8911a31c | 1770 | |
8a68d464 CW |
1771 | if (ppgtt->pd_dirty_engines & engine->mask) { |
1772 | unwind_mm = engine->mask; | |
1773 | ppgtt->pd_dirty_engines &= ~unwind_mm; | |
b3ee09a4 CW |
1774 | hw_flags = MI_FORCE_RESTORE; |
1775 | } | |
8911a31c CW |
1776 | } |
1777 | ||
b3ee09a4 | 1778 | if (rq->hw_context->state) { |
8a68d464 | 1779 | GEM_BUG_ON(engine->id != RCS0); |
8911a31c CW |
1780 | |
1781 | /* | |
1782 | * The kernel context(s) is treated as pure scratch and is not | |
1783 | * expected to retain any state (as we sacrifice it during | |
1784 | * suspend and on resume it may be corrupted). This is ok, | |
1785 | * as nothing actually executes using the kernel context; it | |
1786 | * is purely used for flushing user contexts. | |
1787 | */ | |
c082afac | 1788 | if (i915_gem_context_is_kernel(rq->gem_context)) |
8911a31c CW |
1789 | hw_flags = MI_RESTORE_INHIBIT; |
1790 | ||
1791 | ret = mi_set_context(rq, hw_flags); | |
1792 | if (ret) | |
1793 | goto err_mm; | |
8911a31c | 1794 | } |
8911a31c | 1795 | |
e568ac38 | 1796 | if (vm) { |
06348d30 CW |
1797 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1798 | if (ret) | |
1799 | goto err_mm; | |
1800 | ||
d9d117e4 CW |
1801 | ret = flush_pd_dir(rq); |
1802 | if (ret) | |
1803 | goto err_mm; | |
06348d30 CW |
1804 | |
1805 | /* | |
1806 | * Not only do we need a full barrier (post-sync write) after | |
1807 | * invalidating the TLBs, but we need to wait a little bit | |
1808 | * longer. Whether this is merely delaying us, or the | |
1809 | * subsequent flush is a key part of serialising with the | |
1810 | * post-sync op, this extra pass appears vital before a | |
1811 | * mm switch! | |
1812 | */ | |
1813 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1814 | if (ret) | |
1815 | goto err_mm; | |
1816 | ||
1817 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1818 | if (ret) | |
1819 | goto err_mm; | |
8911a31c CW |
1820 | } |
1821 | ||
c082afac CW |
1822 | ret = remap_l3(rq); |
1823 | if (ret) | |
1824 | goto err_mm; | |
8911a31c CW |
1825 | |
1826 | return 0; | |
1827 | ||
8911a31c | 1828 | err_mm: |
b3ee09a4 | 1829 | if (unwind_mm) |
e568ac38 | 1830 | i915_vm_to_ppgtt(vm)->pd_dirty_engines |= unwind_mm; |
8911a31c CW |
1831 | err: |
1832 | return ret; | |
1833 | } | |
1834 | ||
e61e0f51 | 1835 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1836 | { |
fd138212 | 1837 | int ret; |
6310346e | 1838 | |
08819549 | 1839 | GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); |
85474441 | 1840 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1841 | |
5f5800a7 CW |
1842 | /* |
1843 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1844 | * we start building the request - in which case we will just |
1845 | * have to repeat work. | |
1846 | */ | |
a0442461 | 1847 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1848 | |
928f8f42 CW |
1849 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1850 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
fd138212 CW |
1851 | if (ret) |
1852 | return ret; | |
6310346e | 1853 | |
928f8f42 | 1854 | ret = switch_context(request); |
3fef5cda CW |
1855 | if (ret) |
1856 | return ret; | |
1857 | ||
a0442461 | 1858 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1859 | return 0; |
9d773091 CW |
1860 | } |
1861 | ||
e5dadff4 CW |
1862 | static noinline int |
1863 | wait_for_space(struct intel_ring *ring, | |
1864 | struct intel_timeline *tl, | |
1865 | unsigned int bytes) | |
987046ad | 1866 | { |
e61e0f51 | 1867 | struct i915_request *target; |
e95433c7 CW |
1868 | long timeout; |
1869 | ||
95aebcb2 | 1870 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1871 | return 0; |
1872 | ||
e5dadff4 CW |
1873 | GEM_BUG_ON(list_empty(&tl->requests)); |
1874 | list_for_each_entry(target, &tl->requests, link) { | |
1875 | if (target->ring != ring) | |
1876 | continue; | |
1877 | ||
987046ad | 1878 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1879 | if (bytes <= __intel_ring_space(target->postfix, |
1880 | ring->emit, ring->size)) | |
987046ad | 1881 | break; |
79bbcc29 | 1882 | } |
29b1b415 | 1883 | |
e5dadff4 | 1884 | if (GEM_WARN_ON(&target->link == &tl->requests)) |
987046ad CW |
1885 | return -ENOSPC; |
1886 | ||
e61e0f51 | 1887 | timeout = i915_request_wait(target, |
2f530945 | 1888 | I915_WAIT_INTERRUPTIBLE, |
e95433c7 CW |
1889 | MAX_SCHEDULE_TIMEOUT); |
1890 | if (timeout < 0) | |
1891 | return timeout; | |
7da844c5 | 1892 | |
e61e0f51 | 1893 | i915_request_retire_upto(target); |
7da844c5 CW |
1894 | |
1895 | intel_ring_update_space(ring); | |
1896 | GEM_BUG_ON(ring->space < bytes); | |
1897 | return 0; | |
29b1b415 JH |
1898 | } |
1899 | ||
e61e0f51 | 1900 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1901 | { |
e61e0f51 | 1902 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1903 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1904 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1905 | unsigned int need_wrap = 0; | |
1906 | unsigned int total_bytes; | |
73dec95e | 1907 | u32 *cs; |
29b1b415 | 1908 | |
6492ca79 CW |
1909 | /* Packets must be qword aligned. */ |
1910 | GEM_BUG_ON(num_dwords & 1); | |
1911 | ||
e61e0f51 | 1912 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1913 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1914 | |
5e5655c3 CW |
1915 | if (unlikely(total_bytes > remain_usable)) { |
1916 | const int remain_actual = ring->size - ring->emit; | |
1917 | ||
1918 | if (bytes > remain_usable) { | |
1919 | /* | |
1920 | * Not enough space for the basic request. So need to | |
1921 | * flush out the remainder and then wait for | |
1922 | * base + reserved. | |
1923 | */ | |
1924 | total_bytes += remain_actual; | |
1925 | need_wrap = remain_actual | 1; | |
1926 | } else { | |
1927 | /* | |
1928 | * The base request will fit but the reserved space | |
1929 | * falls off the end. So we don't need an immediate | |
1930 | * wrap and only need to effectively wait for the | |
1931 | * reserved size from the start of ringbuffer. | |
1932 | */ | |
e61e0f51 | 1933 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 1934 | } |
cbcc80df MK |
1935 | } |
1936 | ||
5e5655c3 | 1937 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1938 | int ret; |
1939 | ||
1940 | /* | |
1941 | * Space is reserved in the ringbuffer for finalising the | |
1942 | * request, as that cannot be allowed to fail. During request | |
1943 | * finalisation, reserved_space is set to 0 to stop the | |
1944 | * overallocation and the assumption is that then we never need | |
1945 | * to wait (which has the risk of failing with EINTR). | |
1946 | * | |
e61e0f51 | 1947 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 1948 | */ |
e61e0f51 | 1949 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 | 1950 | |
e5dadff4 | 1951 | ret = wait_for_space(ring, rq->timeline, total_bytes); |
cbcc80df | 1952 | if (unlikely(ret)) |
73dec95e | 1953 | return ERR_PTR(ret); |
cbcc80df MK |
1954 | } |
1955 | ||
987046ad | 1956 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1957 | need_wrap &= ~1; |
1958 | GEM_BUG_ON(need_wrap > ring->space); | |
1959 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 1960 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 1961 | |
987046ad | 1962 | /* Fill the tail with MI_NOOP */ |
46b86332 | 1963 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 1964 | ring->space -= need_wrap; |
46b86332 | 1965 | ring->emit = 0; |
987046ad | 1966 | } |
304d695c | 1967 | |
e6ba9992 | 1968 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1969 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1970 | cs = ring->vaddr + ring->emit; |
46b86332 | 1971 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 1972 | ring->emit += bytes; |
1dae2dfb | 1973 | ring->space -= bytes; |
73dec95e TU |
1974 | |
1975 | return cs; | |
8187a2b7 | 1976 | } |
78501eac | 1977 | |
753b1ad4 | 1978 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 1979 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 1980 | { |
1f177a13 CW |
1981 | int num_dwords; |
1982 | void *cs; | |
753b1ad4 | 1983 | |
1f177a13 | 1984 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
1985 | if (num_dwords == 0) |
1986 | return 0; | |
1987 | ||
1f177a13 CW |
1988 | num_dwords = CACHELINE_DWORDS - num_dwords; |
1989 | GEM_BUG_ON(num_dwords & 1); | |
1990 | ||
e61e0f51 | 1991 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
1992 | if (IS_ERR(cs)) |
1993 | return PTR_ERR(cs); | |
753b1ad4 | 1994 | |
1f177a13 | 1995 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 1996 | intel_ring_advance(rq, cs); |
753b1ad4 | 1997 | |
1f177a13 | 1998 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
1999 | return 0; |
2000 | } | |
2001 | ||
e61e0f51 | 2002 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 2003 | { |
baba6e57 | 2004 | struct intel_uncore *uncore = request->engine->uncore; |
881f47b6 | 2005 | |
d2d551c0 | 2006 | intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); |
76f8421f | 2007 | |
881f47b6 | 2008 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2009 | |
2010 | /* Disable notification that the ring is IDLE. The GT | |
2011 | * will then assume that it is busy and bring it out of rc6. | |
2012 | */ | |
d2d551c0 DCS |
2013 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
2014 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2015 | |
2016 | /* Clear the context id. Here be magic! */ | |
d2d551c0 | 2017 | intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0); |
0206e353 | 2018 | |
12f55818 | 2019 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
d2d551c0 | 2020 | if (__intel_wait_for_register_fw(uncore, |
02b312d0 CW |
2021 | GEN6_BSD_SLEEP_PSMI_CONTROL, |
2022 | GEN6_BSD_SLEEP_INDICATOR, | |
2023 | 0, | |
2024 | 1000, 0, NULL)) | |
12f55818 | 2025 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2026 | |
12f55818 | 2027 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2028 | i9xx_submit_request(request); |
12f55818 CW |
2029 | |
2030 | /* Let the ring send IDLE messages to the GT again, | |
2031 | * and so let it sleep to conserve power when idle. | |
2032 | */ | |
d2d551c0 DCS |
2033 | intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL, |
2034 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
76f8421f | 2035 | |
d2d551c0 | 2036 | intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); |
881f47b6 XH |
2037 | } |
2038 | ||
06348d30 | 2039 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 2040 | { |
73dec95e | 2041 | u32 cmd, *cs; |
b72f3acb | 2042 | |
e61e0f51 | 2043 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
2044 | if (IS_ERR(cs)) |
2045 | return PTR_ERR(cs); | |
b72f3acb | 2046 | |
71a77e07 | 2047 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 2048 | |
70b73f9a CW |
2049 | /* |
2050 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2051 | * commands, such as breadcrumb interrupts, are strictly ordered |
2052 | * wrt the contents of the write cache being flushed to memory | |
2053 | * (and thus being coherent from the CPU). | |
2054 | */ | |
2055 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2056 | ||
9a289771 | 2057 | /* |
70b73f9a | 2058 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2059 | * "If ENABLED, all TLBs will be invalidated once the flush |
2060 | * operation is complete. This bit is only valid when the | |
2061 | * Post-Sync Operation field is a value of 1h or 3h." | |
2062 | */ | |
70b73f9a | 2063 | cmd |= flags; |
f0a1fb10 | 2064 | |
73dec95e TU |
2065 | *cs++ = cmd; |
2066 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2067 | *cs++ = 0; |
73dec95e | 2068 | *cs++ = MI_NOOP; |
70b73f9a | 2069 | |
e61e0f51 | 2070 | intel_ring_advance(rq, cs); |
70b73f9a | 2071 | |
1c7a0623 BW |
2072 | return 0; |
2073 | } | |
2074 | ||
70b73f9a CW |
2075 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2076 | { | |
06348d30 | 2077 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2078 | } |
2079 | ||
2080 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2081 | { | |
2082 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2083 | } | |
2084 | ||
d7d4eedd | 2085 | static int |
e61e0f51 | 2086 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2087 | u64 offset, u32 len, |
2088 | unsigned int dispatch_flags) | |
d7d4eedd | 2089 | { |
73dec95e | 2090 | u32 *cs; |
d7d4eedd | 2091 | |
e61e0f51 | 2092 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2093 | if (IS_ERR(cs)) |
2094 | return PTR_ERR(cs); | |
d7d4eedd | 2095 | |
73dec95e | 2096 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2097 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2098 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2099 | *cs++ = offset; |
e61e0f51 | 2100 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2101 | |
2102 | return 0; | |
2103 | } | |
2104 | ||
881f47b6 | 2105 | static int |
e61e0f51 | 2106 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2107 | u64 offset, u32 len, |
2108 | unsigned int dispatch_flags) | |
881f47b6 | 2109 | { |
73dec95e | 2110 | u32 *cs; |
ab6f8e32 | 2111 | |
e61e0f51 | 2112 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2113 | if (IS_ERR(cs)) |
2114 | return PTR_ERR(cs); | |
e1f99ce6 | 2115 | |
73dec95e TU |
2116 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2117 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2118 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2119 | *cs++ = offset; |
e61e0f51 | 2120 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2121 | |
0206e353 | 2122 | return 0; |
881f47b6 XH |
2123 | } |
2124 | ||
549f7365 CW |
2125 | /* Blitter support (SandyBridge+) */ |
2126 | ||
e61e0f51 | 2127 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2128 | { |
70b73f9a | 2129 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2130 | } |
2131 | ||
ff44ad51 CW |
2132 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2133 | { | |
2134 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2135 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2136 | |
2137 | engine->park = NULL; | |
2138 | engine->unpark = NULL; | |
ff44ad51 CW |
2139 | } |
2140 | ||
2141 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2142 | { | |
aba5e278 | 2143 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2144 | engine->submit_request = gen6_bsd_submit_request; |
2145 | } | |
2146 | ||
45b9c968 CW |
2147 | static void ring_destroy(struct intel_engine_cs *engine) |
2148 | { | |
2149 | struct drm_i915_private *dev_priv = engine->i915; | |
2150 | ||
2151 | WARN_ON(INTEL_GEN(dev_priv) > 2 && | |
2152 | (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); | |
2153 | ||
09c5ab38 CW |
2154 | intel_engine_cleanup_common(engine); |
2155 | ||
75d0a7f3 CW |
2156 | intel_ring_unpin(engine->legacy.ring); |
2157 | intel_ring_put(engine->legacy.ring); | |
2158 | ||
2159 | intel_timeline_unpin(engine->legacy.timeline); | |
2160 | intel_timeline_put(engine->legacy.timeline); | |
45b9c968 | 2161 | |
45b9c968 CW |
2162 | kfree(engine); |
2163 | } | |
2164 | ||
11334c6a CW |
2165 | static void setup_irq(struct intel_engine_cs *engine) |
2166 | { | |
2167 | struct drm_i915_private *i915 = engine->i915; | |
2168 | ||
2169 | if (INTEL_GEN(i915) >= 6) { | |
2170 | engine->irq_enable = gen6_irq_enable; | |
2171 | engine->irq_disable = gen6_irq_disable; | |
2172 | } else if (INTEL_GEN(i915) >= 5) { | |
2173 | engine->irq_enable = gen5_irq_enable; | |
2174 | engine->irq_disable = gen5_irq_disable; | |
2175 | } else if (INTEL_GEN(i915) >= 3) { | |
2176 | engine->irq_enable = i9xx_irq_enable; | |
2177 | engine->irq_disable = i9xx_irq_disable; | |
2178 | } else { | |
2179 | engine->irq_enable = i8xx_irq_enable; | |
2180 | engine->irq_disable = i8xx_irq_disable; | |
2181 | } | |
2182 | } | |
2183 | ||
2184 | static void setup_common(struct intel_engine_cs *engine) | |
06a2fe22 | 2185 | { |
11334c6a CW |
2186 | struct drm_i915_private *i915 = engine->i915; |
2187 | ||
79e6770c | 2188 | /* gen8+ are only supported with execlists */ |
11334c6a | 2189 | GEM_BUG_ON(INTEL_GEN(i915) >= 8); |
79e6770c | 2190 | |
11334c6a | 2191 | setup_irq(engine); |
618e4ca7 | 2192 | |
45b9c968 CW |
2193 | engine->destroy = ring_destroy; |
2194 | ||
79ffac85 | 2195 | engine->resume = xcs_resume; |
5adfb772 CW |
2196 | engine->reset.prepare = reset_prepare; |
2197 | engine->reset.reset = reset_ring; | |
2198 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2199 | |
4dc84b77 | 2200 | engine->cops = &ring_context_ops; |
f73e7399 CW |
2201 | engine->request_alloc = ring_request_alloc; |
2202 | ||
85474441 CW |
2203 | /* |
2204 | * Using a global execution timeline; the previous final breadcrumb is | |
2205 | * equivalent to our next initial bread so we can elide | |
2206 | * engine->emit_init_breadcrumb(). | |
2207 | */ | |
2208 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
11334c6a | 2209 | if (IS_GEN(i915, 5)) |
85474441 | 2210 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2211 | |
2212 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2213 | |
11334c6a | 2214 | if (INTEL_GEN(i915) >= 6) |
803688ba | 2215 | engine->emit_bb_start = gen6_emit_bb_start; |
11334c6a | 2216 | else if (INTEL_GEN(i915) >= 4) |
803688ba | 2217 | engine->emit_bb_start = i965_emit_bb_start; |
11334c6a | 2218 | else if (IS_I830(i915) || IS_I845G(i915)) |
803688ba | 2219 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2220 | else |
803688ba | 2221 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2222 | } |
2223 | ||
11334c6a | 2224 | static void setup_rcs(struct intel_engine_cs *engine) |
5c1143bb | 2225 | { |
11334c6a | 2226 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2227 | |
11334c6a | 2228 | if (HAS_L3_DPF(i915)) |
61ff75ac | 2229 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
f8973c21 | 2230 | |
fa6f071d DCS |
2231 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2232 | ||
11334c6a | 2233 | if (INTEL_GEN(i915) >= 7) { |
c7fe7d25 | 2234 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2235 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
11334c6a | 2236 | } else if (IS_GEN(i915, 6)) { |
caa5915b | 2237 | engine->emit_flush = gen6_render_ring_flush; |
85474441 | 2238 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
11334c6a | 2239 | } else if (IS_GEN(i915, 5)) { |
c7fe7d25 | 2240 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2241 | } else { |
11334c6a | 2242 | if (INTEL_GEN(i915) < 4) |
c7fe7d25 | 2243 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2244 | else |
c7fe7d25 | 2245 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2246 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2247 | } |
707d9cf9 | 2248 | |
11334c6a | 2249 | if (IS_HASWELL(i915)) |
803688ba | 2250 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2251 | |
79ffac85 | 2252 | engine->resume = rcs_resume; |
5c1143bb XH |
2253 | } |
2254 | ||
11334c6a | 2255 | static void setup_vcs(struct intel_engine_cs *engine) |
5c1143bb | 2256 | { |
11334c6a | 2257 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2258 | |
11334c6a | 2259 | if (INTEL_GEN(i915) >= 6) { |
0fd2c201 | 2260 | /* gen6 bsd needs a special wa for tail updates */ |
11334c6a | 2261 | if (IS_GEN(i915, 6)) |
ff44ad51 | 2262 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2263 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2264 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2265 | |
11334c6a | 2266 | if (IS_GEN(i915, 6)) |
85474441 | 2267 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2268 | else |
85474441 | 2269 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2270 | } else { |
c7fe7d25 | 2271 | engine->emit_flush = bsd_ring_flush; |
11334c6a | 2272 | if (IS_GEN(i915, 5)) |
e2f80391 | 2273 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2274 | else |
e2f80391 | 2275 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2276 | } |
5c1143bb | 2277 | } |
549f7365 | 2278 | |
11334c6a | 2279 | static void setup_bcs(struct intel_engine_cs *engine) |
549f7365 | 2280 | { |
11334c6a | 2281 | struct drm_i915_private *i915 = engine->i915; |
06a2fe22 | 2282 | |
c7fe7d25 | 2283 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2284 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2285 | |
11334c6a | 2286 | if (IS_GEN(i915, 6)) |
85474441 | 2287 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2288 | else |
85474441 | 2289 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
549f7365 | 2290 | } |
a7b9761d | 2291 | |
11334c6a | 2292 | static void setup_vecs(struct intel_engine_cs *engine) |
9a8a2213 | 2293 | { |
11334c6a | 2294 | struct drm_i915_private *i915 = engine->i915; |
caa5915b | 2295 | |
11334c6a | 2296 | GEM_BUG_ON(INTEL_GEN(i915) < 7); |
06a2fe22 | 2297 | |
c7fe7d25 | 2298 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2299 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2300 | engine->irq_enable = hsw_vebox_irq_enable; | |
2301 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2302 | |
85474441 | 2303 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
11334c6a CW |
2304 | } |
2305 | ||
2306 | int intel_ring_submission_setup(struct intel_engine_cs *engine) | |
2307 | { | |
2308 | setup_common(engine); | |
2309 | ||
2310 | switch (engine->class) { | |
2311 | case RENDER_CLASS: | |
2312 | setup_rcs(engine); | |
2313 | break; | |
2314 | case VIDEO_DECODE_CLASS: | |
2315 | setup_vcs(engine); | |
2316 | break; | |
2317 | case COPY_ENGINE_CLASS: | |
2318 | setup_bcs(engine); | |
2319 | break; | |
2320 | case VIDEO_ENHANCEMENT_CLASS: | |
2321 | setup_vecs(engine); | |
2322 | break; | |
2323 | default: | |
2324 | MISSING_CASE(engine->class); | |
2325 | return -ENODEV; | |
2326 | } | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | int intel_ring_submission_init(struct intel_engine_cs *engine) | |
2332 | { | |
f0c02c1b | 2333 | struct intel_timeline *timeline; |
11334c6a CW |
2334 | struct intel_ring *ring; |
2335 | int err; | |
2336 | ||
f0c02c1b | 2337 | timeline = intel_timeline_create(engine->gt, engine->status_page.vma); |
11334c6a CW |
2338 | if (IS_ERR(timeline)) { |
2339 | err = PTR_ERR(timeline); | |
2340 | goto err; | |
2341 | } | |
2342 | GEM_BUG_ON(timeline->has_initial_breadcrumb); | |
2343 | ||
75d0a7f3 CW |
2344 | err = intel_timeline_pin(timeline); |
2345 | if (err) | |
2346 | goto err_timeline; | |
2347 | ||
2348 | ring = intel_engine_create_ring(engine, SZ_16K); | |
11334c6a CW |
2349 | if (IS_ERR(ring)) { |
2350 | err = PTR_ERR(ring); | |
75d0a7f3 | 2351 | goto err_timeline_unpin; |
11334c6a CW |
2352 | } |
2353 | ||
2354 | err = intel_ring_pin(ring); | |
2355 | if (err) | |
2356 | goto err_ring; | |
caa5915b | 2357 | |
75d0a7f3 CW |
2358 | GEM_BUG_ON(engine->legacy.ring); |
2359 | engine->legacy.ring = ring; | |
2360 | engine->legacy.timeline = timeline; | |
11334c6a CW |
2361 | |
2362 | err = intel_engine_init_common(engine); | |
2363 | if (err) | |
75d0a7f3 | 2364 | goto err_ring_unpin; |
11334c6a | 2365 | |
75d0a7f3 | 2366 | GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); |
11334c6a CW |
2367 | |
2368 | return 0; | |
2369 | ||
75d0a7f3 | 2370 | err_ring_unpin: |
11334c6a CW |
2371 | intel_ring_unpin(ring); |
2372 | err_ring: | |
2373 | intel_ring_put(ring); | |
75d0a7f3 CW |
2374 | err_timeline_unpin: |
2375 | intel_timeline_unpin(timeline); | |
2376 | err_timeline: | |
2377 | intel_timeline_put(timeline); | |
11334c6a CW |
2378 | err: |
2379 | intel_engine_cleanup_common(engine); | |
2380 | return err; | |
9a8a2213 | 2381 | } |