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1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ke Yu | |
25 | * Zhiyuan Lv <zhiyuan.lv@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Terrence Xu <terrence.xu@intel.com> | |
29 | * Changbin Du <changbin.du@intel.com> | |
30 | * Bing Niu <bing.niu@intel.com> | |
31 | * Zhi Wang <zhi.a.wang@intel.com> | |
32 | * | |
33 | */ | |
34 | ||
35 | #ifndef _GVT_DISPLAY_H_ | |
36 | #define _GVT_DISPLAY_H_ | |
37 | ||
38 | #define SBI_REG_MAX 20 | |
39 | #define DPCD_SIZE 0x700 | |
40 | ||
41 | #define intel_vgpu_port(vgpu, port) \ | |
42 | (&(vgpu->display.ports[port])) | |
43 | ||
44 | #define intel_vgpu_has_monitor_on_port(vgpu, port) \ | |
45 | (intel_vgpu_port(vgpu, port)->edid && \ | |
46 | intel_vgpu_port(vgpu, port)->edid->data_valid) | |
47 | ||
48 | #define intel_vgpu_port_is_dp(vgpu, port) \ | |
49 | ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \ | |
50 | (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \ | |
51 | (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \ | |
52 | (intel_vgpu_port(vgpu, port)->type == GVT_DP_D)) | |
53 | ||
54 | #define INTEL_GVT_MAX_UEVENT_VARS 3 | |
55 | ||
56 | /* DPCD start */ | |
57 | #define DPCD_SIZE 0x700 | |
58 | ||
59 | /* DPCD */ | |
60 | #define DP_SET_POWER 0x600 | |
61 | #define DP_SET_POWER_D0 0x1 | |
62 | #define AUX_NATIVE_WRITE 0x8 | |
63 | #define AUX_NATIVE_READ 0x9 | |
64 | ||
65 | #define AUX_NATIVE_REPLY_MASK (0x3 << 4) | |
66 | #define AUX_NATIVE_REPLY_ACK (0x0 << 4) | |
67 | #define AUX_NATIVE_REPLY_NAK (0x1 << 4) | |
68 | #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) | |
69 | ||
70 | #define AUX_BURST_SIZE 16 | |
71 | ||
72 | /* DPCD addresses */ | |
73 | #define DPCD_REV 0x000 | |
74 | #define DPCD_MAX_LINK_RATE 0x001 | |
75 | #define DPCD_MAX_LANE_COUNT 0x002 | |
76 | ||
77 | #define DPCD_TRAINING_PATTERN_SET 0x102 | |
78 | #define DPCD_SINK_COUNT 0x200 | |
79 | #define DPCD_LANE0_1_STATUS 0x202 | |
80 | #define DPCD_LANE2_3_STATUS 0x203 | |
81 | #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204 | |
82 | #define DPCD_SINK_STATUS 0x205 | |
83 | ||
84 | /* link training */ | |
85 | #define DPCD_TRAINING_PATTERN_SET_MASK 0x03 | |
86 | #define DPCD_LINK_TRAINING_DISABLED 0x00 | |
87 | #define DPCD_TRAINING_PATTERN_1 0x01 | |
88 | #define DPCD_TRAINING_PATTERN_2 0x02 | |
89 | ||
90 | #define DPCD_CP_READY_MASK (1 << 6) | |
91 | ||
92 | /* lane status */ | |
93 | #define DPCD_LANES_CR_DONE 0x11 | |
94 | #define DPCD_LANES_EQ_DONE 0x22 | |
95 | #define DPCD_SYMBOL_LOCKED 0x44 | |
96 | ||
97 | #define DPCD_INTERLANE_ALIGN_DONE 0x01 | |
98 | ||
99 | #define DPCD_SINK_IN_SYNC 0x03 | |
100 | /* DPCD end */ | |
101 | ||
102 | #define SBI_RESPONSE_MASK 0x3 | |
103 | #define SBI_RESPONSE_SHIFT 0x1 | |
104 | #define SBI_STAT_MASK 0x1 | |
105 | #define SBI_STAT_SHIFT 0x0 | |
106 | #define SBI_OPCODE_SHIFT 8 | |
107 | #define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT) | |
108 | #define SBI_CMD_IORD 2 | |
109 | #define SBI_CMD_IOWR 3 | |
110 | #define SBI_CMD_CRRD 6 | |
111 | #define SBI_CMD_CRWR 7 | |
112 | #define SBI_ADDR_OFFSET_SHIFT 16 | |
113 | #define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT) | |
114 | ||
115 | struct intel_vgpu_sbi_register { | |
116 | unsigned int offset; | |
117 | u32 value; | |
118 | }; | |
119 | ||
120 | struct intel_vgpu_sbi { | |
121 | int number; | |
122 | struct intel_vgpu_sbi_register registers[SBI_REG_MAX]; | |
123 | }; | |
124 | ||
125 | enum intel_gvt_plane_type { | |
126 | PRIMARY_PLANE = 0, | |
127 | CURSOR_PLANE, | |
128 | SPRITE_PLANE, | |
129 | MAX_PLANE | |
130 | }; | |
131 | ||
132 | struct intel_vgpu_dpcd_data { | |
133 | bool data_valid; | |
134 | u8 data[DPCD_SIZE]; | |
135 | }; | |
136 | ||
137 | enum intel_vgpu_port_type { | |
138 | GVT_CRT = 0, | |
139 | GVT_DP_A, | |
140 | GVT_DP_B, | |
141 | GVT_DP_C, | |
142 | GVT_DP_D, | |
143 | GVT_HDMI_B, | |
144 | GVT_HDMI_C, | |
145 | GVT_HDMI_D, | |
146 | GVT_PORT_MAX | |
147 | }; | |
148 | ||
149 | struct intel_vgpu_port { | |
150 | /* per display EDID information */ | |
151 | struct intel_vgpu_edid_data *edid; | |
152 | /* per display DPCD information */ | |
153 | struct intel_vgpu_dpcd_data *dpcd; | |
154 | int type; | |
155 | }; | |
156 | ||
bca5609f ZW |
157 | enum intel_vgpu_edid { |
158 | GVT_EDID_1024_768, | |
159 | GVT_EDID_1920_1200, | |
160 | GVT_EDID_NUM, | |
161 | }; | |
162 | ||
d1a513be ZW |
163 | static inline char *vgpu_edid_str(enum intel_vgpu_edid id) |
164 | { | |
165 | switch (id) { | |
166 | case GVT_EDID_1024_768: | |
167 | return "1024x768"; | |
168 | case GVT_EDID_1920_1200: | |
169 | return "1920x1200"; | |
170 | default: | |
171 | return ""; | |
172 | } | |
173 | } | |
174 | ||
04d348ae ZW |
175 | void intel_gvt_emulate_vblank(struct intel_gvt *gvt); |
176 | void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt); | |
177 | ||
d1a513be | 178 | int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution); |
6294b61b | 179 | void intel_vgpu_reset_display(struct intel_vgpu *vgpu); |
04d348ae ZW |
180 | void intel_vgpu_clean_display(struct intel_vgpu *vgpu); |
181 | ||
182 | #endif |