]>
Commit | Line | Data |
---|---|---|
04d348ae ZW |
1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ke Yu | |
25 | * Zhiyuan Lv <zhiyuan.lv@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Terrence Xu <terrence.xu@intel.com> | |
29 | * Changbin Du <changbin.du@intel.com> | |
30 | * Bing Niu <bing.niu@intel.com> | |
31 | * Zhi Wang <zhi.a.wang@intel.com> | |
32 | * | |
33 | */ | |
34 | ||
35 | #include "i915_drv.h" | |
feddf6e8 | 36 | #include "gvt.h" |
04d348ae ZW |
37 | |
38 | #define GMBUS1_TOTAL_BYTES_SHIFT 16 | |
39 | #define GMBUS1_TOTAL_BYTES_MASK 0x1ff | |
40 | #define gmbus1_total_byte_count(v) (((v) >> \ | |
41 | GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK) | |
42 | #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1) | |
43 | #define gmbus1_slave_index(v) (((v) >> 8) & 0xff) | |
44 | #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7) | |
45 | ||
46 | /* GMBUS0 bits definitions */ | |
47 | #define _GMBUS_PIN_SEL_MASK (0x7) | |
48 | ||
49 | static unsigned char edid_get_byte(struct intel_vgpu *vgpu) | |
50 | { | |
51 | struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; | |
52 | unsigned char chr = 0; | |
53 | ||
54 | if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) { | |
695fbc08 | 55 | gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n"); |
04d348ae ZW |
56 | return 0; |
57 | } | |
58 | if (edid->current_edid_read >= EDID_SIZE) { | |
695fbc08 | 59 | gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n"); |
04d348ae ZW |
60 | return 0; |
61 | } | |
62 | ||
63 | if (!edid->edid_available) { | |
695fbc08 | 64 | gvt_vgpu_err("Reading EDID but EDID is not available!\n"); |
04d348ae ZW |
65 | return 0; |
66 | } | |
67 | ||
68 | if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) { | |
69 | struct intel_vgpu_edid_data *edid_data = | |
70 | intel_vgpu_port(vgpu, edid->port)->edid; | |
71 | ||
72 | chr = edid_data->edid_block[edid->current_edid_read]; | |
73 | edid->current_edid_read++; | |
74 | } else { | |
695fbc08 | 75 | gvt_vgpu_err("No EDID available during the reading?\n"); |
04d348ae ZW |
76 | } |
77 | return chr; | |
78 | } | |
79 | ||
80 | static inline int get_port_from_gmbus0(u32 gmbus0) | |
81 | { | |
82 | int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK; | |
83 | int port = -EINVAL; | |
84 | ||
85 | if (port_select == 2) | |
86 | port = PORT_E; | |
87 | else if (port_select == 4) | |
88 | port = PORT_C; | |
89 | else if (port_select == 5) | |
90 | port = PORT_B; | |
91 | else if (port_select == 6) | |
92 | port = PORT_D; | |
93 | return port; | |
94 | } | |
95 | ||
96 | static void reset_gmbus_controller(struct intel_vgpu *vgpu) | |
97 | { | |
98 | vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; | |
99 | if (!vgpu->display.i2c_edid.edid_available) | |
100 | vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; | |
101 | vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; | |
102 | } | |
103 | ||
104 | /* GMBUS0 */ | |
105 | static int gmbus0_mmio_write(struct intel_vgpu *vgpu, | |
106 | unsigned int offset, void *p_data, unsigned int bytes) | |
107 | { | |
108 | int port, pin_select; | |
109 | ||
110 | memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); | |
111 | ||
112 | pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK; | |
113 | ||
114 | intel_vgpu_init_i2c_edid(vgpu); | |
115 | ||
116 | if (pin_select == 0) | |
117 | return 0; | |
118 | ||
119 | port = get_port_from_gmbus0(pin_select); | |
120 | if (WARN_ON(port < 0)) | |
121 | return 0; | |
122 | ||
123 | vgpu->display.i2c_edid.state = I2C_GMBUS; | |
124 | vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; | |
125 | ||
126 | vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; | |
127 | vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; | |
128 | ||
129 | if (intel_vgpu_has_monitor_on_port(vgpu, port) && | |
130 | !intel_vgpu_port_is_dp(vgpu, port)) { | |
131 | vgpu->display.i2c_edid.port = port; | |
132 | vgpu->display.i2c_edid.edid_available = true; | |
133 | vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; | |
134 | } else | |
135 | vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
140 | void *p_data, unsigned int bytes) | |
141 | { | |
142 | struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; | |
143 | u32 slave_addr; | |
144 | u32 wvalue = *(u32 *)p_data; | |
145 | ||
146 | if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { | |
147 | if (!(wvalue & GMBUS_SW_CLR_INT)) { | |
148 | vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; | |
149 | reset_gmbus_controller(vgpu); | |
150 | } | |
151 | /* | |
152 | * TODO: "This bit is cleared to zero when an event | |
153 | * causes the HW_RDY bit transition to occur " | |
154 | */ | |
155 | } else { | |
156 | /* | |
157 | * per bspec setting this bit can cause: | |
158 | * 1) INT status bit cleared | |
159 | * 2) HW_RDY bit asserted | |
160 | */ | |
161 | if (wvalue & GMBUS_SW_CLR_INT) { | |
162 | vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; | |
163 | vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; | |
164 | } | |
165 | ||
166 | /* For virtualization, we suppose that HW is always ready, | |
167 | * so GMBUS_SW_RDY should always be cleared | |
168 | */ | |
169 | if (wvalue & GMBUS_SW_RDY) | |
170 | wvalue &= ~GMBUS_SW_RDY; | |
171 | ||
172 | i2c_edid->gmbus.total_byte_count = | |
173 | gmbus1_total_byte_count(wvalue); | |
174 | slave_addr = gmbus1_slave_addr(wvalue); | |
175 | ||
176 | /* vgpu gmbus only support EDID */ | |
177 | if (slave_addr == EDID_ADDR) { | |
178 | i2c_edid->slave_selected = true; | |
179 | } else if (slave_addr != 0) { | |
180 | gvt_dbg_dpy( | |
181 | "vgpu%d: unsupported gmbus slave addr(0x%x)\n" | |
182 | " gmbus operations will be ignored.\n", | |
183 | vgpu->id, slave_addr); | |
184 | } | |
185 | ||
186 | if (wvalue & GMBUS_CYCLE_INDEX) | |
187 | i2c_edid->current_edid_read = | |
188 | gmbus1_slave_index(wvalue); | |
189 | ||
190 | i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue); | |
191 | switch (gmbus1_bus_cycle(wvalue)) { | |
192 | case GMBUS_NOCYCLE: | |
193 | break; | |
194 | case GMBUS_STOP: | |
195 | /* From spec: | |
196 | * This can only cause a STOP to be generated | |
197 | * if a GMBUS cycle is generated, the GMBUS is | |
198 | * currently in a data/wait/idle phase, or it is in a | |
199 | * WAIT phase | |
200 | */ | |
201 | if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) | |
202 | != GMBUS_NOCYCLE) { | |
203 | intel_vgpu_init_i2c_edid(vgpu); | |
204 | /* After the 'stop' cycle, hw state would become | |
205 | * 'stop phase' and then 'idle phase' after a | |
206 | * few milliseconds. In emulation, we just set | |
207 | * it as 'idle phase' ('stop phase' is not | |
208 | * visible in gmbus interface) | |
209 | */ | |
210 | i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; | |
211 | vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; | |
212 | } | |
213 | break; | |
214 | case NIDX_NS_W: | |
215 | case IDX_NS_W: | |
216 | case NIDX_STOP: | |
217 | case IDX_STOP: | |
218 | /* From hw spec the GMBUS phase | |
219 | * transition like this: | |
220 | * START (-->INDEX) -->DATA | |
221 | */ | |
222 | i2c_edid->gmbus.phase = GMBUS_DATA_PHASE; | |
223 | vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; | |
224 | break; | |
225 | default: | |
695fbc08 | 226 | gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); |
04d348ae ZW |
227 | break; |
228 | } | |
229 | /* | |
230 | * From hw spec the WAIT state will be | |
231 | * cleared: | |
232 | * (1) in a new GMBUS cycle | |
233 | * (2) by generating a stop | |
234 | */ | |
235 | vgpu_vreg(vgpu, offset) = wvalue; | |
236 | } | |
237 | return 0; | |
238 | } | |
239 | ||
240 | static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
241 | void *p_data, unsigned int bytes) | |
242 | { | |
243 | WARN_ON(1); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
248 | void *p_data, unsigned int bytes) | |
249 | { | |
250 | int i; | |
251 | unsigned char byte_data; | |
252 | struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; | |
253 | int byte_left = i2c_edid->gmbus.total_byte_count - | |
254 | i2c_edid->current_edid_read; | |
255 | int byte_count = byte_left; | |
256 | u32 reg_data = 0; | |
257 | ||
258 | /* Data can only be recevied if previous settings correct */ | |
259 | if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { | |
260 | if (byte_left <= 0) { | |
261 | memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | if (byte_count > 4) | |
266 | byte_count = 4; | |
267 | for (i = 0; i < byte_count; i++) { | |
268 | byte_data = edid_get_byte(vgpu); | |
269 | reg_data |= (byte_data << (i << 3)); | |
270 | } | |
271 | ||
272 | memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count); | |
273 | memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); | |
274 | ||
275 | if (byte_left <= 4) { | |
276 | switch (i2c_edid->gmbus.cycle_type) { | |
277 | case NIDX_STOP: | |
278 | case IDX_STOP: | |
279 | i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; | |
280 | break; | |
281 | case NIDX_NS_W: | |
282 | case IDX_NS_W: | |
283 | default: | |
284 | i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE; | |
285 | break; | |
286 | } | |
287 | intel_vgpu_init_i2c_edid(vgpu); | |
288 | } | |
289 | /* | |
290 | * Read GMBUS3 during send operation, | |
291 | * return the latest written value | |
292 | */ | |
293 | } else { | |
294 | memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); | |
695fbc08 | 295 | gvt_vgpu_err("warning: gmbus3 read with nothing returned\n"); |
04d348ae ZW |
296 | } |
297 | return 0; | |
298 | } | |
299 | ||
300 | static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
301 | void *p_data, unsigned int bytes) | |
302 | { | |
303 | u32 value = vgpu_vreg(vgpu, offset); | |
304 | ||
305 | if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE)) | |
306 | vgpu_vreg(vgpu, offset) |= GMBUS_INUSE; | |
307 | memcpy(p_data, (void *)&value, bytes); | |
308 | return 0; | |
309 | } | |
310 | ||
311 | static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
312 | void *p_data, unsigned int bytes) | |
313 | { | |
314 | u32 wvalue = *(u32 *)p_data; | |
315 | ||
316 | if (wvalue & GMBUS_INUSE) | |
317 | vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE; | |
318 | /* All other bits are read-only */ | |
319 | return 0; | |
320 | } | |
321 | ||
322 | /** | |
323 | * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read | |
324 | * @vgpu: a vGPU | |
325 | * | |
326 | * This function is used to emulate gmbus register mmio read | |
327 | * | |
328 | * Returns: | |
329 | * Zero on success, negative error code if failed. | |
330 | * | |
331 | */ | |
332 | int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, | |
333 | unsigned int offset, void *p_data, unsigned int bytes) | |
334 | { | |
335 | if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) | |
336 | return -EINVAL; | |
337 | ||
338 | if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) | |
339 | return gmbus2_mmio_read(vgpu, offset, p_data, bytes); | |
340 | else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) | |
341 | return gmbus3_mmio_read(vgpu, offset, p_data, bytes); | |
342 | ||
343 | memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | /** | |
348 | * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write | |
349 | * @vgpu: a vGPU | |
350 | * | |
351 | * This function is used to emulate gmbus register mmio write | |
352 | * | |
353 | * Returns: | |
354 | * Zero on success, negative error code if failed. | |
355 | * | |
356 | */ | |
357 | int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, | |
358 | unsigned int offset, void *p_data, unsigned int bytes) | |
359 | { | |
360 | if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) | |
361 | return -EINVAL; | |
362 | ||
363 | if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) | |
364 | return gmbus0_mmio_write(vgpu, offset, p_data, bytes); | |
365 | else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) | |
366 | return gmbus1_mmio_write(vgpu, offset, p_data, bytes); | |
367 | else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) | |
368 | return gmbus2_mmio_write(vgpu, offset, p_data, bytes); | |
369 | else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) | |
370 | return gmbus3_mmio_write(vgpu, offset, p_data, bytes); | |
371 | ||
372 | memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); | |
373 | return 0; | |
374 | } | |
375 | ||
376 | enum { | |
377 | AUX_CH_CTL = 0, | |
378 | AUX_CH_DATA1, | |
379 | AUX_CH_DATA2, | |
380 | AUX_CH_DATA3, | |
381 | AUX_CH_DATA4, | |
382 | AUX_CH_DATA5 | |
383 | }; | |
384 | ||
385 | static inline int get_aux_ch_reg(unsigned int offset) | |
386 | { | |
387 | int reg; | |
388 | ||
389 | switch (offset & 0xff) { | |
390 | case 0x10: | |
391 | reg = AUX_CH_CTL; | |
392 | break; | |
393 | case 0x14: | |
394 | reg = AUX_CH_DATA1; | |
395 | break; | |
396 | case 0x18: | |
397 | reg = AUX_CH_DATA2; | |
398 | break; | |
399 | case 0x1c: | |
400 | reg = AUX_CH_DATA3; | |
401 | break; | |
402 | case 0x20: | |
403 | reg = AUX_CH_DATA4; | |
404 | break; | |
405 | case 0x24: | |
406 | reg = AUX_CH_DATA5; | |
407 | break; | |
408 | default: | |
409 | reg = -1; | |
410 | break; | |
411 | } | |
412 | return reg; | |
413 | } | |
414 | ||
415 | #define AUX_CTL_MSG_LENGTH(reg) \ | |
416 | ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \ | |
417 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
418 | ||
419 | /** | |
420 | * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write | |
421 | * @vgpu: a vGPU | |
422 | * | |
423 | * This function is used to emulate AUX channel register write | |
424 | * | |
425 | */ | |
426 | void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, | |
427 | int port_idx, | |
428 | unsigned int offset, | |
429 | void *p_data) | |
430 | { | |
431 | struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; | |
432 | int msg_length, ret_msg_size; | |
433 | int msg, addr, ctrl, op; | |
434 | u32 value = *(u32 *)p_data; | |
435 | int aux_data_for_write = 0; | |
436 | int reg = get_aux_ch_reg(offset); | |
437 | ||
438 | if (reg != AUX_CH_CTL) { | |
439 | vgpu_vreg(vgpu, offset) = value; | |
440 | return; | |
441 | } | |
442 | ||
443 | msg_length = AUX_CTL_MSG_LENGTH(value); | |
444 | // check the msg in DATA register. | |
445 | msg = vgpu_vreg(vgpu, offset + 4); | |
446 | addr = (msg >> 8) & 0xffff; | |
447 | ctrl = (msg >> 24) & 0xff; | |
448 | op = ctrl >> 4; | |
449 | if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) { | |
450 | /* The ctl write to clear some states */ | |
451 | return; | |
452 | } | |
453 | ||
454 | /* Always set the wanted value for vms. */ | |
455 | ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1); | |
456 | vgpu_vreg(vgpu, offset) = | |
457 | DP_AUX_CH_CTL_DONE | | |
458 | ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) & | |
459 | DP_AUX_CH_CTL_MESSAGE_SIZE_MASK); | |
460 | ||
461 | if (msg_length == 3) { | |
462 | if (!(op & GVT_AUX_I2C_MOT)) { | |
463 | /* stop */ | |
464 | intel_vgpu_init_i2c_edid(vgpu); | |
465 | } else { | |
466 | /* start or restart */ | |
467 | i2c_edid->aux_ch.i2c_over_aux_ch = true; | |
468 | i2c_edid->aux_ch.aux_ch_mot = true; | |
469 | if (addr == 0) { | |
470 | /* reset the address */ | |
471 | intel_vgpu_init_i2c_edid(vgpu); | |
472 | } else if (addr == EDID_ADDR) { | |
473 | i2c_edid->state = I2C_AUX_CH; | |
474 | i2c_edid->port = port_idx; | |
475 | i2c_edid->slave_selected = true; | |
476 | if (intel_vgpu_has_monitor_on_port(vgpu, | |
477 | port_idx) && | |
478 | intel_vgpu_port_is_dp(vgpu, port_idx)) | |
479 | i2c_edid->edid_available = true; | |
480 | } | |
481 | } | |
482 | } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) { | |
483 | /* TODO | |
484 | * We only support EDID reading from I2C_over_AUX. And | |
485 | * we do not expect the index mode to be used. Right now | |
486 | * the WRITE operation is ignored. It is good enough to | |
487 | * support the gfx driver to do EDID access. | |
488 | */ | |
489 | } else { | |
490 | if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ)) | |
491 | return; | |
492 | if (WARN_ON(msg_length != 4)) | |
493 | return; | |
494 | if (i2c_edid->edid_available && i2c_edid->slave_selected) { | |
495 | unsigned char val = edid_get_byte(vgpu); | |
496 | ||
497 | aux_data_for_write = (val << 16); | |
14f5ba26 XH |
498 | } else |
499 | aux_data_for_write = (0xff << 16); | |
04d348ae ZW |
500 | } |
501 | /* write the return value in AUX_CH_DATA reg which includes: | |
502 | * ACK of I2C_WRITE | |
503 | * returned byte if it is READ | |
504 | */ | |
ee145f66 | 505 | aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24; |
04d348ae ZW |
506 | vgpu_vreg(vgpu, offset + 4) = aux_data_for_write; |
507 | } | |
508 | ||
509 | /** | |
510 | * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation | |
511 | * @vgpu: a vGPU | |
512 | * | |
513 | * This function is used to initialize vGPU i2c edid emulation stuffs | |
514 | * | |
515 | */ | |
516 | void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu) | |
517 | { | |
518 | struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; | |
519 | ||
520 | edid->state = I2C_NOT_SPECIFIED; | |
521 | ||
522 | edid->port = -1; | |
523 | edid->slave_selected = false; | |
524 | edid->edid_available = false; | |
525 | edid->current_edid_read = 0; | |
526 | ||
527 | memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus)); | |
528 | ||
529 | edid->aux_ch.i2c_over_aux_ch = false; | |
530 | edid->aux_ch.aux_ch_mot = false; | |
531 | } |