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drm/i915/gvt: Fix PTE write flush for taking runtime pm properly
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / gtt.c
CommitLineData
2707e444
ZW		 1/*
2 * GTT virtualization
3 *
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Zhi Wang <zhi.a.wang@intel.com>
27 * Zhenyu Wang <zhenyuw@linux.intel.com>
28 * Xiao Zheng <xiao.zheng@intel.com>
29 *
30 * Contributors:
31 * Min He <min.he@intel.com>
32 * Bing Niu <bing.niu@intel.com>
33 *
34 */
35
36#include "i915_drv.h"
feddf6e8
ZW		 37#include "gvt.h"
38#include "i915_pvinfo.h"
2707e444
ZW		 39#include "trace.h"
40
41static bool enable_out_of_sync = false;
42static int preallocated_oos_pages = 8192;
43
44/*
45 * validate a gm address and related range size,
46 * translate it to host gm address
47 */
48bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
49{
50 if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
51 && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
695fbc08
TZ		 52 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
53 addr, size);
2707e444
ZW		 54 return false;
55 }
56 return true;
57}
58
59/* translate a guest gmadr to host gmadr */
60int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
61{
62 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
63 "invalid guest gmadr %llx\n", g_addr))
64 return -EACCES;
65
66 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
67 *h_addr = vgpu_aperture_gmadr_base(vgpu)
68 + (g_addr - vgpu_aperture_offset(vgpu));
69 else
70 *h_addr = vgpu_hidden_gmadr_base(vgpu)
71 + (g_addr - vgpu_hidden_offset(vgpu));
72 return 0;
73}
74
75/* translate a host gmadr to guest gmadr */
76int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
77{
78 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
79 "invalid host gmadr %llx\n", h_addr))
80 return -EACCES;
81
82 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
83 *g_addr = vgpu_aperture_gmadr_base(vgpu)
84 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
85 else
86 *g_addr = vgpu_hidden_gmadr_base(vgpu)
87 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
88 return 0;
89}
90
91int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
92 unsigned long *h_index)
93{
94 u64 h_addr;
95 int ret;
96
97 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << GTT_PAGE_SHIFT,
98 &h_addr);
99 if (ret)
100 return ret;
101
102 *h_index = h_addr >> GTT_PAGE_SHIFT;
103 return 0;
104}
105
106int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
107 unsigned long *g_index)
108{
109 u64 g_addr;
110 int ret;
111
112 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << GTT_PAGE_SHIFT,
113 &g_addr);
114 if (ret)
115 return ret;
116
117 *g_index = g_addr >> GTT_PAGE_SHIFT;
118 return 0;
119}
120
121#define gtt_type_is_entry(type) \
122 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
123 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
124 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
125
126#define gtt_type_is_pt(type) \
127 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
128
129#define gtt_type_is_pte_pt(type) \
130 (type == GTT_TYPE_PPGTT_PTE_PT)
131
132#define gtt_type_is_root_pointer(type) \
133 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
134
135#define gtt_init_entry(e, t, p, v) do { \
136 (e)->type = t; \
137 (e)->pdev = p; \
138 memcpy(&(e)->val64, &v, sizeof(v)); \
139} while (0)
140
2707e444
ZW		 141/*
142 * Mappings between GTT_TYPE* enumerations.
143 * Following information can be found according to the given type:
144 * - type of next level page table
145 * - type of entry inside this level page table
146 * - type of entry with PSE set
147 *
148 * If the given type doesn't have such a kind of information,
149 * e.g. give a l4 root entry type, then request to get its PSE type,
150 * give a PTE page table type, then request to get its next level page
151 * table type, as we know l4 root entry doesn't have a PSE bit,
152 * and a PTE page table doesn't have a next level page table type,
153 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
154 * page table.
155 */
156
157struct gtt_type_table_entry {
158 int entry_type;
159 int next_pt_type;
160 int pse_entry_type;
161};
162
163#define GTT_TYPE_TABLE_ENTRY(type, e_type, npt_type, pse_type) \
164 [type] = { \
165 .entry_type = e_type, \
166 .next_pt_type = npt_type, \
167 .pse_entry_type = pse_type, \
168 }
169
170static struct gtt_type_table_entry gtt_type_table[] = {
171 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
172 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
173 GTT_TYPE_PPGTT_PML4_PT,
174 GTT_TYPE_INVALID),
175 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
176 GTT_TYPE_PPGTT_PML4_ENTRY,
177 GTT_TYPE_PPGTT_PDP_PT,
178 GTT_TYPE_INVALID),
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
180 GTT_TYPE_PPGTT_PML4_ENTRY,
181 GTT_TYPE_PPGTT_PDP_PT,
182 GTT_TYPE_INVALID),
183 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
184 GTT_TYPE_PPGTT_PDP_ENTRY,
185 GTT_TYPE_PPGTT_PDE_PT,
186 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
187 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
188 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
189 GTT_TYPE_PPGTT_PDE_PT,
190 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
191 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
192 GTT_TYPE_PPGTT_PDP_ENTRY,
193 GTT_TYPE_PPGTT_PDE_PT,
194 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
195 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
196 GTT_TYPE_PPGTT_PDE_ENTRY,
197 GTT_TYPE_PPGTT_PTE_PT,
198 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
200 GTT_TYPE_PPGTT_PDE_ENTRY,
201 GTT_TYPE_PPGTT_PTE_PT,
202 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
203 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
204 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
205 GTT_TYPE_INVALID,
206 GTT_TYPE_INVALID),
207 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
208 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
209 GTT_TYPE_INVALID,
210 GTT_TYPE_INVALID),
211 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
212 GTT_TYPE_PPGTT_PDE_ENTRY,
213 GTT_TYPE_INVALID,
214 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
215 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
216 GTT_TYPE_PPGTT_PDP_ENTRY,
217 GTT_TYPE_INVALID,
218 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
219 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
220 GTT_TYPE_GGTT_PTE,
221 GTT_TYPE_INVALID,
222 GTT_TYPE_INVALID),
223};
224
225static inline int get_next_pt_type(int type)
226{
227 return gtt_type_table[type].next_pt_type;
228}
229
230static inline int get_entry_type(int type)
231{
232 return gtt_type_table[type].entry_type;
233}
234
235static inline int get_pse_type(int type)
236{
237 return gtt_type_table[type].pse_entry_type;
238}
239
240static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
241{
321927db 242 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
905a5035
CD		 243
244 return readq(addr);
2707e444
ZW		 245}
246
247static void write_pte64(struct drm_i915_private *dev_priv,
248 unsigned long index, u64 pte)
249{
321927db 250 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
2707e444 251
2707e444 252 writeq(pte, addr);
905a5035 253
2707e444
ZW		 254 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
255 POSTING_READ(GFX_FLSH_CNTL_GEN6);
256}
257
258static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt,
259 struct intel_gvt_gtt_entry *e,
260 unsigned long index, bool hypervisor_access, unsigned long gpa,
261 struct intel_vgpu *vgpu)
262{
263 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
264 int ret;
265
266 if (WARN_ON(info->gtt_entry_size != 8))
267 return e;
268
269 if (hypervisor_access) {
270 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
271 (index << info->gtt_entry_size_shift),
272 &e->val64, 8);
273 WARN_ON(ret);
274 } else if (!pt) {
275 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
276 } else {
277 e->val64 = *((u64 *)pt + index);
278 }
279 return e;
280}
281
282static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt,
283 struct intel_gvt_gtt_entry *e,
284 unsigned long index, bool hypervisor_access, unsigned long gpa,
285 struct intel_vgpu *vgpu)
286{
287 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
288 int ret;
289
290 if (WARN_ON(info->gtt_entry_size != 8))
291 return e;
292
293 if (hypervisor_access) {
294 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
295 (index << info->gtt_entry_size_shift),
296 &e->val64, 8);
297 WARN_ON(ret);
298 } else if (!pt) {
299 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
300 } else {
301 *((u64 *)pt + index) = e->val64;
302 }
303 return e;
304}
305
306#define GTT_HAW 46
307
308#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
309#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
310#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
311
312static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
313{
314 unsigned long pfn;
315
316 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
317 pfn = (e->val64 & ADDR_1G_MASK) >> 12;
318 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
319 pfn = (e->val64 & ADDR_2M_MASK) >> 12;
320 else
321 pfn = (e->val64 & ADDR_4K_MASK) >> 12;
322 return pfn;
323}
324
325static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
326{
327 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
328 e->val64 &= ~ADDR_1G_MASK;
329 pfn &= (ADDR_1G_MASK >> 12);
330 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
331 e->val64 &= ~ADDR_2M_MASK;
332 pfn &= (ADDR_2M_MASK >> 12);
333 } else {
334 e->val64 &= ~ADDR_4K_MASK;
335 pfn &= (ADDR_4K_MASK >> 12);
336 }
337
338 e->val64 |= (pfn << 12);
339}
340
341static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
342{
343 /* Entry doesn't have PSE bit. */
344 if (get_pse_type(e->type) == GTT_TYPE_INVALID)
345 return false;
346
347 e->type = get_entry_type(e->type);
348 if (!(e->val64 & (1 << 7)))
349 return false;
350
351 e->type = get_pse_type(e->type);
352 return true;
353}
354
355static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
356{
357 /*
358 * i915 writes PDP root pointer registers without present bit,
359 * it also works, so we need to treat root pointer entry
360 * specifically.
361 */
362 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
363 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
364 return (e->val64 != 0);
365 else
366 return (e->val64 & (1 << 0));
367}
368
369static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
370{
371 e->val64 &= ~(1 << 0);
372}
373
374/*
375 * Per-platform GMA routines.
376 */
377static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
378{
379 unsigned long x = (gma >> GTT_PAGE_SHIFT);
380
381 trace_gma_index(__func__, gma, x);
382 return x;
383}
384
385#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
386static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
387{ \
388 unsigned long x = (exp); \
389 trace_gma_index(__func__, gma, x); \
390 return x; \
391}
392
393DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
394DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
395DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
396DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
397DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
398
399static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
400 .get_entry = gtt_get_entry64,
401 .set_entry = gtt_set_entry64,
402 .clear_present = gtt_entry_clear_present,
403 .test_present = gen8_gtt_test_present,
404 .test_pse = gen8_gtt_test_pse,
405 .get_pfn = gen8_gtt_get_pfn,
406 .set_pfn = gen8_gtt_set_pfn,
407};
408
409static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
410 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
411 .gma_to_pte_index = gen8_gma_to_pte_index,
412 .gma_to_pde_index = gen8_gma_to_pde_index,
413 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
414 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
415 .gma_to_pml4_index = gen8_gma_to_pml4_index,
416};
417
418static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
419 struct intel_gvt_gtt_entry *m)
420{
421 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
422 unsigned long gfn, mfn;
423
424 *m = *p;
425
426 if (!ops->test_present(p))
427 return 0;
428
429 gfn = ops->get_pfn(p);
430
431 mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
432 if (mfn == INTEL_GVT_INVALID_ADDR) {
695fbc08 433 gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
2707e444
ZW		 434 return -ENXIO;
435 }
436
437 ops->set_pfn(m, mfn);
438 return 0;
439}
440
441/*
442 * MM helpers.
443 */
444struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm,
445 void *page_table, struct intel_gvt_gtt_entry *e,
446 unsigned long index)
447{
448 struct intel_gvt *gvt = mm->vgpu->gvt;
449 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
450
451 e->type = mm->page_table_entry_type;
452
453 ops->get_entry(page_table, e, index, false, 0, mm->vgpu);
454 ops->test_pse(e);
455 return e;
456}
457
458struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm,
459 void *page_table, struct intel_gvt_gtt_entry *e,
460 unsigned long index)
461{
462 struct intel_gvt *gvt = mm->vgpu->gvt;
463 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
464
465 return ops->set_entry(page_table, e, index, false, 0, mm->vgpu);
466}
467
468/*
469 * PPGTT shadow page table helpers.
470 */
471static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry(
472 struct intel_vgpu_ppgtt_spt *spt,
473 void *page_table, int type,
474 struct intel_gvt_gtt_entry *e, unsigned long index,
475 bool guest)
476{
477 struct intel_gvt *gvt = spt->vgpu->gvt;
478 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
479
480 e->type = get_entry_type(type);
481
482 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
483 return e;
484
485 ops->get_entry(page_table, e, index, guest,
486 spt->guest_page.gfn << GTT_PAGE_SHIFT,
487 spt->vgpu);
488 ops->test_pse(e);
489 return e;
490}
491
492static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry(
493 struct intel_vgpu_ppgtt_spt *spt,
494 void *page_table, int type,
495 struct intel_gvt_gtt_entry *e, unsigned long index,
496 bool guest)
497{
498 struct intel_gvt *gvt = spt->vgpu->gvt;
499 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
500
501 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
502 return e;
503
504 return ops->set_entry(page_table, e, index, guest,
505 spt->guest_page.gfn << GTT_PAGE_SHIFT,
506 spt->vgpu);
507}
508
509#define ppgtt_get_guest_entry(spt, e, index) \
510 ppgtt_spt_get_entry(spt, NULL, \
511 spt->guest_page_type, e, index, true)
512
513#define ppgtt_set_guest_entry(spt, e, index) \
514 ppgtt_spt_set_entry(spt, NULL, \
515 spt->guest_page_type, e, index, true)
516
517#define ppgtt_get_shadow_entry(spt, e, index) \
518 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
519 spt->shadow_page.type, e, index, false)
520
521#define ppgtt_set_shadow_entry(spt, e, index) \
522 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
523 spt->shadow_page.type, e, index, false)
524
525/**
526 * intel_vgpu_init_guest_page - init a guest page data structure
527 * @vgpu: a vGPU
528 * @p: a guest page data structure
529 * @gfn: guest memory page frame number
530 * @handler: function will be called when target guest memory page has
531 * been modified.
532 *
533 * This function is called when user wants to track a guest memory page.
534 *
535 * Returns:
536 * Zero on success, negative error code if failed.
537 */
538int intel_vgpu_init_guest_page(struct intel_vgpu *vgpu,
539 struct intel_vgpu_guest_page *p,
540 unsigned long gfn,
541 int (*handler)(void *, u64, void *, int),
542 void *data)
543{
544 INIT_HLIST_NODE(&p->node);
545
546 p->writeprotection = false;
547 p->gfn = gfn;
548 p->handler = handler;
549 p->data = data;
550 p->oos_page = NULL;
551 p->write_cnt = 0;
552
553 hash_add(vgpu->gtt.guest_page_hash_table, &p->node, p->gfn);
554 return 0;
555}
556
557static int detach_oos_page(struct intel_vgpu *vgpu,
558 struct intel_vgpu_oos_page *oos_page);
559
560/**
561 * intel_vgpu_clean_guest_page - release the resource owned by guest page data
562 * structure
563 * @vgpu: a vGPU
564 * @p: a tracked guest page
565 *
566 * This function is called when user tries to stop tracking a guest memory
567 * page.
568 */
569void intel_vgpu_clean_guest_page(struct intel_vgpu *vgpu,
570 struct intel_vgpu_guest_page *p)
571{
572 if (!hlist_unhashed(&p->node))
573 hash_del(&p->node);
574
575 if (p->oos_page)
576 detach_oos_page(vgpu, p->oos_page);
577
578 if (p->writeprotection)
579 intel_gvt_hypervisor_unset_wp_page(vgpu, p);
580}
581
582/**
583 * intel_vgpu_find_guest_page - find a guest page data structure by GFN.
584 * @vgpu: a vGPU
585 * @gfn: guest memory page frame number
586 *
587 * This function is called when emulation logic wants to know if a trapped GFN
588 * is a tracked guest page.
589 *
590 * Returns:
591 * Pointer to guest page data structure, NULL if failed.
592 */
593struct intel_vgpu_guest_page *intel_vgpu_find_guest_page(
594 struct intel_vgpu *vgpu, unsigned long gfn)
595{
596 struct intel_vgpu_guest_page *p;
597
598 hash_for_each_possible(vgpu->gtt.guest_page_hash_table,
599 p, node, gfn) {
600 if (p->gfn == gfn)
601 return p;
602 }
603 return NULL;
604}
605
606static inline int init_shadow_page(struct intel_vgpu *vgpu,
607 struct intel_vgpu_shadow_page *p, int type)
608{
5de6bd4c
CD		 609 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
610 dma_addr_t daddr;
611
612 daddr = dma_map_page(kdev, p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
613 if (dma_mapping_error(kdev, daddr)) {
695fbc08 614 gvt_vgpu_err("fail to map dma addr\n");
5de6bd4c
CD		 615 return -EINVAL;
616 }
617
2707e444
ZW		 618 p->vaddr = page_address(p->page);
619 p->type = type;
620
621 INIT_HLIST_NODE(&p->node);
622
5de6bd4c 623 p->mfn = daddr >> GTT_PAGE_SHIFT;
2707e444
ZW		 624 hash_add(vgpu->gtt.shadow_page_hash_table, &p->node, p->mfn);
625 return 0;
626}
627
5de6bd4c
CD		 628static inline void clean_shadow_page(struct intel_vgpu *vgpu,
629 struct intel_vgpu_shadow_page *p)
2707e444 630{
5de6bd4c
CD		 631 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
632
633 dma_unmap_page(kdev, p->mfn << GTT_PAGE_SHIFT, 4096,
634 PCI_DMA_BIDIRECTIONAL);
635
2707e444
ZW		 636 if (!hlist_unhashed(&p->node))
637 hash_del(&p->node);
638}
639
640static inline struct intel_vgpu_shadow_page *find_shadow_page(
641 struct intel_vgpu *vgpu, unsigned long mfn)
642{
643 struct intel_vgpu_shadow_page *p;
644
645 hash_for_each_possible(vgpu->gtt.shadow_page_hash_table,
646 p, node, mfn) {
647 if (p->mfn == mfn)
648 return p;
649 }
650 return NULL;
651}
652
653#define guest_page_to_ppgtt_spt(ptr) \
654 container_of(ptr, struct intel_vgpu_ppgtt_spt, guest_page)
655
656#define shadow_page_to_ppgtt_spt(ptr) \
657 container_of(ptr, struct intel_vgpu_ppgtt_spt, shadow_page)
658
659static void *alloc_spt(gfp_t gfp_mask)
660{
661 struct intel_vgpu_ppgtt_spt *spt;
662
663 spt = kzalloc(sizeof(*spt), gfp_mask);
664 if (!spt)
665 return NULL;
666
667 spt->shadow_page.page = alloc_page(gfp_mask);
668 if (!spt->shadow_page.page) {
669 kfree(spt);
670 return NULL;
671 }
672 return spt;
673}
674
675static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
676{
677 __free_page(spt->shadow_page.page);
678 kfree(spt);
679}
680
681static void ppgtt_free_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
682{
683 trace_spt_free(spt->vgpu->id, spt, spt->shadow_page.type);
684
5de6bd4c 685 clean_shadow_page(spt->vgpu, &spt->shadow_page);
2707e444
ZW		 686 intel_vgpu_clean_guest_page(spt->vgpu, &spt->guest_page);
687 list_del_init(&spt->post_shadow_list);
688
689 free_spt(spt);
690}
691
692static void ppgtt_free_all_shadow_page(struct intel_vgpu *vgpu)
693{
694 struct hlist_node *n;
695 struct intel_vgpu_shadow_page *sp;
696 int i;
697
698 hash_for_each_safe(vgpu->gtt.shadow_page_hash_table, i, n, sp, node)
699 ppgtt_free_shadow_page(shadow_page_to_ppgtt_spt(sp));
700}
701
702static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
703 u64 pa, void *p_data, int bytes);
704
705static int ppgtt_write_protection_handler(void *gp, u64 pa,
706 void *p_data, int bytes)
707{
708 struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp;
709 int ret;
710
711 if (bytes != 4 && bytes != 8)
712 return -EINVAL;
713
714 if (!gpt->writeprotection)
715 return -EINVAL;
716
717 ret = ppgtt_handle_guest_write_page_table_bytes(gp,
718 pa, p_data, bytes);
719 if (ret)
720 return ret;
721 return ret;
722}
723
724static int reclaim_one_mm(struct intel_gvt *gvt);
725
726static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_shadow_page(
727 struct intel_vgpu *vgpu, int type, unsigned long gfn)
728{
729 struct intel_vgpu_ppgtt_spt *spt = NULL;
730 int ret;
731
732retry:
733 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
734 if (!spt) {
735 if (reclaim_one_mm(vgpu->gvt))
736 goto retry;
737
695fbc08 738 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
2707e444
ZW		 739 return ERR_PTR(-ENOMEM);
740 }
741
742 spt->vgpu = vgpu;
743 spt->guest_page_type = type;
744 atomic_set(&spt->refcount, 1);
745 INIT_LIST_HEAD(&spt->post_shadow_list);
746
747 /*
748 * TODO: guest page type may be different with shadow page type,
749 * when we support PSE page in future.
750 */
751 ret = init_shadow_page(vgpu, &spt->shadow_page, type);
752 if (ret) {
695fbc08 753 gvt_vgpu_err("fail to initialize shadow page for spt\n");
2707e444
ZW		 754 goto err;
755 }
756
757 ret = intel_vgpu_init_guest_page(vgpu, &spt->guest_page,
758 gfn, ppgtt_write_protection_handler, NULL);
759 if (ret) {
695fbc08 760 gvt_vgpu_err("fail to initialize guest page for spt\n");
2707e444
ZW		 761 goto err;
762 }
763
764 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
765 return spt;
766err:
767 ppgtt_free_shadow_page(spt);
768 return ERR_PTR(ret);
769}
770
771static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page(
772 struct intel_vgpu *vgpu, unsigned long mfn)
773{
774 struct intel_vgpu_shadow_page *p = find_shadow_page(vgpu, mfn);
775
776 if (p)
777 return shadow_page_to_ppgtt_spt(p);
778
695fbc08 779 gvt_vgpu_err("fail to find ppgtt shadow page: 0x%lx\n", mfn);
2707e444
ZW		 780 return NULL;
781}
782
783#define pt_entry_size_shift(spt) \
784 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
785
786#define pt_entries(spt) \
787 (GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
788
789#define for_each_present_guest_entry(spt, e, i) \
790 for (i = 0; i < pt_entries(spt); i++) \
791 if (spt->vgpu->gvt->gtt.pte_ops->test_present( \
792 ppgtt_get_guest_entry(spt, e, i)))
793
794#define for_each_present_shadow_entry(spt, e, i) \
795 for (i = 0; i < pt_entries(spt); i++) \
796 if (spt->vgpu->gvt->gtt.pte_ops->test_present( \
797 ppgtt_get_shadow_entry(spt, e, i)))
798
799static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
800{
801 int v = atomic_read(&spt->refcount);
802
803 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
804
805 atomic_inc(&spt->refcount);
806}
807
808static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);
809
810static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu *vgpu,
811 struct intel_gvt_gtt_entry *e)
812{
813 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
814 struct intel_vgpu_ppgtt_spt *s;
3b6411c2 815 intel_gvt_gtt_type_t cur_pt_type;
2707e444
ZW		 816
817 if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(e->type))))
818 return -EINVAL;
819
3b6411c2
PG		 820 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
821 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
822 cur_pt_type = get_next_pt_type(e->type) + 1;
823 if (ops->get_pfn(e) ==
824 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
825 return 0;
826 }
2707e444
ZW		 827 s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
828 if (!s) {
695fbc08
TZ		 829 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
830 ops->get_pfn(e));
2707e444
ZW		 831 return -ENXIO;
832 }
833 return ppgtt_invalidate_shadow_page(s);
834}
835
836static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
837{
695fbc08 838 struct intel_vgpu *vgpu = spt->vgpu;
2707e444
ZW		 839 struct intel_gvt_gtt_entry e;
840 unsigned long index;
841 int ret;
842 int v = atomic_read(&spt->refcount);
843
844 trace_spt_change(spt->vgpu->id, "die", spt,
845 spt->guest_page.gfn, spt->shadow_page.type);
846
847 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
848
849 if (atomic_dec_return(&spt->refcount) > 0)
850 return 0;
851
852 if (gtt_type_is_pte_pt(spt->shadow_page.type))
853 goto release;
854
855 for_each_present_shadow_entry(spt, &e, index) {
856 if (!gtt_type_is_pt(get_next_pt_type(e.type))) {
695fbc08 857 gvt_vgpu_err("GVT doesn't support pse bit for now\n");
2707e444
ZW		 858 return -EINVAL;
859 }
860 ret = ppgtt_invalidate_shadow_page_by_shadow_entry(
861 spt->vgpu, &e);
862 if (ret)
863 goto fail;
864 }
865release:
866 trace_spt_change(spt->vgpu->id, "release", spt,
867 spt->guest_page.gfn, spt->shadow_page.type);
868 ppgtt_free_shadow_page(spt);
869 return 0;
870fail:
695fbc08
TZ		 871 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
872 spt, e.val64, e.type);
2707e444
ZW		 873 return ret;
874}
875
876static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt);
877
878static struct intel_vgpu_ppgtt_spt *ppgtt_populate_shadow_page_by_guest_entry(
879 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
880{
881 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
882 struct intel_vgpu_ppgtt_spt *s = NULL;
883 struct intel_vgpu_guest_page *g;
884 int ret;
885
886 if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(we->type)))) {
887 ret = -EINVAL;
888 goto fail;
889 }
890
891 g = intel_vgpu_find_guest_page(vgpu, ops->get_pfn(we));
892 if (g) {
893 s = guest_page_to_ppgtt_spt(g);
894 ppgtt_get_shadow_page(s);
895 } else {
896 int type = get_next_pt_type(we->type);
897
898 s = ppgtt_alloc_shadow_page(vgpu, type, ops->get_pfn(we));
899 if (IS_ERR(s)) {
900 ret = PTR_ERR(s);
901 goto fail;
902 }
903
904 ret = intel_gvt_hypervisor_set_wp_page(vgpu, &s->guest_page);
905 if (ret)
906 goto fail;
907
908 ret = ppgtt_populate_shadow_page(s);
909 if (ret)
910 goto fail;
911
912 trace_spt_change(vgpu->id, "new", s, s->guest_page.gfn,
913 s->shadow_page.type);
914 }
915 return s;
916fail:
695fbc08
TZ		 917 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
918 s, we->val64, we->type);
2707e444
ZW		 919 return ERR_PTR(ret);
920}
921
922static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
923 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
924{
925 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
926
927 se->type = ge->type;
928 se->val64 = ge->val64;
929
930 ops->set_pfn(se, s->shadow_page.mfn);
931}
932
933static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
934{
935 struct intel_vgpu *vgpu = spt->vgpu;
936 struct intel_vgpu_ppgtt_spt *s;
937 struct intel_gvt_gtt_entry se, ge;
938 unsigned long i;
939 int ret;
940
941 trace_spt_change(spt->vgpu->id, "born", spt,
942 spt->guest_page.gfn, spt->shadow_page.type);
943
944 if (gtt_type_is_pte_pt(spt->shadow_page.type)) {
945 for_each_present_guest_entry(spt, &ge, i) {
946 ret = gtt_entry_p2m(vgpu, &ge, &se);
947 if (ret)
948 goto fail;
949 ppgtt_set_shadow_entry(spt, &se, i);
950 }
951 return 0;
952 }
953
954 for_each_present_guest_entry(spt, &ge, i) {
955 if (!gtt_type_is_pt(get_next_pt_type(ge.type))) {
695fbc08 956 gvt_vgpu_err("GVT doesn't support pse bit now\n");
2707e444
ZW		 957 ret = -EINVAL;
958 goto fail;
959 }
960
961 s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge);
962 if (IS_ERR(s)) {
963 ret = PTR_ERR(s);
964 goto fail;
965 }
966 ppgtt_get_shadow_entry(spt, &se, i);
967 ppgtt_generate_shadow_entry(&se, s, &ge);
968 ppgtt_set_shadow_entry(spt, &se, i);
969 }
970 return 0;
971fail:
695fbc08
TZ		 972 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
973 spt, ge.val64, ge.type);
2707e444
ZW		 974 return ret;
975}
976
977static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt,
9baf0920 978 unsigned long index)
2707e444
ZW		 979{
980 struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
981 struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
982 struct intel_vgpu *vgpu = spt->vgpu;
983 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
984 struct intel_gvt_gtt_entry e;
985 int ret;
986
2707e444 987 ppgtt_get_shadow_entry(spt, &e, index);
9baf0920
BN		 988
989 trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64,
990 index);
991
2707e444
ZW		 992 if (!ops->test_present(&e))
993 return 0;
994
3b6411c2 995 if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn)
2707e444
ZW		 996 return 0;
997
9baf0920
BN		 998 if (gtt_type_is_pt(get_next_pt_type(e.type))) {
999 struct intel_vgpu_ppgtt_spt *s =
1000 ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e));
1001 if (!s) {
695fbc08 1002 gvt_vgpu_err("fail to find guest page\n");
2707e444
ZW		 1003 ret = -ENXIO;
1004 goto fail;
1005 }
9baf0920 1006 ret = ppgtt_invalidate_shadow_page(s);
2707e444
ZW		 1007 if (ret)
1008 goto fail;
1009 }
3b6411c2 1010 ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn);
2707e444
ZW		 1011 ppgtt_set_shadow_entry(spt, &e, index);
1012 return 0;
1013fail:
695fbc08
TZ		 1014 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1015 spt, e.val64, e.type);
2707e444
ZW		 1016 return ret;
1017}
1018
1019static int ppgtt_handle_guest_entry_add(struct intel_vgpu_guest_page *gpt,
1020 struct intel_gvt_gtt_entry *we, unsigned long index)
1021{
1022 struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
1023 struct intel_vgpu_shadow_page *sp = &spt->shadow_page;
1024 struct intel_vgpu *vgpu = spt->vgpu;
1025 struct intel_gvt_gtt_entry m;
1026 struct intel_vgpu_ppgtt_spt *s;
1027 int ret;
1028
1029 trace_gpt_change(spt->vgpu->id, "add", spt, sp->type,
1030 we->val64, index);
1031
1032 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
1033 s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, we);
1034 if (IS_ERR(s)) {
1035 ret = PTR_ERR(s);
1036 goto fail;
1037 }
1038 ppgtt_get_shadow_entry(spt, &m, index);
1039 ppgtt_generate_shadow_entry(&m, s, we);
1040 ppgtt_set_shadow_entry(spt, &m, index);
1041 } else {
1042 ret = gtt_entry_p2m(vgpu, we, &m);
1043 if (ret)
1044 goto fail;
1045 ppgtt_set_shadow_entry(spt, &m, index);
1046 }
1047 return 0;
1048fail:
695fbc08
TZ		 1049 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1050 spt, we->val64, we->type);
2707e444
ZW		 1051 return ret;
1052}
1053
1054static int sync_oos_page(struct intel_vgpu *vgpu,
1055 struct intel_vgpu_oos_page *oos_page)
1056{
1057 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1058 struct intel_gvt *gvt = vgpu->gvt;
1059 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1060 struct intel_vgpu_ppgtt_spt *spt =
1061 guest_page_to_ppgtt_spt(oos_page->guest_page);
1062 struct intel_gvt_gtt_entry old, new, m;
1063 int index;
1064 int ret;
1065
1066 trace_oos_change(vgpu->id, "sync", oos_page->id,
1067 oos_page->guest_page, spt->guest_page_type);
1068
1069 old.type = new.type = get_entry_type(spt->guest_page_type);
1070 old.val64 = new.val64 = 0;
1071
1072 for (index = 0; index < (GTT_PAGE_SIZE >> info->gtt_entry_size_shift);
1073 index++) {
1074 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1075 ops->get_entry(NULL, &new, index, true,
1076 oos_page->guest_page->gfn << PAGE_SHIFT, vgpu);
1077
1078 if (old.val64 == new.val64
1079 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1080 continue;
1081
1082 trace_oos_sync(vgpu->id, oos_page->id,
1083 oos_page->guest_page, spt->guest_page_type,
1084 new.val64, index);
1085
1086 ret = gtt_entry_p2m(vgpu, &new, &m);
1087 if (ret)
1088 return ret;
1089
1090 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1091 ppgtt_set_shadow_entry(spt, &m, index);
1092 }
1093
1094 oos_page->guest_page->write_cnt = 0;
1095 list_del_init(&spt->post_shadow_list);
1096 return 0;
1097}
1098
1099static int detach_oos_page(struct intel_vgpu *vgpu,
1100 struct intel_vgpu_oos_page *oos_page)
1101{
1102 struct intel_gvt *gvt = vgpu->gvt;
1103 struct intel_vgpu_ppgtt_spt *spt =
1104 guest_page_to_ppgtt_spt(oos_page->guest_page);
1105
1106 trace_oos_change(vgpu->id, "detach", oos_page->id,
1107 oos_page->guest_page, spt->guest_page_type);
1108
1109 oos_page->guest_page->write_cnt = 0;
1110 oos_page->guest_page->oos_page = NULL;
1111 oos_page->guest_page = NULL;
1112
1113 list_del_init(&oos_page->vm_list);
1114 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1115
1116 return 0;
1117}
1118
1119static int attach_oos_page(struct intel_vgpu *vgpu,
1120 struct intel_vgpu_oos_page *oos_page,
1121 struct intel_vgpu_guest_page *gpt)
1122{
1123 struct intel_gvt *gvt = vgpu->gvt;
1124 int ret;
1125
1126 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpt->gfn << GTT_PAGE_SHIFT,
1127 oos_page->mem, GTT_PAGE_SIZE);
1128 if (ret)
1129 return ret;
1130
1131 oos_page->guest_page = gpt;
1132 gpt->oos_page = oos_page;
1133
1134 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1135
1136 trace_oos_change(vgpu->id, "attach", gpt->oos_page->id,
1137 gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
1138 return 0;
1139}
1140
1141static int ppgtt_set_guest_page_sync(struct intel_vgpu *vgpu,
1142 struct intel_vgpu_guest_page *gpt)
1143{
1144 int ret;
1145
1146 ret = intel_gvt_hypervisor_set_wp_page(vgpu, gpt);
1147 if (ret)
1148 return ret;
1149
1150 trace_oos_change(vgpu->id, "set page sync", gpt->oos_page->id,
1151 gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
1152
1153 list_del_init(&gpt->oos_page->vm_list);
1154 return sync_oos_page(vgpu, gpt->oos_page);
1155}
1156
1157static int ppgtt_allocate_oos_page(struct intel_vgpu *vgpu,
1158 struct intel_vgpu_guest_page *gpt)
1159{
1160 struct intel_gvt *gvt = vgpu->gvt;
1161 struct intel_gvt_gtt *gtt = &gvt->gtt;
1162 struct intel_vgpu_oos_page *oos_page = gpt->oos_page;
1163 int ret;
1164
1165 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1166
1167 if (list_empty(&gtt->oos_page_free_list_head)) {
1168 oos_page = container_of(gtt->oos_page_use_list_head.next,
1169 struct intel_vgpu_oos_page, list);
1170 ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page);
1171 if (ret)
1172 return ret;
1173 ret = detach_oos_page(vgpu, oos_page);
1174 if (ret)
1175 return ret;
1176 } else
1177 oos_page = container_of(gtt->oos_page_free_list_head.next,
1178 struct intel_vgpu_oos_page, list);
1179 return attach_oos_page(vgpu, oos_page, gpt);
1180}
1181
1182static int ppgtt_set_guest_page_oos(struct intel_vgpu *vgpu,
1183 struct intel_vgpu_guest_page *gpt)
1184{
1185 struct intel_vgpu_oos_page *oos_page = gpt->oos_page;
1186
1187 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1188 return -EINVAL;
1189
1190 trace_oos_change(vgpu->id, "set page out of sync", gpt->oos_page->id,
1191 gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type);
1192
1193 list_add_tail(&oos_page->vm_list, &vgpu->gtt.oos_page_list_head);
1194 return intel_gvt_hypervisor_unset_wp_page(vgpu, gpt);
1195}
1196
1197/**
1198 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1199 * @vgpu: a vGPU
1200 *
1201 * This function is called before submitting a guest workload to host,
1202 * to sync all the out-of-synced shadow for vGPU
1203 *
1204 * Returns:
1205 * Zero on success, negative error code if failed.
1206 */
1207int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1208{
1209 struct list_head *pos, *n;
1210 struct intel_vgpu_oos_page *oos_page;
1211 int ret;
1212
1213 if (!enable_out_of_sync)
1214 return 0;
1215
1216 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1217 oos_page = container_of(pos,
1218 struct intel_vgpu_oos_page, vm_list);
1219 ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page);
1220 if (ret)
1221 return ret;
1222 }
1223 return 0;
1224}
1225
1226/*
1227 * The heart of PPGTT shadow page table.
1228 */
1229static int ppgtt_handle_guest_write_page_table(
1230 struct intel_vgpu_guest_page *gpt,
1231 struct intel_gvt_gtt_entry *we, unsigned long index)
1232{
1233 struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
1234 struct intel_vgpu *vgpu = spt->vgpu;
1235 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2707e444 1236
2707e444 1237 int ret;
9baf0920 1238 int new_present;
2707e444 1239
2707e444
ZW		 1240 new_present = ops->test_present(we);
1241
9baf0920
BN		 1242 ret = ppgtt_handle_guest_entry_removal(gpt, index);
1243 if (ret)
1244 goto fail;
2707e444 1245
2707e444
ZW		 1246 if (new_present) {
1247 ret = ppgtt_handle_guest_entry_add(gpt, we, index);
1248 if (ret)
1249 goto fail;
1250 }
1251 return 0;
1252fail:
695fbc08
TZ		 1253 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1254 spt, we->val64, we->type);
2707e444
ZW		 1255 return ret;
1256}
1257
1258static inline bool can_do_out_of_sync(struct intel_vgpu_guest_page *gpt)
1259{
1260 return enable_out_of_sync
1261 && gtt_type_is_pte_pt(
1262 guest_page_to_ppgtt_spt(gpt)->guest_page_type)
1263 && gpt->write_cnt >= 2;
1264}
1265
1266static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1267 unsigned long index)
1268{
1269 set_bit(index, spt->post_shadow_bitmap);
1270 if (!list_empty(&spt->post_shadow_list))
1271 return;
1272
1273 list_add_tail(&spt->post_shadow_list,
1274 &spt->vgpu->gtt.post_shadow_list_head);
1275}
1276
1277/**
1278 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1279 * @vgpu: a vGPU
1280 *
1281 * This function is called before submitting a guest workload to host,
1282 * to flush all the post shadows for a vGPU.
1283 *
1284 * Returns:
1285 * Zero on success, negative error code if failed.
1286 */
1287int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1288{
1289 struct list_head *pos, *n;
1290 struct intel_vgpu_ppgtt_spt *spt;
9baf0920 1291 struct intel_gvt_gtt_entry ge;
2707e444
ZW		 1292 unsigned long index;
1293 int ret;
1294
1295 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1296 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1297 post_shadow_list);
1298
1299 for_each_set_bit(index, spt->post_shadow_bitmap,
1300 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1301 ppgtt_get_guest_entry(spt, &ge, index);
2707e444
ZW		 1302
1303 ret = ppgtt_handle_guest_write_page_table(
1304 &spt->guest_page, &ge, index);
1305 if (ret)
1306 return ret;
1307 clear_bit(index, spt->post_shadow_bitmap);
1308 }
1309 list_del_init(&spt->post_shadow_list);
1310 }
1311 return 0;
1312}
1313
1314static int ppgtt_handle_guest_write_page_table_bytes(void *gp,
1315 u64 pa, void *p_data, int bytes)
1316{
1317 struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp;
1318 struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt);
1319 struct intel_vgpu *vgpu = spt->vgpu;
1320 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1321 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1322 struct intel_gvt_gtt_entry we;
1323 unsigned long index;
1324 int ret;
1325
1326 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1327
1328 ppgtt_get_guest_entry(spt, &we, index);
2707e444
ZW		 1329
1330 ops->test_pse(&we);
1331
1332 if (bytes == info->gtt_entry_size) {
1333 ret = ppgtt_handle_guest_write_page_table(gpt, &we, index);
1334 if (ret)
1335 return ret;
1336 } else {
2707e444 1337 if (!test_bit(index, spt->post_shadow_bitmap)) {
9baf0920 1338 ret = ppgtt_handle_guest_entry_removal(gpt, index);
2707e444
ZW		 1339 if (ret)
1340 return ret;
1341 }
1342
1343 ppgtt_set_post_shadow(spt, index);
2707e444
ZW		 1344 }
1345
1346 if (!enable_out_of_sync)
1347 return 0;
1348
1349 gpt->write_cnt++;
1350
1351 if (gpt->oos_page)
1352 ops->set_entry(gpt->oos_page->mem, &we, index,
1353 false, 0, vgpu);
1354
1355 if (can_do_out_of_sync(gpt)) {
1356 if (!gpt->oos_page)
1357 ppgtt_allocate_oos_page(vgpu, gpt);
1358
1359 ret = ppgtt_set_guest_page_oos(vgpu, gpt);
1360 if (ret < 0)
1361 return ret;
1362 }
1363 return 0;
1364}
1365
1366/*
1367 * mm page table allocation policy for bdw+
1368 * - for ggtt, only virtual page table will be allocated.
1369 * - for ppgtt, dedicated virtual/shadow page table will be allocated.
1370 */
1371static int gen8_mm_alloc_page_table(struct intel_vgpu_mm *mm)
1372{
1373 struct intel_vgpu *vgpu = mm->vgpu;
1374 struct intel_gvt *gvt = vgpu->gvt;
1375 const struct intel_gvt_device_info *info = &gvt->device_info;
1376 void *mem;
1377
1378 if (mm->type == INTEL_GVT_MM_PPGTT) {
1379 mm->page_table_entry_cnt = 4;
1380 mm->page_table_entry_size = mm->page_table_entry_cnt *
1381 info->gtt_entry_size;
1382 mem = kzalloc(mm->has_shadow_page_table ?
1383 mm->page_table_entry_size * 2
9631739f 1384 : mm->page_table_entry_size, GFP_KERNEL);
2707e444
ZW		 1385 if (!mem)
1386 return -ENOMEM;
1387 mm->virtual_page_table = mem;
1388 if (!mm->has_shadow_page_table)
1389 return 0;
1390 mm->shadow_page_table = mem + mm->page_table_entry_size;
1391 } else if (mm->type == INTEL_GVT_MM_GGTT) {
1392 mm->page_table_entry_cnt =
1393 (gvt_ggtt_gm_sz(gvt) >> GTT_PAGE_SHIFT);
1394 mm->page_table_entry_size = mm->page_table_entry_cnt *
1395 info->gtt_entry_size;
1396 mem = vzalloc(mm->page_table_entry_size);
1397 if (!mem)
1398 return -ENOMEM;
1399 mm->virtual_page_table = mem;
1400 }
1401 return 0;
1402}
1403
1404static void gen8_mm_free_page_table(struct intel_vgpu_mm *mm)
1405{
1406 if (mm->type == INTEL_GVT_MM_PPGTT) {
1407 kfree(mm->virtual_page_table);
1408 } else if (mm->type == INTEL_GVT_MM_GGTT) {
1409 if (mm->virtual_page_table)
1410 vfree(mm->virtual_page_table);
1411 }
1412 mm->virtual_page_table = mm->shadow_page_table = NULL;
1413}
1414
1415static void invalidate_mm(struct intel_vgpu_mm *mm)
1416{
1417 struct intel_vgpu *vgpu = mm->vgpu;
1418 struct intel_gvt *gvt = vgpu->gvt;
1419 struct intel_gvt_gtt *gtt = &gvt->gtt;
1420 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1421 struct intel_gvt_gtt_entry se;
1422 int i;
1423
1424 if (WARN_ON(!mm->has_shadow_page_table || !mm->shadowed))
1425 return;
1426
1427 for (i = 0; i < mm->page_table_entry_cnt; i++) {
1428 ppgtt_get_shadow_root_entry(mm, &se, i);
1429 if (!ops->test_present(&se))
1430 continue;
1431 ppgtt_invalidate_shadow_page_by_shadow_entry(
1432 vgpu, &se);
1433 se.val64 = 0;
1434 ppgtt_set_shadow_root_entry(mm, &se, i);
1435
1436 trace_gpt_change(vgpu->id, "destroy root pointer",
1437 NULL, se.type, se.val64, i);
1438 }
1439 mm->shadowed = false;
1440}
1441
1442/**
1443 * intel_vgpu_destroy_mm - destroy a mm object
1444 * @mm: a kref object
1445 *
1446 * This function is used to destroy a mm object for vGPU
1447 *
1448 */
1449void intel_vgpu_destroy_mm(struct kref *mm_ref)
1450{
1451 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1452 struct intel_vgpu *vgpu = mm->vgpu;
1453 struct intel_gvt *gvt = vgpu->gvt;
1454 struct intel_gvt_gtt *gtt = &gvt->gtt;
1455
1456 if (!mm->initialized)
1457 goto out;
1458
1459 list_del(&mm->list);
1460 list_del(&mm->lru_list);
1461
1462 if (mm->has_shadow_page_table)
1463 invalidate_mm(mm);
1464
1465 gtt->mm_free_page_table(mm);
1466out:
1467 kfree(mm);
1468}
1469
1470static int shadow_mm(struct intel_vgpu_mm *mm)
1471{
1472 struct intel_vgpu *vgpu = mm->vgpu;
1473 struct intel_gvt *gvt = vgpu->gvt;
1474 struct intel_gvt_gtt *gtt = &gvt->gtt;
1475 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1476 struct intel_vgpu_ppgtt_spt *spt;
1477 struct intel_gvt_gtt_entry ge, se;
1478 int i;
1479 int ret;
1480
1481 if (WARN_ON(!mm->has_shadow_page_table || mm->shadowed))
1482 return 0;
1483
1484 mm->shadowed = true;
1485
1486 for (i = 0; i < mm->page_table_entry_cnt; i++) {
1487 ppgtt_get_guest_root_entry(mm, &ge, i);
1488 if (!ops->test_present(&ge))
1489 continue;
1490
1491 trace_gpt_change(vgpu->id, __func__, NULL,
1492 ge.type, ge.val64, i);
1493
1494 spt = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge);
1495 if (IS_ERR(spt)) {
695fbc08 1496 gvt_vgpu_err("fail to populate guest root pointer\n");
2707e444
ZW		 1497 ret = PTR_ERR(spt);
1498 goto fail;
1499 }
1500 ppgtt_generate_shadow_entry(&se, spt, &ge);
1501 ppgtt_set_shadow_root_entry(mm, &se, i);
1502
1503 trace_gpt_change(vgpu->id, "populate root pointer",
1504 NULL, se.type, se.val64, i);
1505 }
1506 return 0;
1507fail:
1508 invalidate_mm(mm);
1509 return ret;
1510}
1511
1512/**
1513 * intel_vgpu_create_mm - create a mm object for a vGPU
1514 * @vgpu: a vGPU
1515 * @mm_type: mm object type, should be PPGTT or GGTT
1516 * @virtual_page_table: page table root pointers. Could be NULL if user wants
1517 * to populate shadow later.
1518 * @page_table_level: describe the page table level of the mm object
1519 * @pde_base_index: pde root pointer base in GGTT MMIO.
1520 *
1521 * This function is used to create a mm object for a vGPU.
1522 *
1523 * Returns:
1524 * Zero on success, negative error code in pointer if failed.
1525 */
1526struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu,
1527 int mm_type, void *virtual_page_table, int page_table_level,
1528 u32 pde_base_index)
1529{
1530 struct intel_gvt *gvt = vgpu->gvt;
1531 struct intel_gvt_gtt *gtt = &gvt->gtt;
1532 struct intel_vgpu_mm *mm;
1533 int ret;
1534
9631739f 1535 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
2707e444
ZW		 1536 if (!mm) {
1537 ret = -ENOMEM;
1538 goto fail;
1539 }
1540
1541 mm->type = mm_type;
1542
1543 if (page_table_level == 1)
1544 mm->page_table_entry_type = GTT_TYPE_GGTT_PTE;
1545 else if (page_table_level == 3)
1546 mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1547 else if (page_table_level == 4)
1548 mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1549 else {
1550 WARN_ON(1);
1551 ret = -EINVAL;
1552 goto fail;
1553 }
1554
1555 mm->page_table_level = page_table_level;
1556 mm->pde_base_index = pde_base_index;
1557
1558 mm->vgpu = vgpu;
1559 mm->has_shadow_page_table = !!(mm_type == INTEL_GVT_MM_PPGTT);
1560
1561 kref_init(&mm->ref);
1562 atomic_set(&mm->pincount, 0);
1563 INIT_LIST_HEAD(&mm->list);
1564 INIT_LIST_HEAD(&mm->lru_list);
1565 list_add_tail(&mm->list, &vgpu->gtt.mm_list_head);
1566
1567 ret = gtt->mm_alloc_page_table(mm);
1568 if (ret) {
695fbc08 1569 gvt_vgpu_err("fail to allocate page table for mm\n");
2707e444
ZW		 1570 goto fail;
1571 }
1572
1573 mm->initialized = true;
1574
1575 if (virtual_page_table)
1576 memcpy(mm->virtual_page_table, virtual_page_table,
1577 mm->page_table_entry_size);
1578
1579 if (mm->has_shadow_page_table) {
1580 ret = shadow_mm(mm);
1581 if (ret)
1582 goto fail;
1583 list_add_tail(&mm->lru_list, &gvt->gtt.mm_lru_list_head);
1584 }
1585 return mm;
1586fail:
695fbc08 1587 gvt_vgpu_err("fail to create mm\n");
2707e444
ZW		 1588 if (mm)
1589 intel_gvt_mm_unreference(mm);
1590 return ERR_PTR(ret);
1591}
1592
1593/**
1594 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1595 * @mm: a vGPU mm object
1596 *
1597 * This function is called when user doesn't want to use a vGPU mm object
1598 */
1599void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1600{
1601 if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
1602 return;
1603
1604 atomic_dec(&mm->pincount);
1605}
1606
1607/**
1608 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1609 * @vgpu: a vGPU
1610 *
1611 * This function is called when user wants to use a vGPU mm object. If this
1612 * mm object hasn't been shadowed yet, the shadow will be populated at this
1613 * time.
1614 *
1615 * Returns:
1616 * Zero on success, negative error code if failed.
1617 */
1618int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1619{
1620 int ret;
1621
1622 if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
1623 return 0;
1624
1625 atomic_inc(&mm->pincount);
1626
1627 if (!mm->shadowed) {
1628 ret = shadow_mm(mm);
1629 if (ret)
1630 return ret;
1631 }
1632
1633 list_del_init(&mm->lru_list);
1634 list_add_tail(&mm->lru_list, &mm->vgpu->gvt->gtt.mm_lru_list_head);
1635 return 0;
1636}
1637
1638static int reclaim_one_mm(struct intel_gvt *gvt)
1639{
1640 struct intel_vgpu_mm *mm;
1641 struct list_head *pos, *n;
1642
1643 list_for_each_safe(pos, n, &gvt->gtt.mm_lru_list_head) {
1644 mm = container_of(pos, struct intel_vgpu_mm, lru_list);
1645
1646 if (mm->type != INTEL_GVT_MM_PPGTT)
1647 continue;
1648 if (atomic_read(&mm->pincount))
1649 continue;
1650
1651 list_del_init(&mm->lru_list);
1652 invalidate_mm(mm);
1653 return 1;
1654 }
1655 return 0;
1656}
1657
1658/*
1659 * GMA translation APIs.
1660 */
1661static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
1662 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
1663{
1664 struct intel_vgpu *vgpu = mm->vgpu;
1665 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1666 struct intel_vgpu_ppgtt_spt *s;
1667
1668 if (WARN_ON(!mm->has_shadow_page_table))
1669 return -EINVAL;
1670
1671 s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e));
1672 if (!s)
1673 return -ENXIO;
1674
1675 if (!guest)
1676 ppgtt_get_shadow_entry(s, e, index);
1677 else
1678 ppgtt_get_guest_entry(s, e, index);
1679 return 0;
1680}
1681
1682/**
1683 * intel_vgpu_gma_to_gpa - translate a gma to GPA
1684 * @mm: mm object. could be a PPGTT or GGTT mm object
1685 * @gma: graphics memory address in this mm object
1686 *
1687 * This function is used to translate a graphics memory address in specific
1688 * graphics memory space to guest physical address.
1689 *
1690 * Returns:
1691 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
1692 */
1693unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
1694{
1695 struct intel_vgpu *vgpu = mm->vgpu;
1696 struct intel_gvt *gvt = vgpu->gvt;
1697 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
1698 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
1699 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
1700 unsigned long gma_index[4];
1701 struct intel_gvt_gtt_entry e;
1702 int i, index;
1703 int ret;
1704
1705 if (mm->type != INTEL_GVT_MM_GGTT && mm->type != INTEL_GVT_MM_PPGTT)
1706 return INTEL_GVT_INVALID_ADDR;
1707
1708 if (mm->type == INTEL_GVT_MM_GGTT) {
1709 if (!vgpu_gmadr_is_valid(vgpu, gma))
1710 goto err;
1711
1712 ggtt_get_guest_entry(mm, &e,
1713 gma_ops->gma_to_ggtt_pte_index(gma));
1714 gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT)
1715 + (gma & ~GTT_PAGE_MASK);
1716
1717 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
1718 return gpa;
1719 }
1720
1721 switch (mm->page_table_level) {
1722 case 4:
1723 ppgtt_get_shadow_root_entry(mm, &e, 0);
1724 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
1725 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
1726 gma_index[2] = gma_ops->gma_to_pde_index(gma);
1727 gma_index[3] = gma_ops->gma_to_pte_index(gma);
1728 index = 4;
1729 break;
1730 case 3:
1731 ppgtt_get_shadow_root_entry(mm, &e,
1732 gma_ops->gma_to_l3_pdp_index(gma));
1733 gma_index[0] = gma_ops->gma_to_pde_index(gma);
1734 gma_index[1] = gma_ops->gma_to_pte_index(gma);
1735 index = 2;
1736 break;
1737 case 2:
1738 ppgtt_get_shadow_root_entry(mm, &e,
1739 gma_ops->gma_to_pde_index(gma));
1740 gma_index[0] = gma_ops->gma_to_pte_index(gma);
1741 index = 1;
1742 break;
1743 default:
1744 WARN_ON(1);
1745 goto err;
1746 }
1747
1748 /* walk into the shadow page table and get gpa from guest entry */
1749 for (i = 0; i < index; i++) {
1750 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
1751 (i == index - 1));
1752 if (ret)
1753 goto err;
1754 }
1755
1756 gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT)
1757 + (gma & ~GTT_PAGE_MASK);
1758
1759 trace_gma_translate(vgpu->id, "ppgtt", 0,
1760 mm->page_table_level, gma, gpa);
1761 return gpa;
1762err:
695fbc08 1763 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2707e444
ZW		 1764 return INTEL_GVT_INVALID_ADDR;
1765}
1766
1767static int emulate_gtt_mmio_read(struct intel_vgpu *vgpu,
1768 unsigned int off, void *p_data, unsigned int bytes)
1769{
1770 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1771 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1772 unsigned long index = off >> info->gtt_entry_size_shift;
1773 struct intel_gvt_gtt_entry e;
1774
1775 if (bytes != 4 && bytes != 8)
1776 return -EINVAL;
1777
1778 ggtt_get_guest_entry(ggtt_mm, &e, index);
1779 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
1780 bytes);
1781 return 0;
1782}
1783
1784/**
1785 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
1786 * @vgpu: a vGPU
1787 * @off: register offset
1788 * @p_data: data will be returned to guest
1789 * @bytes: data length
1790 *
1791 * This function is used to emulate the GTT MMIO register read
1792 *
1793 * Returns:
1794 * Zero on success, error code if failed.
1795 */
1796int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
1797 void *p_data, unsigned int bytes)
1798{
1799 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1800 int ret;
1801
1802 if (bytes != 4 && bytes != 8)
1803 return -EINVAL;
1804
1805 off -= info->gtt_start_offset;
1806 ret = emulate_gtt_mmio_read(vgpu, off, p_data, bytes);
1807 return ret;
1808}
1809
1810static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
1811 void *p_data, unsigned int bytes)
1812{
1813 struct intel_gvt *gvt = vgpu->gvt;
1814 const struct intel_gvt_device_info *info = &gvt->device_info;
1815 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1816 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1817 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
1818 unsigned long gma;
1819 struct intel_gvt_gtt_entry e, m;
1820 int ret;
1821
1822 if (bytes != 4 && bytes != 8)
1823 return -EINVAL;
1824
1825 gma = g_gtt_index << GTT_PAGE_SHIFT;
1826
1827 /* the VM may configure the whole GM space when ballooning is used */
7c28135c 1828 if (!vgpu_gmadr_is_valid(vgpu, gma))
2707e444 1829 return 0;
2707e444
ZW		 1830
1831 ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
1832
1833 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
1834 bytes);
1835
1836 if (ops->test_present(&e)) {
1837 ret = gtt_entry_p2m(vgpu, &e, &m);
1838 if (ret) {
695fbc08 1839 gvt_vgpu_err("fail to translate guest gtt entry\n");
2707e444
ZW		 1840 return ret;
1841 }
1842 } else {
1843 m = e;
1844 m.val64 = 0;
1845 }
1846
1847 ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);
1848 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
1849 return 0;
1850}
1851
1852/*
1853 * intel_vgpu_emulate_gtt_mmio_write - emulate GTT MMIO register write
1854 * @vgpu: a vGPU
1855 * @off: register offset
1856 * @p_data: data from guest write
1857 * @bytes: data length
1858 *
1859 * This function is used to emulate the GTT MMIO register write
1860 *
1861 * Returns:
1862 * Zero on success, error code if failed.
1863 */
1864int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
1865 void *p_data, unsigned int bytes)
1866{
1867 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1868 int ret;
1869
1870 if (bytes != 4 && bytes != 8)
1871 return -EINVAL;
1872
1873 off -= info->gtt_start_offset;
1874 ret = emulate_gtt_mmio_write(vgpu, off, p_data, bytes);
1875 return ret;
1876}
1877
3b6411c2
PG		 1878static int alloc_scratch_pages(struct intel_vgpu *vgpu,
1879 intel_gvt_gtt_type_t type)
2707e444
ZW		 1880{
1881 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
3b6411c2
PG		 1882 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1883 int page_entry_num = GTT_PAGE_SIZE >>
1884 vgpu->gvt->device_info.gtt_entry_size_shift;
9631739f 1885 void *scratch_pt;
3b6411c2 1886 int i;
5de6bd4c
CD		 1887 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
1888 dma_addr_t daddr;
2707e444 1889
3b6411c2
PG		 1890 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
1891 return -EINVAL;
1892
9631739f 1893 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
3b6411c2 1894 if (!scratch_pt) {
695fbc08 1895 gvt_vgpu_err("fail to allocate scratch page\n");
2707e444
ZW		 1896 return -ENOMEM;
1897 }
1898
5de6bd4c
CD		 1899 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
1900 4096, PCI_DMA_BIDIRECTIONAL);
1901 if (dma_mapping_error(dev, daddr)) {
695fbc08 1902 gvt_vgpu_err("fail to dmamap scratch_pt\n");
5de6bd4c
CD		 1903 __free_page(virt_to_page(scratch_pt));
1904 return -ENOMEM;
3b6411c2 1905 }
5de6bd4c
CD		 1906 gtt->scratch_pt[type].page_mfn =
1907 (unsigned long)(daddr >> GTT_PAGE_SHIFT);
9631739f 1908 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
3b6411c2 1909 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
5de6bd4c 1910 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
3b6411c2
PG		 1911
1912 /* Build the tree by full filled the scratch pt with the entries which
1913 * point to the next level scratch pt or scratch page. The
1914 * scratch_pt[type] indicate the scratch pt/scratch page used by the
1915 * 'type' pt.
1916 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
9631739f 1917 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
3b6411c2
PG		 1918 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
1919 */
1920 if (type > GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) {
1921 struct intel_gvt_gtt_entry se;
1922
1923 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
1924 se.type = get_entry_type(type - 1);
1925 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
1926
1927 /* The entry parameters like present/writeable/cache type
1928 * set to the same as i915's scratch page tree.
1929 */
1930 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
1931 if (type == GTT_TYPE_PPGTT_PDE_PT)
1932 se.val64 |= PPAT_CACHED_INDEX;
1933
1934 for (i = 0; i < page_entry_num; i++)
9631739f 1935 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
3b6411c2
PG		 1936 }
1937
3b6411c2
PG		 1938 return 0;
1939}
2707e444 1940
3b6411c2
PG		 1941static int release_scratch_page_tree(struct intel_vgpu *vgpu)
1942{
1943 int i;
5de6bd4c
CD		 1944 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
1945 dma_addr_t daddr;
3b6411c2
PG		 1946
1947 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
1948 if (vgpu->gtt.scratch_pt[i].page != NULL) {
5de6bd4c
CD		 1949 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
1950 GTT_PAGE_SHIFT);
1951 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
3b6411c2
PG		 1952 __free_page(vgpu->gtt.scratch_pt[i].page);
1953 vgpu->gtt.scratch_pt[i].page = NULL;
1954 vgpu->gtt.scratch_pt[i].page_mfn = 0;
1955 }
2707e444
ZW		 1956 }
1957
2707e444
ZW		 1958 return 0;
1959}
1960
3b6411c2 1961static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2707e444 1962{
3b6411c2
PG		 1963 int i, ret;
1964
1965 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
1966 ret = alloc_scratch_pages(vgpu, i);
1967 if (ret)
1968 goto err;
2707e444 1969 }
3b6411c2
PG		 1970
1971 return 0;
1972
1973err:
1974 release_scratch_page_tree(vgpu);
1975 return ret;
2707e444
ZW		 1976}
1977
1978/**
1979 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
1980 * @vgpu: a vGPU
1981 *
1982 * This function is used to initialize per-vGPU graphics memory virtualization
1983 * components.
1984 *
1985 * Returns:
1986 * Zero on success, error code if failed.
1987 */
1988int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
1989{
1990 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
1991 struct intel_vgpu_mm *ggtt_mm;
1992
1993 hash_init(gtt->guest_page_hash_table);
1994 hash_init(gtt->shadow_page_hash_table);
1995
1996 INIT_LIST_HEAD(&gtt->mm_list_head);
1997 INIT_LIST_HEAD(&gtt->oos_page_list_head);
1998 INIT_LIST_HEAD(&gtt->post_shadow_list_head);
1999
d650ac06
PG		 2000 intel_vgpu_reset_ggtt(vgpu);
2001
2707e444
ZW		 2002 ggtt_mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_GGTT,
2003 NULL, 1, 0);
2004 if (IS_ERR(ggtt_mm)) {
695fbc08 2005 gvt_vgpu_err("fail to create mm for ggtt.\n");
2707e444
ZW		 2006 return PTR_ERR(ggtt_mm);
2007 }
2008
2009 gtt->ggtt_mm = ggtt_mm;
2010
3b6411c2 2011 return create_scratch_page_tree(vgpu);
2707e444
ZW		 2012}
2013
da9cc8de
PG		 2014static void intel_vgpu_free_mm(struct intel_vgpu *vgpu, int type)
2015{
2016 struct list_head *pos, *n;
2017 struct intel_vgpu_mm *mm;
2018
2019 list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) {
2020 mm = container_of(pos, struct intel_vgpu_mm, list);
2021 if (mm->type == type) {
2022 vgpu->gvt->gtt.mm_free_page_table(mm);
2023 list_del(&mm->list);
2024 list_del(&mm->lru_list);
2025 kfree(mm);
2026 }
2027 }
2028}
2029
2707e444
ZW		 2030/**
2031 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2032 * @vgpu: a vGPU
2033 *
2034 * This function is used to clean up per-vGPU graphics memory virtualization
2035 * components.
2036 *
2037 * Returns:
2038 * Zero on success, error code if failed.
2039 */
2040void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2041{
2707e444 2042 ppgtt_free_all_shadow_page(vgpu);
3b6411c2 2043 release_scratch_page_tree(vgpu);
2707e444 2044
da9cc8de
PG		 2045 intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT);
2046 intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_GGTT);
2707e444
ZW		 2047}
2048
2049static void clean_spt_oos(struct intel_gvt *gvt)
2050{
2051 struct intel_gvt_gtt *gtt = &gvt->gtt;
2052 struct list_head *pos, *n;
2053 struct intel_vgpu_oos_page *oos_page;
2054
2055 WARN(!list_empty(&gtt->oos_page_use_list_head),
2056 "someone is still using oos page\n");
2057
2058 list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2059 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2060 list_del(&oos_page->list);
2061 kfree(oos_page);
2062 }
2063}
2064
2065static int setup_spt_oos(struct intel_gvt *gvt)
2066{
2067 struct intel_gvt_gtt *gtt = &gvt->gtt;
2068 struct intel_vgpu_oos_page *oos_page;
2069 int i;
2070 int ret;
2071
2072 INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2073 INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2074
2075 for (i = 0; i < preallocated_oos_pages; i++) {
2076 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2077 if (!oos_page) {
2707e444
ZW		 2078 ret = -ENOMEM;
2079 goto fail;
2080 }
2081
2082 INIT_LIST_HEAD(&oos_page->list);
2083 INIT_LIST_HEAD(&oos_page->vm_list);
2084 oos_page->id = i;
2085 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2086 }
2087
2088 gvt_dbg_mm("%d oos pages preallocated\n", i);
2089
2090 return 0;
2091fail:
2092 clean_spt_oos(gvt);
2093 return ret;
2094}
2095
2096/**
2097 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2098 * @vgpu: a vGPU
2099 * @page_table_level: PPGTT page table level
2100 * @root_entry: PPGTT page table root pointers
2101 *
2102 * This function is used to find a PPGTT mm object from mm object pool
2103 *
2104 * Returns:
2105 * pointer to mm object on success, NULL if failed.
2106 */
2107struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2108 int page_table_level, void *root_entry)
2109{
2110 struct list_head *pos;
2111 struct intel_vgpu_mm *mm;
2112 u64 *src, *dst;
2113
2114 list_for_each(pos, &vgpu->gtt.mm_list_head) {
2115 mm = container_of(pos, struct intel_vgpu_mm, list);
2116 if (mm->type != INTEL_GVT_MM_PPGTT)
2117 continue;
2118
2119 if (mm->page_table_level != page_table_level)
2120 continue;
2121
2122 src = root_entry;
2123 dst = mm->virtual_page_table;
2124
2125 if (page_table_level == 3) {
2126 if (src[0] == dst[0]
2127 && src[1] == dst[1]
2128 && src[2] == dst[2]
2129 && src[3] == dst[3])
2130 return mm;
2131 } else {
2132 if (src[0] == dst[0])
2133 return mm;
2134 }
2135 }
2136 return NULL;
2137}
2138
2139/**
2140 * intel_vgpu_g2v_create_ppgtt_mm - create a PPGTT mm object from
2141 * g2v notification
2142 * @vgpu: a vGPU
2143 * @page_table_level: PPGTT page table level
2144 *
2145 * This function is used to create a PPGTT mm object from a guest to GVT-g
2146 * notification.
2147 *
2148 * Returns:
2149 * Zero on success, negative error code if failed.
2150 */
2151int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu,
2152 int page_table_level)
2153{
2154 u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0]));
2155 struct intel_vgpu_mm *mm;
2156
2157 if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))
2158 return -EINVAL;
2159
2160 mm = intel_vgpu_find_ppgtt_mm(vgpu, page_table_level, pdp);
2161 if (mm) {
2162 intel_gvt_mm_reference(mm);
2163 } else {
2164 mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_PPGTT,
2165 pdp, page_table_level, 0);
2166 if (IS_ERR(mm)) {
695fbc08 2167 gvt_vgpu_err("fail to create mm\n");
2707e444
ZW		 2168 return PTR_ERR(mm);
2169 }
2170 }
2171 return 0;
2172}
2173
2174/**
2175 * intel_vgpu_g2v_destroy_ppgtt_mm - destroy a PPGTT mm object from
2176 * g2v notification
2177 * @vgpu: a vGPU
2178 * @page_table_level: PPGTT page table level
2179 *
2180 * This function is used to create a PPGTT mm object from a guest to GVT-g
2181 * notification.
2182 *
2183 * Returns:
2184 * Zero on success, negative error code if failed.
2185 */
2186int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu,
2187 int page_table_level)
2188{
2189 u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0]));
2190 struct intel_vgpu_mm *mm;
2191
2192 if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))
2193 return -EINVAL;
2194
2195 mm = intel_vgpu_find_ppgtt_mm(vgpu, page_table_level, pdp);
2196 if (!mm) {
695fbc08 2197 gvt_vgpu_err("fail to find ppgtt instance.\n");
2707e444
ZW		 2198 return -EINVAL;
2199 }
2200 intel_gvt_mm_unreference(mm);
2201 return 0;
2202}
2203
2204/**
2205 * intel_gvt_init_gtt - initialize mm components of a GVT device
2206 * @gvt: GVT device
2207 *
2208 * This function is called at the initialization stage, to initialize
2209 * the mm components of a GVT device.
2210 *
2211 * Returns:
2212 * zero on success, negative error code if failed.
2213 */
2214int intel_gvt_init_gtt(struct intel_gvt *gvt)
2215{
2216 int ret;
9631739f 2217 void *page;
5de6bd4c
CD		 2218 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2219 dma_addr_t daddr;
2707e444
ZW		 2220
2221 gvt_dbg_core("init gtt\n");
2222
e3476c00
XH		 2223 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
2224 || IS_KABYLAKE(gvt->dev_priv)) {
2707e444
ZW		 2225 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2226 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2227 gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
2228 gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
2229 } else {
2230 return -ENODEV;
2231 }
2232
9631739f
JS		 2233 page = (void *)get_zeroed_page(GFP_KERNEL);
2234 if (!page) {
d650ac06
PG		 2235 gvt_err("fail to allocate scratch ggtt page\n");
2236 return -ENOMEM;
2237 }
2238
5de6bd4c
CD		 2239 daddr = dma_map_page(dev, virt_to_page(page), 0,
2240 4096, PCI_DMA_BIDIRECTIONAL);
2241 if (dma_mapping_error(dev, daddr)) {
2242 gvt_err("fail to dmamap scratch ggtt page\n");
2243 __free_page(virt_to_page(page));
2244 return -ENOMEM;
d650ac06 2245 }
5de6bd4c
CD		 2246 gvt->gtt.scratch_ggtt_page = virt_to_page(page);
2247 gvt->gtt.scratch_ggtt_mfn = (unsigned long)(daddr >> GTT_PAGE_SHIFT);
d650ac06 2248
2707e444
ZW		 2249 if (enable_out_of_sync) {
2250 ret = setup_spt_oos(gvt);
2251 if (ret) {
2252 gvt_err("fail to initialize SPT oos\n");
2253 return ret;
2254 }
2255 }
2256 INIT_LIST_HEAD(&gvt->gtt.mm_lru_list_head);
2257 return 0;
2258}
2259
2260/**
2261 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2262 * @gvt: GVT device
2263 *
2264 * This function is called at the driver unloading stage, to clean up the
2265 * the mm components of a GVT device.
2266 *
2267 */
2268void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2269{
5de6bd4c
CD		 2270 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2271 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_ggtt_mfn <<
2272 GTT_PAGE_SHIFT);
2273
2274 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2275
d650ac06
PG		 2276 __free_page(gvt->gtt.scratch_ggtt_page);
2277
2707e444
ZW		 2278 if (enable_out_of_sync)
2279 clean_spt_oos(gvt);
2280}
d650ac06
PG		 2281
2282/**
2283 * intel_vgpu_reset_ggtt - reset the GGTT entry
2284 * @vgpu: a vGPU
2285 *
2286 * This function is called at the vGPU create stage
2287 * to reset all the GGTT entries.
2288 *
2289 */
2290void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
2291{
2292 struct intel_gvt *gvt = vgpu->gvt;
5ad59bf0 2293 struct drm_i915_private *dev_priv = gvt->dev_priv;
d650ac06
PG		 2294 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2295 u32 index;
2296 u32 offset;
2297 u32 num_entries;
2298 struct intel_gvt_gtt_entry e;
2299
5ad59bf0
ZW		 2300 intel_runtime_pm_get(dev_priv);
2301
d650ac06
PG		 2302 memset(&e, 0, sizeof(struct intel_gvt_gtt_entry));
2303 e.type = GTT_TYPE_GGTT_PTE;
2304 ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn);
2305 e.val64 |= _PAGE_PRESENT;
2306
2307 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2308 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
2309 for (offset = 0; offset < num_entries; offset++)
2310 ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
2311
2312 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2313 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
2314 for (offset = 0; offset < num_entries; offset++)
2315 ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
5ad59bf0
ZW		 2316
2317 intel_runtime_pm_put(dev_priv);
d650ac06 2318}
b611581b
CD		 2319
2320/**
2321 * intel_vgpu_reset_gtt - reset the all GTT related status
2322 * @vgpu: a vGPU
2323 * @dmlr: true for vGPU Device Model Level Reset, false for GT Reset
2324 *
2325 * This function is called from vfio core to reset reset all
2326 * GTT related status, including GGTT, PPGTT, scratch page.
2327 *
2328 */
2329void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr)
2330{
2331 int i;
2332
2333 ppgtt_free_all_shadow_page(vgpu);
da9cc8de
PG		 2334
2335 /* Shadow pages are only created when there is no page
2336 * table tracking data, so remove page tracking data after
2337 * removing the shadow pages.
2338 */
2339 intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT);
2340
b611581b
CD		 2341 if (!dmlr)
2342 return;
2343
2344 intel_vgpu_reset_ggtt(vgpu);
2345
2346 /* clear scratch page for security */
2347 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2348 if (vgpu->gtt.scratch_pt[i].page != NULL)
2349 memset(page_address(vgpu->gtt.scratch_pt[i].page),
2350 0, PAGE_SIZE);
2351 }
2352}
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