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1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
12d14cc4 ZW |
22 | * |
23 | * Authors: | |
24 | * Kevin Tian <kevin.tian@intel.com> | |
25 | * Eddie Dong <eddie.dong@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Niu Bing <bing.niu@intel.com> | |
29 | * Zhi Wang <zhi.a.wang@intel.com> | |
30 | * | |
0ad35fed ZW |
31 | */ |
32 | ||
33 | #ifndef _GVT_H_ | |
34 | #define _GVT_H_ | |
35 | ||
36 | #include "debug.h" | |
37 | #include "hypercall.h" | |
12d14cc4 | 38 | #include "mmio.h" |
0ad35fed ZW |
39 | |
40 | #define GVT_MAX_VGPU 8 | |
41 | ||
42 | enum { | |
43 | INTEL_GVT_HYPERVISOR_XEN = 0, | |
44 | INTEL_GVT_HYPERVISOR_KVM, | |
45 | }; | |
46 | ||
47 | struct intel_gvt_host { | |
48 | bool initialized; | |
49 | int hypervisor_type; | |
50 | struct intel_gvt_mpt *mpt; | |
51 | }; | |
52 | ||
53 | extern struct intel_gvt_host intel_gvt_host; | |
54 | ||
55 | /* Describe per-platform limitations. */ | |
56 | struct intel_gvt_device_info { | |
57 | u32 max_support_vgpus; | |
12d14cc4 | 58 | u32 mmio_size; |
0ad35fed ZW |
59 | }; |
60 | ||
28a60dee ZW |
61 | /* GM resources owned by a vGPU */ |
62 | struct intel_vgpu_gm { | |
63 | u64 aperture_sz; | |
64 | u64 hidden_sz; | |
65 | struct drm_mm_node low_gm_node; | |
66 | struct drm_mm_node high_gm_node; | |
67 | }; | |
68 | ||
69 | #define INTEL_GVT_MAX_NUM_FENCES 32 | |
70 | ||
71 | /* Fences owned by a vGPU */ | |
72 | struct intel_vgpu_fence { | |
73 | struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; | |
74 | u32 base; | |
75 | u32 size; | |
76 | }; | |
77 | ||
0ad35fed ZW |
78 | struct intel_vgpu { |
79 | struct intel_gvt *gvt; | |
80 | int id; | |
81 | unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ | |
28a60dee ZW |
82 | |
83 | struct intel_vgpu_fence fence; | |
84 | struct intel_vgpu_gm gm; | |
85 | }; | |
86 | ||
87 | struct intel_gvt_gm { | |
88 | unsigned long vgpu_allocated_low_gm_size; | |
89 | unsigned long vgpu_allocated_high_gm_size; | |
90 | }; | |
91 | ||
92 | struct intel_gvt_fence { | |
93 | unsigned long vgpu_allocated_fence_num; | |
0ad35fed ZW |
94 | }; |
95 | ||
12d14cc4 ZW |
96 | #define INTEL_GVT_MMIO_HASH_BITS 9 |
97 | ||
98 | struct intel_gvt_mmio { | |
99 | u32 *mmio_attribute; | |
100 | DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); | |
101 | }; | |
102 | ||
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103 | struct intel_gvt { |
104 | struct mutex lock; | |
105 | bool initialized; | |
106 | ||
107 | struct drm_i915_private *dev_priv; | |
108 | struct idr vgpu_idr; /* vGPU IDR pool */ | |
109 | ||
110 | struct intel_gvt_device_info device_info; | |
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111 | struct intel_gvt_gm gm; |
112 | struct intel_gvt_fence fence; | |
12d14cc4 | 113 | struct intel_gvt_mmio mmio; |
0ad35fed ZW |
114 | }; |
115 | ||
28a60dee ZW |
116 | /* Aperture/GM space definitions for GVT device */ |
117 | #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) | |
118 | #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) | |
119 | ||
120 | #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) | |
121 | #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) | |
122 | ||
123 | #define gvt_aperture_gmadr_base(gvt) (0) | |
124 | #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
125 | + gvt_aperture_sz(gvt) - 1) | |
126 | ||
127 | #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
128 | + gvt_aperture_sz(gvt)) | |
129 | #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ | |
130 | + gvt_hidden_sz(gvt) - 1) | |
131 | ||
132 | #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) | |
133 | ||
134 | /* Aperture/GM space definitions for vGPU */ | |
135 | #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) | |
136 | #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) | |
137 | #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) | |
138 | #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) | |
139 | ||
140 | #define vgpu_aperture_pa_base(vgpu) \ | |
141 | (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) | |
142 | ||
143 | #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) | |
144 | ||
145 | #define vgpu_aperture_pa_end(vgpu) \ | |
146 | (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
147 | ||
148 | #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) | |
149 | #define vgpu_aperture_gmadr_end(vgpu) \ | |
150 | (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
151 | ||
152 | #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) | |
153 | #define vgpu_hidden_gmadr_end(vgpu) \ | |
154 | (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) | |
155 | ||
156 | #define vgpu_fence_base(vgpu) (vgpu->fence.base) | |
157 | #define vgpu_fence_sz(vgpu) (vgpu->fence.size) | |
158 | ||
159 | struct intel_vgpu_creation_params { | |
160 | __u64 handle; | |
161 | __u64 low_gm_sz; /* in MB */ | |
162 | __u64 high_gm_sz; /* in MB */ | |
163 | __u64 fence_sz; | |
164 | __s32 primary; | |
165 | __u64 vgpu_id; | |
166 | }; | |
167 | ||
168 | int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, | |
169 | struct intel_vgpu_creation_params *param); | |
170 | void intel_vgpu_free_resource(struct intel_vgpu *vgpu); | |
171 | void intel_vgpu_write_fence(struct intel_vgpu *vgpu, | |
172 | u32 fence, u64 value); | |
173 | ||
0ad35fed ZW |
174 | #include "mpt.h" |
175 | ||
176 | #endif |