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1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
12d14cc4 ZW |
22 | * |
23 | * Authors: | |
24 | * Kevin Tian <kevin.tian@intel.com> | |
25 | * Eddie Dong <eddie.dong@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Niu Bing <bing.niu@intel.com> | |
29 | * Zhi Wang <zhi.a.wang@intel.com> | |
30 | * | |
0ad35fed ZW |
31 | */ |
32 | ||
33 | #ifndef _GVT_H_ | |
34 | #define _GVT_H_ | |
35 | ||
36 | #include "debug.h" | |
37 | #include "hypercall.h" | |
12d14cc4 | 38 | #include "mmio.h" |
0ad35fed ZW |
39 | |
40 | #define GVT_MAX_VGPU 8 | |
41 | ||
42 | enum { | |
43 | INTEL_GVT_HYPERVISOR_XEN = 0, | |
44 | INTEL_GVT_HYPERVISOR_KVM, | |
45 | }; | |
46 | ||
47 | struct intel_gvt_host { | |
48 | bool initialized; | |
49 | int hypervisor_type; | |
50 | struct intel_gvt_mpt *mpt; | |
51 | }; | |
52 | ||
53 | extern struct intel_gvt_host intel_gvt_host; | |
54 | ||
55 | /* Describe per-platform limitations. */ | |
56 | struct intel_gvt_device_info { | |
57 | u32 max_support_vgpus; | |
12d14cc4 | 58 | u32 mmio_size; |
579cea5f ZW |
59 | u32 cfg_space_size; |
60 | u32 mmio_bar; | |
0ad35fed ZW |
61 | }; |
62 | ||
28a60dee ZW |
63 | /* GM resources owned by a vGPU */ |
64 | struct intel_vgpu_gm { | |
65 | u64 aperture_sz; | |
66 | u64 hidden_sz; | |
67 | struct drm_mm_node low_gm_node; | |
68 | struct drm_mm_node high_gm_node; | |
69 | }; | |
70 | ||
71 | #define INTEL_GVT_MAX_NUM_FENCES 32 | |
72 | ||
73 | /* Fences owned by a vGPU */ | |
74 | struct intel_vgpu_fence { | |
75 | struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; | |
76 | u32 base; | |
77 | u32 size; | |
78 | }; | |
79 | ||
0ad35fed ZW |
80 | struct intel_vgpu { |
81 | struct intel_gvt *gvt; | |
82 | int id; | |
83 | unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ | |
28a60dee ZW |
84 | |
85 | struct intel_vgpu_fence fence; | |
86 | struct intel_vgpu_gm gm; | |
87 | }; | |
88 | ||
89 | struct intel_gvt_gm { | |
90 | unsigned long vgpu_allocated_low_gm_size; | |
91 | unsigned long vgpu_allocated_high_gm_size; | |
92 | }; | |
93 | ||
94 | struct intel_gvt_fence { | |
95 | unsigned long vgpu_allocated_fence_num; | |
0ad35fed ZW |
96 | }; |
97 | ||
12d14cc4 ZW |
98 | #define INTEL_GVT_MMIO_HASH_BITS 9 |
99 | ||
100 | struct intel_gvt_mmio { | |
101 | u32 *mmio_attribute; | |
102 | DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); | |
103 | }; | |
104 | ||
579cea5f ZW |
105 | struct intel_gvt_firmware { |
106 | void *cfg_space; | |
107 | void *mmio; | |
108 | bool firmware_loaded; | |
109 | }; | |
110 | ||
0ad35fed ZW |
111 | struct intel_gvt { |
112 | struct mutex lock; | |
113 | bool initialized; | |
114 | ||
115 | struct drm_i915_private *dev_priv; | |
116 | struct idr vgpu_idr; /* vGPU IDR pool */ | |
117 | ||
118 | struct intel_gvt_device_info device_info; | |
28a60dee ZW |
119 | struct intel_gvt_gm gm; |
120 | struct intel_gvt_fence fence; | |
12d14cc4 | 121 | struct intel_gvt_mmio mmio; |
579cea5f | 122 | struct intel_gvt_firmware firmware; |
0ad35fed ZW |
123 | }; |
124 | ||
579cea5f ZW |
125 | void intel_gvt_free_firmware(struct intel_gvt *gvt); |
126 | int intel_gvt_load_firmware(struct intel_gvt *gvt); | |
127 | ||
28a60dee ZW |
128 | /* Aperture/GM space definitions for GVT device */ |
129 | #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) | |
130 | #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) | |
131 | ||
132 | #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) | |
133 | #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) | |
134 | ||
135 | #define gvt_aperture_gmadr_base(gvt) (0) | |
136 | #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
137 | + gvt_aperture_sz(gvt) - 1) | |
138 | ||
139 | #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
140 | + gvt_aperture_sz(gvt)) | |
141 | #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ | |
142 | + gvt_hidden_sz(gvt) - 1) | |
143 | ||
144 | #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) | |
145 | ||
146 | /* Aperture/GM space definitions for vGPU */ | |
147 | #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) | |
148 | #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) | |
149 | #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) | |
150 | #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) | |
151 | ||
152 | #define vgpu_aperture_pa_base(vgpu) \ | |
153 | (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) | |
154 | ||
155 | #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) | |
156 | ||
157 | #define vgpu_aperture_pa_end(vgpu) \ | |
158 | (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
159 | ||
160 | #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) | |
161 | #define vgpu_aperture_gmadr_end(vgpu) \ | |
162 | (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
163 | ||
164 | #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) | |
165 | #define vgpu_hidden_gmadr_end(vgpu) \ | |
166 | (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) | |
167 | ||
168 | #define vgpu_fence_base(vgpu) (vgpu->fence.base) | |
169 | #define vgpu_fence_sz(vgpu) (vgpu->fence.size) | |
170 | ||
171 | struct intel_vgpu_creation_params { | |
172 | __u64 handle; | |
173 | __u64 low_gm_sz; /* in MB */ | |
174 | __u64 high_gm_sz; /* in MB */ | |
175 | __u64 fence_sz; | |
176 | __s32 primary; | |
177 | __u64 vgpu_id; | |
178 | }; | |
179 | ||
180 | int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, | |
181 | struct intel_vgpu_creation_params *param); | |
182 | void intel_vgpu_free_resource(struct intel_vgpu *vgpu); | |
183 | void intel_vgpu_write_fence(struct intel_vgpu *vgpu, | |
184 | u32 fence, u64 value); | |
185 | ||
0ad35fed ZW |
186 | #include "mpt.h" |
187 | ||
188 | #endif |