[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / gvt.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Kevin Tian <kevin.tian@intel.com>
 *    Eddie Dong <eddie.dong@intel.com>
 *
 * Contributors:
 *    Niu Bing <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#ifndef _GVT_H_
#define _GVT_H_

#include "debug.h"
#include "hypercall.h"
#include "mmio.h"
#include "reg.h"
#include "interrupt.h"
#include "gtt.h"
#include "display.h"
#include "edid.h"
#include "execlist.h"

#define GVT_MAX_VGPU 8

enum {
	INTEL_GVT_HYPERVISOR_XEN = 0,
	INTEL_GVT_HYPERVISOR_KVM,
};

struct intel_gvt_host {
	bool initialized;
	int hypervisor_type;
	struct intel_gvt_mpt *mpt;
};

extern struct intel_gvt_host intel_gvt_host;

/* Describe per-platform limitations. */
struct intel_gvt_device_info {
	u32 max_support_vgpus;
	u32 cfg_space_size;
	u32 mmio_size;
	u32 mmio_bar;
	unsigned long msi_cap_offset;
	u32 gtt_start_offset;
	u32 gtt_entry_size;
	u32 gtt_entry_size_shift;
};

/* GM resources owned by a vGPU */
struct intel_vgpu_gm {
	u64 aperture_sz;
	u64 hidden_sz;
	struct drm_mm_node low_gm_node;
	struct drm_mm_node high_gm_node;
};

#define INTEL_GVT_MAX_NUM_FENCES 32

/* Fences owned by a vGPU */
struct intel_vgpu_fence {
	struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
	u32 base;
	u32 size;
};

struct intel_vgpu_mmio {
	void *vreg;
	void *sreg;
	bool disable_warn_untrack;
};

#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
#define INTEL_GVT_MAX_BAR_NUM 4

struct intel_vgpu_pci_bar {
	u64 size;
	bool tracked;
};

struct intel_vgpu_cfg_space {
	unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
};

#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)

#define INTEL_GVT_MAX_PIPE 4

struct intel_vgpu_irq {
	bool irq_warn_once[INTEL_GVT_EVENT_MAX];
	DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
		       INTEL_GVT_EVENT_MAX);
};

struct intel_vgpu_opregion {
	void *va;
	u32 gfn[INTEL_GVT_OPREGION_PAGES];
	struct page *pages[INTEL_GVT_OPREGION_PAGES];
};

#define vgpu_opregion(vgpu) (&(vgpu->opregion))

#define INTEL_GVT_MAX_PORT 5

struct intel_vgpu_display {
	struct intel_vgpu_i2c_edid i2c_edid;
	struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
	struct intel_vgpu_sbi sbi;
};

struct intel_vgpu {
	struct intel_gvt *gvt;
	int id;
	unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
	bool active;
	bool resetting;

	struct intel_vgpu_fence fence;
	struct intel_vgpu_gm gm;
	struct intel_vgpu_cfg_space cfg_space;
	struct intel_vgpu_mmio mmio;
	struct intel_vgpu_irq irq;
	struct intel_vgpu_gtt gtt;
	struct intel_vgpu_opregion opregion;
	struct intel_vgpu_display display;
	/* TODO: move the declaration of intel_gvt.h to a proper place. */
	struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
};

struct intel_gvt_gm {
	unsigned long vgpu_allocated_low_gm_size;
	unsigned long vgpu_allocated_high_gm_size;
};

struct intel_gvt_fence {
	unsigned long vgpu_allocated_fence_num;
};

#define INTEL_GVT_MMIO_HASH_BITS 9

struct intel_gvt_mmio {
	u32 *mmio_attribute;
	DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
};

struct intel_gvt_firmware {
	void *cfg_space;
	void *mmio;
	bool firmware_loaded;
};

struct intel_gvt_opregion {
	void *opregion_va;
	u32 opregion_pa;
};

struct intel_gvt {
	struct mutex lock;
	bool initialized;

	struct drm_i915_private *dev_priv;
	struct idr vgpu_idr;	/* vGPU IDR pool */

	struct intel_gvt_device_info device_info;
	struct intel_gvt_gm gm;
	struct intel_gvt_fence fence;
	struct intel_gvt_mmio mmio;
	struct intel_gvt_firmware firmware;
	struct intel_gvt_irq irq;
	struct intel_gvt_gtt gtt;
	struct intel_gvt_opregion opregion;

	struct task_struct *service_thread;
	wait_queue_head_t service_thread_wq;
	unsigned long service_request;
};

enum {
	INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
};

static inline void intel_gvt_request_service(struct intel_gvt *gvt,
		int service)
{
	set_bit(service, (void *)&gvt->service_request);
	wake_up(&gvt->service_thread_wq);
}

void intel_gvt_free_firmware(struct intel_gvt *gvt);
int intel_gvt_load_firmware(struct intel_gvt *gvt);

/* Aperture/GM space definitions for GVT device */
#define gvt_aperture_sz(gvt)	  (gvt->dev_priv->ggtt.mappable_end)
#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)

#define gvt_ggtt_gm_sz(gvt)	  (gvt->dev_priv->ggtt.base.total)
#define gvt_ggtt_sz(gvt) \
	((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
#define gvt_hidden_sz(gvt)	  (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))

#define gvt_aperture_gmadr_base(gvt) (0)
#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
				     + gvt_aperture_sz(gvt) - 1)

#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
				    + gvt_aperture_sz(gvt))
#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
				   + gvt_hidden_sz(gvt) - 1)

#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)

/* Aperture/GM space definitions for vGPU */
#define vgpu_aperture_offset(vgpu)	((vgpu)->gm.low_gm_node.start)
#define vgpu_hidden_offset(vgpu)	((vgpu)->gm.high_gm_node.start)
#define vgpu_aperture_sz(vgpu)		((vgpu)->gm.aperture_sz)
#define vgpu_hidden_sz(vgpu)		((vgpu)->gm.hidden_sz)

#define vgpu_aperture_pa_base(vgpu) \
	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))

#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)

#define vgpu_aperture_pa_end(vgpu) \
	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)

#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
#define vgpu_aperture_gmadr_end(vgpu) \
	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)

#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
#define vgpu_hidden_gmadr_end(vgpu) \
	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)

#define vgpu_fence_base(vgpu) (vgpu->fence.base)
#define vgpu_fence_sz(vgpu) (vgpu->fence.size)

struct intel_vgpu_creation_params {
	__u64 handle;
	__u64 low_gm_sz;  /* in MB */
	__u64 high_gm_sz; /* in MB */
	__u64 fence_sz;
	__s32 primary;
	__u64 vgpu_id;
};

int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
			      struct intel_vgpu_creation_params *param);
void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
	u32 fence, u64 value);

/* Macros for easily accessing vGPU virtual/shadow register */
#define vgpu_vreg(vgpu, reg) \
	(*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg8(vgpu, reg) \
	(*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg16(vgpu, reg) \
	(*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg64(vgpu, reg) \
	(*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg(vgpu, reg) \
	(*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg8(vgpu, reg) \
	(*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg16(vgpu, reg) \
	(*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg64(vgpu, reg) \
	(*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define for_each_active_vgpu(gvt, vgpu, id) \
	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
		for_each_if(vgpu->active)

static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
					    u32 offset, u32 val, bool low)
{
	u32 *pval;

	/* BAR offset should be 32 bits algiend */
	offset = rounddown(offset, 4);
	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

	if (low) {
		/*
		 * only update bit 31 - bit 4,
		 * leave the bit 3 - bit 0 unchanged.
		 */
		*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
	}
}

struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
					 struct intel_vgpu_creation_params *
					 param);

void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);

/* validating GM functions */
#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
	((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
	 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))

#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
	((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
	 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))

#define vgpu_gmadr_is_valid(vgpu, gmadr) \
	 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
	  (vgpu_gmadr_is_hidden(vgpu, gmadr))))

#define gvt_gmadr_is_aperture(gvt, gmadr) \
	 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
	  (gmadr <= gvt_aperture_gmadr_end(gvt)))

#define gvt_gmadr_is_hidden(gvt, gmadr) \
	  ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
	   (gmadr <= gvt_hidden_gmadr_end(gvt)))

#define gvt_gmadr_is_valid(gvt, gmadr) \
	  (gvt_gmadr_is_aperture(gvt, gmadr) || \
	    gvt_gmadr_is_hidden(gvt, gmadr))

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index);
int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index);

int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset,
		void *p_data, unsigned int bytes);

int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset,
		void *p_data, unsigned int bytes);

void intel_gvt_clean_opregion(struct intel_gvt *gvt);
int intel_gvt_init_opregion(struct intel_gvt *gvt);

void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);

int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);

#include "mpt.h"

#endif
Commit	Line	Data
0ad35fed ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
12d14cc4 ZW	22	*
	23	* Authors:
	24	* Kevin Tian <kevin.tian@intel.com>
	25	* Eddie Dong <eddie.dong@intel.com>
	26	*
	27	* Contributors:
	28	* Niu Bing <bing.niu@intel.com>
	29	* Zhi Wang <zhi.a.wang@intel.com>
	30	*
0ad35fed ZW	31	*/
	32
	33	#ifndef _GVT_H_
	34	#define _GVT_H_
	35
	36	#include "debug.h"
	37	#include "hypercall.h"
12d14cc4	38	#include "mmio.h"
82d375d1	39	#include "reg.h"
c8fe6a68	40	#include "interrupt.h"
2707e444	41	#include "gtt.h"
04d348ae ZW	42	#include "display.h"
04d348ae ZW	43	#include "edid.h"
8453d674	44	#include "execlist.h"
0ad35fed ZW	45
	46	#define GVT_MAX_VGPU 8
	47
	48	enum {
	49	INTEL_GVT_HYPERVISOR_XEN = 0,
	50	INTEL_GVT_HYPERVISOR_KVM,
	51	};
	52
	53	struct intel_gvt_host {
	54	bool initialized;
	55	int hypervisor_type;
	56	struct intel_gvt_mpt *mpt;
	57	};
	58
	59	extern struct intel_gvt_host intel_gvt_host;
	60
	61	/* Describe per-platform limitations. */
	62	struct intel_gvt_device_info {
	63	u32 max_support_vgpus;
579cea5f	64	u32 cfg_space_size;
c8fe6a68	65	u32 mmio_size;
579cea5f	66	u32 mmio_bar;
c8fe6a68	67	unsigned long msi_cap_offset;
2707e444 ZW	68	u32 gtt_start_offset;
	69	u32 gtt_entry_size;
	70	u32 gtt_entry_size_shift;
0ad35fed ZW	71	};
0ad35fed ZW	72
28a60dee ZW	73	/* GM resources owned by a vGPU */
	74	struct intel_vgpu_gm {
	75	u64 aperture_sz;
	76	u64 hidden_sz;
	77	struct drm_mm_node low_gm_node;
	78	struct drm_mm_node high_gm_node;
	79	};
	80
	81	#define INTEL_GVT_MAX_NUM_FENCES 32
	82
	83	/* Fences owned by a vGPU */
	84	struct intel_vgpu_fence {
	85	struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
	86	u32 base;
	87	u32 size;
	88	};
	89
82d375d1 ZW	90	struct intel_vgpu_mmio {
	91	void *vreg;
	92	void *sreg;
e39c5add	93	bool disable_warn_untrack;
82d375d1 ZW	94	};
	95
	96	#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
	97	#define INTEL_GVT_MAX_BAR_NUM 4
	98
	99	struct intel_vgpu_pci_bar {
	100	u64 size;
	101	bool tracked;
	102	};
	103
	104	struct intel_vgpu_cfg_space {
	105	unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
	106	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
	107	};
	108
	109	#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
	110
04d348ae ZW	111	#define INTEL_GVT_MAX_PIPE 4
04d348ae ZW	112
c8fe6a68 ZW	113	struct intel_vgpu_irq {
c8fe6a68 ZW	114	bool irq_warn_once[INTEL_GVT_EVENT_MAX];
04d348ae ZW	115	DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
04d348ae ZW	116	INTEL_GVT_EVENT_MAX);
c8fe6a68 ZW	117	};
c8fe6a68 ZW	118
4d60c5fd ZW	119	struct intel_vgpu_opregion {
	120	void *va;
	121	u32 gfn[INTEL_GVT_OPREGION_PAGES];
	122	struct page *pages[INTEL_GVT_OPREGION_PAGES];
	123	};
	124
	125	#define vgpu_opregion(vgpu) (&(vgpu->opregion))
	126
04d348ae ZW	127	#define INTEL_GVT_MAX_PORT 5
	128
	129	struct intel_vgpu_display {
	130	struct intel_vgpu_i2c_edid i2c_edid;
	131	struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
	132	struct intel_vgpu_sbi sbi;
	133	};
	134
0ad35fed ZW	135	struct intel_vgpu {
	136	struct intel_gvt *gvt;
	137	int id;
	138	unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
82d375d1 ZW	139	bool active;
82d375d1 ZW	140	bool resetting;
28a60dee ZW	141
	142	struct intel_vgpu_fence fence;
	143	struct intel_vgpu_gm gm;
82d375d1 ZW	144	struct intel_vgpu_cfg_space cfg_space;
82d375d1 ZW	145	struct intel_vgpu_mmio mmio;
c8fe6a68	146	struct intel_vgpu_irq irq;
2707e444	147	struct intel_vgpu_gtt gtt;
4d60c5fd	148	struct intel_vgpu_opregion opregion;
04d348ae	149	struct intel_vgpu_display display;
8453d674 ZW	150	/* TODO: move the declaration of intel_gvt.h to a proper place. */
8453d674 ZW	151	struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
28a60dee ZW	152	};
	153
	154	struct intel_gvt_gm {
	155	unsigned long vgpu_allocated_low_gm_size;
	156	unsigned long vgpu_allocated_high_gm_size;
	157	};
	158
	159	struct intel_gvt_fence {
	160	unsigned long vgpu_allocated_fence_num;
0ad35fed ZW	161	};
0ad35fed ZW	162
12d14cc4 ZW	163	#define INTEL_GVT_MMIO_HASH_BITS 9
	164
	165	struct intel_gvt_mmio {
	166	u32 *mmio_attribute;
	167	DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
	168	};
	169
579cea5f ZW	170	struct intel_gvt_firmware {
	171	void *cfg_space;
	172	void *mmio;
	173	bool firmware_loaded;
	174	};
	175
4d60c5fd ZW	176	struct intel_gvt_opregion {
	177	void *opregion_va;
	178	u32 opregion_pa;
	179	};
	180
0ad35fed ZW	181	struct intel_gvt {
	182	struct mutex lock;
	183	bool initialized;
	184
	185	struct drm_i915_private *dev_priv;
	186	struct idr vgpu_idr; /* vGPU IDR pool */
	187
	188	struct intel_gvt_device_info device_info;
28a60dee ZW	189	struct intel_gvt_gm gm;
28a60dee ZW	190	struct intel_gvt_fence fence;
12d14cc4	191	struct intel_gvt_mmio mmio;
579cea5f	192	struct intel_gvt_firmware firmware;
c8fe6a68	193	struct intel_gvt_irq irq;
2707e444	194	struct intel_gvt_gtt gtt;
4d60c5fd	195	struct intel_gvt_opregion opregion;
04d348ae ZW	196
	197	struct task_struct *service_thread;
	198	wait_queue_head_t service_thread_wq;
	199	unsigned long service_request;
0ad35fed ZW	200	};
0ad35fed ZW	201
04d348ae ZW	202	enum {
	203	INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
	204	};
	205
	206	static inline void intel_gvt_request_service(struct intel_gvt *gvt,
	207	int service)
	208	{
	209	set_bit(service, (void *)&gvt->service_request);
	210	wake_up(&gvt->service_thread_wq);
	211	}
	212
579cea5f ZW	213	void intel_gvt_free_firmware(struct intel_gvt *gvt);
	214	int intel_gvt_load_firmware(struct intel_gvt *gvt);
	215
28a60dee ZW	216	/* Aperture/GM space definitions for GVT device */
	217	#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
	218	#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
	219
	220	#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
e39c5add ZW	221	#define gvt_ggtt_sz(gvt) \
e39c5add ZW	222	((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
28a60dee ZW	223	#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
	224
	225	#define gvt_aperture_gmadr_base(gvt) (0)
	226	#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
	227	+ gvt_aperture_sz(gvt) - 1)
	228
	229	#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
	230	+ gvt_aperture_sz(gvt))
	231	#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
	232	+ gvt_hidden_sz(gvt) - 1)
	233
	234	#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
	235
	236	/* Aperture/GM space definitions for vGPU */
	237	#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
	238	#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
	239	#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
	240	#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
	241
	242	#define vgpu_aperture_pa_base(vgpu) \
	243	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
	244
	245	#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
	246
	247	#define vgpu_aperture_pa_end(vgpu) \
	248	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
	249
	250	#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
	251	#define vgpu_aperture_gmadr_end(vgpu) \
	252	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
	253
	254	#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
	255	#define vgpu_hidden_gmadr_end(vgpu) \
	256	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
	257
	258	#define vgpu_fence_base(vgpu) (vgpu->fence.base)
	259	#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
	260
	261	struct intel_vgpu_creation_params {
	262	__u64 handle;
	263	__u64 low_gm_sz; /* in MB */
	264	__u64 high_gm_sz; /* in MB */
	265	__u64 fence_sz;
	266	__s32 primary;
	267	__u64 vgpu_id;
	268	};
	269
	270	int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
	271	struct intel_vgpu_creation_params *param);
	272	void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
	273	void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
	274	u32 fence, u64 value);
	275
82d375d1 ZW	276	/* Macros for easily accessing vGPU virtual/shadow register */
	277	#define vgpu_vreg(vgpu, reg) \
	278	((u32 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	279	#define vgpu_vreg8(vgpu, reg) \
	280	((u8 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	281	#define vgpu_vreg16(vgpu, reg) \
	282	((u16 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	283	#define vgpu_vreg64(vgpu, reg) \
	284	((u64 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	285	#define vgpu_sreg(vgpu, reg) \
	286	((u32 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	287	#define vgpu_sreg8(vgpu, reg) \
	288	((u8 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	289	#define vgpu_sreg16(vgpu, reg) \
	290	((u16 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	291	#define vgpu_sreg64(vgpu, reg) \
	292	((u64 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	293
	294	#define for_each_active_vgpu(gvt, vgpu, id) \
	295	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
	296	for_each_if(vgpu->active)
	297
	298	static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
	299	u32 offset, u32 val, bool low)
	300	{
	301	u32 *pval;
	302
	303	/* BAR offset should be 32 bits algiend */
	304	offset = rounddown(offset, 4);
	305	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
	306
	307	if (low) {
	308	/*
	309	* only update bit 31 - bit 4,
	310	* leave the bit 3 - bit 0 unchanged.
	311	*/
	312	pval = (val & GENMASK(31, 4)) \| (pval & GENMASK(3, 0));
	313	}
	314	}
	315
	316	struct intel_vgpu intel_gvt_create_vgpu(struct intel_gvt gvt,
	317	struct intel_vgpu_creation_params *
	318	param);
	319
	320	void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
	321
2707e444 ZW	322	/* validating GM functions */
	323	#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
	324	((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
	325	(gmadr <= vgpu_aperture_gmadr_end(vgpu)))
	326
	327	#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
	328	((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
	329	(gmadr <= vgpu_hidden_gmadr_end(vgpu)))
	330
	331	#define vgpu_gmadr_is_valid(vgpu, gmadr) \
	332	((vgpu_gmadr_is_aperture(vgpu, gmadr) \|\| \
	333	(vgpu_gmadr_is_hidden(vgpu, gmadr))))
	334
	335	#define gvt_gmadr_is_aperture(gvt, gmadr) \
	336	((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
	337	(gmadr <= gvt_aperture_gmadr_end(gvt)))
	338
	339	#define gvt_gmadr_is_hidden(gvt, gmadr) \
	340	((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
	341	(gmadr <= gvt_hidden_gmadr_end(gvt)))
	342
	343	#define gvt_gmadr_is_valid(gvt, gmadr) \
	344	(gvt_gmadr_is_aperture(gvt, gmadr) \|\| \
	345	gvt_gmadr_is_hidden(gvt, gmadr))
	346
	347	bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
	348	int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu vgpu, u64 g_addr, u64 h_addr);
	349	int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu vgpu, u64 h_addr, u64 g_addr);
	350	int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
	351	unsigned long *h_index);
	352	int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
	353	unsigned long *g_index);
4d60c5fd ZW	354
	355	int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset,
	356	void *p_data, unsigned int bytes);
	357
	358	int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset,
	359	void *p_data, unsigned int bytes);
	360
	361	void intel_gvt_clean_opregion(struct intel_gvt *gvt);
	362	int intel_gvt_init_opregion(struct intel_gvt *gvt);
	363
	364	void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
	365	int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);
	366
	367	int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
	368
0ad35fed ZW	369	#include "mpt.h"
	370
	371	#endif