]>
Commit | Line | Data |
---|---|---|
0ad35fed ZW |
1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
12d14cc4 ZW |
22 | * |
23 | * Authors: | |
24 | * Kevin Tian <kevin.tian@intel.com> | |
25 | * Eddie Dong <eddie.dong@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Niu Bing <bing.niu@intel.com> | |
29 | * Zhi Wang <zhi.a.wang@intel.com> | |
30 | * | |
0ad35fed ZW |
31 | */ |
32 | ||
33 | #ifndef _GVT_H_ | |
34 | #define _GVT_H_ | |
35 | ||
36 | #include "debug.h" | |
37 | #include "hypercall.h" | |
12d14cc4 | 38 | #include "mmio.h" |
82d375d1 | 39 | #include "reg.h" |
c8fe6a68 | 40 | #include "interrupt.h" |
2707e444 | 41 | #include "gtt.h" |
04d348ae ZW |
42 | #include "display.h" |
43 | #include "edid.h" | |
8453d674 | 44 | #include "execlist.h" |
28c4c6ca | 45 | #include "scheduler.h" |
4b63960e | 46 | #include "sched_policy.h" |
17865713 | 47 | #include "render.h" |
be1da707 | 48 | #include "cmd_parser.h" |
0ad35fed ZW |
49 | |
50 | #define GVT_MAX_VGPU 8 | |
51 | ||
52 | enum { | |
53 | INTEL_GVT_HYPERVISOR_XEN = 0, | |
54 | INTEL_GVT_HYPERVISOR_KVM, | |
55 | }; | |
56 | ||
57 | struct intel_gvt_host { | |
58 | bool initialized; | |
59 | int hypervisor_type; | |
60 | struct intel_gvt_mpt *mpt; | |
61 | }; | |
62 | ||
63 | extern struct intel_gvt_host intel_gvt_host; | |
64 | ||
65 | /* Describe per-platform limitations. */ | |
66 | struct intel_gvt_device_info { | |
67 | u32 max_support_vgpus; | |
579cea5f | 68 | u32 cfg_space_size; |
c8fe6a68 | 69 | u32 mmio_size; |
579cea5f | 70 | u32 mmio_bar; |
c8fe6a68 | 71 | unsigned long msi_cap_offset; |
2707e444 ZW |
72 | u32 gtt_start_offset; |
73 | u32 gtt_entry_size; | |
74 | u32 gtt_entry_size_shift; | |
be1da707 ZW |
75 | int gmadr_bytes_in_cmd; |
76 | u32 max_surface_size; | |
0ad35fed ZW |
77 | }; |
78 | ||
28a60dee ZW |
79 | /* GM resources owned by a vGPU */ |
80 | struct intel_vgpu_gm { | |
81 | u64 aperture_sz; | |
82 | u64 hidden_sz; | |
83 | struct drm_mm_node low_gm_node; | |
84 | struct drm_mm_node high_gm_node; | |
85 | }; | |
86 | ||
87 | #define INTEL_GVT_MAX_NUM_FENCES 32 | |
88 | ||
89 | /* Fences owned by a vGPU */ | |
90 | struct intel_vgpu_fence { | |
91 | struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; | |
92 | u32 base; | |
93 | u32 size; | |
94 | }; | |
95 | ||
82d375d1 ZW |
96 | struct intel_vgpu_mmio { |
97 | void *vreg; | |
98 | void *sreg; | |
e39c5add | 99 | bool disable_warn_untrack; |
82d375d1 ZW |
100 | }; |
101 | ||
102 | #define INTEL_GVT_MAX_CFG_SPACE_SZ 256 | |
103 | #define INTEL_GVT_MAX_BAR_NUM 4 | |
104 | ||
105 | struct intel_vgpu_pci_bar { | |
106 | u64 size; | |
107 | bool tracked; | |
108 | }; | |
109 | ||
110 | struct intel_vgpu_cfg_space { | |
111 | unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ]; | |
112 | struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; | |
113 | }; | |
114 | ||
115 | #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) | |
116 | ||
04d348ae ZW |
117 | #define INTEL_GVT_MAX_PIPE 4 |
118 | ||
c8fe6a68 ZW |
119 | struct intel_vgpu_irq { |
120 | bool irq_warn_once[INTEL_GVT_EVENT_MAX]; | |
04d348ae ZW |
121 | DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], |
122 | INTEL_GVT_EVENT_MAX); | |
c8fe6a68 ZW |
123 | }; |
124 | ||
4d60c5fd ZW |
125 | struct intel_vgpu_opregion { |
126 | void *va; | |
127 | u32 gfn[INTEL_GVT_OPREGION_PAGES]; | |
128 | struct page *pages[INTEL_GVT_OPREGION_PAGES]; | |
129 | }; | |
130 | ||
131 | #define vgpu_opregion(vgpu) (&(vgpu->opregion)) | |
132 | ||
04d348ae ZW |
133 | #define INTEL_GVT_MAX_PORT 5 |
134 | ||
135 | struct intel_vgpu_display { | |
136 | struct intel_vgpu_i2c_edid i2c_edid; | |
137 | struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; | |
138 | struct intel_vgpu_sbi sbi; | |
139 | }; | |
140 | ||
0ad35fed ZW |
141 | struct intel_vgpu { |
142 | struct intel_gvt *gvt; | |
143 | int id; | |
144 | unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ | |
82d375d1 ZW |
145 | bool active; |
146 | bool resetting; | |
4b63960e | 147 | void *sched_data; |
28a60dee ZW |
148 | |
149 | struct intel_vgpu_fence fence; | |
150 | struct intel_vgpu_gm gm; | |
82d375d1 ZW |
151 | struct intel_vgpu_cfg_space cfg_space; |
152 | struct intel_vgpu_mmio mmio; | |
c8fe6a68 | 153 | struct intel_vgpu_irq irq; |
2707e444 | 154 | struct intel_vgpu_gtt gtt; |
4d60c5fd | 155 | struct intel_vgpu_opregion opregion; |
04d348ae | 156 | struct intel_vgpu_display display; |
8453d674 | 157 | struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; |
28c4c6ca ZW |
158 | struct list_head workload_q_head[I915_NUM_ENGINES]; |
159 | struct kmem_cache *workloads; | |
e4734057 | 160 | atomic_t running_workload_num; |
17865713 | 161 | DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); |
e4734057 ZW |
162 | struct i915_gem_context *shadow_ctx; |
163 | struct notifier_block shadow_ctx_notifier_block; | |
28a60dee ZW |
164 | }; |
165 | ||
166 | struct intel_gvt_gm { | |
167 | unsigned long vgpu_allocated_low_gm_size; | |
168 | unsigned long vgpu_allocated_high_gm_size; | |
169 | }; | |
170 | ||
171 | struct intel_gvt_fence { | |
172 | unsigned long vgpu_allocated_fence_num; | |
0ad35fed ZW |
173 | }; |
174 | ||
12d14cc4 ZW |
175 | #define INTEL_GVT_MMIO_HASH_BITS 9 |
176 | ||
177 | struct intel_gvt_mmio { | |
178 | u32 *mmio_attribute; | |
179 | DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); | |
180 | }; | |
181 | ||
579cea5f ZW |
182 | struct intel_gvt_firmware { |
183 | void *cfg_space; | |
184 | void *mmio; | |
185 | bool firmware_loaded; | |
186 | }; | |
187 | ||
4d60c5fd | 188 | struct intel_gvt_opregion { |
321927db | 189 | void __iomem *opregion_va; |
4d60c5fd ZW |
190 | u32 opregion_pa; |
191 | }; | |
192 | ||
1f31c829 ZW |
193 | #define NR_MAX_INTEL_VGPU_TYPES 20 |
194 | struct intel_vgpu_type { | |
195 | char name[16]; | |
196 | unsigned int max_instance; | |
197 | unsigned int avail_instance; | |
198 | unsigned int low_gm_size; | |
199 | unsigned int high_gm_size; | |
200 | unsigned int fence; | |
201 | }; | |
202 | ||
0ad35fed ZW |
203 | struct intel_gvt { |
204 | struct mutex lock; | |
0ad35fed ZW |
205 | struct drm_i915_private *dev_priv; |
206 | struct idr vgpu_idr; /* vGPU IDR pool */ | |
207 | ||
208 | struct intel_gvt_device_info device_info; | |
28a60dee ZW |
209 | struct intel_gvt_gm gm; |
210 | struct intel_gvt_fence fence; | |
12d14cc4 | 211 | struct intel_gvt_mmio mmio; |
579cea5f | 212 | struct intel_gvt_firmware firmware; |
c8fe6a68 | 213 | struct intel_gvt_irq irq; |
2707e444 | 214 | struct intel_gvt_gtt gtt; |
4d60c5fd | 215 | struct intel_gvt_opregion opregion; |
28c4c6ca | 216 | struct intel_gvt_workload_scheduler scheduler; |
be1da707 | 217 | DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); |
1f31c829 ZW |
218 | struct intel_vgpu_type *types; |
219 | unsigned int num_types; | |
04d348ae ZW |
220 | |
221 | struct task_struct *service_thread; | |
222 | wait_queue_head_t service_thread_wq; | |
223 | unsigned long service_request; | |
0ad35fed ZW |
224 | }; |
225 | ||
feddf6e8 ZW |
226 | static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) |
227 | { | |
228 | return i915->gvt; | |
229 | } | |
230 | ||
04d348ae ZW |
231 | enum { |
232 | INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, | |
233 | }; | |
234 | ||
235 | static inline void intel_gvt_request_service(struct intel_gvt *gvt, | |
236 | int service) | |
237 | { | |
238 | set_bit(service, (void *)&gvt->service_request); | |
239 | wake_up(&gvt->service_thread_wq); | |
240 | } | |
241 | ||
579cea5f ZW |
242 | void intel_gvt_free_firmware(struct intel_gvt *gvt); |
243 | int intel_gvt_load_firmware(struct intel_gvt *gvt); | |
244 | ||
1f31c829 ZW |
245 | /* Aperture/GM space definitions for GVT device */ |
246 | #define MB_TO_BYTES(mb) ((mb) << 20ULL) | |
247 | #define BYTES_TO_MB(b) ((b) >> 20ULL) | |
248 | ||
249 | #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) | |
250 | #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) | |
251 | #define HOST_FENCE 4 | |
252 | ||
28a60dee ZW |
253 | /* Aperture/GM space definitions for GVT device */ |
254 | #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) | |
255 | #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) | |
256 | ||
257 | #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) | |
e39c5add ZW |
258 | #define gvt_ggtt_sz(gvt) \ |
259 | ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) | |
28a60dee ZW |
260 | #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) |
261 | ||
262 | #define gvt_aperture_gmadr_base(gvt) (0) | |
263 | #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
264 | + gvt_aperture_sz(gvt) - 1) | |
265 | ||
266 | #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ | |
267 | + gvt_aperture_sz(gvt)) | |
268 | #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ | |
269 | + gvt_hidden_sz(gvt) - 1) | |
270 | ||
271 | #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) | |
272 | ||
273 | /* Aperture/GM space definitions for vGPU */ | |
274 | #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) | |
275 | #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) | |
276 | #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) | |
277 | #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) | |
278 | ||
279 | #define vgpu_aperture_pa_base(vgpu) \ | |
280 | (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) | |
281 | ||
282 | #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) | |
283 | ||
284 | #define vgpu_aperture_pa_end(vgpu) \ | |
285 | (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
286 | ||
287 | #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) | |
288 | #define vgpu_aperture_gmadr_end(vgpu) \ | |
289 | (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) | |
290 | ||
291 | #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) | |
292 | #define vgpu_hidden_gmadr_end(vgpu) \ | |
293 | (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) | |
294 | ||
295 | #define vgpu_fence_base(vgpu) (vgpu->fence.base) | |
296 | #define vgpu_fence_sz(vgpu) (vgpu->fence.size) | |
297 | ||
298 | struct intel_vgpu_creation_params { | |
299 | __u64 handle; | |
300 | __u64 low_gm_sz; /* in MB */ | |
301 | __u64 high_gm_sz; /* in MB */ | |
302 | __u64 fence_sz; | |
303 | __s32 primary; | |
304 | __u64 vgpu_id; | |
305 | }; | |
306 | ||
307 | int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, | |
308 | struct intel_vgpu_creation_params *param); | |
309 | void intel_vgpu_free_resource(struct intel_vgpu *vgpu); | |
310 | void intel_vgpu_write_fence(struct intel_vgpu *vgpu, | |
311 | u32 fence, u64 value); | |
312 | ||
82d375d1 ZW |
313 | /* Macros for easily accessing vGPU virtual/shadow register */ |
314 | #define vgpu_vreg(vgpu, reg) \ | |
315 | (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
316 | #define vgpu_vreg8(vgpu, reg) \ | |
317 | (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
318 | #define vgpu_vreg16(vgpu, reg) \ | |
319 | (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
320 | #define vgpu_vreg64(vgpu, reg) \ | |
321 | (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
322 | #define vgpu_sreg(vgpu, reg) \ | |
323 | (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
324 | #define vgpu_sreg8(vgpu, reg) \ | |
325 | (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
326 | #define vgpu_sreg16(vgpu, reg) \ | |
327 | (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
328 | #define vgpu_sreg64(vgpu, reg) \ | |
329 | (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) | |
330 | ||
331 | #define for_each_active_vgpu(gvt, vgpu, id) \ | |
332 | idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ | |
333 | for_each_if(vgpu->active) | |
334 | ||
335 | static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, | |
336 | u32 offset, u32 val, bool low) | |
337 | { | |
338 | u32 *pval; | |
339 | ||
340 | /* BAR offset should be 32 bits algiend */ | |
341 | offset = rounddown(offset, 4); | |
342 | pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); | |
343 | ||
344 | if (low) { | |
345 | /* | |
346 | * only update bit 31 - bit 4, | |
347 | * leave the bit 3 - bit 0 unchanged. | |
348 | */ | |
349 | *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); | |
350 | } | |
351 | } | |
352 | ||
1f31c829 ZW |
353 | int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); |
354 | void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); | |
82d375d1 | 355 | |
1f31c829 ZW |
356 | struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, |
357 | struct intel_vgpu_type *type); | |
82d375d1 | 358 | void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); |
9ec1e66b | 359 | void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); |
82d375d1 | 360 | |
1f31c829 | 361 | |
2707e444 ZW |
362 | /* validating GM functions */ |
363 | #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ | |
364 | ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ | |
365 | (gmadr <= vgpu_aperture_gmadr_end(vgpu))) | |
366 | ||
367 | #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ | |
368 | ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ | |
369 | (gmadr <= vgpu_hidden_gmadr_end(vgpu))) | |
370 | ||
371 | #define vgpu_gmadr_is_valid(vgpu, gmadr) \ | |
372 | ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ | |
373 | (vgpu_gmadr_is_hidden(vgpu, gmadr)))) | |
374 | ||
375 | #define gvt_gmadr_is_aperture(gvt, gmadr) \ | |
376 | ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ | |
377 | (gmadr <= gvt_aperture_gmadr_end(gvt))) | |
378 | ||
379 | #define gvt_gmadr_is_hidden(gvt, gmadr) \ | |
380 | ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ | |
381 | (gmadr <= gvt_hidden_gmadr_end(gvt))) | |
382 | ||
383 | #define gvt_gmadr_is_valid(gvt, gmadr) \ | |
384 | (gvt_gmadr_is_aperture(gvt, gmadr) || \ | |
385 | gvt_gmadr_is_hidden(gvt, gmadr)) | |
386 | ||
387 | bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); | |
388 | int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); | |
389 | int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); | |
390 | int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, | |
391 | unsigned long *h_index); | |
392 | int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, | |
393 | unsigned long *g_index); | |
4d60c5fd | 394 | |
9ec1e66b | 395 | int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, |
4d60c5fd ZW |
396 | void *p_data, unsigned int bytes); |
397 | ||
9ec1e66b | 398 | int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, |
4d60c5fd ZW |
399 | void *p_data, unsigned int bytes); |
400 | ||
401 | void intel_gvt_clean_opregion(struct intel_gvt *gvt); | |
402 | int intel_gvt_init_opregion(struct intel_gvt *gvt); | |
403 | ||
404 | void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); | |
405 | int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); | |
406 | ||
407 | int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); | |
23736d1b PG |
408 | int setup_vgpu_mmio(struct intel_vgpu *vgpu); |
409 | void populate_pvinfo_page(struct intel_vgpu *vgpu); | |
4d60c5fd | 410 | |
9ec1e66b JS |
411 | struct intel_gvt_ops { |
412 | int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, | |
413 | unsigned int); | |
414 | int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, | |
415 | unsigned int); | |
416 | int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, | |
417 | unsigned int); | |
418 | int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, | |
419 | unsigned int); | |
420 | struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, | |
421 | struct intel_vgpu_type *); | |
422 | void (*vgpu_destroy)(struct intel_vgpu *); | |
423 | void (*vgpu_reset)(struct intel_vgpu *); | |
424 | }; | |
425 | ||
426 | ||
0ad35fed ZW |
427 | #include "mpt.h" |
428 | ||
429 | #endif |