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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / handlers.c
CommitLineData
12d14cc4
ZW		 1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
feddf6e8
ZW		 40#include "gvt.h"
41#include "i915_pvinfo.h"
12d14cc4 42
e39c5add
ZW		 43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
12d14cc4
ZW		 50/* Register contains RO bits */
51#define F_RO (1 << 0)
52/* Register contains graphics address */
53#define F_GMADR (1 << 1)
54/* Mode mask registers with high 16 bits as the mask bits */
55#define F_MODE_MASK (1 << 2)
56/* This reg can be accessed by GPU commands */
57#define F_CMD_ACCESS (1 << 3)
58/* This reg has been accessed by a VM */
59#define F_ACCESSED (1 << 4)
60/* This reg has been accessed through GPU commands */
61#define F_CMD_ACCESSED (1 << 5)
62/* This reg could be accessed by unaligned address */
63#define F_UNALIGN (1 << 6)
64
65unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
66{
67 if (IS_BROADWELL(gvt->dev_priv))
68 return D_BDW;
69 else if (IS_SKYLAKE(gvt->dev_priv))
70 return D_SKL;
71
72 return 0;
73}
74
75bool intel_gvt_match_device(struct intel_gvt *gvt,
76 unsigned long device)
77{
78 return intel_gvt_get_device_type(gvt) & device;
79}
80
e39c5add
ZW		 81static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
82 void *p_data, unsigned int bytes)
83{
84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
85}
86
87static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
88 void *p_data, unsigned int bytes)
89{
90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
91}
92
12d14cc4
ZW		 93static int new_mmio_info(struct intel_gvt *gvt,
94 u32 offset, u32 flags, u32 size,
95 u32 addr_mask, u32 ro_mask, u32 device,
3e70c5d6
NI		 96 int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int),
97 int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int))
12d14cc4
ZW		 98{
99 struct intel_gvt_mmio_info *info, *p;
100 u32 start, end, i;
101
102 if (!intel_gvt_match_device(gvt, device))
103 return 0;
104
105 if (WARN_ON(!IS_ALIGNED(offset, 4)))
106 return -EINVAL;
107
108 start = offset;
109 end = offset + size;
110
111 for (i = start; i < end; i += 4) {
112 info = kzalloc(sizeof(*info), GFP_KERNEL);
113 if (!info)
114 return -ENOMEM;
115
116 info->offset = i;
117 p = intel_gvt_find_mmio_info(gvt, info->offset);
118 if (p)
119 gvt_err("dup mmio definition offset %x\n",
120 info->offset);
121 info->size = size;
122 info->length = (i + 4) < end ? 4 : (end - i);
123 info->addr_mask = addr_mask;
4ec3dd89 124 info->ro_mask = ro_mask;
12d14cc4 125 info->device = device;
e39c5add
ZW		 126 info->read = read ? read : intel_vgpu_default_mmio_read;
127 info->write = write ? write : intel_vgpu_default_mmio_write;
12d14cc4
ZW		 128 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
129 INIT_HLIST_NODE(&info->node);
130 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
131 }
132 return 0;
133}
134
28c4c6ca
ZW		 135static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
136{
0fac21e7
ZW		 137 enum intel_engine_id id;
138 struct intel_engine_cs *engine;
28c4c6ca
ZW		 139
140 reg &= ~GENMASK(11, 0);
0fac21e7
ZW		 141 for_each_engine(engine, gvt->dev_priv, id) {
142 if (engine->mmio_base == reg)
143 return id;
28c4c6ca
ZW		 144 }
145 return -1;
146}
147
e39c5add
ZW		 148#define offset_to_fence_num(offset) \
149 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
150
151#define fence_num_to_offset(num) \
152 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
153
fd64be63
MH		 154
155static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
156{
157 switch (reason) {
158 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
159 pr_err("Detected your guest driver doesn't support GVT-g.\n");
160 break;
a33fc7a0
MH		 161 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
162 pr_err("Graphics resource is not enough for the guest\n");
fd64be63
MH		 163 default:
164 break;
165 }
166 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
167 vgpu->failsafe = true;
168}
169
e39c5add
ZW		 170static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
171 unsigned int fence_num, void *p_data, unsigned int bytes)
172{
173 if (fence_num >= vgpu_fence_sz(vgpu)) {
fd64be63
MH		 174
175 /* When guest access oob fence regs without access
176 * pv_info first, we treat guest not supporting GVT,
177 * and we will let vgpu enter failsafe mode.
178 */
d1be371d 179 if (!vgpu->pv_notified)
fd64be63
MH		 180 enter_failsafe_mode(vgpu,
181 GVT_FAILSAFE_UNSUPPORTED_GUEST);
d1be371d
ZX		 182
183 if (!vgpu->mmio.disable_warn_untrack) {
695fbc08
TZ		 184 gvt_vgpu_err("found oob fence register access\n");
185 gvt_vgpu_err("total fence %d, access fence %d\n",
186 vgpu_fence_sz(vgpu), fence_num);
fd64be63 187 }
e39c5add 188 memset(p_data, 0, bytes);
d1be371d 189 return -EINVAL;
e39c5add
ZW		 190 }
191 return 0;
192}
193
194static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
195 void *p_data, unsigned int bytes)
196{
197 int ret;
198
199 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
200 p_data, bytes);
201 if (ret)
202 return ret;
203 read_vreg(vgpu, off, p_data, bytes);
204 return 0;
205}
206
207static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
208 void *p_data, unsigned int bytes)
209{
210 unsigned int fence_num = offset_to_fence_num(off);
211 int ret;
212
213 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
214 if (ret)
215 return ret;
216 write_vreg(vgpu, off, p_data, bytes);
217
218 intel_vgpu_write_fence(vgpu, fence_num,
219 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
220 return 0;
221}
222
223#define CALC_MODE_MASK_REG(old, new) \
224 (((new) & GENMASK(31, 16)) \
225 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
226 | ((new) & ((new) >> 16))))
227
228static int mul_force_wake_write(struct intel_vgpu *vgpu,
229 unsigned int offset, void *p_data, unsigned int bytes)
230{
231 u32 old, new;
232 uint32_t ack_reg_offset;
233
234 old = vgpu_vreg(vgpu, offset);
235 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
236
237 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
238 switch (offset) {
239 case FORCEWAKE_RENDER_GEN9_REG:
240 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
241 break;
242 case FORCEWAKE_BLITTER_GEN9_REG:
243 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
244 break;
245 case FORCEWAKE_MEDIA_GEN9_REG:
246 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
247 break;
248 default:
249 /*should not hit here*/
695fbc08 250 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
39762ad4 251 return -EINVAL;
e39c5add
ZW		 252 }
253 } else {
254 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
255 }
256
257 vgpu_vreg(vgpu, offset) = new;
258 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
259 return 0;
260}
261
262static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
c34eaa8d 263 void *p_data, unsigned int bytes)
e39c5add 264{
c34eaa8d 265 unsigned int engine_mask = 0;
e39c5add 266 u32 data;
e39c5add 267
40d2428b 268 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 269 data = vgpu_vreg(vgpu, offset);
270
271 if (data & GEN6_GRDOM_FULL) {
272 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
c34eaa8d
CD		 273 engine_mask = ALL_ENGINES;
274 } else {
275 if (data & GEN6_GRDOM_RENDER) {
276 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
277 engine_mask |= (1 << RCS);
278 }
279 if (data & GEN6_GRDOM_MEDIA) {
280 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
281 engine_mask |= (1 << VCS);
282 }
283 if (data & GEN6_GRDOM_BLT) {
284 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
285 engine_mask |= (1 << BCS);
286 }
287 if (data & GEN6_GRDOM_VECS) {
288 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
289 engine_mask |= (1 << VECS);
290 }
291 if (data & GEN8_GRDOM_MEDIA2) {
292 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
293 if (HAS_BSD2(vgpu->gvt->dev_priv))
294 engine_mask |= (1 << VCS2);
295 }
e39c5add 296 }
c34eaa8d
CD		 297
298 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
299
300 return 0;
e39c5add
ZW		 301}
302
04d348ae
ZW		 303static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
304 void *p_data, unsigned int bytes)
305{
306 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
307}
308
309static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
310 void *p_data, unsigned int bytes)
311{
312 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
313}
314
315static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
316 unsigned int offset, void *p_data, unsigned int bytes)
317{
318 write_vreg(vgpu, offset, p_data, bytes);
319
320 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
321 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
322 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
323 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
324 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
325
326 } else
327 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
328 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
329 | PP_CYCLE_DELAY_ACTIVE);
330 return 0;
331}
332
333static int transconf_mmio_write(struct intel_vgpu *vgpu,
334 unsigned int offset, void *p_data, unsigned int bytes)
335{
336 write_vreg(vgpu, offset, p_data, bytes);
337
338 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
339 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
340 else
341 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
342 return 0;
343}
344
345static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
346 void *p_data, unsigned int bytes)
347{
348 write_vreg(vgpu, offset, p_data, bytes);
349
350 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
351 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
352 else
353 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
354
355 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
356 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
357 else
358 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
359
360 return 0;
361}
362
363static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
364 void *p_data, unsigned int bytes)
365{
366 *(u32 *)p_data = (1 << 17);
367 return 0;
368}
369
370static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
371 void *p_data, unsigned int bytes)
372{
373 *(u32 *)p_data = 3;
374 return 0;
375}
376
377static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
378 void *p_data, unsigned int bytes)
379{
380 *(u32 *)p_data = (0x2f << 16);
381 return 0;
382}
383
384static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
385 void *p_data, unsigned int bytes)
386{
387 u32 data;
388
389 write_vreg(vgpu, offset, p_data, bytes);
390 data = vgpu_vreg(vgpu, offset);
391
392 if (data & PIPECONF_ENABLE)
393 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
394 else
395 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
396 intel_gvt_check_vblank_emulation(vgpu->gvt);
397 return 0;
398}
399
e6cedfea
ZY		 400/* ascendingly sorted */
401static i915_reg_t force_nonpriv_white_list[] = {
402 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
403 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
404 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
405 _MMIO(0x2690),
406 _MMIO(0x2694),
407 _MMIO(0x2698),
408 _MMIO(0x4de0),
409 _MMIO(0x4de4),
410 _MMIO(0x4dfc),
411 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
412 _MMIO(0x7014),
413 HDC_CHICKEN0,//_MMIO(0x7300)
414 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
415 _MMIO(0x7700),
416 _MMIO(0x7704),
417 _MMIO(0x7708),
418 _MMIO(0x770c),
419 _MMIO(0xb110),
420 GEN8_L3SQCREG4,//_MMIO(0xb118)
421 _MMIO(0xe100),
422 _MMIO(0xe18c),
423 _MMIO(0xe48c),
424 _MMIO(0xe5f4),
425};
426
427/* a simple bsearch */
428static inline bool in_whitelist(unsigned int reg)
429{
430 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
431 i915_reg_t *array = force_nonpriv_white_list;
432
433 while (left < right) {
434 int mid = (left + right)/2;
435
436 if (reg > array[mid].reg)
437 left = mid + 1;
438 else if (reg < array[mid].reg)
439 right = mid;
440 else
441 return true;
442 }
443 return false;
444}
445
446static int force_nonpriv_write(struct intel_vgpu *vgpu,
447 unsigned int offset, void *p_data, unsigned int bytes)
448{
449 u32 reg_nonpriv = *(u32 *)p_data;
450 int ret = -EINVAL;
451
452 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
453 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
454 vgpu->id, offset, bytes);
455 return ret;
456 }
457
458 if (in_whitelist(reg_nonpriv)) {
459 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
460 bytes);
461 } else {
462 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
463 vgpu->id, reg_nonpriv);
464 }
465 return ret;
466}
467
04d348ae
ZW		 468static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
469 void *p_data, unsigned int bytes)
470{
471 write_vreg(vgpu, offset, p_data, bytes);
472
473 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
474 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
475 } else {
476 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
477 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
478 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
479 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
480 }
481 return 0;
482}
483
484static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
485 unsigned int offset, void *p_data, unsigned int bytes)
486{
487 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
488 return 0;
489}
490
491#define FDI_LINK_TRAIN_PATTERN1 0
492#define FDI_LINK_TRAIN_PATTERN2 1
493
494static int fdi_auto_training_started(struct intel_vgpu *vgpu)
495{
496 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
497 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
498 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
499
500 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
501 (rx_ctl & FDI_RX_ENABLE) &&
502 (rx_ctl & FDI_AUTO_TRAINING) &&
503 (tx_ctl & DP_TP_CTL_ENABLE) &&
504 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
505 return 1;
506 else
507 return 0;
508}
509
510static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
511 enum pipe pipe, unsigned int train_pattern)
512{
513 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
514 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
515 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
516 unsigned int fdi_iir_check_bits;
517
518 fdi_rx_imr = FDI_RX_IMR(pipe);
519 fdi_tx_ctl = FDI_TX_CTL(pipe);
520 fdi_rx_ctl = FDI_RX_CTL(pipe);
521
522 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
523 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
524 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
525 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
526 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
527 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
528 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
529 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
530 } else {
695fbc08 531 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
04d348ae
ZW		 532 return -EINVAL;
533 }
534
535 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
536 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
537
538 /* If imr bit has been masked */
539 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
540 return 0;
541
542 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
543 == fdi_tx_check_bits)
544 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
545 == fdi_rx_check_bits))
546 return 1;
547 else
548 return 0;
549}
550
551#define INVALID_INDEX (~0U)
552
553static unsigned int calc_index(unsigned int offset, unsigned int start,
554 unsigned int next, unsigned int end, i915_reg_t i915_end)
555{
556 unsigned int range = next - start;
557
558 if (!end)
559 end = i915_mmio_reg_offset(i915_end);
560 if (offset < start || offset > end)
561 return INVALID_INDEX;
562 offset -= start;
563 return offset / range;
564}
565
566#define FDI_RX_CTL_TO_PIPE(offset) \
567 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
568
569#define FDI_TX_CTL_TO_PIPE(offset) \
570 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
571
572#define FDI_RX_IMR_TO_PIPE(offset) \
573 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
574
575static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
576 unsigned int offset, void *p_data, unsigned int bytes)
577{
578 i915_reg_t fdi_rx_iir;
579 unsigned int index;
580 int ret;
581
582 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
583 index = FDI_RX_CTL_TO_PIPE(offset);
584 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
585 index = FDI_TX_CTL_TO_PIPE(offset);
586 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
587 index = FDI_RX_IMR_TO_PIPE(offset);
588 else {
695fbc08 589 gvt_vgpu_err("Unsupport registers %x\n", offset);
04d348ae
ZW		 590 return -EINVAL;
591 }
592
593 write_vreg(vgpu, offset, p_data, bytes);
594
595 fdi_rx_iir = FDI_RX_IIR(index);
596
597 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
598 if (ret < 0)
599 return ret;
600 if (ret)
601 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
602
603 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
604 if (ret < 0)
605 return ret;
606 if (ret)
607 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
608
609 if (offset == _FDI_RXA_CTL)
610 if (fdi_auto_training_started(vgpu))
611 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
612 DP_TP_STATUS_AUTOTRAIN_DONE;
613 return 0;
614}
615
616#define DP_TP_CTL_TO_PORT(offset) \
617 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
618
619static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
620 void *p_data, unsigned int bytes)
621{
622 i915_reg_t status_reg;
623 unsigned int index;
624 u32 data;
625
626 write_vreg(vgpu, offset, p_data, bytes);
627
628 index = DP_TP_CTL_TO_PORT(offset);
629 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
630 if (data == 0x2) {
631 status_reg = DP_TP_STATUS(index);
632 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
633 }
634 return 0;
635}
636
637static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
638 unsigned int offset, void *p_data, unsigned int bytes)
639{
640 u32 reg_val;
641 u32 sticky_mask;
642
643 reg_val = *((u32 *)p_data);
644 sticky_mask = GENMASK(27, 26) | (1 << 24);
645
646 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
647 (vgpu_vreg(vgpu, offset) & sticky_mask);
648 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
649 return 0;
650}
651
652static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
653 unsigned int offset, void *p_data, unsigned int bytes)
654{
655 u32 data;
656
657 write_vreg(vgpu, offset, p_data, bytes);
658 data = vgpu_vreg(vgpu, offset);
659
660 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
661 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
662 return 0;
663}
664
665static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
666 unsigned int offset, void *p_data, unsigned int bytes)
667{
668 u32 data;
669
670 write_vreg(vgpu, offset, p_data, bytes);
671 data = vgpu_vreg(vgpu, offset);
672
673 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
674 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
675 else
676 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
677 return 0;
678}
679
680#define DSPSURF_TO_PIPE(offset) \
681 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
682
683static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
684 void *p_data, unsigned int bytes)
685{
686 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
687 unsigned int index = DSPSURF_TO_PIPE(offset);
688 i915_reg_t surflive_reg = DSPSURFLIVE(index);
689 int flip_event[] = {
690 [PIPE_A] = PRIMARY_A_FLIP_DONE,
691 [PIPE_B] = PRIMARY_B_FLIP_DONE,
692 [PIPE_C] = PRIMARY_C_FLIP_DONE,
693 };
694
695 write_vreg(vgpu, offset, p_data, bytes);
696 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
697
698 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
699 return 0;
700}
701
702#define SPRSURF_TO_PIPE(offset) \
703 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
704
705static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
706 void *p_data, unsigned int bytes)
707{
708 unsigned int index = SPRSURF_TO_PIPE(offset);
709 i915_reg_t surflive_reg = SPRSURFLIVE(index);
710 int flip_event[] = {
711 [PIPE_A] = SPRITE_A_FLIP_DONE,
712 [PIPE_B] = SPRITE_B_FLIP_DONE,
713 [PIPE_C] = SPRITE_C_FLIP_DONE,
714 };
715
716 write_vreg(vgpu, offset, p_data, bytes);
717 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
718
719 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
720 return 0;
721}
722
723static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
724 unsigned int reg)
725{
726 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
727 enum intel_gvt_event_type event;
728
729 if (reg == _DPA_AUX_CH_CTL)
730 event = AUX_CHANNEL_A;
731 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
732 event = AUX_CHANNEL_B;
733 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
734 event = AUX_CHANNEL_C;
735 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
736 event = AUX_CHANNEL_D;
737 else {
738 WARN_ON(true);
739 return -EINVAL;
740 }
741
742 intel_vgpu_trigger_virtual_event(vgpu, event);
743 return 0;
744}
745
746static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
747 unsigned int reg, int len, bool data_valid)
748{
749 /* mark transaction done */
750 value |= DP_AUX_CH_CTL_DONE;
751 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
752 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
753
754 if (data_valid)
755 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
756 else
757 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
758
759 /* message size */
760 value &= ~(0xf << 20);
761 value |= (len << 20);
762 vgpu_vreg(vgpu, reg) = value;
763
764 if (value & DP_AUX_CH_CTL_INTERRUPT)
765 return trigger_aux_channel_interrupt(vgpu, reg);
766 return 0;
767}
768
769static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
770 uint8_t t)
771{
772 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
773 /* training pattern 1 for CR */
774 /* set LANE0_CR_DONE, LANE1_CR_DONE */
775 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
776 /* set LANE2_CR_DONE, LANE3_CR_DONE */
777 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
778 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
779 DPCD_TRAINING_PATTERN_2) {
780 /* training pattern 2 for EQ */
781 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
782 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
783 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
784 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
785 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
786 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
787 /* set INTERLANE_ALIGN_DONE */
788 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
789 DPCD_INTERLANE_ALIGN_DONE;
790 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
791 DPCD_LINK_TRAINING_DISABLED) {
792 /* finish link training */
793 /* set sink status as synchronized */
794 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
795 }
796}
797
798#define _REG_HSW_DP_AUX_CH_CTL(dp) \
799 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
800
801#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
802
803#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
804
805#define dpy_is_valid_port(port) \
806 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
807
808static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
809 unsigned int offset, void *p_data, unsigned int bytes)
810{
811 struct intel_vgpu_display *display = &vgpu->display;
812 int msg, addr, ctrl, op, len;
813 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
814 struct intel_vgpu_dpcd_data *dpcd = NULL;
815 struct intel_vgpu_port *port = NULL;
816 u32 data;
817
818 if (!dpy_is_valid_port(port_index)) {
695fbc08 819 gvt_vgpu_err("Unsupported DP port access!\n");
04d348ae
ZW		 820 return 0;
821 }
822
823 write_vreg(vgpu, offset, p_data, bytes);
824 data = vgpu_vreg(vgpu, offset);
825
826 if (IS_SKYLAKE(vgpu->gvt->dev_priv) &&
827 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
828 /* SKL DPB/C/D aux ctl register changed */
829 return 0;
830 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
831 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
832 /* write to the data registers */
833 return 0;
834 }
835
836 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
837 /* just want to clear the sticky bits */
838 vgpu_vreg(vgpu, offset) = 0;
839 return 0;
840 }
841
842 port = &display->ports[port_index];
843 dpcd = port->dpcd;
844
845 /* read out message from DATA1 register */
846 msg = vgpu_vreg(vgpu, offset + 4);
847 addr = (msg >> 8) & 0xffff;
848 ctrl = (msg >> 24) & 0xff;
849 len = msg & 0xff;
850 op = ctrl >> 4;
851
852 if (op == GVT_AUX_NATIVE_WRITE) {
853 int t;
854 uint8_t buf[16];
855
856 if ((addr + len + 1) >= DPCD_SIZE) {
857 /*
858 * Write request exceeds what we supported,
859 * DCPD spec: When a Source Device is writing a DPCD
860 * address not supported by the Sink Device, the Sink
861 * Device shall reply with AUX NACK and “M” equal to
862 * zero.
863 */
864
865 /* NAK the write */
866 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
867 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
868 return 0;
869 }
870
871 /*
872 * Write request format: (command + address) occupies
873 * 3 bytes, followed by (len + 1) bytes of data.
874 */
875 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
876 return -EINVAL;
877
878 /* unpack data from vreg to buf */
879 for (t = 0; t < 4; t++) {
880 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
881
882 buf[t * 4] = (r >> 24) & 0xff;
883 buf[t * 4 + 1] = (r >> 16) & 0xff;
884 buf[t * 4 + 2] = (r >> 8) & 0xff;
885 buf[t * 4 + 3] = r & 0xff;
886 }
887
888 /* write to virtual DPCD */
889 if (dpcd && dpcd->data_valid) {
890 for (t = 0; t <= len; t++) {
891 int p = addr + t;
892
893 dpcd->data[p] = buf[t];
894 /* check for link training */
895 if (p == DPCD_TRAINING_PATTERN_SET)
896 dp_aux_ch_ctl_link_training(dpcd,
897 buf[t]);
898 }
899 }
900
901 /* ACK the write */
902 vgpu_vreg(vgpu, offset + 4) = 0;
903 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
904 dpcd && dpcd->data_valid);
905 return 0;
906 }
907
908 if (op == GVT_AUX_NATIVE_READ) {
909 int idx, i, ret = 0;
910
911 if ((addr + len + 1) >= DPCD_SIZE) {
912 /*
913 * read request exceeds what we supported
914 * DPCD spec: A Sink Device receiving a Native AUX CH
915 * read request for an unsupported DPCD address must
916 * reply with an AUX ACK and read data set equal to
917 * zero instead of replying with AUX NACK.
918 */
919
920 /* ACK the READ*/
921 vgpu_vreg(vgpu, offset + 4) = 0;
922 vgpu_vreg(vgpu, offset + 8) = 0;
923 vgpu_vreg(vgpu, offset + 12) = 0;
924 vgpu_vreg(vgpu, offset + 16) = 0;
925 vgpu_vreg(vgpu, offset + 20) = 0;
926
927 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
928 true);
929 return 0;
930 }
931
932 for (idx = 1; idx <= 5; idx++) {
933 /* clear the data registers */
934 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
935 }
936
937 /*
938 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
939 */
940 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
941 return -EINVAL;
942
943 /* read from virtual DPCD to vreg */
944 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
945 if (dpcd && dpcd->data_valid) {
946 for (i = 1; i <= (len + 1); i++) {
947 int t;
948
949 t = dpcd->data[addr + i - 1];
950 t <<= (24 - 8 * (i % 4));
951 ret |= t;
952
953 if ((i % 4 == 3) || (i == (len + 1))) {
954 vgpu_vreg(vgpu, offset +
955 (i / 4 + 1) * 4) = ret;
956 ret = 0;
957 }
958 }
959 }
960 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
961 dpcd && dpcd->data_valid);
962 return 0;
963 }
964
965 /* i2c transaction starts */
966 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
967
968 if (data & DP_AUX_CH_CTL_INTERRUPT)
969 trigger_aux_channel_interrupt(vgpu, offset);
970 return 0;
971}
972
975629c3
PZ		 973static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
974 void *p_data, unsigned int bytes)
975{
976 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
977 write_vreg(vgpu, offset, p_data, bytes);
978 return 0;
979}
980
04d348ae
ZW		 981static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
982 void *p_data, unsigned int bytes)
983{
984 bool vga_disable;
985
986 write_vreg(vgpu, offset, p_data, bytes);
987 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
988
989 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
990 vga_disable ? "Disable" : "Enable");
991 return 0;
992}
993
994static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
995 unsigned int sbi_offset)
996{
997 struct intel_vgpu_display *display = &vgpu->display;
998 int num = display->sbi.number;
999 int i;
1000
1001 for (i = 0; i < num; ++i)
1002 if (display->sbi.registers[i].offset == sbi_offset)
1003 break;
1004
1005 if (i == num)
1006 return 0;
1007
1008 return display->sbi.registers[i].value;
1009}
1010
1011static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1012 unsigned int offset, u32 value)
1013{
1014 struct intel_vgpu_display *display = &vgpu->display;
1015 int num = display->sbi.number;
1016 int i;
1017
1018 for (i = 0; i < num; ++i) {
1019 if (display->sbi.registers[i].offset == offset)
1020 break;
1021 }
1022
1023 if (i == num) {
1024 if (num == SBI_REG_MAX) {
695fbc08 1025 gvt_vgpu_err("SBI caching meets maximum limits\n");
04d348ae
ZW		 1026 return;
1027 }
1028 display->sbi.number++;
1029 }
1030
1031 display->sbi.registers[i].offset = offset;
1032 display->sbi.registers[i].value = value;
1033}
1034
1035static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1036 void *p_data, unsigned int bytes)
1037{
1038 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1039 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1040 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1041 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1042 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1043 sbi_offset);
1044 }
1045 read_vreg(vgpu, offset, p_data, bytes);
1046 return 0;
1047}
1048
3e70c5d6 1049static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
04d348ae
ZW		 1050 void *p_data, unsigned int bytes)
1051{
1052 u32 data;
1053
1054 write_vreg(vgpu, offset, p_data, bytes);
1055 data = vgpu_vreg(vgpu, offset);
1056
1057 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1058 data |= SBI_READY;
1059
1060 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1061 data |= SBI_RESPONSE_SUCCESS;
1062
1063 vgpu_vreg(vgpu, offset) = data;
1064
1065 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1066 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1067 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1068 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1069
1070 write_virtual_sbi_register(vgpu, sbi_offset,
1071 vgpu_vreg(vgpu, SBI_DATA));
1072 }
1073 return 0;
1074}
1075
e39c5add
ZW		 1076#define _vgtif_reg(x) \
1077 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1078
1079static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1080 void *p_data, unsigned int bytes)
1081{
1082 bool invalid_read = false;
1083
1084 read_vreg(vgpu, offset, p_data, bytes);
1085
1086 switch (offset) {
1087 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1088 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1089 invalid_read = true;
1090 break;
1091 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1092 _vgtif_reg(avail_rs.fence_num):
1093 if (offset + bytes >
1094 _vgtif_reg(avail_rs.fence_num) + 4)
1095 invalid_read = true;
1096 break;
1097 case 0x78010: /* vgt_caps */
1098 case 0x7881c:
1099 break;
1100 default:
1101 invalid_read = true;
1102 break;
1103 }
1104 if (invalid_read)
695fbc08 1105 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
e39c5add 1106 offset, bytes, *(u32 *)p_data);
fd64be63 1107 vgpu->pv_notified = true;
e39c5add
ZW		 1108 return 0;
1109}
1110
1111static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1112{
1113 int ret = 0;
1114
1115 switch (notification) {
1116 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1117 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1118 break;
1119 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1120 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1121 break;
1122 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1123 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1124 break;
1125 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1126 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1127 break;
1128 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1129 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1130 case 1: /* Remove this in guest driver. */
1131 break;
1132 default:
695fbc08 1133 gvt_vgpu_err("Invalid PV notification %d\n", notification);
e39c5add
ZW		 1134 }
1135 return ret;
1136}
1137
04d348ae
ZW		 1138static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1139{
1140 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1141 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1142 char *env[3] = {NULL, NULL, NULL};
1143 char vmid_str[20];
1144 char display_ready_str[20];
1145
d8e9b2b9 1146 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
04d348ae
ZW		 1147 env[0] = display_ready_str;
1148
1149 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1150 env[1] = vmid_str;
1151
1152 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1153}
1154
e39c5add
ZW		 1155static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1156 void *p_data, unsigned int bytes)
1157{
1158 u32 data;
1159 int ret;
1160
1161 write_vreg(vgpu, offset, p_data, bytes);
1162 data = vgpu_vreg(vgpu, offset);
1163
1164 switch (offset) {
1165 case _vgtif_reg(display_ready):
04d348ae
ZW		 1166 send_display_ready_uevent(vgpu, data ? 1 : 0);
1167 break;
e39c5add
ZW		 1168 case _vgtif_reg(g2v_notify):
1169 ret = handle_g2v_notification(vgpu, data);
1170 break;
1171 /* add xhot and yhot to handled list to avoid error log */
1172 case 0x78830:
1173 case 0x78834:
1174 case _vgtif_reg(pdp[0].lo):
1175 case _vgtif_reg(pdp[0].hi):
1176 case _vgtif_reg(pdp[1].lo):
1177 case _vgtif_reg(pdp[1].hi):
1178 case _vgtif_reg(pdp[2].lo):
1179 case _vgtif_reg(pdp[2].hi):
1180 case _vgtif_reg(pdp[3].lo):
1181 case _vgtif_reg(pdp[3].hi):
1182 case _vgtif_reg(execlist_context_descriptor_lo):
1183 case _vgtif_reg(execlist_context_descriptor_hi):
1184 break;
a33fc7a0
MH		 1185 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1186 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1187 break;
e39c5add 1188 default:
695fbc08 1189 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
e39c5add
ZW		 1190 offset, bytes, data);
1191 break;
1192 }
1193 return 0;
1194}
1195
04d348ae
ZW		 1196static int pf_write(struct intel_vgpu *vgpu,
1197 unsigned int offset, void *p_data, unsigned int bytes)
1198{
1199 u32 val = *(u32 *)p_data;
1200
1201 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1202 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1203 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1204 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1205 vgpu->id);
1206 return 0;
1207 }
1208
1209 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1210}
1211
1212static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1213 unsigned int offset, void *p_data, unsigned int bytes)
1214{
1215 write_vreg(vgpu, offset, p_data, bytes);
1216
1217 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
1218 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
1219 else
1220 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
1221 return 0;
1222}
1223
e39c5add
ZW		 1224static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1225 unsigned int offset, void *p_data, unsigned int bytes)
1226{
1227 write_vreg(vgpu, offset, p_data, bytes);
1228
1229 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1230 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1231 return 0;
1232}
1233
1234static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1235 void *p_data, unsigned int bytes)
1236{
5f399f11
PG		 1237 u32 mode;
1238
1239 write_vreg(vgpu, offset, p_data, bytes);
1240 mode = vgpu_vreg(vgpu, offset);
e39c5add
ZW		 1241
1242 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1243 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
1244 vgpu->id);
1245 return 0;
1246 }
1247
1248 return 0;
1249}
1250
1251static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1252 void *p_data, unsigned int bytes)
1253{
1254 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1255 u32 trtte = *(u32 *)p_data;
1256
1257 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1258 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1259 vgpu->id);
1260 return -EINVAL;
1261 }
1262 write_vreg(vgpu, offset, p_data, bytes);
1263 /* TRTTE is not per-context */
1264 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1265
1266 return 0;
1267}
1268
1269static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1270 void *p_data, unsigned int bytes)
1271{
1272 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1273 u32 val = *(u32 *)p_data;
1274
1275 if (val & 1) {
1276 /* unblock hw logic */
1277 I915_WRITE(_MMIO(offset), val);
1278 }
1279 write_vreg(vgpu, offset, p_data, bytes);
1280 return 0;
1281}
1282
04d348ae
ZW		 1283static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1284 void *p_data, unsigned int bytes)
1285{
1286 u32 v = 0;
1287
1288 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1289 v |= (1 << 0);
1290
1291 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1292 v |= (1 << 8);
1293
1294 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1295 v |= (1 << 16);
1296
1297 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1298 v |= (1 << 24);
1299
1300 vgpu_vreg(vgpu, offset) = v;
1301
1302 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1303}
1304
1305static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1306 void *p_data, unsigned int bytes)
1307{
1308 u32 value = *(u32 *)p_data;
1309 u32 cmd = value & 0xff;
1310 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1311
1312 switch (cmd) {
8bcd7c18
WL		 1313 case GEN9_PCODE_READ_MEM_LATENCY:
1314 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
1315 /**
1316 * "Read memory latency" command on gen9.
1317 * Below memory latency values are read
1318 * from skylake platform.
1319 */
1320 if (!*data0)
1321 *data0 = 0x1e1a1100;
1322 else
1323 *data0 = 0x61514b3d;
1324 }
04d348ae 1325 break;
d8a355be 1326 case SKL_PCODE_CDCLK_CONTROL:
8bcd7c18
WL		 1327 if (IS_SKYLAKE(vgpu->gvt->dev_priv))
1328 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
d8a355be 1329 break;
8bcd7c18 1330 case GEN6_PCODE_READ_RC6VIDS:
04d348ae
ZW		 1331 *data0 |= 0x1;
1332 break;
1333 }
1334
1335 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1336 vgpu->id, value, *data0);
d8a355be
WL		 1337 /**
1338 * PCODE_READY clear means ready for pcode read/write,
1339 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1340 * always emulate as pcode read/write success and ready for access
1341 * anytime, since we don't touch real physical registers here.
1342 */
1343 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
04d348ae
ZW		 1344 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1345}
1346
1347static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1348 unsigned int offset, void *p_data, unsigned int bytes)
1349{
1350 u32 v = *(u32 *)p_data;
1351
1352 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1353 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1354 v |= (v >> 1);
1355
1356 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1357}
1358
1359static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1360 void *p_data, unsigned int bytes)
1361{
1362 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1363 i915_reg_t reg = {.reg = offset};
1364
1365 switch (offset) {
1366 case 0x4ddc:
1367 vgpu_vreg(vgpu, offset) = 0x8000003c;
d4362225 1368 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
955c1dd1 1369 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
04d348ae
ZW		 1370 break;
1371 case 0x42080:
1372 vgpu_vreg(vgpu, offset) = 0x8000;
d4362225 1373 /* WaCompressedResourceDisplayNewHashMode:skl */
955c1dd1 1374 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
04d348ae
ZW		 1375 break;
1376 default:
1377 return -EINVAL;
1378 }
1379
04d348ae
ZW		 1380 return 0;
1381}
1382
1383static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1384 void *p_data, unsigned int bytes)
1385{
1386 u32 v = *(u32 *)p_data;
1387
1388 /* other bits are MBZ. */
1389 v &= (1 << 31) | (1 << 30);
1390 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1391
1392 vgpu_vreg(vgpu, offset) = v;
1393
1394 return 0;
1395}
1396
1397static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1398 unsigned int offset, void *p_data, unsigned int bytes)
1399{
1400 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1401
1402 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1403 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1404}
1405
28c4c6ca
ZW		 1406static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1407 void *p_data, unsigned int bytes)
1408{
1409 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1410 struct intel_vgpu_execlist *execlist;
1411 u32 data = *(u32 *)p_data;
6fb5082a 1412 int ret = 0;
28c4c6ca 1413
0fac21e7 1414 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
28c4c6ca
ZW		 1415 return -EINVAL;
1416
1417 execlist = &vgpu->execlist[ring_id];
1418
1419 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data;
6fb5082a 1420 if (execlist->elsp_dwords.index == 3) {
28c4c6ca 1421 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
6fb5082a 1422 if(ret)
695fbc08
TZ		 1423 gvt_vgpu_err("fail submit workload on ring %d\n",
1424 ring_id);
6fb5082a 1425 }
28c4c6ca
ZW		 1426
1427 ++execlist->elsp_dwords.index;
1428 execlist->elsp_dwords.index &= 0x3;
6fb5082a 1429 return ret;
28c4c6ca
ZW		 1430}
1431
4b63960e
ZW		 1432static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1433 void *p_data, unsigned int bytes)
1434{
1435 u32 data = *(u32 *)p_data;
1436 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1437 bool enable_execlist;
1438
1439 write_vreg(vgpu, offset, p_data, bytes);
fd64be63
MH		 1440
1441 /* when PPGTT mode enabled, we will check if guest has called
1442 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1443 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1444 */
1445 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1446 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1447 && !vgpu->pv_notified) {
1448 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1449 return 0;
1450 }
4b63960e
ZW		 1451 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1452 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1453 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1454
1455 gvt_dbg_core("EXECLIST %s on ring %d\n",
1456 (enable_execlist ? "enabling" : "disabling"),
1457 ring_id);
1458
1459 if (enable_execlist)
1460 intel_vgpu_start_schedule(vgpu);
1461 }
1462 return 0;
1463}
1464
17865713
ZW		 1465static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1466 unsigned int offset, void *p_data, unsigned int bytes)
1467{
17865713
ZW		 1468 unsigned int id = 0;
1469
f24940e0 1470 write_vreg(vgpu, offset, p_data, bytes);
4f3f1aed 1471 vgpu_vreg(vgpu, offset) = 0;
f24940e0 1472
17865713
ZW		 1473 switch (offset) {
1474 case 0x4260:
1475 id = RCS;
1476 break;
1477 case 0x4264:
1478 id = VCS;
1479 break;
1480 case 0x4268:
1481 id = VCS2;
1482 break;
1483 case 0x426c:
1484 id = BCS;
1485 break;
1486 case 0x4270:
1487 id = VECS;
1488 break;
1489 default:
a1201053 1490 return -EINVAL;
17865713
ZW		 1491 }
1492 set_bit(id, (void *)vgpu->tlb_handle_pending);
1493
a1201053 1494 return 0;
17865713
ZW		 1495}
1496
2fb39fad
DC		 1497static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1498 unsigned int offset, void *p_data, unsigned int bytes)
1499{
1500 u32 data;
1501
1502 write_vreg(vgpu, offset, p_data, bytes);
1503 data = vgpu_vreg(vgpu, offset);
1504
1505 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1506 data |= RESET_CTL_READY_TO_RESET;
1507 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1508 data &= ~RESET_CTL_READY_TO_RESET;
1509
1510 vgpu_vreg(vgpu, offset) = data;
1511 return 0;
1512}
1513
12d14cc4
ZW		 1514#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1515 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1516 f, s, am, rm, d, r, w); \
1517 if (ret) \
1518 return ret; \
1519} while (0)
1520
1521#define MMIO_D(reg, d) \
1522 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1523
1524#define MMIO_DH(reg, d, r, w) \
1525 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1526
1527#define MMIO_DFH(reg, d, f, r, w) \
1528 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1529
1530#define MMIO_GM(reg, d, r, w) \
1531 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1532
0aa5277c
ZY		 1533#define MMIO_GM_RDR(reg, d, r, w) \
1534 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1535
12d14cc4
ZW		 1536#define MMIO_RO(reg, d, f, rm, r, w) \
1537 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1538
1539#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1540 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1541 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1542 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1543 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1544} while (0)
1545
1546#define MMIO_RING_D(prefix, d) \
1547 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1548
1549#define MMIO_RING_DFH(prefix, d, f, r, w) \
1550 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1551
1552#define MMIO_RING_GM(prefix, d, r, w) \
1553 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1554
0aa5277c
ZY		 1555#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1556 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1557
12d14cc4
ZW		 1558#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1559 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1560
1561static int init_generic_mmio_info(struct intel_gvt *gvt)
1562{
e39c5add 1563 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 1564 int ret;
1565
0aa5277c
ZY		 1566 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1567 intel_vgpu_reg_imr_handler);
e39c5add
ZW		 1568
1569 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1570 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1571 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1572 MMIO_D(SDEISR, D_ALL);
1573
0aa5277c 1574 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 1575
0aa5277c
ZY		 1576 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1577 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1578 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1579 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
e39c5add
ZW		 1580
1581#define RING_REG(base) (base + 0x28)
0aa5277c 1582 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1583#undef RING_REG
1584
1585#define RING_REG(base) (base + 0x134)
0aa5277c 1586 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1587#undef RING_REG
1588
0aa5277c
ZY		 1589 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1590 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1591 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
e39c5add
ZW		 1592 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1593
0aa5277c
ZY		 1594 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1595 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1596 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1597 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1598 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
e39c5add
ZW		 1599
1600 /* RING MODE */
1601#define RING_REG(base) (base + 0x29c)
0aa5277c
ZY		 1602 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1603 ring_mode_mmio_write);
e39c5add
ZW		 1604#undef RING_REG
1605
0aa5277c
ZY		 1606 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1607 NULL, NULL);
41bfab35
PZ		 1608 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1609 NULL, NULL);
04d348ae
ZW		 1610 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1611 ring_timestamp_mmio_read, NULL);
1612 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1613 ring_timestamp_mmio_read, NULL);
e39c5add 1614
0aa5277c
ZY		 1615 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1616 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1617 NULL, NULL);
a045fba4 1618 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 1619 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1620 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1621
1622 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1623 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1624 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1625 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1626 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1627 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1628 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1629 NULL, NULL);
a045fba4 1630 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 1631 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1632 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1633 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1634 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1635 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1636 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1637 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1638 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 1639 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
187447a1 1640 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1641
1642 /* display */
1643 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1644 MMIO_D(0x602a0, D_ALL);
1645
1646 MMIO_D(0x65050, D_ALL);
1647 MMIO_D(0x650b4, D_ALL);
1648
1649 MMIO_D(0xc4040, D_ALL);
1650 MMIO_D(DERRMR, D_ALL);
1651
1652 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1653 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1654 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1655 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1656
04d348ae
ZW		 1657 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1658 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1659 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1660 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
e39c5add
ZW		 1661
1662 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1663 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1664 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1665 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1666
1667 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1668 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1669 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1670 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1671
1672 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1673 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1674 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1675 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1676
1677 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1678 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1679 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1680
1681 MMIO_D(CURPOS(PIPE_A), D_ALL);
1682 MMIO_D(CURPOS(PIPE_B), D_ALL);
1683 MMIO_D(CURPOS(PIPE_C), D_ALL);
1684
1685 MMIO_D(CURBASE(PIPE_A), D_ALL);
1686 MMIO_D(CURBASE(PIPE_B), D_ALL);
1687 MMIO_D(CURBASE(PIPE_C), D_ALL);
1688
1689 MMIO_D(0x700ac, D_ALL);
1690 MMIO_D(0x710ac, D_ALL);
1691 MMIO_D(0x720ac, D_ALL);
1692
1693 MMIO_D(0x70090, D_ALL);
1694 MMIO_D(0x70094, D_ALL);
1695 MMIO_D(0x70098, D_ALL);
1696 MMIO_D(0x7009c, D_ALL);
1697
1698 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1699 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1700 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1701 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1702 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
04d348ae 1703 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1704 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1705 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1706
1707 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1708 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1709 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1710 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1711 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
04d348ae 1712 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1713 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1714 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1715
1716 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1717 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1718 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1719 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1720 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
04d348ae 1721 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 1722 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1723 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1724
1725 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1726 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1727 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1728 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1729 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1730 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1731 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
04d348ae 1732 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1733 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1734 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1735 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1736 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1737
1738 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1739 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1740 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1741 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1742 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1743 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1744 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
04d348ae 1745 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1746 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1747 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1748 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1749 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1750
1751 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1752 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1753 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1754 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1755 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1756 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1757 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
04d348ae 1758 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 1759 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1760 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1761 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1762 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1763
1764 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1765 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1766 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1767
1768 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1769 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1770 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1771 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1772 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1773 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1774 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1775 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1776 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1777
1778 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1779 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1780 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1781 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1782 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1783 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1784 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1785 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1786 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1787
1788 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1789 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1790 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1791 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1792 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1793 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1794 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1795 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1796 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1797
1798 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1799 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1800 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1801 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1802 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1803 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1804 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1805 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1806
1807 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1808 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1809 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1810 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1811 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1812 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1813 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1814 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1815
1816 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1817 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1818 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1819 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1820 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1821 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1822 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1823 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1824
1825 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1826 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1827 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1828 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1829 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1830 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1831 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1832 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1833
1834 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1835 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1836 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1837 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1838 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1839 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1840 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1841 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1842
1843 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1844 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1845 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1846 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1847 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1848
1849 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1850 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1851 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1852 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1853 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1854
1855 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1856 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1857 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1858 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1859 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1860
1861 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1862 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1863 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1864 MMIO_D(WM1_LP_ILK, D_ALL);
1865 MMIO_D(WM2_LP_ILK, D_ALL);
1866 MMIO_D(WM3_LP_ILK, D_ALL);
1867 MMIO_D(WM1S_LP_ILK, D_ALL);
1868 MMIO_D(WM2S_LP_IVB, D_ALL);
1869 MMIO_D(WM3S_LP_IVB, D_ALL);
1870
1871 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1872 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1873 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1874 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1875
1876 MMIO_D(0x48268, D_ALL);
1877
04d348ae
ZW		 1878 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1879 gmbus_mmio_write);
1880 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 1881 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1882
04d348ae
ZW		 1883 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1884 dp_aux_ch_ctl_mmio_write);
1885 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1886 dp_aux_ch_ctl_mmio_write);
1887 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1888 dp_aux_ch_ctl_mmio_write);
e39c5add 1889
04d348ae 1890 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
e39c5add 1891
04d348ae
ZW		 1892 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1893 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
e39c5add 1894
04d348ae
ZW		 1895 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1896 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1897 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1898 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1899 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1900 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1901 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1902 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1903 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
e39c5add
ZW		 1904
1905 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1906 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1907 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1908 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1909 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1910 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1911 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1912
1913 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1914 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1915 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1916 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1917 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1918 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1919 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1920
1921 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1922 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1923 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1924 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1925 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1926 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1927 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1928 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1929
1930 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1931 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1932 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1933
1934 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1935 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1936 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1937
1938 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1939 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1940 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1941
1942 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1943 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1944 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1945
1946 MMIO_D(_FDI_RXA_MISC, D_ALL);
1947 MMIO_D(_FDI_RXB_MISC, D_ALL);
1948 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1949 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1950 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1951 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1952
04d348ae 1953 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
e39c5add
ZW		 1954 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1955 MMIO_D(PCH_PP_STATUS, D_ALL);
1956 MMIO_D(PCH_LVDS, D_ALL);
1957 MMIO_D(_PCH_DPLL_A, D_ALL);
1958 MMIO_D(_PCH_DPLL_B, D_ALL);
1959 MMIO_D(_PCH_FPA0, D_ALL);
1960 MMIO_D(_PCH_FPA1, D_ALL);
1961 MMIO_D(_PCH_FPB0, D_ALL);
1962 MMIO_D(_PCH_FPB1, D_ALL);
1963 MMIO_D(PCH_DREF_CONTROL, D_ALL);
1964 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
1965 MMIO_D(PCH_DPLL_SEL, D_ALL);
1966
1967 MMIO_D(0x61208, D_ALL);
1968 MMIO_D(0x6120c, D_ALL);
1969 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
1970 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
1971
04d348ae
ZW		 1972 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
1973 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
1974 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
1975 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
1976 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
1977 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
e39c5add
ZW		 1978
1979 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
1980 PORTA_HOTPLUG_STATUS_MASK
1981 | PORTB_HOTPLUG_STATUS_MASK
1982 | PORTC_HOTPLUG_STATUS_MASK
1983 | PORTD_HOTPLUG_STATUS_MASK,
1984 NULL, NULL);
1985
04d348ae 1986 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
e39c5add
ZW		 1987 MMIO_D(FUSE_STRAP, D_ALL);
1988 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
1989
1990 MMIO_D(DISP_ARB_CTL, D_ALL);
1991 MMIO_D(DISP_ARB_CTL2, D_ALL);
1992
1993 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
1994 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
1995 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
1996
1997 MMIO_D(SOUTH_CHICKEN1, D_ALL);
04d348ae 1998 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
e39c5add
ZW		 1999 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
2000 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
2001 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2002 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
2003 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
2004
2005 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2006 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2007 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2008 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2009 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2010 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2011 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2012
2013 MMIO_D(IPS_CTL, D_ALL);
2014
2015 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2016 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2017 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2018 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2019 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2020 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2021 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2022 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2023 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2024 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2025 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2026 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2027 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2028
2029 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2030 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2031 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2032 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2033 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2034 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2035 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2036 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2037 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2038 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2039 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2040 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2041 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2042
2043 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2044 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2045 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2046 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2047 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2048 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2049 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2050 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2051 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2052 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2053 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2054 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2055 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2056
04d348ae
ZW		 2057 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2058 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2059 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2060
2061 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2062 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2063 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2064
2065 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2066 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2067 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2068
e39c5add
ZW		 2069 MMIO_D(0x60110, D_ALL);
2070 MMIO_D(0x61110, D_ALL);
2071 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2072 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2073 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2074 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2075 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2076 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2077 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2078 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2079 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2080
2081 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2082 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2083 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2084 MMIO_D(SPLL_CTL, D_ALL);
2085 MMIO_D(_WRPLL_CTL1, D_ALL);
2086 MMIO_D(_WRPLL_CTL2, D_ALL);
2087 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2088 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2089 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2090 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2091 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2092 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2093 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2094 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2095
2096 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2097 MMIO_D(0x46508, D_ALL);
2098
2099 MMIO_D(0x49080, D_ALL);
2100 MMIO_D(0x49180, D_ALL);
2101 MMIO_D(0x49280, D_ALL);
2102
2103 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2104 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2105 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2106
2107 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2108 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2109 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2110
e39c5add
ZW		 2111 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2112 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2113 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2114
2115 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2116 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2117 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2118
2119 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2120 MMIO_D(SBI_ADDR, D_ALL);
04d348ae
ZW		 2121 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2122 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
e39c5add
ZW		 2123 MMIO_D(PIXCLK_GATE, D_ALL);
2124
04d348ae
ZW		 2125 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2126 dp_aux_ch_ctl_mmio_write);
2127
2128 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2129 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2130 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2131 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2132 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2133
2134 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2135 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2136 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2137 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2138 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2139
2140 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2141 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2142 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2143 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2144 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
e39c5add
ZW		 2145
2146 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2147 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2148 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2149 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2150 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2151
2152 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2153 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2154
2155 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2156 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2157 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2158 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2159
2160 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2161 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2162 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2163 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2164
2165 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2166 MMIO_D(FORCEWAKE_ACK, D_ALL);
2167 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2168 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
0aa5277c
ZY		 2169 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2170 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2171 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2172 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL);
2173 MMIO_D(ECOBUS, D_ALL);
2174 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2175 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2176 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2177 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2178 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2179 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2180 MMIO_D(GEN6_RPSTAT1, D_ALL);
2181 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2182 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2183 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2184 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2185 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2186 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2187 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2188 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2189 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2190 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2191 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2192 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2193 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2194 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2195 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2196 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2197 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2198 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2199 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2200 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2201 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2202 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2203 MMIO_D(GEN6_PMINTRMSK, D_ALL);
04d348ae
ZW		 2204 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2205 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2206 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2207 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2208 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2209 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
e39c5add
ZW		 2210
2211 MMIO_D(RSTDBYCTL, D_ALL);
2212
2213 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2214 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2215 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
04d348ae 2216 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
e39c5add
ZW		 2217
2218 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL);
2219
2220 MMIO_D(TILECTL, D_ALL);
2221
2222 MMIO_D(GEN6_UCGCTL1, D_ALL);
2223 MMIO_D(GEN6_UCGCTL2, D_ALL);
2224
2225 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2226
8bcd7c18 2227 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_BDW);
e39c5add
ZW		 2228 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2229 MMIO_D(0x13812c, D_ALL);
2230 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2231 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2232 MMIO_D(HSW_IDICR, D_ALL);
2233 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2234
2235 MMIO_D(0x3c, D_ALL);
2236 MMIO_D(0x860, D_ALL);
2237 MMIO_D(ECOSKPD, D_ALL);
2238 MMIO_D(0x121d0, D_ALL);
2239 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2240 MMIO_D(0x41d0, D_ALL);
2241 MMIO_D(GAC_ECO_BITS, D_ALL);
2242 MMIO_D(0x6200, D_ALL);
2243 MMIO_D(0x6204, D_ALL);
2244 MMIO_D(0x6208, D_ALL);
2245 MMIO_D(0x7118, D_ALL);
2246 MMIO_D(0x7180, D_ALL);
2247 MMIO_D(0x7408, D_ALL);
2248 MMIO_D(0x7c00, D_ALL);
975629c3 2249 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
e39c5add
ZW		 2250 MMIO_D(0x911c, D_ALL);
2251 MMIO_D(0x9120, D_ALL);
a045fba4 2252 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2253
2254 MMIO_D(GAB_CTL, D_ALL);
2255 MMIO_D(0x48800, D_ALL);
2256 MMIO_D(0xce044, D_ALL);
2257 MMIO_D(0xe6500, D_ALL);
2258 MMIO_D(0xe6504, D_ALL);
2259 MMIO_D(0xe6600, D_ALL);
2260 MMIO_D(0xe6604, D_ALL);
2261 MMIO_D(0xe6700, D_ALL);
2262 MMIO_D(0xe6704, D_ALL);
2263 MMIO_D(0xe6800, D_ALL);
2264 MMIO_D(0xe6804, D_ALL);
2265 MMIO_D(PCH_GMBUS4, D_ALL);
2266 MMIO_D(PCH_GMBUS5, D_ALL);
2267
2268 MMIO_D(0x902c, D_ALL);
2269 MMIO_D(0xec008, D_ALL);
2270 MMIO_D(0xec00c, D_ALL);
2271 MMIO_D(0xec008 + 0x18, D_ALL);
2272 MMIO_D(0xec00c + 0x18, D_ALL);
2273 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2274 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2275 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2276 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2277 MMIO_D(0xec408, D_ALL);
2278 MMIO_D(0xec40c, D_ALL);
2279 MMIO_D(0xec408 + 0x18, D_ALL);
2280 MMIO_D(0xec40c + 0x18, D_ALL);
2281 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2282 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2283 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2284 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2285 MMIO_D(0xfc810, D_ALL);
2286 MMIO_D(0xfc81c, D_ALL);
2287 MMIO_D(0xfc828, D_ALL);
2288 MMIO_D(0xfc834, D_ALL);
2289 MMIO_D(0xfcc00, D_ALL);
2290 MMIO_D(0xfcc0c, D_ALL);
2291 MMIO_D(0xfcc18, D_ALL);
2292 MMIO_D(0xfcc24, D_ALL);
2293 MMIO_D(0xfd000, D_ALL);
2294 MMIO_D(0xfd00c, D_ALL);
2295 MMIO_D(0xfd018, D_ALL);
2296 MMIO_D(0xfd024, D_ALL);
2297 MMIO_D(0xfd034, D_ALL);
2298
2299 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2300 MMIO_D(0x2054, D_ALL);
2301 MMIO_D(0x12054, D_ALL);
2302 MMIO_D(0x22054, D_ALL);
2303 MMIO_D(0x1a054, D_ALL);
2304
2305 MMIO_D(0x44070, D_ALL);
41bfab35 2306 MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2307 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2308 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2309 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2310 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2311
0aa5277c
ZY		 2312 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_HSW_PLUS, NULL, NULL);
2313 MMIO_DFH(GEN7_OACONTROL, D_HSW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2314 MMIO_D(0x2b00, D_BDW_PLUS);
2315 MMIO_D(0x2360, D_BDW_PLUS);
0aa5277c
ZY		 2316 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2317 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2318 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2319
2320 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2321 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2322 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2323
2324 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2325 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2326 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2327 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2328 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2329 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2330 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2331 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2332 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2333 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2334 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
17865713
ZW		 2335 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2336 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2337 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2338 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2339 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
e39c5add
ZW		 2340 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2341
9112caaf
ZY		 2342 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2343 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2344 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2345 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2346 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2347 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2348 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2349 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2350 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2351 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2352 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2353 return 0;
2354}
2355
2356static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2357{
e39c5add 2358 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 2359 int ret;
2360
0aa5277c 2361 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
e39c5add
ZW		 2362 intel_vgpu_reg_imr_handler);
2363
2364 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2365 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2366 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2367 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2368
2369 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2370 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2371 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2372 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2373
2374 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2375 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2376 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2377 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2378
2379 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2380 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2381 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2382 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2383
2384 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2385 intel_vgpu_reg_imr_handler);
2386 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2387 intel_vgpu_reg_ier_handler);
2388 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2389 intel_vgpu_reg_iir_handler);
2390 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2391
2392 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2393 intel_vgpu_reg_imr_handler);
2394 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2395 intel_vgpu_reg_ier_handler);
2396 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2397 intel_vgpu_reg_iir_handler);
2398 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2399
2400 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2401 intel_vgpu_reg_imr_handler);
2402 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2403 intel_vgpu_reg_ier_handler);
2404 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2405 intel_vgpu_reg_iir_handler);
2406 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2407
2408 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2409 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2410 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2411 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2412
2413 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2414 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2415 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2416 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2417
2418 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2419 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2420 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2421 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2422
2423 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2424 intel_vgpu_reg_master_irq_handler);
2425
0aa5277c
ZY		 2426 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2427 F_CMD_ACCESS, NULL, NULL);
2428 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2429
2430 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2431 NULL, NULL);
2432 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2433 F_CMD_ACCESS, NULL, NULL);
2434 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2435 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2436 NULL, NULL);
2437 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2438 F_CMD_ACCESS, NULL, NULL);
2439 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2440 F_CMD_ACCESS, NULL, NULL);
2441 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2442 ring_mode_mmio_write);
2443 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2444 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2445 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2446 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
04d348ae
ZW		 2447 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2448 ring_timestamp_mmio_read, NULL);
e39c5add 2449
0aa5277c 2450 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2451
2fb39fad
DC		 2452#define RING_REG(base) (base + 0xd0)
2453 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2454 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2455 ring_reset_ctl_write);
2456 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2457 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2458 ring_reset_ctl_write);
2459#undef RING_REG
2460
e39c5add 2461#define RING_REG(base) (base + 0x230)
28c4c6ca
ZW		 2462 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2463 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
e39c5add
ZW		 2464#undef RING_REG
2465
2466#define RING_REG(base) (base + 0x234)
0aa5277c
ZY		 2467 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2468 NULL, NULL);
2469 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2470 ~0LL, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2471#undef RING_REG
2472
2473#define RING_REG(base) (base + 0x244)
0aa5277c
ZY		 2474 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2475 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2476 NULL, NULL);
e39c5add
ZW		 2477#undef RING_REG
2478
2479#define RING_REG(base) (base + 0x370)
2480 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2481 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2482 NULL, NULL);
2483#undef RING_REG
2484
2485#define RING_REG(base) (base + 0x3a0)
2486 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2487 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2488#undef RING_REG
2489
2490 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2491 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2492 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2493 MMIO_D(0x1c1d0, D_BDW_PLUS);
2494 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2495 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2496 MMIO_D(0x1c054, D_BDW_PLUS);
2497
8bcd7c18
WL		 2498 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2499
e39c5add
ZW		 2500 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2501 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2502
2503 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2504
2505#define RING_REG(base) (base + 0x270)
2506 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2507 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2508#undef RING_REG
2509
0aa5277c
ZY		 2510 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2511 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
e39c5add 2512
a045fba4 2513 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2514
593e59b4
ZY		 2515 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2516 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2517 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
e39c5add
ZW		 2518
2519 MMIO_D(WM_MISC, D_BDW);
2520 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2521
2522 MMIO_D(0x66c00, D_BDW_PLUS);
2523 MMIO_D(0x66c04, D_BDW_PLUS);
2524
2525 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2526
2527 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2528 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2529 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2530
593e59b4 2531 MMIO_D(0xfdc, D_BDW_PLUS);
0aa5277c
ZY		 2532 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2533 NULL, NULL);
2534 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2535 NULL, NULL);
2536 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2537
0aa5277c
ZY		 2538 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2539 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2540 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2541 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2542 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2543 MMIO_D(0xb110, D_BDW);
2544
e6cedfea
ZY		 2545 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2546 NULL, force_nonpriv_write);
e39c5add 2547
593e59b4
ZY		 2548 MMIO_D(0x22040, D_BDW_PLUS);
2549 MMIO_D(0x44484, D_BDW_PLUS);
2550 MMIO_D(0x4448c, D_BDW_PLUS);
2551
0aa5277c 2552 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2553 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2554
0aa5277c 2555 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2556
2557 MMIO_D(0x110000, D_BDW_PLUS);
2558
2559 MMIO_D(0x48400, D_BDW_PLUS);
2560
2561 MMIO_D(0x6e570, D_BDW_PLUS);
2562 MMIO_D(0x65f10, D_BDW_PLUS);
2563
a045fba4
PG		 2564 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2565 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2566 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 2567 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2568
0aa5277c 2569 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2570
9112caaf
ZY		 2571 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2572 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2574 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2576 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2577 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2578 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2580 return 0;
2581}
2582
e39c5add
ZW		 2583static int init_skl_mmio_info(struct intel_gvt *gvt)
2584{
2585 struct drm_i915_private *dev_priv = gvt->dev_priv;
2586 int ret;
2587
2588 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2589 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2590 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2591 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2592 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2593 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2594
04d348ae
ZW		 2595 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2596 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2597 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
e39c5add
ZW		 2598
2599 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
04d348ae 2600 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write);
e39c5add 2601
e39c5add
ZW		 2602 MMIO_D(0xa210, D_SKL_PLUS);
2603 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2604 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
a045fba4 2605 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
04d348ae
ZW		 2606 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write);
2607 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write);
e39c5add
ZW		 2608 MMIO_D(0x45504, D_SKL);
2609 MMIO_D(0x45520, D_SKL);
2610 MMIO_D(0x46000, D_SKL);
04d348ae
ZW		 2611 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write);
2612 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write);
e39c5add
ZW		 2613 MMIO_D(0x6C040, D_SKL);
2614 MMIO_D(0x6C048, D_SKL);
2615 MMIO_D(0x6C050, D_SKL);
2616 MMIO_D(0x6C044, D_SKL);
2617 MMIO_D(0x6C04C, D_SKL);
2618 MMIO_D(0x6C054, D_SKL);
2619 MMIO_D(0x6c058, D_SKL);
2620 MMIO_D(0x6c05c, D_SKL);
04d348ae
ZW		 2621 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL);
2622
2623 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write);
2624 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write);
2625 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write);
2626 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write);
2627 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write);
2628 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write);
2629
2630 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write);
2631 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write);
2632 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write);
2633 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write);
2634 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write);
2635 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write);
2636
2637 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write);
2638 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write);
2639 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write);
2640 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write);
2641 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write);
2642 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write);
e39c5add
ZW		 2643
2644 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2645 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2646 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2647 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2648
2649 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2650 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2651 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2652 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2653
2654 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2657 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2658
2659 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL);
2660 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL);
2661 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL);
2662
2663 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2664 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2665 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2666
2667 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2668 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2669 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2670
2671 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2672 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2673 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2674
2675 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2676 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2677 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2678
2679 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL);
2680 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL);
2681 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL);
2682
2683 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL);
2684 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL);
2685 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL);
2686
2687 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL);
2688 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL);
2689 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL);
2690
2691 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL);
2692 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL);
2693 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL);
2694
2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2697 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2698 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2699
2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2702 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2703 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2704
2705 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2706 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2707 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2708 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2709
2710 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL);
2711 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL);
2712 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL);
2713 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL);
2714
2715 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL);
2716 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL);
2717 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL);
2718 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL);
2719
2720 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL);
2721 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL);
2722 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL);
2723 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL);
2724
2725 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL);
2726 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL);
2727 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL);
2728 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL);
2729
2730 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL);
2731 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL);
2732 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL);
2733 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL);
2734
2735 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL);
2736 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL);
2737 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL);
2738 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL);
2739
2740 MMIO_D(0x70380, D_SKL);
2741 MMIO_D(0x71380, D_SKL);
2742 MMIO_D(0x72380, D_SKL);
2743 MMIO_D(0x7039c, D_SKL);
2744
2745 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL);
2746 MMIO_D(0x8f074, D_SKL);
2747 MMIO_D(0x8f004, D_SKL);
2748 MMIO_D(0x8f034, D_SKL);
2749
2750 MMIO_D(0xb11c, D_SKL);
2751
2752 MMIO_D(0x51000, D_SKL);
2753 MMIO_D(0x6c00c, D_SKL);
2754
a045fba4
PG		 2755 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
2756 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
e39c5add
ZW		 2757
2758 MMIO_D(0xd08, D_SKL);
1f58af30 2759 MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL);
0aa5277c 2760 MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2761
2762 /* TRTT */
0aa5277c
ZY		 2763 MMIO_DFH(0x4de0, D_SKL, F_CMD_ACCESS, NULL, NULL);
2764 MMIO_DFH(0x4de4, D_SKL, F_CMD_ACCESS, NULL, NULL);
2765 MMIO_DFH(0x4de8, D_SKL, F_CMD_ACCESS, NULL, NULL);
2766 MMIO_DFH(0x4dec, D_SKL, F_CMD_ACCESS, NULL, NULL);
2767 MMIO_DFH(0x4df0, D_SKL, F_CMD_ACCESS, NULL, NULL);
2768 MMIO_DFH(0x4df4, D_SKL, F_CMD_ACCESS, NULL, gen9_trtte_write);
e39c5add
ZW		 2769 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write);
2770
2771 MMIO_D(0x45008, D_SKL);
2772
2773 MMIO_D(0x46430, D_SKL);
2774
2775 MMIO_D(0x46520, D_SKL);
2776
2777 MMIO_D(0xc403c, D_SKL);
2778 MMIO_D(0xb004, D_SKL);
2779 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2780
2781 MMIO_D(0x65900, D_SKL);
2782 MMIO_D(0x1082c0, D_SKL);
2783 MMIO_D(0x4068, D_SKL);
2784 MMIO_D(0x67054, D_SKL);
2785 MMIO_D(0x6e560, D_SKL);
2786 MMIO_D(0x6e554, D_SKL);
2787 MMIO_D(0x2b20, D_SKL);
2788 MMIO_D(0x65f00, D_SKL);
2789 MMIO_D(0x65f08, D_SKL);
2790 MMIO_D(0x320f0, D_SKL);
2791
0aa5277c 2792 MMIO_DFH(_REG_VCS2_EXCC, D_SKL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2793 MMIO_D(0x70034, D_SKL);
2794 MMIO_D(0x71034, D_SKL);
2795 MMIO_D(0x72034, D_SKL);
2796
2797 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL);
2798 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL);
2799 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL);
2800 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL);
2801 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL);
2802 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);
2803
2804 MMIO_D(0x44500, D_SKL);
0aa5277c 2805 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
9112caaf
ZY		 2806 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL, F_MODE_MASK | F_CMD_ACCESS,
2807 NULL, NULL);
e39c5add
ZW		 2808 return 0;
2809}
04d348ae 2810
12d14cc4
ZW		 2811/**
2812 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset
2813 * @gvt: GVT device
2814 * @offset: register offset
2815 *
2816 * This function is used to find the MMIO information entry from hash table
2817 *
2818 * Returns:
2819 * pointer to MMIO information entry, NULL if not exists
2820 */
2821struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
2822 unsigned int offset)
2823{
2824 struct intel_gvt_mmio_info *e;
2825
2826 WARN_ON(!IS_ALIGNED(offset, 4));
2827
2828 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
2829 if (e->offset == offset)
2830 return e;
2831 }
2832 return NULL;
2833}
2834
2835/**
2836 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2837 * @gvt: GVT device
2838 *
2839 * This function is called at the driver unloading stage, to clean up the MMIO
2840 * information table of GVT device
2841 *
2842 */
2843void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2844{
2845 struct hlist_node *tmp;
2846 struct intel_gvt_mmio_info *e;
2847 int i;
2848
2849 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2850 kfree(e);
2851
2852 vfree(gvt->mmio.mmio_attribute);
2853 gvt->mmio.mmio_attribute = NULL;
2854}
2855
2856/**
2857 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2858 * @gvt: GVT device
2859 *
2860 * This function is called at the initialization stage, to setup the MMIO
2861 * information table for GVT device
2862 *
2863 * Returns:
2864 * zero on success, negative if failed.
2865 */
2866int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2867{
2868 struct intel_gvt_device_info *info = &gvt->device_info;
2869 struct drm_i915_private *dev_priv = gvt->dev_priv;
2870 int ret;
2871
2872 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size);
2873 if (!gvt->mmio.mmio_attribute)
2874 return -ENOMEM;
2875
2876 ret = init_generic_mmio_info(gvt);
2877 if (ret)
2878 goto err;
2879
2880 if (IS_BROADWELL(dev_priv)) {
2881 ret = init_broadwell_mmio_info(gvt);
2882 if (ret)
2883 goto err;
e39c5add
ZW		 2884 } else if (IS_SKYLAKE(dev_priv)) {
2885 ret = init_broadwell_mmio_info(gvt);
2886 if (ret)
2887 goto err;
2888 ret = init_skl_mmio_info(gvt);
2889 if (ret)
2890 goto err;
12d14cc4
ZW		 2891 }
2892 return 0;
2893err:
2894 intel_gvt_clean_mmio_info(gvt);
2895 return ret;
2896}
e39c5add
ZW		 2897
2898/**
2899 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
2900 * @gvt: a GVT device
2901 * @offset: register offset
2902 *
2903 */
2904void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset)
2905{
2906 gvt->mmio.mmio_attribute[offset >> 2] |=
2907 F_ACCESSED;
2908}
2909
2910/**
2911 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
2912 * @gvt: a GVT device
2913 * @offset: register offset
2914 *
2915 */
2916bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt,
2917 unsigned int offset)
2918{
2919 return gvt->mmio.mmio_attribute[offset >> 2] &
2920 F_CMD_ACCESS;
2921}
2922
2923/**
2924 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
2925 * @gvt: a GVT device
2926 * @offset: register offset
2927 *
2928 */
2929bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt,
2930 unsigned int offset)
2931{
2932 return gvt->mmio.mmio_attribute[offset >> 2] &
2933 F_UNALIGN;
2934}
2935
2936/**
2937 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
2938 * @gvt: a GVT device
2939 * @offset: register offset
2940 *
2941 */
2942void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt,
2943 unsigned int offset)
2944{
2945 gvt->mmio.mmio_attribute[offset >> 2] |=
2946 F_CMD_ACCESSED;
2947}
2948
2949/**
2950 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
2951 * @gvt: a GVT device
2952 * @offset: register offset
2953 *
2954 * Returns:
2955 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
2956 *
2957 */
2958bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset)
2959{
2960 return gvt->mmio.mmio_attribute[offset >> 2] &
2961 F_MODE_MASK;
2962}
2963
2964/**
2965 * intel_vgpu_default_mmio_read - default MMIO read handler
2966 * @vgpu: a vGPU
2967 * @offset: access offset
2968 * @p_data: data return buffer
2969 * @bytes: access data length
2970 *
2971 * Returns:
2972 * Zero on success, negative error code if failed.
2973 */
2974int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2975 void *p_data, unsigned int bytes)
2976{
2977 read_vreg(vgpu, offset, p_data, bytes);
2978 return 0;
2979}
2980
2981/**
2982 * intel_t_default_mmio_write - default MMIO write handler
2983 * @vgpu: a vGPU
2984 * @offset: access offset
2985 * @p_data: write data buffer
2986 * @bytes: access data length
2987 *
2988 * Returns:
2989 * Zero on success, negative error code if failed.
2990 */
2991int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2992 void *p_data, unsigned int bytes)
2993{
2994 write_vreg(vgpu, offset, p_data, bytes);
2995 return 0;
2996}
4938ca90
ZY		 2997
2998/**
2999 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3000 * force-nopriv register
3001 *
3002 * @gvt: a GVT device
3003 * @offset: register offset
3004 *
3005 * Returns:
3006 * True if the register is in force-nonpriv whitelist;
3007 * False if outside;
3008 */
3009bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3010 unsigned int offset)
3011{
3012 return in_whitelist(offset);
3013}
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