[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / gvt / mmio_context.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Eddie Dong <eddie.dong@intel.com>
 *    Kevin Tian <kevin.tian@intel.com>
 *
 * Contributors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Changbin Du <changbin.du@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Tina Zhang <tina.zhang@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"
#include "trace.h"

/**
 * Defined in Intel Open Source PRM.
 * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
 */
#define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i)*4)
#define TRNULLDETCT		_MMIO(0x4de8)
#define TRINVTILEDETCT		_MMIO(0x4dec)
#define TRVADR			_MMIO(0x4df0)
#define TRTTE			_MMIO(0x4df4)
#define RING_EXCC(base)		_MMIO((base) + 0x28)
#define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
#define VF_GUARDBAND		_MMIO(0x83a4)

/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
};

static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
	{RCS, TRVADR, 0, false}, /* 0x4df0 */
	{RCS, TRTTE, 0, false}, /* 0x4df4 */

	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */

	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */

	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */

	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */

	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
};

static struct {
	bool initialized;
	u32 control_table[I915_NUM_ENGINES][64];
	u32 l3cc_table[32];
} gen9_render_mocs;

static void load_render_mocs(struct drm_i915_private *dev_priv)
{
	i915_reg_t offset;
	u32 regs[] = {
		[RCS] = 0xc800,
		[VCS] = 0xc900,
		[VCS2] = 0xca00,
		[BCS] = 0xcc00,
		[VECS] = 0xcb00,
	};
	int ring_id, i;

	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
		offset.reg = regs[ring_id];
		for (i = 0; i < 64; i++) {
			gen9_render_mocs.control_table[ring_id][i] =
				I915_READ_FW(offset);
			offset.reg += 4;
		}
	}

	offset.reg = 0xb020;
	for (i = 0; i < 32; i++) {
		gen9_render_mocs.l3cc_table[i] =
			I915_READ_FW(offset);
		offset.reg += 4;
	}
	gen9_render_mocs.initialized = true;
}

static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	struct intel_vgpu_submission *s = &vgpu->submission;
	enum forcewake_domains fw;
	i915_reg_t reg;
	u32 regs[] = {
		[RCS] = 0x4260,
		[VCS] = 0x4264,
		[VCS2] = 0x4268,
		[BCS] = 0x426c,
		[VECS] = 0x4270,
	};

	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
		return;

	if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
		return;

	reg = _MMIO(regs[ring_id]);

	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
	 * we need to put a forcewake when invalidating RCS TLB caches,
	 * otherwise device can go to RC6 state and interrupt invalidation
	 * process
	 */
	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
					    FW_REG_READ | FW_REG_WRITE);
	if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
		fw |= FORCEWAKE_RENDER;

	intel_uncore_forcewake_get(dev_priv, fw);

	I915_WRITE_FW(reg, 0x1);

	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
		gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
	else
		vgpu_vreg_t(vgpu, reg) = 0;

	intel_uncore_forcewake_put(dev_priv, fw);

	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}

static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
			int ring_id)
{
	struct drm_i915_private *dev_priv;
	i915_reg_t offset, l3_offset;
	u32 old_v, new_v;

	u32 regs[] = {
		[RCS] = 0xc800,
		[VCS] = 0xc900,
		[VCS2] = 0xca00,
		[BCS] = 0xcc00,
		[VECS] = 0xcb00,
	};
	int i;

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
		return;

	if (!pre && !gen9_render_mocs.initialized)
		load_render_mocs(dev_priv);

	offset.reg = regs[ring_id];
	for (i = 0; i < 64; i++) {
		if (pre)
			old_v = vgpu_vreg_t(pre, offset);
		else
			old_v = gen9_render_mocs.control_table[ring_id][i];
		if (next)
			new_v = vgpu_vreg_t(next, offset);
		else
			new_v = gen9_render_mocs.control_table[ring_id][i];

		if (old_v != new_v)
			I915_WRITE_FW(offset, new_v);

		offset.reg += 4;
	}

	if (ring_id == RCS) {
		l3_offset.reg = 0xb020;
		for (i = 0; i < 32; i++) {
			if (pre)
				old_v = vgpu_vreg_t(pre, l3_offset);
			else
				old_v = gen9_render_mocs.l3cc_table[i];
			if (next)
				new_v = vgpu_vreg_t(next, l3_offset);
			else
				new_v = gen9_render_mocs.l3cc_table[i];

			if (old_v != new_v)
				I915_WRITE_FW(l3_offset, new_v);

			l3_offset.reg += 4;
		}
	}
}

#define CTX_CONTEXT_CONTROL_VAL	0x03

/* Switch ring mmio values (context). */
static void switch_mmio(struct intel_vgpu *pre,
			struct intel_vgpu *next,
			int ring_id)
{
	struct drm_i915_private *dev_priv;
	struct intel_vgpu_submission *s;
	u32 *reg_state, ctx_ctrl;
	u32 inhibit_mask =
		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
	struct engine_mmio *mmio;
	u32 old_v, new_v;

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
		switch_mocs(pre, next, ring_id);

	for (mmio = dev_priv->gvt->engine_mmio_list;
	     i915_mmio_reg_valid(mmio->reg); mmio++) {
		if (mmio->ring_id != ring_id)
			continue;
		// save
		if (pre) {
			vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
			if (mmio->mask)
				vgpu_vreg_t(pre, mmio->reg) &=
						~(mmio->mask << 16);
			old_v = vgpu_vreg_t(pre, mmio->reg);
		} else
			old_v = mmio->value = I915_READ_FW(mmio->reg);

		// restore
		if (next) {
			s = &next->submission;
			reg_state =
				s->shadow_ctx->engine[ring_id].lrc_reg_state;
			ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
			/*
			 * if it is an inhibit context, load in_context mmio
			 * into HW by mmio write. If it is not, skip this mmio
			 * write.
			 */
			if (mmio->in_context &&
			    (ctx_ctrl & inhibit_mask) != inhibit_mask)
				continue;

			if (mmio->mask)
				new_v = vgpu_vreg_t(next, mmio->reg) |
							(mmio->mask << 16);
			else
				new_v = vgpu_vreg_t(next, mmio->reg);
		} else {
			if (mmio->in_context)
				continue;
			if (mmio->mask)
				new_v = mmio->value | (mmio->mask << 16);
			else
				new_v = mmio->value;
		}

		I915_WRITE_FW(mmio->reg, new_v);

		trace_render_mmio(pre ? pre->id : 0,
				  next ? next->id : 0,
				  "switch",
				  i915_mmio_reg_offset(mmio->reg),
				  old_v, new_v);
	}

	if (next)
		handle_tlb_pending_event(next, ring_id);
}

/**
 * intel_gvt_switch_render_mmio - switch mmio context of specific engine
 * @pre: the last vGPU that own the engine
 * @next: the vGPU to switch to
 * @ring_id: specify the engine
 *
 * If pre is null indicates that host own the engine. If next is null
 * indicates that we are switching to host workload.
 */
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
			   struct intel_vgpu *next, int ring_id)
{
	struct drm_i915_private *dev_priv;

	if (WARN_ON(!pre && !next))
		return;

	gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
		       pre ? "vGPU" : "host", next ? "vGPU" : "HOST");

	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;

	/**
	 * We are using raw mmio access wrapper to improve the
	 * performace for batch mmio read/write, so we need
	 * handle forcewake mannually.
	 */
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
	switch_mmio(pre, next, ring_id);
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

/**
 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
 * @gvt: GVT device
 *
 */
void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
{
	if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv))
		gvt->engine_mmio_list = gen9_engine_mmio_list;
	else
		gvt->engine_mmio_list = gen8_engine_mmio_list;
}
Commit	Line	Data
17865713 ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Eddie Dong <eddie.dong@intel.com>
	25	* Kevin Tian <kevin.tian@intel.com>
	26	*
	27	* Contributors:
	28	* Zhi Wang <zhi.a.wang@intel.com>
	29	* Changbin Du <changbin.du@intel.com>
	30	* Zhenyu Wang <zhenyuw@linux.intel.com>
	31	* Tina Zhang <tina.zhang@intel.com>
	32	* Bing Niu <bing.niu@intel.com>
	33	*
	34	*/
	35
	36	#include "i915_drv.h"
feddf6e8	37	#include "gvt.h"
7fb6a7d6	38	#include "trace.h"
17865713	39
4447f423 CD	40	/**
	41	* Defined in Intel Open Source PRM.
	42	* Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
	43	*/
	44	#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4)
	45	#define TRNULLDETCT _MMIO(0x4de8)
	46	#define TRINVTILEDETCT _MMIO(0x4dec)
	47	#define TRVADR _MMIO(0x4df0)
	48	#define TRTTE _MMIO(0x4df4)
	49	#define RING_EXCC(base) _MMIO((base) + 0x28)
	50	#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
	51	#define VF_GUARDBAND _MMIO(0x83a4)
	52
	53	/* Raw offset is appened to each line for convenience. */
83164886	54	static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
4447f423 CD	55	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	56	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	57	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	58	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	59	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	60	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	61	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	62	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	63	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	64	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	65	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	66	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	67	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	68	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	69	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	70	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	71	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	72	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	73	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	74	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	75	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	76	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
	77
	78	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	79	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	80	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	81	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	82	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
d9df2c09	83	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
17865713 ZW	84	};
17865713 ZW	85
83164886	86	static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
4447f423 CD	87	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
	88	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	89	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
	90	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
	91	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
	92	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
	93	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
	94	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
	95	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
	96	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
	97	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
	98	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
	99	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
	100	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
	101	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
	102	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
	103	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
	104	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
	105	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
	106	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
	107	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
	108	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
	109
	110	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
	111	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
	112	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
	113	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
	114	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
	115	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
	116	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
	117	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
	118	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
	119	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
	120	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
	121	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
	122	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
	123	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
	124	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
	125	{RCS, TRVADR, 0, false}, /* 0x4df0 */
	126	{RCS, TRTTE, 0, false}, /* 0x4df4 */
	127
	128	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
	129	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
	130	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
	131	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
	132	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
	133
	134	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
	135
	136	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
	137
	138	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
	139	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
	140	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
	141	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
	142
	143	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
	144	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
	145
	146	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
	147	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
	148	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
d9df2c09	149	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
17865713 ZW	150	};
17865713 ZW	151
b05b3397 WL	152	static struct {
	153	bool initialized;
	154	u32 control_table[I915_NUM_ENGINES][64];
	155	u32 l3cc_table[32];
	156	} gen9_render_mocs;
	157
	158	static void load_render_mocs(struct drm_i915_private *dev_priv)
	159	{
	160	i915_reg_t offset;
	161	u32 regs[] = {
	162	[RCS] = 0xc800,
	163	[VCS] = 0xc900,
	164	[VCS2] = 0xca00,
	165	[BCS] = 0xcc00,
	166	[VECS] = 0xcb00,
	167	};
	168	int ring_id, i;
	169
8466169a	170	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
b05b3397 WL	171	offset.reg = regs[ring_id];
	172	for (i = 0; i < 64; i++) {
	173	gen9_render_mocs.control_table[ring_id][i] =
	174	I915_READ_FW(offset);
	175	offset.reg += 4;
	176	}
	177	}
	178
	179	offset.reg = 0xb020;
	180	for (i = 0; i < 32; i++) {
	181	gen9_render_mocs.l3cc_table[i] =
	182	I915_READ_FW(offset);
	183	offset.reg += 4;
	184	}
	185	gen9_render_mocs.initialized = true;
	186	}
17865713 ZW	187
	188	static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
	189	{
	190	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
91d5d854	191	struct intel_vgpu_submission *s = &vgpu->submission;
1c860a30	192	enum forcewake_domains fw;
17865713 ZW	193	i915_reg_t reg;
	194	u32 regs[] = {
	195	[RCS] = 0x4260,
	196	[VCS] = 0x4264,
	197	[VCS2] = 0x4268,
	198	[BCS] = 0x426c,
	199	[VECS] = 0x4270,
	200	};
	201
	202	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
	203	return;
	204
91d5d854	205	if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
17865713 ZW	206	return;
	207
	208	reg = _MMIO(regs[ring_id]);
	209
1c860a30 AH	210	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
	211	* we need to put a forcewake when invalidating RCS TLB caches,
	212	* otherwise device can go to RC6 state and interrupt invalidation
	213	* process
	214	*/
	215	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
	216	FW_REG_READ \| FW_REG_WRITE);
e3476c00	217	if (ring_id == RCS && (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)))
1c860a30	218	fw \|= FORCEWAKE_RENDER;
17865713	219
1c860a30 AH	220	intel_uncore_forcewake_get(dev_priv, fw);
	221
	222	I915_WRITE_FW(reg, 0x1);
	223
	224	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
695fbc08	225	gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
f24940e0	226	else
90551a12	227	vgpu_vreg_t(vgpu, reg) = 0;
17865713	228
1c860a30 AH	229	intel_uncore_forcewake_put(dev_priv, fw);
1c860a30 AH	230
17865713 ZW	231	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
	232	}
	233
e47107ad WL	234	static void switch_mocs(struct intel_vgpu pre, struct intel_vgpu next,
e47107ad WL	235	int ring_id)
17865713	236	{
e47107ad	237	struct drm_i915_private *dev_priv;
17865713	238	i915_reg_t offset, l3_offset;
f402f2d6 WL	239	u32 old_v, new_v;
f402f2d6 WL	240
17865713 ZW	241	u32 regs[] = {
	242	[RCS] = 0xc800,
	243	[VCS] = 0xc900,
	244	[VCS2] = 0xca00,
	245	[BCS] = 0xcc00,
	246	[VECS] = 0xcb00,
	247	};
	248	int i;
	249
e47107ad	250	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
17865713 ZW	251	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
	252	return;
	253
b05b3397 WL	254	if (!pre && !gen9_render_mocs.initialized)
b05b3397 WL	255	load_render_mocs(dev_priv);
17865713	256
b05b3397	257	offset.reg = regs[ring_id];
e47107ad WL	258	for (i = 0; i < 64; i++) {
e47107ad WL	259	if (pre)
90551a12	260	old_v = vgpu_vreg_t(pre, offset);
e47107ad	261	else
b05b3397	262	old_v = gen9_render_mocs.control_table[ring_id][i];
e47107ad	263	if (next)
90551a12	264	new_v = vgpu_vreg_t(next, offset);
e47107ad	265	else
b05b3397	266	new_v = gen9_render_mocs.control_table[ring_id][i];
f402f2d6 WL	267
	268	if (old_v != new_v)
	269	I915_WRITE_FW(offset, new_v);
17865713	270
17865713 ZW	271	offset.reg += 4;
	272	}
	273
	274	if (ring_id == RCS) {
	275	l3_offset.reg = 0xb020;
	276	for (i = 0; i < 32; i++) {
e47107ad	277	if (pre)
90551a12	278	old_v = vgpu_vreg_t(pre, l3_offset);
e47107ad	279	else
b05b3397	280	old_v = gen9_render_mocs.l3cc_table[i];
e47107ad	281	if (next)
90551a12	282	new_v = vgpu_vreg_t(next, l3_offset);
e47107ad	283	else
b05b3397	284	new_v = gen9_render_mocs.l3cc_table[i];
f402f2d6 WL	285
	286	if (old_v != new_v)
	287	I915_WRITE_FW(l3_offset, new_v);
e47107ad	288
17865713 ZW	289	l3_offset.reg += 4;
	290	}
	291	}
	292	}
	293
bc6a1c85 CD	294	#define CTX_CONTEXT_CONTROL_VAL 0x03
bc6a1c85 CD	295
e47107ad WL	296	/* Switch ring mmio values (context). */
	297	static void switch_mmio(struct intel_vgpu *pre,
	298	struct intel_vgpu *next,
	299	int ring_id)
17865713	300	{
e47107ad WL	301	struct drm_i915_private *dev_priv;
	302	struct intel_vgpu_submission *s;
	303	u32 *reg_state, ctx_ctrl;
bc6a1c85 CD	304	u32 inhibit_mask =
bc6a1c85 CD	305	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
83164886	306	struct engine_mmio *mmio;
e47107ad	307	u32 old_v, new_v;
17865713	308
e47107ad	309	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
83164886	310	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
e47107ad	311	switch_mocs(pre, next, ring_id);
17865713	312
d9df2c09 XZ	313	for (mmio = dev_priv->gvt->engine_mmio_list;
d9df2c09 XZ	314	i915_mmio_reg_valid(mmio->reg); mmio++) {
17865713 ZW	315	if (mmio->ring_id != ring_id)
17865713 ZW	316	continue;
e47107ad WL	317	// save
e47107ad WL	318	if (pre) {
90551a12	319	vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
e47107ad	320	if (mmio->mask)
90551a12	321	vgpu_vreg_t(pre, mmio->reg) &=
e47107ad	322	~(mmio->mask << 16);
90551a12	323	old_v = vgpu_vreg_t(pre, mmio->reg);
17865713	324	} else
e47107ad WL	325	old_v = mmio->value = I915_READ_FW(mmio->reg);
	326
	327	// restore
	328	if (next) {
	329	s = &next->submission;
	330	reg_state =
	331	s->shadow_ctx->engine[ring_id].lrc_reg_state;
	332	ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
	333	/*
	334	* if it is an inhibit context, load in_context mmio
	335	* into HW by mmio write. If it is not, skip this mmio
	336	* write.
	337	*/
	338	if (mmio->in_context &&
	339	(ctx_ctrl & inhibit_mask) != inhibit_mask)
	340	continue;
	341
	342	if (mmio->mask)
90551a12	343	new_v = vgpu_vreg_t(next, mmio->reg) \|
e47107ad WL	344	(mmio->mask << 16);
e47107ad WL	345	else
90551a12	346	new_v = vgpu_vreg_t(next, mmio->reg);
e47107ad WL	347	} else {
	348	if (mmio->in_context)
	349	continue;
	350	if (mmio->mask)
	351	new_v = mmio->value \| (mmio->mask << 16);
	352	else
	353	new_v = mmio->value;
	354	}
2345ab1d	355
e47107ad	356	I915_WRITE_FW(mmio->reg, new_v);
17865713	357
e47107ad WL	358	trace_render_mmio(pre ? pre->id : 0,
	359	next ? next->id : 0,
	360	"switch",
7fb6a7d6	361	i915_mmio_reg_offset(mmio->reg),
e47107ad	362	old_v, new_v);
17865713	363	}
e47107ad WL	364
	365	if (next)
	366	handle_tlb_pending_event(next, ring_id);
17865713	367	}
0e86cc9c CD	368
	369	/**
	370	* intel_gvt_switch_render_mmio - switch mmio context of specific engine
	371	* @pre: the last vGPU that own the engine
	372	* @next: the vGPU to switch to
	373	* @ring_id: specify the engine
	374	*
	375	* If pre is null indicates that host own the engine. If next is null
	376	* indicates that we are switching to host workload.
	377	*/
	378	void intel_gvt_switch_mmio(struct intel_vgpu *pre,
	379	struct intel_vgpu *next, int ring_id)
	380	{
4671ea20 CD	381	struct drm_i915_private *dev_priv;
4671ea20 CD	382
0e86cc9c CD	383	if (WARN_ON(!pre && !next))
	384	return;
	385
	386	gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
	387	pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
	388
4671ea20 CD	389	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
	390
	391	/**
	392	* We are using raw mmio access wrapper to improve the
	393	* performace for batch mmio read/write, so we need
	394	* handle forcewake mannually.
	395	*/
	396	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
e47107ad	397	switch_mmio(pre, next, ring_id);
4671ea20	398	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0e86cc9c	399	}
83164886 CD	400
	401	/**
	402	* intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
	403	* @gvt: GVT device
	404	*
	405	*/
	406	void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
	407	{
	408	if (IS_SKYLAKE(gvt->dev_priv) \|\| IS_KABYLAKE(gvt->dev_priv))
	409	gvt->engine_mmio_list = gen9_engine_mmio_list;
	410	else
	411	gvt->engine_mmio_list = gen8_engine_mmio_list;
	412	}