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351e3db2 BV |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Brad Volkin <bradley.d.volkin@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | ||
30 | /** | |
31 | * DOC: i915 batch buffer command parser | |
32 | * | |
33 | * Motivation: | |
34 | * Certain OpenGL features (e.g. transform feedback, performance monitoring) | |
35 | * require userspace code to submit batches containing commands such as | |
36 | * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some | |
37 | * generations of the hardware will noop these commands in "unsecure" batches | |
38 | * (which includes all userspace batches submitted via i915) even though the | |
39 | * commands may be safe and represent the intended programming model of the | |
40 | * device. | |
41 | * | |
42 | * The software command parser is similar in operation to the command parsing | |
43 | * done in hardware for unsecure batches. However, the software parser allows | |
44 | * some operations that would be noop'd by hardware, if the parser determines | |
45 | * the operation is safe, and submits the batch as "secure" to prevent hardware | |
46 | * parsing. | |
47 | * | |
48 | * Threats: | |
49 | * At a high level, the hardware (and software) checks attempt to prevent | |
50 | * granting userspace undue privileges. There are three categories of privilege. | |
51 | * | |
52 | * First, commands which are explicitly defined as privileged or which should | |
53 | * only be used by the kernel driver. The parser generally rejects such | |
54 | * commands, though it may allow some from the drm master process. | |
55 | * | |
56 | * Second, commands which access registers. To support correct/enhanced | |
57 | * userspace functionality, particularly certain OpenGL extensions, the parser | |
58 | * provides a whitelist of registers which userspace may safely access (for both | |
59 | * normal and drm master processes). | |
60 | * | |
61 | * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). | |
62 | * The parser always rejects such commands. | |
63 | * | |
64 | * The majority of the problematic commands fall in the MI_* range, with only a | |
65 | * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). | |
66 | * | |
67 | * Implementation: | |
68 | * Each ring maintains tables of commands and registers which the parser uses in | |
69 | * scanning batch buffers submitted to that ring. | |
70 | * | |
71 | * Since the set of commands that the parser must check for is significantly | |
72 | * smaller than the number of commands supported, the parser tables contain only | |
73 | * those commands required by the parser. This generally works because command | |
74 | * opcode ranges have standard command length encodings. So for commands that | |
75 | * the parser does not need to check, it can easily skip them. This is | |
76 | * implementated via a per-ring length decoding vfunc. | |
77 | * | |
78 | * Unfortunately, there are a number of commands that do not follow the standard | |
79 | * length encoding for their opcode range, primarily amongst the MI_* commands. | |
80 | * To handle this, the parser provides a way to define explicit "skip" entries | |
81 | * in the per-ring command tables. | |
82 | * | |
83 | * Other command table entries map fairly directly to high level categories | |
84 | * mentioned above: rejected, master-only, register whitelist. The parser | |
85 | * implements a number of checks, including the privileged memory checks, via a | |
86 | * general bitmasking mechanism. | |
87 | */ | |
88 | ||
3a6fa984 BV |
89 | #define STD_MI_OPCODE_MASK 0xFF800000 |
90 | #define STD_3D_OPCODE_MASK 0xFFFF0000 | |
91 | #define STD_2D_OPCODE_MASK 0xFFC00000 | |
92 | #define STD_MFX_OPCODE_MASK 0xFFFF0000 | |
93 | ||
94 | #define CMD(op, opm, f, lm, fl, ...) \ | |
95 | { \ | |
96 | .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ | |
97 | .cmd = { (op), (opm) }, \ | |
98 | .length = { (lm) }, \ | |
99 | __VA_ARGS__ \ | |
100 | } | |
101 | ||
102 | /* Convenience macros to compress the tables */ | |
103 | #define SMI STD_MI_OPCODE_MASK | |
104 | #define S3D STD_3D_OPCODE_MASK | |
105 | #define S2D STD_2D_OPCODE_MASK | |
106 | #define SMFX STD_MFX_OPCODE_MASK | |
107 | #define F true | |
108 | #define S CMD_DESC_SKIP | |
109 | #define R CMD_DESC_REJECT | |
110 | #define W CMD_DESC_REGISTER | |
111 | #define B CMD_DESC_BITMASK | |
112 | #define M CMD_DESC_MASTER | |
113 | ||
114 | /* Command Mask Fixed Len Action | |
115 | ---------------------------------------------------------- */ | |
116 | static const struct drm_i915_cmd_descriptor common_cmds[] = { | |
117 | CMD( MI_NOOP, SMI, F, 1, S ), | |
118 | CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), | |
119 | CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), | |
120 | CMD( MI_ARB_CHECK, SMI, F, 1, S ), | |
121 | CMD( MI_REPORT_HEAD, SMI, F, 1, S ), | |
122 | CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), | |
123 | CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ), | |
124 | CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ), | |
125 | CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ), | |
126 | CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ), | |
127 | CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ), | |
128 | CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), | |
129 | }; | |
130 | ||
131 | static const struct drm_i915_cmd_descriptor render_cmds[] = { | |
132 | CMD( MI_FLUSH, SMI, F, 1, S ), | |
133 | CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), | |
134 | CMD( MI_PREDICATE, SMI, F, 1, S ), | |
135 | CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), | |
136 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), | |
137 | CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ), | |
138 | CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), | |
139 | CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ), | |
140 | CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ), | |
141 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), | |
142 | CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), | |
143 | CMD( PIPELINE_SELECT, S3D, F, 1, S ), | |
144 | CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), | |
145 | CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), | |
146 | CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), | |
147 | }; | |
148 | ||
149 | static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { | |
150 | CMD( MI_SET_PREDICATE, SMI, F, 1, S ), | |
151 | CMD( MI_RS_CONTROL, SMI, F, 1, S ), | |
152 | CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), | |
153 | CMD( MI_RS_CONTEXT, SMI, F, 1, S ), | |
154 | CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ), | |
155 | CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), | |
156 | CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), | |
157 | CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), | |
158 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), | |
159 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), | |
160 | ||
161 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), | |
162 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), | |
163 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), | |
164 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), | |
165 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), | |
166 | }; | |
167 | ||
168 | static const struct drm_i915_cmd_descriptor video_cmds[] = { | |
169 | CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), | |
170 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), | |
171 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), | |
172 | /* | |
173 | * MFX_WAIT doesn't fit the way we handle length for most commands. | |
174 | * It has a length field but it uses a non-standard length bias. | |
175 | * It is always 1 dword though, so just treat it as fixed length. | |
176 | */ | |
177 | CMD( MFX_WAIT, SMFX, F, 1, S ), | |
178 | }; | |
179 | ||
180 | static const struct drm_i915_cmd_descriptor vecs_cmds[] = { | |
181 | CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), | |
182 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), | |
183 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), | |
184 | }; | |
185 | ||
186 | static const struct drm_i915_cmd_descriptor blt_cmds[] = { | |
187 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), | |
188 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), | |
189 | CMD( COLOR_BLT, S2D, !F, 0x3F, S ), | |
190 | CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), | |
191 | }; | |
192 | ||
193 | #undef CMD | |
194 | #undef SMI | |
195 | #undef S3D | |
196 | #undef S2D | |
197 | #undef SMFX | |
198 | #undef F | |
199 | #undef S | |
200 | #undef R | |
201 | #undef W | |
202 | #undef B | |
203 | #undef M | |
204 | ||
205 | static const struct drm_i915_cmd_table gen7_render_cmds[] = { | |
206 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
207 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
208 | }; | |
209 | ||
210 | static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { | |
211 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
212 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
213 | { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, | |
214 | }; | |
215 | ||
216 | static const struct drm_i915_cmd_table gen7_video_cmds[] = { | |
217 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
218 | { video_cmds, ARRAY_SIZE(video_cmds) }, | |
219 | }; | |
220 | ||
221 | static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { | |
222 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
223 | { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, | |
224 | }; | |
225 | ||
226 | static const struct drm_i915_cmd_table gen7_blt_cmds[] = { | |
227 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
228 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, | |
229 | }; | |
230 | ||
351e3db2 BV |
231 | static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) |
232 | { | |
233 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
234 | u32 subclient = | |
235 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
236 | ||
237 | if (client == INSTR_MI_CLIENT) | |
238 | return 0x3F; | |
239 | else if (client == INSTR_RC_CLIENT) { | |
240 | if (subclient == INSTR_MEDIA_SUBCLIENT) | |
241 | return 0xFFFF; | |
242 | else | |
243 | return 0xFF; | |
244 | } | |
245 | ||
246 | DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) | |
251 | { | |
252 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
253 | u32 subclient = | |
254 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
255 | ||
256 | if (client == INSTR_MI_CLIENT) | |
257 | return 0x3F; | |
258 | else if (client == INSTR_RC_CLIENT) { | |
259 | if (subclient == INSTR_MEDIA_SUBCLIENT) | |
260 | return 0xFFF; | |
261 | else | |
262 | return 0xFF; | |
263 | } | |
264 | ||
265 | DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); | |
266 | return 0; | |
267 | } | |
268 | ||
269 | static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) | |
270 | { | |
271 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
272 | ||
273 | if (client == INSTR_MI_CLIENT) | |
274 | return 0x3F; | |
275 | else if (client == INSTR_BC_CLIENT) | |
276 | return 0xFF; | |
277 | ||
278 | DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); | |
279 | return 0; | |
280 | } | |
281 | ||
282 | static void validate_cmds_sorted(struct intel_ring_buffer *ring) | |
283 | { | |
284 | int i; | |
285 | ||
286 | if (!ring->cmd_tables || ring->cmd_table_count == 0) | |
287 | return; | |
288 | ||
289 | for (i = 0; i < ring->cmd_table_count; i++) { | |
290 | const struct drm_i915_cmd_table *table = &ring->cmd_tables[i]; | |
291 | u32 previous = 0; | |
292 | int j; | |
293 | ||
294 | for (j = 0; j < table->count; j++) { | |
295 | const struct drm_i915_cmd_descriptor *desc = | |
296 | &table->table[i]; | |
297 | u32 curr = desc->cmd.value & desc->cmd.mask; | |
298 | ||
299 | if (curr < previous) | |
300 | DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", | |
301 | ring->id, i, j, curr, previous); | |
302 | ||
303 | previous = curr; | |
304 | } | |
305 | } | |
306 | } | |
307 | ||
308 | static void check_sorted(int ring_id, const u32 *reg_table, int reg_count) | |
309 | { | |
310 | int i; | |
311 | u32 previous = 0; | |
312 | ||
313 | for (i = 0; i < reg_count; i++) { | |
314 | u32 curr = reg_table[i]; | |
315 | ||
316 | if (curr < previous) | |
317 | DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", | |
318 | ring_id, i, curr, previous); | |
319 | ||
320 | previous = curr; | |
321 | } | |
322 | } | |
323 | ||
324 | static void validate_regs_sorted(struct intel_ring_buffer *ring) | |
325 | { | |
326 | check_sorted(ring->id, ring->reg_table, ring->reg_count); | |
327 | check_sorted(ring->id, ring->master_reg_table, ring->master_reg_count); | |
328 | } | |
329 | ||
330 | /** | |
331 | * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer | |
332 | * @ring: the ringbuffer to initialize | |
333 | * | |
334 | * Optionally initializes fields related to batch buffer command parsing in the | |
335 | * struct intel_ring_buffer based on whether the platform requires software | |
336 | * command parsing. | |
337 | */ | |
338 | void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring) | |
339 | { | |
340 | if (!IS_GEN7(ring->dev)) | |
341 | return; | |
342 | ||
343 | switch (ring->id) { | |
344 | case RCS: | |
3a6fa984 BV |
345 | if (IS_HASWELL(ring->dev)) { |
346 | ring->cmd_tables = hsw_render_ring_cmds; | |
347 | ring->cmd_table_count = | |
348 | ARRAY_SIZE(hsw_render_ring_cmds); | |
349 | } else { | |
350 | ring->cmd_tables = gen7_render_cmds; | |
351 | ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds); | |
352 | } | |
353 | ||
351e3db2 BV |
354 | ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; |
355 | break; | |
356 | case VCS: | |
3a6fa984 BV |
357 | ring->cmd_tables = gen7_video_cmds; |
358 | ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds); | |
351e3db2 BV |
359 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
360 | break; | |
361 | case BCS: | |
3a6fa984 BV |
362 | ring->cmd_tables = gen7_blt_cmds; |
363 | ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); | |
351e3db2 BV |
364 | ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; |
365 | break; | |
366 | case VECS: | |
3a6fa984 BV |
367 | ring->cmd_tables = hsw_vebox_cmds; |
368 | ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); | |
351e3db2 BV |
369 | /* VECS can use the same length_mask function as VCS */ |
370 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; | |
371 | break; | |
372 | default: | |
373 | DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", | |
374 | ring->id); | |
375 | BUG(); | |
376 | } | |
377 | ||
378 | validate_cmds_sorted(ring); | |
379 | validate_regs_sorted(ring); | |
380 | } | |
381 | ||
382 | static const struct drm_i915_cmd_descriptor* | |
383 | find_cmd_in_table(const struct drm_i915_cmd_table *table, | |
384 | u32 cmd_header) | |
385 | { | |
386 | int i; | |
387 | ||
388 | for (i = 0; i < table->count; i++) { | |
389 | const struct drm_i915_cmd_descriptor *desc = &table->table[i]; | |
390 | u32 masked_cmd = desc->cmd.mask & cmd_header; | |
391 | u32 masked_value = desc->cmd.value & desc->cmd.mask; | |
392 | ||
393 | if (masked_cmd == masked_value) | |
394 | return desc; | |
395 | } | |
396 | ||
397 | return NULL; | |
398 | } | |
399 | ||
400 | /* | |
401 | * Returns a pointer to a descriptor for the command specified by cmd_header. | |
402 | * | |
403 | * The caller must supply space for a default descriptor via the default_desc | |
404 | * parameter. If no descriptor for the specified command exists in the ring's | |
405 | * command parser tables, this function fills in default_desc based on the | |
406 | * ring's default length encoding and returns default_desc. | |
407 | */ | |
408 | static const struct drm_i915_cmd_descriptor* | |
409 | find_cmd(struct intel_ring_buffer *ring, | |
410 | u32 cmd_header, | |
411 | struct drm_i915_cmd_descriptor *default_desc) | |
412 | { | |
413 | u32 mask; | |
414 | int i; | |
415 | ||
416 | for (i = 0; i < ring->cmd_table_count; i++) { | |
417 | const struct drm_i915_cmd_descriptor *desc; | |
418 | ||
419 | desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header); | |
420 | if (desc) | |
421 | return desc; | |
422 | } | |
423 | ||
424 | mask = ring->get_cmd_length_mask(cmd_header); | |
425 | if (!mask) | |
426 | return NULL; | |
427 | ||
428 | BUG_ON(!default_desc); | |
429 | default_desc->flags = CMD_DESC_SKIP; | |
430 | default_desc->length.mask = mask; | |
431 | ||
432 | return default_desc; | |
433 | } | |
434 | ||
435 | static bool valid_reg(const u32 *table, int count, u32 addr) | |
436 | { | |
437 | if (table && count != 0) { | |
438 | int i; | |
439 | ||
440 | for (i = 0; i < count; i++) { | |
441 | if (table[i] == addr) | |
442 | return true; | |
443 | } | |
444 | } | |
445 | ||
446 | return false; | |
447 | } | |
448 | ||
449 | static u32 *vmap_batch(struct drm_i915_gem_object *obj) | |
450 | { | |
451 | int i; | |
452 | void *addr = NULL; | |
453 | struct sg_page_iter sg_iter; | |
454 | struct page **pages; | |
455 | ||
456 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); | |
457 | if (pages == NULL) { | |
458 | DRM_DEBUG_DRIVER("Failed to get space for pages\n"); | |
459 | goto finish; | |
460 | } | |
461 | ||
462 | i = 0; | |
463 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
464 | pages[i] = sg_page_iter_page(&sg_iter); | |
465 | i++; | |
466 | } | |
467 | ||
468 | addr = vmap(pages, i, 0, PAGE_KERNEL); | |
469 | if (addr == NULL) { | |
470 | DRM_DEBUG_DRIVER("Failed to vmap pages\n"); | |
471 | goto finish; | |
472 | } | |
473 | ||
474 | finish: | |
475 | if (pages) | |
476 | drm_free_large(pages); | |
477 | return (u32*)addr; | |
478 | } | |
479 | ||
480 | /** | |
481 | * i915_needs_cmd_parser() - should a given ring use software command parsing? | |
482 | * @ring: the ring in question | |
483 | * | |
484 | * Only certain platforms require software batch buffer command parsing, and | |
485 | * only when enabled via module paramter. | |
486 | * | |
487 | * Return: true if the ring requires software command parsing | |
488 | */ | |
489 | bool i915_needs_cmd_parser(struct intel_ring_buffer *ring) | |
490 | { | |
491 | /* No command tables indicates a platform without parsing */ | |
492 | if (!ring->cmd_tables) | |
493 | return false; | |
494 | ||
495 | return (i915.enable_cmd_parser == 1); | |
496 | } | |
497 | ||
498 | #define LENGTH_BIAS 2 | |
499 | ||
500 | /** | |
501 | * i915_parse_cmds() - parse a submitted batch buffer for privilege violations | |
502 | * @ring: the ring on which the batch is to execute | |
503 | * @batch_obj: the batch buffer in question | |
504 | * @batch_start_offset: byte offset in the batch at which execution starts | |
505 | * @is_master: is the submitting process the drm master? | |
506 | * | |
507 | * Parses the specified batch buffer looking for privilege violations as | |
508 | * described in the overview. | |
509 | * | |
510 | * Return: non-zero if the parser finds violations or otherwise fails | |
511 | */ | |
512 | int i915_parse_cmds(struct intel_ring_buffer *ring, | |
513 | struct drm_i915_gem_object *batch_obj, | |
514 | u32 batch_start_offset, | |
515 | bool is_master) | |
516 | { | |
517 | int ret = 0; | |
518 | u32 *cmd, *batch_base, *batch_end; | |
519 | struct drm_i915_cmd_descriptor default_desc = { 0 }; | |
520 | int needs_clflush = 0; | |
521 | ||
522 | ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush); | |
523 | if (ret) { | |
524 | DRM_DEBUG_DRIVER("CMD: failed to prep read\n"); | |
525 | return ret; | |
526 | } | |
527 | ||
528 | batch_base = vmap_batch(batch_obj); | |
529 | if (!batch_base) { | |
530 | DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); | |
531 | i915_gem_object_unpin_pages(batch_obj); | |
532 | return -ENOMEM; | |
533 | } | |
534 | ||
535 | if (needs_clflush) | |
536 | drm_clflush_virt_range((char *)batch_base, batch_obj->base.size); | |
537 | ||
538 | cmd = batch_base + (batch_start_offset / sizeof(*cmd)); | |
539 | batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end)); | |
540 | ||
541 | while (cmd < batch_end) { | |
542 | const struct drm_i915_cmd_descriptor *desc; | |
543 | u32 length; | |
544 | ||
545 | if (*cmd == MI_BATCH_BUFFER_END) | |
546 | break; | |
547 | ||
548 | desc = find_cmd(ring, *cmd, &default_desc); | |
549 | if (!desc) { | |
550 | DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", | |
551 | *cmd); | |
552 | ret = -EINVAL; | |
553 | break; | |
554 | } | |
555 | ||
556 | if (desc->flags & CMD_DESC_FIXED) | |
557 | length = desc->length.fixed; | |
558 | else | |
559 | length = ((*cmd & desc->length.mask) + LENGTH_BIAS); | |
560 | ||
561 | if ((batch_end - cmd) < length) { | |
e5081a53 | 562 | DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n", |
351e3db2 BV |
563 | *cmd, |
564 | length, | |
565 | batch_end - cmd); | |
566 | ret = -EINVAL; | |
567 | break; | |
568 | } | |
569 | ||
570 | if (desc->flags & CMD_DESC_REJECT) { | |
571 | DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); | |
572 | ret = -EINVAL; | |
573 | break; | |
574 | } | |
575 | ||
576 | if ((desc->flags & CMD_DESC_MASTER) && !is_master) { | |
577 | DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", | |
578 | *cmd); | |
579 | ret = -EINVAL; | |
580 | break; | |
581 | } | |
582 | ||
583 | if (desc->flags & CMD_DESC_REGISTER) { | |
584 | u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask; | |
585 | ||
586 | if (!valid_reg(ring->reg_table, | |
587 | ring->reg_count, reg_addr)) { | |
588 | if (!is_master || | |
589 | !valid_reg(ring->master_reg_table, | |
590 | ring->master_reg_count, | |
591 | reg_addr)) { | |
592 | DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", | |
593 | reg_addr, | |
594 | *cmd, | |
595 | ring->id); | |
596 | ret = -EINVAL; | |
597 | break; | |
598 | } | |
599 | } | |
600 | } | |
601 | ||
602 | if (desc->flags & CMD_DESC_BITMASK) { | |
603 | int i; | |
604 | ||
605 | for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { | |
606 | u32 dword; | |
607 | ||
608 | if (desc->bits[i].mask == 0) | |
609 | break; | |
610 | ||
611 | dword = cmd[desc->bits[i].offset] & | |
612 | desc->bits[i].mask; | |
613 | ||
614 | if (dword != desc->bits[i].expected) { | |
615 | DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", | |
616 | *cmd, | |
617 | desc->bits[i].mask, | |
618 | desc->bits[i].expected, | |
619 | dword, ring->id); | |
620 | ret = -EINVAL; | |
621 | break; | |
622 | } | |
623 | } | |
624 | ||
625 | if (ret) | |
626 | break; | |
627 | } | |
628 | ||
629 | cmd += length; | |
630 | } | |
631 | ||
632 | if (cmd >= batch_end) { | |
633 | DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); | |
634 | ret = -EINVAL; | |
635 | } | |
636 | ||
637 | vunmap(batch_base); | |
638 | ||
639 | i915_gem_object_unpin_pages(batch_obj); | |
640 | ||
641 | return ret; | |
642 | } |