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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
36cdd013 DW |
43 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
44 | { | |
45 | return to_i915(node->minor->dev); | |
46 | } | |
47 | ||
497666d8 DL |
48 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
49 | * allocated we need to hook into the minor for release. */ | |
50 | static int | |
51 | drm_add_fake_info_node(struct drm_minor *minor, | |
52 | struct dentry *ent, | |
53 | const void *key) | |
54 | { | |
55 | struct drm_info_node *node; | |
56 | ||
57 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
58 | if (node == NULL) { | |
59 | debugfs_remove(ent); | |
60 | return -ENOMEM; | |
61 | } | |
62 | ||
63 | node->minor = minor; | |
64 | node->dent = ent; | |
36cdd013 | 65 | node->info_ent = (void *)key; |
497666d8 DL |
66 | |
67 | mutex_lock(&minor->debugfs_lock); | |
68 | list_add(&node->list, &minor->debugfs_list); | |
69 | mutex_unlock(&minor->debugfs_lock); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
70d39fe4 CW |
74 | static int i915_capabilities(struct seq_file *m, void *data) |
75 | { | |
36cdd013 DW |
76 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
77 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 78 | |
36cdd013 DW |
79 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
80 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); | |
79fc46df DL |
81 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
82 | #define SEP_SEMICOLON ; | |
83 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
84 | #undef PRINT_FLAG | |
85 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
86 | |
87 | return 0; | |
88 | } | |
2017263e | 89 | |
a7363de7 | 90 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 91 | { |
573adb39 | 92 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
93 | } |
94 | ||
a7363de7 | 95 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
96 | { |
97 | return obj->pin_display ? 'p' : ' '; | |
98 | } | |
99 | ||
a7363de7 | 100 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 101 | { |
3e510a8e | 102 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 103 | default: |
be12a86b TU |
104 | case I915_TILING_NONE: return ' '; |
105 | case I915_TILING_X: return 'X'; | |
106 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 107 | } |
a6172a80 CW |
108 | } |
109 | ||
a7363de7 | 110 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 111 | { |
058d88c4 | 112 | return i915_gem_object_to_ggtt(obj, NULL) ? 'g' : ' '; |
be12a86b TU |
113 | } |
114 | ||
a7363de7 | 115 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 116 | { |
be12a86b | 117 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
118 | } |
119 | ||
ca1543be TU |
120 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
121 | { | |
122 | u64 size = 0; | |
123 | struct i915_vma *vma; | |
124 | ||
1c7f4bca | 125 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 126 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
127 | size += vma->node.size; |
128 | } | |
129 | ||
130 | return size; | |
131 | } | |
132 | ||
37811fcc CW |
133 | static void |
134 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
135 | { | |
b4716185 | 136 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 137 | struct intel_engine_cs *engine; |
1d693bcc | 138 | struct i915_vma *vma; |
faf5bf0a | 139 | unsigned int frontbuffer_bits; |
d7f46fc4 | 140 | int pin_count = 0; |
c3232b18 | 141 | enum intel_engine_id id; |
d7f46fc4 | 142 | |
188c1ab7 CW |
143 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
144 | ||
be12a86b | 145 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 146 | &obj->base, |
be12a86b | 147 | get_active_flag(obj), |
37811fcc CW |
148 | get_pin_flag(obj), |
149 | get_tiling_flag(obj), | |
1d693bcc | 150 | get_global_flag(obj), |
be12a86b | 151 | get_pin_mapped_flag(obj), |
a05a5862 | 152 | obj->base.size / 1024, |
37811fcc | 153 | obj->base.read_domains, |
b4716185 | 154 | obj->base.write_domain); |
c3232b18 | 155 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 156 | seq_printf(m, "%x ", |
d72d908b CW |
157 | i915_gem_active_get_seqno(&obj->last_read[id], |
158 | &obj->base.dev->struct_mutex)); | |
49ef5294 | 159 | seq_printf(m, "] %x %s%s%s", |
d72d908b CW |
160 | i915_gem_active_get_seqno(&obj->last_write, |
161 | &obj->base.dev->struct_mutex), | |
36cdd013 | 162 | i915_cache_level_str(dev_priv, obj->cache_level), |
37811fcc CW |
163 | obj->dirty ? " dirty" : "", |
164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
165 | if (obj->base.name) | |
166 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 168 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 169 | pin_count++; |
ba0635ff DC |
170 | } |
171 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
172 | if (obj->pin_display) |
173 | seq_printf(m, " (display)"); | |
1c7f4bca | 174 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
175 | if (!drm_mm_node_allocated(&vma->node)) |
176 | continue; | |
177 | ||
8d2fdc3f | 178 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 179 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 180 | vma->node.start, vma->node.size); |
3272db53 | 181 | if (i915_vma_is_ggtt(vma)) |
596c5923 | 182 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
49ef5294 CW |
183 | if (vma->fence) |
184 | seq_printf(m, " , fence: %d%s", | |
185 | vma->fence->id, | |
186 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 187 | seq_puts(m, ")"); |
1d693bcc | 188 | } |
c1ad11fc | 189 | if (obj->stolen) |
440fd528 | 190 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 191 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 192 | char s[3], *t = s; |
30154650 | 193 | if (obj->pin_display) |
6299f992 CW |
194 | *t++ = 'p'; |
195 | if (obj->fault_mappable) | |
196 | *t++ = 'f'; | |
197 | *t = '\0'; | |
198 | seq_printf(m, " (%s mappable)", s); | |
199 | } | |
27c01aae | 200 | |
d72d908b | 201 | engine = i915_gem_active_get_engine(&obj->last_write, |
36cdd013 | 202 | &dev_priv->drm.struct_mutex); |
27c01aae CW |
203 | if (engine) |
204 | seq_printf(m, " (%s)", engine->name); | |
205 | ||
faf5bf0a CW |
206 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
207 | if (frontbuffer_bits) | |
208 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
209 | } |
210 | ||
6d2b8885 CW |
211 | static int obj_rank_by_stolen(void *priv, |
212 | struct list_head *A, struct list_head *B) | |
213 | { | |
214 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 215 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 216 | struct drm_i915_gem_object *b = |
b25cb2f8 | 217 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 218 | |
2d05fa16 RV |
219 | if (a->stolen->start < b->stolen->start) |
220 | return -1; | |
221 | if (a->stolen->start > b->stolen->start) | |
222 | return 1; | |
223 | return 0; | |
6d2b8885 CW |
224 | } |
225 | ||
226 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
227 | { | |
36cdd013 DW |
228 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
229 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 230 | struct drm_i915_gem_object *obj; |
c44ef60e | 231 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
232 | LIST_HEAD(stolen); |
233 | int count, ret; | |
234 | ||
235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
236 | if (ret) | |
237 | return ret; | |
238 | ||
239 | total_obj_size = total_gtt_size = count = 0; | |
240 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
241 | if (obj->stolen == NULL) | |
242 | continue; | |
243 | ||
b25cb2f8 | 244 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
245 | |
246 | total_obj_size += obj->base.size; | |
ca1543be | 247 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
248 | count++; |
249 | } | |
250 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
251 | if (obj->stolen == NULL) | |
252 | continue; | |
253 | ||
b25cb2f8 | 254 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
255 | |
256 | total_obj_size += obj->base.size; | |
257 | count++; | |
258 | } | |
259 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
260 | seq_puts(m, "Stolen:\n"); | |
261 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 262 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
263 | seq_puts(m, " "); |
264 | describe_obj(m, obj); | |
265 | seq_putc(m, '\n'); | |
b25cb2f8 | 266 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
267 | } |
268 | mutex_unlock(&dev->struct_mutex); | |
269 | ||
c44ef60e | 270 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
271 | count, total_obj_size, total_gtt_size); |
272 | return 0; | |
273 | } | |
274 | ||
2db8e9d6 | 275 | struct file_stats { |
6313c204 | 276 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
277 | unsigned long count; |
278 | u64 total, unbound; | |
279 | u64 global, shared; | |
280 | u64 active, inactive; | |
2db8e9d6 CW |
281 | }; |
282 | ||
283 | static int per_file_stats(int id, void *ptr, void *data) | |
284 | { | |
285 | struct drm_i915_gem_object *obj = ptr; | |
286 | struct file_stats *stats = data; | |
6313c204 | 287 | struct i915_vma *vma; |
2db8e9d6 CW |
288 | |
289 | stats->count++; | |
290 | stats->total += obj->base.size; | |
15717de2 CW |
291 | if (!obj->bind_count) |
292 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
293 | if (obj->base.name || obj->base.dma_buf) |
294 | stats->shared += obj->base.size; | |
295 | ||
894eeecc CW |
296 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
297 | if (!drm_mm_node_allocated(&vma->node)) | |
298 | continue; | |
6313c204 | 299 | |
3272db53 | 300 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
301 | stats->global += vma->node.size; |
302 | } else { | |
303 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 304 | |
2bfa996e | 305 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 306 | continue; |
6313c204 | 307 | } |
894eeecc | 308 | |
b0decaf7 | 309 | if (i915_vma_is_active(vma)) |
894eeecc CW |
310 | stats->active += vma->node.size; |
311 | else | |
312 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
313 | } |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
b0da1b79 CW |
318 | #define print_file_stats(m, name, stats) do { \ |
319 | if (stats.count) \ | |
c44ef60e | 320 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
321 | name, \ |
322 | stats.count, \ | |
323 | stats.total, \ | |
324 | stats.active, \ | |
325 | stats.inactive, \ | |
326 | stats.global, \ | |
327 | stats.shared, \ | |
328 | stats.unbound); \ | |
329 | } while (0) | |
493018dc BV |
330 | |
331 | static void print_batch_pool_stats(struct seq_file *m, | |
332 | struct drm_i915_private *dev_priv) | |
333 | { | |
334 | struct drm_i915_gem_object *obj; | |
335 | struct file_stats stats; | |
e2f80391 | 336 | struct intel_engine_cs *engine; |
b4ac5afc | 337 | int j; |
493018dc BV |
338 | |
339 | memset(&stats, 0, sizeof(stats)); | |
340 | ||
b4ac5afc | 341 | for_each_engine(engine, dev_priv) { |
e2f80391 | 342 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 343 | list_for_each_entry(obj, |
e2f80391 | 344 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
345 | batch_pool_link) |
346 | per_file_stats(0, obj, &stats); | |
347 | } | |
06fbca71 | 348 | } |
493018dc | 349 | |
b0da1b79 | 350 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
351 | } |
352 | ||
15da9565 CW |
353 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
354 | { | |
355 | struct i915_gem_context *ctx = ptr; | |
356 | int n; | |
357 | ||
358 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
359 | if (ctx->engine[n].state) | |
bf3783e5 | 360 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 361 | if (ctx->engine[n].ring) |
57e88531 | 362 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
363 | } |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static void print_context_stats(struct seq_file *m, | |
369 | struct drm_i915_private *dev_priv) | |
370 | { | |
36cdd013 | 371 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
372 | struct file_stats stats; |
373 | struct drm_file *file; | |
374 | ||
375 | memset(&stats, 0, sizeof(stats)); | |
376 | ||
36cdd013 | 377 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
378 | if (dev_priv->kernel_context) |
379 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
380 | ||
36cdd013 | 381 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
382 | struct drm_i915_file_private *fpriv = file->driver_priv; |
383 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
384 | } | |
36cdd013 | 385 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
386 | |
387 | print_file_stats(m, "[k]contexts", stats); | |
388 | } | |
389 | ||
36cdd013 | 390 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 391 | { |
36cdd013 DW |
392 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
393 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 394 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
395 | u32 count, mapped_count, purgeable_count, dpy_count; |
396 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 397 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 398 | struct drm_file *file; |
73aa808f CW |
399 | int ret; |
400 | ||
401 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
402 | if (ret) | |
403 | return ret; | |
404 | ||
6299f992 CW |
405 | seq_printf(m, "%u objects, %zu bytes\n", |
406 | dev_priv->mm.object_count, | |
407 | dev_priv->mm.object_memory); | |
408 | ||
1544c42e CW |
409 | size = count = 0; |
410 | mapped_size = mapped_count = 0; | |
411 | purgeable_size = purgeable_count = 0; | |
35c20a60 | 412 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
2bd160a1 CW |
413 | size += obj->base.size; |
414 | ++count; | |
415 | ||
416 | if (obj->madv == I915_MADV_DONTNEED) { | |
417 | purgeable_size += obj->base.size; | |
418 | ++purgeable_count; | |
419 | } | |
420 | ||
be19b10d | 421 | if (obj->mapping) { |
2bd160a1 CW |
422 | mapped_count++; |
423 | mapped_size += obj->base.size; | |
be19b10d | 424 | } |
b7abb714 | 425 | } |
c44ef60e | 426 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 427 | |
2bd160a1 | 428 | size = count = dpy_size = dpy_count = 0; |
35c20a60 | 429 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2bd160a1 CW |
430 | size += obj->base.size; |
431 | ++count; | |
432 | ||
30154650 | 433 | if (obj->pin_display) { |
2bd160a1 CW |
434 | dpy_size += obj->base.size; |
435 | ++dpy_count; | |
6299f992 | 436 | } |
2bd160a1 | 437 | |
b7abb714 CW |
438 | if (obj->madv == I915_MADV_DONTNEED) { |
439 | purgeable_size += obj->base.size; | |
440 | ++purgeable_count; | |
441 | } | |
2bd160a1 | 442 | |
be19b10d | 443 | if (obj->mapping) { |
2bd160a1 CW |
444 | mapped_count++; |
445 | mapped_size += obj->base.size; | |
be19b10d | 446 | } |
6299f992 | 447 | } |
2bd160a1 CW |
448 | seq_printf(m, "%u bound objects, %llu bytes\n", |
449 | count, size); | |
c44ef60e | 450 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 451 | purgeable_count, purgeable_size); |
2bd160a1 CW |
452 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
453 | mapped_count, mapped_size); | |
454 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
455 | dpy_count, dpy_size); | |
6299f992 | 456 | |
c44ef60e | 457 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 458 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 459 | |
493018dc BV |
460 | seq_putc(m, '\n'); |
461 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
462 | mutex_unlock(&dev->struct_mutex); |
463 | ||
464 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 465 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
466 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
467 | struct file_stats stats; | |
c84455b4 CW |
468 | struct drm_i915_file_private *file_priv = file->driver_priv; |
469 | struct drm_i915_gem_request *request; | |
3ec2f427 | 470 | struct task_struct *task; |
2db8e9d6 CW |
471 | |
472 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 473 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 474 | spin_lock(&file->table_lock); |
2db8e9d6 | 475 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 476 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
477 | /* |
478 | * Although we have a valid reference on file->pid, that does | |
479 | * not guarantee that the task_struct who called get_pid() is | |
480 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
481 | * Therefore, we need to protect this ->comm access using RCU. | |
482 | */ | |
c84455b4 CW |
483 | mutex_lock(&dev->struct_mutex); |
484 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
485 | struct drm_i915_gem_request, | |
486 | client_list); | |
3ec2f427 | 487 | rcu_read_lock(); |
c84455b4 CW |
488 | task = pid_task(request && request->ctx->pid ? |
489 | request->ctx->pid : file->pid, | |
490 | PIDTYPE_PID); | |
493018dc | 491 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 492 | rcu_read_unlock(); |
c84455b4 | 493 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 494 | } |
1d2ac403 | 495 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
aee56cff | 500 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 501 | { |
9f25d007 | 502 | struct drm_info_node *node = m->private; |
36cdd013 DW |
503 | struct drm_i915_private *dev_priv = node_to_i915(node); |
504 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 505 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 506 | struct drm_i915_gem_object *obj; |
c44ef60e | 507 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
508 | int count, ret; |
509 | ||
510 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
514 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 515 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6da84829 | 516 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
517 | continue; |
518 | ||
267f0c90 | 519 | seq_puts(m, " "); |
08c18323 | 520 | describe_obj(m, obj); |
267f0c90 | 521 | seq_putc(m, '\n'); |
08c18323 | 522 | total_obj_size += obj->base.size; |
ca1543be | 523 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
524 | count++; |
525 | } | |
526 | ||
527 | mutex_unlock(&dev->struct_mutex); | |
528 | ||
c44ef60e | 529 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
530 | count, total_obj_size, total_gtt_size); |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
4e5359cd SF |
535 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
536 | { | |
36cdd013 DW |
537 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
538 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 539 | struct intel_crtc *crtc; |
8a270ebf DV |
540 | int ret; |
541 | ||
542 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
543 | if (ret) | |
544 | return ret; | |
4e5359cd | 545 | |
d3fcc808 | 546 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
547 | const char pipe = pipe_name(crtc->pipe); |
548 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 549 | struct intel_flip_work *work; |
4e5359cd | 550 | |
5e2d7afc | 551 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
552 | work = crtc->flip_work; |
553 | if (work == NULL) { | |
9db4a9c7 | 554 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
555 | pipe, plane); |
556 | } else { | |
5a21b665 DV |
557 | u32 pending; |
558 | u32 addr; | |
559 | ||
560 | pending = atomic_read(&work->pending); | |
561 | if (pending) { | |
562 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
563 | pipe, plane); | |
564 | } else { | |
565 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
566 | pipe, plane); | |
567 | } | |
568 | if (work->flip_queued_req) { | |
569 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
570 | ||
571 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
572 | engine->name, | |
573 | i915_gem_request_get_seqno(work->flip_queued_req), | |
574 | dev_priv->next_seqno, | |
1b7744e7 | 575 | intel_engine_get_seqno(engine), |
f69a02c9 | 576 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
577 | } else |
578 | seq_printf(m, "Flip not associated with any ring\n"); | |
579 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
580 | work->flip_queued_vblank, | |
581 | work->flip_ready_vblank, | |
582 | intel_crtc_get_vblank_counter(crtc)); | |
583 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
584 | ||
36cdd013 | 585 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
586 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
587 | else | |
588 | addr = I915_READ(DSPADDR(crtc->plane)); | |
589 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
590 | ||
591 | if (work->pending_flip_obj) { | |
592 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
593 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
594 | } |
595 | } | |
5e2d7afc | 596 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
597 | } |
598 | ||
8a270ebf DV |
599 | mutex_unlock(&dev->struct_mutex); |
600 | ||
4e5359cd SF |
601 | return 0; |
602 | } | |
603 | ||
493018dc BV |
604 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
605 | { | |
36cdd013 DW |
606 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
607 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 608 | struct drm_i915_gem_object *obj; |
e2f80391 | 609 | struct intel_engine_cs *engine; |
8d9d5744 | 610 | int total = 0; |
b4ac5afc | 611 | int ret, j; |
493018dc BV |
612 | |
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
b4ac5afc | 617 | for_each_engine(engine, dev_priv) { |
e2f80391 | 618 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
619 | int count; |
620 | ||
621 | count = 0; | |
622 | list_for_each_entry(obj, | |
e2f80391 | 623 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
624 | batch_pool_link) |
625 | count++; | |
626 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 627 | engine->name, j, count); |
8d9d5744 CW |
628 | |
629 | list_for_each_entry(obj, | |
e2f80391 | 630 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
631 | batch_pool_link) { |
632 | seq_puts(m, " "); | |
633 | describe_obj(m, obj); | |
634 | seq_putc(m, '\n'); | |
635 | } | |
636 | ||
637 | total += count; | |
06fbca71 | 638 | } |
493018dc BV |
639 | } |
640 | ||
8d9d5744 | 641 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
642 | |
643 | mutex_unlock(&dev->struct_mutex); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
2017263e BG |
648 | static int i915_gem_request_info(struct seq_file *m, void *data) |
649 | { | |
36cdd013 DW |
650 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
651 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 652 | struct intel_engine_cs *engine; |
eed29a5b | 653 | struct drm_i915_gem_request *req; |
b4ac5afc | 654 | int ret, any; |
de227ef0 CW |
655 | |
656 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
657 | if (ret) | |
658 | return ret; | |
2017263e | 659 | |
2d1070b2 | 660 | any = 0; |
b4ac5afc | 661 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
662 | int count; |
663 | ||
664 | count = 0; | |
efdf7c06 | 665 | list_for_each_entry(req, &engine->request_list, link) |
2d1070b2 CW |
666 | count++; |
667 | if (count == 0) | |
a2c7f6fd CW |
668 | continue; |
669 | ||
e2f80391 | 670 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
efdf7c06 | 671 | list_for_each_entry(req, &engine->request_list, link) { |
c84455b4 | 672 | struct pid *pid = req->ctx->pid; |
2d1070b2 CW |
673 | struct task_struct *task; |
674 | ||
675 | rcu_read_lock(); | |
c84455b4 | 676 | task = pid ? pid_task(pid, PIDTYPE_PID) : NULL; |
2d1070b2 | 677 | seq_printf(m, " %x @ %d: %s [%d]\n", |
04769652 | 678 | req->fence.seqno, |
eed29a5b | 679 | (int) (jiffies - req->emitted_jiffies), |
2d1070b2 CW |
680 | task ? task->comm : "<unknown>", |
681 | task ? task->pid : -1); | |
682 | rcu_read_unlock(); | |
c2c347a9 | 683 | } |
2d1070b2 CW |
684 | |
685 | any++; | |
2017263e | 686 | } |
de227ef0 CW |
687 | mutex_unlock(&dev->struct_mutex); |
688 | ||
2d1070b2 | 689 | if (any == 0) |
267f0c90 | 690 | seq_puts(m, "No requests\n"); |
c2c347a9 | 691 | |
2017263e BG |
692 | return 0; |
693 | } | |
694 | ||
b2223497 | 695 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 696 | struct intel_engine_cs *engine) |
b2223497 | 697 | { |
688e6c72 CW |
698 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
699 | struct rb_node *rb; | |
700 | ||
12471ba8 | 701 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 702 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 CW |
703 | |
704 | spin_lock(&b->lock); | |
705 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
706 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
707 | ||
708 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
709 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
710 | } | |
711 | spin_unlock(&b->lock); | |
b2223497 CW |
712 | } |
713 | ||
2017263e BG |
714 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
715 | { | |
36cdd013 | 716 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 717 | struct intel_engine_cs *engine; |
2017263e | 718 | |
b4ac5afc | 719 | for_each_engine(engine, dev_priv) |
e2f80391 | 720 | i915_ring_seqno_info(m, engine); |
de227ef0 | 721 | |
2017263e BG |
722 | return 0; |
723 | } | |
724 | ||
725 | ||
726 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
727 | { | |
36cdd013 DW |
728 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
729 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 730 | struct intel_engine_cs *engine; |
9db4a9c7 | 731 | int ret, i, pipe; |
de227ef0 CW |
732 | |
733 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
734 | if (ret) | |
735 | return ret; | |
c8c8fb33 | 736 | intel_runtime_pm_get(dev_priv); |
2017263e | 737 | |
36cdd013 | 738 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
739 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
740 | I915_READ(GEN8_MASTER_IRQ)); | |
741 | ||
742 | seq_printf(m, "Display IER:\t%08x\n", | |
743 | I915_READ(VLV_IER)); | |
744 | seq_printf(m, "Display IIR:\t%08x\n", | |
745 | I915_READ(VLV_IIR)); | |
746 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
747 | I915_READ(VLV_IIR_RW)); | |
748 | seq_printf(m, "Display IMR:\t%08x\n", | |
749 | I915_READ(VLV_IMR)); | |
055e393f | 750 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
751 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
752 | pipe_name(pipe), | |
753 | I915_READ(PIPESTAT(pipe))); | |
754 | ||
755 | seq_printf(m, "Port hotplug:\t%08x\n", | |
756 | I915_READ(PORT_HOTPLUG_EN)); | |
757 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
758 | I915_READ(VLV_DPFLIPSTAT)); | |
759 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
760 | I915_READ(DPINVGTT)); | |
761 | ||
762 | for (i = 0; i < 4; i++) { | |
763 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
764 | i, I915_READ(GEN8_GT_IMR(i))); | |
765 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
766 | i, I915_READ(GEN8_GT_IIR(i))); | |
767 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
768 | i, I915_READ(GEN8_GT_IER(i))); | |
769 | } | |
770 | ||
771 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
772 | I915_READ(GEN8_PCU_IMR)); | |
773 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
774 | I915_READ(GEN8_PCU_IIR)); | |
775 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
776 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 777 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
778 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
779 | I915_READ(GEN8_MASTER_IRQ)); | |
780 | ||
781 | for (i = 0; i < 4; i++) { | |
782 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
783 | i, I915_READ(GEN8_GT_IMR(i))); | |
784 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
785 | i, I915_READ(GEN8_GT_IIR(i))); | |
786 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
787 | i, I915_READ(GEN8_GT_IER(i))); | |
788 | } | |
789 | ||
055e393f | 790 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
791 | enum intel_display_power_domain power_domain; |
792 | ||
793 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
794 | if (!intel_display_power_get_if_enabled(dev_priv, | |
795 | power_domain)) { | |
22c59960 PZ |
796 | seq_printf(m, "Pipe %c power disabled\n", |
797 | pipe_name(pipe)); | |
798 | continue; | |
799 | } | |
a123f157 | 800 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
801 | pipe_name(pipe), |
802 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 803 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
804 | pipe_name(pipe), |
805 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 806 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
807 | pipe_name(pipe), |
808 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
809 | |
810 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
811 | } |
812 | ||
813 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
814 | I915_READ(GEN8_DE_PORT_IMR)); | |
815 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
816 | I915_READ(GEN8_DE_PORT_IIR)); | |
817 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
818 | I915_READ(GEN8_DE_PORT_IER)); | |
819 | ||
820 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
821 | I915_READ(GEN8_DE_MISC_IMR)); | |
822 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
823 | I915_READ(GEN8_DE_MISC_IIR)); | |
824 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
825 | I915_READ(GEN8_DE_MISC_IER)); | |
826 | ||
827 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
828 | I915_READ(GEN8_PCU_IMR)); | |
829 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
830 | I915_READ(GEN8_PCU_IIR)); | |
831 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
832 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 833 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
834 | seq_printf(m, "Display IER:\t%08x\n", |
835 | I915_READ(VLV_IER)); | |
836 | seq_printf(m, "Display IIR:\t%08x\n", | |
837 | I915_READ(VLV_IIR)); | |
838 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
839 | I915_READ(VLV_IIR_RW)); | |
840 | seq_printf(m, "Display IMR:\t%08x\n", | |
841 | I915_READ(VLV_IMR)); | |
055e393f | 842 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
843 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
844 | pipe_name(pipe), | |
845 | I915_READ(PIPESTAT(pipe))); | |
846 | ||
847 | seq_printf(m, "Master IER:\t%08x\n", | |
848 | I915_READ(VLV_MASTER_IER)); | |
849 | ||
850 | seq_printf(m, "Render IER:\t%08x\n", | |
851 | I915_READ(GTIER)); | |
852 | seq_printf(m, "Render IIR:\t%08x\n", | |
853 | I915_READ(GTIIR)); | |
854 | seq_printf(m, "Render IMR:\t%08x\n", | |
855 | I915_READ(GTIMR)); | |
856 | ||
857 | seq_printf(m, "PM IER:\t\t%08x\n", | |
858 | I915_READ(GEN6_PMIER)); | |
859 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
860 | I915_READ(GEN6_PMIIR)); | |
861 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
862 | I915_READ(GEN6_PMIMR)); | |
863 | ||
864 | seq_printf(m, "Port hotplug:\t%08x\n", | |
865 | I915_READ(PORT_HOTPLUG_EN)); | |
866 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
867 | I915_READ(VLV_DPFLIPSTAT)); | |
868 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
869 | I915_READ(DPINVGTT)); | |
870 | ||
36cdd013 | 871 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
872 | seq_printf(m, "Interrupt enable: %08x\n", |
873 | I915_READ(IER)); | |
874 | seq_printf(m, "Interrupt identity: %08x\n", | |
875 | I915_READ(IIR)); | |
876 | seq_printf(m, "Interrupt mask: %08x\n", | |
877 | I915_READ(IMR)); | |
055e393f | 878 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
879 | seq_printf(m, "Pipe %c stat: %08x\n", |
880 | pipe_name(pipe), | |
881 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
882 | } else { |
883 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
884 | I915_READ(DEIER)); | |
885 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
886 | I915_READ(DEIIR)); | |
887 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
888 | I915_READ(DEIMR)); | |
889 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
890 | I915_READ(SDEIER)); | |
891 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
892 | I915_READ(SDEIIR)); | |
893 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
894 | I915_READ(SDEIMR)); | |
895 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
896 | I915_READ(GTIER)); | |
897 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
898 | I915_READ(GTIIR)); | |
899 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
900 | I915_READ(GTIMR)); | |
901 | } | |
b4ac5afc | 902 | for_each_engine(engine, dev_priv) { |
36cdd013 | 903 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
904 | seq_printf(m, |
905 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 906 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 907 | } |
e2f80391 | 908 | i915_ring_seqno_info(m, engine); |
9862e600 | 909 | } |
c8c8fb33 | 910 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
911 | mutex_unlock(&dev->struct_mutex); |
912 | ||
2017263e BG |
913 | return 0; |
914 | } | |
915 | ||
a6172a80 CW |
916 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
917 | { | |
36cdd013 DW |
918 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
919 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
920 | int i, ret; |
921 | ||
922 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
923 | if (ret) | |
924 | return ret; | |
a6172a80 | 925 | |
a6172a80 CW |
926 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
927 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 928 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 929 | |
6c085a72 CW |
930 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
931 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 932 | if (!vma) |
267f0c90 | 933 | seq_puts(m, "unused"); |
c2c347a9 | 934 | else |
49ef5294 | 935 | describe_obj(m, vma->obj); |
267f0c90 | 936 | seq_putc(m, '\n'); |
a6172a80 CW |
937 | } |
938 | ||
05394f39 | 939 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
940 | return 0; |
941 | } | |
942 | ||
2017263e BG |
943 | static int i915_hws_info(struct seq_file *m, void *data) |
944 | { | |
9f25d007 | 945 | struct drm_info_node *node = m->private; |
36cdd013 | 946 | struct drm_i915_private *dev_priv = node_to_i915(node); |
e2f80391 | 947 | struct intel_engine_cs *engine; |
1a240d4d | 948 | const u32 *hws; |
4066c0ae CW |
949 | int i; |
950 | ||
4a570db5 | 951 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 952 | hws = engine->status_page.page_addr; |
2017263e BG |
953 | if (hws == NULL) |
954 | return 0; | |
955 | ||
956 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
957 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
958 | i * 4, | |
959 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
960 | } | |
961 | return 0; | |
962 | } | |
963 | ||
d5442303 DV |
964 | static ssize_t |
965 | i915_error_state_write(struct file *filp, | |
966 | const char __user *ubuf, | |
967 | size_t cnt, | |
968 | loff_t *ppos) | |
969 | { | |
edc3d884 | 970 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
971 | |
972 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
662d19e7 | 973 | i915_destroy_error_state(error_priv->dev); |
d5442303 DV |
974 | |
975 | return cnt; | |
976 | } | |
977 | ||
978 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
979 | { | |
36cdd013 | 980 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 981 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
982 | |
983 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
984 | if (!error_priv) | |
985 | return -ENOMEM; | |
986 | ||
36cdd013 | 987 | error_priv->dev = &dev_priv->drm; |
d5442303 | 988 | |
36cdd013 | 989 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 990 | |
edc3d884 MK |
991 | file->private_data = error_priv; |
992 | ||
993 | return 0; | |
d5442303 DV |
994 | } |
995 | ||
996 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
997 | { | |
edc3d884 | 998 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 999 | |
95d5bfb3 | 1000 | i915_error_state_put(error_priv); |
d5442303 DV |
1001 | kfree(error_priv); |
1002 | ||
edc3d884 MK |
1003 | return 0; |
1004 | } | |
1005 | ||
4dc955f7 MK |
1006 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1007 | size_t count, loff_t *pos) | |
1008 | { | |
1009 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1010 | struct drm_i915_error_state_buf error_str; | |
1011 | loff_t tmp_pos = 0; | |
1012 | ssize_t ret_count = 0; | |
1013 | int ret; | |
1014 | ||
36cdd013 DW |
1015 | ret = i915_error_state_buf_init(&error_str, |
1016 | to_i915(error_priv->dev), count, *pos); | |
4dc955f7 MK |
1017 | if (ret) |
1018 | return ret; | |
edc3d884 | 1019 | |
fc16b48b | 1020 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1021 | if (ret) |
1022 | goto out; | |
1023 | ||
edc3d884 MK |
1024 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1025 | error_str.buf, | |
1026 | error_str.bytes); | |
1027 | ||
1028 | if (ret_count < 0) | |
1029 | ret = ret_count; | |
1030 | else | |
1031 | *pos = error_str.start + ret_count; | |
1032 | out: | |
4dc955f7 | 1033 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1034 | return ret ?: ret_count; |
d5442303 DV |
1035 | } |
1036 | ||
1037 | static const struct file_operations i915_error_state_fops = { | |
1038 | .owner = THIS_MODULE, | |
1039 | .open = i915_error_state_open, | |
edc3d884 | 1040 | .read = i915_error_state_read, |
d5442303 DV |
1041 | .write = i915_error_state_write, |
1042 | .llseek = default_llseek, | |
1043 | .release = i915_error_state_release, | |
1044 | }; | |
1045 | ||
647416f9 KC |
1046 | static int |
1047 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1048 | { |
36cdd013 | 1049 | struct drm_i915_private *dev_priv = data; |
40633219 MK |
1050 | int ret; |
1051 | ||
36cdd013 | 1052 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
40633219 MK |
1053 | if (ret) |
1054 | return ret; | |
1055 | ||
647416f9 | 1056 | *val = dev_priv->next_seqno; |
36cdd013 | 1057 | mutex_unlock(&dev_priv->drm.struct_mutex); |
40633219 | 1058 | |
647416f9 | 1059 | return 0; |
40633219 MK |
1060 | } |
1061 | ||
647416f9 KC |
1062 | static int |
1063 | i915_next_seqno_set(void *data, u64 val) | |
1064 | { | |
36cdd013 DW |
1065 | struct drm_i915_private *dev_priv = data; |
1066 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1067 | int ret; |
1068 | ||
40633219 MK |
1069 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1070 | if (ret) | |
1071 | return ret; | |
1072 | ||
e94fbaa8 | 1073 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1074 | mutex_unlock(&dev->struct_mutex); |
1075 | ||
647416f9 | 1076 | return ret; |
40633219 MK |
1077 | } |
1078 | ||
647416f9 KC |
1079 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1080 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1081 | "0x%llx\n"); |
40633219 | 1082 | |
adb4bd12 | 1083 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1084 | { |
36cdd013 DW |
1085 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1086 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1087 | int ret = 0; |
1088 | ||
1089 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1090 | |
36cdd013 | 1091 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1092 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1093 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1094 | ||
1095 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1096 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1097 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1098 | MEMSTAT_VID_SHIFT); | |
1099 | seq_printf(m, "Current P-state: %d\n", | |
1100 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1101 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1102 | u32 freq_sts; |
1103 | ||
1104 | mutex_lock(&dev_priv->rps.hw_lock); | |
1105 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1106 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1107 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1108 | ||
1109 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1110 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1111 | ||
1112 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1113 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1114 | ||
1115 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1116 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1117 | ||
1118 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1119 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1120 | ||
1121 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1122 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1123 | ||
1124 | seq_printf(m, | |
1125 | "efficient (RPe) frequency: %d MHz\n", | |
1126 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1127 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1128 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1129 | u32 rp_state_limits; |
1130 | u32 gt_perf_status; | |
1131 | u32 rp_state_cap; | |
0d8f9491 | 1132 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1133 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1134 | u32 rpupei, rpcurup, rpprevup; |
1135 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1136 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1137 | int max_freq; |
1138 | ||
35040562 | 1139 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
36cdd013 | 1140 | if (IS_BROXTON(dev_priv)) { |
35040562 BP |
1141 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1142 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1143 | } else { | |
1144 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1145 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1146 | } | |
1147 | ||
3b8d8d91 | 1148 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1149 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1150 | if (ret) | |
c8c8fb33 | 1151 | goto out; |
d1ebd816 | 1152 | |
59bad947 | 1153 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1154 | |
8e8c06cd | 1155 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1156 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1157 | reqf >>= 23; |
1158 | else { | |
1159 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1160 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1161 | reqf >>= 24; |
1162 | else | |
1163 | reqf >>= 25; | |
1164 | } | |
7c59a9c1 | 1165 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1166 | |
0d8f9491 CW |
1167 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1168 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1169 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1170 | ||
ccab5c82 | 1171 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1172 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1173 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1174 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1175 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1176 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1177 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1178 | if (IS_GEN9(dev_priv)) |
60260a5b | 1179 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1180 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1181 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1182 | else | |
1183 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1184 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1185 | |
59bad947 | 1186 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1187 | mutex_unlock(&dev->struct_mutex); |
1188 | ||
36cdd013 | 1189 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1190 | pm_ier = I915_READ(GEN6_PMIER); |
1191 | pm_imr = I915_READ(GEN6_PMIMR); | |
1192 | pm_isr = I915_READ(GEN6_PMISR); | |
1193 | pm_iir = I915_READ(GEN6_PMIIR); | |
1194 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1195 | } else { | |
1196 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1197 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1198 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1199 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1200 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1201 | } | |
0d8f9491 | 1202 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1203 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1204 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1205 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1206 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1207 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1208 | seq_printf(m, "Render p-state VID: %d\n", |
1209 | gt_perf_status & 0xff); | |
1210 | seq_printf(m, "Render p-state limit: %d\n", | |
1211 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1212 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1213 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1214 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1215 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1216 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1217 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1218 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1219 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1220 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1221 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1222 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1223 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1224 | seq_printf(m, "Up threshold: %d%%\n", |
1225 | dev_priv->rps.up_threshold); | |
1226 | ||
d6cda9c7 AG |
1227 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1228 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1229 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1230 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1231 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1232 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1233 | seq_printf(m, "Down threshold: %d%%\n", |
1234 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1235 | |
36cdd013 | 1236 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1237 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1238 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1239 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1240 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1241 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1242 | |
1243 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1244 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1245 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1246 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1247 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1248 | |
36cdd013 | 1249 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1250 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1251 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1252 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1253 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1254 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1255 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1256 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1257 | |
d86ed34a CW |
1258 | seq_printf(m, "Current freq: %d MHz\n", |
1259 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1260 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1261 | seq_printf(m, "Idle freq: %d MHz\n", |
1262 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1263 | seq_printf(m, "Min freq: %d MHz\n", |
1264 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1265 | seq_printf(m, "Boost freq: %d MHz\n", |
1266 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1267 | seq_printf(m, "Max freq: %d MHz\n", |
1268 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1269 | seq_printf(m, | |
1270 | "efficient (RPe) frequency: %d MHz\n", | |
1271 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1272 | } else { |
267f0c90 | 1273 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1274 | } |
f97108d1 | 1275 | |
1170f28c MK |
1276 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1277 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1278 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1279 | ||
c8c8fb33 PZ |
1280 | out: |
1281 | intel_runtime_pm_put(dev_priv); | |
1282 | return ret; | |
f97108d1 JB |
1283 | } |
1284 | ||
f654449a CW |
1285 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1286 | { | |
36cdd013 | 1287 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1288 | struct intel_engine_cs *engine; |
666796da TU |
1289 | u64 acthd[I915_NUM_ENGINES]; |
1290 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1291 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1292 | enum intel_engine_id id; |
1293 | int j; | |
f654449a CW |
1294 | |
1295 | if (!i915.enable_hangcheck) { | |
1296 | seq_printf(m, "Hangcheck disabled\n"); | |
1297 | return 0; | |
1298 | } | |
1299 | ||
ebbc7546 MK |
1300 | intel_runtime_pm_get(dev_priv); |
1301 | ||
c3232b18 | 1302 | for_each_engine_id(engine, dev_priv, id) { |
7e37f889 | 1303 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1304 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1305 | } |
1306 | ||
c033666a | 1307 | i915_get_extra_instdone(dev_priv, instdone); |
61642ff0 | 1308 | |
ebbc7546 MK |
1309 | intel_runtime_pm_put(dev_priv); |
1310 | ||
f654449a CW |
1311 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1312 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1313 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1314 | jiffies)); | |
1315 | } else | |
1316 | seq_printf(m, "Hangcheck inactive\n"); | |
1317 | ||
c3232b18 | 1318 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1319 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1320 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1321 | engine->hangcheck.seqno, | |
1322 | seqno[id], | |
1323 | engine->last_submitted_seqno); | |
83348ba8 CW |
1324 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1325 | yesno(intel_engine_has_waiter(engine)), | |
1326 | yesno(test_bit(engine->id, | |
1327 | &dev_priv->gpu_error.missed_irq_rings))); | |
f654449a | 1328 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1329 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1330 | (long long)acthd[id]); |
e2f80391 TU |
1331 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1332 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1333 | |
e2f80391 | 1334 | if (engine->id == RCS) { |
61642ff0 MK |
1335 | seq_puts(m, "\tinstdone read ="); |
1336 | ||
1337 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1338 | seq_printf(m, " 0x%08x", instdone[j]); | |
1339 | ||
1340 | seq_puts(m, "\n\tinstdone accu ="); | |
1341 | ||
1342 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1343 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1344 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1345 | |
1346 | seq_puts(m, "\n"); | |
1347 | } | |
f654449a CW |
1348 | } |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
4d85529d | 1353 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1354 | { |
36cdd013 DW |
1355 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1356 | struct drm_device *dev = &dev_priv->drm; | |
616fdb5a BW |
1357 | u32 rgvmodectl, rstdbyctl; |
1358 | u16 crstandvid; | |
1359 | int ret; | |
1360 | ||
1361 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1362 | if (ret) | |
1363 | return ret; | |
c8c8fb33 | 1364 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1365 | |
1366 | rgvmodectl = I915_READ(MEMMODECTL); | |
1367 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1368 | crstandvid = I915_READ16(CRSTANDVID); | |
1369 | ||
c8c8fb33 | 1370 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1371 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1372 | |
742f491d | 1373 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1374 | seq_printf(m, "Boost freq: %d\n", |
1375 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1376 | MEMMODE_BOOST_FREQ_SHIFT); | |
1377 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1378 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1379 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1380 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1381 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1382 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1383 | seq_printf(m, "Starting frequency: P%d\n", |
1384 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1385 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1386 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1387 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1388 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1389 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1390 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1391 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1392 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1393 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1394 | case RSX_STATUS_ON: | |
267f0c90 | 1395 | seq_puts(m, "on\n"); |
88271da3 JB |
1396 | break; |
1397 | case RSX_STATUS_RC1: | |
267f0c90 | 1398 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1399 | break; |
1400 | case RSX_STATUS_RC1E: | |
267f0c90 | 1401 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1402 | break; |
1403 | case RSX_STATUS_RS1: | |
267f0c90 | 1404 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1405 | break; |
1406 | case RSX_STATUS_RS2: | |
267f0c90 | 1407 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1408 | break; |
1409 | case RSX_STATUS_RS3: | |
267f0c90 | 1410 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1411 | break; |
1412 | default: | |
267f0c90 | 1413 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1414 | break; |
1415 | } | |
f97108d1 JB |
1416 | |
1417 | return 0; | |
1418 | } | |
1419 | ||
f65367b5 | 1420 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1421 | { |
36cdd013 | 1422 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1423 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1424 | |
1425 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1426 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1427 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1428 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1429 | fw_domain->wake_count); |
1430 | } | |
1431 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1432 | |
b2cff0db CW |
1433 | return 0; |
1434 | } | |
1435 | ||
1436 | static int vlv_drpc_info(struct seq_file *m) | |
1437 | { | |
36cdd013 | 1438 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1439 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1440 | |
d46c0517 ID |
1441 | intel_runtime_pm_get(dev_priv); |
1442 | ||
6b312cd3 | 1443 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1444 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1445 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1446 | ||
d46c0517 ID |
1447 | intel_runtime_pm_put(dev_priv); |
1448 | ||
669ab5aa D |
1449 | seq_printf(m, "Video Turbo Mode: %s\n", |
1450 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1451 | seq_printf(m, "Turbo enabled: %s\n", | |
1452 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1453 | seq_printf(m, "HW control enabled: %s\n", | |
1454 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1455 | seq_printf(m, "SW control enabled: %s\n", | |
1456 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1457 | GEN6_RP_MEDIA_SW_MODE)); | |
1458 | seq_printf(m, "RC6 Enabled: %s\n", | |
1459 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1460 | GEN6_RC_CTL_EI_MODE(1)))); | |
1461 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1462 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1463 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1464 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1465 | |
9cc19be5 ID |
1466 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1467 | I915_READ(VLV_GT_RENDER_RC6)); | |
1468 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1469 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1470 | ||
f65367b5 | 1471 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1472 | } |
1473 | ||
4d85529d BW |
1474 | static int gen6_drpc_info(struct seq_file *m) |
1475 | { | |
36cdd013 DW |
1476 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1477 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1478 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1479 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1480 | unsigned forcewake_count; |
aee56cff | 1481 | int count = 0, ret; |
4d85529d BW |
1482 | |
1483 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1484 | if (ret) | |
1485 | return ret; | |
c8c8fb33 | 1486 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1487 | |
907b28c5 | 1488 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1489 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1490 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1491 | |
1492 | if (forcewake_count) { | |
267f0c90 DL |
1493 | seq_puts(m, "RC information inaccurate because somebody " |
1494 | "holds a forcewake reference \n"); | |
4d85529d BW |
1495 | } else { |
1496 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1497 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1498 | udelay(10); | |
1499 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1500 | } | |
1501 | ||
75aa3f63 | 1502 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1503 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1504 | |
1505 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1506 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1507 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1508 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1509 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1510 | } | |
4d85529d | 1511 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1512 | mutex_lock(&dev_priv->rps.hw_lock); |
1513 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1514 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1515 | |
c8c8fb33 PZ |
1516 | intel_runtime_pm_put(dev_priv); |
1517 | ||
4d85529d BW |
1518 | seq_printf(m, "Video Turbo Mode: %s\n", |
1519 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1520 | seq_printf(m, "HW control enabled: %s\n", | |
1521 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1522 | seq_printf(m, "SW control enabled: %s\n", | |
1523 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1524 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1525 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1526 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1527 | seq_printf(m, "RC6 Enabled: %s\n", | |
1528 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1529 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1530 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1531 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1532 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1533 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1534 | } | |
4d85529d BW |
1535 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1536 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1537 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1538 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1539 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1540 | switch (gt_core_status & GEN6_RCn_MASK) { |
1541 | case GEN6_RC0: | |
1542 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1543 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1544 | else |
267f0c90 | 1545 | seq_puts(m, "on\n"); |
4d85529d BW |
1546 | break; |
1547 | case GEN6_RC3: | |
267f0c90 | 1548 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1549 | break; |
1550 | case GEN6_RC6: | |
267f0c90 | 1551 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1552 | break; |
1553 | case GEN6_RC7: | |
267f0c90 | 1554 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1555 | break; |
1556 | default: | |
267f0c90 | 1557 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1558 | break; |
1559 | } | |
1560 | ||
1561 | seq_printf(m, "Core Power Down: %s\n", | |
1562 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1563 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1564 | seq_printf(m, "Render Power Well: %s\n", |
1565 | (gen9_powergate_status & | |
1566 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1567 | seq_printf(m, "Media Power Well: %s\n", | |
1568 | (gen9_powergate_status & | |
1569 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1570 | } | |
cce66a28 BW |
1571 | |
1572 | /* Not exactly sure what this is */ | |
1573 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1574 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1575 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1576 | I915_READ(GEN6_GT_GFX_RC6)); | |
1577 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1578 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1579 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1580 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1581 | ||
ecd8faea BW |
1582 | seq_printf(m, "RC6 voltage: %dmV\n", |
1583 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1584 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1585 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1586 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1587 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1588 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1589 | } |
1590 | ||
1591 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1592 | { | |
36cdd013 | 1593 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1594 | |
36cdd013 | 1595 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1596 | return vlv_drpc_info(m); |
36cdd013 | 1597 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1598 | return gen6_drpc_info(m); |
1599 | else | |
1600 | return ironlake_drpc_info(m); | |
1601 | } | |
1602 | ||
9a851789 DV |
1603 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1604 | { | |
36cdd013 | 1605 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1606 | |
1607 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1608 | dev_priv->fb_tracking.busy_bits); | |
1609 | ||
1610 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1611 | dev_priv->fb_tracking.flip_bits); | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
b5e50c3f JB |
1616 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1617 | { | |
36cdd013 | 1618 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1619 | |
36cdd013 | 1620 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1621 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1622 | return 0; |
1623 | } | |
1624 | ||
36623ef8 | 1625 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1626 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1627 | |
0e631adc | 1628 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1629 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1630 | else |
1631 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1632 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1633 | |
36cdd013 | 1634 | if (INTEL_GEN(dev_priv) >= 7) |
31b9df10 PZ |
1635 | seq_printf(m, "Compressing: %s\n", |
1636 | yesno(I915_READ(FBC_STATUS2) & | |
1637 | FBC_COMPRESSION_MASK)); | |
1638 | ||
25ad93fd | 1639 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1640 | intel_runtime_pm_put(dev_priv); |
1641 | ||
b5e50c3f JB |
1642 | return 0; |
1643 | } | |
1644 | ||
da46f936 RV |
1645 | static int i915_fbc_fc_get(void *data, u64 *val) |
1646 | { | |
36cdd013 | 1647 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1648 | |
36cdd013 | 1649 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1650 | return -ENODEV; |
1651 | ||
da46f936 | 1652 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1653 | |
1654 | return 0; | |
1655 | } | |
1656 | ||
1657 | static int i915_fbc_fc_set(void *data, u64 val) | |
1658 | { | |
36cdd013 | 1659 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1660 | u32 reg; |
1661 | ||
36cdd013 | 1662 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1663 | return -ENODEV; |
1664 | ||
25ad93fd | 1665 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1666 | |
1667 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1668 | dev_priv->fbc.false_color = val; | |
1669 | ||
1670 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1671 | (reg | FBC_CTL_FALSE_COLOR) : | |
1672 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1673 | ||
25ad93fd | 1674 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1675 | return 0; |
1676 | } | |
1677 | ||
1678 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1679 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1680 | "%llu\n"); | |
1681 | ||
92d44621 PZ |
1682 | static int i915_ips_status(struct seq_file *m, void *unused) |
1683 | { | |
36cdd013 | 1684 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1685 | |
36cdd013 | 1686 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1687 | seq_puts(m, "not supported\n"); |
1688 | return 0; | |
1689 | } | |
1690 | ||
36623ef8 PZ |
1691 | intel_runtime_pm_get(dev_priv); |
1692 | ||
0eaa53f0 RV |
1693 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1694 | yesno(i915.enable_ips)); | |
1695 | ||
36cdd013 | 1696 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1697 | seq_puts(m, "Currently: unknown\n"); |
1698 | } else { | |
1699 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1700 | seq_puts(m, "Currently: enabled\n"); | |
1701 | else | |
1702 | seq_puts(m, "Currently: disabled\n"); | |
1703 | } | |
92d44621 | 1704 | |
36623ef8 PZ |
1705 | intel_runtime_pm_put(dev_priv); |
1706 | ||
92d44621 PZ |
1707 | return 0; |
1708 | } | |
1709 | ||
4a9bef37 JB |
1710 | static int i915_sr_status(struct seq_file *m, void *unused) |
1711 | { | |
36cdd013 | 1712 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1713 | bool sr_enabled = false; |
1714 | ||
36623ef8 PZ |
1715 | intel_runtime_pm_get(dev_priv); |
1716 | ||
36cdd013 | 1717 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1718 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
36cdd013 DW |
1719 | else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || |
1720 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) | |
4a9bef37 | 1721 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1722 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1723 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1724 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1725 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1726 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1727 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1728 | |
36623ef8 PZ |
1729 | intel_runtime_pm_put(dev_priv); |
1730 | ||
5ba2aaaa CW |
1731 | seq_printf(m, "self-refresh: %s\n", |
1732 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1733 | |
1734 | return 0; | |
1735 | } | |
1736 | ||
7648fa99 JB |
1737 | static int i915_emon_status(struct seq_file *m, void *unused) |
1738 | { | |
36cdd013 DW |
1739 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1740 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1741 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1742 | int ret; |
1743 | ||
36cdd013 | 1744 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1745 | return -ENODEV; |
1746 | ||
de227ef0 CW |
1747 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1748 | if (ret) | |
1749 | return ret; | |
7648fa99 JB |
1750 | |
1751 | temp = i915_mch_val(dev_priv); | |
1752 | chipset = i915_chipset_val(dev_priv); | |
1753 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1754 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1755 | |
1756 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1757 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1758 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1759 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
23b2f8bb JB |
1764 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1765 | { | |
36cdd013 | 1766 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1767 | int ret = 0; |
23b2f8bb | 1768 | int gpu_freq, ia_freq; |
f936ec34 | 1769 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1770 | |
36cdd013 | 1771 | if (!HAS_CORE_RING_FREQ(dev_priv)) { |
267f0c90 | 1772 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1773 | return 0; |
1774 | } | |
1775 | ||
5bfa0199 PZ |
1776 | intel_runtime_pm_get(dev_priv); |
1777 | ||
4fc688ce | 1778 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1779 | if (ret) |
5bfa0199 | 1780 | goto out; |
23b2f8bb | 1781 | |
36cdd013 | 1782 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1783 | /* Convert GT frequency to 50 HZ units */ |
1784 | min_gpu_freq = | |
1785 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1786 | max_gpu_freq = | |
1787 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1788 | } else { | |
1789 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1790 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1791 | } | |
1792 | ||
267f0c90 | 1793 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1794 | |
f936ec34 | 1795 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1796 | ia_freq = gpu_freq; |
1797 | sandybridge_pcode_read(dev_priv, | |
1798 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1799 | &ia_freq); | |
3ebecd07 | 1800 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1801 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1802 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1803 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1804 | ((ia_freq >> 0) & 0xff) * 100, |
1805 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1806 | } |
1807 | ||
4fc688ce | 1808 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1809 | |
5bfa0199 PZ |
1810 | out: |
1811 | intel_runtime_pm_put(dev_priv); | |
1812 | return ret; | |
23b2f8bb JB |
1813 | } |
1814 | ||
44834a67 CW |
1815 | static int i915_opregion(struct seq_file *m, void *unused) |
1816 | { | |
36cdd013 DW |
1817 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1818 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1819 | struct intel_opregion *opregion = &dev_priv->opregion; |
1820 | int ret; | |
1821 | ||
1822 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1823 | if (ret) | |
0d38f009 | 1824 | goto out; |
44834a67 | 1825 | |
2455a8e4 JN |
1826 | if (opregion->header) |
1827 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1828 | |
1829 | mutex_unlock(&dev->struct_mutex); | |
1830 | ||
0d38f009 | 1831 | out: |
44834a67 CW |
1832 | return 0; |
1833 | } | |
1834 | ||
ada8f955 JN |
1835 | static int i915_vbt(struct seq_file *m, void *unused) |
1836 | { | |
36cdd013 | 1837 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1838 | |
1839 | if (opregion->vbt) | |
1840 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
37811fcc CW |
1845 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1846 | { | |
36cdd013 DW |
1847 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1848 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1849 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1850 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1851 | int ret; |
1852 | ||
1853 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1854 | if (ret) | |
1855 | return ret; | |
37811fcc | 1856 | |
0695726e | 1857 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1858 | if (dev_priv->fbdev) { |
1859 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1860 | |
1861 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1862 | fbdev_fb->base.width, | |
1863 | fbdev_fb->base.height, | |
1864 | fbdev_fb->base.depth, | |
1865 | fbdev_fb->base.bits_per_pixel, | |
1866 | fbdev_fb->base.modifier[0], | |
1867 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1868 | describe_obj(m, fbdev_fb->obj); | |
1869 | seq_putc(m, '\n'); | |
1870 | } | |
4520f53a | 1871 | #endif |
37811fcc | 1872 | |
4b096ac1 | 1873 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1874 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1875 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1876 | if (fb == fbdev_fb) | |
37811fcc CW |
1877 | continue; |
1878 | ||
c1ca506d | 1879 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1880 | fb->base.width, |
1881 | fb->base.height, | |
1882 | fb->base.depth, | |
623f9783 | 1883 | fb->base.bits_per_pixel, |
c1ca506d | 1884 | fb->base.modifier[0], |
747a598f | 1885 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1886 | describe_obj(m, fb->obj); |
267f0c90 | 1887 | seq_putc(m, '\n'); |
37811fcc | 1888 | } |
4b096ac1 | 1889 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1890 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1891 | |
1892 | return 0; | |
1893 | } | |
1894 | ||
7e37f889 | 1895 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1896 | { |
1897 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1898 | ring->space, ring->head, ring->tail, |
1899 | ring->last_retired_head); | |
c9fe99bd OM |
1900 | } |
1901 | ||
e76d3630 BW |
1902 | static int i915_context_status(struct seq_file *m, void *unused) |
1903 | { | |
36cdd013 DW |
1904 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1905 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1906 | struct intel_engine_cs *engine; |
e2efd130 | 1907 | struct i915_gem_context *ctx; |
c3232b18 | 1908 | int ret; |
e76d3630 | 1909 | |
f3d28878 | 1910 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1911 | if (ret) |
1912 | return ret; | |
1913 | ||
a33afea5 | 1914 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1915 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1916 | if (ctx->pid) { |
d28b99ab CW |
1917 | struct task_struct *task; |
1918 | ||
c84455b4 | 1919 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1920 | if (task) { |
1921 | seq_printf(m, "(%s [%d]) ", | |
1922 | task->comm, task->pid); | |
1923 | put_task_struct(task); | |
1924 | } | |
c84455b4 CW |
1925 | } else if (IS_ERR(ctx->file_priv)) { |
1926 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1927 | } else { |
1928 | seq_puts(m, "(kernel) "); | |
1929 | } | |
1930 | ||
bca44d80 CW |
1931 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1932 | seq_putc(m, '\n'); | |
c9fe99bd | 1933 | |
bca44d80 CW |
1934 | for_each_engine(engine, dev_priv) { |
1935 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1936 | ||
1937 | seq_printf(m, "%s: ", engine->name); | |
1938 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1939 | if (ce->state) | |
bf3783e5 | 1940 | describe_obj(m, ce->state->obj); |
dca33ecc | 1941 | if (ce->ring) |
7e37f889 | 1942 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1943 | seq_putc(m, '\n'); |
c9fe99bd | 1944 | } |
a33afea5 | 1945 | |
a33afea5 | 1946 | seq_putc(m, '\n'); |
a168c293 BW |
1947 | } |
1948 | ||
f3d28878 | 1949 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1950 | |
1951 | return 0; | |
1952 | } | |
1953 | ||
064ca1d2 | 1954 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1955 | struct i915_gem_context *ctx, |
0bc40be8 | 1956 | struct intel_engine_cs *engine) |
064ca1d2 | 1957 | { |
bf3783e5 | 1958 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1959 | struct page *page; |
064ca1d2 | 1960 | int j; |
064ca1d2 | 1961 | |
7069b144 CW |
1962 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1963 | ||
bf3783e5 CW |
1964 | if (!vma) { |
1965 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
1966 | return; |
1967 | } | |
1968 | ||
bf3783e5 CW |
1969 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
1970 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 1971 | i915_ggtt_offset(vma)); |
064ca1d2 | 1972 | |
bf3783e5 CW |
1973 | if (i915_gem_object_get_pages(vma->obj)) { |
1974 | seq_puts(m, "\tFailed to get pages for context object\n\n"); | |
064ca1d2 TD |
1975 | return; |
1976 | } | |
1977 | ||
bf3783e5 CW |
1978 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
1979 | if (page) { | |
1980 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
1981 | |
1982 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
1983 | seq_printf(m, |
1984 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1985 | j * 4, | |
064ca1d2 TD |
1986 | reg_state[j], reg_state[j + 1], |
1987 | reg_state[j + 2], reg_state[j + 3]); | |
1988 | } | |
1989 | kunmap_atomic(reg_state); | |
1990 | } | |
1991 | ||
1992 | seq_putc(m, '\n'); | |
1993 | } | |
1994 | ||
c0ab1ae9 BW |
1995 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
1996 | { | |
36cdd013 DW |
1997 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1998 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1999 | struct intel_engine_cs *engine; |
e2efd130 | 2000 | struct i915_gem_context *ctx; |
b4ac5afc | 2001 | int ret; |
c0ab1ae9 BW |
2002 | |
2003 | if (!i915.enable_execlists) { | |
2004 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2009 | if (ret) | |
2010 | return ret; | |
2011 | ||
e28e404c | 2012 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2013 | for_each_engine(engine, dev_priv) |
2014 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2015 | |
2016 | mutex_unlock(&dev->struct_mutex); | |
2017 | ||
2018 | return 0; | |
2019 | } | |
2020 | ||
4ba70e44 OM |
2021 | static int i915_execlists(struct seq_file *m, void *data) |
2022 | { | |
36cdd013 DW |
2023 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2024 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2025 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2026 | u32 status_pointer; |
2027 | u8 read_pointer; | |
2028 | u8 write_pointer; | |
2029 | u32 status; | |
2030 | u32 ctx_id; | |
2031 | struct list_head *cursor; | |
b4ac5afc | 2032 | int i, ret; |
4ba70e44 OM |
2033 | |
2034 | if (!i915.enable_execlists) { | |
2035 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2040 | if (ret) | |
2041 | return ret; | |
2042 | ||
fc0412ec MT |
2043 | intel_runtime_pm_get(dev_priv); |
2044 | ||
b4ac5afc | 2045 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2046 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2047 | int count = 0; |
4ba70e44 | 2048 | |
e2f80391 | 2049 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2050 | |
e2f80391 TU |
2051 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2052 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2053 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2054 | status, ctx_id); | |
2055 | ||
e2f80391 | 2056 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2057 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2058 | ||
e2f80391 | 2059 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2060 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2061 | if (read_pointer > write_pointer) |
5590a5f0 | 2062 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2063 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2064 | read_pointer, write_pointer); | |
2065 | ||
5590a5f0 | 2066 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2067 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2068 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2069 | |
2070 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2071 | i, status, ctx_id); | |
2072 | } | |
2073 | ||
27af5eea | 2074 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2075 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2076 | count++; |
e2f80391 TU |
2077 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2078 | struct drm_i915_gem_request, | |
2079 | execlist_link); | |
27af5eea | 2080 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2081 | |
2082 | seq_printf(m, "\t%d requests in queue\n", count); | |
2083 | if (head_req) { | |
7069b144 CW |
2084 | seq_printf(m, "\tHead request context: %u\n", |
2085 | head_req->ctx->hw_id); | |
4ba70e44 | 2086 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2087 | head_req->tail); |
4ba70e44 OM |
2088 | } |
2089 | ||
2090 | seq_putc(m, '\n'); | |
2091 | } | |
2092 | ||
fc0412ec | 2093 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2094 | mutex_unlock(&dev->struct_mutex); |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
ea16a3cd DV |
2099 | static const char *swizzle_string(unsigned swizzle) |
2100 | { | |
aee56cff | 2101 | switch (swizzle) { |
ea16a3cd DV |
2102 | case I915_BIT_6_SWIZZLE_NONE: |
2103 | return "none"; | |
2104 | case I915_BIT_6_SWIZZLE_9: | |
2105 | return "bit9"; | |
2106 | case I915_BIT_6_SWIZZLE_9_10: | |
2107 | return "bit9/bit10"; | |
2108 | case I915_BIT_6_SWIZZLE_9_11: | |
2109 | return "bit9/bit11"; | |
2110 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2111 | return "bit9/bit10/bit11"; | |
2112 | case I915_BIT_6_SWIZZLE_9_17: | |
2113 | return "bit9/bit17"; | |
2114 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2115 | return "bit9/bit10/bit17"; | |
2116 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2117 | return "unknown"; |
ea16a3cd DV |
2118 | } |
2119 | ||
2120 | return "bug"; | |
2121 | } | |
2122 | ||
2123 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2124 | { | |
36cdd013 DW |
2125 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2126 | struct drm_device *dev = &dev_priv->drm; | |
22bcfc6a DV |
2127 | int ret; |
2128 | ||
2129 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2130 | if (ret) | |
2131 | return ret; | |
c8c8fb33 | 2132 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2133 | |
ea16a3cd DV |
2134 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2135 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2136 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2137 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2138 | ||
36cdd013 | 2139 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2140 | seq_printf(m, "DDC = 0x%08x\n", |
2141 | I915_READ(DCC)); | |
656bfa3a DV |
2142 | seq_printf(m, "DDC2 = 0x%08x\n", |
2143 | I915_READ(DCC2)); | |
ea16a3cd DV |
2144 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2145 | I915_READ16(C0DRB3)); | |
2146 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2147 | I915_READ16(C1DRB3)); | |
36cdd013 | 2148 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2149 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2150 | I915_READ(MAD_DIMM_C0)); | |
2151 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2152 | I915_READ(MAD_DIMM_C1)); | |
2153 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2154 | I915_READ(MAD_DIMM_C2)); | |
2155 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2156 | I915_READ(TILECTL)); | |
36cdd013 | 2157 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2158 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2159 | I915_READ(GAMTARBMODE)); | |
2160 | else | |
2161 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2162 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2163 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2164 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2165 | } |
656bfa3a DV |
2166 | |
2167 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2168 | seq_puts(m, "L-shaped memory detected\n"); | |
2169 | ||
c8c8fb33 | 2170 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2171 | mutex_unlock(&dev->struct_mutex); |
2172 | ||
2173 | return 0; | |
2174 | } | |
2175 | ||
1c60fef5 BW |
2176 | static int per_file_ctx(int id, void *ptr, void *data) |
2177 | { | |
e2efd130 | 2178 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2179 | struct seq_file *m = data; |
ae6c4806 DV |
2180 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2181 | ||
2182 | if (!ppgtt) { | |
2183 | seq_printf(m, " no ppgtt for context %d\n", | |
2184 | ctx->user_handle); | |
2185 | return 0; | |
2186 | } | |
1c60fef5 | 2187 | |
f83d6518 OM |
2188 | if (i915_gem_context_is_default(ctx)) |
2189 | seq_puts(m, " default context:\n"); | |
2190 | else | |
821d66dd | 2191 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2192 | ppgtt->debug_dump(ppgtt, m); |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | ||
36cdd013 DW |
2197 | static void gen8_ppgtt_info(struct seq_file *m, |
2198 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2199 | { |
e2f80391 | 2200 | struct intel_engine_cs *engine; |
77df6772 | 2201 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2202 | int i; |
3cf17fc5 | 2203 | |
77df6772 BW |
2204 | if (!ppgtt) |
2205 | return; | |
2206 | ||
b4ac5afc | 2207 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2208 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2209 | for (i = 0; i < 4; i++) { |
e2f80391 | 2210 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2211 | pdp <<= 32; |
e2f80391 | 2212 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2213 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2214 | } |
2215 | } | |
2216 | } | |
2217 | ||
36cdd013 DW |
2218 | static void gen6_ppgtt_info(struct seq_file *m, |
2219 | struct drm_i915_private *dev_priv) | |
77df6772 | 2220 | { |
e2f80391 | 2221 | struct intel_engine_cs *engine; |
3cf17fc5 | 2222 | |
7e22dbbb | 2223 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2224 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2225 | ||
b4ac5afc | 2226 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2227 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2228 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2229 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2230 | I915_READ(RING_MODE_GEN7(engine))); | |
2231 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2232 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2233 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2234 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2235 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2236 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2237 | } |
2238 | if (dev_priv->mm.aliasing_ppgtt) { | |
2239 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2240 | ||
267f0c90 | 2241 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2242 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2243 | |
87d60b63 | 2244 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2245 | } |
1c60fef5 | 2246 | |
3cf17fc5 | 2247 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2248 | } |
2249 | ||
2250 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2251 | { | |
36cdd013 DW |
2252 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2253 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2254 | struct drm_file *file; |
637ee29e | 2255 | int ret; |
77df6772 | 2256 | |
637ee29e CW |
2257 | mutex_lock(&dev->filelist_mutex); |
2258 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2259 | if (ret) |
637ee29e CW |
2260 | goto out_unlock; |
2261 | ||
c8c8fb33 | 2262 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2263 | |
36cdd013 DW |
2264 | if (INTEL_GEN(dev_priv) >= 8) |
2265 | gen8_ppgtt_info(m, dev_priv); | |
2266 | else if (INTEL_GEN(dev_priv) >= 6) | |
2267 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2268 | |
ea91e401 MT |
2269 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2270 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2271 | struct task_struct *task; |
ea91e401 | 2272 | |
7cb5dff8 | 2273 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2274 | if (!task) { |
2275 | ret = -ESRCH; | |
637ee29e | 2276 | goto out_rpm; |
06812760 | 2277 | } |
7cb5dff8 GT |
2278 | seq_printf(m, "\nproc: %s\n", task->comm); |
2279 | put_task_struct(task); | |
ea91e401 MT |
2280 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2281 | (void *)(unsigned long)m); | |
2282 | } | |
2283 | ||
637ee29e | 2284 | out_rpm: |
c8c8fb33 | 2285 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2286 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2287 | out_unlock: |
2288 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2289 | return ret; |
3cf17fc5 DV |
2290 | } |
2291 | ||
f5a4c67d CW |
2292 | static int count_irq_waiters(struct drm_i915_private *i915) |
2293 | { | |
e2f80391 | 2294 | struct intel_engine_cs *engine; |
f5a4c67d | 2295 | int count = 0; |
f5a4c67d | 2296 | |
b4ac5afc | 2297 | for_each_engine(engine, i915) |
688e6c72 | 2298 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2299 | |
2300 | return count; | |
2301 | } | |
2302 | ||
7466c291 CW |
2303 | static const char *rps_power_to_str(unsigned int power) |
2304 | { | |
2305 | static const char * const strings[] = { | |
2306 | [LOW_POWER] = "low power", | |
2307 | [BETWEEN] = "mixed", | |
2308 | [HIGH_POWER] = "high power", | |
2309 | }; | |
2310 | ||
2311 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2312 | return "unknown"; | |
2313 | ||
2314 | return strings[power]; | |
2315 | } | |
2316 | ||
1854d5ca CW |
2317 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2318 | { | |
36cdd013 DW |
2319 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2320 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2321 | struct drm_file *file; |
1854d5ca | 2322 | |
f5a4c67d | 2323 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
67d97da3 CW |
2324 | seq_printf(m, "GPU busy? %s [%x]\n", |
2325 | yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); | |
f5a4c67d | 2326 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2327 | seq_printf(m, "Frequency requested %d\n", |
2328 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2329 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2330 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2331 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2332 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2333 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2334 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2335 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2336 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2337 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2338 | |
2339 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2340 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2341 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2342 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2343 | struct task_struct *task; | |
2344 | ||
2345 | rcu_read_lock(); | |
2346 | task = pid_task(file->pid, PIDTYPE_PID); | |
2347 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2348 | task ? task->comm : "<unknown>", | |
2349 | task ? task->pid : -1, | |
2e1b8730 CW |
2350 | file_priv->rps.boosts, |
2351 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2352 | rcu_read_unlock(); |
2353 | } | |
197be2ae | 2354 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2355 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2356 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2357 | |
7466c291 CW |
2358 | if (INTEL_GEN(dev_priv) >= 6 && |
2359 | dev_priv->rps.enabled && | |
2360 | dev_priv->gt.active_engines) { | |
2361 | u32 rpup, rpupei; | |
2362 | u32 rpdown, rpdownei; | |
2363 | ||
2364 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2365 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2366 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2367 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2368 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2369 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2370 | ||
2371 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2372 | rps_power_to_str(dev_priv->rps.power)); | |
2373 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2374 | 100 * rpup / rpupei, | |
2375 | dev_priv->rps.up_threshold); | |
2376 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2377 | 100 * rpdown / rpdownei, | |
2378 | dev_priv->rps.down_threshold); | |
2379 | } else { | |
2380 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2381 | } | |
2382 | ||
8d3afd7d | 2383 | return 0; |
1854d5ca CW |
2384 | } |
2385 | ||
63573eb7 BW |
2386 | static int i915_llc(struct seq_file *m, void *data) |
2387 | { | |
36cdd013 | 2388 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2389 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2390 | |
36cdd013 | 2391 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2392 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2393 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2394 | |
2395 | return 0; | |
2396 | } | |
2397 | ||
fdf5d357 AD |
2398 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2399 | { | |
36cdd013 | 2400 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2401 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2402 | u32 tmp, i; | |
2403 | ||
2d1fe073 | 2404 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2405 | return 0; |
2406 | ||
2407 | seq_printf(m, "GuC firmware status:\n"); | |
2408 | seq_printf(m, "\tpath: %s\n", | |
2409 | guc_fw->guc_fw_path); | |
2410 | seq_printf(m, "\tfetch: %s\n", | |
2411 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2412 | seq_printf(m, "\tload: %s\n", | |
2413 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2414 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2415 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2416 | seq_printf(m, "\tversion found: %d.%d\n", | |
2417 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2418 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2419 | guc_fw->header_offset, guc_fw->header_size); | |
2420 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2421 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2422 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2423 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2424 | |
2425 | tmp = I915_READ(GUC_STATUS); | |
2426 | ||
2427 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2428 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2429 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2430 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2431 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2432 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2433 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2434 | seq_puts(m, "\nScratch registers:\n"); | |
2435 | for (i = 0; i < 16; i++) | |
2436 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2437 | ||
2438 | return 0; | |
2439 | } | |
2440 | ||
8b417c26 DG |
2441 | static void i915_guc_client_info(struct seq_file *m, |
2442 | struct drm_i915_private *dev_priv, | |
2443 | struct i915_guc_client *client) | |
2444 | { | |
e2f80391 | 2445 | struct intel_engine_cs *engine; |
c18468c4 | 2446 | enum intel_engine_id id; |
8b417c26 | 2447 | uint64_t tot = 0; |
8b417c26 DG |
2448 | |
2449 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2450 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2451 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2452 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2453 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2454 | client->wq_size, client->wq_offset, client->wq_tail); | |
2455 | ||
551aaecd | 2456 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2457 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2458 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2459 | ||
c18468c4 DG |
2460 | for_each_engine_id(engine, dev_priv, id) { |
2461 | u64 submissions = client->submissions[id]; | |
2462 | tot += submissions; | |
8b417c26 | 2463 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2464 | submissions, engine->name); |
8b417c26 DG |
2465 | } |
2466 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2467 | } | |
2468 | ||
2469 | static int i915_guc_info(struct seq_file *m, void *data) | |
2470 | { | |
36cdd013 DW |
2471 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2472 | struct drm_device *dev = &dev_priv->drm; | |
8b417c26 | 2473 | struct intel_guc guc; |
0a0b457f | 2474 | struct i915_guc_client client = {}; |
e2f80391 | 2475 | struct intel_engine_cs *engine; |
c18468c4 | 2476 | enum intel_engine_id id; |
8b417c26 DG |
2477 | u64 total = 0; |
2478 | ||
2d1fe073 | 2479 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2480 | return 0; |
2481 | ||
5a843307 AD |
2482 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2483 | return 0; | |
2484 | ||
8b417c26 | 2485 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2486 | guc = dev_priv->guc; |
5a843307 | 2487 | if (guc.execbuf_client) |
8b417c26 | 2488 | client = *guc.execbuf_client; |
5a843307 AD |
2489 | |
2490 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2491 | |
9636f6db DG |
2492 | seq_printf(m, "Doorbell map:\n"); |
2493 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2494 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2495 | ||
8b417c26 DG |
2496 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2497 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2498 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2499 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2500 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2501 | ||
2502 | seq_printf(m, "\nGuC submissions:\n"); | |
c18468c4 DG |
2503 | for_each_engine_id(engine, dev_priv, id) { |
2504 | u64 submissions = guc.submissions[id]; | |
2505 | total += submissions; | |
397097b0 | 2506 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2507 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2508 | } |
2509 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2510 | ||
2511 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2512 | i915_guc_client_info(m, dev_priv, &client); | |
2513 | ||
2514 | /* Add more as required ... */ | |
2515 | ||
2516 | return 0; | |
2517 | } | |
2518 | ||
4c7e77fc AD |
2519 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2520 | { | |
36cdd013 | 2521 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2522 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2523 | int i = 0, pg; |
2524 | ||
8b797af1 | 2525 | if (!dev_priv->guc.log_vma) |
4c7e77fc AD |
2526 | return 0; |
2527 | ||
8b797af1 CW |
2528 | obj = dev_priv->guc.log_vma->obj; |
2529 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { | |
2530 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2531 | |
2532 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2533 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2534 | *(log + i), *(log + i + 1), | |
2535 | *(log + i + 2), *(log + i + 3)); | |
2536 | ||
2537 | kunmap_atomic(log); | |
2538 | } | |
2539 | ||
2540 | seq_putc(m, '\n'); | |
2541 | ||
2542 | return 0; | |
2543 | } | |
2544 | ||
e91fd8c6 RV |
2545 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2546 | { | |
36cdd013 | 2547 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2548 | u32 psrperf = 0; |
a6cbdb8e RV |
2549 | u32 stat[3]; |
2550 | enum pipe pipe; | |
a031d709 | 2551 | bool enabled = false; |
e91fd8c6 | 2552 | |
36cdd013 | 2553 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2554 | seq_puts(m, "PSR not supported\n"); |
2555 | return 0; | |
2556 | } | |
2557 | ||
c8c8fb33 PZ |
2558 | intel_runtime_pm_get(dev_priv); |
2559 | ||
fa128fa6 | 2560 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2561 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2562 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2563 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2564 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2565 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2566 | dev_priv->psr.busy_frontbuffer_bits); | |
2567 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2568 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2569 | |
36cdd013 | 2570 | if (HAS_DDI(dev_priv)) |
443a389f | 2571 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2572 | else { |
2573 | for_each_pipe(dev_priv, pipe) { | |
2574 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2575 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2576 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2577 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2578 | enabled = true; | |
a6cbdb8e RV |
2579 | } |
2580 | } | |
60e5ffe3 RV |
2581 | |
2582 | seq_printf(m, "Main link in standby mode: %s\n", | |
2583 | yesno(dev_priv->psr.link_standby)); | |
2584 | ||
a6cbdb8e RV |
2585 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2586 | ||
36cdd013 | 2587 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2588 | for_each_pipe(dev_priv, pipe) { |
2589 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2590 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2591 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2592 | } | |
2593 | seq_puts(m, "\n"); | |
e91fd8c6 | 2594 | |
05eec3c2 RV |
2595 | /* |
2596 | * VLV/CHV PSR has no kind of performance counter | |
2597 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2598 | */ | |
36cdd013 | 2599 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2600 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2601 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2602 | |
2603 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2604 | } | |
fa128fa6 | 2605 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2606 | |
c8c8fb33 | 2607 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2608 | return 0; |
2609 | } | |
2610 | ||
d2e216d0 RV |
2611 | static int i915_sink_crc(struct seq_file *m, void *data) |
2612 | { | |
36cdd013 DW |
2613 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2614 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2615 | struct intel_connector *connector; |
2616 | struct intel_dp *intel_dp = NULL; | |
2617 | int ret; | |
2618 | u8 crc[6]; | |
2619 | ||
2620 | drm_modeset_lock_all(dev); | |
aca5e361 | 2621 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2622 | struct drm_crtc *crtc; |
d2e216d0 | 2623 | |
26c17cf6 | 2624 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2625 | continue; |
2626 | ||
26c17cf6 ML |
2627 | crtc = connector->base.state->crtc; |
2628 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2629 | continue; |
2630 | ||
26c17cf6 | 2631 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2632 | continue; |
2633 | ||
26c17cf6 | 2634 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2635 | |
2636 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2637 | if (ret) | |
2638 | goto out; | |
2639 | ||
2640 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2641 | crc[0], crc[1], crc[2], | |
2642 | crc[3], crc[4], crc[5]); | |
2643 | goto out; | |
2644 | } | |
2645 | ret = -ENODEV; | |
2646 | out: | |
2647 | drm_modeset_unlock_all(dev); | |
2648 | return ret; | |
2649 | } | |
2650 | ||
ec013e7f JB |
2651 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2652 | { | |
36cdd013 | 2653 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2654 | u64 power; |
2655 | u32 units; | |
2656 | ||
36cdd013 | 2657 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2658 | return -ENODEV; |
2659 | ||
36623ef8 PZ |
2660 | intel_runtime_pm_get(dev_priv); |
2661 | ||
ec013e7f JB |
2662 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2663 | power = (power & 0x1f00) >> 8; | |
2664 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2665 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2666 | power *= units; | |
2667 | ||
36623ef8 PZ |
2668 | intel_runtime_pm_put(dev_priv); |
2669 | ||
ec013e7f | 2670 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2671 | |
2672 | return 0; | |
2673 | } | |
2674 | ||
6455c870 | 2675 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2676 | { |
36cdd013 | 2677 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2678 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2679 | |
a156e64d CW |
2680 | if (!HAS_RUNTIME_PM(dev_priv)) |
2681 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2682 | |
67d97da3 | 2683 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2684 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2685 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2686 | #ifdef CONFIG_PM |
a6aaec8b | 2687 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2688 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2689 | #else |
2690 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2691 | #endif | |
a156e64d | 2692 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2693 | pci_power_name(pdev->current_state), |
2694 | pdev->current_state); | |
371db66a | 2695 | |
ec013e7f JB |
2696 | return 0; |
2697 | } | |
2698 | ||
1da51581 ID |
2699 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2700 | { | |
36cdd013 | 2701 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2702 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2703 | int i; | |
2704 | ||
2705 | mutex_lock(&power_domains->lock); | |
2706 | ||
2707 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2708 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2709 | struct i915_power_well *power_well; | |
2710 | enum intel_display_power_domain power_domain; | |
2711 | ||
2712 | power_well = &power_domains->power_wells[i]; | |
2713 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2714 | power_well->count); | |
2715 | ||
2716 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2717 | power_domain++) { | |
2718 | if (!(BIT(power_domain) & power_well->domains)) | |
2719 | continue; | |
2720 | ||
2721 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2722 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2723 | power_domains->domain_use_count[power_domain]); |
2724 | } | |
2725 | } | |
2726 | ||
2727 | mutex_unlock(&power_domains->lock); | |
2728 | ||
2729 | return 0; | |
2730 | } | |
2731 | ||
b7cec66d DL |
2732 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2733 | { | |
36cdd013 | 2734 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2735 | struct intel_csr *csr; |
2736 | ||
36cdd013 | 2737 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2738 | seq_puts(m, "not supported\n"); |
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | csr = &dev_priv->csr; | |
2743 | ||
6fb403de MK |
2744 | intel_runtime_pm_get(dev_priv); |
2745 | ||
b7cec66d DL |
2746 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2747 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2748 | ||
2749 | if (!csr->dmc_payload) | |
6fb403de | 2750 | goto out; |
b7cec66d DL |
2751 | |
2752 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2753 | CSR_VERSION_MINOR(csr->version)); | |
2754 | ||
36cdd013 | 2755 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2756 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2757 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2758 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2759 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2760 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2761 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2762 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2763 | } |
2764 | ||
6fb403de MK |
2765 | out: |
2766 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2767 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2768 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2769 | ||
8337206d DL |
2770 | intel_runtime_pm_put(dev_priv); |
2771 | ||
b7cec66d DL |
2772 | return 0; |
2773 | } | |
2774 | ||
53f5e3ca JB |
2775 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2776 | struct drm_display_mode *mode) | |
2777 | { | |
2778 | int i; | |
2779 | ||
2780 | for (i = 0; i < tabs; i++) | |
2781 | seq_putc(m, '\t'); | |
2782 | ||
2783 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2784 | mode->base.id, mode->name, | |
2785 | mode->vrefresh, mode->clock, | |
2786 | mode->hdisplay, mode->hsync_start, | |
2787 | mode->hsync_end, mode->htotal, | |
2788 | mode->vdisplay, mode->vsync_start, | |
2789 | mode->vsync_end, mode->vtotal, | |
2790 | mode->type, mode->flags); | |
2791 | } | |
2792 | ||
2793 | static void intel_encoder_info(struct seq_file *m, | |
2794 | struct intel_crtc *intel_crtc, | |
2795 | struct intel_encoder *intel_encoder) | |
2796 | { | |
36cdd013 DW |
2797 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2798 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2799 | struct drm_crtc *crtc = &intel_crtc->base; |
2800 | struct intel_connector *intel_connector; | |
2801 | struct drm_encoder *encoder; | |
2802 | ||
2803 | encoder = &intel_encoder->base; | |
2804 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2805 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2806 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2807 | struct drm_connector *connector = &intel_connector->base; | |
2808 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2809 | connector->base.id, | |
c23cc417 | 2810 | connector->name, |
53f5e3ca JB |
2811 | drm_get_connector_status_name(connector->status)); |
2812 | if (connector->status == connector_status_connected) { | |
2813 | struct drm_display_mode *mode = &crtc->mode; | |
2814 | seq_printf(m, ", mode:\n"); | |
2815 | intel_seq_print_mode(m, 2, mode); | |
2816 | } else { | |
2817 | seq_putc(m, '\n'); | |
2818 | } | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2823 | { | |
36cdd013 DW |
2824 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2825 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2826 | struct drm_crtc *crtc = &intel_crtc->base; |
2827 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2828 | struct drm_plane_state *plane_state = crtc->primary->state; |
2829 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2830 | |
23a48d53 | 2831 | if (fb) |
5aa8a937 | 2832 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2833 | fb->base.id, plane_state->src_x >> 16, |
2834 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2835 | else |
2836 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2837 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2838 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2839 | } | |
2840 | ||
2841 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2842 | { | |
2843 | struct drm_display_mode *mode = panel->fixed_mode; | |
2844 | ||
2845 | seq_printf(m, "\tfixed mode:\n"); | |
2846 | intel_seq_print_mode(m, 2, mode); | |
2847 | } | |
2848 | ||
2849 | static void intel_dp_info(struct seq_file *m, | |
2850 | struct intel_connector *intel_connector) | |
2851 | { | |
2852 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2853 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2854 | ||
2855 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2856 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2857 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca JB |
2858 | intel_panel_info(m, &intel_connector->panel); |
2859 | } | |
2860 | ||
2861 | static void intel_hdmi_info(struct seq_file *m, | |
2862 | struct intel_connector *intel_connector) | |
2863 | { | |
2864 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2865 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2866 | ||
742f491d | 2867 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2868 | } |
2869 | ||
2870 | static void intel_lvds_info(struct seq_file *m, | |
2871 | struct intel_connector *intel_connector) | |
2872 | { | |
2873 | intel_panel_info(m, &intel_connector->panel); | |
2874 | } | |
2875 | ||
2876 | static void intel_connector_info(struct seq_file *m, | |
2877 | struct drm_connector *connector) | |
2878 | { | |
2879 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2880 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2881 | struct drm_display_mode *mode; |
53f5e3ca JB |
2882 | |
2883 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2884 | connector->base.id, connector->name, |
53f5e3ca JB |
2885 | drm_get_connector_status_name(connector->status)); |
2886 | if (connector->status == connector_status_connected) { | |
2887 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2888 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2889 | connector->display_info.width_mm, | |
2890 | connector->display_info.height_mm); | |
2891 | seq_printf(m, "\tsubpixel order: %s\n", | |
2892 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2893 | seq_printf(m, "\tCEA rev: %d\n", | |
2894 | connector->display_info.cea_rev); | |
2895 | } | |
ee648a74 ML |
2896 | |
2897 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2898 | return; | |
2899 | ||
2900 | switch (connector->connector_type) { | |
2901 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2902 | case DRM_MODE_CONNECTOR_eDP: | |
2903 | intel_dp_info(m, intel_connector); | |
2904 | break; | |
2905 | case DRM_MODE_CONNECTOR_LVDS: | |
2906 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2907 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2908 | break; |
2909 | case DRM_MODE_CONNECTOR_HDMIA: | |
2910 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2911 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2912 | intel_hdmi_info(m, intel_connector); | |
2913 | break; | |
2914 | default: | |
2915 | break; | |
36cd7444 | 2916 | } |
53f5e3ca | 2917 | |
f103fc7d JB |
2918 | seq_printf(m, "\tmodes:\n"); |
2919 | list_for_each_entry(mode, &connector->modes, head) | |
2920 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2921 | } |
2922 | ||
36cdd013 | 2923 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2924 | { |
065f2ec2 CW |
2925 | u32 state; |
2926 | ||
36cdd013 | 2927 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 2928 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2929 | else |
5efb3e28 | 2930 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2931 | |
2932 | return state; | |
2933 | } | |
2934 | ||
36cdd013 DW |
2935 | static bool cursor_position(struct drm_i915_private *dev_priv, |
2936 | int pipe, int *x, int *y) | |
065f2ec2 | 2937 | { |
065f2ec2 CW |
2938 | u32 pos; |
2939 | ||
5efb3e28 | 2940 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2941 | |
2942 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2943 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2944 | *x = -*x; | |
2945 | ||
2946 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2947 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2948 | *y = -*y; | |
2949 | ||
36cdd013 | 2950 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
2951 | } |
2952 | ||
3abc4e09 RF |
2953 | static const char *plane_type(enum drm_plane_type type) |
2954 | { | |
2955 | switch (type) { | |
2956 | case DRM_PLANE_TYPE_OVERLAY: | |
2957 | return "OVL"; | |
2958 | case DRM_PLANE_TYPE_PRIMARY: | |
2959 | return "PRI"; | |
2960 | case DRM_PLANE_TYPE_CURSOR: | |
2961 | return "CUR"; | |
2962 | /* | |
2963 | * Deliberately omitting default: to generate compiler warnings | |
2964 | * when a new drm_plane_type gets added. | |
2965 | */ | |
2966 | } | |
2967 | ||
2968 | return "unknown"; | |
2969 | } | |
2970 | ||
2971 | static const char *plane_rotation(unsigned int rotation) | |
2972 | { | |
2973 | static char buf[48]; | |
2974 | /* | |
2975 | * According to doc only one DRM_ROTATE_ is allowed but this | |
2976 | * will print them all to visualize if the values are misused | |
2977 | */ | |
2978 | snprintf(buf, sizeof(buf), | |
2979 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
2980 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
2981 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
2982 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
2983 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
2984 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
2985 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
2986 | rotation); |
2987 | ||
2988 | return buf; | |
2989 | } | |
2990 | ||
2991 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2992 | { | |
36cdd013 DW |
2993 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2994 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
2995 | struct intel_plane *intel_plane; |
2996 | ||
2997 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
2998 | struct drm_plane_state *state; | |
2999 | struct drm_plane *plane = &intel_plane->base; | |
3000 | ||
3001 | if (!plane->state) { | |
3002 | seq_puts(m, "plane->state is NULL!\n"); | |
3003 | continue; | |
3004 | } | |
3005 | ||
3006 | state = plane->state; | |
3007 | ||
3008 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3009 | plane->base.id, | |
3010 | plane_type(intel_plane->base.type), | |
3011 | state->crtc_x, state->crtc_y, | |
3012 | state->crtc_w, state->crtc_h, | |
3013 | (state->src_x >> 16), | |
3014 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3015 | (state->src_y >> 16), | |
3016 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3017 | (state->src_w >> 16), | |
3018 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3019 | (state->src_h >> 16), | |
3020 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3021 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3022 | plane_rotation(state->rotation)); | |
3023 | } | |
3024 | } | |
3025 | ||
3026 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3027 | { | |
3028 | struct intel_crtc_state *pipe_config; | |
3029 | int num_scalers = intel_crtc->num_scalers; | |
3030 | int i; | |
3031 | ||
3032 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3033 | ||
3034 | /* Not all platformas have a scaler */ | |
3035 | if (num_scalers) { | |
3036 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3037 | num_scalers, | |
3038 | pipe_config->scaler_state.scaler_users, | |
3039 | pipe_config->scaler_state.scaler_id); | |
3040 | ||
3041 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3042 | struct intel_scaler *sc = | |
3043 | &pipe_config->scaler_state.scalers[i]; | |
3044 | ||
3045 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3046 | i, yesno(sc->in_use), sc->mode); | |
3047 | } | |
3048 | seq_puts(m, "\n"); | |
3049 | } else { | |
3050 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3051 | } | |
3052 | } | |
3053 | ||
53f5e3ca JB |
3054 | static int i915_display_info(struct seq_file *m, void *unused) |
3055 | { | |
36cdd013 DW |
3056 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3057 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3058 | struct intel_crtc *crtc; |
53f5e3ca JB |
3059 | struct drm_connector *connector; |
3060 | ||
b0e5ddf3 | 3061 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3062 | drm_modeset_lock_all(dev); |
3063 | seq_printf(m, "CRTC info\n"); | |
3064 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3065 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3066 | bool active; |
f77076c9 | 3067 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3068 | int x, y; |
53f5e3ca | 3069 | |
f77076c9 ML |
3070 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3071 | ||
3abc4e09 | 3072 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3073 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3074 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3075 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3076 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3077 | ||
f77076c9 | 3078 | if (pipe_config->base.active) { |
065f2ec2 CW |
3079 | intel_crtc_info(m, crtc); |
3080 | ||
36cdd013 | 3081 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3082 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3083 | yesno(crtc->cursor_base), |
3dd512fb MR |
3084 | x, y, crtc->base.cursor->state->crtc_w, |
3085 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3086 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3087 | intel_scaler_info(m, crtc); |
3088 | intel_plane_info(m, crtc); | |
a23dc658 | 3089 | } |
cace841c DV |
3090 | |
3091 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3092 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3093 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3094 | } |
3095 | ||
3096 | seq_printf(m, "\n"); | |
3097 | seq_printf(m, "Connector info\n"); | |
3098 | seq_printf(m, "--------------\n"); | |
3099 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3100 | intel_connector_info(m, connector); | |
3101 | } | |
3102 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3103 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3104 | |
3105 | return 0; | |
3106 | } | |
3107 | ||
e04934cf BW |
3108 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3109 | { | |
36cdd013 DW |
3110 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3111 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3112 | struct intel_engine_cs *engine; |
36cdd013 | 3113 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3114 | enum intel_engine_id id; |
3115 | int j, ret; | |
e04934cf | 3116 | |
39df9190 | 3117 | if (!i915.semaphores) { |
e04934cf BW |
3118 | seq_puts(m, "Semaphores are disabled\n"); |
3119 | return 0; | |
3120 | } | |
3121 | ||
3122 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3123 | if (ret) | |
3124 | return ret; | |
03872064 | 3125 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3126 | |
36cdd013 | 3127 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3128 | struct page *page; |
3129 | uint64_t *seqno; | |
3130 | ||
51d545d0 | 3131 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3132 | |
3133 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3134 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3135 | uint64_t offset; |
3136 | ||
e2f80391 | 3137 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3138 | |
3139 | seq_puts(m, " Last signal:"); | |
3140 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3141 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3142 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3143 | seqno[offset], offset * 8); | |
3144 | } | |
3145 | seq_putc(m, '\n'); | |
3146 | ||
3147 | seq_puts(m, " Last wait: "); | |
3148 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3149 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3150 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3151 | seqno[offset], offset * 8); | |
3152 | } | |
3153 | seq_putc(m, '\n'); | |
3154 | ||
3155 | } | |
3156 | kunmap_atomic(seqno); | |
3157 | } else { | |
3158 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3159 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3160 | for (j = 0; j < num_rings; j++) |
3161 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3162 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3163 | seq_putc(m, '\n'); |
3164 | } | |
3165 | ||
3166 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3167 | for_each_engine(engine, dev_priv) { |
3168 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3169 | seq_printf(m, " 0x%08x ", |
3170 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3171 | seq_putc(m, '\n'); |
3172 | } | |
3173 | seq_putc(m, '\n'); | |
3174 | ||
03872064 | 3175 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3176 | mutex_unlock(&dev->struct_mutex); |
3177 | return 0; | |
3178 | } | |
3179 | ||
728e29d7 DV |
3180 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3181 | { | |
36cdd013 DW |
3182 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3183 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3184 | int i; |
3185 | ||
3186 | drm_modeset_lock_all(dev); | |
3187 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3188 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3189 | ||
3190 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3191 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3192 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3193 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3194 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3195 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3196 | pll->config.hw_state.dpll_md); | |
3197 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3198 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3199 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3200 | } |
3201 | drm_modeset_unlock_all(dev); | |
3202 | ||
3203 | return 0; | |
3204 | } | |
3205 | ||
1ed1ef9d | 3206 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3207 | { |
3208 | int i; | |
3209 | int ret; | |
e2f80391 | 3210 | struct intel_engine_cs *engine; |
36cdd013 DW |
3211 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3212 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3213 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3214 | enum intel_engine_id id; |
888b5995 | 3215 | |
888b5995 AS |
3216 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3217 | if (ret) | |
3218 | return ret; | |
3219 | ||
3220 | intel_runtime_pm_get(dev_priv); | |
3221 | ||
33136b06 | 3222 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3223 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3224 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3225 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3226 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3227 | i915_reg_t addr; |
3228 | u32 mask, value, read; | |
2fa60f6d | 3229 | bool ok; |
888b5995 | 3230 | |
33136b06 AS |
3231 | addr = workarounds->reg[i].addr; |
3232 | mask = workarounds->reg[i].mask; | |
3233 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3234 | read = I915_READ(addr); |
3235 | ok = (value & mask) == (read & mask); | |
3236 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3237 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3238 | } |
3239 | ||
3240 | intel_runtime_pm_put(dev_priv); | |
3241 | mutex_unlock(&dev->struct_mutex); | |
3242 | ||
3243 | return 0; | |
3244 | } | |
3245 | ||
c5511e44 DL |
3246 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3247 | { | |
36cdd013 DW |
3248 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3249 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3250 | struct skl_ddb_allocation *ddb; |
3251 | struct skl_ddb_entry *entry; | |
3252 | enum pipe pipe; | |
3253 | int plane; | |
3254 | ||
36cdd013 | 3255 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3256 | return 0; |
3257 | ||
c5511e44 DL |
3258 | drm_modeset_lock_all(dev); |
3259 | ||
3260 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3261 | ||
3262 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3263 | ||
3264 | for_each_pipe(dev_priv, pipe) { | |
3265 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3266 | ||
dd740780 | 3267 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3268 | entry = &ddb->plane[pipe][plane]; |
3269 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3270 | entry->start, entry->end, | |
3271 | skl_ddb_entry_size(entry)); | |
3272 | } | |
3273 | ||
4969d33e | 3274 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3275 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3276 | entry->end, skl_ddb_entry_size(entry)); | |
3277 | } | |
3278 | ||
3279 | drm_modeset_unlock_all(dev); | |
3280 | ||
3281 | return 0; | |
3282 | } | |
3283 | ||
a54746e3 | 3284 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3285 | struct drm_device *dev, |
3286 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3287 | { |
fac5e23e | 3288 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3289 | struct i915_drrs *drrs = &dev_priv->drrs; |
3290 | int vrefresh = 0; | |
26875fe5 | 3291 | struct drm_connector *connector; |
a54746e3 | 3292 | |
26875fe5 ML |
3293 | drm_for_each_connector(connector, dev) { |
3294 | if (connector->state->crtc != &intel_crtc->base) | |
3295 | continue; | |
3296 | ||
3297 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3298 | } |
3299 | ||
3300 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3301 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3302 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3303 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3304 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3305 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3306 | else | |
3307 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3308 | ||
3309 | seq_puts(m, "\n\n"); | |
3310 | ||
f77076c9 | 3311 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3312 | struct intel_panel *panel; |
3313 | ||
3314 | mutex_lock(&drrs->mutex); | |
3315 | /* DRRS Supported */ | |
3316 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3317 | ||
3318 | /* disable_drrs() will make drrs->dp NULL */ | |
3319 | if (!drrs->dp) { | |
3320 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3321 | mutex_unlock(&drrs->mutex); | |
3322 | return; | |
3323 | } | |
3324 | ||
3325 | panel = &drrs->dp->attached_connector->panel; | |
3326 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3327 | drrs->busy_frontbuffer_bits); | |
3328 | ||
3329 | seq_puts(m, "\n\t\t"); | |
3330 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3331 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3332 | vrefresh = panel->fixed_mode->vrefresh; | |
3333 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3334 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3335 | vrefresh = panel->downclock_mode->vrefresh; | |
3336 | } else { | |
3337 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3338 | drrs->refresh_rate_type); | |
3339 | mutex_unlock(&drrs->mutex); | |
3340 | return; | |
3341 | } | |
3342 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3343 | ||
3344 | seq_puts(m, "\n\t\t"); | |
3345 | mutex_unlock(&drrs->mutex); | |
3346 | } else { | |
3347 | /* DRRS not supported. Print the VBT parameter*/ | |
3348 | seq_puts(m, "\tDRRS Supported : No"); | |
3349 | } | |
3350 | seq_puts(m, "\n"); | |
3351 | } | |
3352 | ||
3353 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3354 | { | |
36cdd013 DW |
3355 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3356 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3357 | struct intel_crtc *intel_crtc; |
3358 | int active_crtc_cnt = 0; | |
3359 | ||
26875fe5 | 3360 | drm_modeset_lock_all(dev); |
a54746e3 | 3361 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3362 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3363 | active_crtc_cnt++; |
3364 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3365 | ||
3366 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3367 | } | |
a54746e3 | 3368 | } |
26875fe5 | 3369 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3370 | |
3371 | if (!active_crtc_cnt) | |
3372 | seq_puts(m, "No active crtc found\n"); | |
3373 | ||
3374 | return 0; | |
3375 | } | |
3376 | ||
07144428 DL |
3377 | struct pipe_crc_info { |
3378 | const char *name; | |
36cdd013 | 3379 | struct drm_i915_private *dev_priv; |
07144428 DL |
3380 | enum pipe pipe; |
3381 | }; | |
3382 | ||
11bed958 DA |
3383 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3384 | { | |
36cdd013 DW |
3385 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3386 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3387 | struct intel_encoder *intel_encoder; |
3388 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3389 | struct drm_connector *connector; |
3390 | ||
11bed958 | 3391 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3392 | drm_for_each_connector(connector, dev) { |
3393 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3394 | continue; |
b6dabe3b ML |
3395 | |
3396 | intel_encoder = intel_attached_encoder(connector); | |
3397 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3398 | continue; | |
3399 | ||
3400 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3401 | if (!intel_dig_port->dp.can_mst) |
3402 | continue; | |
b6dabe3b | 3403 | |
40ae80cc JB |
3404 | seq_printf(m, "MST Source Port %c\n", |
3405 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3406 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3407 | } | |
3408 | drm_modeset_unlock_all(dev); | |
3409 | return 0; | |
3410 | } | |
3411 | ||
07144428 DL |
3412 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3413 | { | |
be5c7a90 | 3414 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3415 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3416 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3417 | ||
36cdd013 | 3418 | if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) |
7eb1c496 DV |
3419 | return -ENODEV; |
3420 | ||
d538bbdf DL |
3421 | spin_lock_irq(&pipe_crc->lock); |
3422 | ||
3423 | if (pipe_crc->opened) { | |
3424 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3425 | return -EBUSY; /* already open */ |
3426 | } | |
3427 | ||
d538bbdf | 3428 | pipe_crc->opened = true; |
07144428 DL |
3429 | filep->private_data = inode->i_private; |
3430 | ||
d538bbdf DL |
3431 | spin_unlock_irq(&pipe_crc->lock); |
3432 | ||
07144428 DL |
3433 | return 0; |
3434 | } | |
3435 | ||
3436 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3437 | { | |
be5c7a90 | 3438 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3439 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3440 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3441 | ||
d538bbdf DL |
3442 | spin_lock_irq(&pipe_crc->lock); |
3443 | pipe_crc->opened = false; | |
3444 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3445 | |
07144428 DL |
3446 | return 0; |
3447 | } | |
3448 | ||
3449 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3450 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3451 | /* account for \'0' */ | |
3452 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3453 | ||
3454 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3455 | { |
d538bbdf DL |
3456 | assert_spin_locked(&pipe_crc->lock); |
3457 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3458 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3459 | } |
3460 | ||
3461 | static ssize_t | |
3462 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3463 | loff_t *pos) | |
3464 | { | |
3465 | struct pipe_crc_info *info = filep->private_data; | |
36cdd013 | 3466 | struct drm_i915_private *dev_priv = info->dev_priv; |
07144428 DL |
3467 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3468 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3469 | int n_entries; |
07144428 DL |
3470 | ssize_t bytes_read; |
3471 | ||
3472 | /* | |
3473 | * Don't allow user space to provide buffers not big enough to hold | |
3474 | * a line of data. | |
3475 | */ | |
3476 | if (count < PIPE_CRC_LINE_LEN) | |
3477 | return -EINVAL; | |
3478 | ||
3479 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3480 | return 0; |
07144428 DL |
3481 | |
3482 | /* nothing to read */ | |
d538bbdf | 3483 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3484 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3485 | int ret; |
3486 | ||
3487 | if (filep->f_flags & O_NONBLOCK) { | |
3488 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3489 | return -EAGAIN; |
d538bbdf | 3490 | } |
07144428 | 3491 | |
d538bbdf DL |
3492 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3493 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3494 | if (ret) { | |
3495 | spin_unlock_irq(&pipe_crc->lock); | |
3496 | return ret; | |
3497 | } | |
8bf1e9f1 SH |
3498 | } |
3499 | ||
07144428 | 3500 | /* We now have one or more entries to read */ |
9ad6d99f | 3501 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3502 | |
07144428 | 3503 | bytes_read = 0; |
9ad6d99f VS |
3504 | while (n_entries > 0) { |
3505 | struct intel_pipe_crc_entry *entry = | |
3506 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3507 | |
9ad6d99f VS |
3508 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3509 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3510 | break; | |
3511 | ||
3512 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3513 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3514 | ||
07144428 DL |
3515 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3516 | "%8u %8x %8x %8x %8x %8x\n", | |
3517 | entry->frame, entry->crc[0], | |
3518 | entry->crc[1], entry->crc[2], | |
3519 | entry->crc[3], entry->crc[4]); | |
3520 | ||
9ad6d99f VS |
3521 | spin_unlock_irq(&pipe_crc->lock); |
3522 | ||
4e9121e6 | 3523 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3524 | return -EFAULT; |
b2c88f5b | 3525 | |
9ad6d99f VS |
3526 | user_buf += PIPE_CRC_LINE_LEN; |
3527 | n_entries--; | |
3528 | ||
3529 | spin_lock_irq(&pipe_crc->lock); | |
3530 | } | |
8bf1e9f1 | 3531 | |
d538bbdf DL |
3532 | spin_unlock_irq(&pipe_crc->lock); |
3533 | ||
07144428 DL |
3534 | return bytes_read; |
3535 | } | |
3536 | ||
3537 | static const struct file_operations i915_pipe_crc_fops = { | |
3538 | .owner = THIS_MODULE, | |
3539 | .open = i915_pipe_crc_open, | |
3540 | .read = i915_pipe_crc_read, | |
3541 | .release = i915_pipe_crc_release, | |
3542 | }; | |
3543 | ||
3544 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3545 | { | |
3546 | .name = "i915_pipe_A_crc", | |
3547 | .pipe = PIPE_A, | |
3548 | }, | |
3549 | { | |
3550 | .name = "i915_pipe_B_crc", | |
3551 | .pipe = PIPE_B, | |
3552 | }, | |
3553 | { | |
3554 | .name = "i915_pipe_C_crc", | |
3555 | .pipe = PIPE_C, | |
3556 | }, | |
3557 | }; | |
3558 | ||
3559 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3560 | enum pipe pipe) | |
3561 | { | |
36cdd013 | 3562 | struct drm_i915_private *dev_priv = to_i915(minor->dev); |
07144428 DL |
3563 | struct dentry *ent; |
3564 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3565 | ||
36cdd013 | 3566 | info->dev_priv = dev_priv; |
07144428 DL |
3567 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
3568 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3569 | if (!ent) |
3570 | return -ENOMEM; | |
07144428 DL |
3571 | |
3572 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3573 | } |
3574 | ||
e8dfcf78 | 3575 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3576 | "none", |
3577 | "plane1", | |
3578 | "plane2", | |
3579 | "pf", | |
5b3a856b | 3580 | "pipe", |
3d099a05 DV |
3581 | "TV", |
3582 | "DP-B", | |
3583 | "DP-C", | |
3584 | "DP-D", | |
46a19188 | 3585 | "auto", |
926321d5 DV |
3586 | }; |
3587 | ||
3588 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3589 | { | |
3590 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3591 | return pipe_crc_sources[source]; | |
3592 | } | |
3593 | ||
bd9db02f | 3594 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 | 3595 | { |
36cdd013 | 3596 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
3597 | int i; |
3598 | ||
3599 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3600 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3601 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3602 | ||
3603 | return 0; | |
3604 | } | |
3605 | ||
bd9db02f | 3606 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 | 3607 | { |
36cdd013 | 3608 | return single_open(file, display_crc_ctl_show, inode->i_private); |
926321d5 DV |
3609 | } |
3610 | ||
46a19188 | 3611 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3612 | uint32_t *val) |
3613 | { | |
46a19188 DV |
3614 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3615 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3616 | ||
3617 | switch (*source) { | |
52f843f6 DV |
3618 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3619 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3620 | break; | |
3621 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3622 | *val = 0; | |
3623 | break; | |
3624 | default: | |
3625 | return -EINVAL; | |
3626 | } | |
3627 | ||
3628 | return 0; | |
3629 | } | |
3630 | ||
36cdd013 DW |
3631 | static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, |
3632 | enum pipe pipe, | |
46a19188 DV |
3633 | enum intel_pipe_crc_source *source) |
3634 | { | |
36cdd013 | 3635 | struct drm_device *dev = &dev_priv->drm; |
46a19188 DV |
3636 | struct intel_encoder *encoder; |
3637 | struct intel_crtc *crtc; | |
26756809 | 3638 | struct intel_digital_port *dig_port; |
46a19188 DV |
3639 | int ret = 0; |
3640 | ||
3641 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3642 | ||
6e9f798d | 3643 | drm_modeset_lock_all(dev); |
b2784e15 | 3644 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3645 | if (!encoder->base.crtc) |
3646 | continue; | |
3647 | ||
3648 | crtc = to_intel_crtc(encoder->base.crtc); | |
3649 | ||
3650 | if (crtc->pipe != pipe) | |
3651 | continue; | |
3652 | ||
3653 | switch (encoder->type) { | |
3654 | case INTEL_OUTPUT_TVOUT: | |
3655 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3656 | break; | |
cca0502b | 3657 | case INTEL_OUTPUT_DP: |
46a19188 | 3658 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3659 | dig_port = enc_to_dig_port(&encoder->base); |
3660 | switch (dig_port->port) { | |
3661 | case PORT_B: | |
3662 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3663 | break; | |
3664 | case PORT_C: | |
3665 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3666 | break; | |
3667 | case PORT_D: | |
3668 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3669 | break; | |
3670 | default: | |
3671 | WARN(1, "nonexisting DP port %c\n", | |
3672 | port_name(dig_port->port)); | |
3673 | break; | |
3674 | } | |
46a19188 | 3675 | break; |
6847d71b PZ |
3676 | default: |
3677 | break; | |
46a19188 DV |
3678 | } |
3679 | } | |
6e9f798d | 3680 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3681 | |
3682 | return ret; | |
3683 | } | |
3684 | ||
36cdd013 | 3685 | static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3686 | enum pipe pipe, |
3687 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3688 | uint32_t *val) |
3689 | { | |
8d2f24ca DV |
3690 | bool need_stable_symbols = false; |
3691 | ||
46a19188 | 3692 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3693 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3694 | if (ret) |
3695 | return ret; | |
3696 | } | |
3697 | ||
3698 | switch (*source) { | |
7ac0129b DV |
3699 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3700 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3701 | break; | |
3702 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3703 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3704 | need_stable_symbols = true; |
7ac0129b DV |
3705 | break; |
3706 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3707 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3708 | need_stable_symbols = true; |
7ac0129b | 3709 | break; |
2be57922 | 3710 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
36cdd013 | 3711 | if (!IS_CHERRYVIEW(dev_priv)) |
2be57922 VS |
3712 | return -EINVAL; |
3713 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3714 | need_stable_symbols = true; | |
3715 | break; | |
7ac0129b DV |
3716 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3717 | *val = 0; | |
3718 | break; | |
3719 | default: | |
3720 | return -EINVAL; | |
3721 | } | |
3722 | ||
8d2f24ca DV |
3723 | /* |
3724 | * When the pipe CRC tap point is after the transcoders we need | |
3725 | * to tweak symbol-level features to produce a deterministic series of | |
3726 | * symbols for a given frame. We need to reset those features only once | |
3727 | * a frame (instead of every nth symbol): | |
3728 | * - DC-balance: used to ensure a better clock recovery from the data | |
3729 | * link (SDVO) | |
3730 | * - DisplayPort scrambling: used for EMI reduction | |
3731 | */ | |
3732 | if (need_stable_symbols) { | |
3733 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3734 | ||
8d2f24ca | 3735 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3736 | switch (pipe) { |
3737 | case PIPE_A: | |
8d2f24ca | 3738 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3739 | break; |
3740 | case PIPE_B: | |
8d2f24ca | 3741 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3742 | break; |
3743 | case PIPE_C: | |
3744 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3745 | break; | |
3746 | default: | |
3747 | return -EINVAL; | |
3748 | } | |
8d2f24ca DV |
3749 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3750 | } | |
3751 | ||
7ac0129b DV |
3752 | return 0; |
3753 | } | |
3754 | ||
36cdd013 | 3755 | static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3756 | enum pipe pipe, |
3757 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3758 | uint32_t *val) |
3759 | { | |
84093603 DV |
3760 | bool need_stable_symbols = false; |
3761 | ||
46a19188 | 3762 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3763 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3764 | if (ret) |
3765 | return ret; | |
3766 | } | |
3767 | ||
3768 | switch (*source) { | |
4b79ebf7 DV |
3769 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3770 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3771 | break; | |
3772 | case INTEL_PIPE_CRC_SOURCE_TV: | |
36cdd013 | 3773 | if (!SUPPORTS_TV(dev_priv)) |
4b79ebf7 DV |
3774 | return -EINVAL; |
3775 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3776 | break; | |
3777 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
36cdd013 | 3778 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3779 | return -EINVAL; |
3780 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3781 | need_stable_symbols = true; |
4b79ebf7 DV |
3782 | break; |
3783 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
36cdd013 | 3784 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3785 | return -EINVAL; |
3786 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3787 | need_stable_symbols = true; |
4b79ebf7 DV |
3788 | break; |
3789 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
36cdd013 | 3790 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3791 | return -EINVAL; |
3792 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3793 | need_stable_symbols = true; |
4b79ebf7 DV |
3794 | break; |
3795 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3796 | *val = 0; | |
3797 | break; | |
3798 | default: | |
3799 | return -EINVAL; | |
3800 | } | |
3801 | ||
84093603 DV |
3802 | /* |
3803 | * When the pipe CRC tap point is after the transcoders we need | |
3804 | * to tweak symbol-level features to produce a deterministic series of | |
3805 | * symbols for a given frame. We need to reset those features only once | |
3806 | * a frame (instead of every nth symbol): | |
3807 | * - DC-balance: used to ensure a better clock recovery from the data | |
3808 | * link (SDVO) | |
3809 | * - DisplayPort scrambling: used for EMI reduction | |
3810 | */ | |
3811 | if (need_stable_symbols) { | |
3812 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3813 | ||
36cdd013 | 3814 | WARN_ON(!IS_G4X(dev_priv)); |
84093603 DV |
3815 | |
3816 | I915_WRITE(PORT_DFT_I9XX, | |
3817 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3818 | ||
3819 | if (pipe == PIPE_A) | |
3820 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3821 | else | |
3822 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3823 | ||
3824 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3825 | } | |
3826 | ||
4b79ebf7 DV |
3827 | return 0; |
3828 | } | |
3829 | ||
36cdd013 | 3830 | static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
8d2f24ca DV |
3831 | enum pipe pipe) |
3832 | { | |
8d2f24ca DV |
3833 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3834 | ||
eb736679 VS |
3835 | switch (pipe) { |
3836 | case PIPE_A: | |
8d2f24ca | 3837 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3838 | break; |
3839 | case PIPE_B: | |
8d2f24ca | 3840 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3841 | break; |
3842 | case PIPE_C: | |
3843 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3844 | break; | |
3845 | default: | |
3846 | return; | |
3847 | } | |
8d2f24ca DV |
3848 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3849 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3850 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3851 | ||
3852 | } | |
3853 | ||
36cdd013 | 3854 | static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
84093603 DV |
3855 | enum pipe pipe) |
3856 | { | |
84093603 DV |
3857 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3858 | ||
3859 | if (pipe == PIPE_A) | |
3860 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3861 | else | |
3862 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3863 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3864 | ||
3865 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3866 | I915_WRITE(PORT_DFT_I9XX, | |
3867 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3868 | } | |
3869 | } | |
3870 | ||
46a19188 | 3871 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3872 | uint32_t *val) |
3873 | { | |
46a19188 DV |
3874 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3875 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3876 | ||
3877 | switch (*source) { | |
5b3a856b DV |
3878 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3879 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3880 | break; | |
3881 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3882 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3883 | break; | |
5b3a856b DV |
3884 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3885 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3886 | break; | |
3d099a05 | 3887 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3888 | *val = 0; |
3889 | break; | |
3d099a05 DV |
3890 | default: |
3891 | return -EINVAL; | |
5b3a856b DV |
3892 | } |
3893 | ||
3894 | return 0; | |
3895 | } | |
3896 | ||
36cdd013 DW |
3897 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, |
3898 | bool enable) | |
fabf6e51 | 3899 | { |
36cdd013 | 3900 | struct drm_device *dev = &dev_priv->drm; |
fabf6e51 DV |
3901 | struct intel_crtc *crtc = |
3902 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3903 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3904 | struct drm_atomic_state *state; |
3905 | int ret = 0; | |
fabf6e51 DV |
3906 | |
3907 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3908 | state = drm_atomic_state_alloc(dev); |
3909 | if (!state) { | |
3910 | ret = -ENOMEM; | |
3911 | goto out; | |
fabf6e51 | 3912 | } |
fabf6e51 | 3913 | |
c4e2d043 ML |
3914 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3915 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3916 | if (IS_ERR(pipe_config)) { | |
3917 | ret = PTR_ERR(pipe_config); | |
3918 | goto out; | |
3919 | } | |
fabf6e51 | 3920 | |
c4e2d043 ML |
3921 | pipe_config->pch_pfit.force_thru = enable; |
3922 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
3923 | pipe_config->pch_pfit.enabled != enable) | |
3924 | pipe_config->base.connectors_changed = true; | |
1b509259 | 3925 | |
c4e2d043 ML |
3926 | ret = drm_atomic_commit(state); |
3927 | out: | |
fabf6e51 | 3928 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
3929 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
3930 | if (ret) | |
3931 | drm_atomic_state_free(state); | |
fabf6e51 DV |
3932 | } |
3933 | ||
36cdd013 | 3934 | static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
fabf6e51 DV |
3935 | enum pipe pipe, |
3936 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3937 | uint32_t *val) |
3938 | { | |
46a19188 DV |
3939 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3940 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3941 | ||
3942 | switch (*source) { | |
5b3a856b DV |
3943 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3944 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3945 | break; | |
3946 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3947 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3948 | break; | |
3949 | case INTEL_PIPE_CRC_SOURCE_PF: | |
36cdd013 DW |
3950 | if (IS_HASWELL(dev_priv) && pipe == PIPE_A) |
3951 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); | |
fabf6e51 | 3952 | |
5b3a856b DV |
3953 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3954 | break; | |
3d099a05 | 3955 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3956 | *val = 0; |
3957 | break; | |
3d099a05 DV |
3958 | default: |
3959 | return -EINVAL; | |
5b3a856b DV |
3960 | } |
3961 | ||
3962 | return 0; | |
3963 | } | |
3964 | ||
36cdd013 DW |
3965 | static int pipe_crc_set_source(struct drm_i915_private *dev_priv, |
3966 | enum pipe pipe, | |
926321d5 DV |
3967 | enum intel_pipe_crc_source source) |
3968 | { | |
36cdd013 | 3969 | struct drm_device *dev = &dev_priv->drm; |
cc3da175 | 3970 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
36cdd013 DW |
3971 | struct intel_crtc *crtc = |
3972 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
e129649b | 3973 | enum intel_display_power_domain power_domain; |
432f3342 | 3974 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3975 | int ret; |
926321d5 | 3976 | |
cc3da175 DL |
3977 | if (pipe_crc->source == source) |
3978 | return 0; | |
3979 | ||
ae676fcd DL |
3980 | /* forbid changing the source without going back to 'none' */ |
3981 | if (pipe_crc->source && source) | |
3982 | return -EINVAL; | |
3983 | ||
e129649b ID |
3984 | power_domain = POWER_DOMAIN_PIPE(pipe); |
3985 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
3986 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
3987 | return -EIO; | |
3988 | } | |
3989 | ||
36cdd013 | 3990 | if (IS_GEN2(dev_priv)) |
46a19188 | 3991 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
36cdd013 DW |
3992 | else if (INTEL_GEN(dev_priv) < 5) |
3993 | ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
3994 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
3995 | ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
3996 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) | |
46a19188 | 3997 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3998 | else |
36cdd013 | 3999 | ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); |
5b3a856b DV |
4000 | |
4001 | if (ret != 0) | |
e129649b | 4002 | goto out; |
5b3a856b | 4003 | |
4b584369 DL |
4004 | /* none -> real source transition */ |
4005 | if (source) { | |
4252fbc3 VS |
4006 | struct intel_pipe_crc_entry *entries; |
4007 | ||
7cd6ccff DL |
4008 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4009 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4010 | ||
3cf54b34 VS |
4011 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4012 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4013 | GFP_KERNEL); |
e129649b ID |
4014 | if (!entries) { |
4015 | ret = -ENOMEM; | |
4016 | goto out; | |
4017 | } | |
e5f75aca | 4018 | |
8c740dce PZ |
4019 | /* |
4020 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4021 | * enabled and disabled dynamically based on package C states, | |
4022 | * user space can't make reliable use of the CRCs, so let's just | |
4023 | * completely disable it. | |
4024 | */ | |
4025 | hsw_disable_ips(crtc); | |
4026 | ||
d538bbdf | 4027 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4028 | kfree(pipe_crc->entries); |
4252fbc3 | 4029 | pipe_crc->entries = entries; |
d538bbdf DL |
4030 | pipe_crc->head = 0; |
4031 | pipe_crc->tail = 0; | |
4032 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4033 | } |
4034 | ||
cc3da175 | 4035 | pipe_crc->source = source; |
926321d5 | 4036 | |
926321d5 DV |
4037 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4038 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4039 | ||
e5f75aca DL |
4040 | /* real source -> none transition */ |
4041 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4042 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4043 | struct intel_crtc *crtc = |
4044 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4045 | |
7cd6ccff DL |
4046 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4047 | pipe_name(pipe)); | |
4048 | ||
a33d7105 | 4049 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4050 | if (crtc->base.state->active) |
a33d7105 DV |
4051 | intel_wait_for_vblank(dev, pipe); |
4052 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4053 | |
d538bbdf DL |
4054 | spin_lock_irq(&pipe_crc->lock); |
4055 | entries = pipe_crc->entries; | |
e5f75aca | 4056 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4057 | pipe_crc->head = 0; |
4058 | pipe_crc->tail = 0; | |
d538bbdf DL |
4059 | spin_unlock_irq(&pipe_crc->lock); |
4060 | ||
4061 | kfree(entries); | |
84093603 | 4062 | |
36cdd013 DW |
4063 | if (IS_G4X(dev_priv)) |
4064 | g4x_undo_pipe_scramble_reset(dev_priv, pipe); | |
4065 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4066 | vlv_undo_pipe_scramble_reset(dev_priv, pipe); | |
4067 | else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
4068 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
8c740dce PZ |
4069 | |
4070 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4071 | } |
4072 | ||
e129649b ID |
4073 | ret = 0; |
4074 | ||
4075 | out: | |
4076 | intel_display_power_put(dev_priv, power_domain); | |
4077 | ||
4078 | return ret; | |
926321d5 DV |
4079 | } |
4080 | ||
4081 | /* | |
4082 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4083 | * command: wsp* object wsp+ name wsp+ source wsp* |
4084 | * object: 'pipe' | |
4085 | * name: (A | B | C) | |
926321d5 DV |
4086 | * source: (none | plane1 | plane2 | pf) |
4087 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4088 | * | |
4089 | * eg.: | |
b94dec87 DL |
4090 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4091 | * "pipe A none" -> Stop CRC | |
926321d5 | 4092 | */ |
bd9db02f | 4093 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4094 | { |
4095 | int n_words = 0; | |
4096 | ||
4097 | while (*buf) { | |
4098 | char *end; | |
4099 | ||
4100 | /* skip leading white space */ | |
4101 | buf = skip_spaces(buf); | |
4102 | if (!*buf) | |
4103 | break; /* end of buffer */ | |
4104 | ||
4105 | /* find end of word */ | |
4106 | for (end = buf; *end && !isspace(*end); end++) | |
4107 | ; | |
4108 | ||
4109 | if (n_words == max_words) { | |
4110 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4111 | max_words); | |
4112 | return -EINVAL; /* ran out of words[] before bytes */ | |
4113 | } | |
4114 | ||
4115 | if (*end) | |
4116 | *end++ = '\0'; | |
4117 | words[n_words++] = buf; | |
4118 | buf = end; | |
4119 | } | |
4120 | ||
4121 | return n_words; | |
4122 | } | |
4123 | ||
b94dec87 DL |
4124 | enum intel_pipe_crc_object { |
4125 | PIPE_CRC_OBJECT_PIPE, | |
4126 | }; | |
4127 | ||
e8dfcf78 | 4128 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4129 | "pipe", |
4130 | }; | |
4131 | ||
4132 | static int | |
bd9db02f | 4133 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4134 | { |
4135 | int i; | |
4136 | ||
4137 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4138 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4139 | *o = i; |
b94dec87 DL |
4140 | return 0; |
4141 | } | |
4142 | ||
4143 | return -EINVAL; | |
4144 | } | |
4145 | ||
bd9db02f | 4146 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4147 | { |
4148 | const char name = buf[0]; | |
4149 | ||
4150 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4151 | return -EINVAL; | |
4152 | ||
4153 | *pipe = name - 'A'; | |
4154 | ||
4155 | return 0; | |
4156 | } | |
4157 | ||
4158 | static int | |
bd9db02f | 4159 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4160 | { |
4161 | int i; | |
4162 | ||
4163 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4164 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4165 | *s = i; |
926321d5 DV |
4166 | return 0; |
4167 | } | |
4168 | ||
4169 | return -EINVAL; | |
4170 | } | |
4171 | ||
36cdd013 DW |
4172 | static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, |
4173 | char *buf, size_t len) | |
926321d5 | 4174 | { |
b94dec87 | 4175 | #define N_WORDS 3 |
926321d5 | 4176 | int n_words; |
b94dec87 | 4177 | char *words[N_WORDS]; |
926321d5 | 4178 | enum pipe pipe; |
b94dec87 | 4179 | enum intel_pipe_crc_object object; |
926321d5 DV |
4180 | enum intel_pipe_crc_source source; |
4181 | ||
bd9db02f | 4182 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4183 | if (n_words != N_WORDS) { |
4184 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4185 | N_WORDS); | |
4186 | return -EINVAL; | |
4187 | } | |
4188 | ||
bd9db02f | 4189 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4190 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4191 | return -EINVAL; |
4192 | } | |
4193 | ||
bd9db02f | 4194 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4195 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4196 | return -EINVAL; |
4197 | } | |
4198 | ||
bd9db02f | 4199 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4200 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4201 | return -EINVAL; |
4202 | } | |
4203 | ||
36cdd013 | 4204 | return pipe_crc_set_source(dev_priv, pipe, source); |
926321d5 DV |
4205 | } |
4206 | ||
bd9db02f DL |
4207 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4208 | size_t len, loff_t *offp) | |
926321d5 DV |
4209 | { |
4210 | struct seq_file *m = file->private_data; | |
36cdd013 | 4211 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
4212 | char *tmpbuf; |
4213 | int ret; | |
4214 | ||
4215 | if (len == 0) | |
4216 | return 0; | |
4217 | ||
4218 | if (len > PAGE_SIZE - 1) { | |
4219 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4220 | PAGE_SIZE); | |
4221 | return -E2BIG; | |
4222 | } | |
4223 | ||
4224 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4225 | if (!tmpbuf) | |
4226 | return -ENOMEM; | |
4227 | ||
4228 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4229 | ret = -EFAULT; | |
4230 | goto out; | |
4231 | } | |
4232 | tmpbuf[len] = '\0'; | |
4233 | ||
36cdd013 | 4234 | ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); |
926321d5 DV |
4235 | |
4236 | out: | |
4237 | kfree(tmpbuf); | |
4238 | if (ret < 0) | |
4239 | return ret; | |
4240 | ||
4241 | *offp += len; | |
4242 | return len; | |
4243 | } | |
4244 | ||
bd9db02f | 4245 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4246 | .owner = THIS_MODULE, |
bd9db02f | 4247 | .open = display_crc_ctl_open, |
926321d5 DV |
4248 | .read = seq_read, |
4249 | .llseek = seq_lseek, | |
4250 | .release = single_release, | |
bd9db02f | 4251 | .write = display_crc_ctl_write |
926321d5 DV |
4252 | }; |
4253 | ||
eb3394fa | 4254 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
4255 | const char __user *ubuf, |
4256 | size_t len, loff_t *offp) | |
eb3394fa TP |
4257 | { |
4258 | char *input_buffer; | |
4259 | int status = 0; | |
eb3394fa TP |
4260 | struct drm_device *dev; |
4261 | struct drm_connector *connector; | |
4262 | struct list_head *connector_list; | |
4263 | struct intel_dp *intel_dp; | |
4264 | int val = 0; | |
4265 | ||
9aaffa34 | 4266 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4267 | |
eb3394fa TP |
4268 | connector_list = &dev->mode_config.connector_list; |
4269 | ||
4270 | if (len == 0) | |
4271 | return 0; | |
4272 | ||
4273 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4274 | if (!input_buffer) | |
4275 | return -ENOMEM; | |
4276 | ||
4277 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4278 | status = -EFAULT; | |
4279 | goto out; | |
4280 | } | |
4281 | ||
4282 | input_buffer[len] = '\0'; | |
4283 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4284 | ||
4285 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
4286 | if (connector->connector_type != |
4287 | DRM_MODE_CONNECTOR_DisplayPort) | |
4288 | continue; | |
4289 | ||
b8bb08ec | 4290 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4291 | connector->encoder != NULL) { |
4292 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4293 | status = kstrtoint(input_buffer, 10, &val); | |
4294 | if (status < 0) | |
4295 | goto out; | |
4296 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4297 | /* To prevent erroneous activation of the compliance | |
4298 | * testing code, only accept an actual value of 1 here | |
4299 | */ | |
4300 | if (val == 1) | |
4301 | intel_dp->compliance_test_active = 1; | |
4302 | else | |
4303 | intel_dp->compliance_test_active = 0; | |
4304 | } | |
4305 | } | |
4306 | out: | |
4307 | kfree(input_buffer); | |
4308 | if (status < 0) | |
4309 | return status; | |
4310 | ||
4311 | *offp += len; | |
4312 | return len; | |
4313 | } | |
4314 | ||
4315 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4316 | { | |
4317 | struct drm_device *dev = m->private; | |
4318 | struct drm_connector *connector; | |
4319 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4320 | struct intel_dp *intel_dp; | |
4321 | ||
eb3394fa | 4322 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4323 | if (connector->connector_type != |
4324 | DRM_MODE_CONNECTOR_DisplayPort) | |
4325 | continue; | |
4326 | ||
4327 | if (connector->status == connector_status_connected && | |
4328 | connector->encoder != NULL) { | |
4329 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4330 | if (intel_dp->compliance_test_active) | |
4331 | seq_puts(m, "1"); | |
4332 | else | |
4333 | seq_puts(m, "0"); | |
4334 | } else | |
4335 | seq_puts(m, "0"); | |
4336 | } | |
4337 | ||
4338 | return 0; | |
4339 | } | |
4340 | ||
4341 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 4342 | struct file *file) |
eb3394fa | 4343 | { |
36cdd013 | 4344 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4345 | |
36cdd013 DW |
4346 | return single_open(file, i915_displayport_test_active_show, |
4347 | &dev_priv->drm); | |
eb3394fa TP |
4348 | } |
4349 | ||
4350 | static const struct file_operations i915_displayport_test_active_fops = { | |
4351 | .owner = THIS_MODULE, | |
4352 | .open = i915_displayport_test_active_open, | |
4353 | .read = seq_read, | |
4354 | .llseek = seq_lseek, | |
4355 | .release = single_release, | |
4356 | .write = i915_displayport_test_active_write | |
4357 | }; | |
4358 | ||
4359 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4360 | { | |
4361 | struct drm_device *dev = m->private; | |
4362 | struct drm_connector *connector; | |
4363 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4364 | struct intel_dp *intel_dp; | |
4365 | ||
eb3394fa | 4366 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4367 | if (connector->connector_type != |
4368 | DRM_MODE_CONNECTOR_DisplayPort) | |
4369 | continue; | |
4370 | ||
4371 | if (connector->status == connector_status_connected && | |
4372 | connector->encoder != NULL) { | |
4373 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4374 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4375 | } else | |
4376 | seq_puts(m, "0"); | |
4377 | } | |
4378 | ||
4379 | return 0; | |
4380 | } | |
4381 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 4382 | struct file *file) |
eb3394fa | 4383 | { |
36cdd013 | 4384 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4385 | |
36cdd013 DW |
4386 | return single_open(file, i915_displayport_test_data_show, |
4387 | &dev_priv->drm); | |
eb3394fa TP |
4388 | } |
4389 | ||
4390 | static const struct file_operations i915_displayport_test_data_fops = { | |
4391 | .owner = THIS_MODULE, | |
4392 | .open = i915_displayport_test_data_open, | |
4393 | .read = seq_read, | |
4394 | .llseek = seq_lseek, | |
4395 | .release = single_release | |
4396 | }; | |
4397 | ||
4398 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4399 | { | |
4400 | struct drm_device *dev = m->private; | |
4401 | struct drm_connector *connector; | |
4402 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4403 | struct intel_dp *intel_dp; | |
4404 | ||
eb3394fa | 4405 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4406 | if (connector->connector_type != |
4407 | DRM_MODE_CONNECTOR_DisplayPort) | |
4408 | continue; | |
4409 | ||
4410 | if (connector->status == connector_status_connected && | |
4411 | connector->encoder != NULL) { | |
4412 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4413 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4414 | } else | |
4415 | seq_puts(m, "0"); | |
4416 | } | |
4417 | ||
4418 | return 0; | |
4419 | } | |
4420 | ||
4421 | static int i915_displayport_test_type_open(struct inode *inode, | |
4422 | struct file *file) | |
4423 | { | |
36cdd013 | 4424 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4425 | |
36cdd013 DW |
4426 | return single_open(file, i915_displayport_test_type_show, |
4427 | &dev_priv->drm); | |
eb3394fa TP |
4428 | } |
4429 | ||
4430 | static const struct file_operations i915_displayport_test_type_fops = { | |
4431 | .owner = THIS_MODULE, | |
4432 | .open = i915_displayport_test_type_open, | |
4433 | .read = seq_read, | |
4434 | .llseek = seq_lseek, | |
4435 | .release = single_release | |
4436 | }; | |
4437 | ||
97e94b22 | 4438 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 4439 | { |
36cdd013 DW |
4440 | struct drm_i915_private *dev_priv = m->private; |
4441 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 4442 | int level; |
de38b95c VS |
4443 | int num_levels; |
4444 | ||
36cdd013 | 4445 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4446 | num_levels = 3; |
36cdd013 | 4447 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4448 | num_levels = 1; |
4449 | else | |
4450 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4451 | |
4452 | drm_modeset_lock_all(dev); | |
4453 | ||
4454 | for (level = 0; level < num_levels; level++) { | |
4455 | unsigned int latency = wm[level]; | |
4456 | ||
97e94b22 DL |
4457 | /* |
4458 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4459 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4460 | */ |
36cdd013 DW |
4461 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
4462 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
4463 | latency *= 10; |
4464 | else if (level > 0) | |
369a1342 VS |
4465 | latency *= 5; |
4466 | ||
4467 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4468 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4469 | } |
4470 | ||
4471 | drm_modeset_unlock_all(dev); | |
4472 | } | |
4473 | ||
4474 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4475 | { | |
36cdd013 | 4476 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4477 | const uint16_t *latencies; |
4478 | ||
36cdd013 | 4479 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4480 | latencies = dev_priv->wm.skl_latency; |
4481 | else | |
36cdd013 | 4482 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 4483 | |
97e94b22 | 4484 | wm_latency_show(m, latencies); |
369a1342 VS |
4485 | |
4486 | return 0; | |
4487 | } | |
4488 | ||
4489 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4490 | { | |
36cdd013 | 4491 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4492 | const uint16_t *latencies; |
4493 | ||
36cdd013 | 4494 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4495 | latencies = dev_priv->wm.skl_latency; |
4496 | else | |
36cdd013 | 4497 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 4498 | |
97e94b22 | 4499 | wm_latency_show(m, latencies); |
369a1342 VS |
4500 | |
4501 | return 0; | |
4502 | } | |
4503 | ||
4504 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4505 | { | |
36cdd013 | 4506 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4507 | const uint16_t *latencies; |
4508 | ||
36cdd013 | 4509 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4510 | latencies = dev_priv->wm.skl_latency; |
4511 | else | |
36cdd013 | 4512 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4513 | |
97e94b22 | 4514 | wm_latency_show(m, latencies); |
369a1342 VS |
4515 | |
4516 | return 0; | |
4517 | } | |
4518 | ||
4519 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4520 | { | |
36cdd013 | 4521 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4522 | |
36cdd013 | 4523 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
4524 | return -ENODEV; |
4525 | ||
36cdd013 | 4526 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
4527 | } |
4528 | ||
4529 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4530 | { | |
36cdd013 | 4531 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4532 | |
36cdd013 | 4533 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4534 | return -ENODEV; |
4535 | ||
36cdd013 | 4536 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
4537 | } |
4538 | ||
4539 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4540 | { | |
36cdd013 | 4541 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4542 | |
36cdd013 | 4543 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4544 | return -ENODEV; |
4545 | ||
36cdd013 | 4546 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4547 | } |
4548 | ||
4549 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4550 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4551 | { |
4552 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4553 | struct drm_i915_private *dev_priv = m->private; |
4554 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4555 | uint16_t new[8] = { 0 }; |
de38b95c | 4556 | int num_levels; |
369a1342 VS |
4557 | int level; |
4558 | int ret; | |
4559 | char tmp[32]; | |
4560 | ||
36cdd013 | 4561 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4562 | num_levels = 3; |
36cdd013 | 4563 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4564 | num_levels = 1; |
4565 | else | |
4566 | num_levels = ilk_wm_max_level(dev) + 1; | |
4567 | ||
369a1342 VS |
4568 | if (len >= sizeof(tmp)) |
4569 | return -EINVAL; | |
4570 | ||
4571 | if (copy_from_user(tmp, ubuf, len)) | |
4572 | return -EFAULT; | |
4573 | ||
4574 | tmp[len] = '\0'; | |
4575 | ||
97e94b22 DL |
4576 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4577 | &new[0], &new[1], &new[2], &new[3], | |
4578 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4579 | if (ret != num_levels) |
4580 | return -EINVAL; | |
4581 | ||
4582 | drm_modeset_lock_all(dev); | |
4583 | ||
4584 | for (level = 0; level < num_levels; level++) | |
4585 | wm[level] = new[level]; | |
4586 | ||
4587 | drm_modeset_unlock_all(dev); | |
4588 | ||
4589 | return len; | |
4590 | } | |
4591 | ||
4592 | ||
4593 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4594 | size_t len, loff_t *offp) | |
4595 | { | |
4596 | struct seq_file *m = file->private_data; | |
36cdd013 | 4597 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4598 | uint16_t *latencies; |
369a1342 | 4599 | |
36cdd013 | 4600 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4601 | latencies = dev_priv->wm.skl_latency; |
4602 | else | |
36cdd013 | 4603 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4604 | |
4605 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4606 | } |
4607 | ||
4608 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4609 | size_t len, loff_t *offp) | |
4610 | { | |
4611 | struct seq_file *m = file->private_data; | |
36cdd013 | 4612 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4613 | uint16_t *latencies; |
369a1342 | 4614 | |
36cdd013 | 4615 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4616 | latencies = dev_priv->wm.skl_latency; |
4617 | else | |
36cdd013 | 4618 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4619 | |
4620 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4621 | } |
4622 | ||
4623 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4624 | size_t len, loff_t *offp) | |
4625 | { | |
4626 | struct seq_file *m = file->private_data; | |
36cdd013 | 4627 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4628 | uint16_t *latencies; |
4629 | ||
36cdd013 | 4630 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4631 | latencies = dev_priv->wm.skl_latency; |
4632 | else | |
36cdd013 | 4633 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4634 | |
97e94b22 | 4635 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4636 | } |
4637 | ||
4638 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4639 | .owner = THIS_MODULE, | |
4640 | .open = pri_wm_latency_open, | |
4641 | .read = seq_read, | |
4642 | .llseek = seq_lseek, | |
4643 | .release = single_release, | |
4644 | .write = pri_wm_latency_write | |
4645 | }; | |
4646 | ||
4647 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4648 | .owner = THIS_MODULE, | |
4649 | .open = spr_wm_latency_open, | |
4650 | .read = seq_read, | |
4651 | .llseek = seq_lseek, | |
4652 | .release = single_release, | |
4653 | .write = spr_wm_latency_write | |
4654 | }; | |
4655 | ||
4656 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4657 | .owner = THIS_MODULE, | |
4658 | .open = cur_wm_latency_open, | |
4659 | .read = seq_read, | |
4660 | .llseek = seq_lseek, | |
4661 | .release = single_release, | |
4662 | .write = cur_wm_latency_write | |
4663 | }; | |
4664 | ||
647416f9 KC |
4665 | static int |
4666 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4667 | { |
36cdd013 | 4668 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4669 | |
d98c52cf | 4670 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4671 | |
647416f9 | 4672 | return 0; |
f3cd474b CW |
4673 | } |
4674 | ||
647416f9 KC |
4675 | static int |
4676 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4677 | { |
36cdd013 | 4678 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4679 | |
b8d24a06 MK |
4680 | /* |
4681 | * There is no safeguard against this debugfs entry colliding | |
4682 | * with the hangcheck calling same i915_handle_error() in | |
4683 | * parallel, causing an explosion. For now we assume that the | |
4684 | * test harness is responsible enough not to inject gpu hangs | |
4685 | * while it is writing to 'i915_wedged' | |
4686 | */ | |
4687 | ||
d98c52cf | 4688 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4689 | return -EAGAIN; |
4690 | ||
d46c0517 | 4691 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4692 | |
c033666a | 4693 | i915_handle_error(dev_priv, val, |
58174462 | 4694 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4695 | |
4696 | intel_runtime_pm_put(dev_priv); | |
4697 | ||
647416f9 | 4698 | return 0; |
f3cd474b CW |
4699 | } |
4700 | ||
647416f9 KC |
4701 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4702 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4703 | "%llu\n"); |
f3cd474b | 4704 | |
094f9a54 CW |
4705 | static int |
4706 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4707 | { | |
36cdd013 | 4708 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4709 | |
4710 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4711 | return 0; | |
4712 | } | |
4713 | ||
4714 | static int | |
4715 | i915_ring_missed_irq_set(void *data, u64 val) | |
4716 | { | |
36cdd013 DW |
4717 | struct drm_i915_private *dev_priv = data; |
4718 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4719 | int ret; |
4720 | ||
4721 | /* Lock against concurrent debugfs callers */ | |
4722 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4723 | if (ret) | |
4724 | return ret; | |
4725 | dev_priv->gpu_error.missed_irq_rings = val; | |
4726 | mutex_unlock(&dev->struct_mutex); | |
4727 | ||
4728 | return 0; | |
4729 | } | |
4730 | ||
4731 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4732 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4733 | "0x%08llx\n"); | |
4734 | ||
4735 | static int | |
4736 | i915_ring_test_irq_get(void *data, u64 *val) | |
4737 | { | |
36cdd013 | 4738 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4739 | |
4740 | *val = dev_priv->gpu_error.test_irq_rings; | |
4741 | ||
4742 | return 0; | |
4743 | } | |
4744 | ||
4745 | static int | |
4746 | i915_ring_test_irq_set(void *data, u64 val) | |
4747 | { | |
36cdd013 | 4748 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4749 | |
3a122c27 | 4750 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4751 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4752 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4753 | |
4754 | return 0; | |
4755 | } | |
4756 | ||
4757 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4758 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4759 | "0x%08llx\n"); | |
4760 | ||
dd624afd CW |
4761 | #define DROP_UNBOUND 0x1 |
4762 | #define DROP_BOUND 0x2 | |
4763 | #define DROP_RETIRE 0x4 | |
4764 | #define DROP_ACTIVE 0x8 | |
4765 | #define DROP_ALL (DROP_UNBOUND | \ | |
4766 | DROP_BOUND | \ | |
4767 | DROP_RETIRE | \ | |
4768 | DROP_ACTIVE) | |
647416f9 KC |
4769 | static int |
4770 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4771 | { |
647416f9 | 4772 | *val = DROP_ALL; |
dd624afd | 4773 | |
647416f9 | 4774 | return 0; |
dd624afd CW |
4775 | } |
4776 | ||
647416f9 KC |
4777 | static int |
4778 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4779 | { |
36cdd013 DW |
4780 | struct drm_i915_private *dev_priv = data; |
4781 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4782 | int ret; |
dd624afd | 4783 | |
2f9fe5ff | 4784 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4785 | |
4786 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4787 | * on ioctls on -EAGAIN. */ | |
4788 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4789 | if (ret) | |
4790 | return ret; | |
4791 | ||
4792 | if (val & DROP_ACTIVE) { | |
dcff85c8 | 4793 | ret = i915_gem_wait_for_idle(dev_priv, true); |
dd624afd CW |
4794 | if (ret) |
4795 | goto unlock; | |
4796 | } | |
4797 | ||
4798 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4799 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4800 | |
21ab4e74 CW |
4801 | if (val & DROP_BOUND) |
4802 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4803 | |
21ab4e74 CW |
4804 | if (val & DROP_UNBOUND) |
4805 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4806 | |
4807 | unlock: | |
4808 | mutex_unlock(&dev->struct_mutex); | |
4809 | ||
647416f9 | 4810 | return ret; |
dd624afd CW |
4811 | } |
4812 | ||
647416f9 KC |
4813 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4814 | i915_drop_caches_get, i915_drop_caches_set, | |
4815 | "0x%08llx\n"); | |
dd624afd | 4816 | |
647416f9 KC |
4817 | static int |
4818 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4819 | { |
36cdd013 | 4820 | struct drm_i915_private *dev_priv = data; |
004777cb | 4821 | |
36cdd013 | 4822 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4823 | return -ENODEV; |
4824 | ||
7c59a9c1 | 4825 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4826 | return 0; |
358733e9 JB |
4827 | } |
4828 | ||
647416f9 KC |
4829 | static int |
4830 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4831 | { |
36cdd013 | 4832 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4833 | u32 hw_max, hw_min; |
647416f9 | 4834 | int ret; |
004777cb | 4835 | |
36cdd013 | 4836 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4837 | return -ENODEV; |
358733e9 | 4838 | |
647416f9 | 4839 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4840 | |
4fc688ce | 4841 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4842 | if (ret) |
4843 | return ret; | |
4844 | ||
358733e9 JB |
4845 | /* |
4846 | * Turbo will still be enabled, but won't go above the set value. | |
4847 | */ | |
bc4d91f6 | 4848 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4849 | |
bc4d91f6 AG |
4850 | hw_max = dev_priv->rps.max_freq; |
4851 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4852 | |
b39fb297 | 4853 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4854 | mutex_unlock(&dev_priv->rps.hw_lock); |
4855 | return -EINVAL; | |
0a073b84 JB |
4856 | } |
4857 | ||
b39fb297 | 4858 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4859 | |
dc97997a | 4860 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4861 | |
4fc688ce | 4862 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4863 | |
647416f9 | 4864 | return 0; |
358733e9 JB |
4865 | } |
4866 | ||
647416f9 KC |
4867 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4868 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4869 | "%llu\n"); |
358733e9 | 4870 | |
647416f9 KC |
4871 | static int |
4872 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4873 | { |
36cdd013 | 4874 | struct drm_i915_private *dev_priv = data; |
004777cb | 4875 | |
62e1baa1 | 4876 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4877 | return -ENODEV; |
4878 | ||
7c59a9c1 | 4879 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4880 | return 0; |
1523c310 JB |
4881 | } |
4882 | ||
647416f9 KC |
4883 | static int |
4884 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4885 | { |
36cdd013 | 4886 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4887 | u32 hw_max, hw_min; |
647416f9 | 4888 | int ret; |
004777cb | 4889 | |
62e1baa1 | 4890 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4891 | return -ENODEV; |
1523c310 | 4892 | |
647416f9 | 4893 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4894 | |
4fc688ce | 4895 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4896 | if (ret) |
4897 | return ret; | |
4898 | ||
1523c310 JB |
4899 | /* |
4900 | * Turbo will still be enabled, but won't go below the set value. | |
4901 | */ | |
bc4d91f6 | 4902 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4903 | |
bc4d91f6 AG |
4904 | hw_max = dev_priv->rps.max_freq; |
4905 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4906 | |
36cdd013 DW |
4907 | if (val < hw_min || |
4908 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4909 | mutex_unlock(&dev_priv->rps.hw_lock); |
4910 | return -EINVAL; | |
0a073b84 | 4911 | } |
dd0a1aa1 | 4912 | |
b39fb297 | 4913 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4914 | |
dc97997a | 4915 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4916 | |
4fc688ce | 4917 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4918 | |
647416f9 | 4919 | return 0; |
1523c310 JB |
4920 | } |
4921 | ||
647416f9 KC |
4922 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4923 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4924 | "%llu\n"); |
1523c310 | 4925 | |
647416f9 KC |
4926 | static int |
4927 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4928 | { |
36cdd013 DW |
4929 | struct drm_i915_private *dev_priv = data; |
4930 | struct drm_device *dev = &dev_priv->drm; | |
07b7ddd9 | 4931 | u32 snpcr; |
647416f9 | 4932 | int ret; |
07b7ddd9 | 4933 | |
36cdd013 | 4934 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4935 | return -ENODEV; |
4936 | ||
22bcfc6a DV |
4937 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4938 | if (ret) | |
4939 | return ret; | |
c8c8fb33 | 4940 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4941 | |
07b7ddd9 | 4942 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4943 | |
4944 | intel_runtime_pm_put(dev_priv); | |
36cdd013 | 4945 | mutex_unlock(&dev->struct_mutex); |
07b7ddd9 | 4946 | |
647416f9 | 4947 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4948 | |
647416f9 | 4949 | return 0; |
07b7ddd9 JB |
4950 | } |
4951 | ||
647416f9 KC |
4952 | static int |
4953 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4954 | { |
36cdd013 | 4955 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4956 | u32 snpcr; |
07b7ddd9 | 4957 | |
36cdd013 | 4958 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4959 | return -ENODEV; |
4960 | ||
647416f9 | 4961 | if (val > 3) |
07b7ddd9 JB |
4962 | return -EINVAL; |
4963 | ||
c8c8fb33 | 4964 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4965 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4966 | |
4967 | /* Update the cache sharing policy here as well */ | |
4968 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4969 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4970 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4971 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4972 | ||
c8c8fb33 | 4973 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4974 | return 0; |
07b7ddd9 JB |
4975 | } |
4976 | ||
647416f9 KC |
4977 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4978 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4979 | "%llu\n"); | |
07b7ddd9 | 4980 | |
36cdd013 | 4981 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4982 | struct sseu_dev_info *sseu) |
5d39525a | 4983 | { |
0a0b457f | 4984 | int ss_max = 2; |
5d39525a JM |
4985 | int ss; |
4986 | u32 sig1[ss_max], sig2[ss_max]; | |
4987 | ||
4988 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4989 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4990 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4991 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4992 | ||
4993 | for (ss = 0; ss < ss_max; ss++) { | |
4994 | unsigned int eu_cnt; | |
4995 | ||
4996 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4997 | /* skip disabled subslice */ | |
4998 | continue; | |
4999 | ||
f08a0c92 | 5000 | sseu->slice_mask = BIT(0); |
57ec171e | 5001 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
5002 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
5003 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5004 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5005 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
5006 | sseu->eu_total += eu_cnt; |
5007 | sseu->eu_per_subslice = max_t(unsigned int, | |
5008 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 5009 | } |
5d39525a JM |
5010 | } |
5011 | ||
36cdd013 | 5012 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5013 | struct sseu_dev_info *sseu) |
5d39525a | 5014 | { |
1c046bc1 | 5015 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5016 | int s, ss; |
5017 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5018 | ||
1c046bc1 | 5019 | /* BXT has a single slice and at most 3 subslices. */ |
36cdd013 | 5020 | if (IS_BROXTON(dev_priv)) { |
1c046bc1 JM |
5021 | s_max = 1; |
5022 | ss_max = 3; | |
5023 | } | |
5024 | ||
5025 | for (s = 0; s < s_max; s++) { | |
5026 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5027 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5028 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5029 | } | |
5030 | ||
5d39525a JM |
5031 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5032 | GEN9_PGCTL_SSA_EU19_ACK | | |
5033 | GEN9_PGCTL_SSA_EU210_ACK | | |
5034 | GEN9_PGCTL_SSA_EU311_ACK; | |
5035 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5036 | GEN9_PGCTL_SSB_EU19_ACK | | |
5037 | GEN9_PGCTL_SSB_EU210_ACK | | |
5038 | GEN9_PGCTL_SSB_EU311_ACK; | |
5039 | ||
5040 | for (s = 0; s < s_max; s++) { | |
5041 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
5042 | /* skip disabled slice */ | |
5043 | continue; | |
5044 | ||
f08a0c92 | 5045 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 5046 | |
36cdd013 | 5047 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
5048 | sseu->subslice_mask = |
5049 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 5050 | |
5d39525a JM |
5051 | for (ss = 0; ss < ss_max; ss++) { |
5052 | unsigned int eu_cnt; | |
5053 | ||
57ec171e ID |
5054 | if (IS_BROXTON(dev_priv)) { |
5055 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5056 | /* skip disabled subslice */ | |
5057 | continue; | |
1c046bc1 | 5058 | |
57ec171e ID |
5059 | sseu->subslice_mask |= BIT(ss); |
5060 | } | |
1c046bc1 | 5061 | |
5d39525a JM |
5062 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5063 | eu_mask[ss%2]); | |
915490d5 ID |
5064 | sseu->eu_total += eu_cnt; |
5065 | sseu->eu_per_subslice = max_t(unsigned int, | |
5066 | sseu->eu_per_subslice, | |
5067 | eu_cnt); | |
5d39525a JM |
5068 | } |
5069 | } | |
5070 | } | |
5071 | ||
36cdd013 | 5072 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5073 | struct sseu_dev_info *sseu) |
91bedd34 | 5074 | { |
91bedd34 | 5075 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 5076 | int s; |
91bedd34 | 5077 | |
f08a0c92 | 5078 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 5079 | |
f08a0c92 | 5080 | if (sseu->slice_mask) { |
57ec171e | 5081 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
5082 | sseu->eu_per_subslice = |
5083 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
5084 | sseu->eu_total = sseu->eu_per_subslice * |
5085 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
5086 | |
5087 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 5088 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
5089 | u8 subslice_7eu = |
5090 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 5091 | |
915490d5 | 5092 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
5093 | } |
5094 | } | |
5095 | } | |
5096 | ||
615d8908 ID |
5097 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
5098 | const struct sseu_dev_info *sseu) | |
5099 | { | |
5100 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
5101 | const char *type = is_available_info ? "Available" : "Enabled"; | |
5102 | ||
c67ba538 ID |
5103 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
5104 | sseu->slice_mask); | |
615d8908 | 5105 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 5106 | hweight8(sseu->slice_mask)); |
615d8908 | 5107 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 5108 | sseu_subslice_total(sseu)); |
c67ba538 ID |
5109 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
5110 | sseu->subslice_mask); | |
615d8908 | 5111 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 5112 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
5113 | seq_printf(m, " %s EU Total: %u\n", type, |
5114 | sseu->eu_total); | |
5115 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
5116 | sseu->eu_per_subslice); | |
5117 | ||
5118 | if (!is_available_info) | |
5119 | return; | |
5120 | ||
5121 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
5122 | if (HAS_POOLED_EU(dev_priv)) | |
5123 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
5124 | ||
5125 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5126 | yesno(sseu->has_slice_pg)); | |
5127 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5128 | yesno(sseu->has_subslice_pg)); | |
5129 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5130 | yesno(sseu->has_eu_pg)); | |
5131 | } | |
5132 | ||
3873218f JM |
5133 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5134 | { | |
36cdd013 | 5135 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 5136 | struct sseu_dev_info sseu; |
3873218f | 5137 | |
36cdd013 | 5138 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
5139 | return -ENODEV; |
5140 | ||
5141 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 5142 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 5143 | |
7f992aba | 5144 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 5145 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
5146 | |
5147 | intel_runtime_pm_get(dev_priv); | |
5148 | ||
36cdd013 | 5149 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 5150 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5151 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 5152 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5153 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 5154 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 5155 | } |
238010ed DW |
5156 | |
5157 | intel_runtime_pm_put(dev_priv); | |
5158 | ||
615d8908 | 5159 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 5160 | |
3873218f JM |
5161 | return 0; |
5162 | } | |
5163 | ||
6d794d42 BW |
5164 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5165 | { | |
36cdd013 | 5166 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5167 | |
36cdd013 | 5168 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5169 | return 0; |
5170 | ||
6daccb0b | 5171 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5172 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5173 | |
5174 | return 0; | |
5175 | } | |
5176 | ||
c43b5634 | 5177 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 5178 | { |
36cdd013 | 5179 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5180 | |
36cdd013 | 5181 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5182 | return 0; |
5183 | ||
59bad947 | 5184 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5185 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5186 | |
5187 | return 0; | |
5188 | } | |
5189 | ||
5190 | static const struct file_operations i915_forcewake_fops = { | |
5191 | .owner = THIS_MODULE, | |
5192 | .open = i915_forcewake_open, | |
5193 | .release = i915_forcewake_release, | |
5194 | }; | |
5195 | ||
5196 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5197 | { | |
6d794d42 BW |
5198 | struct dentry *ent; |
5199 | ||
5200 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5201 | S_IRUSR, |
36cdd013 | 5202 | root, to_i915(minor->dev), |
6d794d42 | 5203 | &i915_forcewake_fops); |
f3c5fe97 WY |
5204 | if (!ent) |
5205 | return -ENOMEM; | |
6d794d42 | 5206 | |
8eb57294 | 5207 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5208 | } |
5209 | ||
6a9c308d DV |
5210 | static int i915_debugfs_create(struct dentry *root, |
5211 | struct drm_minor *minor, | |
5212 | const char *name, | |
5213 | const struct file_operations *fops) | |
07b7ddd9 | 5214 | { |
07b7ddd9 JB |
5215 | struct dentry *ent; |
5216 | ||
6a9c308d | 5217 | ent = debugfs_create_file(name, |
07b7ddd9 | 5218 | S_IRUGO | S_IWUSR, |
36cdd013 | 5219 | root, to_i915(minor->dev), |
6a9c308d | 5220 | fops); |
f3c5fe97 WY |
5221 | if (!ent) |
5222 | return -ENOMEM; | |
07b7ddd9 | 5223 | |
6a9c308d | 5224 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5225 | } |
5226 | ||
06c5bf8c | 5227 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5228 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5229 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5230 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 5231 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 5232 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5233 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5234 | {"i915_gem_request", i915_gem_request_info, 0}, |
5235 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5236 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5237 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5238 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5239 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5240 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5241 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5242 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5243 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5244 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5245 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5246 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5247 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5248 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5249 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5250 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5251 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5252 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5253 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5254 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5255 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5256 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5257 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5258 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5259 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5260 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5261 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5262 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5263 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5264 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5265 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5266 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5267 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5268 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5269 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5270 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5271 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5272 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5273 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5274 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5275 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5276 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5277 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5278 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5279 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5280 | }; |
27c202ad | 5281 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5282 | |
06c5bf8c | 5283 | static const struct i915_debugfs_files { |
34b9674c DV |
5284 | const char *name; |
5285 | const struct file_operations *fops; | |
5286 | } i915_debugfs_files[] = { | |
5287 | {"i915_wedged", &i915_wedged_fops}, | |
5288 | {"i915_max_freq", &i915_max_freq_fops}, | |
5289 | {"i915_min_freq", &i915_min_freq_fops}, | |
5290 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5291 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5292 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5293 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5294 | {"i915_error_state", &i915_error_state_fops}, | |
5295 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5296 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5297 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5298 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5299 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5300 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5301 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5302 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5303 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5304 | }; |
5305 | ||
36cdd013 | 5306 | void intel_display_crc_init(struct drm_i915_private *dev_priv) |
07144428 | 5307 | { |
b378360e | 5308 | enum pipe pipe; |
07144428 | 5309 | |
055e393f | 5310 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5311 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5312 | |
d538bbdf DL |
5313 | pipe_crc->opened = false; |
5314 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5315 | init_waitqueue_head(&pipe_crc->wq); |
5316 | } | |
5317 | } | |
5318 | ||
1dac891c | 5319 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5320 | { |
91c8a326 | 5321 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5322 | int ret, i; |
f3cd474b | 5323 | |
6d794d42 | 5324 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5325 | if (ret) |
5326 | return ret; | |
6a9c308d | 5327 | |
07144428 DL |
5328 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5329 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5330 | if (ret) | |
5331 | return ret; | |
5332 | } | |
5333 | ||
34b9674c DV |
5334 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5335 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5336 | i915_debugfs_files[i].name, | |
5337 | i915_debugfs_files[i].fops); | |
5338 | if (ret) | |
5339 | return ret; | |
5340 | } | |
40633219 | 5341 | |
27c202ad BG |
5342 | return drm_debugfs_create_files(i915_debugfs_list, |
5343 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5344 | minor->debugfs_root, minor); |
5345 | } | |
5346 | ||
1dac891c | 5347 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5348 | { |
91c8a326 | 5349 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5350 | int i; |
5351 | ||
27c202ad BG |
5352 | drm_debugfs_remove_files(i915_debugfs_list, |
5353 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5354 | |
36cdd013 | 5355 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 5356 | 1, minor); |
07144428 | 5357 | |
e309a997 | 5358 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5359 | struct drm_info_list *info_list = |
5360 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5361 | ||
5362 | drm_debugfs_remove_files(info_list, 1, minor); | |
5363 | } | |
5364 | ||
34b9674c DV |
5365 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5366 | struct drm_info_list *info_list = | |
36cdd013 | 5367 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
5368 | |
5369 | drm_debugfs_remove_files(info_list, 1, minor); | |
5370 | } | |
2017263e | 5371 | } |
aa7471d2 JN |
5372 | |
5373 | struct dpcd_block { | |
5374 | /* DPCD dump start address. */ | |
5375 | unsigned int offset; | |
5376 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5377 | unsigned int end; | |
5378 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5379 | size_t size; | |
5380 | /* Only valid for eDP. */ | |
5381 | bool edp; | |
5382 | }; | |
5383 | ||
5384 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5385 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5386 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5387 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5388 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5389 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5390 | { .offset = DP_SET_POWER }, | |
5391 | { .offset = DP_EDP_DPCD_REV }, | |
5392 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5393 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5394 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5395 | }; | |
5396 | ||
5397 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5398 | { | |
5399 | struct drm_connector *connector = m->private; | |
5400 | struct intel_dp *intel_dp = | |
5401 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5402 | uint8_t buf[16]; | |
5403 | ssize_t err; | |
5404 | int i; | |
5405 | ||
5c1a8875 MK |
5406 | if (connector->status != connector_status_connected) |
5407 | return -ENODEV; | |
5408 | ||
aa7471d2 JN |
5409 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5410 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5411 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5412 | ||
5413 | if (b->edp && | |
5414 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5415 | continue; | |
5416 | ||
5417 | /* low tech for now */ | |
5418 | if (WARN_ON(size > sizeof(buf))) | |
5419 | continue; | |
5420 | ||
5421 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5422 | if (err <= 0) { | |
5423 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5424 | size, b->offset, err); | |
5425 | continue; | |
5426 | } | |
5427 | ||
5428 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5429 | } |
aa7471d2 JN |
5430 | |
5431 | return 0; | |
5432 | } | |
5433 | ||
5434 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5435 | { | |
5436 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5437 | } | |
5438 | ||
5439 | static const struct file_operations i915_dpcd_fops = { | |
5440 | .owner = THIS_MODULE, | |
5441 | .open = i915_dpcd_open, | |
5442 | .read = seq_read, | |
5443 | .llseek = seq_lseek, | |
5444 | .release = single_release, | |
5445 | }; | |
5446 | ||
ecbd6781 DW |
5447 | static int i915_panel_show(struct seq_file *m, void *data) |
5448 | { | |
5449 | struct drm_connector *connector = m->private; | |
5450 | struct intel_dp *intel_dp = | |
5451 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5452 | ||
5453 | if (connector->status != connector_status_connected) | |
5454 | return -ENODEV; | |
5455 | ||
5456 | seq_printf(m, "Panel power up delay: %d\n", | |
5457 | intel_dp->panel_power_up_delay); | |
5458 | seq_printf(m, "Panel power down delay: %d\n", | |
5459 | intel_dp->panel_power_down_delay); | |
5460 | seq_printf(m, "Backlight on delay: %d\n", | |
5461 | intel_dp->backlight_on_delay); | |
5462 | seq_printf(m, "Backlight off delay: %d\n", | |
5463 | intel_dp->backlight_off_delay); | |
5464 | ||
5465 | return 0; | |
5466 | } | |
5467 | ||
5468 | static int i915_panel_open(struct inode *inode, struct file *file) | |
5469 | { | |
5470 | return single_open(file, i915_panel_show, inode->i_private); | |
5471 | } | |
5472 | ||
5473 | static const struct file_operations i915_panel_fops = { | |
5474 | .owner = THIS_MODULE, | |
5475 | .open = i915_panel_open, | |
5476 | .read = seq_read, | |
5477 | .llseek = seq_lseek, | |
5478 | .release = single_release, | |
5479 | }; | |
5480 | ||
aa7471d2 JN |
5481 | /** |
5482 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5483 | * @connector: pointer to a registered drm_connector | |
5484 | * | |
5485 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5486 | * drm_debugfs_connector_remove(). | |
5487 | * | |
5488 | * Returns 0 on success, negative error codes on error. | |
5489 | */ | |
5490 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5491 | { | |
5492 | struct dentry *root = connector->debugfs_entry; | |
5493 | ||
5494 | /* The connector must have been registered beforehands. */ | |
5495 | if (!root) | |
5496 | return -ENODEV; | |
5497 | ||
5498 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5499 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5500 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5501 | connector, &i915_dpcd_fops); | |
5502 | ||
5503 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5504 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5505 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5506 | |
5507 | return 0; | |
5508 | } |