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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
d92a8cfc | 31 | #include <linux/sched/mm.h> |
4e5359cd | 32 | #include "intel_drv.h" |
a2695744 | 33 | #include "intel_guc_submission.h" |
2017263e | 34 | |
36cdd013 DW |
35 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
36 | { | |
37 | return to_i915(node->minor->dev); | |
38 | } | |
39 | ||
418e3cd8 CW |
40 | static __always_inline void seq_print_param(struct seq_file *m, |
41 | const char *name, | |
42 | const char *type, | |
43 | const void *x) | |
44 | { | |
45 | if (!__builtin_strcmp(type, "bool")) | |
46 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
47 | else if (!__builtin_strcmp(type, "int")) | |
48 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
49 | else if (!__builtin_strcmp(type, "unsigned int")) | |
50 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
51 | else if (!__builtin_strcmp(type, "char *")) |
52 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
53 | else |
54 | BUILD_BUG(); | |
55 | } | |
56 | ||
70d39fe4 CW |
57 | static int i915_capabilities(struct seq_file *m, void *data) |
58 | { | |
36cdd013 DW |
59 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
60 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 61 | |
36cdd013 | 62 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 63 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 65 | |
79fc46df | 66 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 67 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 68 | #undef PRINT_FLAG |
70d39fe4 | 69 | |
418e3cd8 | 70 | kernel_param_lock(THIS_MODULE); |
7075cb85 | 71 | #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x); |
418e3cd8 CW |
72 | I915_PARAMS_FOR_EACH(PRINT_PARAM); |
73 | #undef PRINT_PARAM | |
74 | kernel_param_unlock(THIS_MODULE); | |
75 | ||
70d39fe4 CW |
76 | return 0; |
77 | } | |
2017263e | 78 | |
a7363de7 | 79 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 80 | { |
573adb39 | 81 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
82 | } |
83 | ||
a7363de7 | 84 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b | 85 | { |
bd3d2252 | 86 | return obj->pin_global ? 'p' : ' '; |
be12a86b TU |
87 | } |
88 | ||
a7363de7 | 89 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 90 | { |
3e510a8e | 91 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 92 | default: |
be12a86b TU |
93 | case I915_TILING_NONE: return ' '; |
94 | case I915_TILING_X: return 'X'; | |
95 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 96 | } |
a6172a80 CW |
97 | } |
98 | ||
a7363de7 | 99 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 100 | { |
a65adaf8 | 101 | return obj->userfault_count ? 'g' : ' '; |
be12a86b TU |
102 | } |
103 | ||
a7363de7 | 104 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 105 | { |
a4f5ea64 | 106 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
107 | } |
108 | ||
ca1543be TU |
109 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
110 | { | |
111 | u64 size = 0; | |
112 | struct i915_vma *vma; | |
113 | ||
e2189dd0 CW |
114 | for_each_ggtt_vma(vma, obj) { |
115 | if (drm_mm_node_allocated(&vma->node)) | |
ca1543be TU |
116 | size += vma->node.size; |
117 | } | |
118 | ||
119 | return size; | |
120 | } | |
121 | ||
7393b7ee MA |
122 | static const char * |
123 | stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) | |
124 | { | |
125 | size_t x = 0; | |
126 | ||
127 | switch (page_sizes) { | |
128 | case 0: | |
129 | return ""; | |
130 | case I915_GTT_PAGE_SIZE_4K: | |
131 | return "4K"; | |
132 | case I915_GTT_PAGE_SIZE_64K: | |
133 | return "64K"; | |
134 | case I915_GTT_PAGE_SIZE_2M: | |
135 | return "2M"; | |
136 | default: | |
137 | if (!buf) | |
138 | return "M"; | |
139 | ||
140 | if (page_sizes & I915_GTT_PAGE_SIZE_2M) | |
141 | x += snprintf(buf + x, len - x, "2M, "); | |
142 | if (page_sizes & I915_GTT_PAGE_SIZE_64K) | |
143 | x += snprintf(buf + x, len - x, "64K, "); | |
144 | if (page_sizes & I915_GTT_PAGE_SIZE_4K) | |
145 | x += snprintf(buf + x, len - x, "4K, "); | |
146 | buf[x-2] = '\0'; | |
147 | ||
148 | return buf; | |
149 | } | |
150 | } | |
151 | ||
37811fcc CW |
152 | static void |
153 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
154 | { | |
b4716185 | 155 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 156 | struct intel_engine_cs *engine; |
1d693bcc | 157 | struct i915_vma *vma; |
faf5bf0a | 158 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
159 | int pin_count = 0; |
160 | ||
188c1ab7 CW |
161 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
162 | ||
d07f0e59 | 163 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 164 | &obj->base, |
be12a86b | 165 | get_active_flag(obj), |
37811fcc CW |
166 | get_pin_flag(obj), |
167 | get_tiling_flag(obj), | |
1d693bcc | 168 | get_global_flag(obj), |
be12a86b | 169 | get_pin_mapped_flag(obj), |
a05a5862 | 170 | obj->base.size / 1024, |
37811fcc | 171 | obj->base.read_domains, |
d07f0e59 | 172 | obj->base.write_domain, |
36cdd013 | 173 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
174 | obj->mm.dirty ? " dirty" : "", |
175 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
176 | if (obj->base.name) |
177 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 178 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 179 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 180 | pin_count++; |
ba0635ff DC |
181 | } |
182 | seq_printf(m, " (pinned x %d)", pin_count); | |
bd3d2252 CW |
183 | if (obj->pin_global) |
184 | seq_printf(m, " (global)"); | |
1c7f4bca | 185 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
186 | if (!drm_mm_node_allocated(&vma->node)) |
187 | continue; | |
188 | ||
7393b7ee | 189 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", |
3272db53 | 190 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
7393b7ee MA |
191 | vma->node.start, vma->node.size, |
192 | stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); | |
21976853 CW |
193 | if (i915_vma_is_ggtt(vma)) { |
194 | switch (vma->ggtt_view.type) { | |
195 | case I915_GGTT_VIEW_NORMAL: | |
196 | seq_puts(m, ", normal"); | |
197 | break; | |
198 | ||
199 | case I915_GGTT_VIEW_PARTIAL: | |
200 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
201 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
202 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
203 | break; |
204 | ||
205 | case I915_GGTT_VIEW_ROTATED: | |
206 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
207 | vma->ggtt_view.rotated.plane[0].width, |
208 | vma->ggtt_view.rotated.plane[0].height, | |
209 | vma->ggtt_view.rotated.plane[0].stride, | |
210 | vma->ggtt_view.rotated.plane[0].offset, | |
211 | vma->ggtt_view.rotated.plane[1].width, | |
212 | vma->ggtt_view.rotated.plane[1].height, | |
213 | vma->ggtt_view.rotated.plane[1].stride, | |
214 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
215 | break; |
216 | ||
217 | default: | |
218 | MISSING_CASE(vma->ggtt_view.type); | |
219 | break; | |
220 | } | |
221 | } | |
49ef5294 CW |
222 | if (vma->fence) |
223 | seq_printf(m, " , fence: %d%s", | |
224 | vma->fence->id, | |
225 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 226 | seq_puts(m, ")"); |
1d693bcc | 227 | } |
c1ad11fc | 228 | if (obj->stolen) |
440fd528 | 229 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 230 | |
d07f0e59 | 231 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
232 | if (engine) |
233 | seq_printf(m, " (%s)", engine->name); | |
234 | ||
faf5bf0a CW |
235 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
236 | if (frontbuffer_bits) | |
237 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
238 | } |
239 | ||
e637d2cb | 240 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 241 | { |
e637d2cb CW |
242 | const struct drm_i915_gem_object *a = |
243 | *(const struct drm_i915_gem_object **)A; | |
244 | const struct drm_i915_gem_object *b = | |
245 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 246 | |
2d05fa16 RV |
247 | if (a->stolen->start < b->stolen->start) |
248 | return -1; | |
249 | if (a->stolen->start > b->stolen->start) | |
250 | return 1; | |
251 | return 0; | |
6d2b8885 CW |
252 | } |
253 | ||
254 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
255 | { | |
36cdd013 DW |
256 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
257 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 258 | struct drm_i915_gem_object **objects; |
6d2b8885 | 259 | struct drm_i915_gem_object *obj; |
c44ef60e | 260 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
261 | unsigned long total, count, n; |
262 | int ret; | |
263 | ||
264 | total = READ_ONCE(dev_priv->mm.object_count); | |
2098105e | 265 | objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL); |
e637d2cb CW |
266 | if (!objects) |
267 | return -ENOMEM; | |
6d2b8885 CW |
268 | |
269 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
270 | if (ret) | |
e637d2cb | 271 | goto out; |
6d2b8885 CW |
272 | |
273 | total_obj_size = total_gtt_size = count = 0; | |
f2123818 CW |
274 | |
275 | spin_lock(&dev_priv->mm.obj_lock); | |
276 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
e637d2cb CW |
277 | if (count == total) |
278 | break; | |
279 | ||
6d2b8885 CW |
280 | if (obj->stolen == NULL) |
281 | continue; | |
282 | ||
e637d2cb | 283 | objects[count++] = obj; |
6d2b8885 | 284 | total_obj_size += obj->base.size; |
ca1543be | 285 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 286 | |
6d2b8885 | 287 | } |
f2123818 | 288 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { |
e637d2cb CW |
289 | if (count == total) |
290 | break; | |
291 | ||
6d2b8885 CW |
292 | if (obj->stolen == NULL) |
293 | continue; | |
294 | ||
e637d2cb | 295 | objects[count++] = obj; |
6d2b8885 | 296 | total_obj_size += obj->base.size; |
6d2b8885 | 297 | } |
f2123818 | 298 | spin_unlock(&dev_priv->mm.obj_lock); |
e637d2cb CW |
299 | |
300 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
301 | ||
6d2b8885 | 302 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 303 | for (n = 0; n < count; n++) { |
6d2b8885 | 304 | seq_puts(m, " "); |
e637d2cb | 305 | describe_obj(m, objects[n]); |
6d2b8885 | 306 | seq_putc(m, '\n'); |
6d2b8885 | 307 | } |
e637d2cb | 308 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 309 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
310 | |
311 | mutex_unlock(&dev->struct_mutex); | |
312 | out: | |
2098105e | 313 | kvfree(objects); |
e637d2cb | 314 | return ret; |
6d2b8885 CW |
315 | } |
316 | ||
2db8e9d6 | 317 | struct file_stats { |
6313c204 | 318 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
319 | unsigned long count; |
320 | u64 total, unbound; | |
321 | u64 global, shared; | |
322 | u64 active, inactive; | |
2db8e9d6 CW |
323 | }; |
324 | ||
325 | static int per_file_stats(int id, void *ptr, void *data) | |
326 | { | |
327 | struct drm_i915_gem_object *obj = ptr; | |
328 | struct file_stats *stats = data; | |
6313c204 | 329 | struct i915_vma *vma; |
2db8e9d6 | 330 | |
0caf81b5 CW |
331 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
332 | ||
2db8e9d6 CW |
333 | stats->count++; |
334 | stats->total += obj->base.size; | |
15717de2 CW |
335 | if (!obj->bind_count) |
336 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
337 | if (obj->base.name || obj->base.dma_buf) |
338 | stats->shared += obj->base.size; | |
339 | ||
894eeecc CW |
340 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
341 | if (!drm_mm_node_allocated(&vma->node)) | |
342 | continue; | |
6313c204 | 343 | |
3272db53 | 344 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
345 | stats->global += vma->node.size; |
346 | } else { | |
347 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 348 | |
2bfa996e | 349 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 350 | continue; |
6313c204 | 351 | } |
894eeecc | 352 | |
b0decaf7 | 353 | if (i915_vma_is_active(vma)) |
894eeecc CW |
354 | stats->active += vma->node.size; |
355 | else | |
356 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
357 | } |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
b0da1b79 CW |
362 | #define print_file_stats(m, name, stats) do { \ |
363 | if (stats.count) \ | |
c44ef60e | 364 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
365 | name, \ |
366 | stats.count, \ | |
367 | stats.total, \ | |
368 | stats.active, \ | |
369 | stats.inactive, \ | |
370 | stats.global, \ | |
371 | stats.shared, \ | |
372 | stats.unbound); \ | |
373 | } while (0) | |
493018dc BV |
374 | |
375 | static void print_batch_pool_stats(struct seq_file *m, | |
376 | struct drm_i915_private *dev_priv) | |
377 | { | |
378 | struct drm_i915_gem_object *obj; | |
379 | struct file_stats stats; | |
e2f80391 | 380 | struct intel_engine_cs *engine; |
3b3f1650 | 381 | enum intel_engine_id id; |
b4ac5afc | 382 | int j; |
493018dc BV |
383 | |
384 | memset(&stats, 0, sizeof(stats)); | |
385 | ||
3b3f1650 | 386 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 387 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 388 | list_for_each_entry(obj, |
e2f80391 | 389 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
390 | batch_pool_link) |
391 | per_file_stats(0, obj, &stats); | |
392 | } | |
06fbca71 | 393 | } |
493018dc | 394 | |
b0da1b79 | 395 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
396 | } |
397 | ||
15da9565 CW |
398 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
399 | { | |
400 | struct i915_gem_context *ctx = ptr; | |
401 | int n; | |
402 | ||
403 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
404 | if (ctx->engine[n].state) | |
bf3783e5 | 405 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 406 | if (ctx->engine[n].ring) |
57e88531 | 407 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
408 | } |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static void print_context_stats(struct seq_file *m, | |
414 | struct drm_i915_private *dev_priv) | |
415 | { | |
36cdd013 | 416 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
417 | struct file_stats stats; |
418 | struct drm_file *file; | |
419 | ||
420 | memset(&stats, 0, sizeof(stats)); | |
421 | ||
36cdd013 | 422 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
423 | if (dev_priv->kernel_context) |
424 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
425 | ||
36cdd013 | 426 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
427 | struct drm_i915_file_private *fpriv = file->driver_priv; |
428 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
429 | } | |
36cdd013 | 430 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
431 | |
432 | print_file_stats(m, "[k]contexts", stats); | |
433 | } | |
434 | ||
36cdd013 | 435 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 436 | { |
36cdd013 DW |
437 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
438 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 439 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7393b7ee MA |
440 | u32 count, mapped_count, purgeable_count, dpy_count, huge_count; |
441 | u64 size, mapped_size, purgeable_size, dpy_size, huge_size; | |
6299f992 | 442 | struct drm_i915_gem_object *obj; |
7393b7ee | 443 | unsigned int page_sizes = 0; |
2db8e9d6 | 444 | struct drm_file *file; |
7393b7ee | 445 | char buf[80]; |
73aa808f CW |
446 | int ret; |
447 | ||
448 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
449 | if (ret) | |
450 | return ret; | |
451 | ||
3ef7f228 | 452 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
453 | dev_priv->mm.object_count, |
454 | dev_priv->mm.object_memory); | |
455 | ||
1544c42e CW |
456 | size = count = 0; |
457 | mapped_size = mapped_count = 0; | |
458 | purgeable_size = purgeable_count = 0; | |
7393b7ee | 459 | huge_size = huge_count = 0; |
f2123818 CW |
460 | |
461 | spin_lock(&dev_priv->mm.obj_lock); | |
462 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { | |
2bd160a1 CW |
463 | size += obj->base.size; |
464 | ++count; | |
465 | ||
a4f5ea64 | 466 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
467 | purgeable_size += obj->base.size; |
468 | ++purgeable_count; | |
469 | } | |
470 | ||
a4f5ea64 | 471 | if (obj->mm.mapping) { |
2bd160a1 CW |
472 | mapped_count++; |
473 | mapped_size += obj->base.size; | |
be19b10d | 474 | } |
7393b7ee MA |
475 | |
476 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
477 | huge_count++; | |
478 | huge_size += obj->base.size; | |
479 | page_sizes |= obj->mm.page_sizes.sg; | |
480 | } | |
b7abb714 | 481 | } |
c44ef60e | 482 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 483 | |
2bd160a1 | 484 | size = count = dpy_size = dpy_count = 0; |
f2123818 | 485 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { |
2bd160a1 CW |
486 | size += obj->base.size; |
487 | ++count; | |
488 | ||
bd3d2252 | 489 | if (obj->pin_global) { |
2bd160a1 CW |
490 | dpy_size += obj->base.size; |
491 | ++dpy_count; | |
6299f992 | 492 | } |
2bd160a1 | 493 | |
a4f5ea64 | 494 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
495 | purgeable_size += obj->base.size; |
496 | ++purgeable_count; | |
497 | } | |
2bd160a1 | 498 | |
a4f5ea64 | 499 | if (obj->mm.mapping) { |
2bd160a1 CW |
500 | mapped_count++; |
501 | mapped_size += obj->base.size; | |
be19b10d | 502 | } |
7393b7ee MA |
503 | |
504 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
505 | huge_count++; | |
506 | huge_size += obj->base.size; | |
507 | page_sizes |= obj->mm.page_sizes.sg; | |
508 | } | |
6299f992 | 509 | } |
f2123818 CW |
510 | spin_unlock(&dev_priv->mm.obj_lock); |
511 | ||
2bd160a1 CW |
512 | seq_printf(m, "%u bound objects, %llu bytes\n", |
513 | count, size); | |
c44ef60e | 514 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 515 | purgeable_count, purgeable_size); |
2bd160a1 CW |
516 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
517 | mapped_count, mapped_size); | |
7393b7ee MA |
518 | seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n", |
519 | huge_count, | |
520 | stringify_page_sizes(page_sizes, buf, sizeof(buf)), | |
521 | huge_size); | |
bd3d2252 | 522 | seq_printf(m, "%u display objects (globally pinned), %llu bytes\n", |
2bd160a1 | 523 | dpy_count, dpy_size); |
6299f992 | 524 | |
b7128ef1 MA |
525 | seq_printf(m, "%llu [%pa] gtt total\n", |
526 | ggtt->base.total, &ggtt->mappable_end); | |
7393b7ee MA |
527 | seq_printf(m, "Supported page sizes: %s\n", |
528 | stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, | |
529 | buf, sizeof(buf))); | |
73aa808f | 530 | |
493018dc BV |
531 | seq_putc(m, '\n'); |
532 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
533 | mutex_unlock(&dev->struct_mutex); |
534 | ||
535 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 536 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
537 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
538 | struct file_stats stats; | |
c84455b4 CW |
539 | struct drm_i915_file_private *file_priv = file->driver_priv; |
540 | struct drm_i915_gem_request *request; | |
3ec2f427 | 541 | struct task_struct *task; |
2db8e9d6 | 542 | |
0caf81b5 CW |
543 | mutex_lock(&dev->struct_mutex); |
544 | ||
2db8e9d6 | 545 | memset(&stats, 0, sizeof(stats)); |
6313c204 | 546 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 547 | spin_lock(&file->table_lock); |
2db8e9d6 | 548 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 549 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
550 | /* |
551 | * Although we have a valid reference on file->pid, that does | |
552 | * not guarantee that the task_struct who called get_pid() is | |
553 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
554 | * Therefore, we need to protect this ->comm access using RCU. | |
555 | */ | |
c84455b4 CW |
556 | request = list_first_entry_or_null(&file_priv->mm.request_list, |
557 | struct drm_i915_gem_request, | |
c8659efa | 558 | client_link); |
3ec2f427 | 559 | rcu_read_lock(); |
c84455b4 CW |
560 | task = pid_task(request && request->ctx->pid ? |
561 | request->ctx->pid : file->pid, | |
562 | PIDTYPE_PID); | |
493018dc | 563 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 564 | rcu_read_unlock(); |
0caf81b5 | 565 | |
c84455b4 | 566 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 567 | } |
1d2ac403 | 568 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
569 | |
570 | return 0; | |
571 | } | |
572 | ||
aee56cff | 573 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 574 | { |
9f25d007 | 575 | struct drm_info_node *node = m->private; |
36cdd013 DW |
576 | struct drm_i915_private *dev_priv = node_to_i915(node); |
577 | struct drm_device *dev = &dev_priv->drm; | |
f2123818 | 578 | struct drm_i915_gem_object **objects; |
08c18323 | 579 | struct drm_i915_gem_object *obj; |
c44ef60e | 580 | u64 total_obj_size, total_gtt_size; |
f2123818 | 581 | unsigned long nobject, n; |
08c18323 CW |
582 | int count, ret; |
583 | ||
f2123818 CW |
584 | nobject = READ_ONCE(dev_priv->mm.object_count); |
585 | objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL); | |
586 | if (!objects) | |
587 | return -ENOMEM; | |
588 | ||
08c18323 CW |
589 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
590 | if (ret) | |
591 | return ret; | |
592 | ||
f2123818 CW |
593 | count = 0; |
594 | spin_lock(&dev_priv->mm.obj_lock); | |
595 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
596 | objects[count++] = obj; | |
597 | if (count == nobject) | |
598 | break; | |
599 | } | |
600 | spin_unlock(&dev_priv->mm.obj_lock); | |
601 | ||
602 | total_obj_size = total_gtt_size = 0; | |
603 | for (n = 0; n < count; n++) { | |
604 | obj = objects[n]; | |
605 | ||
267f0c90 | 606 | seq_puts(m, " "); |
08c18323 | 607 | describe_obj(m, obj); |
267f0c90 | 608 | seq_putc(m, '\n'); |
08c18323 | 609 | total_obj_size += obj->base.size; |
ca1543be | 610 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
611 | } |
612 | ||
613 | mutex_unlock(&dev->struct_mutex); | |
614 | ||
c44ef60e | 615 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 | 616 | count, total_obj_size, total_gtt_size); |
f2123818 | 617 | kvfree(objects); |
08c18323 CW |
618 | |
619 | return 0; | |
620 | } | |
621 | ||
493018dc BV |
622 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
623 | { | |
36cdd013 DW |
624 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
625 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 626 | struct drm_i915_gem_object *obj; |
e2f80391 | 627 | struct intel_engine_cs *engine; |
3b3f1650 | 628 | enum intel_engine_id id; |
8d9d5744 | 629 | int total = 0; |
b4ac5afc | 630 | int ret, j; |
493018dc BV |
631 | |
632 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
633 | if (ret) | |
634 | return ret; | |
635 | ||
3b3f1650 | 636 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 637 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
638 | int count; |
639 | ||
640 | count = 0; | |
641 | list_for_each_entry(obj, | |
e2f80391 | 642 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
643 | batch_pool_link) |
644 | count++; | |
645 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 646 | engine->name, j, count); |
8d9d5744 CW |
647 | |
648 | list_for_each_entry(obj, | |
e2f80391 | 649 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
650 | batch_pool_link) { |
651 | seq_puts(m, " "); | |
652 | describe_obj(m, obj); | |
653 | seq_putc(m, '\n'); | |
654 | } | |
655 | ||
656 | total += count; | |
06fbca71 | 657 | } |
493018dc BV |
658 | } |
659 | ||
8d9d5744 | 660 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
661 | |
662 | mutex_unlock(&dev->struct_mutex); | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
2017263e BG |
667 | static int i915_interrupt_info(struct seq_file *m, void *data) |
668 | { | |
36cdd013 | 669 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 670 | struct intel_engine_cs *engine; |
3b3f1650 | 671 | enum intel_engine_id id; |
4bb05040 | 672 | int i, pipe; |
de227ef0 | 673 | |
c8c8fb33 | 674 | intel_runtime_pm_get(dev_priv); |
2017263e | 675 | |
36cdd013 | 676 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
677 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
678 | I915_READ(GEN8_MASTER_IRQ)); | |
679 | ||
680 | seq_printf(m, "Display IER:\t%08x\n", | |
681 | I915_READ(VLV_IER)); | |
682 | seq_printf(m, "Display IIR:\t%08x\n", | |
683 | I915_READ(VLV_IIR)); | |
684 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
685 | I915_READ(VLV_IIR_RW)); | |
686 | seq_printf(m, "Display IMR:\t%08x\n", | |
687 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
688 | for_each_pipe(dev_priv, pipe) { |
689 | enum intel_display_power_domain power_domain; | |
690 | ||
691 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
692 | if (!intel_display_power_get_if_enabled(dev_priv, | |
693 | power_domain)) { | |
694 | seq_printf(m, "Pipe %c power disabled\n", | |
695 | pipe_name(pipe)); | |
696 | continue; | |
697 | } | |
698 | ||
74e1ca8c VS |
699 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
700 | pipe_name(pipe), | |
701 | I915_READ(PIPESTAT(pipe))); | |
702 | ||
9c870d03 CW |
703 | intel_display_power_put(dev_priv, power_domain); |
704 | } | |
705 | ||
706 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
707 | seq_printf(m, "Port hotplug:\t%08x\n", |
708 | I915_READ(PORT_HOTPLUG_EN)); | |
709 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
710 | I915_READ(VLV_DPFLIPSTAT)); | |
711 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
712 | I915_READ(DPINVGTT)); | |
9c870d03 | 713 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
714 | |
715 | for (i = 0; i < 4; i++) { | |
716 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
717 | i, I915_READ(GEN8_GT_IMR(i))); | |
718 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
719 | i, I915_READ(GEN8_GT_IIR(i))); | |
720 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
721 | i, I915_READ(GEN8_GT_IER(i))); | |
722 | } | |
723 | ||
724 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
725 | I915_READ(GEN8_PCU_IMR)); | |
726 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
727 | I915_READ(GEN8_PCU_IIR)); | |
728 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
729 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 730 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
731 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
732 | I915_READ(GEN8_MASTER_IRQ)); | |
733 | ||
734 | for (i = 0; i < 4; i++) { | |
735 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
736 | i, I915_READ(GEN8_GT_IMR(i))); | |
737 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
738 | i, I915_READ(GEN8_GT_IIR(i))); | |
739 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
740 | i, I915_READ(GEN8_GT_IER(i))); | |
741 | } | |
742 | ||
055e393f | 743 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
744 | enum intel_display_power_domain power_domain; |
745 | ||
746 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
747 | if (!intel_display_power_get_if_enabled(dev_priv, | |
748 | power_domain)) { | |
22c59960 PZ |
749 | seq_printf(m, "Pipe %c power disabled\n", |
750 | pipe_name(pipe)); | |
751 | continue; | |
752 | } | |
a123f157 | 753 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
754 | pipe_name(pipe), |
755 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 756 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
757 | pipe_name(pipe), |
758 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 759 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
760 | pipe_name(pipe), |
761 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
762 | |
763 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
764 | } |
765 | ||
766 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
767 | I915_READ(GEN8_DE_PORT_IMR)); | |
768 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
769 | I915_READ(GEN8_DE_PORT_IIR)); | |
770 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
771 | I915_READ(GEN8_DE_PORT_IER)); | |
772 | ||
773 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
774 | I915_READ(GEN8_DE_MISC_IMR)); | |
775 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
776 | I915_READ(GEN8_DE_MISC_IIR)); | |
777 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
778 | I915_READ(GEN8_DE_MISC_IER)); | |
779 | ||
780 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
781 | I915_READ(GEN8_PCU_IMR)); | |
782 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
783 | I915_READ(GEN8_PCU_IIR)); | |
784 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
785 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 786 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
787 | seq_printf(m, "Display IER:\t%08x\n", |
788 | I915_READ(VLV_IER)); | |
789 | seq_printf(m, "Display IIR:\t%08x\n", | |
790 | I915_READ(VLV_IIR)); | |
791 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
792 | I915_READ(VLV_IIR_RW)); | |
793 | seq_printf(m, "Display IMR:\t%08x\n", | |
794 | I915_READ(VLV_IMR)); | |
4f4631af CW |
795 | for_each_pipe(dev_priv, pipe) { |
796 | enum intel_display_power_domain power_domain; | |
797 | ||
798 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
799 | if (!intel_display_power_get_if_enabled(dev_priv, | |
800 | power_domain)) { | |
801 | seq_printf(m, "Pipe %c power disabled\n", | |
802 | pipe_name(pipe)); | |
803 | continue; | |
804 | } | |
805 | ||
7e231dbe JB |
806 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
807 | pipe_name(pipe), | |
808 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
809 | intel_display_power_put(dev_priv, power_domain); |
810 | } | |
7e231dbe JB |
811 | |
812 | seq_printf(m, "Master IER:\t%08x\n", | |
813 | I915_READ(VLV_MASTER_IER)); | |
814 | ||
815 | seq_printf(m, "Render IER:\t%08x\n", | |
816 | I915_READ(GTIER)); | |
817 | seq_printf(m, "Render IIR:\t%08x\n", | |
818 | I915_READ(GTIIR)); | |
819 | seq_printf(m, "Render IMR:\t%08x\n", | |
820 | I915_READ(GTIMR)); | |
821 | ||
822 | seq_printf(m, "PM IER:\t\t%08x\n", | |
823 | I915_READ(GEN6_PMIER)); | |
824 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
825 | I915_READ(GEN6_PMIIR)); | |
826 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
827 | I915_READ(GEN6_PMIMR)); | |
828 | ||
829 | seq_printf(m, "Port hotplug:\t%08x\n", | |
830 | I915_READ(PORT_HOTPLUG_EN)); | |
831 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
832 | I915_READ(VLV_DPFLIPSTAT)); | |
833 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
834 | I915_READ(DPINVGTT)); | |
835 | ||
36cdd013 | 836 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
837 | seq_printf(m, "Interrupt enable: %08x\n", |
838 | I915_READ(IER)); | |
839 | seq_printf(m, "Interrupt identity: %08x\n", | |
840 | I915_READ(IIR)); | |
841 | seq_printf(m, "Interrupt mask: %08x\n", | |
842 | I915_READ(IMR)); | |
055e393f | 843 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
844 | seq_printf(m, "Pipe %c stat: %08x\n", |
845 | pipe_name(pipe), | |
846 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
847 | } else { |
848 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
849 | I915_READ(DEIER)); | |
850 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
851 | I915_READ(DEIIR)); | |
852 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
853 | I915_READ(DEIMR)); | |
854 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
855 | I915_READ(SDEIER)); | |
856 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
857 | I915_READ(SDEIIR)); | |
858 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
859 | I915_READ(SDEIMR)); | |
860 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
861 | I915_READ(GTIER)); | |
862 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
863 | I915_READ(GTIIR)); | |
864 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
865 | I915_READ(GTIMR)); | |
866 | } | |
d5acadfe CW |
867 | if (INTEL_GEN(dev_priv) >= 6) { |
868 | for_each_engine(engine, dev_priv, id) { | |
a2c7f6fd CW |
869 | seq_printf(m, |
870 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 871 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 872 | } |
9862e600 | 873 | } |
c8c8fb33 | 874 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 875 | |
2017263e BG |
876 | return 0; |
877 | } | |
878 | ||
a6172a80 CW |
879 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
880 | { | |
36cdd013 DW |
881 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
882 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
883 | int i, ret; |
884 | ||
885 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
886 | if (ret) | |
887 | return ret; | |
a6172a80 | 888 | |
a6172a80 CW |
889 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
890 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 891 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 892 | |
6c085a72 CW |
893 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
894 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 895 | if (!vma) |
267f0c90 | 896 | seq_puts(m, "unused"); |
c2c347a9 | 897 | else |
49ef5294 | 898 | describe_obj(m, vma->obj); |
267f0c90 | 899 | seq_putc(m, '\n'); |
a6172a80 CW |
900 | } |
901 | ||
05394f39 | 902 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
903 | return 0; |
904 | } | |
905 | ||
98a2f411 | 906 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
907 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
908 | size_t count, loff_t *pos) | |
d5442303 | 909 | { |
5a4c6f1b CW |
910 | struct i915_gpu_state *error = file->private_data; |
911 | struct drm_i915_error_state_buf str; | |
912 | ssize_t ret; | |
913 | loff_t tmp; | |
d5442303 | 914 | |
5a4c6f1b CW |
915 | if (!error) |
916 | return 0; | |
d5442303 | 917 | |
5a4c6f1b CW |
918 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
919 | if (ret) | |
920 | return ret; | |
d5442303 | 921 | |
5a4c6f1b CW |
922 | ret = i915_error_state_to_str(&str, error); |
923 | if (ret) | |
924 | goto out; | |
d5442303 | 925 | |
5a4c6f1b CW |
926 | tmp = 0; |
927 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
928 | if (ret < 0) | |
929 | goto out; | |
d5442303 | 930 | |
5a4c6f1b CW |
931 | *pos = str.start + ret; |
932 | out: | |
933 | i915_error_state_buf_release(&str); | |
934 | return ret; | |
935 | } | |
edc3d884 | 936 | |
5a4c6f1b CW |
937 | static int gpu_state_release(struct inode *inode, struct file *file) |
938 | { | |
939 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 940 | return 0; |
d5442303 DV |
941 | } |
942 | ||
5a4c6f1b | 943 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 944 | { |
090e5fe3 | 945 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 946 | struct i915_gpu_state *gpu; |
d5442303 | 947 | |
090e5fe3 CW |
948 | intel_runtime_pm_get(i915); |
949 | gpu = i915_capture_gpu_state(i915); | |
950 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
951 | if (!gpu) |
952 | return -ENOMEM; | |
d5442303 | 953 | |
5a4c6f1b | 954 | file->private_data = gpu; |
edc3d884 MK |
955 | return 0; |
956 | } | |
957 | ||
5a4c6f1b CW |
958 | static const struct file_operations i915_gpu_info_fops = { |
959 | .owner = THIS_MODULE, | |
960 | .open = i915_gpu_info_open, | |
961 | .read = gpu_state_read, | |
962 | .llseek = default_llseek, | |
963 | .release = gpu_state_release, | |
964 | }; | |
965 | ||
966 | static ssize_t | |
967 | i915_error_state_write(struct file *filp, | |
968 | const char __user *ubuf, | |
969 | size_t cnt, | |
970 | loff_t *ppos) | |
4dc955f7 | 971 | { |
5a4c6f1b | 972 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 973 | |
5a4c6f1b CW |
974 | if (!error) |
975 | return 0; | |
edc3d884 | 976 | |
5a4c6f1b CW |
977 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
978 | i915_reset_error_state(error->i915); | |
edc3d884 | 979 | |
5a4c6f1b CW |
980 | return cnt; |
981 | } | |
edc3d884 | 982 | |
5a4c6f1b CW |
983 | static int i915_error_state_open(struct inode *inode, struct file *file) |
984 | { | |
985 | file->private_data = i915_first_error_state(inode->i_private); | |
986 | return 0; | |
d5442303 DV |
987 | } |
988 | ||
989 | static const struct file_operations i915_error_state_fops = { | |
990 | .owner = THIS_MODULE, | |
991 | .open = i915_error_state_open, | |
5a4c6f1b | 992 | .read = gpu_state_read, |
d5442303 DV |
993 | .write = i915_error_state_write, |
994 | .llseek = default_llseek, | |
5a4c6f1b | 995 | .release = gpu_state_release, |
d5442303 | 996 | }; |
98a2f411 CW |
997 | #endif |
998 | ||
647416f9 KC |
999 | static int |
1000 | i915_next_seqno_set(void *data, u64 val) | |
1001 | { | |
36cdd013 DW |
1002 | struct drm_i915_private *dev_priv = data; |
1003 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1004 | int ret; |
1005 | ||
40633219 MK |
1006 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1007 | if (ret) | |
1008 | return ret; | |
1009 | ||
73cb9701 | 1010 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1011 | mutex_unlock(&dev->struct_mutex); |
1012 | ||
647416f9 | 1013 | return ret; |
40633219 MK |
1014 | } |
1015 | ||
647416f9 | 1016 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1017 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1018 | "0x%llx\n"); |
40633219 | 1019 | |
adb4bd12 | 1020 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1021 | { |
36cdd013 | 1022 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1023 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
c8c8fb33 PZ |
1024 | int ret = 0; |
1025 | ||
1026 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1027 | |
36cdd013 | 1028 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1029 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1030 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1031 | ||
1032 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1033 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1034 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1035 | MEMSTAT_VID_SHIFT); | |
1036 | seq_printf(m, "Current P-state: %d\n", | |
1037 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1038 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
0d6fc92a | 1039 | u32 rpmodectl, freq_sts; |
666a4537 | 1040 | |
9f817501 | 1041 | mutex_lock(&dev_priv->pcu_lock); |
0d6fc92a SAK |
1042 | |
1043 | rpmodectl = I915_READ(GEN6_RP_CONTROL); | |
1044 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1045 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1046 | seq_printf(m, "HW control enabled: %s\n", | |
1047 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1048 | seq_printf(m, "SW control enabled: %s\n", | |
1049 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1050 | GEN6_RP_MEDIA_SW_MODE)); | |
1051 | ||
666a4537 WB |
1052 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
1053 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1054 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1055 | ||
1056 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1057 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1058 | ||
1059 | seq_printf(m, "current GPU freq: %d MHz\n", | |
562d9bae | 1060 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
666a4537 WB |
1061 | |
1062 | seq_printf(m, "max GPU freq: %d MHz\n", | |
562d9bae | 1063 | intel_gpu_freq(dev_priv, rps->max_freq)); |
666a4537 WB |
1064 | |
1065 | seq_printf(m, "min GPU freq: %d MHz\n", | |
562d9bae | 1066 | intel_gpu_freq(dev_priv, rps->min_freq)); |
666a4537 WB |
1067 | |
1068 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
562d9bae | 1069 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
666a4537 WB |
1070 | |
1071 | seq_printf(m, | |
1072 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1073 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
9f817501 | 1074 | mutex_unlock(&dev_priv->pcu_lock); |
36cdd013 | 1075 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1076 | u32 rp_state_limits; |
1077 | u32 gt_perf_status; | |
1078 | u32 rp_state_cap; | |
0d8f9491 | 1079 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1080 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1081 | u32 rpupei, rpcurup, rpprevup; |
1082 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1083 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1084 | int max_freq; |
1085 | ||
35040562 | 1086 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1087 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1088 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1089 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1090 | } else { | |
1091 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1092 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1093 | } | |
1094 | ||
3b8d8d91 | 1095 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1096 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1097 | |
8e8c06cd | 1098 | reqf = I915_READ(GEN6_RPNSWREQ); |
35ceabf3 | 1099 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b AG |
1100 | reqf >>= 23; |
1101 | else { | |
1102 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1103 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1104 | reqf >>= 24; |
1105 | else | |
1106 | reqf >>= 25; | |
1107 | } | |
7c59a9c1 | 1108 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1109 | |
0d8f9491 CW |
1110 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1111 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1112 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1113 | ||
ccab5c82 | 1114 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1115 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1116 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1117 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1118 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1119 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1120 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
c84b2705 TU |
1121 | cagf = intel_gpu_freq(dev_priv, |
1122 | intel_get_cagf(dev_priv, rpstat)); | |
ccab5c82 | 1123 | |
59bad947 | 1124 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1125 | |
36cdd013 | 1126 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1127 | pm_ier = I915_READ(GEN6_PMIER); |
1128 | pm_imr = I915_READ(GEN6_PMIMR); | |
1129 | pm_isr = I915_READ(GEN6_PMISR); | |
1130 | pm_iir = I915_READ(GEN6_PMIIR); | |
1131 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1132 | } else { | |
1133 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1134 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1135 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1136 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1137 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1138 | } | |
960e5465 SAK |
1139 | seq_printf(m, "Video Turbo Mode: %s\n", |
1140 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1141 | seq_printf(m, "HW control enabled: %s\n", | |
1142 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1143 | seq_printf(m, "SW control enabled: %s\n", | |
1144 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1145 | GEN6_RP_MEDIA_SW_MODE)); | |
0d8f9491 | 1146 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1147 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 | 1148 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
562d9bae | 1149 | rps->pm_intrmsk_mbz); |
3b8d8d91 | 1150 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1151 | seq_printf(m, "Render p-state ratio: %d\n", |
35ceabf3 | 1152 | (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1153 | seq_printf(m, "Render p-state VID: %d\n", |
1154 | gt_perf_status & 0xff); | |
1155 | seq_printf(m, "Render p-state limit: %d\n", | |
1156 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1157 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1158 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1159 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1160 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1161 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1162 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1163 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1164 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1165 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1166 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1167 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1168 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
562d9bae | 1169 | seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold); |
d86ed34a | 1170 | |
d6cda9c7 AG |
1171 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1172 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1173 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1174 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1175 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1176 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
562d9bae | 1177 | seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold); |
3b8d8d91 | 1178 | |
cc3f90f0 | 1179 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1180 | rp_state_cap >> 16) & 0xff; |
35ceabf3 RV |
1181 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1182 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1183 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1184 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1185 | |
1186 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
35ceabf3 RV |
1187 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1188 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1189 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1190 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1191 | |
cc3f90f0 | 1192 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1193 | rp_state_cap >> 0) & 0xff; |
35ceabf3 RV |
1194 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1195 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1196 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1197 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1198 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
562d9bae | 1199 | intel_gpu_freq(dev_priv, rps->max_freq)); |
aed242ff | 1200 | |
d86ed34a | 1201 | seq_printf(m, "Current freq: %d MHz\n", |
562d9bae | 1202 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
d86ed34a | 1203 | seq_printf(m, "Actual freq: %d MHz\n", cagf); |
aed242ff | 1204 | seq_printf(m, "Idle freq: %d MHz\n", |
562d9bae | 1205 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
d86ed34a | 1206 | seq_printf(m, "Min freq: %d MHz\n", |
562d9bae | 1207 | intel_gpu_freq(dev_priv, rps->min_freq)); |
29ecd78d | 1208 | seq_printf(m, "Boost freq: %d MHz\n", |
562d9bae | 1209 | intel_gpu_freq(dev_priv, rps->boost_freq)); |
d86ed34a | 1210 | seq_printf(m, "Max freq: %d MHz\n", |
562d9bae | 1211 | intel_gpu_freq(dev_priv, rps->max_freq)); |
d86ed34a CW |
1212 | seq_printf(m, |
1213 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1214 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
3b8d8d91 | 1215 | } else { |
267f0c90 | 1216 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1217 | } |
f97108d1 | 1218 | |
49cd97a3 | 1219 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1220 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1221 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1222 | ||
c8c8fb33 PZ |
1223 | intel_runtime_pm_put(dev_priv); |
1224 | return ret; | |
f97108d1 JB |
1225 | } |
1226 | ||
d636951e BW |
1227 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1228 | struct seq_file *m, | |
1229 | struct intel_instdone *instdone) | |
1230 | { | |
f9e61372 BW |
1231 | int slice; |
1232 | int subslice; | |
1233 | ||
d636951e BW |
1234 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1235 | instdone->instdone); | |
1236 | ||
1237 | if (INTEL_GEN(dev_priv) <= 3) | |
1238 | return; | |
1239 | ||
1240 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1241 | instdone->slice_common); | |
1242 | ||
1243 | if (INTEL_GEN(dev_priv) <= 6) | |
1244 | return; | |
1245 | ||
f9e61372 BW |
1246 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1247 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1248 | slice, subslice, instdone->sampler[slice][subslice]); | |
1249 | ||
1250 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1251 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1252 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1253 | } |
1254 | ||
f654449a CW |
1255 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1256 | { | |
36cdd013 | 1257 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1258 | struct intel_engine_cs *engine; |
666796da TU |
1259 | u64 acthd[I915_NUM_ENGINES]; |
1260 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1261 | struct intel_instdone instdone; |
c3232b18 | 1262 | enum intel_engine_id id; |
f654449a | 1263 | |
8af29b0c | 1264 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1265 | seq_puts(m, "Wedged\n"); |
1266 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1267 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1268 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1269 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1270 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1271 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1272 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1273 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1274 | |
4f044a88 | 1275 | if (!i915_modparams.enable_hangcheck) { |
8c185eca | 1276 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1277 | return 0; |
1278 | } | |
1279 | ||
ebbc7546 MK |
1280 | intel_runtime_pm_get(dev_priv); |
1281 | ||
3b3f1650 | 1282 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1283 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1284 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1285 | } |
1286 | ||
3b3f1650 | 1287 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1288 | |
ebbc7546 MK |
1289 | intel_runtime_pm_put(dev_priv); |
1290 | ||
8352aea3 CW |
1291 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1292 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1293 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1294 | jiffies)); | |
8352aea3 CW |
1295 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1296 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1297 | else | |
1298 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1299 | |
f73b5674 CW |
1300 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1301 | ||
3b3f1650 | 1302 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1303 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1304 | struct rb_node *rb; | |
1305 | ||
e2f80391 | 1306 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1307 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1308 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1309 | intel_engine_last_submit(engine), |
1310 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1311 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1312 | yesno(intel_engine_has_waiter(engine)), |
1313 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1314 | &dev_priv->gpu_error.missed_irq_rings)), |
1315 | yesno(engine->hangcheck.stalled)); | |
1316 | ||
61d3dc70 | 1317 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1318 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1319 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1320 | |
1321 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1322 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1323 | } | |
61d3dc70 | 1324 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1325 | |
f654449a | 1326 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1327 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1328 | (long long)acthd[id]); |
3fe3b030 MK |
1329 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1330 | hangcheck_action_to_str(engine->hangcheck.action), | |
1331 | engine->hangcheck.action, | |
1332 | jiffies_to_msecs(jiffies - | |
1333 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1334 | |
e2f80391 | 1335 | if (engine->id == RCS) { |
d636951e | 1336 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1337 | |
d636951e | 1338 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1339 | |
d636951e | 1340 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1341 | |
d636951e BW |
1342 | i915_instdone_info(dev_priv, m, |
1343 | &engine->hangcheck.instdone); | |
61642ff0 | 1344 | } |
f654449a CW |
1345 | } |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
061d06a2 MT |
1350 | static int i915_reset_info(struct seq_file *m, void *unused) |
1351 | { | |
1352 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1353 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
1354 | struct intel_engine_cs *engine; | |
1355 | enum intel_engine_id id; | |
1356 | ||
1357 | seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); | |
1358 | ||
1359 | for_each_engine(engine, dev_priv, id) { | |
1360 | seq_printf(m, "%s = %u\n", engine->name, | |
1361 | i915_reset_engine_count(error, engine)); | |
1362 | } | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
4d85529d | 1367 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1368 | { |
36cdd013 | 1369 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1370 | u32 rgvmodectl, rstdbyctl; |
1371 | u16 crstandvid; | |
616fdb5a | 1372 | |
616fdb5a BW |
1373 | rgvmodectl = I915_READ(MEMMODECTL); |
1374 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1375 | crstandvid = I915_READ16(CRSTANDVID); | |
1376 | ||
742f491d | 1377 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1378 | seq_printf(m, "Boost freq: %d\n", |
1379 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1380 | MEMMODE_BOOST_FREQ_SHIFT); | |
1381 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1382 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1383 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1384 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1385 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1386 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1387 | seq_printf(m, "Starting frequency: P%d\n", |
1388 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1389 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1390 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1391 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1392 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1393 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1394 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1395 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1396 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1397 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1398 | case RSX_STATUS_ON: | |
267f0c90 | 1399 | seq_puts(m, "on\n"); |
88271da3 JB |
1400 | break; |
1401 | case RSX_STATUS_RC1: | |
267f0c90 | 1402 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1403 | break; |
1404 | case RSX_STATUS_RC1E: | |
267f0c90 | 1405 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1406 | break; |
1407 | case RSX_STATUS_RS1: | |
267f0c90 | 1408 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1409 | break; |
1410 | case RSX_STATUS_RS2: | |
267f0c90 | 1411 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1412 | break; |
1413 | case RSX_STATUS_RS3: | |
267f0c90 | 1414 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1415 | break; |
1416 | default: | |
267f0c90 | 1417 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1418 | break; |
1419 | } | |
f97108d1 JB |
1420 | |
1421 | return 0; | |
1422 | } | |
1423 | ||
f65367b5 | 1424 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1425 | { |
233ebf57 | 1426 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1427 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1428 | unsigned int tmp; |
b2cff0db | 1429 | |
d7a133d8 CW |
1430 | seq_printf(m, "user.bypass_count = %u\n", |
1431 | i915->uncore.user_forcewake.count); | |
1432 | ||
233ebf57 | 1433 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1434 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1435 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1436 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1437 | |
b2cff0db CW |
1438 | return 0; |
1439 | } | |
1440 | ||
1362877e MK |
1441 | static void print_rc6_res(struct seq_file *m, |
1442 | const char *title, | |
1443 | const i915_reg_t reg) | |
1444 | { | |
1445 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1446 | ||
1447 | seq_printf(m, "%s %u (%llu us)\n", | |
1448 | title, I915_READ(reg), | |
1449 | intel_rc6_residency_us(dev_priv, reg)); | |
1450 | } | |
1451 | ||
b2cff0db CW |
1452 | static int vlv_drpc_info(struct seq_file *m) |
1453 | { | |
36cdd013 | 1454 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
0d6fc92a | 1455 | u32 rcctl1, pw_status; |
669ab5aa | 1456 | |
6b312cd3 | 1457 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1458 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
1459 | ||
669ab5aa D |
1460 | seq_printf(m, "RC6 Enabled: %s\n", |
1461 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1462 | GEN6_RC_CTL_EI_MODE(1)))); | |
1463 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1464 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1465 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1466 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1467 | |
1362877e MK |
1468 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1469 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1470 | |
f65367b5 | 1471 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1472 | } |
1473 | ||
4d85529d BW |
1474 | static int gen6_drpc_info(struct seq_file *m) |
1475 | { | |
36cdd013 | 1476 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
960e5465 | 1477 | u32 gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1478 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1479 | unsigned forcewake_count; |
cf632bd6 | 1480 | int count = 0; |
93b525dc | 1481 | |
cf632bd6 | 1482 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1483 | if (forcewake_count) { |
267f0c90 DL |
1484 | seq_puts(m, "RC information inaccurate because somebody " |
1485 | "holds a forcewake reference \n"); | |
4d85529d BW |
1486 | } else { |
1487 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1488 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1489 | udelay(10); | |
1490 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1491 | } | |
1492 | ||
75aa3f63 | 1493 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1494 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d | 1495 | |
4d85529d | 1496 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
36cdd013 | 1497 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1498 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1499 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1500 | } | |
cf632bd6 | 1501 | |
9f817501 | 1502 | mutex_lock(&dev_priv->pcu_lock); |
44cbd338 | 1503 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
9f817501 | 1504 | mutex_unlock(&dev_priv->pcu_lock); |
4d85529d | 1505 | |
fff24e21 | 1506 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1507 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1508 | seq_printf(m, "RC6 Enabled: %s\n", | |
1509 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1510 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1511 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1512 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1513 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1514 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1515 | } | |
4d85529d BW |
1516 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1517 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1518 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1519 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1520 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1521 | switch (gt_core_status & GEN6_RCn_MASK) { |
1522 | case GEN6_RC0: | |
1523 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1524 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1525 | else |
267f0c90 | 1526 | seq_puts(m, "on\n"); |
4d85529d BW |
1527 | break; |
1528 | case GEN6_RC3: | |
267f0c90 | 1529 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1530 | break; |
1531 | case GEN6_RC6: | |
267f0c90 | 1532 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1533 | break; |
1534 | case GEN6_RC7: | |
267f0c90 | 1535 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1536 | break; |
1537 | default: | |
267f0c90 | 1538 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1539 | break; |
1540 | } | |
1541 | ||
1542 | seq_printf(m, "Core Power Down: %s\n", | |
1543 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1544 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1545 | seq_printf(m, "Render Power Well: %s\n", |
1546 | (gen9_powergate_status & | |
1547 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1548 | seq_printf(m, "Media Power Well: %s\n", | |
1549 | (gen9_powergate_status & | |
1550 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1551 | } | |
cce66a28 BW |
1552 | |
1553 | /* Not exactly sure what this is */ | |
1362877e MK |
1554 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1555 | GEN6_GT_GFX_RC6_LOCKED); | |
1556 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1557 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1558 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1559 | |
ecd8faea BW |
1560 | seq_printf(m, "RC6 voltage: %dmV\n", |
1561 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1562 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1563 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1564 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1565 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1566 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1567 | } |
1568 | ||
1569 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1570 | { | |
36cdd013 | 1571 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1572 | int err; |
1573 | ||
1574 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1575 | |
36cdd013 | 1576 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1577 | err = vlv_drpc_info(m); |
36cdd013 | 1578 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1579 | err = gen6_drpc_info(m); |
4d85529d | 1580 | else |
cf632bd6 CW |
1581 | err = ironlake_drpc_info(m); |
1582 | ||
1583 | intel_runtime_pm_put(dev_priv); | |
1584 | ||
1585 | return err; | |
4d85529d BW |
1586 | } |
1587 | ||
9a851789 DV |
1588 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1589 | { | |
36cdd013 | 1590 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1591 | |
1592 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1593 | dev_priv->fb_tracking.busy_bits); | |
1594 | ||
1595 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1596 | dev_priv->fb_tracking.flip_bits); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
b5e50c3f JB |
1601 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1602 | { | |
36cdd013 | 1603 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1604 | |
ab309a6a MW |
1605 | if (!HAS_FBC(dev_priv)) |
1606 | return -ENODEV; | |
b5e50c3f | 1607 | |
36623ef8 | 1608 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1609 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1610 | |
0e631adc | 1611 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1612 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1613 | else |
1614 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1615 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1616 | |
3fd5d1ec VS |
1617 | if (intel_fbc_is_active(dev_priv)) { |
1618 | u32 mask; | |
1619 | ||
1620 | if (INTEL_GEN(dev_priv) >= 8) | |
1621 | mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; | |
1622 | else if (INTEL_GEN(dev_priv) >= 7) | |
1623 | mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; | |
1624 | else if (INTEL_GEN(dev_priv) >= 5) | |
1625 | mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; | |
1626 | else if (IS_G4X(dev_priv)) | |
1627 | mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; | |
1628 | else | |
1629 | mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | | |
1630 | FBC_STAT_COMPRESSED); | |
1631 | ||
1632 | seq_printf(m, "Compressing: %s\n", yesno(mask)); | |
0fc6a9dc | 1633 | } |
31b9df10 | 1634 | |
25ad93fd | 1635 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1636 | intel_runtime_pm_put(dev_priv); |
1637 | ||
b5e50c3f JB |
1638 | return 0; |
1639 | } | |
1640 | ||
4127dc43 | 1641 | static int i915_fbc_false_color_get(void *data, u64 *val) |
da46f936 | 1642 | { |
36cdd013 | 1643 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1644 | |
36cdd013 | 1645 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1646 | return -ENODEV; |
1647 | ||
da46f936 | 1648 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1649 | |
1650 | return 0; | |
1651 | } | |
1652 | ||
4127dc43 | 1653 | static int i915_fbc_false_color_set(void *data, u64 val) |
da46f936 | 1654 | { |
36cdd013 | 1655 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1656 | u32 reg; |
1657 | ||
36cdd013 | 1658 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1659 | return -ENODEV; |
1660 | ||
25ad93fd | 1661 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1662 | |
1663 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1664 | dev_priv->fbc.false_color = val; | |
1665 | ||
1666 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1667 | (reg | FBC_CTL_FALSE_COLOR) : | |
1668 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1669 | ||
25ad93fd | 1670 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1671 | return 0; |
1672 | } | |
1673 | ||
4127dc43 VS |
1674 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, |
1675 | i915_fbc_false_color_get, i915_fbc_false_color_set, | |
da46f936 RV |
1676 | "%llu\n"); |
1677 | ||
92d44621 PZ |
1678 | static int i915_ips_status(struct seq_file *m, void *unused) |
1679 | { | |
36cdd013 | 1680 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1681 | |
ab309a6a MW |
1682 | if (!HAS_IPS(dev_priv)) |
1683 | return -ENODEV; | |
92d44621 | 1684 | |
36623ef8 PZ |
1685 | intel_runtime_pm_get(dev_priv); |
1686 | ||
0eaa53f0 | 1687 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
4f044a88 | 1688 | yesno(i915_modparams.enable_ips)); |
0eaa53f0 | 1689 | |
36cdd013 | 1690 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1691 | seq_puts(m, "Currently: unknown\n"); |
1692 | } else { | |
1693 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1694 | seq_puts(m, "Currently: enabled\n"); | |
1695 | else | |
1696 | seq_puts(m, "Currently: disabled\n"); | |
1697 | } | |
92d44621 | 1698 | |
36623ef8 PZ |
1699 | intel_runtime_pm_put(dev_priv); |
1700 | ||
92d44621 PZ |
1701 | return 0; |
1702 | } | |
1703 | ||
4a9bef37 JB |
1704 | static int i915_sr_status(struct seq_file *m, void *unused) |
1705 | { | |
36cdd013 | 1706 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1707 | bool sr_enabled = false; |
1708 | ||
36623ef8 | 1709 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1710 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1711 | |
7342a72c CW |
1712 | if (INTEL_GEN(dev_priv) >= 9) |
1713 | /* no global SR status; inspect per-plane WM */; | |
1714 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1715 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1716 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1717 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1718 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1719 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1720 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1721 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1722 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1723 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1724 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1725 | |
9c870d03 | 1726 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1727 | intel_runtime_pm_put(dev_priv); |
1728 | ||
08c4d7fc | 1729 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1730 | |
1731 | return 0; | |
1732 | } | |
1733 | ||
7648fa99 JB |
1734 | static int i915_emon_status(struct seq_file *m, void *unused) |
1735 | { | |
36cdd013 DW |
1736 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1737 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1738 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1739 | int ret; |
1740 | ||
36cdd013 | 1741 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1742 | return -ENODEV; |
1743 | ||
de227ef0 CW |
1744 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1745 | if (ret) | |
1746 | return ret; | |
7648fa99 JB |
1747 | |
1748 | temp = i915_mch_val(dev_priv); | |
1749 | chipset = i915_chipset_val(dev_priv); | |
1750 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1751 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1752 | |
1753 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1754 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1755 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1756 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1757 | ||
1758 | return 0; | |
1759 | } | |
1760 | ||
23b2f8bb JB |
1761 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1762 | { | |
36cdd013 | 1763 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1764 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
5bfa0199 | 1765 | int ret = 0; |
23b2f8bb | 1766 | int gpu_freq, ia_freq; |
f936ec34 | 1767 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1768 | |
ab309a6a MW |
1769 | if (!HAS_LLC(dev_priv)) |
1770 | return -ENODEV; | |
23b2f8bb | 1771 | |
5bfa0199 PZ |
1772 | intel_runtime_pm_get(dev_priv); |
1773 | ||
9f817501 | 1774 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
23b2f8bb | 1775 | if (ret) |
5bfa0199 | 1776 | goto out; |
23b2f8bb | 1777 | |
35ceabf3 | 1778 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
f936ec34 | 1779 | /* Convert GT frequency to 50 HZ units */ |
562d9bae SAK |
1780 | min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER; |
1781 | max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER; | |
f936ec34 | 1782 | } else { |
562d9bae SAK |
1783 | min_gpu_freq = rps->min_freq_softlimit; |
1784 | max_gpu_freq = rps->max_freq_softlimit; | |
f936ec34 AG |
1785 | } |
1786 | ||
267f0c90 | 1787 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1788 | |
f936ec34 | 1789 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1790 | ia_freq = gpu_freq; |
1791 | sandybridge_pcode_read(dev_priv, | |
1792 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1793 | &ia_freq); | |
3ebecd07 | 1794 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1795 | intel_gpu_freq(dev_priv, (gpu_freq * |
35ceabf3 RV |
1796 | (IS_GEN9_BC(dev_priv) || |
1797 | IS_CANNONLAKE(dev_priv) ? | |
b976dc53 | 1798 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1799 | ((ia_freq >> 0) & 0xff) * 100, |
1800 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1801 | } |
1802 | ||
9f817501 | 1803 | mutex_unlock(&dev_priv->pcu_lock); |
23b2f8bb | 1804 | |
5bfa0199 PZ |
1805 | out: |
1806 | intel_runtime_pm_put(dev_priv); | |
1807 | return ret; | |
23b2f8bb JB |
1808 | } |
1809 | ||
44834a67 CW |
1810 | static int i915_opregion(struct seq_file *m, void *unused) |
1811 | { | |
36cdd013 DW |
1812 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1813 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1814 | struct intel_opregion *opregion = &dev_priv->opregion; |
1815 | int ret; | |
1816 | ||
1817 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1818 | if (ret) | |
0d38f009 | 1819 | goto out; |
44834a67 | 1820 | |
2455a8e4 JN |
1821 | if (opregion->header) |
1822 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1823 | |
1824 | mutex_unlock(&dev->struct_mutex); | |
1825 | ||
0d38f009 | 1826 | out: |
44834a67 CW |
1827 | return 0; |
1828 | } | |
1829 | ||
ada8f955 JN |
1830 | static int i915_vbt(struct seq_file *m, void *unused) |
1831 | { | |
36cdd013 | 1832 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1833 | |
1834 | if (opregion->vbt) | |
1835 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1836 | ||
1837 | return 0; | |
1838 | } | |
1839 | ||
37811fcc CW |
1840 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1841 | { | |
36cdd013 DW |
1842 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1843 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1844 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1845 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1846 | int ret; |
1847 | ||
1848 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1849 | if (ret) | |
1850 | return ret; | |
37811fcc | 1851 | |
0695726e | 1852 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
346fb4e0 | 1853 | if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { |
36cdd013 | 1854 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); |
25bcce94 CW |
1855 | |
1856 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1857 | fbdev_fb->base.width, | |
1858 | fbdev_fb->base.height, | |
b00c600e | 1859 | fbdev_fb->base.format->depth, |
272725c7 | 1860 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1861 | fbdev_fb->base.modifier, |
25bcce94 CW |
1862 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1863 | describe_obj(m, fbdev_fb->obj); | |
1864 | seq_putc(m, '\n'); | |
1865 | } | |
4520f53a | 1866 | #endif |
37811fcc | 1867 | |
4b096ac1 | 1868 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1869 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1870 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1871 | if (fb == fbdev_fb) | |
37811fcc CW |
1872 | continue; |
1873 | ||
c1ca506d | 1874 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1875 | fb->base.width, |
1876 | fb->base.height, | |
b00c600e | 1877 | fb->base.format->depth, |
272725c7 | 1878 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1879 | fb->base.modifier, |
747a598f | 1880 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1881 | describe_obj(m, fb->obj); |
267f0c90 | 1882 | seq_putc(m, '\n'); |
37811fcc | 1883 | } |
4b096ac1 | 1884 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1885 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1886 | |
1887 | return 0; | |
1888 | } | |
1889 | ||
7e37f889 | 1890 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1891 | { |
fe085f13 CW |
1892 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1893 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1894 | } |
1895 | ||
e76d3630 BW |
1896 | static int i915_context_status(struct seq_file *m, void *unused) |
1897 | { | |
36cdd013 DW |
1898 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1899 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1900 | struct intel_engine_cs *engine; |
e2efd130 | 1901 | struct i915_gem_context *ctx; |
3b3f1650 | 1902 | enum intel_engine_id id; |
c3232b18 | 1903 | int ret; |
e76d3630 | 1904 | |
f3d28878 | 1905 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1906 | if (ret) |
1907 | return ret; | |
1908 | ||
829a0af2 | 1909 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
5d1808ec | 1910 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1911 | if (ctx->pid) { |
d28b99ab CW |
1912 | struct task_struct *task; |
1913 | ||
c84455b4 | 1914 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1915 | if (task) { |
1916 | seq_printf(m, "(%s [%d]) ", | |
1917 | task->comm, task->pid); | |
1918 | put_task_struct(task); | |
1919 | } | |
c84455b4 CW |
1920 | } else if (IS_ERR(ctx->file_priv)) { |
1921 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1922 | } else { |
1923 | seq_puts(m, "(kernel) "); | |
1924 | } | |
1925 | ||
bca44d80 CW |
1926 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1927 | seq_putc(m, '\n'); | |
c9fe99bd | 1928 | |
3b3f1650 | 1929 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1930 | struct intel_context *ce = &ctx->engine[engine->id]; |
1931 | ||
1932 | seq_printf(m, "%s: ", engine->name); | |
bca44d80 | 1933 | if (ce->state) |
bf3783e5 | 1934 | describe_obj(m, ce->state->obj); |
dca33ecc | 1935 | if (ce->ring) |
7e37f889 | 1936 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1937 | seq_putc(m, '\n'); |
c9fe99bd | 1938 | } |
a33afea5 | 1939 | |
a33afea5 | 1940 | seq_putc(m, '\n'); |
a168c293 BW |
1941 | } |
1942 | ||
f3d28878 | 1943 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1944 | |
1945 | return 0; | |
1946 | } | |
1947 | ||
ea16a3cd DV |
1948 | static const char *swizzle_string(unsigned swizzle) |
1949 | { | |
aee56cff | 1950 | switch (swizzle) { |
ea16a3cd DV |
1951 | case I915_BIT_6_SWIZZLE_NONE: |
1952 | return "none"; | |
1953 | case I915_BIT_6_SWIZZLE_9: | |
1954 | return "bit9"; | |
1955 | case I915_BIT_6_SWIZZLE_9_10: | |
1956 | return "bit9/bit10"; | |
1957 | case I915_BIT_6_SWIZZLE_9_11: | |
1958 | return "bit9/bit11"; | |
1959 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1960 | return "bit9/bit10/bit11"; | |
1961 | case I915_BIT_6_SWIZZLE_9_17: | |
1962 | return "bit9/bit17"; | |
1963 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1964 | return "bit9/bit10/bit17"; | |
1965 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1966 | return "unknown"; |
ea16a3cd DV |
1967 | } |
1968 | ||
1969 | return "bug"; | |
1970 | } | |
1971 | ||
1972 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1973 | { | |
36cdd013 | 1974 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 1975 | |
c8c8fb33 | 1976 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1977 | |
ea16a3cd DV |
1978 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1979 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1980 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1981 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1982 | ||
36cdd013 | 1983 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
1984 | seq_printf(m, "DDC = 0x%08x\n", |
1985 | I915_READ(DCC)); | |
656bfa3a DV |
1986 | seq_printf(m, "DDC2 = 0x%08x\n", |
1987 | I915_READ(DCC2)); | |
ea16a3cd DV |
1988 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
1989 | I915_READ16(C0DRB3)); | |
1990 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1991 | I915_READ16(C1DRB3)); | |
36cdd013 | 1992 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
1993 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1994 | I915_READ(MAD_DIMM_C0)); | |
1995 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1996 | I915_READ(MAD_DIMM_C1)); | |
1997 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1998 | I915_READ(MAD_DIMM_C2)); | |
1999 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2000 | I915_READ(TILECTL)); | |
36cdd013 | 2001 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2002 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2003 | I915_READ(GAMTARBMODE)); | |
2004 | else | |
2005 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2006 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2007 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2008 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2009 | } |
656bfa3a DV |
2010 | |
2011 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2012 | seq_puts(m, "L-shaped memory detected\n"); | |
2013 | ||
c8c8fb33 | 2014 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2015 | |
2016 | return 0; | |
2017 | } | |
2018 | ||
1c60fef5 BW |
2019 | static int per_file_ctx(int id, void *ptr, void *data) |
2020 | { | |
e2efd130 | 2021 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2022 | struct seq_file *m = data; |
ae6c4806 DV |
2023 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2024 | ||
2025 | if (!ppgtt) { | |
2026 | seq_printf(m, " no ppgtt for context %d\n", | |
2027 | ctx->user_handle); | |
2028 | return 0; | |
2029 | } | |
1c60fef5 | 2030 | |
f83d6518 OM |
2031 | if (i915_gem_context_is_default(ctx)) |
2032 | seq_puts(m, " default context:\n"); | |
2033 | else | |
821d66dd | 2034 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2035 | ppgtt->debug_dump(ppgtt, m); |
2036 | ||
2037 | return 0; | |
2038 | } | |
2039 | ||
36cdd013 DW |
2040 | static void gen8_ppgtt_info(struct seq_file *m, |
2041 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2042 | { |
77df6772 | 2043 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2044 | struct intel_engine_cs *engine; |
2045 | enum intel_engine_id id; | |
b4ac5afc | 2046 | int i; |
3cf17fc5 | 2047 | |
77df6772 BW |
2048 | if (!ppgtt) |
2049 | return; | |
2050 | ||
3b3f1650 | 2051 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2052 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2053 | for (i = 0; i < 4; i++) { |
e2f80391 | 2054 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2055 | pdp <<= 32; |
e2f80391 | 2056 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2057 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2058 | } |
2059 | } | |
2060 | } | |
2061 | ||
36cdd013 DW |
2062 | static void gen6_ppgtt_info(struct seq_file *m, |
2063 | struct drm_i915_private *dev_priv) | |
77df6772 | 2064 | { |
e2f80391 | 2065 | struct intel_engine_cs *engine; |
3b3f1650 | 2066 | enum intel_engine_id id; |
3cf17fc5 | 2067 | |
7e22dbbb | 2068 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2069 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2070 | ||
3b3f1650 | 2071 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2072 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2073 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2074 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2075 | I915_READ(RING_MODE_GEN7(engine))); | |
2076 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2077 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2078 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2079 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2080 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2081 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2082 | } |
2083 | if (dev_priv->mm.aliasing_ppgtt) { | |
2084 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2085 | ||
267f0c90 | 2086 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2087 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2088 | |
87d60b63 | 2089 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2090 | } |
1c60fef5 | 2091 | |
3cf17fc5 | 2092 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2093 | } |
2094 | ||
2095 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2096 | { | |
36cdd013 DW |
2097 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2098 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2099 | struct drm_file *file; |
637ee29e | 2100 | int ret; |
77df6772 | 2101 | |
637ee29e CW |
2102 | mutex_lock(&dev->filelist_mutex); |
2103 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2104 | if (ret) |
637ee29e CW |
2105 | goto out_unlock; |
2106 | ||
c8c8fb33 | 2107 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2108 | |
36cdd013 DW |
2109 | if (INTEL_GEN(dev_priv) >= 8) |
2110 | gen8_ppgtt_info(m, dev_priv); | |
2111 | else if (INTEL_GEN(dev_priv) >= 6) | |
2112 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2113 | |
ea91e401 MT |
2114 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2115 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2116 | struct task_struct *task; |
ea91e401 | 2117 | |
7cb5dff8 | 2118 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2119 | if (!task) { |
2120 | ret = -ESRCH; | |
637ee29e | 2121 | goto out_rpm; |
06812760 | 2122 | } |
7cb5dff8 GT |
2123 | seq_printf(m, "\nproc: %s\n", task->comm); |
2124 | put_task_struct(task); | |
ea91e401 MT |
2125 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2126 | (void *)(unsigned long)m); | |
2127 | } | |
2128 | ||
637ee29e | 2129 | out_rpm: |
c8c8fb33 | 2130 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2131 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2132 | out_unlock: |
2133 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2134 | return ret; |
3cf17fc5 DV |
2135 | } |
2136 | ||
f5a4c67d CW |
2137 | static int count_irq_waiters(struct drm_i915_private *i915) |
2138 | { | |
e2f80391 | 2139 | struct intel_engine_cs *engine; |
3b3f1650 | 2140 | enum intel_engine_id id; |
f5a4c67d | 2141 | int count = 0; |
f5a4c67d | 2142 | |
3b3f1650 | 2143 | for_each_engine(engine, i915, id) |
688e6c72 | 2144 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2145 | |
2146 | return count; | |
2147 | } | |
2148 | ||
7466c291 CW |
2149 | static const char *rps_power_to_str(unsigned int power) |
2150 | { | |
2151 | static const char * const strings[] = { | |
2152 | [LOW_POWER] = "low power", | |
2153 | [BETWEEN] = "mixed", | |
2154 | [HIGH_POWER] = "high power", | |
2155 | }; | |
2156 | ||
2157 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2158 | return "unknown"; | |
2159 | ||
2160 | return strings[power]; | |
2161 | } | |
2162 | ||
1854d5ca CW |
2163 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2164 | { | |
36cdd013 DW |
2165 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2166 | struct drm_device *dev = &dev_priv->drm; | |
562d9bae | 2167 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
1854d5ca | 2168 | struct drm_file *file; |
1854d5ca | 2169 | |
562d9bae | 2170 | seq_printf(m, "RPS enabled? %d\n", rps->enabled); |
28176ef4 CW |
2171 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2172 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2173 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7b92c1bd | 2174 | seq_printf(m, "Boosts outstanding? %d\n", |
562d9bae | 2175 | atomic_read(&rps->num_waiters)); |
7466c291 | 2176 | seq_printf(m, "Frequency requested %d\n", |
562d9bae | 2177 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
7466c291 | 2178 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", |
562d9bae SAK |
2179 | intel_gpu_freq(dev_priv, rps->min_freq), |
2180 | intel_gpu_freq(dev_priv, rps->min_freq_softlimit), | |
2181 | intel_gpu_freq(dev_priv, rps->max_freq_softlimit), | |
2182 | intel_gpu_freq(dev_priv, rps->max_freq)); | |
7466c291 | 2183 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
562d9bae SAK |
2184 | intel_gpu_freq(dev_priv, rps->idle_freq), |
2185 | intel_gpu_freq(dev_priv, rps->efficient_freq), | |
2186 | intel_gpu_freq(dev_priv, rps->boost_freq)); | |
1d2ac403 DV |
2187 | |
2188 | mutex_lock(&dev->filelist_mutex); | |
1854d5ca CW |
2189 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2190 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2191 | struct task_struct *task; | |
2192 | ||
2193 | rcu_read_lock(); | |
2194 | task = pid_task(file->pid, PIDTYPE_PID); | |
7b92c1bd | 2195 | seq_printf(m, "%s [%d]: %d boosts\n", |
1854d5ca CW |
2196 | task ? task->comm : "<unknown>", |
2197 | task ? task->pid : -1, | |
562d9bae | 2198 | atomic_read(&file_priv->rps_client.boosts)); |
1854d5ca CW |
2199 | rcu_read_unlock(); |
2200 | } | |
7b92c1bd | 2201 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", |
562d9bae | 2202 | atomic_read(&rps->boosts)); |
1d2ac403 | 2203 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2204 | |
7466c291 | 2205 | if (INTEL_GEN(dev_priv) >= 6 && |
562d9bae | 2206 | rps->enabled && |
28176ef4 | 2207 | dev_priv->gt.active_requests) { |
7466c291 CW |
2208 | u32 rpup, rpupei; |
2209 | u32 rpdown, rpdownei; | |
2210 | ||
2211 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2212 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2213 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2214 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2215 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2216 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2217 | ||
2218 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
562d9bae | 2219 | rps_power_to_str(rps->power)); |
7466c291 | 2220 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", |
23f4a287 | 2221 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
562d9bae | 2222 | rps->up_threshold); |
7466c291 | 2223 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", |
23f4a287 | 2224 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
562d9bae | 2225 | rps->down_threshold); |
7466c291 CW |
2226 | } else { |
2227 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2228 | } | |
2229 | ||
8d3afd7d | 2230 | return 0; |
1854d5ca CW |
2231 | } |
2232 | ||
63573eb7 BW |
2233 | static int i915_llc(struct seq_file *m, void *data) |
2234 | { | |
36cdd013 | 2235 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2236 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2237 | |
36cdd013 | 2238 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2239 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2240 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2241 | |
2242 | return 0; | |
2243 | } | |
2244 | ||
0509ead1 AS |
2245 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2246 | { | |
2247 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
56ffc742 | 2248 | struct drm_printer p; |
0509ead1 | 2249 | |
ab309a6a MW |
2250 | if (!HAS_HUC(dev_priv)) |
2251 | return -ENODEV; | |
0509ead1 | 2252 | |
56ffc742 MW |
2253 | p = drm_seq_file_printer(m); |
2254 | intel_uc_fw_dump(&dev_priv->huc.fw, &p); | |
0509ead1 | 2255 | |
3582ad13 | 2256 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2257 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2258 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2259 | |
2260 | return 0; | |
2261 | } | |
2262 | ||
fdf5d357 AD |
2263 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2264 | { | |
36cdd013 | 2265 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
56ffc742 | 2266 | struct drm_printer p; |
fdf5d357 AD |
2267 | u32 tmp, i; |
2268 | ||
ab309a6a MW |
2269 | if (!HAS_GUC(dev_priv)) |
2270 | return -ENODEV; | |
fdf5d357 | 2271 | |
56ffc742 MW |
2272 | p = drm_seq_file_printer(m); |
2273 | intel_uc_fw_dump(&dev_priv->guc.fw, &p); | |
fdf5d357 | 2274 | |
3582ad13 | 2275 | intel_runtime_pm_get(dev_priv); |
2276 | ||
fdf5d357 AD |
2277 | tmp = I915_READ(GUC_STATUS); |
2278 | ||
2279 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2280 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2281 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2282 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2283 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2284 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2285 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2286 | seq_puts(m, "\nScratch registers:\n"); | |
2287 | for (i = 0; i < 16; i++) | |
2288 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2289 | ||
3582ad13 | 2290 | intel_runtime_pm_put(dev_priv); |
2291 | ||
fdf5d357 AD |
2292 | return 0; |
2293 | } | |
2294 | ||
5aa1ee4b AG |
2295 | static void i915_guc_log_info(struct seq_file *m, |
2296 | struct drm_i915_private *dev_priv) | |
2297 | { | |
2298 | struct intel_guc *guc = &dev_priv->guc; | |
2299 | ||
2300 | seq_puts(m, "\nGuC logging stats:\n"); | |
2301 | ||
2302 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2303 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2304 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2305 | ||
2306 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2307 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2308 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2309 | ||
2310 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2311 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2312 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2313 | ||
2314 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2315 | guc->log.flush_interrupt_count); | |
2316 | ||
2317 | seq_printf(m, "\tCapture miss count: %u\n", | |
2318 | guc->log.capture_miss_count); | |
2319 | } | |
2320 | ||
8b417c26 DG |
2321 | static void i915_guc_client_info(struct seq_file *m, |
2322 | struct drm_i915_private *dev_priv, | |
5afc8b49 | 2323 | struct intel_guc_client *client) |
8b417c26 | 2324 | { |
e2f80391 | 2325 | struct intel_engine_cs *engine; |
c18468c4 | 2326 | enum intel_engine_id id; |
8b417c26 | 2327 | uint64_t tot = 0; |
8b417c26 | 2328 | |
b09935a6 OM |
2329 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2330 | client->priority, client->stage_id, client->proc_desc_offset); | |
59db36cf MW |
2331 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", |
2332 | client->doorbell_id, client->doorbell_offset); | |
8b417c26 | 2333 | |
3b3f1650 | 2334 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2335 | u64 submissions = client->submissions[id]; |
2336 | tot += submissions; | |
8b417c26 | 2337 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2338 | submissions, engine->name); |
8b417c26 DG |
2339 | } |
2340 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2341 | } | |
2342 | ||
a8b9370f OM |
2343 | static int i915_guc_info(struct seq_file *m, void *data) |
2344 | { | |
2345 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2346 | const struct intel_guc *guc = &dev_priv->guc; | |
a8b9370f | 2347 | |
ab309a6a MW |
2348 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2349 | return -ENODEV; | |
2350 | ||
2351 | GEM_BUG_ON(!guc->execbuf_client); | |
2352 | GEM_BUG_ON(!guc->preempt_client); | |
a8b9370f | 2353 | |
9636f6db | 2354 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2355 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2356 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2357 | |
334636c6 CW |
2358 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2359 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
e12ab169 DG |
2360 | seq_printf(m, "\nGuC preempt client @ %p:\n", guc->preempt_client); |
2361 | i915_guc_client_info(m, dev_priv, guc->preempt_client); | |
8b417c26 | 2362 | |
5aa1ee4b AG |
2363 | i915_guc_log_info(m, dev_priv); |
2364 | ||
8b417c26 DG |
2365 | /* Add more as required ... */ |
2366 | ||
2367 | return 0; | |
2368 | } | |
2369 | ||
a8b9370f | 2370 | static int i915_guc_stage_pool(struct seq_file *m, void *data) |
4c7e77fc | 2371 | { |
36cdd013 | 2372 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a8b9370f OM |
2373 | const struct intel_guc *guc = &dev_priv->guc; |
2374 | struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; | |
5afc8b49 | 2375 | struct intel_guc_client *client = guc->execbuf_client; |
a8b9370f OM |
2376 | unsigned int tmp; |
2377 | int index; | |
4c7e77fc | 2378 | |
ab309a6a MW |
2379 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2380 | return -ENODEV; | |
4c7e77fc | 2381 | |
a8b9370f OM |
2382 | for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { |
2383 | struct intel_engine_cs *engine; | |
2384 | ||
2385 | if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)) | |
2386 | continue; | |
2387 | ||
2388 | seq_printf(m, "GuC stage descriptor %u:\n", index); | |
2389 | seq_printf(m, "\tIndex: %u\n", desc->stage_id); | |
2390 | seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); | |
2391 | seq_printf(m, "\tPriority: %d\n", desc->priority); | |
2392 | seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); | |
2393 | seq_printf(m, "\tEngines used: 0x%x\n", | |
2394 | desc->engines_used); | |
2395 | seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", | |
2396 | desc->db_trigger_phy, | |
2397 | desc->db_trigger_cpu, | |
2398 | desc->db_trigger_uk); | |
2399 | seq_printf(m, "\tProcess descriptor: 0x%x\n", | |
2400 | desc->process_desc); | |
9a09485d | 2401 | seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", |
a8b9370f OM |
2402 | desc->wq_addr, desc->wq_size); |
2403 | seq_putc(m, '\n'); | |
2404 | ||
2405 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { | |
2406 | u32 guc_engine_id = engine->guc_id; | |
2407 | struct guc_execlist_context *lrc = | |
2408 | &desc->lrc[guc_engine_id]; | |
2409 | ||
2410 | seq_printf(m, "\t%s LRC:\n", engine->name); | |
2411 | seq_printf(m, "\t\tContext desc: 0x%x\n", | |
2412 | lrc->context_desc); | |
2413 | seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); | |
2414 | seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); | |
2415 | seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); | |
2416 | seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); | |
2417 | seq_putc(m, '\n'); | |
2418 | } | |
2419 | } | |
2420 | ||
2421 | return 0; | |
2422 | } | |
2423 | ||
4c7e77fc AD |
2424 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2425 | { | |
ac58d2ab DCS |
2426 | struct drm_info_node *node = m->private; |
2427 | struct drm_i915_private *dev_priv = node_to_i915(node); | |
2428 | bool dump_load_err = !!node->info_ent->data; | |
2429 | struct drm_i915_gem_object *obj = NULL; | |
2430 | u32 *log; | |
2431 | int i = 0; | |
4c7e77fc | 2432 | |
ab309a6a MW |
2433 | if (!HAS_GUC(dev_priv)) |
2434 | return -ENODEV; | |
2435 | ||
ac58d2ab DCS |
2436 | if (dump_load_err) |
2437 | obj = dev_priv->guc.load_err_log; | |
2438 | else if (dev_priv->guc.log.vma) | |
2439 | obj = dev_priv->guc.log.vma->obj; | |
4c7e77fc | 2440 | |
ac58d2ab DCS |
2441 | if (!obj) |
2442 | return 0; | |
4c7e77fc | 2443 | |
ac58d2ab DCS |
2444 | log = i915_gem_object_pin_map(obj, I915_MAP_WC); |
2445 | if (IS_ERR(log)) { | |
2446 | DRM_DEBUG("Failed to pin object\n"); | |
2447 | seq_puts(m, "(log data unaccessible)\n"); | |
2448 | return PTR_ERR(log); | |
4c7e77fc AD |
2449 | } |
2450 | ||
ac58d2ab DCS |
2451 | for (i = 0; i < obj->base.size / sizeof(u32); i += 4) |
2452 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2453 | *(log + i), *(log + i + 1), | |
2454 | *(log + i + 2), *(log + i + 3)); | |
2455 | ||
4c7e77fc AD |
2456 | seq_putc(m, '\n'); |
2457 | ||
ac58d2ab DCS |
2458 | i915_gem_object_unpin_map(obj); |
2459 | ||
4c7e77fc AD |
2460 | return 0; |
2461 | } | |
2462 | ||
685534ef SAK |
2463 | static int i915_guc_log_control_get(void *data, u64 *val) |
2464 | { | |
bcc36d8a | 2465 | struct drm_i915_private *dev_priv = data; |
685534ef | 2466 | |
ab309a6a MW |
2467 | if (!HAS_GUC(dev_priv)) |
2468 | return -ENODEV; | |
2469 | ||
685534ef SAK |
2470 | if (!dev_priv->guc.log.vma) |
2471 | return -EINVAL; | |
2472 | ||
4f044a88 | 2473 | *val = i915_modparams.guc_log_level; |
685534ef SAK |
2474 | |
2475 | return 0; | |
2476 | } | |
2477 | ||
2478 | static int i915_guc_log_control_set(void *data, u64 val) | |
2479 | { | |
bcc36d8a | 2480 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2481 | int ret; |
2482 | ||
ab309a6a MW |
2483 | if (!HAS_GUC(dev_priv)) |
2484 | return -ENODEV; | |
2485 | ||
685534ef SAK |
2486 | if (!dev_priv->guc.log.vma) |
2487 | return -EINVAL; | |
2488 | ||
bcc36d8a | 2489 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2490 | if (ret) |
2491 | return ret; | |
2492 | ||
2493 | intel_runtime_pm_get(dev_priv); | |
2494 | ret = i915_guc_log_control(dev_priv, val); | |
2495 | intel_runtime_pm_put(dev_priv); | |
2496 | ||
bcc36d8a | 2497 | mutex_unlock(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2498 | return ret; |
2499 | } | |
2500 | ||
2501 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2502 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2503 | "%lld\n"); | |
2504 | ||
b86bef20 CW |
2505 | static const char *psr2_live_status(u32 val) |
2506 | { | |
2507 | static const char * const live_status[] = { | |
2508 | "IDLE", | |
2509 | "CAPTURE", | |
2510 | "CAPTURE_FS", | |
2511 | "SLEEP", | |
2512 | "BUFON_FW", | |
2513 | "ML_UP", | |
2514 | "SU_STANDBY", | |
2515 | "FAST_SLEEP", | |
2516 | "DEEP_SLEEP", | |
2517 | "BUF_ON", | |
2518 | "TG_ON" | |
2519 | }; | |
2520 | ||
2521 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2522 | if (val < ARRAY_SIZE(live_status)) | |
2523 | return live_status[val]; | |
2524 | ||
2525 | return "unknown"; | |
2526 | } | |
2527 | ||
e91fd8c6 RV |
2528 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2529 | { | |
36cdd013 | 2530 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2531 | u32 psrperf = 0; |
a6cbdb8e RV |
2532 | u32 stat[3]; |
2533 | enum pipe pipe; | |
a031d709 | 2534 | bool enabled = false; |
e91fd8c6 | 2535 | |
ab309a6a MW |
2536 | if (!HAS_PSR(dev_priv)) |
2537 | return -ENODEV; | |
3553a8ea | 2538 | |
c8c8fb33 PZ |
2539 | intel_runtime_pm_get(dev_priv); |
2540 | ||
fa128fa6 | 2541 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2542 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2543 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2544 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2545 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2546 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2547 | dev_priv->psr.busy_frontbuffer_bits); | |
2548 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2549 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2550 | |
7e3eb599 NV |
2551 | if (HAS_DDI(dev_priv)) { |
2552 | if (dev_priv->psr.psr2_support) | |
2553 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2554 | else | |
2555 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2556 | } else { | |
3553a8ea | 2557 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2558 | enum transcoder cpu_transcoder = |
2559 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2560 | enum intel_display_power_domain power_domain; | |
2561 | ||
2562 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2563 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2564 | power_domain)) | |
2565 | continue; | |
2566 | ||
3553a8ea DL |
2567 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2568 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2569 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2570 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2571 | enabled = true; | |
9c870d03 CW |
2572 | |
2573 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2574 | } |
2575 | } | |
60e5ffe3 RV |
2576 | |
2577 | seq_printf(m, "Main link in standby mode: %s\n", | |
2578 | yesno(dev_priv->psr.link_standby)); | |
2579 | ||
a6cbdb8e RV |
2580 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2581 | ||
36cdd013 | 2582 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2583 | for_each_pipe(dev_priv, pipe) { |
2584 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2585 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2586 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2587 | } | |
2588 | seq_puts(m, "\n"); | |
e91fd8c6 | 2589 | |
05eec3c2 RV |
2590 | /* |
2591 | * VLV/CHV PSR has no kind of performance counter | |
2592 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2593 | */ | |
36cdd013 | 2594 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2595 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2596 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2597 | |
2598 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2599 | } | |
6ba1f9e1 | 2600 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2601 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2602 | ||
2603 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2604 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2605 | } |
fa128fa6 | 2606 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2607 | |
c8c8fb33 | 2608 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2609 | return 0; |
2610 | } | |
2611 | ||
d2e216d0 RV |
2612 | static int i915_sink_crc(struct seq_file *m, void *data) |
2613 | { | |
36cdd013 DW |
2614 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2615 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2616 | struct intel_connector *connector; |
3f6a5e1e | 2617 | struct drm_connector_list_iter conn_iter; |
d2e216d0 | 2618 | struct intel_dp *intel_dp = NULL; |
10bf0a38 | 2619 | struct drm_modeset_acquire_ctx ctx; |
d2e216d0 RV |
2620 | int ret; |
2621 | u8 crc[6]; | |
2622 | ||
10bf0a38 ML |
2623 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
2624 | ||
3f6a5e1e | 2625 | drm_connector_list_iter_begin(dev, &conn_iter); |
10bf0a38 | 2626 | |
3f6a5e1e | 2627 | for_each_intel_connector_iter(connector, &conn_iter) { |
26c17cf6 | 2628 | struct drm_crtc *crtc; |
10bf0a38 | 2629 | struct drm_connector_state *state; |
93313538 | 2630 | struct intel_crtc_state *crtc_state; |
d2e216d0 | 2631 | |
10bf0a38 | 2632 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2633 | continue; |
2634 | ||
10bf0a38 ML |
2635 | retry: |
2636 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); | |
2637 | if (ret) | |
2638 | goto err; | |
2639 | ||
2640 | state = connector->base.state; | |
2641 | if (!state->best_encoder) | |
b6ae3c7c PZ |
2642 | continue; |
2643 | ||
10bf0a38 ML |
2644 | crtc = state->crtc; |
2645 | ret = drm_modeset_lock(&crtc->mutex, &ctx); | |
2646 | if (ret) | |
2647 | goto err; | |
2648 | ||
93313538 ML |
2649 | crtc_state = to_intel_crtc_state(crtc->state); |
2650 | if (!crtc_state->base.active) | |
d2e216d0 RV |
2651 | continue; |
2652 | ||
93313538 ML |
2653 | /* |
2654 | * We need to wait for all crtc updates to complete, to make | |
2655 | * sure any pending modesets and plane updates are completed. | |
2656 | */ | |
2657 | if (crtc_state->base.commit) { | |
2658 | ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done); | |
2659 | ||
2660 | if (ret) | |
2661 | goto err; | |
2662 | } | |
2663 | ||
10bf0a38 | 2664 | intel_dp = enc_to_intel_dp(state->best_encoder); |
d2e216d0 | 2665 | |
93313538 | 2666 | ret = intel_dp_sink_crc(intel_dp, crtc_state, crc); |
d2e216d0 | 2667 | if (ret) |
10bf0a38 | 2668 | goto err; |
d2e216d0 RV |
2669 | |
2670 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2671 | crc[0], crc[1], crc[2], | |
2672 | crc[3], crc[4], crc[5]); | |
2673 | goto out; | |
10bf0a38 ML |
2674 | |
2675 | err: | |
2676 | if (ret == -EDEADLK) { | |
2677 | ret = drm_modeset_backoff(&ctx); | |
2678 | if (!ret) | |
2679 | goto retry; | |
2680 | } | |
2681 | goto out; | |
d2e216d0 RV |
2682 | } |
2683 | ret = -ENODEV; | |
2684 | out: | |
3f6a5e1e | 2685 | drm_connector_list_iter_end(&conn_iter); |
10bf0a38 ML |
2686 | drm_modeset_drop_locks(&ctx); |
2687 | drm_modeset_acquire_fini(&ctx); | |
2688 | ||
d2e216d0 RV |
2689 | return ret; |
2690 | } | |
2691 | ||
ec013e7f JB |
2692 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2693 | { | |
36cdd013 | 2694 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
d38014ea | 2695 | unsigned long long power; |
ec013e7f JB |
2696 | u32 units; |
2697 | ||
36cdd013 | 2698 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2699 | return -ENODEV; |
2700 | ||
36623ef8 PZ |
2701 | intel_runtime_pm_get(dev_priv); |
2702 | ||
d38014ea GKB |
2703 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { |
2704 | intel_runtime_pm_put(dev_priv); | |
2705 | return -ENODEV; | |
2706 | } | |
2707 | ||
2708 | units = (power & 0x1f00) >> 8; | |
ec013e7f | 2709 | power = I915_READ(MCH_SECP_NRG_STTS); |
d38014ea | 2710 | power = (1000000 * power) >> units; /* convert to uJ */ |
ec013e7f | 2711 | |
36623ef8 PZ |
2712 | intel_runtime_pm_put(dev_priv); |
2713 | ||
d38014ea | 2714 | seq_printf(m, "%llu", power); |
371db66a PZ |
2715 | |
2716 | return 0; | |
2717 | } | |
2718 | ||
6455c870 | 2719 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2720 | { |
36cdd013 | 2721 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2722 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2723 | |
a156e64d CW |
2724 | if (!HAS_RUNTIME_PM(dev_priv)) |
2725 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2726 | |
67d97da3 | 2727 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2728 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2729 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2730 | #ifdef CONFIG_PM |
a6aaec8b | 2731 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2732 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2733 | #else |
2734 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2735 | #endif | |
a156e64d | 2736 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2737 | pci_power_name(pdev->current_state), |
2738 | pdev->current_state); | |
371db66a | 2739 | |
ec013e7f JB |
2740 | return 0; |
2741 | } | |
2742 | ||
1da51581 ID |
2743 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2744 | { | |
36cdd013 | 2745 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2746 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2747 | int i; | |
2748 | ||
2749 | mutex_lock(&power_domains->lock); | |
2750 | ||
2751 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2752 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2753 | struct i915_power_well *power_well; | |
2754 | enum intel_display_power_domain power_domain; | |
2755 | ||
2756 | power_well = &power_domains->power_wells[i]; | |
2757 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2758 | power_well->count); | |
2759 | ||
8385c2ec | 2760 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2761 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2762 | intel_display_power_domain_str(power_domain), |
1da51581 | 2763 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2764 | } |
2765 | ||
2766 | mutex_unlock(&power_domains->lock); | |
2767 | ||
2768 | return 0; | |
2769 | } | |
2770 | ||
b7cec66d DL |
2771 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2772 | { | |
36cdd013 | 2773 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2774 | struct intel_csr *csr; |
2775 | ||
ab309a6a MW |
2776 | if (!HAS_CSR(dev_priv)) |
2777 | return -ENODEV; | |
b7cec66d DL |
2778 | |
2779 | csr = &dev_priv->csr; | |
2780 | ||
6fb403de MK |
2781 | intel_runtime_pm_get(dev_priv); |
2782 | ||
b7cec66d DL |
2783 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2784 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2785 | ||
2786 | if (!csr->dmc_payload) | |
6fb403de | 2787 | goto out; |
b7cec66d DL |
2788 | |
2789 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2790 | CSR_VERSION_MINOR(csr->version)); | |
2791 | ||
48de568c MK |
2792 | if (IS_KABYLAKE(dev_priv) || |
2793 | (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) { | |
8337206d DL |
2794 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2795 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2796 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2797 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2798 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2799 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2800 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2801 | } |
2802 | ||
6fb403de MK |
2803 | out: |
2804 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2805 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2806 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2807 | ||
8337206d DL |
2808 | intel_runtime_pm_put(dev_priv); |
2809 | ||
b7cec66d DL |
2810 | return 0; |
2811 | } | |
2812 | ||
53f5e3ca JB |
2813 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2814 | struct drm_display_mode *mode) | |
2815 | { | |
2816 | int i; | |
2817 | ||
2818 | for (i = 0; i < tabs; i++) | |
2819 | seq_putc(m, '\t'); | |
2820 | ||
2821 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2822 | mode->base.id, mode->name, | |
2823 | mode->vrefresh, mode->clock, | |
2824 | mode->hdisplay, mode->hsync_start, | |
2825 | mode->hsync_end, mode->htotal, | |
2826 | mode->vdisplay, mode->vsync_start, | |
2827 | mode->vsync_end, mode->vtotal, | |
2828 | mode->type, mode->flags); | |
2829 | } | |
2830 | ||
2831 | static void intel_encoder_info(struct seq_file *m, | |
2832 | struct intel_crtc *intel_crtc, | |
2833 | struct intel_encoder *intel_encoder) | |
2834 | { | |
36cdd013 DW |
2835 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2836 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2837 | struct drm_crtc *crtc = &intel_crtc->base; |
2838 | struct intel_connector *intel_connector; | |
2839 | struct drm_encoder *encoder; | |
2840 | ||
2841 | encoder = &intel_encoder->base; | |
2842 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2843 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2844 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2845 | struct drm_connector *connector = &intel_connector->base; | |
2846 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2847 | connector->base.id, | |
c23cc417 | 2848 | connector->name, |
53f5e3ca JB |
2849 | drm_get_connector_status_name(connector->status)); |
2850 | if (connector->status == connector_status_connected) { | |
2851 | struct drm_display_mode *mode = &crtc->mode; | |
2852 | seq_printf(m, ", mode:\n"); | |
2853 | intel_seq_print_mode(m, 2, mode); | |
2854 | } else { | |
2855 | seq_putc(m, '\n'); | |
2856 | } | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2861 | { | |
36cdd013 DW |
2862 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2863 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2864 | struct drm_crtc *crtc = &intel_crtc->base; |
2865 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2866 | struct drm_plane_state *plane_state = crtc->primary->state; |
2867 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2868 | |
23a48d53 | 2869 | if (fb) |
5aa8a937 | 2870 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2871 | fb->base.id, plane_state->src_x >> 16, |
2872 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2873 | else |
2874 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2875 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2876 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2877 | } | |
2878 | ||
2879 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2880 | { | |
2881 | struct drm_display_mode *mode = panel->fixed_mode; | |
2882 | ||
2883 | seq_printf(m, "\tfixed mode:\n"); | |
2884 | intel_seq_print_mode(m, 2, mode); | |
2885 | } | |
2886 | ||
2887 | static void intel_dp_info(struct seq_file *m, | |
2888 | struct intel_connector *intel_connector) | |
2889 | { | |
2890 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2891 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2892 | ||
2893 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2894 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2895 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2896 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2897 | |
2898 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2899 | &intel_dp->aux); | |
53f5e3ca JB |
2900 | } |
2901 | ||
9a148a96 LY |
2902 | static void intel_dp_mst_info(struct seq_file *m, |
2903 | struct intel_connector *intel_connector) | |
2904 | { | |
2905 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2906 | struct intel_dp_mst_encoder *intel_mst = | |
2907 | enc_to_mst(&intel_encoder->base); | |
2908 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2909 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2910 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2911 | intel_connector->port); | |
2912 | ||
2913 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2914 | } | |
2915 | ||
53f5e3ca JB |
2916 | static void intel_hdmi_info(struct seq_file *m, |
2917 | struct intel_connector *intel_connector) | |
2918 | { | |
2919 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2920 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2921 | ||
742f491d | 2922 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2923 | } |
2924 | ||
2925 | static void intel_lvds_info(struct seq_file *m, | |
2926 | struct intel_connector *intel_connector) | |
2927 | { | |
2928 | intel_panel_info(m, &intel_connector->panel); | |
2929 | } | |
2930 | ||
2931 | static void intel_connector_info(struct seq_file *m, | |
2932 | struct drm_connector *connector) | |
2933 | { | |
2934 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2935 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2936 | struct drm_display_mode *mode; |
53f5e3ca JB |
2937 | |
2938 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2939 | connector->base.id, connector->name, |
53f5e3ca JB |
2940 | drm_get_connector_status_name(connector->status)); |
2941 | if (connector->status == connector_status_connected) { | |
2942 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2943 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2944 | connector->display_info.width_mm, | |
2945 | connector->display_info.height_mm); | |
2946 | seq_printf(m, "\tsubpixel order: %s\n", | |
2947 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2948 | seq_printf(m, "\tCEA rev: %d\n", | |
2949 | connector->display_info.cea_rev); | |
2950 | } | |
ee648a74 | 2951 | |
77d1f615 | 2952 | if (!intel_encoder) |
ee648a74 ML |
2953 | return; |
2954 | ||
2955 | switch (connector->connector_type) { | |
2956 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2957 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
2958 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2959 | intel_dp_mst_info(m, intel_connector); | |
2960 | else | |
2961 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
2962 | break; |
2963 | case DRM_MODE_CONNECTOR_LVDS: | |
2964 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2965 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2966 | break; |
2967 | case DRM_MODE_CONNECTOR_HDMIA: | |
2968 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
7e732cac | 2969 | intel_encoder->type == INTEL_OUTPUT_DDI) |
ee648a74 ML |
2970 | intel_hdmi_info(m, intel_connector); |
2971 | break; | |
2972 | default: | |
2973 | break; | |
36cd7444 | 2974 | } |
53f5e3ca | 2975 | |
f103fc7d JB |
2976 | seq_printf(m, "\tmodes:\n"); |
2977 | list_for_each_entry(mode, &connector->modes, head) | |
2978 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2979 | } |
2980 | ||
3abc4e09 RF |
2981 | static const char *plane_type(enum drm_plane_type type) |
2982 | { | |
2983 | switch (type) { | |
2984 | case DRM_PLANE_TYPE_OVERLAY: | |
2985 | return "OVL"; | |
2986 | case DRM_PLANE_TYPE_PRIMARY: | |
2987 | return "PRI"; | |
2988 | case DRM_PLANE_TYPE_CURSOR: | |
2989 | return "CUR"; | |
2990 | /* | |
2991 | * Deliberately omitting default: to generate compiler warnings | |
2992 | * when a new drm_plane_type gets added. | |
2993 | */ | |
2994 | } | |
2995 | ||
2996 | return "unknown"; | |
2997 | } | |
2998 | ||
2999 | static const char *plane_rotation(unsigned int rotation) | |
3000 | { | |
3001 | static char buf[48]; | |
3002 | /* | |
c2c446ad | 3003 | * According to doc only one DRM_MODE_ROTATE_ is allowed but this |
3abc4e09 RF |
3004 | * will print them all to visualize if the values are misused |
3005 | */ | |
3006 | snprintf(buf, sizeof(buf), | |
3007 | "%s%s%s%s%s%s(0x%08x)", | |
c2c446ad RF |
3008 | (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", |
3009 | (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", | |
3010 | (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", | |
3011 | (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", | |
3012 | (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", | |
3013 | (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3014 | rotation); |
3015 | ||
3016 | return buf; | |
3017 | } | |
3018 | ||
3019 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3020 | { | |
36cdd013 DW |
3021 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3022 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3023 | struct intel_plane *intel_plane; |
3024 | ||
3025 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3026 | struct drm_plane_state *state; | |
3027 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3028 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3029 | |
3030 | if (!plane->state) { | |
3031 | seq_puts(m, "plane->state is NULL!\n"); | |
3032 | continue; | |
3033 | } | |
3034 | ||
3035 | state = plane->state; | |
3036 | ||
90844f00 | 3037 | if (state->fb) { |
438b74a5 VS |
3038 | drm_get_format_name(state->fb->format->format, |
3039 | &format_name); | |
90844f00 | 3040 | } else { |
b3c11ac2 | 3041 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3042 | } |
3043 | ||
3abc4e09 RF |
3044 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3045 | plane->base.id, | |
3046 | plane_type(intel_plane->base.type), | |
3047 | state->crtc_x, state->crtc_y, | |
3048 | state->crtc_w, state->crtc_h, | |
3049 | (state->src_x >> 16), | |
3050 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3051 | (state->src_y >> 16), | |
3052 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3053 | (state->src_w >> 16), | |
3054 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3055 | (state->src_h >> 16), | |
3056 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3057 | format_name.str, |
3abc4e09 RF |
3058 | plane_rotation(state->rotation)); |
3059 | } | |
3060 | } | |
3061 | ||
3062 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3063 | { | |
3064 | struct intel_crtc_state *pipe_config; | |
3065 | int num_scalers = intel_crtc->num_scalers; | |
3066 | int i; | |
3067 | ||
3068 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3069 | ||
3070 | /* Not all platformas have a scaler */ | |
3071 | if (num_scalers) { | |
3072 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3073 | num_scalers, | |
3074 | pipe_config->scaler_state.scaler_users, | |
3075 | pipe_config->scaler_state.scaler_id); | |
3076 | ||
58415918 | 3077 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3078 | struct intel_scaler *sc = |
3079 | &pipe_config->scaler_state.scalers[i]; | |
3080 | ||
3081 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3082 | i, yesno(sc->in_use), sc->mode); | |
3083 | } | |
3084 | seq_puts(m, "\n"); | |
3085 | } else { | |
3086 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3087 | } | |
3088 | } | |
3089 | ||
53f5e3ca JB |
3090 | static int i915_display_info(struct seq_file *m, void *unused) |
3091 | { | |
36cdd013 DW |
3092 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3093 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3094 | struct intel_crtc *crtc; |
53f5e3ca | 3095 | struct drm_connector *connector; |
3f6a5e1e | 3096 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3097 | |
b0e5ddf3 | 3098 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3099 | seq_printf(m, "CRTC info\n"); |
3100 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3101 | for_each_intel_crtc(dev, crtc) { |
f77076c9 | 3102 | struct intel_crtc_state *pipe_config; |
53f5e3ca | 3103 | |
3f6a5e1e | 3104 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3105 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3106 | ||
3abc4e09 | 3107 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3108 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3109 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3110 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3111 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3112 | ||
f77076c9 | 3113 | if (pipe_config->base.active) { |
cd5dcbf1 VS |
3114 | struct intel_plane *cursor = |
3115 | to_intel_plane(crtc->base.cursor); | |
3116 | ||
065f2ec2 CW |
3117 | intel_crtc_info(m, crtc); |
3118 | ||
cd5dcbf1 VS |
3119 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", |
3120 | yesno(cursor->base.state->visible), | |
3121 | cursor->base.state->crtc_x, | |
3122 | cursor->base.state->crtc_y, | |
3123 | cursor->base.state->crtc_w, | |
3124 | cursor->base.state->crtc_h, | |
3125 | cursor->cursor.base); | |
3abc4e09 RF |
3126 | intel_scaler_info(m, crtc); |
3127 | intel_plane_info(m, crtc); | |
a23dc658 | 3128 | } |
cace841c DV |
3129 | |
3130 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3131 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3132 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3133 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3134 | } |
3135 | ||
3136 | seq_printf(m, "\n"); | |
3137 | seq_printf(m, "Connector info\n"); | |
3138 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3139 | mutex_lock(&dev->mode_config.mutex); |
3140 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3141 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3142 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3143 | drm_connector_list_iter_end(&conn_iter); |
3144 | mutex_unlock(&dev->mode_config.mutex); | |
3145 | ||
b0e5ddf3 | 3146 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3147 | |
3148 | return 0; | |
3149 | } | |
3150 | ||
1b36595f CW |
3151 | static int i915_engine_info(struct seq_file *m, void *unused) |
3152 | { | |
3153 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3154 | struct intel_engine_cs *engine; | |
3b3f1650 | 3155 | enum intel_engine_id id; |
f636edb2 | 3156 | struct drm_printer p; |
1b36595f | 3157 | |
9c870d03 CW |
3158 | intel_runtime_pm_get(dev_priv); |
3159 | ||
f73b5674 CW |
3160 | seq_printf(m, "GT awake? %s\n", |
3161 | yesno(dev_priv->gt.awake)); | |
3162 | seq_printf(m, "Global active requests: %d\n", | |
3163 | dev_priv->gt.active_requests); | |
f577a03b LL |
3164 | seq_printf(m, "CS timestamp frequency: %u kHz\n", |
3165 | dev_priv->info.cs_timestamp_frequency_khz); | |
f73b5674 | 3166 | |
f636edb2 CW |
3167 | p = drm_seq_file_printer(m); |
3168 | for_each_engine(engine, dev_priv, id) | |
0db18b17 | 3169 | intel_engine_dump(engine, &p, "%s\n", engine->name); |
1b36595f | 3170 | |
9c870d03 CW |
3171 | intel_runtime_pm_put(dev_priv); |
3172 | ||
1b36595f CW |
3173 | return 0; |
3174 | } | |
3175 | ||
c5418a8b CW |
3176 | static int i915_shrinker_info(struct seq_file *m, void *unused) |
3177 | { | |
3178 | struct drm_i915_private *i915 = node_to_i915(m->private); | |
3179 | ||
3180 | seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks); | |
3181 | seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch); | |
3182 | ||
3183 | return 0; | |
3184 | } | |
3185 | ||
728e29d7 DV |
3186 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3187 | { | |
36cdd013 DW |
3188 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3189 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3190 | int i; |
3191 | ||
3192 | drm_modeset_lock_all(dev); | |
3193 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3194 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3195 | ||
3196 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3197 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3198 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3199 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3200 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3201 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3202 | pll->state.hw_state.dpll_md); |
3203 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3204 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3205 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3206 | } |
3207 | drm_modeset_unlock_all(dev); | |
3208 | ||
3209 | return 0; | |
3210 | } | |
3211 | ||
1ed1ef9d | 3212 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3213 | { |
3214 | int i; | |
3215 | int ret; | |
e2f80391 | 3216 | struct intel_engine_cs *engine; |
36cdd013 DW |
3217 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3218 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3219 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3220 | enum intel_engine_id id; |
888b5995 | 3221 | |
888b5995 AS |
3222 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3223 | if (ret) | |
3224 | return ret; | |
3225 | ||
3226 | intel_runtime_pm_get(dev_priv); | |
3227 | ||
33136b06 | 3228 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3229 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3230 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3231 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3232 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3233 | i915_reg_t addr; |
3234 | u32 mask, value, read; | |
2fa60f6d | 3235 | bool ok; |
888b5995 | 3236 | |
33136b06 AS |
3237 | addr = workarounds->reg[i].addr; |
3238 | mask = workarounds->reg[i].mask; | |
3239 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3240 | read = I915_READ(addr); |
3241 | ok = (value & mask) == (read & mask); | |
3242 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3243 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3244 | } |
3245 | ||
3246 | intel_runtime_pm_put(dev_priv); | |
3247 | mutex_unlock(&dev->struct_mutex); | |
3248 | ||
3249 | return 0; | |
3250 | } | |
3251 | ||
d2d4f39b KM |
3252 | static int i915_ipc_status_show(struct seq_file *m, void *data) |
3253 | { | |
3254 | struct drm_i915_private *dev_priv = m->private; | |
3255 | ||
3256 | seq_printf(m, "Isochronous Priority Control: %s\n", | |
3257 | yesno(dev_priv->ipc_enabled)); | |
3258 | return 0; | |
3259 | } | |
3260 | ||
3261 | static int i915_ipc_status_open(struct inode *inode, struct file *file) | |
3262 | { | |
3263 | struct drm_i915_private *dev_priv = inode->i_private; | |
3264 | ||
3265 | if (!HAS_IPC(dev_priv)) | |
3266 | return -ENODEV; | |
3267 | ||
3268 | return single_open(file, i915_ipc_status_show, dev_priv); | |
3269 | } | |
3270 | ||
3271 | static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, | |
3272 | size_t len, loff_t *offp) | |
3273 | { | |
3274 | struct seq_file *m = file->private_data; | |
3275 | struct drm_i915_private *dev_priv = m->private; | |
3276 | int ret; | |
3277 | bool enable; | |
3278 | ||
3279 | ret = kstrtobool_from_user(ubuf, len, &enable); | |
3280 | if (ret < 0) | |
3281 | return ret; | |
3282 | ||
3283 | intel_runtime_pm_get(dev_priv); | |
3284 | if (!dev_priv->ipc_enabled && enable) | |
3285 | DRM_INFO("Enabling IPC: WM will be proper only after next commit\n"); | |
3286 | dev_priv->wm.distrust_bios_wm = true; | |
3287 | dev_priv->ipc_enabled = enable; | |
3288 | intel_enable_ipc(dev_priv); | |
3289 | intel_runtime_pm_put(dev_priv); | |
3290 | ||
3291 | return len; | |
3292 | } | |
3293 | ||
3294 | static const struct file_operations i915_ipc_status_fops = { | |
3295 | .owner = THIS_MODULE, | |
3296 | .open = i915_ipc_status_open, | |
3297 | .read = seq_read, | |
3298 | .llseek = seq_lseek, | |
3299 | .release = single_release, | |
3300 | .write = i915_ipc_status_write | |
3301 | }; | |
3302 | ||
c5511e44 DL |
3303 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3304 | { | |
36cdd013 DW |
3305 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3306 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3307 | struct skl_ddb_allocation *ddb; |
3308 | struct skl_ddb_entry *entry; | |
3309 | enum pipe pipe; | |
3310 | int plane; | |
3311 | ||
36cdd013 | 3312 | if (INTEL_GEN(dev_priv) < 9) |
ab309a6a | 3313 | return -ENODEV; |
2fcffe19 | 3314 | |
c5511e44 DL |
3315 | drm_modeset_lock_all(dev); |
3316 | ||
3317 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3318 | ||
3319 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3320 | ||
3321 | for_each_pipe(dev_priv, pipe) { | |
3322 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3323 | ||
8b364b41 | 3324 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3325 | entry = &ddb->plane[pipe][plane]; |
3326 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3327 | entry->start, entry->end, | |
3328 | skl_ddb_entry_size(entry)); | |
3329 | } | |
3330 | ||
4969d33e | 3331 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3332 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3333 | entry->end, skl_ddb_entry_size(entry)); | |
3334 | } | |
3335 | ||
3336 | drm_modeset_unlock_all(dev); | |
3337 | ||
3338 | return 0; | |
3339 | } | |
3340 | ||
a54746e3 | 3341 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3342 | struct drm_device *dev, |
3343 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3344 | { |
fac5e23e | 3345 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3346 | struct i915_drrs *drrs = &dev_priv->drrs; |
3347 | int vrefresh = 0; | |
26875fe5 | 3348 | struct drm_connector *connector; |
3f6a5e1e | 3349 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3350 | |
3f6a5e1e DV |
3351 | drm_connector_list_iter_begin(dev, &conn_iter); |
3352 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3353 | if (connector->state->crtc != &intel_crtc->base) |
3354 | continue; | |
3355 | ||
3356 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3357 | } |
3f6a5e1e | 3358 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3359 | |
3360 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3361 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3362 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3363 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3364 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3365 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3366 | else | |
3367 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3368 | ||
3369 | seq_puts(m, "\n\n"); | |
3370 | ||
f77076c9 | 3371 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3372 | struct intel_panel *panel; |
3373 | ||
3374 | mutex_lock(&drrs->mutex); | |
3375 | /* DRRS Supported */ | |
3376 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3377 | ||
3378 | /* disable_drrs() will make drrs->dp NULL */ | |
3379 | if (!drrs->dp) { | |
3380 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3381 | mutex_unlock(&drrs->mutex); | |
3382 | return; | |
3383 | } | |
3384 | ||
3385 | panel = &drrs->dp->attached_connector->panel; | |
3386 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3387 | drrs->busy_frontbuffer_bits); | |
3388 | ||
3389 | seq_puts(m, "\n\t\t"); | |
3390 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3391 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3392 | vrefresh = panel->fixed_mode->vrefresh; | |
3393 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3394 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3395 | vrefresh = panel->downclock_mode->vrefresh; | |
3396 | } else { | |
3397 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3398 | drrs->refresh_rate_type); | |
3399 | mutex_unlock(&drrs->mutex); | |
3400 | return; | |
3401 | } | |
3402 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3403 | ||
3404 | seq_puts(m, "\n\t\t"); | |
3405 | mutex_unlock(&drrs->mutex); | |
3406 | } else { | |
3407 | /* DRRS not supported. Print the VBT parameter*/ | |
3408 | seq_puts(m, "\tDRRS Supported : No"); | |
3409 | } | |
3410 | seq_puts(m, "\n"); | |
3411 | } | |
3412 | ||
3413 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3414 | { | |
36cdd013 DW |
3415 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3416 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3417 | struct intel_crtc *intel_crtc; |
3418 | int active_crtc_cnt = 0; | |
3419 | ||
26875fe5 | 3420 | drm_modeset_lock_all(dev); |
a54746e3 | 3421 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3422 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3423 | active_crtc_cnt++; |
3424 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3425 | ||
3426 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3427 | } | |
a54746e3 | 3428 | } |
26875fe5 | 3429 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3430 | |
3431 | if (!active_crtc_cnt) | |
3432 | seq_puts(m, "No active crtc found\n"); | |
3433 | ||
3434 | return 0; | |
3435 | } | |
3436 | ||
11bed958 DA |
3437 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3438 | { | |
36cdd013 DW |
3439 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3440 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3441 | struct intel_encoder *intel_encoder; |
3442 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3443 | struct drm_connector *connector; |
3f6a5e1e | 3444 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3445 | |
3f6a5e1e DV |
3446 | drm_connector_list_iter_begin(dev, &conn_iter); |
3447 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3448 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3449 | continue; |
b6dabe3b ML |
3450 | |
3451 | intel_encoder = intel_attached_encoder(connector); | |
3452 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3453 | continue; | |
3454 | ||
3455 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3456 | if (!intel_dig_port->dp.can_mst) |
3457 | continue; | |
b6dabe3b | 3458 | |
40ae80cc | 3459 | seq_printf(m, "MST Source Port %c\n", |
8f4f2797 | 3460 | port_name(intel_dig_port->base.port)); |
11bed958 DA |
3461 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3462 | } | |
3f6a5e1e DV |
3463 | drm_connector_list_iter_end(&conn_iter); |
3464 | ||
11bed958 DA |
3465 | return 0; |
3466 | } | |
3467 | ||
eb3394fa | 3468 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3469 | const char __user *ubuf, |
3470 | size_t len, loff_t *offp) | |
eb3394fa TP |
3471 | { |
3472 | char *input_buffer; | |
3473 | int status = 0; | |
eb3394fa TP |
3474 | struct drm_device *dev; |
3475 | struct drm_connector *connector; | |
3f6a5e1e | 3476 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3477 | struct intel_dp *intel_dp; |
3478 | int val = 0; | |
3479 | ||
9aaffa34 | 3480 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3481 | |
eb3394fa TP |
3482 | if (len == 0) |
3483 | return 0; | |
3484 | ||
261aeba8 GT |
3485 | input_buffer = memdup_user_nul(ubuf, len); |
3486 | if (IS_ERR(input_buffer)) | |
3487 | return PTR_ERR(input_buffer); | |
eb3394fa | 3488 | |
eb3394fa TP |
3489 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3490 | ||
3f6a5e1e DV |
3491 | drm_connector_list_iter_begin(dev, &conn_iter); |
3492 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3493 | struct intel_encoder *encoder; |
3494 | ||
eb3394fa TP |
3495 | if (connector->connector_type != |
3496 | DRM_MODE_CONNECTOR_DisplayPort) | |
3497 | continue; | |
3498 | ||
a874b6a3 ML |
3499 | encoder = to_intel_encoder(connector->encoder); |
3500 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3501 | continue; | |
3502 | ||
3503 | if (encoder && connector->status == connector_status_connected) { | |
3504 | intel_dp = enc_to_intel_dp(&encoder->base); | |
eb3394fa TP |
3505 | status = kstrtoint(input_buffer, 10, &val); |
3506 | if (status < 0) | |
3f6a5e1e | 3507 | break; |
eb3394fa TP |
3508 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3509 | /* To prevent erroneous activation of the compliance | |
3510 | * testing code, only accept an actual value of 1 here | |
3511 | */ | |
3512 | if (val == 1) | |
c1617abc | 3513 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3514 | else |
c1617abc | 3515 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3516 | } |
3517 | } | |
3f6a5e1e | 3518 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3519 | kfree(input_buffer); |
3520 | if (status < 0) | |
3521 | return status; | |
3522 | ||
3523 | *offp += len; | |
3524 | return len; | |
3525 | } | |
3526 | ||
3527 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3528 | { | |
3529 | struct drm_device *dev = m->private; | |
3530 | struct drm_connector *connector; | |
3f6a5e1e | 3531 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3532 | struct intel_dp *intel_dp; |
3533 | ||
3f6a5e1e DV |
3534 | drm_connector_list_iter_begin(dev, &conn_iter); |
3535 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3536 | struct intel_encoder *encoder; |
3537 | ||
eb3394fa TP |
3538 | if (connector->connector_type != |
3539 | DRM_MODE_CONNECTOR_DisplayPort) | |
3540 | continue; | |
3541 | ||
a874b6a3 ML |
3542 | encoder = to_intel_encoder(connector->encoder); |
3543 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3544 | continue; | |
3545 | ||
3546 | if (encoder && connector->status == connector_status_connected) { | |
3547 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3548 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3549 | seq_puts(m, "1"); |
3550 | else | |
3551 | seq_puts(m, "0"); | |
3552 | } else | |
3553 | seq_puts(m, "0"); | |
3554 | } | |
3f6a5e1e | 3555 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3556 | |
3557 | return 0; | |
3558 | } | |
3559 | ||
3560 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3561 | struct file *file) |
eb3394fa | 3562 | { |
36cdd013 | 3563 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3564 | |
36cdd013 DW |
3565 | return single_open(file, i915_displayport_test_active_show, |
3566 | &dev_priv->drm); | |
eb3394fa TP |
3567 | } |
3568 | ||
3569 | static const struct file_operations i915_displayport_test_active_fops = { | |
3570 | .owner = THIS_MODULE, | |
3571 | .open = i915_displayport_test_active_open, | |
3572 | .read = seq_read, | |
3573 | .llseek = seq_lseek, | |
3574 | .release = single_release, | |
3575 | .write = i915_displayport_test_active_write | |
3576 | }; | |
3577 | ||
3578 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3579 | { | |
3580 | struct drm_device *dev = m->private; | |
3581 | struct drm_connector *connector; | |
3f6a5e1e | 3582 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3583 | struct intel_dp *intel_dp; |
3584 | ||
3f6a5e1e DV |
3585 | drm_connector_list_iter_begin(dev, &conn_iter); |
3586 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3587 | struct intel_encoder *encoder; |
3588 | ||
eb3394fa TP |
3589 | if (connector->connector_type != |
3590 | DRM_MODE_CONNECTOR_DisplayPort) | |
3591 | continue; | |
3592 | ||
a874b6a3 ML |
3593 | encoder = to_intel_encoder(connector->encoder); |
3594 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3595 | continue; | |
3596 | ||
3597 | if (encoder && connector->status == connector_status_connected) { | |
3598 | intel_dp = enc_to_intel_dp(&encoder->base); | |
b48a5ba9 MN |
3599 | if (intel_dp->compliance.test_type == |
3600 | DP_TEST_LINK_EDID_READ) | |
3601 | seq_printf(m, "%lx", | |
3602 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3603 | else if (intel_dp->compliance.test_type == |
3604 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3605 | seq_printf(m, "hdisplay: %d\n", | |
3606 | intel_dp->compliance.test_data.hdisplay); | |
3607 | seq_printf(m, "vdisplay: %d\n", | |
3608 | intel_dp->compliance.test_data.vdisplay); | |
3609 | seq_printf(m, "bpc: %u\n", | |
3610 | intel_dp->compliance.test_data.bpc); | |
3611 | } | |
eb3394fa TP |
3612 | } else |
3613 | seq_puts(m, "0"); | |
3614 | } | |
3f6a5e1e | 3615 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3616 | |
3617 | return 0; | |
3618 | } | |
3619 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3620 | struct file *file) |
eb3394fa | 3621 | { |
36cdd013 | 3622 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3623 | |
36cdd013 DW |
3624 | return single_open(file, i915_displayport_test_data_show, |
3625 | &dev_priv->drm); | |
eb3394fa TP |
3626 | } |
3627 | ||
3628 | static const struct file_operations i915_displayport_test_data_fops = { | |
3629 | .owner = THIS_MODULE, | |
3630 | .open = i915_displayport_test_data_open, | |
3631 | .read = seq_read, | |
3632 | .llseek = seq_lseek, | |
3633 | .release = single_release | |
3634 | }; | |
3635 | ||
3636 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3637 | { | |
3638 | struct drm_device *dev = m->private; | |
3639 | struct drm_connector *connector; | |
3f6a5e1e | 3640 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3641 | struct intel_dp *intel_dp; |
3642 | ||
3f6a5e1e DV |
3643 | drm_connector_list_iter_begin(dev, &conn_iter); |
3644 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3645 | struct intel_encoder *encoder; |
3646 | ||
eb3394fa TP |
3647 | if (connector->connector_type != |
3648 | DRM_MODE_CONNECTOR_DisplayPort) | |
3649 | continue; | |
3650 | ||
a874b6a3 ML |
3651 | encoder = to_intel_encoder(connector->encoder); |
3652 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3653 | continue; | |
3654 | ||
3655 | if (encoder && connector->status == connector_status_connected) { | |
3656 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3657 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3658 | } else |
3659 | seq_puts(m, "0"); | |
3660 | } | |
3f6a5e1e | 3661 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3662 | |
3663 | return 0; | |
3664 | } | |
3665 | ||
3666 | static int i915_displayport_test_type_open(struct inode *inode, | |
3667 | struct file *file) | |
3668 | { | |
36cdd013 | 3669 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3670 | |
36cdd013 DW |
3671 | return single_open(file, i915_displayport_test_type_show, |
3672 | &dev_priv->drm); | |
eb3394fa TP |
3673 | } |
3674 | ||
3675 | static const struct file_operations i915_displayport_test_type_fops = { | |
3676 | .owner = THIS_MODULE, | |
3677 | .open = i915_displayport_test_type_open, | |
3678 | .read = seq_read, | |
3679 | .llseek = seq_lseek, | |
3680 | .release = single_release | |
3681 | }; | |
3682 | ||
97e94b22 | 3683 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3684 | { |
36cdd013 DW |
3685 | struct drm_i915_private *dev_priv = m->private; |
3686 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3687 | int level; |
de38b95c VS |
3688 | int num_levels; |
3689 | ||
36cdd013 | 3690 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3691 | num_levels = 3; |
36cdd013 | 3692 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3693 | num_levels = 1; |
04548cba VS |
3694 | else if (IS_G4X(dev_priv)) |
3695 | num_levels = 3; | |
de38b95c | 3696 | else |
5db94019 | 3697 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3698 | |
3699 | drm_modeset_lock_all(dev); | |
3700 | ||
3701 | for (level = 0; level < num_levels; level++) { | |
3702 | unsigned int latency = wm[level]; | |
3703 | ||
97e94b22 DL |
3704 | /* |
3705 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3706 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3707 | */ |
04548cba VS |
3708 | if (INTEL_GEN(dev_priv) >= 9 || |
3709 | IS_VALLEYVIEW(dev_priv) || | |
3710 | IS_CHERRYVIEW(dev_priv) || | |
3711 | IS_G4X(dev_priv)) | |
97e94b22 DL |
3712 | latency *= 10; |
3713 | else if (level > 0) | |
369a1342 VS |
3714 | latency *= 5; |
3715 | ||
3716 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3717 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3718 | } |
3719 | ||
3720 | drm_modeset_unlock_all(dev); | |
3721 | } | |
3722 | ||
3723 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3724 | { | |
36cdd013 | 3725 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3726 | const uint16_t *latencies; |
3727 | ||
36cdd013 | 3728 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3729 | latencies = dev_priv->wm.skl_latency; |
3730 | else | |
36cdd013 | 3731 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3732 | |
97e94b22 | 3733 | wm_latency_show(m, latencies); |
369a1342 VS |
3734 | |
3735 | return 0; | |
3736 | } | |
3737 | ||
3738 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3739 | { | |
36cdd013 | 3740 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3741 | const uint16_t *latencies; |
3742 | ||
36cdd013 | 3743 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3744 | latencies = dev_priv->wm.skl_latency; |
3745 | else | |
36cdd013 | 3746 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3747 | |
97e94b22 | 3748 | wm_latency_show(m, latencies); |
369a1342 VS |
3749 | |
3750 | return 0; | |
3751 | } | |
3752 | ||
3753 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3754 | { | |
36cdd013 | 3755 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3756 | const uint16_t *latencies; |
3757 | ||
36cdd013 | 3758 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3759 | latencies = dev_priv->wm.skl_latency; |
3760 | else | |
36cdd013 | 3761 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3762 | |
97e94b22 | 3763 | wm_latency_show(m, latencies); |
369a1342 VS |
3764 | |
3765 | return 0; | |
3766 | } | |
3767 | ||
3768 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3769 | { | |
36cdd013 | 3770 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3771 | |
04548cba | 3772 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
369a1342 VS |
3773 | return -ENODEV; |
3774 | ||
36cdd013 | 3775 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3776 | } |
3777 | ||
3778 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3779 | { | |
36cdd013 | 3780 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3781 | |
36cdd013 | 3782 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3783 | return -ENODEV; |
3784 | ||
36cdd013 | 3785 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3786 | } |
3787 | ||
3788 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3789 | { | |
36cdd013 | 3790 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3791 | |
36cdd013 | 3792 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3793 | return -ENODEV; |
3794 | ||
36cdd013 | 3795 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3796 | } |
3797 | ||
3798 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3799 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3800 | { |
3801 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3802 | struct drm_i915_private *dev_priv = m->private; |
3803 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3804 | uint16_t new[8] = { 0 }; |
de38b95c | 3805 | int num_levels; |
369a1342 VS |
3806 | int level; |
3807 | int ret; | |
3808 | char tmp[32]; | |
3809 | ||
36cdd013 | 3810 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3811 | num_levels = 3; |
36cdd013 | 3812 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3813 | num_levels = 1; |
04548cba VS |
3814 | else if (IS_G4X(dev_priv)) |
3815 | num_levels = 3; | |
de38b95c | 3816 | else |
5db94019 | 3817 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 3818 | |
369a1342 VS |
3819 | if (len >= sizeof(tmp)) |
3820 | return -EINVAL; | |
3821 | ||
3822 | if (copy_from_user(tmp, ubuf, len)) | |
3823 | return -EFAULT; | |
3824 | ||
3825 | tmp[len] = '\0'; | |
3826 | ||
97e94b22 DL |
3827 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3828 | &new[0], &new[1], &new[2], &new[3], | |
3829 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3830 | if (ret != num_levels) |
3831 | return -EINVAL; | |
3832 | ||
3833 | drm_modeset_lock_all(dev); | |
3834 | ||
3835 | for (level = 0; level < num_levels; level++) | |
3836 | wm[level] = new[level]; | |
3837 | ||
3838 | drm_modeset_unlock_all(dev); | |
3839 | ||
3840 | return len; | |
3841 | } | |
3842 | ||
3843 | ||
3844 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3845 | size_t len, loff_t *offp) | |
3846 | { | |
3847 | struct seq_file *m = file->private_data; | |
36cdd013 | 3848 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3849 | uint16_t *latencies; |
369a1342 | 3850 | |
36cdd013 | 3851 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3852 | latencies = dev_priv->wm.skl_latency; |
3853 | else | |
36cdd013 | 3854 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
3855 | |
3856 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3857 | } |
3858 | ||
3859 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3860 | size_t len, loff_t *offp) | |
3861 | { | |
3862 | struct seq_file *m = file->private_data; | |
36cdd013 | 3863 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3864 | uint16_t *latencies; |
369a1342 | 3865 | |
36cdd013 | 3866 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3867 | latencies = dev_priv->wm.skl_latency; |
3868 | else | |
36cdd013 | 3869 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
3870 | |
3871 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3872 | } |
3873 | ||
3874 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3875 | size_t len, loff_t *offp) | |
3876 | { | |
3877 | struct seq_file *m = file->private_data; | |
36cdd013 | 3878 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3879 | uint16_t *latencies; |
3880 | ||
36cdd013 | 3881 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3882 | latencies = dev_priv->wm.skl_latency; |
3883 | else | |
36cdd013 | 3884 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3885 | |
97e94b22 | 3886 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
3887 | } |
3888 | ||
3889 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3890 | .owner = THIS_MODULE, | |
3891 | .open = pri_wm_latency_open, | |
3892 | .read = seq_read, | |
3893 | .llseek = seq_lseek, | |
3894 | .release = single_release, | |
3895 | .write = pri_wm_latency_write | |
3896 | }; | |
3897 | ||
3898 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3899 | .owner = THIS_MODULE, | |
3900 | .open = spr_wm_latency_open, | |
3901 | .read = seq_read, | |
3902 | .llseek = seq_lseek, | |
3903 | .release = single_release, | |
3904 | .write = spr_wm_latency_write | |
3905 | }; | |
3906 | ||
3907 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3908 | .owner = THIS_MODULE, | |
3909 | .open = cur_wm_latency_open, | |
3910 | .read = seq_read, | |
3911 | .llseek = seq_lseek, | |
3912 | .release = single_release, | |
3913 | .write = cur_wm_latency_write | |
3914 | }; | |
3915 | ||
647416f9 KC |
3916 | static int |
3917 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3918 | { |
36cdd013 | 3919 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 3920 | |
d98c52cf | 3921 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 3922 | |
647416f9 | 3923 | return 0; |
f3cd474b CW |
3924 | } |
3925 | ||
647416f9 KC |
3926 | static int |
3927 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3928 | { |
598b6b5a CW |
3929 | struct drm_i915_private *i915 = data; |
3930 | struct intel_engine_cs *engine; | |
3931 | unsigned int tmp; | |
d46c0517 | 3932 | |
b8d24a06 MK |
3933 | /* |
3934 | * There is no safeguard against this debugfs entry colliding | |
3935 | * with the hangcheck calling same i915_handle_error() in | |
3936 | * parallel, causing an explosion. For now we assume that the | |
3937 | * test harness is responsible enough not to inject gpu hangs | |
3938 | * while it is writing to 'i915_wedged' | |
3939 | */ | |
3940 | ||
598b6b5a | 3941 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
3942 | return -EAGAIN; |
3943 | ||
598b6b5a CW |
3944 | for_each_engine_masked(engine, i915, val, tmp) { |
3945 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
3946 | engine->hangcheck.stalled = true; | |
3947 | } | |
3948 | ||
3949 | i915_handle_error(i915, val, "Manually setting wedged to %llu", val); | |
d46c0517 | 3950 | |
598b6b5a | 3951 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
3952 | I915_RESET_HANDOFF, |
3953 | TASK_UNINTERRUPTIBLE); | |
3954 | ||
647416f9 | 3955 | return 0; |
f3cd474b CW |
3956 | } |
3957 | ||
647416f9 KC |
3958 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3959 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3960 | "%llu\n"); |
f3cd474b | 3961 | |
64486ae7 CW |
3962 | static int |
3963 | fault_irq_set(struct drm_i915_private *i915, | |
3964 | unsigned long *irq, | |
3965 | unsigned long val) | |
3966 | { | |
3967 | int err; | |
3968 | ||
3969 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
3970 | if (err) | |
3971 | return err; | |
3972 | ||
3973 | err = i915_gem_wait_for_idle(i915, | |
3974 | I915_WAIT_LOCKED | | |
3975 | I915_WAIT_INTERRUPTIBLE); | |
3976 | if (err) | |
3977 | goto err_unlock; | |
3978 | ||
64486ae7 CW |
3979 | *irq = val; |
3980 | mutex_unlock(&i915->drm.struct_mutex); | |
3981 | ||
3982 | /* Flush idle worker to disarm irq */ | |
7c26240e | 3983 | drain_delayed_work(&i915->gt.idle_work); |
64486ae7 CW |
3984 | |
3985 | return 0; | |
3986 | ||
3987 | err_unlock: | |
3988 | mutex_unlock(&i915->drm.struct_mutex); | |
3989 | return err; | |
3990 | } | |
3991 | ||
094f9a54 CW |
3992 | static int |
3993 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3994 | { | |
36cdd013 | 3995 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
3996 | |
3997 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3998 | return 0; | |
3999 | } | |
4000 | ||
4001 | static int | |
4002 | i915_ring_missed_irq_set(void *data, u64 val) | |
4003 | { | |
64486ae7 | 4004 | struct drm_i915_private *i915 = data; |
094f9a54 | 4005 | |
64486ae7 | 4006 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4007 | } |
4008 | ||
4009 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4010 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4011 | "0x%08llx\n"); | |
4012 | ||
4013 | static int | |
4014 | i915_ring_test_irq_get(void *data, u64 *val) | |
4015 | { | |
36cdd013 | 4016 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4017 | |
4018 | *val = dev_priv->gpu_error.test_irq_rings; | |
4019 | ||
4020 | return 0; | |
4021 | } | |
4022 | ||
4023 | static int | |
4024 | i915_ring_test_irq_set(void *data, u64 val) | |
4025 | { | |
64486ae7 | 4026 | struct drm_i915_private *i915 = data; |
094f9a54 | 4027 | |
64486ae7 | 4028 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4029 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4030 | |
64486ae7 | 4031 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4032 | } |
4033 | ||
4034 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4035 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4036 | "0x%08llx\n"); | |
4037 | ||
b4a0b32d CW |
4038 | #define DROP_UNBOUND BIT(0) |
4039 | #define DROP_BOUND BIT(1) | |
4040 | #define DROP_RETIRE BIT(2) | |
4041 | #define DROP_ACTIVE BIT(3) | |
4042 | #define DROP_FREED BIT(4) | |
4043 | #define DROP_SHRINK_ALL BIT(5) | |
4044 | #define DROP_IDLE BIT(6) | |
fbbd37b3 CW |
4045 | #define DROP_ALL (DROP_UNBOUND | \ |
4046 | DROP_BOUND | \ | |
4047 | DROP_RETIRE | \ | |
4048 | DROP_ACTIVE | \ | |
8eadc19b | 4049 | DROP_FREED | \ |
b4a0b32d CW |
4050 | DROP_SHRINK_ALL |\ |
4051 | DROP_IDLE) | |
647416f9 KC |
4052 | static int |
4053 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4054 | { |
647416f9 | 4055 | *val = DROP_ALL; |
dd624afd | 4056 | |
647416f9 | 4057 | return 0; |
dd624afd CW |
4058 | } |
4059 | ||
647416f9 KC |
4060 | static int |
4061 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4062 | { |
36cdd013 DW |
4063 | struct drm_i915_private *dev_priv = data; |
4064 | struct drm_device *dev = &dev_priv->drm; | |
00c26cf9 | 4065 | int ret = 0; |
dd624afd | 4066 | |
b4a0b32d CW |
4067 | DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", |
4068 | val, val & DROP_ALL); | |
dd624afd CW |
4069 | |
4070 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4071 | * on ioctls on -EAGAIN. */ | |
00c26cf9 CW |
4072 | if (val & (DROP_ACTIVE | DROP_RETIRE)) { |
4073 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
dd624afd | 4074 | if (ret) |
00c26cf9 | 4075 | return ret; |
dd624afd | 4076 | |
00c26cf9 CW |
4077 | if (val & DROP_ACTIVE) |
4078 | ret = i915_gem_wait_for_idle(dev_priv, | |
4079 | I915_WAIT_INTERRUPTIBLE | | |
4080 | I915_WAIT_LOCKED); | |
4081 | ||
4082 | if (val & DROP_RETIRE) | |
4083 | i915_gem_retire_requests(dev_priv); | |
4084 | ||
4085 | mutex_unlock(&dev->struct_mutex); | |
4086 | } | |
dd624afd | 4087 | |
d92a8cfc | 4088 | fs_reclaim_acquire(GFP_KERNEL); |
21ab4e74 | 4089 | if (val & DROP_BOUND) |
912d572d | 4090 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND); |
4ad72b7f | 4091 | |
21ab4e74 | 4092 | if (val & DROP_UNBOUND) |
912d572d | 4093 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND); |
dd624afd | 4094 | |
8eadc19b CW |
4095 | if (val & DROP_SHRINK_ALL) |
4096 | i915_gem_shrink_all(dev_priv); | |
d92a8cfc | 4097 | fs_reclaim_release(GFP_KERNEL); |
8eadc19b | 4098 | |
b4a0b32d CW |
4099 | if (val & DROP_IDLE) |
4100 | drain_delayed_work(&dev_priv->gt.idle_work); | |
4101 | ||
fbbd37b3 CW |
4102 | if (val & DROP_FREED) { |
4103 | synchronize_rcu(); | |
bdeb9785 | 4104 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4105 | } |
4106 | ||
647416f9 | 4107 | return ret; |
dd624afd CW |
4108 | } |
4109 | ||
647416f9 KC |
4110 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4111 | i915_drop_caches_get, i915_drop_caches_set, | |
4112 | "0x%08llx\n"); | |
dd624afd | 4113 | |
647416f9 KC |
4114 | static int |
4115 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4116 | { |
36cdd013 | 4117 | struct drm_i915_private *dev_priv = data; |
004777cb | 4118 | |
36cdd013 | 4119 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4120 | return -ENODEV; |
4121 | ||
562d9bae | 4122 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit); |
647416f9 | 4123 | return 0; |
358733e9 JB |
4124 | } |
4125 | ||
647416f9 KC |
4126 | static int |
4127 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4128 | { |
36cdd013 | 4129 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4130 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4131 | u32 hw_max, hw_min; |
647416f9 | 4132 | int ret; |
004777cb | 4133 | |
36cdd013 | 4134 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4135 | return -ENODEV; |
358733e9 | 4136 | |
647416f9 | 4137 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4138 | |
9f817501 | 4139 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4140 | if (ret) |
4141 | return ret; | |
4142 | ||
358733e9 JB |
4143 | /* |
4144 | * Turbo will still be enabled, but won't go above the set value. | |
4145 | */ | |
bc4d91f6 | 4146 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4147 | |
562d9bae SAK |
4148 | hw_max = rps->max_freq; |
4149 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4150 | |
562d9bae | 4151 | if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) { |
9f817501 | 4152 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4153 | return -EINVAL; |
0a073b84 JB |
4154 | } |
4155 | ||
562d9bae | 4156 | rps->max_freq_softlimit = val; |
dd0a1aa1 | 4157 | |
9fcee2f7 CW |
4158 | if (intel_set_rps(dev_priv, val)) |
4159 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4160 | |
9f817501 | 4161 | mutex_unlock(&dev_priv->pcu_lock); |
358733e9 | 4162 | |
647416f9 | 4163 | return 0; |
358733e9 JB |
4164 | } |
4165 | ||
647416f9 KC |
4166 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4167 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4168 | "%llu\n"); |
358733e9 | 4169 | |
647416f9 KC |
4170 | static int |
4171 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4172 | { |
36cdd013 | 4173 | struct drm_i915_private *dev_priv = data; |
004777cb | 4174 | |
62e1baa1 | 4175 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4176 | return -ENODEV; |
4177 | ||
562d9bae | 4178 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit); |
647416f9 | 4179 | return 0; |
1523c310 JB |
4180 | } |
4181 | ||
647416f9 KC |
4182 | static int |
4183 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4184 | { |
36cdd013 | 4185 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4186 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4187 | u32 hw_max, hw_min; |
647416f9 | 4188 | int ret; |
004777cb | 4189 | |
62e1baa1 | 4190 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4191 | return -ENODEV; |
1523c310 | 4192 | |
647416f9 | 4193 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4194 | |
9f817501 | 4195 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4196 | if (ret) |
4197 | return ret; | |
4198 | ||
1523c310 JB |
4199 | /* |
4200 | * Turbo will still be enabled, but won't go below the set value. | |
4201 | */ | |
bc4d91f6 | 4202 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4203 | |
562d9bae SAK |
4204 | hw_max = rps->max_freq; |
4205 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4206 | |
36cdd013 | 4207 | if (val < hw_min || |
562d9bae | 4208 | val > hw_max || val > rps->max_freq_softlimit) { |
9f817501 | 4209 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4210 | return -EINVAL; |
0a073b84 | 4211 | } |
dd0a1aa1 | 4212 | |
562d9bae | 4213 | rps->min_freq_softlimit = val; |
dd0a1aa1 | 4214 | |
9fcee2f7 CW |
4215 | if (intel_set_rps(dev_priv, val)) |
4216 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4217 | |
9f817501 | 4218 | mutex_unlock(&dev_priv->pcu_lock); |
1523c310 | 4219 | |
647416f9 | 4220 | return 0; |
1523c310 JB |
4221 | } |
4222 | ||
647416f9 KC |
4223 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4224 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4225 | "%llu\n"); |
1523c310 | 4226 | |
647416f9 KC |
4227 | static int |
4228 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4229 | { |
36cdd013 | 4230 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4231 | u32 snpcr; |
07b7ddd9 | 4232 | |
36cdd013 | 4233 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4234 | return -ENODEV; |
4235 | ||
c8c8fb33 | 4236 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4237 | |
07b7ddd9 | 4238 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4239 | |
4240 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4241 | |
647416f9 | 4242 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4243 | |
647416f9 | 4244 | return 0; |
07b7ddd9 JB |
4245 | } |
4246 | ||
647416f9 KC |
4247 | static int |
4248 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4249 | { |
36cdd013 | 4250 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4251 | u32 snpcr; |
07b7ddd9 | 4252 | |
36cdd013 | 4253 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4254 | return -ENODEV; |
4255 | ||
647416f9 | 4256 | if (val > 3) |
07b7ddd9 JB |
4257 | return -EINVAL; |
4258 | ||
c8c8fb33 | 4259 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4260 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4261 | |
4262 | /* Update the cache sharing policy here as well */ | |
4263 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4264 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4265 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4266 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4267 | ||
c8c8fb33 | 4268 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4269 | return 0; |
07b7ddd9 JB |
4270 | } |
4271 | ||
647416f9 KC |
4272 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4273 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4274 | "%llu\n"); | |
07b7ddd9 | 4275 | |
36cdd013 | 4276 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4277 | struct sseu_dev_info *sseu) |
5d39525a | 4278 | { |
0a0b457f | 4279 | int ss_max = 2; |
5d39525a JM |
4280 | int ss; |
4281 | u32 sig1[ss_max], sig2[ss_max]; | |
4282 | ||
4283 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4284 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4285 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4286 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4287 | ||
4288 | for (ss = 0; ss < ss_max; ss++) { | |
4289 | unsigned int eu_cnt; | |
4290 | ||
4291 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4292 | /* skip disabled subslice */ | |
4293 | continue; | |
4294 | ||
f08a0c92 | 4295 | sseu->slice_mask = BIT(0); |
57ec171e | 4296 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4297 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4298 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4299 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4300 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4301 | sseu->eu_total += eu_cnt; |
4302 | sseu->eu_per_subslice = max_t(unsigned int, | |
4303 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4304 | } |
5d39525a JM |
4305 | } |
4306 | ||
f8c3dcf9 RV |
4307 | static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, |
4308 | struct sseu_dev_info *sseu) | |
4309 | { | |
4310 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
4311 | int s_max = 6, ss_max = 4; | |
4312 | int s, ss; | |
4313 | u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2]; | |
4314 | ||
4315 | for (s = 0; s < s_max; s++) { | |
4316 | /* | |
4317 | * FIXME: Valid SS Mask respects the spec and read | |
4318 | * only valid bits for those registers, excluding reserverd | |
4319 | * although this seems wrong because it would leave many | |
4320 | * subslices without ACK. | |
4321 | */ | |
4322 | s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) & | |
4323 | GEN10_PGCTL_VALID_SS_MASK(s); | |
4324 | eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s)); | |
4325 | eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s)); | |
4326 | } | |
4327 | ||
4328 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | | |
4329 | GEN9_PGCTL_SSA_EU19_ACK | | |
4330 | GEN9_PGCTL_SSA_EU210_ACK | | |
4331 | GEN9_PGCTL_SSA_EU311_ACK; | |
4332 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4333 | GEN9_PGCTL_SSB_EU19_ACK | | |
4334 | GEN9_PGCTL_SSB_EU210_ACK | | |
4335 | GEN9_PGCTL_SSB_EU311_ACK; | |
4336 | ||
4337 | for (s = 0; s < s_max; s++) { | |
4338 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4339 | /* skip disabled slice */ | |
4340 | continue; | |
4341 | ||
4342 | sseu->slice_mask |= BIT(s); | |
4343 | sseu->subslice_mask = info->sseu.subslice_mask; | |
4344 | ||
4345 | for (ss = 0; ss < ss_max; ss++) { | |
4346 | unsigned int eu_cnt; | |
4347 | ||
4348 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
4349 | /* skip disabled subslice */ | |
4350 | continue; | |
4351 | ||
4352 | eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] & | |
4353 | eu_mask[ss % 2]); | |
4354 | sseu->eu_total += eu_cnt; | |
4355 | sseu->eu_per_subslice = max_t(unsigned int, | |
4356 | sseu->eu_per_subslice, | |
4357 | eu_cnt); | |
4358 | } | |
4359 | } | |
4360 | } | |
4361 | ||
36cdd013 | 4362 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4363 | struct sseu_dev_info *sseu) |
5d39525a | 4364 | { |
1c046bc1 | 4365 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4366 | int s, ss; |
4367 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4368 | ||
1c046bc1 | 4369 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4370 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4371 | s_max = 1; |
4372 | ss_max = 3; | |
4373 | } | |
4374 | ||
4375 | for (s = 0; s < s_max; s++) { | |
4376 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4377 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4378 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4379 | } | |
4380 | ||
5d39525a JM |
4381 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4382 | GEN9_PGCTL_SSA_EU19_ACK | | |
4383 | GEN9_PGCTL_SSA_EU210_ACK | | |
4384 | GEN9_PGCTL_SSA_EU311_ACK; | |
4385 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4386 | GEN9_PGCTL_SSB_EU19_ACK | | |
4387 | GEN9_PGCTL_SSB_EU210_ACK | | |
4388 | GEN9_PGCTL_SSB_EU311_ACK; | |
4389 | ||
4390 | for (s = 0; s < s_max; s++) { | |
4391 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4392 | /* skip disabled slice */ | |
4393 | continue; | |
4394 | ||
f08a0c92 | 4395 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4396 | |
f8c3dcf9 | 4397 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4398 | sseu->subslice_mask = |
4399 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4400 | |
5d39525a JM |
4401 | for (ss = 0; ss < ss_max; ss++) { |
4402 | unsigned int eu_cnt; | |
4403 | ||
cc3f90f0 | 4404 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4405 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4406 | /* skip disabled subslice */ | |
4407 | continue; | |
1c046bc1 | 4408 | |
57ec171e ID |
4409 | sseu->subslice_mask |= BIT(ss); |
4410 | } | |
1c046bc1 | 4411 | |
5d39525a JM |
4412 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4413 | eu_mask[ss%2]); | |
915490d5 ID |
4414 | sseu->eu_total += eu_cnt; |
4415 | sseu->eu_per_subslice = max_t(unsigned int, | |
4416 | sseu->eu_per_subslice, | |
4417 | eu_cnt); | |
5d39525a JM |
4418 | } |
4419 | } | |
4420 | } | |
4421 | ||
36cdd013 | 4422 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4423 | struct sseu_dev_info *sseu) |
91bedd34 | 4424 | { |
91bedd34 | 4425 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4426 | int s; |
91bedd34 | 4427 | |
f08a0c92 | 4428 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4429 | |
f08a0c92 | 4430 | if (sseu->slice_mask) { |
57ec171e | 4431 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4432 | sseu->eu_per_subslice = |
4433 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4434 | sseu->eu_total = sseu->eu_per_subslice * |
4435 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4436 | |
4437 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4438 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4439 | u8 subslice_7eu = |
4440 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4441 | |
915490d5 | 4442 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4443 | } |
4444 | } | |
4445 | } | |
4446 | ||
615d8908 ID |
4447 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4448 | const struct sseu_dev_info *sseu) | |
4449 | { | |
4450 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4451 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4452 | ||
c67ba538 ID |
4453 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4454 | sseu->slice_mask); | |
615d8908 | 4455 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4456 | hweight8(sseu->slice_mask)); |
615d8908 | 4457 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4458 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4459 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4460 | sseu->subslice_mask); | |
615d8908 | 4461 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4462 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4463 | seq_printf(m, " %s EU Total: %u\n", type, |
4464 | sseu->eu_total); | |
4465 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4466 | sseu->eu_per_subslice); | |
4467 | ||
4468 | if (!is_available_info) | |
4469 | return; | |
4470 | ||
4471 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4472 | if (HAS_POOLED_EU(dev_priv)) | |
4473 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4474 | ||
4475 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4476 | yesno(sseu->has_slice_pg)); | |
4477 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4478 | yesno(sseu->has_subslice_pg)); | |
4479 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4480 | yesno(sseu->has_eu_pg)); | |
4481 | } | |
4482 | ||
3873218f JM |
4483 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4484 | { | |
36cdd013 | 4485 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4486 | struct sseu_dev_info sseu; |
3873218f | 4487 | |
36cdd013 | 4488 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4489 | return -ENODEV; |
4490 | ||
4491 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4492 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4493 | |
7f992aba | 4494 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4495 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4496 | |
4497 | intel_runtime_pm_get(dev_priv); | |
4498 | ||
36cdd013 | 4499 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4500 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4501 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4502 | broadwell_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 | 4503 | } else if (IS_GEN9(dev_priv)) { |
915490d5 | 4504 | gen9_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 RV |
4505 | } else if (INTEL_GEN(dev_priv) >= 10) { |
4506 | gen10_sseu_device_status(dev_priv, &sseu); | |
7f992aba | 4507 | } |
238010ed DW |
4508 | |
4509 | intel_runtime_pm_put(dev_priv); | |
4510 | ||
615d8908 | 4511 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4512 | |
3873218f JM |
4513 | return 0; |
4514 | } | |
4515 | ||
6d794d42 BW |
4516 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4517 | { | |
d7a133d8 | 4518 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4519 | |
d7a133d8 | 4520 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4521 | return 0; |
4522 | ||
d7a133d8 CW |
4523 | intel_runtime_pm_get(i915); |
4524 | intel_uncore_forcewake_user_get(i915); | |
6d794d42 BW |
4525 | |
4526 | return 0; | |
4527 | } | |
4528 | ||
c43b5634 | 4529 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4530 | { |
d7a133d8 | 4531 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4532 | |
d7a133d8 | 4533 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4534 | return 0; |
4535 | ||
d7a133d8 CW |
4536 | intel_uncore_forcewake_user_put(i915); |
4537 | intel_runtime_pm_put(i915); | |
6d794d42 BW |
4538 | |
4539 | return 0; | |
4540 | } | |
4541 | ||
4542 | static const struct file_operations i915_forcewake_fops = { | |
4543 | .owner = THIS_MODULE, | |
4544 | .open = i915_forcewake_open, | |
4545 | .release = i915_forcewake_release, | |
4546 | }; | |
4547 | ||
317eaa95 L |
4548 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4549 | { | |
4550 | struct drm_i915_private *dev_priv = m->private; | |
4551 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4552 | ||
4553 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4554 | seq_printf(m, "Detected: %s\n", | |
4555 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4556 | ||
4557 | return 0; | |
4558 | } | |
4559 | ||
4560 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4561 | const char __user *ubuf, size_t len, | |
4562 | loff_t *offp) | |
4563 | { | |
4564 | struct seq_file *m = file->private_data; | |
4565 | struct drm_i915_private *dev_priv = m->private; | |
4566 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4567 | unsigned int new_threshold; | |
4568 | int i; | |
4569 | char *newline; | |
4570 | char tmp[16]; | |
4571 | ||
4572 | if (len >= sizeof(tmp)) | |
4573 | return -EINVAL; | |
4574 | ||
4575 | if (copy_from_user(tmp, ubuf, len)) | |
4576 | return -EFAULT; | |
4577 | ||
4578 | tmp[len] = '\0'; | |
4579 | ||
4580 | /* Strip newline, if any */ | |
4581 | newline = strchr(tmp, '\n'); | |
4582 | if (newline) | |
4583 | *newline = '\0'; | |
4584 | ||
4585 | if (strcmp(tmp, "reset") == 0) | |
4586 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4587 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4588 | return -EINVAL; | |
4589 | ||
4590 | if (new_threshold > 0) | |
4591 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4592 | new_threshold); | |
4593 | else | |
4594 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4595 | ||
4596 | spin_lock_irq(&dev_priv->irq_lock); | |
4597 | hotplug->hpd_storm_threshold = new_threshold; | |
4598 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4599 | for_each_hpd_pin(i) | |
4600 | hotplug->stats[i].count = 0; | |
4601 | spin_unlock_irq(&dev_priv->irq_lock); | |
4602 | ||
4603 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4604 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4605 | ||
4606 | return len; | |
4607 | } | |
4608 | ||
4609 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4610 | { | |
4611 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4612 | } | |
4613 | ||
4614 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4615 | .owner = THIS_MODULE, | |
4616 | .open = i915_hpd_storm_ctl_open, | |
4617 | .read = seq_read, | |
4618 | .llseek = seq_lseek, | |
4619 | .release = single_release, | |
4620 | .write = i915_hpd_storm_ctl_write | |
4621 | }; | |
4622 | ||
06c5bf8c | 4623 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4624 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4625 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4626 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6d2b8885 | 4627 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
a6172a80 | 4628 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4629 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4630 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4631 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4632 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4633 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
ac58d2ab | 4634 | {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, |
a8b9370f | 4635 | {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, |
0509ead1 | 4636 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4637 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4638 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
061d06a2 | 4639 | {"i915_reset_info", i915_reset_info, 0}, |
f97108d1 | 4640 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4641 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4642 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4643 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4644 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4645 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4646 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4647 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4648 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4649 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4650 | {"i915_context_status", i915_context_status, 0}, |
f65367b5 | 4651 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4652 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4653 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4654 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4655 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4656 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4657 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4658 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4659 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4660 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4661 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4662 | {"i915_engine_info", i915_engine_info, 0}, |
c5418a8b | 4663 | {"i915_shrinker_info", i915_shrinker_info, 0}, |
728e29d7 | 4664 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4665 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4666 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4667 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4668 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4669 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4670 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4671 | }; |
27c202ad | 4672 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4673 | |
06c5bf8c | 4674 | static const struct i915_debugfs_files { |
34b9674c DV |
4675 | const char *name; |
4676 | const struct file_operations *fops; | |
4677 | } i915_debugfs_files[] = { | |
4678 | {"i915_wedged", &i915_wedged_fops}, | |
4679 | {"i915_max_freq", &i915_max_freq_fops}, | |
4680 | {"i915_min_freq", &i915_min_freq_fops}, | |
4681 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4682 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4683 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4684 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4685 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4686 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4687 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4688 | #endif |
34b9674c | 4689 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4690 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4691 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4692 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4693 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
4127dc43 | 4694 | {"i915_fbc_false_color", &i915_fbc_false_color_fops}, |
eb3394fa TP |
4695 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4696 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4697 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 | 4698 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
d2d4f39b KM |
4699 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, |
4700 | {"i915_ipc_status", &i915_ipc_status_fops} | |
34b9674c DV |
4701 | }; |
4702 | ||
1dac891c | 4703 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4704 | { |
91c8a326 | 4705 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4706 | struct dentry *ent; |
34b9674c | 4707 | int ret, i; |
f3cd474b | 4708 | |
b05eeb0f NT |
4709 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4710 | minor->debugfs_root, to_i915(minor->dev), | |
4711 | &i915_forcewake_fops); | |
4712 | if (!ent) | |
4713 | return -ENOMEM; | |
6a9c308d | 4714 | |
731035fe TV |
4715 | ret = intel_pipe_crc_create(minor); |
4716 | if (ret) | |
4717 | return ret; | |
07144428 | 4718 | |
34b9674c | 4719 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4720 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4721 | S_IRUGO | S_IWUSR, | |
4722 | minor->debugfs_root, | |
4723 | to_i915(minor->dev), | |
34b9674c | 4724 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4725 | if (!ent) |
4726 | return -ENOMEM; | |
34b9674c | 4727 | } |
40633219 | 4728 | |
27c202ad BG |
4729 | return drm_debugfs_create_files(i915_debugfs_list, |
4730 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4731 | minor->debugfs_root, minor); |
4732 | } | |
4733 | ||
aa7471d2 JN |
4734 | struct dpcd_block { |
4735 | /* DPCD dump start address. */ | |
4736 | unsigned int offset; | |
4737 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4738 | unsigned int end; | |
4739 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4740 | size_t size; | |
4741 | /* Only valid for eDP. */ | |
4742 | bool edp; | |
4743 | }; | |
4744 | ||
4745 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4746 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4747 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4748 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4749 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4750 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4751 | { .offset = DP_SET_POWER }, | |
4752 | { .offset = DP_EDP_DPCD_REV }, | |
4753 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4754 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4755 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4756 | }; | |
4757 | ||
4758 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4759 | { | |
4760 | struct drm_connector *connector = m->private; | |
4761 | struct intel_dp *intel_dp = | |
4762 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4763 | uint8_t buf[16]; | |
4764 | ssize_t err; | |
4765 | int i; | |
4766 | ||
5c1a8875 MK |
4767 | if (connector->status != connector_status_connected) |
4768 | return -ENODEV; | |
4769 | ||
aa7471d2 JN |
4770 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4771 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4772 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4773 | ||
4774 | if (b->edp && | |
4775 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4776 | continue; | |
4777 | ||
4778 | /* low tech for now */ | |
4779 | if (WARN_ON(size > sizeof(buf))) | |
4780 | continue; | |
4781 | ||
4782 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4783 | if (err <= 0) { | |
4784 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4785 | size, b->offset, err); | |
4786 | continue; | |
4787 | } | |
4788 | ||
4789 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4790 | } |
aa7471d2 JN |
4791 | |
4792 | return 0; | |
4793 | } | |
4794 | ||
4795 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4796 | { | |
4797 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4798 | } | |
4799 | ||
4800 | static const struct file_operations i915_dpcd_fops = { | |
4801 | .owner = THIS_MODULE, | |
4802 | .open = i915_dpcd_open, | |
4803 | .read = seq_read, | |
4804 | .llseek = seq_lseek, | |
4805 | .release = single_release, | |
4806 | }; | |
4807 | ||
ecbd6781 DW |
4808 | static int i915_panel_show(struct seq_file *m, void *data) |
4809 | { | |
4810 | struct drm_connector *connector = m->private; | |
4811 | struct intel_dp *intel_dp = | |
4812 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4813 | ||
4814 | if (connector->status != connector_status_connected) | |
4815 | return -ENODEV; | |
4816 | ||
4817 | seq_printf(m, "Panel power up delay: %d\n", | |
4818 | intel_dp->panel_power_up_delay); | |
4819 | seq_printf(m, "Panel power down delay: %d\n", | |
4820 | intel_dp->panel_power_down_delay); | |
4821 | seq_printf(m, "Backlight on delay: %d\n", | |
4822 | intel_dp->backlight_on_delay); | |
4823 | seq_printf(m, "Backlight off delay: %d\n", | |
4824 | intel_dp->backlight_off_delay); | |
4825 | ||
4826 | return 0; | |
4827 | } | |
4828 | ||
4829 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4830 | { | |
4831 | return single_open(file, i915_panel_show, inode->i_private); | |
4832 | } | |
4833 | ||
4834 | static const struct file_operations i915_panel_fops = { | |
4835 | .owner = THIS_MODULE, | |
4836 | .open = i915_panel_open, | |
4837 | .read = seq_read, | |
4838 | .llseek = seq_lseek, | |
4839 | .release = single_release, | |
4840 | }; | |
4841 | ||
aa7471d2 JN |
4842 | /** |
4843 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4844 | * @connector: pointer to a registered drm_connector | |
4845 | * | |
4846 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4847 | * drm_debugfs_connector_remove(). | |
4848 | * | |
4849 | * Returns 0 on success, negative error codes on error. | |
4850 | */ | |
4851 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4852 | { | |
4853 | struct dentry *root = connector->debugfs_entry; | |
4854 | ||
4855 | /* The connector must have been registered beforehands. */ | |
4856 | if (!root) | |
4857 | return -ENODEV; | |
4858 | ||
4859 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4860 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4861 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4862 | connector, &i915_dpcd_fops); | |
4863 | ||
4864 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4865 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4866 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4867 | |
4868 | return 0; | |
4869 | } |