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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
2017263e BG |
43 | #if defined(CONFIG_DEBUG_FS) |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
56 | static int i915_capabilities(struct seq_file *m, void *data) | |
57 | { | |
58 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
59 | struct drm_device *dev = node->minor->dev; | |
60 | const struct intel_device_info *info = INTEL_INFO(dev); | |
61 | ||
62 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 63 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
65 | #define SEP_SEMICOLON ; | |
66 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
67 | #undef PRINT_FLAG | |
68 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
69 | |
70 | return 0; | |
71 | } | |
2017263e | 72 | |
05394f39 | 73 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 74 | { |
05394f39 | 75 | if (obj->user_pin_count > 0) |
a6172a80 | 76 | return "P"; |
05394f39 | 77 | else if (obj->pin_count > 0) |
a6172a80 CW |
78 | return "p"; |
79 | else | |
80 | return " "; | |
81 | } | |
82 | ||
05394f39 | 83 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 84 | { |
0206e353 AJ |
85 | switch (obj->tiling_mode) { |
86 | default: | |
87 | case I915_TILING_NONE: return " "; | |
88 | case I915_TILING_X: return "X"; | |
89 | case I915_TILING_Y: return "Y"; | |
90 | } | |
a6172a80 CW |
91 | } |
92 | ||
1d693bcc BW |
93 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
94 | { | |
95 | return obj->has_global_gtt_mapping ? "g" : " "; | |
96 | } | |
97 | ||
37811fcc CW |
98 | static void |
99 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
100 | { | |
1d693bcc | 101 | struct i915_vma *vma; |
fb1ae911 | 102 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
103 | &obj->base, |
104 | get_pin_flag(obj), | |
105 | get_tiling_flag(obj), | |
1d693bcc | 106 | get_global_flag(obj), |
a05a5862 | 107 | obj->base.size / 1024, |
37811fcc CW |
108 | obj->base.read_domains, |
109 | obj->base.write_domain, | |
0201f1ec CW |
110 | obj->last_read_seqno, |
111 | obj->last_write_seqno, | |
caea7476 | 112 | obj->last_fenced_seqno, |
84734a04 | 113 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
114 | obj->dirty ? " dirty" : "", |
115 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
116 | if (obj->base.name) | |
117 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
118 | if (obj->pin_count) |
119 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
120 | if (obj->pin_display) |
121 | seq_printf(m, " (display)"); | |
37811fcc CW |
122 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
123 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
124 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
125 | if (!i915_is_ggtt(vma->vm)) | |
126 | seq_puts(m, " (pp"); | |
127 | else | |
128 | seq_puts(m, " (g"); | |
129 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
130 | vma->node.start, vma->node.size); | |
131 | } | |
c1ad11fc CW |
132 | if (obj->stolen) |
133 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
134 | if (obj->pin_mappable || obj->fault_mappable) { |
135 | char s[3], *t = s; | |
136 | if (obj->pin_mappable) | |
137 | *t++ = 'p'; | |
138 | if (obj->fault_mappable) | |
139 | *t++ = 'f'; | |
140 | *t = '\0'; | |
141 | seq_printf(m, " (%s mappable)", s); | |
142 | } | |
69dc4987 CW |
143 | if (obj->ring != NULL) |
144 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
145 | } |
146 | ||
3ccfd19d BW |
147 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
148 | { | |
149 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
150 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
151 | seq_putc(m, ' '); | |
152 | } | |
153 | ||
433e12f7 | 154 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
155 | { |
156 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
157 | uintptr_t list = (uintptr_t) node->info_ent->data; |
158 | struct list_head *head; | |
2017263e | 159 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
160 | struct drm_i915_private *dev_priv = dev->dev_private; |
161 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 162 | struct i915_vma *vma; |
8f2480fb CW |
163 | size_t total_obj_size, total_gtt_size; |
164 | int count, ret; | |
de227ef0 CW |
165 | |
166 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
167 | if (ret) | |
168 | return ret; | |
2017263e | 169 | |
ca191b13 | 170 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
171 | switch (list) { |
172 | case ACTIVE_LIST: | |
267f0c90 | 173 | seq_puts(m, "Active:\n"); |
5cef07e1 | 174 | head = &vm->active_list; |
433e12f7 BG |
175 | break; |
176 | case INACTIVE_LIST: | |
267f0c90 | 177 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 178 | head = &vm->inactive_list; |
433e12f7 | 179 | break; |
433e12f7 | 180 | default: |
de227ef0 CW |
181 | mutex_unlock(&dev->struct_mutex); |
182 | return -EINVAL; | |
2017263e | 183 | } |
2017263e | 184 | |
8f2480fb | 185 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
186 | list_for_each_entry(vma, head, mm_list) { |
187 | seq_printf(m, " "); | |
188 | describe_obj(m, vma->obj); | |
189 | seq_printf(m, "\n"); | |
190 | total_obj_size += vma->obj->base.size; | |
191 | total_gtt_size += vma->node.size; | |
8f2480fb | 192 | count++; |
2017263e | 193 | } |
de227ef0 | 194 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 195 | |
8f2480fb CW |
196 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
197 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
198 | return 0; |
199 | } | |
200 | ||
6d2b8885 CW |
201 | static int obj_rank_by_stolen(void *priv, |
202 | struct list_head *A, struct list_head *B) | |
203 | { | |
204 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 205 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 206 | struct drm_i915_gem_object *b = |
b25cb2f8 | 207 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
208 | |
209 | return a->stolen->start - b->stolen->start; | |
210 | } | |
211 | ||
212 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
213 | { | |
214 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
215 | struct drm_device *dev = node->minor->dev; | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | struct drm_i915_gem_object *obj; | |
218 | size_t total_obj_size, total_gtt_size; | |
219 | LIST_HEAD(stolen); | |
220 | int count, ret; | |
221 | ||
222 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | total_obj_size = total_gtt_size = count = 0; | |
227 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
228 | if (obj->stolen == NULL) | |
229 | continue; | |
230 | ||
b25cb2f8 | 231 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
232 | |
233 | total_obj_size += obj->base.size; | |
234 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
235 | count++; | |
236 | } | |
237 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
238 | if (obj->stolen == NULL) | |
239 | continue; | |
240 | ||
b25cb2f8 | 241 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
242 | |
243 | total_obj_size += obj->base.size; | |
244 | count++; | |
245 | } | |
246 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
247 | seq_puts(m, "Stolen:\n"); | |
248 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 249 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
250 | seq_puts(m, " "); |
251 | describe_obj(m, obj); | |
252 | seq_putc(m, '\n'); | |
b25cb2f8 | 253 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
254 | } |
255 | mutex_unlock(&dev->struct_mutex); | |
256 | ||
257 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
258 | count, total_obj_size, total_gtt_size); | |
259 | return 0; | |
260 | } | |
261 | ||
6299f992 CW |
262 | #define count_objects(list, member) do { \ |
263 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 264 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
265 | ++count; \ |
266 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 267 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
268 | ++mappable_count; \ |
269 | } \ | |
270 | } \ | |
0206e353 | 271 | } while (0) |
6299f992 | 272 | |
2db8e9d6 CW |
273 | struct file_stats { |
274 | int count; | |
275 | size_t total, active, inactive, unbound; | |
276 | }; | |
277 | ||
278 | static int per_file_stats(int id, void *ptr, void *data) | |
279 | { | |
280 | struct drm_i915_gem_object *obj = ptr; | |
281 | struct file_stats *stats = data; | |
282 | ||
283 | stats->count++; | |
284 | stats->total += obj->base.size; | |
285 | ||
f343c5f6 | 286 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
287 | if (!list_empty(&obj->ring_list)) |
288 | stats->active += obj->base.size; | |
289 | else | |
290 | stats->inactive += obj->base.size; | |
291 | } else { | |
292 | if (!list_empty(&obj->global_list)) | |
293 | stats->unbound += obj->base.size; | |
294 | } | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
ca191b13 BW |
299 | #define count_vmas(list, member) do { \ |
300 | list_for_each_entry(vma, list, member) { \ | |
301 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
302 | ++count; \ | |
303 | if (vma->obj->map_and_fenceable) { \ | |
304 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
305 | ++mappable_count; \ | |
306 | } \ | |
307 | } \ | |
308 | } while (0) | |
309 | ||
310 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
311 | { |
312 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
313 | struct drm_device *dev = node->minor->dev; | |
314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
315 | u32 count, mappable_count, purgeable_count; |
316 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 317 | struct drm_i915_gem_object *obj; |
5cef07e1 | 318 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 319 | struct drm_file *file; |
ca191b13 | 320 | struct i915_vma *vma; |
73aa808f CW |
321 | int ret; |
322 | ||
323 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
324 | if (ret) | |
325 | return ret; | |
326 | ||
6299f992 CW |
327 | seq_printf(m, "%u objects, %zu bytes\n", |
328 | dev_priv->mm.object_count, | |
329 | dev_priv->mm.object_memory); | |
330 | ||
331 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 332 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
333 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
334 | count, mappable_count, size, mappable_size); | |
335 | ||
336 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 337 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
338 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
339 | count, mappable_count, size, mappable_size); | |
340 | ||
6299f992 | 341 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 342 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
343 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
344 | count, mappable_count, size, mappable_size); | |
345 | ||
b7abb714 | 346 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 347 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 348 | size += obj->base.size, ++count; |
b7abb714 CW |
349 | if (obj->madv == I915_MADV_DONTNEED) |
350 | purgeable_size += obj->base.size, ++purgeable_count; | |
351 | } | |
6c085a72 CW |
352 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
353 | ||
6299f992 | 354 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 355 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 356 | if (obj->fault_mappable) { |
f343c5f6 | 357 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
358 | ++count; |
359 | } | |
360 | if (obj->pin_mappable) { | |
f343c5f6 | 361 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
362 | ++mappable_count; |
363 | } | |
b7abb714 CW |
364 | if (obj->madv == I915_MADV_DONTNEED) { |
365 | purgeable_size += obj->base.size; | |
366 | ++purgeable_count; | |
367 | } | |
6299f992 | 368 | } |
b7abb714 CW |
369 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
370 | purgeable_count, purgeable_size); | |
6299f992 CW |
371 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
372 | mappable_count, mappable_size); | |
373 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
374 | count, size); | |
375 | ||
93d18799 | 376 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
377 | dev_priv->gtt.base.total, |
378 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 379 | |
267f0c90 | 380 | seq_putc(m, '\n'); |
2db8e9d6 CW |
381 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
382 | struct file_stats stats; | |
383 | ||
384 | memset(&stats, 0, sizeof(stats)); | |
385 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
386 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
387 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
388 | stats.count, | |
389 | stats.total, | |
390 | stats.active, | |
391 | stats.inactive, | |
392 | stats.unbound); | |
393 | } | |
394 | ||
73aa808f CW |
395 | mutex_unlock(&dev->struct_mutex); |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
aee56cff | 400 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
401 | { |
402 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
403 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 404 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
405 | struct drm_i915_private *dev_priv = dev->dev_private; |
406 | struct drm_i915_gem_object *obj; | |
407 | size_t total_obj_size, total_gtt_size; | |
408 | int count, ret; | |
409 | ||
410 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
414 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 415 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
416 | if (list == PINNED_LIST && obj->pin_count == 0) |
417 | continue; | |
418 | ||
267f0c90 | 419 | seq_puts(m, " "); |
08c18323 | 420 | describe_obj(m, obj); |
267f0c90 | 421 | seq_putc(m, '\n'); |
08c18323 | 422 | total_obj_size += obj->base.size; |
f343c5f6 | 423 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
424 | count++; |
425 | } | |
426 | ||
427 | mutex_unlock(&dev->struct_mutex); | |
428 | ||
429 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
430 | count, total_obj_size, total_gtt_size); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
4e5359cd SF |
435 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
436 | { | |
437 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
438 | struct drm_device *dev = node->minor->dev; | |
439 | unsigned long flags; | |
440 | struct intel_crtc *crtc; | |
441 | ||
442 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
443 | const char pipe = pipe_name(crtc->pipe); |
444 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
445 | struct intel_unpin_work *work; |
446 | ||
447 | spin_lock_irqsave(&dev->event_lock, flags); | |
448 | work = crtc->unpin_work; | |
449 | if (work == NULL) { | |
9db4a9c7 | 450 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
451 | pipe, plane); |
452 | } else { | |
e7d841ca | 453 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 454 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
455 | pipe, plane); |
456 | } else { | |
9db4a9c7 | 457 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
458 | pipe, plane); |
459 | } | |
460 | if (work->enable_stall_check) | |
267f0c90 | 461 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 462 | else |
267f0c90 | 463 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 464 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
465 | |
466 | if (work->old_fb_obj) { | |
05394f39 CW |
467 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
468 | if (obj) | |
f343c5f6 BW |
469 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
470 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
471 | } |
472 | if (work->pending_flip_obj) { | |
05394f39 CW |
473 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
474 | if (obj) | |
f343c5f6 BW |
475 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
476 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
477 | } |
478 | } | |
479 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
2017263e BG |
485 | static int i915_gem_request_info(struct seq_file *m, void *data) |
486 | { | |
487 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
488 | struct drm_device *dev = node->minor->dev; | |
489 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 490 | struct intel_ring_buffer *ring; |
2017263e | 491 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 492 | int ret, count, i; |
de227ef0 CW |
493 | |
494 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
495 | if (ret) | |
496 | return ret; | |
2017263e | 497 | |
c2c347a9 | 498 | count = 0; |
a2c7f6fd CW |
499 | for_each_ring(ring, dev_priv, i) { |
500 | if (list_empty(&ring->request_list)) | |
501 | continue; | |
502 | ||
503 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 504 | list_for_each_entry(gem_request, |
a2c7f6fd | 505 | &ring->request_list, |
c2c347a9 CW |
506 | list) { |
507 | seq_printf(m, " %d @ %d\n", | |
508 | gem_request->seqno, | |
509 | (int) (jiffies - gem_request->emitted_jiffies)); | |
510 | } | |
511 | count++; | |
2017263e | 512 | } |
de227ef0 CW |
513 | mutex_unlock(&dev->struct_mutex); |
514 | ||
c2c347a9 | 515 | if (count == 0) |
267f0c90 | 516 | seq_puts(m, "No requests\n"); |
c2c347a9 | 517 | |
2017263e BG |
518 | return 0; |
519 | } | |
520 | ||
b2223497 CW |
521 | static void i915_ring_seqno_info(struct seq_file *m, |
522 | struct intel_ring_buffer *ring) | |
523 | { | |
524 | if (ring->get_seqno) { | |
43a7b924 | 525 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 526 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
527 | } |
528 | } | |
529 | ||
2017263e BG |
530 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
531 | { | |
532 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
533 | struct drm_device *dev = node->minor->dev; | |
534 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 535 | struct intel_ring_buffer *ring; |
1ec14ad3 | 536 | int ret, i; |
de227ef0 CW |
537 | |
538 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
539 | if (ret) | |
540 | return ret; | |
2017263e | 541 | |
a2c7f6fd CW |
542 | for_each_ring(ring, dev_priv, i) |
543 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
544 | |
545 | mutex_unlock(&dev->struct_mutex); | |
546 | ||
2017263e BG |
547 | return 0; |
548 | } | |
549 | ||
550 | ||
551 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
552 | { | |
553 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
554 | struct drm_device *dev = node->minor->dev; | |
555 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 556 | struct intel_ring_buffer *ring; |
9db4a9c7 | 557 | int ret, i, pipe; |
de227ef0 CW |
558 | |
559 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
560 | if (ret) | |
561 | return ret; | |
2017263e | 562 | |
7e231dbe JB |
563 | if (IS_VALLEYVIEW(dev)) { |
564 | seq_printf(m, "Display IER:\t%08x\n", | |
565 | I915_READ(VLV_IER)); | |
566 | seq_printf(m, "Display IIR:\t%08x\n", | |
567 | I915_READ(VLV_IIR)); | |
568 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
569 | I915_READ(VLV_IIR_RW)); | |
570 | seq_printf(m, "Display IMR:\t%08x\n", | |
571 | I915_READ(VLV_IMR)); | |
572 | for_each_pipe(pipe) | |
573 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
574 | pipe_name(pipe), | |
575 | I915_READ(PIPESTAT(pipe))); | |
576 | ||
577 | seq_printf(m, "Master IER:\t%08x\n", | |
578 | I915_READ(VLV_MASTER_IER)); | |
579 | ||
580 | seq_printf(m, "Render IER:\t%08x\n", | |
581 | I915_READ(GTIER)); | |
582 | seq_printf(m, "Render IIR:\t%08x\n", | |
583 | I915_READ(GTIIR)); | |
584 | seq_printf(m, "Render IMR:\t%08x\n", | |
585 | I915_READ(GTIMR)); | |
586 | ||
587 | seq_printf(m, "PM IER:\t\t%08x\n", | |
588 | I915_READ(GEN6_PMIER)); | |
589 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
590 | I915_READ(GEN6_PMIIR)); | |
591 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
592 | I915_READ(GEN6_PMIMR)); | |
593 | ||
594 | seq_printf(m, "Port hotplug:\t%08x\n", | |
595 | I915_READ(PORT_HOTPLUG_EN)); | |
596 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
597 | I915_READ(VLV_DPFLIPSTAT)); | |
598 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
599 | I915_READ(DPINVGTT)); | |
600 | ||
601 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
602 | seq_printf(m, "Interrupt enable: %08x\n", |
603 | I915_READ(IER)); | |
604 | seq_printf(m, "Interrupt identity: %08x\n", | |
605 | I915_READ(IIR)); | |
606 | seq_printf(m, "Interrupt mask: %08x\n", | |
607 | I915_READ(IMR)); | |
9db4a9c7 JB |
608 | for_each_pipe(pipe) |
609 | seq_printf(m, "Pipe %c stat: %08x\n", | |
610 | pipe_name(pipe), | |
611 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
612 | } else { |
613 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
614 | I915_READ(DEIER)); | |
615 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
616 | I915_READ(DEIIR)); | |
617 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
618 | I915_READ(DEIMR)); | |
619 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
620 | I915_READ(SDEIER)); | |
621 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
622 | I915_READ(SDEIIR)); | |
623 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
624 | I915_READ(SDEIMR)); | |
625 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
626 | I915_READ(GTIER)); | |
627 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
628 | I915_READ(GTIIR)); | |
629 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
630 | I915_READ(GTIMR)); | |
631 | } | |
2017263e BG |
632 | seq_printf(m, "Interrupts received: %d\n", |
633 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 634 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 635 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
636 | seq_printf(m, |
637 | "Graphics Interrupt mask (%s): %08x\n", | |
638 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 639 | } |
a2c7f6fd | 640 | i915_ring_seqno_info(m, ring); |
9862e600 | 641 | } |
de227ef0 CW |
642 | mutex_unlock(&dev->struct_mutex); |
643 | ||
2017263e BG |
644 | return 0; |
645 | } | |
646 | ||
a6172a80 CW |
647 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
648 | { | |
649 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
650 | struct drm_device *dev = node->minor->dev; | |
651 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
652 | int i, ret; |
653 | ||
654 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
655 | if (ret) | |
656 | return ret; | |
a6172a80 CW |
657 | |
658 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
659 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
660 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 661 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 662 | |
6c085a72 CW |
663 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
664 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 665 | if (obj == NULL) |
267f0c90 | 666 | seq_puts(m, "unused"); |
c2c347a9 | 667 | else |
05394f39 | 668 | describe_obj(m, obj); |
267f0c90 | 669 | seq_putc(m, '\n'); |
a6172a80 CW |
670 | } |
671 | ||
05394f39 | 672 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
673 | return 0; |
674 | } | |
675 | ||
2017263e BG |
676 | static int i915_hws_info(struct seq_file *m, void *data) |
677 | { | |
678 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
679 | struct drm_device *dev = node->minor->dev; | |
680 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 681 | struct intel_ring_buffer *ring; |
1a240d4d | 682 | const u32 *hws; |
4066c0ae CW |
683 | int i; |
684 | ||
1ec14ad3 | 685 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 686 | hws = ring->status_page.page_addr; |
2017263e BG |
687 | if (hws == NULL) |
688 | return 0; | |
689 | ||
690 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
691 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
692 | i * 4, | |
693 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
694 | } | |
695 | return 0; | |
696 | } | |
697 | ||
d5442303 DV |
698 | static ssize_t |
699 | i915_error_state_write(struct file *filp, | |
700 | const char __user *ubuf, | |
701 | size_t cnt, | |
702 | loff_t *ppos) | |
703 | { | |
edc3d884 | 704 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 705 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 706 | int ret; |
d5442303 DV |
707 | |
708 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
709 | ||
22bcfc6a DV |
710 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
711 | if (ret) | |
712 | return ret; | |
713 | ||
d5442303 DV |
714 | i915_destroy_error_state(dev); |
715 | mutex_unlock(&dev->struct_mutex); | |
716 | ||
717 | return cnt; | |
718 | } | |
719 | ||
720 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
721 | { | |
722 | struct drm_device *dev = inode->i_private; | |
d5442303 | 723 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
724 | |
725 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
726 | if (!error_priv) | |
727 | return -ENOMEM; | |
728 | ||
729 | error_priv->dev = dev; | |
730 | ||
95d5bfb3 | 731 | i915_error_state_get(dev, error_priv); |
d5442303 | 732 | |
edc3d884 MK |
733 | file->private_data = error_priv; |
734 | ||
735 | return 0; | |
d5442303 DV |
736 | } |
737 | ||
738 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
739 | { | |
edc3d884 | 740 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 741 | |
95d5bfb3 | 742 | i915_error_state_put(error_priv); |
d5442303 DV |
743 | kfree(error_priv); |
744 | ||
edc3d884 MK |
745 | return 0; |
746 | } | |
747 | ||
4dc955f7 MK |
748 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
749 | size_t count, loff_t *pos) | |
750 | { | |
751 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
752 | struct drm_i915_error_state_buf error_str; | |
753 | loff_t tmp_pos = 0; | |
754 | ssize_t ret_count = 0; | |
755 | int ret; | |
756 | ||
757 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
758 | if (ret) | |
759 | return ret; | |
edc3d884 | 760 | |
fc16b48b | 761 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
762 | if (ret) |
763 | goto out; | |
764 | ||
edc3d884 MK |
765 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
766 | error_str.buf, | |
767 | error_str.bytes); | |
768 | ||
769 | if (ret_count < 0) | |
770 | ret = ret_count; | |
771 | else | |
772 | *pos = error_str.start + ret_count; | |
773 | out: | |
4dc955f7 | 774 | i915_error_state_buf_release(&error_str); |
edc3d884 | 775 | return ret ?: ret_count; |
d5442303 DV |
776 | } |
777 | ||
778 | static const struct file_operations i915_error_state_fops = { | |
779 | .owner = THIS_MODULE, | |
780 | .open = i915_error_state_open, | |
edc3d884 | 781 | .read = i915_error_state_read, |
d5442303 DV |
782 | .write = i915_error_state_write, |
783 | .llseek = default_llseek, | |
784 | .release = i915_error_state_release, | |
785 | }; | |
786 | ||
647416f9 KC |
787 | static int |
788 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 789 | { |
647416f9 | 790 | struct drm_device *dev = data; |
40633219 | 791 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
792 | int ret; |
793 | ||
794 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
795 | if (ret) | |
796 | return ret; | |
797 | ||
647416f9 | 798 | *val = dev_priv->next_seqno; |
40633219 MK |
799 | mutex_unlock(&dev->struct_mutex); |
800 | ||
647416f9 | 801 | return 0; |
40633219 MK |
802 | } |
803 | ||
647416f9 KC |
804 | static int |
805 | i915_next_seqno_set(void *data, u64 val) | |
806 | { | |
807 | struct drm_device *dev = data; | |
40633219 MK |
808 | int ret; |
809 | ||
40633219 MK |
810 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
811 | if (ret) | |
812 | return ret; | |
813 | ||
e94fbaa8 | 814 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
815 | mutex_unlock(&dev->struct_mutex); |
816 | ||
647416f9 | 817 | return ret; |
40633219 MK |
818 | } |
819 | ||
647416f9 KC |
820 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
821 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 822 | "0x%llx\n"); |
40633219 | 823 | |
f97108d1 JB |
824 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
825 | { | |
826 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
827 | struct drm_device *dev = node->minor->dev; | |
828 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
829 | u16 crstanddelay; |
830 | int ret; | |
831 | ||
832 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
833 | if (ret) | |
834 | return ret; | |
835 | ||
836 | crstanddelay = I915_READ16(CRSTANDVID); | |
837 | ||
838 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
839 | |
840 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
846 | { | |
847 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
848 | struct drm_device *dev = node->minor->dev; | |
849 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 850 | int ret; |
3b8d8d91 | 851 | |
5c9669ce TR |
852 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
853 | ||
3b8d8d91 JB |
854 | if (IS_GEN5(dev)) { |
855 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
856 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
857 | ||
858 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
859 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
860 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
861 | MEMSTAT_VID_SHIFT); | |
862 | seq_printf(m, "Current P-state: %d\n", | |
863 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 864 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
865 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
866 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
867 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 868 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
869 | u32 rpupei, rpcurup, rpprevup; |
870 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
871 | int max_freq; |
872 | ||
873 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
874 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
875 | if (ret) | |
876 | return ret; | |
877 | ||
fcca7926 | 878 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 879 | |
8e8c06cd CW |
880 | reqf = I915_READ(GEN6_RPNSWREQ); |
881 | reqf &= ~GEN6_TURBO_DISABLE; | |
882 | if (IS_HASWELL(dev)) | |
883 | reqf >>= 24; | |
884 | else | |
885 | reqf >>= 25; | |
886 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
887 | ||
ccab5c82 JB |
888 | rpstat = I915_READ(GEN6_RPSTAT1); |
889 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
890 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
891 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
892 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
893 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
894 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
895 | if (IS_HASWELL(dev)) |
896 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
897 | else | |
898 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
899 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 900 | |
d1ebd816 BW |
901 | gen6_gt_force_wake_put(dev_priv); |
902 | mutex_unlock(&dev->struct_mutex); | |
903 | ||
3b8d8d91 | 904 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 905 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
906 | seq_printf(m, "Render p-state ratio: %d\n", |
907 | (gt_perf_status & 0xff00) >> 8); | |
908 | seq_printf(m, "Render p-state VID: %d\n", | |
909 | gt_perf_status & 0xff); | |
910 | seq_printf(m, "Render p-state limit: %d\n", | |
911 | rp_state_limits & 0xff); | |
8e8c06cd | 912 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 913 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
914 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
915 | GEN6_CURICONT_MASK); | |
916 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
917 | GEN6_CURBSYTAVG_MASK); | |
918 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
919 | GEN6_CURBSYTAVG_MASK); | |
920 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
921 | GEN6_CURIAVG_MASK); | |
922 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
923 | GEN6_CURBSYTAVG_MASK); | |
924 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
925 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
926 | |
927 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
928 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 929 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
930 | |
931 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
932 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 933 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
934 | |
935 | max_freq = rp_state_cap & 0xff; | |
936 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 937 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
938 | |
939 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
940 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
941 | } else if (IS_VALLEYVIEW(dev)) { |
942 | u32 freq_sts, val; | |
943 | ||
259bd5d4 | 944 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 945 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
946 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
947 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
948 | ||
64936258 | 949 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
950 | seq_printf(m, "max GPU freq: %d MHz\n", |
951 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
952 | ||
64936258 | 953 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
954 | seq_printf(m, "min GPU freq: %d MHz\n", |
955 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
956 | ||
957 | seq_printf(m, "current GPU freq: %d MHz\n", | |
958 | vlv_gpu_freq(dev_priv->mem_freq, | |
959 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 960 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 961 | } else { |
267f0c90 | 962 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 963 | } |
f97108d1 JB |
964 | |
965 | return 0; | |
966 | } | |
967 | ||
968 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
969 | { | |
970 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
971 | struct drm_device *dev = node->minor->dev; | |
972 | drm_i915_private_t *dev_priv = dev->dev_private; | |
973 | u32 delayfreq; | |
616fdb5a BW |
974 | int ret, i; |
975 | ||
976 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
977 | if (ret) | |
978 | return ret; | |
f97108d1 JB |
979 | |
980 | for (i = 0; i < 16; i++) { | |
981 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
982 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
983 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
984 | } |
985 | ||
616fdb5a BW |
986 | mutex_unlock(&dev->struct_mutex); |
987 | ||
f97108d1 JB |
988 | return 0; |
989 | } | |
990 | ||
991 | static inline int MAP_TO_MV(int map) | |
992 | { | |
993 | return 1250 - (map * 25); | |
994 | } | |
995 | ||
996 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
997 | { | |
998 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
999 | struct drm_device *dev = node->minor->dev; | |
1000 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1001 | u32 inttoext; | |
616fdb5a BW |
1002 | int ret, i; |
1003 | ||
1004 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1005 | if (ret) | |
1006 | return ret; | |
f97108d1 JB |
1007 | |
1008 | for (i = 1; i <= 32; i++) { | |
1009 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1010 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1011 | } | |
1012 | ||
616fdb5a BW |
1013 | mutex_unlock(&dev->struct_mutex); |
1014 | ||
f97108d1 JB |
1015 | return 0; |
1016 | } | |
1017 | ||
4d85529d | 1018 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1019 | { |
1020 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1021 | struct drm_device *dev = node->minor->dev; | |
1022 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1023 | u32 rgvmodectl, rstdbyctl; |
1024 | u16 crstandvid; | |
1025 | int ret; | |
1026 | ||
1027 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1028 | if (ret) | |
1029 | return ret; | |
1030 | ||
1031 | rgvmodectl = I915_READ(MEMMODECTL); | |
1032 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1033 | crstandvid = I915_READ16(CRSTANDVID); | |
1034 | ||
1035 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1036 | |
1037 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1038 | "yes" : "no"); | |
1039 | seq_printf(m, "Boost freq: %d\n", | |
1040 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1041 | MEMMODE_BOOST_FREQ_SHIFT); | |
1042 | seq_printf(m, "HW control enabled: %s\n", | |
1043 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1044 | seq_printf(m, "SW control enabled: %s\n", | |
1045 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1046 | seq_printf(m, "Gated voltage change: %s\n", | |
1047 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1048 | seq_printf(m, "Starting frequency: P%d\n", | |
1049 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1050 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1051 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1052 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1053 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1054 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1055 | seq_printf(m, "Render standby enabled: %s\n", | |
1056 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1057 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1058 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1059 | case RSX_STATUS_ON: | |
267f0c90 | 1060 | seq_puts(m, "on\n"); |
88271da3 JB |
1061 | break; |
1062 | case RSX_STATUS_RC1: | |
267f0c90 | 1063 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1064 | break; |
1065 | case RSX_STATUS_RC1E: | |
267f0c90 | 1066 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1067 | break; |
1068 | case RSX_STATUS_RS1: | |
267f0c90 | 1069 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1070 | break; |
1071 | case RSX_STATUS_RS2: | |
267f0c90 | 1072 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1073 | break; |
1074 | case RSX_STATUS_RS3: | |
267f0c90 | 1075 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1076 | break; |
1077 | default: | |
267f0c90 | 1078 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1079 | break; |
1080 | } | |
f97108d1 JB |
1081 | |
1082 | return 0; | |
1083 | } | |
1084 | ||
4d85529d BW |
1085 | static int gen6_drpc_info(struct seq_file *m) |
1086 | { | |
1087 | ||
1088 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1089 | struct drm_device *dev = node->minor->dev; | |
1090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1091 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1092 | unsigned forcewake_count; |
aee56cff | 1093 | int count = 0, ret; |
4d85529d BW |
1094 | |
1095 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1096 | if (ret) | |
1097 | return ret; | |
1098 | ||
907b28c5 CW |
1099 | spin_lock_irq(&dev_priv->uncore.lock); |
1100 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1101 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1102 | |
1103 | if (forcewake_count) { | |
267f0c90 DL |
1104 | seq_puts(m, "RC information inaccurate because somebody " |
1105 | "holds a forcewake reference \n"); | |
4d85529d BW |
1106 | } else { |
1107 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1108 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1109 | udelay(10); | |
1110 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1111 | } | |
1112 | ||
1113 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1114 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1115 | |
1116 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1117 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1118 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1119 | mutex_lock(&dev_priv->rps.hw_lock); |
1120 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1121 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1122 | |
1123 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1124 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1125 | seq_printf(m, "HW control enabled: %s\n", | |
1126 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1127 | seq_printf(m, "SW control enabled: %s\n", | |
1128 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1129 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1130 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1131 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1132 | seq_printf(m, "RC6 Enabled: %s\n", | |
1133 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1134 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1135 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1136 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1137 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1138 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1139 | switch (gt_core_status & GEN6_RCn_MASK) { |
1140 | case GEN6_RC0: | |
1141 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1142 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1143 | else |
267f0c90 | 1144 | seq_puts(m, "on\n"); |
4d85529d BW |
1145 | break; |
1146 | case GEN6_RC3: | |
267f0c90 | 1147 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1148 | break; |
1149 | case GEN6_RC6: | |
267f0c90 | 1150 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1151 | break; |
1152 | case GEN6_RC7: | |
267f0c90 | 1153 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1154 | break; |
1155 | default: | |
267f0c90 | 1156 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1157 | break; |
1158 | } | |
1159 | ||
1160 | seq_printf(m, "Core Power Down: %s\n", | |
1161 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1162 | |
1163 | /* Not exactly sure what this is */ | |
1164 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1165 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1166 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1167 | I915_READ(GEN6_GT_GFX_RC6)); | |
1168 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1169 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1170 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1171 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1172 | ||
ecd8faea BW |
1173 | seq_printf(m, "RC6 voltage: %dmV\n", |
1174 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1175 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1176 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1177 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1178 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1179 | return 0; |
1180 | } | |
1181 | ||
1182 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1183 | { | |
1184 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1185 | struct drm_device *dev = node->minor->dev; | |
1186 | ||
1187 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1188 | return gen6_drpc_info(m); | |
1189 | else | |
1190 | return ironlake_drpc_info(m); | |
1191 | } | |
1192 | ||
b5e50c3f JB |
1193 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1194 | { | |
1195 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1196 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1197 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1198 | |
ee5382ae | 1199 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1200 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1201 | return 0; |
1202 | } | |
1203 | ||
ee5382ae | 1204 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1205 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1206 | } else { |
267f0c90 | 1207 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1208 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1209 | case FBC_OK: |
1210 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1211 | break; | |
1212 | case FBC_UNSUPPORTED: | |
1213 | seq_puts(m, "unsupported by this chipset"); | |
1214 | break; | |
bed4a673 | 1215 | case FBC_NO_OUTPUT: |
267f0c90 | 1216 | seq_puts(m, "no outputs"); |
bed4a673 | 1217 | break; |
b5e50c3f | 1218 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1219 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1220 | break; |
1221 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1222 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1223 | break; |
1224 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1225 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1226 | break; |
1227 | case FBC_BAD_PLANE: | |
267f0c90 | 1228 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1229 | break; |
1230 | case FBC_NOT_TILED: | |
267f0c90 | 1231 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1232 | break; |
9c928d16 | 1233 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1234 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1235 | break; |
c1a9f047 | 1236 | case FBC_MODULE_PARAM: |
267f0c90 | 1237 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1238 | break; |
8a5729a3 | 1239 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1240 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1241 | break; |
b5e50c3f | 1242 | default: |
267f0c90 | 1243 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1244 | } |
267f0c90 | 1245 | seq_putc(m, '\n'); |
b5e50c3f JB |
1246 | } |
1247 | return 0; | |
1248 | } | |
1249 | ||
92d44621 PZ |
1250 | static int i915_ips_status(struct seq_file *m, void *unused) |
1251 | { | |
1252 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1253 | struct drm_device *dev = node->minor->dev; | |
1254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1255 | ||
f5adf94e | 1256 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1257 | seq_puts(m, "not supported\n"); |
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1262 | seq_puts(m, "enabled\n"); | |
1263 | else | |
1264 | seq_puts(m, "disabled\n"); | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
4a9bef37 JB |
1269 | static int i915_sr_status(struct seq_file *m, void *unused) |
1270 | { | |
1271 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1272 | struct drm_device *dev = node->minor->dev; | |
1273 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1274 | bool sr_enabled = false; | |
1275 | ||
1398261a | 1276 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1277 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1278 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1279 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1280 | else if (IS_I915GM(dev)) | |
1281 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1282 | else if (IS_PINEVIEW(dev)) | |
1283 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1284 | ||
5ba2aaaa CW |
1285 | seq_printf(m, "self-refresh: %s\n", |
1286 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1287 | |
1288 | return 0; | |
1289 | } | |
1290 | ||
7648fa99 JB |
1291 | static int i915_emon_status(struct seq_file *m, void *unused) |
1292 | { | |
1293 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1294 | struct drm_device *dev = node->minor->dev; | |
1295 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1296 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1297 | int ret; |
1298 | ||
582be6b4 CW |
1299 | if (!IS_GEN5(dev)) |
1300 | return -ENODEV; | |
1301 | ||
de227ef0 CW |
1302 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1303 | if (ret) | |
1304 | return ret; | |
7648fa99 JB |
1305 | |
1306 | temp = i915_mch_val(dev_priv); | |
1307 | chipset = i915_chipset_val(dev_priv); | |
1308 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1309 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1310 | |
1311 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1312 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1313 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1314 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
23b2f8bb JB |
1319 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1320 | { | |
1321 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1322 | struct drm_device *dev = node->minor->dev; | |
1323 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1324 | int ret; | |
1325 | int gpu_freq, ia_freq; | |
1326 | ||
1c70c0ce | 1327 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1328 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1329 | return 0; |
1330 | } | |
1331 | ||
5c9669ce TR |
1332 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1333 | ||
4fc688ce | 1334 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1335 | if (ret) |
1336 | return ret; | |
1337 | ||
267f0c90 | 1338 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1339 | |
c6a828d3 DV |
1340 | for (gpu_freq = dev_priv->rps.min_delay; |
1341 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1342 | gpu_freq++) { |
42c0526c BW |
1343 | ia_freq = gpu_freq; |
1344 | sandybridge_pcode_read(dev_priv, | |
1345 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1346 | &ia_freq); | |
3ebecd07 CW |
1347 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1348 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1349 | ((ia_freq >> 0) & 0xff) * 100, | |
1350 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1351 | } |
1352 | ||
4fc688ce | 1353 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1354 | |
1355 | return 0; | |
1356 | } | |
1357 | ||
7648fa99 JB |
1358 | static int i915_gfxec(struct seq_file *m, void *unused) |
1359 | { | |
1360 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1361 | struct drm_device *dev = node->minor->dev; | |
1362 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1363 | int ret; |
1364 | ||
1365 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1366 | if (ret) | |
1367 | return ret; | |
7648fa99 JB |
1368 | |
1369 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1370 | ||
616fdb5a BW |
1371 | mutex_unlock(&dev->struct_mutex); |
1372 | ||
7648fa99 JB |
1373 | return 0; |
1374 | } | |
1375 | ||
44834a67 CW |
1376 | static int i915_opregion(struct seq_file *m, void *unused) |
1377 | { | |
1378 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1379 | struct drm_device *dev = node->minor->dev; | |
1380 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1381 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1382 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1383 | int ret; |
1384 | ||
0d38f009 DV |
1385 | if (data == NULL) |
1386 | return -ENOMEM; | |
1387 | ||
44834a67 CW |
1388 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1389 | if (ret) | |
0d38f009 | 1390 | goto out; |
44834a67 | 1391 | |
0d38f009 DV |
1392 | if (opregion->header) { |
1393 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1394 | seq_write(m, data, OPREGION_SIZE); | |
1395 | } | |
44834a67 CW |
1396 | |
1397 | mutex_unlock(&dev->struct_mutex); | |
1398 | ||
0d38f009 DV |
1399 | out: |
1400 | kfree(data); | |
44834a67 CW |
1401 | return 0; |
1402 | } | |
1403 | ||
37811fcc CW |
1404 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1405 | { | |
1406 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1407 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1408 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1409 | struct intel_framebuffer *fb; |
37811fcc | 1410 | |
4520f53a DV |
1411 | #ifdef CONFIG_DRM_I915_FBDEV |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1413 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1414 | if (ret) |
1415 | return ret; | |
1416 | ||
1417 | ifbdev = dev_priv->fbdev; | |
1418 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1419 | ||
623f9783 | 1420 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1421 | fb->base.width, |
1422 | fb->base.height, | |
1423 | fb->base.depth, | |
623f9783 DV |
1424 | fb->base.bits_per_pixel, |
1425 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1426 | describe_obj(m, fb->obj); |
267f0c90 | 1427 | seq_putc(m, '\n'); |
4b096ac1 | 1428 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1429 | #endif |
37811fcc | 1430 | |
4b096ac1 | 1431 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1432 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1433 | if (&fb->base == ifbdev->helper.fb) | |
1434 | continue; | |
1435 | ||
623f9783 | 1436 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1437 | fb->base.width, |
1438 | fb->base.height, | |
1439 | fb->base.depth, | |
623f9783 DV |
1440 | fb->base.bits_per_pixel, |
1441 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1442 | describe_obj(m, fb->obj); |
267f0c90 | 1443 | seq_putc(m, '\n'); |
37811fcc | 1444 | } |
4b096ac1 | 1445 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1446 | |
1447 | return 0; | |
1448 | } | |
1449 | ||
e76d3630 BW |
1450 | static int i915_context_status(struct seq_file *m, void *unused) |
1451 | { | |
1452 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1453 | struct drm_device *dev = node->minor->dev; | |
1454 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1455 | struct intel_ring_buffer *ring; |
a33afea5 | 1456 | struct i915_hw_context *ctx; |
a168c293 | 1457 | int ret, i; |
e76d3630 BW |
1458 | |
1459 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1460 | if (ret) | |
1461 | return ret; | |
1462 | ||
3e373948 | 1463 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1464 | seq_puts(m, "power context "); |
3e373948 | 1465 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1466 | seq_putc(m, '\n'); |
dc501fbc | 1467 | } |
e76d3630 | 1468 | |
3e373948 | 1469 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1470 | seq_puts(m, "render context "); |
3e373948 | 1471 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1472 | seq_putc(m, '\n'); |
dc501fbc | 1473 | } |
e76d3630 | 1474 | |
a33afea5 BW |
1475 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1476 | seq_puts(m, "HW context "); | |
3ccfd19d | 1477 | describe_ctx(m, ctx); |
a33afea5 BW |
1478 | for_each_ring(ring, dev_priv, i) |
1479 | if (ring->default_context == ctx) | |
1480 | seq_printf(m, "(default context %s) ", ring->name); | |
1481 | ||
1482 | describe_obj(m, ctx->obj); | |
1483 | seq_putc(m, '\n'); | |
a168c293 BW |
1484 | } |
1485 | ||
e76d3630 BW |
1486 | mutex_unlock(&dev->mode_config.mutex); |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
6d794d42 BW |
1491 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1492 | { | |
1493 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1494 | struct drm_device *dev = node->minor->dev; | |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1496 | unsigned forcewake_count; |
6d794d42 | 1497 | |
907b28c5 CW |
1498 | spin_lock_irq(&dev_priv->uncore.lock); |
1499 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1500 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1501 | |
9f1f46a4 | 1502 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
ea16a3cd DV |
1507 | static const char *swizzle_string(unsigned swizzle) |
1508 | { | |
aee56cff | 1509 | switch (swizzle) { |
ea16a3cd DV |
1510 | case I915_BIT_6_SWIZZLE_NONE: |
1511 | return "none"; | |
1512 | case I915_BIT_6_SWIZZLE_9: | |
1513 | return "bit9"; | |
1514 | case I915_BIT_6_SWIZZLE_9_10: | |
1515 | return "bit9/bit10"; | |
1516 | case I915_BIT_6_SWIZZLE_9_11: | |
1517 | return "bit9/bit11"; | |
1518 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1519 | return "bit9/bit10/bit11"; | |
1520 | case I915_BIT_6_SWIZZLE_9_17: | |
1521 | return "bit9/bit17"; | |
1522 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1523 | return "bit9/bit10/bit17"; | |
1524 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1525 | return "unknown"; |
ea16a3cd DV |
1526 | } |
1527 | ||
1528 | return "bug"; | |
1529 | } | |
1530 | ||
1531 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1532 | { | |
1533 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1534 | struct drm_device *dev = node->minor->dev; | |
1535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1536 | int ret; |
1537 | ||
1538 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1539 | if (ret) | |
1540 | return ret; | |
ea16a3cd | 1541 | |
ea16a3cd DV |
1542 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1543 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1544 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1545 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1546 | ||
1547 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1548 | seq_printf(m, "DDC = 0x%08x\n", | |
1549 | I915_READ(DCC)); | |
1550 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1551 | I915_READ16(C0DRB3)); | |
1552 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1553 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1554 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1555 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1556 | I915_READ(MAD_DIMM_C0)); | |
1557 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1558 | I915_READ(MAD_DIMM_C1)); | |
1559 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1560 | I915_READ(MAD_DIMM_C2)); | |
1561 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1562 | I915_READ(TILECTL)); | |
1563 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1564 | I915_READ(ARB_MODE)); | |
1565 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1566 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1567 | } |
1568 | mutex_unlock(&dev->struct_mutex); | |
1569 | ||
1570 | return 0; | |
1571 | } | |
1572 | ||
3cf17fc5 DV |
1573 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1574 | { | |
1575 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1576 | struct drm_device *dev = node->minor->dev; | |
1577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1578 | struct intel_ring_buffer *ring; | |
1579 | int i, ret; | |
1580 | ||
1581 | ||
1582 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1583 | if (ret) | |
1584 | return ret; | |
1585 | if (INTEL_INFO(dev)->gen == 6) | |
1586 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1587 | ||
a2c7f6fd | 1588 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1589 | seq_printf(m, "%s\n", ring->name); |
1590 | if (INTEL_INFO(dev)->gen == 7) | |
1591 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1592 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1593 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1594 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1595 | } | |
1596 | if (dev_priv->mm.aliasing_ppgtt) { | |
1597 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1598 | ||
267f0c90 | 1599 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1600 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1601 | } | |
1602 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1603 | mutex_unlock(&dev->struct_mutex); | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
57f350b6 JB |
1608 | static int i915_dpio_info(struct seq_file *m, void *data) |
1609 | { | |
1610 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1611 | struct drm_device *dev = node->minor->dev; | |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | int ret; | |
1614 | ||
1615 | ||
1616 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1617 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1618 | return 0; |
1619 | } | |
1620 | ||
09153000 | 1621 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1622 | if (ret) |
1623 | return ret; | |
1624 | ||
1625 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1626 | ||
1627 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1628 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1629 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1630 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1631 | |
1632 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1633 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1634 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1635 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1636 | |
1637 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1638 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1639 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1640 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1641 | |
4abb2c39 | 1642 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1643 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1644 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1645 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1646 | |
1647 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1648 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1649 | |
09153000 | 1650 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1651 | |
1652 | return 0; | |
1653 | } | |
1654 | ||
63573eb7 BW |
1655 | static int i915_llc(struct seq_file *m, void *data) |
1656 | { | |
1657 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1658 | struct drm_device *dev = node->minor->dev; | |
1659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1660 | ||
1661 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1662 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1663 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1664 | ||
1665 | return 0; | |
1666 | } | |
1667 | ||
e91fd8c6 RV |
1668 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1669 | { | |
1670 | struct drm_info_node *node = m->private; | |
1671 | struct drm_device *dev = node->minor->dev; | |
1672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1673 | u32 psrperf = 0; |
1674 | bool enabled = false; | |
e91fd8c6 | 1675 | |
a031d709 RV |
1676 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1677 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1678 | |
a031d709 RV |
1679 | enabled = HAS_PSR(dev) && |
1680 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1681 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1682 | |
a031d709 RV |
1683 | if (HAS_PSR(dev)) |
1684 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1685 | EDP_PSR_PERF_CNT_MASK; | |
1686 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1687 | |
1688 | return 0; | |
1689 | } | |
1690 | ||
ec013e7f JB |
1691 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1692 | { | |
1693 | struct drm_info_node *node = m->private; | |
1694 | struct drm_device *dev = node->minor->dev; | |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1696 | u64 power; | |
1697 | u32 units; | |
1698 | ||
1699 | if (INTEL_INFO(dev)->gen < 6) | |
1700 | return -ENODEV; | |
1701 | ||
1702 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1703 | power = (power & 0x1f00) >> 8; | |
1704 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1705 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1706 | power *= units; | |
1707 | ||
1708 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1714 | { | |
1715 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1716 | struct drm_device *dev = node->minor->dev; | |
1717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1718 | ||
1719 | if (!IS_HASWELL(dev)) { | |
1720 | seq_puts(m, "not supported\n"); | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | mutex_lock(&dev_priv->pc8.lock); | |
1725 | seq_printf(m, "Requirements met: %s\n", | |
1726 | yesno(dev_priv->pc8.requirements_met)); | |
1727 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1728 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1729 | seq_printf(m, "IRQs disabled: %s\n", | |
1730 | yesno(dev_priv->pc8.irqs_disabled)); | |
1731 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1732 | mutex_unlock(&dev_priv->pc8.lock); | |
1733 | ||
ec013e7f JB |
1734 | return 0; |
1735 | } | |
1736 | ||
8bf1e9f1 SH |
1737 | static int i915_pipe_crc(struct seq_file *m, void *data) |
1738 | { | |
1739 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1740 | struct drm_device *dev = node->minor->dev; | |
1741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1742 | enum pipe pipe = (enum pipe)node->info_ent->data; | |
b2c88f5b DL |
1743 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1744 | int head, tail; | |
8bf1e9f1 | 1745 | |
926321d5 DV |
1746 | if (dev_priv->pipe_crc[pipe].source == INTEL_PIPE_CRC_SOURCE_NONE) { |
1747 | seq_puts(m, "none\n"); | |
8bf1e9f1 SH |
1748 | return 0; |
1749 | } | |
1750 | ||
ac2300d4 | 1751 | seq_puts(m, " frame CRC1 CRC2 CRC3 CRC4 CRC5\n"); |
b2c88f5b DL |
1752 | head = atomic_read(&pipe_crc->head); |
1753 | tail = atomic_read(&pipe_crc->tail); | |
1754 | ||
1755 | while (CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) >= 1) { | |
1756 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; | |
8bf1e9f1 | 1757 | |
ac2300d4 | 1758 | seq_printf(m, "%8u %8x %8x %8x %8x %8x\n", entry->frame, |
8bf1e9f1 SH |
1759 | entry->crc[0], entry->crc[1], entry->crc[2], |
1760 | entry->crc[3], entry->crc[4]); | |
b2c88f5b DL |
1761 | |
1762 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
1763 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
1764 | atomic_set(&pipe_crc->tail, tail); | |
8bf1e9f1 SH |
1765 | } |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
926321d5 DV |
1770 | static const char *pipe_crc_sources[] = { |
1771 | "none", | |
1772 | "plane1", | |
1773 | "plane2", | |
1774 | "pf", | |
1775 | }; | |
1776 | ||
1777 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
1778 | { | |
1779 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
1780 | return pipe_crc_sources[source]; | |
1781 | } | |
1782 | ||
bd9db02f | 1783 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
1784 | { |
1785 | struct drm_device *dev = m->private; | |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1787 | int i; | |
1788 | ||
1789 | for (i = 0; i < I915_MAX_PIPES; i++) | |
1790 | seq_printf(m, "%c %s\n", pipe_name(i), | |
1791 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
1792 | ||
1793 | return 0; | |
1794 | } | |
1795 | ||
bd9db02f | 1796 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
1797 | { |
1798 | struct drm_device *dev = inode->i_private; | |
1799 | ||
bd9db02f | 1800 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
1801 | } |
1802 | ||
1803 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, | |
1804 | enum intel_pipe_crc_source source) | |
1805 | { | |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 1807 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
926321d5 DV |
1808 | u32 val; |
1809 | ||
1810 | ||
1811 | return -ENODEV; | |
1812 | ||
1813 | if (!IS_IVYBRIDGE(dev)) | |
1814 | return -ENODEV; | |
1815 | ||
cc3da175 DL |
1816 | if (pipe_crc->source == source) |
1817 | return 0; | |
1818 | ||
ae676fcd DL |
1819 | /* forbid changing the source without going back to 'none' */ |
1820 | if (pipe_crc->source && source) | |
1821 | return -EINVAL; | |
1822 | ||
4b584369 DL |
1823 | /* none -> real source transition */ |
1824 | if (source) { | |
e5f75aca DL |
1825 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
1826 | INTEL_PIPE_CRC_ENTRIES_NR, | |
1827 | GFP_KERNEL); | |
1828 | if (!pipe_crc->entries) | |
1829 | return -ENOMEM; | |
1830 | ||
4b584369 DL |
1831 | atomic_set(&pipe_crc->head, 0); |
1832 | atomic_set(&pipe_crc->tail, 0); | |
1833 | } | |
1834 | ||
cc3da175 | 1835 | pipe_crc->source = source; |
926321d5 DV |
1836 | |
1837 | switch (source) { | |
1838 | case INTEL_PIPE_CRC_SOURCE_PLANE1: | |
1839 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
1840 | break; | |
1841 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
1842 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
1843 | break; | |
1844 | case INTEL_PIPE_CRC_SOURCE_PF: | |
1845 | val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
1846 | break; | |
1847 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
1848 | default: | |
1849 | val = 0; | |
1850 | break; | |
1851 | } | |
1852 | ||
1853 | I915_WRITE(PIPE_CRC_CTL(pipe), val); | |
1854 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
1855 | ||
e5f75aca DL |
1856 | /* real source -> none transition */ |
1857 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
1858 | kfree(pipe_crc->entries); | |
1859 | pipe_crc->entries = NULL; | |
1860 | } | |
1861 | ||
926321d5 DV |
1862 | return 0; |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * Parse pipe CRC command strings: | |
b94dec87 DL |
1867 | * command: wsp* object wsp+ name wsp+ source wsp* |
1868 | * object: 'pipe' | |
1869 | * name: (A | B | C) | |
926321d5 DV |
1870 | * source: (none | plane1 | plane2 | pf) |
1871 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
1872 | * | |
1873 | * eg.: | |
b94dec87 DL |
1874 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
1875 | * "pipe A none" -> Stop CRC | |
926321d5 | 1876 | */ |
bd9db02f | 1877 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
1878 | { |
1879 | int n_words = 0; | |
1880 | ||
1881 | while (*buf) { | |
1882 | char *end; | |
1883 | ||
1884 | /* skip leading white space */ | |
1885 | buf = skip_spaces(buf); | |
1886 | if (!*buf) | |
1887 | break; /* end of buffer */ | |
1888 | ||
1889 | /* find end of word */ | |
1890 | for (end = buf; *end && !isspace(*end); end++) | |
1891 | ; | |
1892 | ||
1893 | if (n_words == max_words) { | |
1894 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
1895 | max_words); | |
1896 | return -EINVAL; /* ran out of words[] before bytes */ | |
1897 | } | |
1898 | ||
1899 | if (*end) | |
1900 | *end++ = '\0'; | |
1901 | words[n_words++] = buf; | |
1902 | buf = end; | |
1903 | } | |
1904 | ||
1905 | return n_words; | |
1906 | } | |
1907 | ||
b94dec87 DL |
1908 | enum intel_pipe_crc_object { |
1909 | PIPE_CRC_OBJECT_PIPE, | |
1910 | }; | |
1911 | ||
1912 | static const char *pipe_crc_objects[] = { | |
1913 | "pipe", | |
1914 | }; | |
1915 | ||
1916 | static int | |
bd9db02f | 1917 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
1918 | { |
1919 | int i; | |
1920 | ||
1921 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
1922 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 1923 | *o = i; |
b94dec87 DL |
1924 | return 0; |
1925 | } | |
1926 | ||
1927 | return -EINVAL; | |
1928 | } | |
1929 | ||
bd9db02f | 1930 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
1931 | { |
1932 | const char name = buf[0]; | |
1933 | ||
1934 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
1935 | return -EINVAL; | |
1936 | ||
1937 | *pipe = name - 'A'; | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
1942 | static int | |
bd9db02f | 1943 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
1944 | { |
1945 | int i; | |
1946 | ||
1947 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
1948 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 1949 | *s = i; |
926321d5 DV |
1950 | return 0; |
1951 | } | |
1952 | ||
1953 | return -EINVAL; | |
1954 | } | |
1955 | ||
bd9db02f | 1956 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 1957 | { |
b94dec87 | 1958 | #define N_WORDS 3 |
926321d5 | 1959 | int n_words; |
b94dec87 | 1960 | char *words[N_WORDS]; |
926321d5 | 1961 | enum pipe pipe; |
b94dec87 | 1962 | enum intel_pipe_crc_object object; |
926321d5 DV |
1963 | enum intel_pipe_crc_source source; |
1964 | ||
bd9db02f | 1965 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
1966 | if (n_words != N_WORDS) { |
1967 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
1968 | N_WORDS); | |
1969 | return -EINVAL; | |
1970 | } | |
1971 | ||
bd9db02f | 1972 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 1973 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
1974 | return -EINVAL; |
1975 | } | |
1976 | ||
bd9db02f | 1977 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 1978 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
1979 | return -EINVAL; |
1980 | } | |
1981 | ||
bd9db02f | 1982 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 1983 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
1984 | return -EINVAL; |
1985 | } | |
1986 | ||
1987 | return pipe_crc_set_source(dev, pipe, source); | |
1988 | } | |
1989 | ||
bd9db02f DL |
1990 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
1991 | size_t len, loff_t *offp) | |
926321d5 DV |
1992 | { |
1993 | struct seq_file *m = file->private_data; | |
1994 | struct drm_device *dev = m->private; | |
1995 | char *tmpbuf; | |
1996 | int ret; | |
1997 | ||
1998 | if (len == 0) | |
1999 | return 0; | |
2000 | ||
2001 | if (len > PAGE_SIZE - 1) { | |
2002 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
2003 | PAGE_SIZE); | |
2004 | return -E2BIG; | |
2005 | } | |
2006 | ||
2007 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
2008 | if (!tmpbuf) | |
2009 | return -ENOMEM; | |
2010 | ||
2011 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
2012 | ret = -EFAULT; | |
2013 | goto out; | |
2014 | } | |
2015 | tmpbuf[len] = '\0'; | |
2016 | ||
bd9db02f | 2017 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
2018 | |
2019 | out: | |
2020 | kfree(tmpbuf); | |
2021 | if (ret < 0) | |
2022 | return ret; | |
2023 | ||
2024 | *offp += len; | |
2025 | return len; | |
2026 | } | |
2027 | ||
bd9db02f | 2028 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 2029 | .owner = THIS_MODULE, |
bd9db02f | 2030 | .open = display_crc_ctl_open, |
926321d5 DV |
2031 | .read = seq_read, |
2032 | .llseek = seq_lseek, | |
2033 | .release = single_release, | |
bd9db02f | 2034 | .write = display_crc_ctl_write |
926321d5 DV |
2035 | }; |
2036 | ||
647416f9 KC |
2037 | static int |
2038 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 2039 | { |
647416f9 | 2040 | struct drm_device *dev = data; |
f3cd474b | 2041 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 2042 | |
647416f9 | 2043 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 2044 | |
647416f9 | 2045 | return 0; |
f3cd474b CW |
2046 | } |
2047 | ||
647416f9 KC |
2048 | static int |
2049 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 2050 | { |
647416f9 | 2051 | struct drm_device *dev = data; |
f3cd474b | 2052 | |
647416f9 | 2053 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 2054 | i915_handle_error(dev, val); |
f3cd474b | 2055 | |
647416f9 | 2056 | return 0; |
f3cd474b CW |
2057 | } |
2058 | ||
647416f9 KC |
2059 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
2060 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 2061 | "%llu\n"); |
f3cd474b | 2062 | |
647416f9 KC |
2063 | static int |
2064 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 2065 | { |
647416f9 | 2066 | struct drm_device *dev = data; |
e5eb3d63 | 2067 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 2068 | |
647416f9 | 2069 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 2070 | |
647416f9 | 2071 | return 0; |
e5eb3d63 DV |
2072 | } |
2073 | ||
647416f9 KC |
2074 | static int |
2075 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 2076 | { |
647416f9 | 2077 | struct drm_device *dev = data; |
e5eb3d63 | 2078 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2079 | int ret; |
e5eb3d63 | 2080 | |
647416f9 | 2081 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 2082 | |
22bcfc6a DV |
2083 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2084 | if (ret) | |
2085 | return ret; | |
2086 | ||
99584db3 | 2087 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
2088 | mutex_unlock(&dev->struct_mutex); |
2089 | ||
647416f9 | 2090 | return 0; |
e5eb3d63 DV |
2091 | } |
2092 | ||
647416f9 KC |
2093 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
2094 | i915_ring_stop_get, i915_ring_stop_set, | |
2095 | "0x%08llx\n"); | |
d5442303 | 2096 | |
094f9a54 CW |
2097 | static int |
2098 | i915_ring_missed_irq_get(void *data, u64 *val) | |
2099 | { | |
2100 | struct drm_device *dev = data; | |
2101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2102 | ||
2103 | *val = dev_priv->gpu_error.missed_irq_rings; | |
2104 | return 0; | |
2105 | } | |
2106 | ||
2107 | static int | |
2108 | i915_ring_missed_irq_set(void *data, u64 val) | |
2109 | { | |
2110 | struct drm_device *dev = data; | |
2111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2112 | int ret; | |
2113 | ||
2114 | /* Lock against concurrent debugfs callers */ | |
2115 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2116 | if (ret) | |
2117 | return ret; | |
2118 | dev_priv->gpu_error.missed_irq_rings = val; | |
2119 | mutex_unlock(&dev->struct_mutex); | |
2120 | ||
2121 | return 0; | |
2122 | } | |
2123 | ||
2124 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
2125 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
2126 | "0x%08llx\n"); | |
2127 | ||
2128 | static int | |
2129 | i915_ring_test_irq_get(void *data, u64 *val) | |
2130 | { | |
2131 | struct drm_device *dev = data; | |
2132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2133 | ||
2134 | *val = dev_priv->gpu_error.test_irq_rings; | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
2139 | static int | |
2140 | i915_ring_test_irq_set(void *data, u64 val) | |
2141 | { | |
2142 | struct drm_device *dev = data; | |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2144 | int ret; | |
2145 | ||
2146 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
2147 | ||
2148 | /* Lock against concurrent debugfs callers */ | |
2149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2150 | if (ret) | |
2151 | return ret; | |
2152 | ||
2153 | dev_priv->gpu_error.test_irq_rings = val; | |
2154 | mutex_unlock(&dev->struct_mutex); | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
2160 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
2161 | "0x%08llx\n"); | |
2162 | ||
dd624afd CW |
2163 | #define DROP_UNBOUND 0x1 |
2164 | #define DROP_BOUND 0x2 | |
2165 | #define DROP_RETIRE 0x4 | |
2166 | #define DROP_ACTIVE 0x8 | |
2167 | #define DROP_ALL (DROP_UNBOUND | \ | |
2168 | DROP_BOUND | \ | |
2169 | DROP_RETIRE | \ | |
2170 | DROP_ACTIVE) | |
647416f9 KC |
2171 | static int |
2172 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2173 | { |
647416f9 | 2174 | *val = DROP_ALL; |
dd624afd | 2175 | |
647416f9 | 2176 | return 0; |
dd624afd CW |
2177 | } |
2178 | ||
647416f9 KC |
2179 | static int |
2180 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2181 | { |
647416f9 | 2182 | struct drm_device *dev = data; |
dd624afd CW |
2183 | struct drm_i915_private *dev_priv = dev->dev_private; |
2184 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
2185 | struct i915_address_space *vm; |
2186 | struct i915_vma *vma, *x; | |
647416f9 | 2187 | int ret; |
dd624afd | 2188 | |
647416f9 | 2189 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2190 | |
2191 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2192 | * on ioctls on -EAGAIN. */ | |
2193 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2194 | if (ret) | |
2195 | return ret; | |
2196 | ||
2197 | if (val & DROP_ACTIVE) { | |
2198 | ret = i915_gpu_idle(dev); | |
2199 | if (ret) | |
2200 | goto unlock; | |
2201 | } | |
2202 | ||
2203 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2204 | i915_gem_retire_requests(dev); | |
2205 | ||
2206 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2207 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2208 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2209 | mm_list) { | |
2210 | if (vma->obj->pin_count) | |
2211 | continue; | |
2212 | ||
2213 | ret = i915_vma_unbind(vma); | |
2214 | if (ret) | |
2215 | goto unlock; | |
2216 | } | |
31a46c9c | 2217 | } |
dd624afd CW |
2218 | } |
2219 | ||
2220 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2221 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2222 | global_list) | |
dd624afd CW |
2223 | if (obj->pages_pin_count == 0) { |
2224 | ret = i915_gem_object_put_pages(obj); | |
2225 | if (ret) | |
2226 | goto unlock; | |
2227 | } | |
2228 | } | |
2229 | ||
2230 | unlock: | |
2231 | mutex_unlock(&dev->struct_mutex); | |
2232 | ||
647416f9 | 2233 | return ret; |
dd624afd CW |
2234 | } |
2235 | ||
647416f9 KC |
2236 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2237 | i915_drop_caches_get, i915_drop_caches_set, | |
2238 | "0x%08llx\n"); | |
dd624afd | 2239 | |
647416f9 KC |
2240 | static int |
2241 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2242 | { |
647416f9 | 2243 | struct drm_device *dev = data; |
358733e9 | 2244 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2245 | int ret; |
004777cb DV |
2246 | |
2247 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2248 | return -ENODEV; | |
2249 | ||
5c9669ce TR |
2250 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2251 | ||
4fc688ce | 2252 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2253 | if (ret) |
2254 | return ret; | |
358733e9 | 2255 | |
0a073b84 JB |
2256 | if (IS_VALLEYVIEW(dev)) |
2257 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2258 | dev_priv->rps.max_delay); | |
2259 | else | |
2260 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2261 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2262 | |
647416f9 | 2263 | return 0; |
358733e9 JB |
2264 | } |
2265 | ||
647416f9 KC |
2266 | static int |
2267 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2268 | { |
647416f9 | 2269 | struct drm_device *dev = data; |
358733e9 | 2270 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2271 | int ret; |
004777cb DV |
2272 | |
2273 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2274 | return -ENODEV; | |
358733e9 | 2275 | |
5c9669ce TR |
2276 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2277 | ||
647416f9 | 2278 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2279 | |
4fc688ce | 2280 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2281 | if (ret) |
2282 | return ret; | |
2283 | ||
358733e9 JB |
2284 | /* |
2285 | * Turbo will still be enabled, but won't go above the set value. | |
2286 | */ | |
0a073b84 JB |
2287 | if (IS_VALLEYVIEW(dev)) { |
2288 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2289 | dev_priv->rps.max_delay = val; | |
2290 | gen6_set_rps(dev, val); | |
2291 | } else { | |
2292 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2293 | dev_priv->rps.max_delay = val; | |
2294 | gen6_set_rps(dev, val); | |
2295 | } | |
2296 | ||
4fc688ce | 2297 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2298 | |
647416f9 | 2299 | return 0; |
358733e9 JB |
2300 | } |
2301 | ||
647416f9 KC |
2302 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2303 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2304 | "%llu\n"); |
358733e9 | 2305 | |
647416f9 KC |
2306 | static int |
2307 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2308 | { |
647416f9 | 2309 | struct drm_device *dev = data; |
1523c310 | 2310 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2311 | int ret; |
004777cb DV |
2312 | |
2313 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2314 | return -ENODEV; | |
2315 | ||
5c9669ce TR |
2316 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2317 | ||
4fc688ce | 2318 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2319 | if (ret) |
2320 | return ret; | |
1523c310 | 2321 | |
0a073b84 JB |
2322 | if (IS_VALLEYVIEW(dev)) |
2323 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2324 | dev_priv->rps.min_delay); | |
2325 | else | |
2326 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2327 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2328 | |
647416f9 | 2329 | return 0; |
1523c310 JB |
2330 | } |
2331 | ||
647416f9 KC |
2332 | static int |
2333 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2334 | { |
647416f9 | 2335 | struct drm_device *dev = data; |
1523c310 | 2336 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2337 | int ret; |
004777cb DV |
2338 | |
2339 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2340 | return -ENODEV; | |
1523c310 | 2341 | |
5c9669ce TR |
2342 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2343 | ||
647416f9 | 2344 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2345 | |
4fc688ce | 2346 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2347 | if (ret) |
2348 | return ret; | |
2349 | ||
1523c310 JB |
2350 | /* |
2351 | * Turbo will still be enabled, but won't go below the set value. | |
2352 | */ | |
0a073b84 JB |
2353 | if (IS_VALLEYVIEW(dev)) { |
2354 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2355 | dev_priv->rps.min_delay = val; | |
2356 | valleyview_set_rps(dev, val); | |
2357 | } else { | |
2358 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2359 | dev_priv->rps.min_delay = val; | |
2360 | gen6_set_rps(dev, val); | |
2361 | } | |
4fc688ce | 2362 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2363 | |
647416f9 | 2364 | return 0; |
1523c310 JB |
2365 | } |
2366 | ||
647416f9 KC |
2367 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2368 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2369 | "%llu\n"); |
1523c310 | 2370 | |
647416f9 KC |
2371 | static int |
2372 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2373 | { |
647416f9 | 2374 | struct drm_device *dev = data; |
07b7ddd9 | 2375 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2376 | u32 snpcr; |
647416f9 | 2377 | int ret; |
07b7ddd9 | 2378 | |
004777cb DV |
2379 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2380 | return -ENODEV; | |
2381 | ||
22bcfc6a DV |
2382 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2383 | if (ret) | |
2384 | return ret; | |
2385 | ||
07b7ddd9 JB |
2386 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2387 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2388 | ||
647416f9 | 2389 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2390 | |
647416f9 | 2391 | return 0; |
07b7ddd9 JB |
2392 | } |
2393 | ||
647416f9 KC |
2394 | static int |
2395 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2396 | { |
647416f9 | 2397 | struct drm_device *dev = data; |
07b7ddd9 | 2398 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2399 | u32 snpcr; |
07b7ddd9 | 2400 | |
004777cb DV |
2401 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2402 | return -ENODEV; | |
2403 | ||
647416f9 | 2404 | if (val > 3) |
07b7ddd9 JB |
2405 | return -EINVAL; |
2406 | ||
647416f9 | 2407 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2408 | |
2409 | /* Update the cache sharing policy here as well */ | |
2410 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2411 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2412 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2413 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2414 | ||
647416f9 | 2415 | return 0; |
07b7ddd9 JB |
2416 | } |
2417 | ||
647416f9 KC |
2418 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2419 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2420 | "%llu\n"); | |
07b7ddd9 | 2421 | |
f3cd474b CW |
2422 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2423 | * allocated we need to hook into the minor for release. */ | |
2424 | static int | |
2425 | drm_add_fake_info_node(struct drm_minor *minor, | |
2426 | struct dentry *ent, | |
2427 | const void *key) | |
2428 | { | |
2429 | struct drm_info_node *node; | |
2430 | ||
b14c5679 | 2431 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
f3cd474b CW |
2432 | if (node == NULL) { |
2433 | debugfs_remove(ent); | |
2434 | return -ENOMEM; | |
2435 | } | |
2436 | ||
2437 | node->minor = minor; | |
2438 | node->dent = ent; | |
2439 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2440 | |
2441 | mutex_lock(&minor->debugfs_lock); | |
2442 | list_add(&node->list, &minor->debugfs_list); | |
2443 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2444 | |
2445 | return 0; | |
2446 | } | |
2447 | ||
6d794d42 BW |
2448 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2449 | { | |
2450 | struct drm_device *dev = inode->i_private; | |
2451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2452 | |
075edca4 | 2453 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2454 | return 0; |
2455 | ||
6d794d42 | 2456 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2457 | |
2458 | return 0; | |
2459 | } | |
2460 | ||
c43b5634 | 2461 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2462 | { |
2463 | struct drm_device *dev = inode->i_private; | |
2464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2465 | ||
075edca4 | 2466 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2467 | return 0; |
2468 | ||
6d794d42 | 2469 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2470 | |
2471 | return 0; | |
2472 | } | |
2473 | ||
2474 | static const struct file_operations i915_forcewake_fops = { | |
2475 | .owner = THIS_MODULE, | |
2476 | .open = i915_forcewake_open, | |
2477 | .release = i915_forcewake_release, | |
2478 | }; | |
2479 | ||
2480 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2481 | { | |
2482 | struct drm_device *dev = minor->dev; | |
2483 | struct dentry *ent; | |
2484 | ||
2485 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2486 | S_IRUSR, |
6d794d42 BW |
2487 | root, dev, |
2488 | &i915_forcewake_fops); | |
2489 | if (IS_ERR(ent)) | |
2490 | return PTR_ERR(ent); | |
2491 | ||
8eb57294 | 2492 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2493 | } |
2494 | ||
6a9c308d DV |
2495 | static int i915_debugfs_create(struct dentry *root, |
2496 | struct drm_minor *minor, | |
2497 | const char *name, | |
2498 | const struct file_operations *fops) | |
07b7ddd9 JB |
2499 | { |
2500 | struct drm_device *dev = minor->dev; | |
2501 | struct dentry *ent; | |
2502 | ||
6a9c308d | 2503 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2504 | S_IRUGO | S_IWUSR, |
2505 | root, dev, | |
6a9c308d | 2506 | fops); |
07b7ddd9 JB |
2507 | if (IS_ERR(ent)) |
2508 | return PTR_ERR(ent); | |
2509 | ||
6a9c308d | 2510 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2511 | } |
2512 | ||
27c202ad | 2513 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2514 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2515 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2516 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2517 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2518 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2519 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2520 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2521 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2522 | {"i915_gem_request", i915_gem_request_info, 0}, |
2523 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2524 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2525 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2526 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2527 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2528 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2529 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2530 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2531 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2532 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2533 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2534 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2535 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2536 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2537 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2538 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2539 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2540 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2541 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2542 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2543 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2544 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2545 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2546 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2547 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2548 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2549 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2550 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2551 | {"i915_pc8_status", i915_pc8_status, 0}, |
8bf1e9f1 SH |
2552 | {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A}, |
2553 | {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B}, | |
2554 | {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C}, | |
2017263e | 2555 | }; |
27c202ad | 2556 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2557 | |
2b4bd0e0 | 2558 | static struct i915_debugfs_files { |
34b9674c DV |
2559 | const char *name; |
2560 | const struct file_operations *fops; | |
2561 | } i915_debugfs_files[] = { | |
2562 | {"i915_wedged", &i915_wedged_fops}, | |
2563 | {"i915_max_freq", &i915_max_freq_fops}, | |
2564 | {"i915_min_freq", &i915_min_freq_fops}, | |
2565 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2566 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
2567 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
2568 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
2569 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
2570 | {"i915_error_state", &i915_error_state_fops}, | |
2571 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 2572 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
34b9674c DV |
2573 | }; |
2574 | ||
27c202ad | 2575 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2576 | { |
34b9674c | 2577 | int ret, i; |
f3cd474b | 2578 | |
6d794d42 | 2579 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2580 | if (ret) |
2581 | return ret; | |
6a9c308d | 2582 | |
34b9674c DV |
2583 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2584 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2585 | i915_debugfs_files[i].name, | |
2586 | i915_debugfs_files[i].fops); | |
2587 | if (ret) | |
2588 | return ret; | |
2589 | } | |
40633219 | 2590 | |
27c202ad BG |
2591 | return drm_debugfs_create_files(i915_debugfs_list, |
2592 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2593 | minor->debugfs_root, minor); |
2594 | } | |
2595 | ||
27c202ad | 2596 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2597 | { |
34b9674c DV |
2598 | int i; |
2599 | ||
27c202ad BG |
2600 | drm_debugfs_remove_files(i915_debugfs_list, |
2601 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2602 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2603 | 1, minor); | |
34b9674c DV |
2604 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2605 | struct drm_info_list *info_list = | |
2606 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2607 | ||
2608 | drm_debugfs_remove_files(info_list, 1, minor); | |
2609 | } | |
2017263e BG |
2610 | } |
2611 | ||
2612 | #endif /* CONFIG_DEBUG_FS */ |