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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
418e3cd8 CW |
38 | static __always_inline void seq_print_param(struct seq_file *m, |
39 | const char *name, | |
40 | const char *type, | |
41 | const void *x) | |
42 | { | |
43 | if (!__builtin_strcmp(type, "bool")) | |
44 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
45 | else if (!__builtin_strcmp(type, "int")) | |
46 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
47 | else if (!__builtin_strcmp(type, "unsigned int")) | |
48 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
49 | else if (!__builtin_strcmp(type, "char *")) |
50 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
51 | else |
52 | BUILD_BUG(); | |
53 | } | |
54 | ||
70d39fe4 CW |
55 | static int i915_capabilities(struct seq_file *m, void *data) |
56 | { | |
36cdd013 DW |
57 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
58 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 59 | |
36cdd013 | 60 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 61 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 63 | |
79fc46df | 64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 66 | #undef PRINT_FLAG |
70d39fe4 | 67 | |
418e3cd8 CW |
68 | kernel_param_lock(THIS_MODULE); |
69 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
70 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
71 | #undef PRINT_PARAM | |
72 | kernel_param_unlock(THIS_MODULE); | |
73 | ||
70d39fe4 CW |
74 | return 0; |
75 | } | |
2017263e | 76 | |
a7363de7 | 77 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 78 | { |
573adb39 | 79 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
80 | } |
81 | ||
a7363de7 | 82 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
83 | { |
84 | return obj->pin_display ? 'p' : ' '; | |
85 | } | |
86 | ||
a7363de7 | 87 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 88 | { |
3e510a8e | 89 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 90 | default: |
be12a86b TU |
91 | case I915_TILING_NONE: return ' '; |
92 | case I915_TILING_X: return 'X'; | |
93 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 94 | } |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 98 | { |
275f039d | 99 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
100 | } |
101 | ||
a7363de7 | 102 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 103 | { |
a4f5ea64 | 104 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
105 | } |
106 | ||
ca1543be TU |
107 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
108 | { | |
109 | u64 size = 0; | |
110 | struct i915_vma *vma; | |
111 | ||
1c7f4bca | 112 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 113 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
114 | size += vma->node.size; |
115 | } | |
116 | ||
117 | return size; | |
118 | } | |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
b4716185 | 123 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 124 | struct intel_engine_cs *engine; |
1d693bcc | 125 | struct i915_vma *vma; |
faf5bf0a | 126 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
127 | int pin_count = 0; |
128 | ||
188c1ab7 CW |
129 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
130 | ||
d07f0e59 | 131 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 132 | &obj->base, |
be12a86b | 133 | get_active_flag(obj), |
37811fcc CW |
134 | get_pin_flag(obj), |
135 | get_tiling_flag(obj), | |
1d693bcc | 136 | get_global_flag(obj), |
be12a86b | 137 | get_pin_mapped_flag(obj), |
a05a5862 | 138 | obj->base.size / 1024, |
37811fcc | 139 | obj->base.read_domains, |
d07f0e59 | 140 | obj->base.write_domain, |
36cdd013 | 141 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
142 | obj->mm.dirty ? " dirty" : "", |
143 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
144 | if (obj->base.name) |
145 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 146 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 147 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 148 | pin_count++; |
ba0635ff DC |
149 | } |
150 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
151 | if (obj->pin_display) |
152 | seq_printf(m, " (display)"); | |
1c7f4bca | 153 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
154 | if (!drm_mm_node_allocated(&vma->node)) |
155 | continue; | |
156 | ||
8d2fdc3f | 157 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 158 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 159 | vma->node.start, vma->node.size); |
21976853 CW |
160 | if (i915_vma_is_ggtt(vma)) { |
161 | switch (vma->ggtt_view.type) { | |
162 | case I915_GGTT_VIEW_NORMAL: | |
163 | seq_puts(m, ", normal"); | |
164 | break; | |
165 | ||
166 | case I915_GGTT_VIEW_PARTIAL: | |
167 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
168 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
169 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
170 | break; |
171 | ||
172 | case I915_GGTT_VIEW_ROTATED: | |
173 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
174 | vma->ggtt_view.rotated.plane[0].width, |
175 | vma->ggtt_view.rotated.plane[0].height, | |
176 | vma->ggtt_view.rotated.plane[0].stride, | |
177 | vma->ggtt_view.rotated.plane[0].offset, | |
178 | vma->ggtt_view.rotated.plane[1].width, | |
179 | vma->ggtt_view.rotated.plane[1].height, | |
180 | vma->ggtt_view.rotated.plane[1].stride, | |
181 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
182 | break; |
183 | ||
184 | default: | |
185 | MISSING_CASE(vma->ggtt_view.type); | |
186 | break; | |
187 | } | |
188 | } | |
49ef5294 CW |
189 | if (vma->fence) |
190 | seq_printf(m, " , fence: %d%s", | |
191 | vma->fence->id, | |
192 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 193 | seq_puts(m, ")"); |
1d693bcc | 194 | } |
c1ad11fc | 195 | if (obj->stolen) |
440fd528 | 196 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 197 | |
d07f0e59 | 198 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
199 | if (engine) |
200 | seq_printf(m, " (%s)", engine->name); | |
201 | ||
faf5bf0a CW |
202 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
203 | if (frontbuffer_bits) | |
204 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
205 | } |
206 | ||
e637d2cb | 207 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 208 | { |
e637d2cb CW |
209 | const struct drm_i915_gem_object *a = |
210 | *(const struct drm_i915_gem_object **)A; | |
211 | const struct drm_i915_gem_object *b = | |
212 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 213 | |
2d05fa16 RV |
214 | if (a->stolen->start < b->stolen->start) |
215 | return -1; | |
216 | if (a->stolen->start > b->stolen->start) | |
217 | return 1; | |
218 | return 0; | |
6d2b8885 CW |
219 | } |
220 | ||
221 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
222 | { | |
36cdd013 DW |
223 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
224 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 225 | struct drm_i915_gem_object **objects; |
6d2b8885 | 226 | struct drm_i915_gem_object *obj; |
c44ef60e | 227 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
228 | unsigned long total, count, n; |
229 | int ret; | |
230 | ||
231 | total = READ_ONCE(dev_priv->mm.object_count); | |
232 | objects = drm_malloc_ab(total, sizeof(*objects)); | |
233 | if (!objects) | |
234 | return -ENOMEM; | |
6d2b8885 CW |
235 | |
236 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
237 | if (ret) | |
e637d2cb | 238 | goto out; |
6d2b8885 CW |
239 | |
240 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 241 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
e637d2cb CW |
242 | if (count == total) |
243 | break; | |
244 | ||
6d2b8885 CW |
245 | if (obj->stolen == NULL) |
246 | continue; | |
247 | ||
e637d2cb | 248 | objects[count++] = obj; |
6d2b8885 | 249 | total_obj_size += obj->base.size; |
ca1543be | 250 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 251 | |
6d2b8885 | 252 | } |
56cea323 | 253 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
e637d2cb CW |
254 | if (count == total) |
255 | break; | |
256 | ||
6d2b8885 CW |
257 | if (obj->stolen == NULL) |
258 | continue; | |
259 | ||
e637d2cb | 260 | objects[count++] = obj; |
6d2b8885 | 261 | total_obj_size += obj->base.size; |
6d2b8885 | 262 | } |
e637d2cb CW |
263 | |
264 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
265 | ||
6d2b8885 | 266 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 267 | for (n = 0; n < count; n++) { |
6d2b8885 | 268 | seq_puts(m, " "); |
e637d2cb | 269 | describe_obj(m, objects[n]); |
6d2b8885 | 270 | seq_putc(m, '\n'); |
6d2b8885 | 271 | } |
e637d2cb | 272 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 273 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
274 | |
275 | mutex_unlock(&dev->struct_mutex); | |
276 | out: | |
277 | drm_free_large(objects); | |
278 | return ret; | |
6d2b8885 CW |
279 | } |
280 | ||
2db8e9d6 | 281 | struct file_stats { |
6313c204 | 282 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
283 | unsigned long count; |
284 | u64 total, unbound; | |
285 | u64 global, shared; | |
286 | u64 active, inactive; | |
2db8e9d6 CW |
287 | }; |
288 | ||
289 | static int per_file_stats(int id, void *ptr, void *data) | |
290 | { | |
291 | struct drm_i915_gem_object *obj = ptr; | |
292 | struct file_stats *stats = data; | |
6313c204 | 293 | struct i915_vma *vma; |
2db8e9d6 CW |
294 | |
295 | stats->count++; | |
296 | stats->total += obj->base.size; | |
15717de2 CW |
297 | if (!obj->bind_count) |
298 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
299 | if (obj->base.name || obj->base.dma_buf) |
300 | stats->shared += obj->base.size; | |
301 | ||
894eeecc CW |
302 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
303 | if (!drm_mm_node_allocated(&vma->node)) | |
304 | continue; | |
6313c204 | 305 | |
3272db53 | 306 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
307 | stats->global += vma->node.size; |
308 | } else { | |
309 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 310 | |
2bfa996e | 311 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 312 | continue; |
6313c204 | 313 | } |
894eeecc | 314 | |
b0decaf7 | 315 | if (i915_vma_is_active(vma)) |
894eeecc CW |
316 | stats->active += vma->node.size; |
317 | else | |
318 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
319 | } |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
b0da1b79 CW |
324 | #define print_file_stats(m, name, stats) do { \ |
325 | if (stats.count) \ | |
c44ef60e | 326 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
327 | name, \ |
328 | stats.count, \ | |
329 | stats.total, \ | |
330 | stats.active, \ | |
331 | stats.inactive, \ | |
332 | stats.global, \ | |
333 | stats.shared, \ | |
334 | stats.unbound); \ | |
335 | } while (0) | |
493018dc BV |
336 | |
337 | static void print_batch_pool_stats(struct seq_file *m, | |
338 | struct drm_i915_private *dev_priv) | |
339 | { | |
340 | struct drm_i915_gem_object *obj; | |
341 | struct file_stats stats; | |
e2f80391 | 342 | struct intel_engine_cs *engine; |
3b3f1650 | 343 | enum intel_engine_id id; |
b4ac5afc | 344 | int j; |
493018dc BV |
345 | |
346 | memset(&stats, 0, sizeof(stats)); | |
347 | ||
3b3f1650 | 348 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 349 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 350 | list_for_each_entry(obj, |
e2f80391 | 351 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
352 | batch_pool_link) |
353 | per_file_stats(0, obj, &stats); | |
354 | } | |
06fbca71 | 355 | } |
493018dc | 356 | |
b0da1b79 | 357 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
358 | } |
359 | ||
15da9565 CW |
360 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
361 | { | |
362 | struct i915_gem_context *ctx = ptr; | |
363 | int n; | |
364 | ||
365 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
366 | if (ctx->engine[n].state) | |
bf3783e5 | 367 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 368 | if (ctx->engine[n].ring) |
57e88531 | 369 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
370 | } |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static void print_context_stats(struct seq_file *m, | |
376 | struct drm_i915_private *dev_priv) | |
377 | { | |
36cdd013 | 378 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
379 | struct file_stats stats; |
380 | struct drm_file *file; | |
381 | ||
382 | memset(&stats, 0, sizeof(stats)); | |
383 | ||
36cdd013 | 384 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
385 | if (dev_priv->kernel_context) |
386 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
387 | ||
36cdd013 | 388 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
389 | struct drm_i915_file_private *fpriv = file->driver_priv; |
390 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
391 | } | |
36cdd013 | 392 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
393 | |
394 | print_file_stats(m, "[k]contexts", stats); | |
395 | } | |
396 | ||
36cdd013 | 397 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 398 | { |
36cdd013 DW |
399 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
400 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 401 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
402 | u32 count, mapped_count, purgeable_count, dpy_count; |
403 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 404 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 405 | struct drm_file *file; |
73aa808f CW |
406 | int ret; |
407 | ||
408 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
3ef7f228 | 412 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
413 | dev_priv->mm.object_count, |
414 | dev_priv->mm.object_memory); | |
415 | ||
1544c42e CW |
416 | size = count = 0; |
417 | mapped_size = mapped_count = 0; | |
418 | purgeable_size = purgeable_count = 0; | |
56cea323 | 419 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
420 | size += obj->base.size; |
421 | ++count; | |
422 | ||
a4f5ea64 | 423 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
424 | purgeable_size += obj->base.size; |
425 | ++purgeable_count; | |
426 | } | |
427 | ||
a4f5ea64 | 428 | if (obj->mm.mapping) { |
2bd160a1 CW |
429 | mapped_count++; |
430 | mapped_size += obj->base.size; | |
be19b10d | 431 | } |
b7abb714 | 432 | } |
c44ef60e | 433 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 434 | |
2bd160a1 | 435 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 436 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
437 | size += obj->base.size; |
438 | ++count; | |
439 | ||
30154650 | 440 | if (obj->pin_display) { |
2bd160a1 CW |
441 | dpy_size += obj->base.size; |
442 | ++dpy_count; | |
6299f992 | 443 | } |
2bd160a1 | 444 | |
a4f5ea64 | 445 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
446 | purgeable_size += obj->base.size; |
447 | ++purgeable_count; | |
448 | } | |
2bd160a1 | 449 | |
a4f5ea64 | 450 | if (obj->mm.mapping) { |
2bd160a1 CW |
451 | mapped_count++; |
452 | mapped_size += obj->base.size; | |
be19b10d | 453 | } |
6299f992 | 454 | } |
2bd160a1 CW |
455 | seq_printf(m, "%u bound objects, %llu bytes\n", |
456 | count, size); | |
c44ef60e | 457 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 458 | purgeable_count, purgeable_size); |
2bd160a1 CW |
459 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
460 | mapped_count, mapped_size); | |
461 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
462 | dpy_count, dpy_size); | |
6299f992 | 463 | |
c44ef60e | 464 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 465 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 466 | |
493018dc BV |
467 | seq_putc(m, '\n'); |
468 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
469 | mutex_unlock(&dev->struct_mutex); |
470 | ||
471 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 472 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
473 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
474 | struct file_stats stats; | |
c84455b4 CW |
475 | struct drm_i915_file_private *file_priv = file->driver_priv; |
476 | struct drm_i915_gem_request *request; | |
3ec2f427 | 477 | struct task_struct *task; |
2db8e9d6 CW |
478 | |
479 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 480 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 481 | spin_lock(&file->table_lock); |
2db8e9d6 | 482 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 483 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
484 | /* |
485 | * Although we have a valid reference on file->pid, that does | |
486 | * not guarantee that the task_struct who called get_pid() is | |
487 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
488 | * Therefore, we need to protect this ->comm access using RCU. | |
489 | */ | |
c84455b4 CW |
490 | mutex_lock(&dev->struct_mutex); |
491 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
492 | struct drm_i915_gem_request, | |
c8659efa | 493 | client_link); |
3ec2f427 | 494 | rcu_read_lock(); |
c84455b4 CW |
495 | task = pid_task(request && request->ctx->pid ? |
496 | request->ctx->pid : file->pid, | |
497 | PIDTYPE_PID); | |
493018dc | 498 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 499 | rcu_read_unlock(); |
c84455b4 | 500 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 501 | } |
1d2ac403 | 502 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
503 | |
504 | return 0; | |
505 | } | |
506 | ||
aee56cff | 507 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 508 | { |
9f25d007 | 509 | struct drm_info_node *node = m->private; |
36cdd013 DW |
510 | struct drm_i915_private *dev_priv = node_to_i915(node); |
511 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 512 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 513 | struct drm_i915_gem_object *obj; |
c44ef60e | 514 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
515 | int count, ret; |
516 | ||
517 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 522 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 523 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
524 | continue; |
525 | ||
267f0c90 | 526 | seq_puts(m, " "); |
08c18323 | 527 | describe_obj(m, obj); |
267f0c90 | 528 | seq_putc(m, '\n'); |
08c18323 | 529 | total_obj_size += obj->base.size; |
ca1543be | 530 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
531 | count++; |
532 | } | |
533 | ||
534 | mutex_unlock(&dev->struct_mutex); | |
535 | ||
c44ef60e | 536 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
537 | count, total_obj_size, total_gtt_size); |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
4e5359cd SF |
542 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
543 | { | |
36cdd013 DW |
544 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
545 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 546 | struct intel_crtc *crtc; |
8a270ebf DV |
547 | int ret; |
548 | ||
549 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
550 | if (ret) | |
551 | return ret; | |
4e5359cd | 552 | |
d3fcc808 | 553 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
554 | const char pipe = pipe_name(crtc->pipe); |
555 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 556 | struct intel_flip_work *work; |
4e5359cd | 557 | |
5e2d7afc | 558 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
559 | work = crtc->flip_work; |
560 | if (work == NULL) { | |
9db4a9c7 | 561 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
562 | pipe, plane); |
563 | } else { | |
5a21b665 DV |
564 | u32 pending; |
565 | u32 addr; | |
566 | ||
567 | pending = atomic_read(&work->pending); | |
568 | if (pending) { | |
569 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
570 | pipe, plane); | |
571 | } else { | |
572 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
573 | pipe, plane); | |
574 | } | |
575 | if (work->flip_queued_req) { | |
24327f83 | 576 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 577 | |
312c3c47 | 578 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 579 | engine->name, |
24327f83 | 580 | work->flip_queued_req->global_seqno, |
312c3c47 | 581 | intel_engine_last_submit(engine), |
1b7744e7 | 582 | intel_engine_get_seqno(engine), |
f69a02c9 | 583 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
584 | } else |
585 | seq_printf(m, "Flip not associated with any ring\n"); | |
586 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
587 | work->flip_queued_vblank, | |
588 | work->flip_ready_vblank, | |
589 | intel_crtc_get_vblank_counter(crtc)); | |
590 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
591 | ||
36cdd013 | 592 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
593 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
594 | else | |
595 | addr = I915_READ(DSPADDR(crtc->plane)); | |
596 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
597 | ||
598 | if (work->pending_flip_obj) { | |
599 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
600 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
601 | } |
602 | } | |
5e2d7afc | 603 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
604 | } |
605 | ||
8a270ebf DV |
606 | mutex_unlock(&dev->struct_mutex); |
607 | ||
4e5359cd SF |
608 | return 0; |
609 | } | |
610 | ||
493018dc BV |
611 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
612 | { | |
36cdd013 DW |
613 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
614 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 615 | struct drm_i915_gem_object *obj; |
e2f80391 | 616 | struct intel_engine_cs *engine; |
3b3f1650 | 617 | enum intel_engine_id id; |
8d9d5744 | 618 | int total = 0; |
b4ac5afc | 619 | int ret, j; |
493018dc BV |
620 | |
621 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
622 | if (ret) | |
623 | return ret; | |
624 | ||
3b3f1650 | 625 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 626 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
627 | int count; |
628 | ||
629 | count = 0; | |
630 | list_for_each_entry(obj, | |
e2f80391 | 631 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
632 | batch_pool_link) |
633 | count++; | |
634 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 635 | engine->name, j, count); |
8d9d5744 CW |
636 | |
637 | list_for_each_entry(obj, | |
e2f80391 | 638 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
639 | batch_pool_link) { |
640 | seq_puts(m, " "); | |
641 | describe_obj(m, obj); | |
642 | seq_putc(m, '\n'); | |
643 | } | |
644 | ||
645 | total += count; | |
06fbca71 | 646 | } |
493018dc BV |
647 | } |
648 | ||
8d9d5744 | 649 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
650 | |
651 | mutex_unlock(&dev->struct_mutex); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
1b36595f CW |
656 | static void print_request(struct seq_file *m, |
657 | struct drm_i915_gem_request *rq, | |
658 | const char *prefix) | |
659 | { | |
20311bd3 | 660 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 661 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 662 | rq->priotree.priority, |
1b36595f | 663 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 664 | rq->timeline->common->name); |
1b36595f CW |
665 | } |
666 | ||
2017263e BG |
667 | static int i915_gem_request_info(struct seq_file *m, void *data) |
668 | { | |
36cdd013 DW |
669 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
670 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 671 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
672 | struct intel_engine_cs *engine; |
673 | enum intel_engine_id id; | |
b4ac5afc | 674 | int ret, any; |
de227ef0 CW |
675 | |
676 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
677 | if (ret) | |
678 | return ret; | |
2017263e | 679 | |
2d1070b2 | 680 | any = 0; |
3b3f1650 | 681 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
682 | int count; |
683 | ||
684 | count = 0; | |
73cb9701 | 685 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
686 | count++; |
687 | if (count == 0) | |
a2c7f6fd CW |
688 | continue; |
689 | ||
e2f80391 | 690 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 691 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 692 | print_request(m, req, " "); |
2d1070b2 CW |
693 | |
694 | any++; | |
2017263e | 695 | } |
de227ef0 CW |
696 | mutex_unlock(&dev->struct_mutex); |
697 | ||
2d1070b2 | 698 | if (any == 0) |
267f0c90 | 699 | seq_puts(m, "No requests\n"); |
c2c347a9 | 700 | |
2017263e BG |
701 | return 0; |
702 | } | |
703 | ||
b2223497 | 704 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 705 | struct intel_engine_cs *engine) |
b2223497 | 706 | { |
688e6c72 CW |
707 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
708 | struct rb_node *rb; | |
709 | ||
12471ba8 | 710 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 711 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 712 | |
61d3dc70 | 713 | spin_lock_irq(&b->rb_lock); |
688e6c72 | 714 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 715 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
716 | |
717 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
718 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
719 | } | |
61d3dc70 | 720 | spin_unlock_irq(&b->rb_lock); |
b2223497 CW |
721 | } |
722 | ||
2017263e BG |
723 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
724 | { | |
36cdd013 | 725 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 726 | struct intel_engine_cs *engine; |
3b3f1650 | 727 | enum intel_engine_id id; |
2017263e | 728 | |
3b3f1650 | 729 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 730 | i915_ring_seqno_info(m, engine); |
de227ef0 | 731 | |
2017263e BG |
732 | return 0; |
733 | } | |
734 | ||
735 | ||
736 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
737 | { | |
36cdd013 | 738 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 739 | struct intel_engine_cs *engine; |
3b3f1650 | 740 | enum intel_engine_id id; |
4bb05040 | 741 | int i, pipe; |
de227ef0 | 742 | |
c8c8fb33 | 743 | intel_runtime_pm_get(dev_priv); |
2017263e | 744 | |
36cdd013 | 745 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
746 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
747 | I915_READ(GEN8_MASTER_IRQ)); | |
748 | ||
749 | seq_printf(m, "Display IER:\t%08x\n", | |
750 | I915_READ(VLV_IER)); | |
751 | seq_printf(m, "Display IIR:\t%08x\n", | |
752 | I915_READ(VLV_IIR)); | |
753 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
754 | I915_READ(VLV_IIR_RW)); | |
755 | seq_printf(m, "Display IMR:\t%08x\n", | |
756 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
757 | for_each_pipe(dev_priv, pipe) { |
758 | enum intel_display_power_domain power_domain; | |
759 | ||
760 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
761 | if (!intel_display_power_get_if_enabled(dev_priv, | |
762 | power_domain)) { | |
763 | seq_printf(m, "Pipe %c power disabled\n", | |
764 | pipe_name(pipe)); | |
765 | continue; | |
766 | } | |
767 | ||
74e1ca8c VS |
768 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
769 | pipe_name(pipe), | |
770 | I915_READ(PIPESTAT(pipe))); | |
771 | ||
9c870d03 CW |
772 | intel_display_power_put(dev_priv, power_domain); |
773 | } | |
774 | ||
775 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
776 | seq_printf(m, "Port hotplug:\t%08x\n", |
777 | I915_READ(PORT_HOTPLUG_EN)); | |
778 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
779 | I915_READ(VLV_DPFLIPSTAT)); | |
780 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
781 | I915_READ(DPINVGTT)); | |
9c870d03 | 782 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
783 | |
784 | for (i = 0; i < 4; i++) { | |
785 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
786 | i, I915_READ(GEN8_GT_IMR(i))); | |
787 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
788 | i, I915_READ(GEN8_GT_IIR(i))); | |
789 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
790 | i, I915_READ(GEN8_GT_IER(i))); | |
791 | } | |
792 | ||
793 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
794 | I915_READ(GEN8_PCU_IMR)); | |
795 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
796 | I915_READ(GEN8_PCU_IIR)); | |
797 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
798 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 799 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
800 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
801 | I915_READ(GEN8_MASTER_IRQ)); | |
802 | ||
803 | for (i = 0; i < 4; i++) { | |
804 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
805 | i, I915_READ(GEN8_GT_IMR(i))); | |
806 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
807 | i, I915_READ(GEN8_GT_IIR(i))); | |
808 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
809 | i, I915_READ(GEN8_GT_IER(i))); | |
810 | } | |
811 | ||
055e393f | 812 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
813 | enum intel_display_power_domain power_domain; |
814 | ||
815 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
816 | if (!intel_display_power_get_if_enabled(dev_priv, | |
817 | power_domain)) { | |
22c59960 PZ |
818 | seq_printf(m, "Pipe %c power disabled\n", |
819 | pipe_name(pipe)); | |
820 | continue; | |
821 | } | |
a123f157 | 822 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
823 | pipe_name(pipe), |
824 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 825 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
826 | pipe_name(pipe), |
827 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 828 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
829 | pipe_name(pipe), |
830 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
831 | |
832 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
833 | } |
834 | ||
835 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
836 | I915_READ(GEN8_DE_PORT_IMR)); | |
837 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
838 | I915_READ(GEN8_DE_PORT_IIR)); | |
839 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
840 | I915_READ(GEN8_DE_PORT_IER)); | |
841 | ||
842 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
843 | I915_READ(GEN8_DE_MISC_IMR)); | |
844 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
845 | I915_READ(GEN8_DE_MISC_IIR)); | |
846 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
847 | I915_READ(GEN8_DE_MISC_IER)); | |
848 | ||
849 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
850 | I915_READ(GEN8_PCU_IMR)); | |
851 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
852 | I915_READ(GEN8_PCU_IIR)); | |
853 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
854 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 855 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
856 | seq_printf(m, "Display IER:\t%08x\n", |
857 | I915_READ(VLV_IER)); | |
858 | seq_printf(m, "Display IIR:\t%08x\n", | |
859 | I915_READ(VLV_IIR)); | |
860 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
861 | I915_READ(VLV_IIR_RW)); | |
862 | seq_printf(m, "Display IMR:\t%08x\n", | |
863 | I915_READ(VLV_IMR)); | |
4f4631af CW |
864 | for_each_pipe(dev_priv, pipe) { |
865 | enum intel_display_power_domain power_domain; | |
866 | ||
867 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
868 | if (!intel_display_power_get_if_enabled(dev_priv, | |
869 | power_domain)) { | |
870 | seq_printf(m, "Pipe %c power disabled\n", | |
871 | pipe_name(pipe)); | |
872 | continue; | |
873 | } | |
874 | ||
7e231dbe JB |
875 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
876 | pipe_name(pipe), | |
877 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
878 | intel_display_power_put(dev_priv, power_domain); |
879 | } | |
7e231dbe JB |
880 | |
881 | seq_printf(m, "Master IER:\t%08x\n", | |
882 | I915_READ(VLV_MASTER_IER)); | |
883 | ||
884 | seq_printf(m, "Render IER:\t%08x\n", | |
885 | I915_READ(GTIER)); | |
886 | seq_printf(m, "Render IIR:\t%08x\n", | |
887 | I915_READ(GTIIR)); | |
888 | seq_printf(m, "Render IMR:\t%08x\n", | |
889 | I915_READ(GTIMR)); | |
890 | ||
891 | seq_printf(m, "PM IER:\t\t%08x\n", | |
892 | I915_READ(GEN6_PMIER)); | |
893 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
894 | I915_READ(GEN6_PMIIR)); | |
895 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
896 | I915_READ(GEN6_PMIMR)); | |
897 | ||
898 | seq_printf(m, "Port hotplug:\t%08x\n", | |
899 | I915_READ(PORT_HOTPLUG_EN)); | |
900 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
901 | I915_READ(VLV_DPFLIPSTAT)); | |
902 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
903 | I915_READ(DPINVGTT)); | |
904 | ||
36cdd013 | 905 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
906 | seq_printf(m, "Interrupt enable: %08x\n", |
907 | I915_READ(IER)); | |
908 | seq_printf(m, "Interrupt identity: %08x\n", | |
909 | I915_READ(IIR)); | |
910 | seq_printf(m, "Interrupt mask: %08x\n", | |
911 | I915_READ(IMR)); | |
055e393f | 912 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
913 | seq_printf(m, "Pipe %c stat: %08x\n", |
914 | pipe_name(pipe), | |
915 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
916 | } else { |
917 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
918 | I915_READ(DEIER)); | |
919 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
920 | I915_READ(DEIIR)); | |
921 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
922 | I915_READ(DEIMR)); | |
923 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
924 | I915_READ(SDEIER)); | |
925 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
926 | I915_READ(SDEIIR)); | |
927 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
928 | I915_READ(SDEIMR)); | |
929 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
930 | I915_READ(GTIER)); | |
931 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
932 | I915_READ(GTIIR)); | |
933 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
934 | I915_READ(GTIMR)); | |
935 | } | |
3b3f1650 | 936 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 937 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
938 | seq_printf(m, |
939 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 940 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 941 | } |
e2f80391 | 942 | i915_ring_seqno_info(m, engine); |
9862e600 | 943 | } |
c8c8fb33 | 944 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 945 | |
2017263e BG |
946 | return 0; |
947 | } | |
948 | ||
a6172a80 CW |
949 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
950 | { | |
36cdd013 DW |
951 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
952 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
953 | int i, ret; |
954 | ||
955 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
956 | if (ret) | |
957 | return ret; | |
a6172a80 | 958 | |
a6172a80 CW |
959 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
960 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 961 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 962 | |
6c085a72 CW |
963 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
964 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 965 | if (!vma) |
267f0c90 | 966 | seq_puts(m, "unused"); |
c2c347a9 | 967 | else |
49ef5294 | 968 | describe_obj(m, vma->obj); |
267f0c90 | 969 | seq_putc(m, '\n'); |
a6172a80 CW |
970 | } |
971 | ||
05394f39 | 972 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
973 | return 0; |
974 | } | |
975 | ||
98a2f411 | 976 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
977 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
978 | size_t count, loff_t *pos) | |
d5442303 | 979 | { |
5a4c6f1b CW |
980 | struct i915_gpu_state *error = file->private_data; |
981 | struct drm_i915_error_state_buf str; | |
982 | ssize_t ret; | |
983 | loff_t tmp; | |
d5442303 | 984 | |
5a4c6f1b CW |
985 | if (!error) |
986 | return 0; | |
d5442303 | 987 | |
5a4c6f1b CW |
988 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
989 | if (ret) | |
990 | return ret; | |
d5442303 | 991 | |
5a4c6f1b CW |
992 | ret = i915_error_state_to_str(&str, error); |
993 | if (ret) | |
994 | goto out; | |
d5442303 | 995 | |
5a4c6f1b CW |
996 | tmp = 0; |
997 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
998 | if (ret < 0) | |
999 | goto out; | |
d5442303 | 1000 | |
5a4c6f1b CW |
1001 | *pos = str.start + ret; |
1002 | out: | |
1003 | i915_error_state_buf_release(&str); | |
1004 | return ret; | |
1005 | } | |
edc3d884 | 1006 | |
5a4c6f1b CW |
1007 | static int gpu_state_release(struct inode *inode, struct file *file) |
1008 | { | |
1009 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1010 | return 0; |
d5442303 DV |
1011 | } |
1012 | ||
5a4c6f1b | 1013 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1014 | { |
090e5fe3 | 1015 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 1016 | struct i915_gpu_state *gpu; |
d5442303 | 1017 | |
090e5fe3 CW |
1018 | intel_runtime_pm_get(i915); |
1019 | gpu = i915_capture_gpu_state(i915); | |
1020 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
1021 | if (!gpu) |
1022 | return -ENOMEM; | |
d5442303 | 1023 | |
5a4c6f1b | 1024 | file->private_data = gpu; |
edc3d884 MK |
1025 | return 0; |
1026 | } | |
1027 | ||
5a4c6f1b CW |
1028 | static const struct file_operations i915_gpu_info_fops = { |
1029 | .owner = THIS_MODULE, | |
1030 | .open = i915_gpu_info_open, | |
1031 | .read = gpu_state_read, | |
1032 | .llseek = default_llseek, | |
1033 | .release = gpu_state_release, | |
1034 | }; | |
1035 | ||
1036 | static ssize_t | |
1037 | i915_error_state_write(struct file *filp, | |
1038 | const char __user *ubuf, | |
1039 | size_t cnt, | |
1040 | loff_t *ppos) | |
4dc955f7 | 1041 | { |
5a4c6f1b | 1042 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1043 | |
5a4c6f1b CW |
1044 | if (!error) |
1045 | return 0; | |
edc3d884 | 1046 | |
5a4c6f1b CW |
1047 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1048 | i915_reset_error_state(error->i915); | |
edc3d884 | 1049 | |
5a4c6f1b CW |
1050 | return cnt; |
1051 | } | |
edc3d884 | 1052 | |
5a4c6f1b CW |
1053 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1054 | { | |
1055 | file->private_data = i915_first_error_state(inode->i_private); | |
1056 | return 0; | |
d5442303 DV |
1057 | } |
1058 | ||
1059 | static const struct file_operations i915_error_state_fops = { | |
1060 | .owner = THIS_MODULE, | |
1061 | .open = i915_error_state_open, | |
5a4c6f1b | 1062 | .read = gpu_state_read, |
d5442303 DV |
1063 | .write = i915_error_state_write, |
1064 | .llseek = default_llseek, | |
5a4c6f1b | 1065 | .release = gpu_state_release, |
d5442303 | 1066 | }; |
98a2f411 CW |
1067 | #endif |
1068 | ||
647416f9 KC |
1069 | static int |
1070 | i915_next_seqno_set(void *data, u64 val) | |
1071 | { | |
36cdd013 DW |
1072 | struct drm_i915_private *dev_priv = data; |
1073 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1074 | int ret; |
1075 | ||
40633219 MK |
1076 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1077 | if (ret) | |
1078 | return ret; | |
1079 | ||
73cb9701 | 1080 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1081 | mutex_unlock(&dev->struct_mutex); |
1082 | ||
647416f9 | 1083 | return ret; |
40633219 MK |
1084 | } |
1085 | ||
647416f9 | 1086 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1087 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1088 | "0x%llx\n"); |
40633219 | 1089 | |
adb4bd12 | 1090 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1091 | { |
36cdd013 | 1092 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1093 | int ret = 0; |
1094 | ||
1095 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1096 | |
36cdd013 | 1097 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1098 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1099 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1100 | ||
1101 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1102 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1103 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1104 | MEMSTAT_VID_SHIFT); | |
1105 | seq_printf(m, "Current P-state: %d\n", | |
1106 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1107 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1108 | u32 freq_sts; |
1109 | ||
1110 | mutex_lock(&dev_priv->rps.hw_lock); | |
1111 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1112 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1113 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1114 | ||
1115 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1116 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1117 | ||
1118 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1119 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1120 | ||
1121 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1122 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1123 | ||
1124 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1125 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1126 | ||
1127 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1128 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1129 | ||
1130 | seq_printf(m, | |
1131 | "efficient (RPe) frequency: %d MHz\n", | |
1132 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1133 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1134 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1135 | u32 rp_state_limits; |
1136 | u32 gt_perf_status; | |
1137 | u32 rp_state_cap; | |
0d8f9491 | 1138 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1139 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1140 | u32 rpupei, rpcurup, rpprevup; |
1141 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1142 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1143 | int max_freq; |
1144 | ||
35040562 | 1145 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1146 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1147 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1148 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1149 | } else { | |
1150 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1151 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1152 | } | |
1153 | ||
3b8d8d91 | 1154 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1155 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1156 | |
8e8c06cd | 1157 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1158 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1159 | reqf >>= 23; |
1160 | else { | |
1161 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1162 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1163 | reqf >>= 24; |
1164 | else | |
1165 | reqf >>= 25; | |
1166 | } | |
7c59a9c1 | 1167 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1168 | |
0d8f9491 CW |
1169 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1170 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1171 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1172 | ||
ccab5c82 | 1173 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1174 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1175 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1176 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1177 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1178 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1179 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1180 | if (IS_GEN9(dev_priv)) |
60260a5b | 1181 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1182 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1183 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1184 | else | |
1185 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1186 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1187 | |
59bad947 | 1188 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1189 | |
36cdd013 | 1190 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1191 | pm_ier = I915_READ(GEN6_PMIER); |
1192 | pm_imr = I915_READ(GEN6_PMIMR); | |
1193 | pm_isr = I915_READ(GEN6_PMISR); | |
1194 | pm_iir = I915_READ(GEN6_PMIIR); | |
1195 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1196 | } else { | |
1197 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1198 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1199 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1200 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1201 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1202 | } | |
0d8f9491 | 1203 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1204 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 SAK |
1205 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
1206 | dev_priv->rps.pm_intrmsk_mbz); | |
3b8d8d91 | 1207 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1208 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1209 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1210 | seq_printf(m, "Render p-state VID: %d\n", |
1211 | gt_perf_status & 0xff); | |
1212 | seq_printf(m, "Render p-state limit: %d\n", | |
1213 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1214 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1215 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1216 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1217 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1218 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1219 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1220 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1221 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1222 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1223 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1224 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1225 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1226 | seq_printf(m, "Up threshold: %d%%\n", |
1227 | dev_priv->rps.up_threshold); | |
1228 | ||
d6cda9c7 AG |
1229 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1230 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1231 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1232 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1233 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1234 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1235 | seq_printf(m, "Down threshold: %d%%\n", |
1236 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1237 | |
cc3f90f0 | 1238 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1239 | rp_state_cap >> 16) & 0xff; |
b976dc53 | 1240 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1241 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1242 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1243 | |
1244 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
b976dc53 | 1245 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1246 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1247 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1248 | |
cc3f90f0 | 1249 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1250 | rp_state_cap >> 0) & 0xff; |
b976dc53 | 1251 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1252 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1253 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1254 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1255 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1256 | |
d86ed34a CW |
1257 | seq_printf(m, "Current freq: %d MHz\n", |
1258 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1259 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1260 | seq_printf(m, "Idle freq: %d MHz\n", |
1261 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1262 | seq_printf(m, "Min freq: %d MHz\n", |
1263 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1264 | seq_printf(m, "Boost freq: %d MHz\n", |
1265 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1266 | seq_printf(m, "Max freq: %d MHz\n", |
1267 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1268 | seq_printf(m, | |
1269 | "efficient (RPe) frequency: %d MHz\n", | |
1270 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1271 | } else { |
267f0c90 | 1272 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1273 | } |
f97108d1 | 1274 | |
49cd97a3 | 1275 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1276 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1277 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1278 | ||
c8c8fb33 PZ |
1279 | intel_runtime_pm_put(dev_priv); |
1280 | return ret; | |
f97108d1 JB |
1281 | } |
1282 | ||
d636951e BW |
1283 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1284 | struct seq_file *m, | |
1285 | struct intel_instdone *instdone) | |
1286 | { | |
f9e61372 BW |
1287 | int slice; |
1288 | int subslice; | |
1289 | ||
d636951e BW |
1290 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1291 | instdone->instdone); | |
1292 | ||
1293 | if (INTEL_GEN(dev_priv) <= 3) | |
1294 | return; | |
1295 | ||
1296 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1297 | instdone->slice_common); | |
1298 | ||
1299 | if (INTEL_GEN(dev_priv) <= 6) | |
1300 | return; | |
1301 | ||
f9e61372 BW |
1302 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1303 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1304 | slice, subslice, instdone->sampler[slice][subslice]); | |
1305 | ||
1306 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1307 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1308 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1309 | } |
1310 | ||
f654449a CW |
1311 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1312 | { | |
36cdd013 | 1313 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1314 | struct intel_engine_cs *engine; |
666796da TU |
1315 | u64 acthd[I915_NUM_ENGINES]; |
1316 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1317 | struct intel_instdone instdone; |
c3232b18 | 1318 | enum intel_engine_id id; |
f654449a | 1319 | |
8af29b0c | 1320 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1321 | seq_puts(m, "Wedged\n"); |
1322 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1323 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1324 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1325 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1326 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1327 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1328 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1329 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1330 | |
f654449a | 1331 | if (!i915.enable_hangcheck) { |
8c185eca | 1332 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1333 | return 0; |
1334 | } | |
1335 | ||
ebbc7546 MK |
1336 | intel_runtime_pm_get(dev_priv); |
1337 | ||
3b3f1650 | 1338 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1339 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1340 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1341 | } |
1342 | ||
3b3f1650 | 1343 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1344 | |
ebbc7546 MK |
1345 | intel_runtime_pm_put(dev_priv); |
1346 | ||
8352aea3 CW |
1347 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1348 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1349 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1350 | jiffies)); | |
8352aea3 CW |
1351 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1352 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1353 | else | |
1354 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1355 | |
f73b5674 CW |
1356 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1357 | ||
3b3f1650 | 1358 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1359 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1360 | struct rb_node *rb; | |
1361 | ||
e2f80391 | 1362 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1363 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1364 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1365 | intel_engine_last_submit(engine), |
1366 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1367 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1368 | yesno(intel_engine_has_waiter(engine)), |
1369 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1370 | &dev_priv->gpu_error.missed_irq_rings)), |
1371 | yesno(engine->hangcheck.stalled)); | |
1372 | ||
61d3dc70 | 1373 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1374 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1375 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1376 | |
1377 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1378 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1379 | } | |
61d3dc70 | 1380 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1381 | |
f654449a | 1382 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1383 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1384 | (long long)acthd[id]); |
3fe3b030 MK |
1385 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1386 | hangcheck_action_to_str(engine->hangcheck.action), | |
1387 | engine->hangcheck.action, | |
1388 | jiffies_to_msecs(jiffies - | |
1389 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1390 | |
e2f80391 | 1391 | if (engine->id == RCS) { |
d636951e | 1392 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1393 | |
d636951e | 1394 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1395 | |
d636951e | 1396 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1397 | |
d636951e BW |
1398 | i915_instdone_info(dev_priv, m, |
1399 | &engine->hangcheck.instdone); | |
61642ff0 | 1400 | } |
f654449a CW |
1401 | } |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
4d85529d | 1406 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1407 | { |
36cdd013 | 1408 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1409 | u32 rgvmodectl, rstdbyctl; |
1410 | u16 crstandvid; | |
616fdb5a | 1411 | |
616fdb5a BW |
1412 | rgvmodectl = I915_READ(MEMMODECTL); |
1413 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1414 | crstandvid = I915_READ16(CRSTANDVID); | |
1415 | ||
742f491d | 1416 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1417 | seq_printf(m, "Boost freq: %d\n", |
1418 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1419 | MEMMODE_BOOST_FREQ_SHIFT); | |
1420 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1421 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1422 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1423 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1424 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1425 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1426 | seq_printf(m, "Starting frequency: P%d\n", |
1427 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1428 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1429 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1430 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1431 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1432 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1433 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1434 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1435 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1436 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1437 | case RSX_STATUS_ON: | |
267f0c90 | 1438 | seq_puts(m, "on\n"); |
88271da3 JB |
1439 | break; |
1440 | case RSX_STATUS_RC1: | |
267f0c90 | 1441 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1442 | break; |
1443 | case RSX_STATUS_RC1E: | |
267f0c90 | 1444 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1445 | break; |
1446 | case RSX_STATUS_RS1: | |
267f0c90 | 1447 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1448 | break; |
1449 | case RSX_STATUS_RS2: | |
267f0c90 | 1450 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1451 | break; |
1452 | case RSX_STATUS_RS3: | |
267f0c90 | 1453 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1454 | break; |
1455 | default: | |
267f0c90 | 1456 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1457 | break; |
1458 | } | |
f97108d1 JB |
1459 | |
1460 | return 0; | |
1461 | } | |
1462 | ||
f65367b5 | 1463 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1464 | { |
233ebf57 | 1465 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1466 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1467 | unsigned int tmp; |
b2cff0db | 1468 | |
233ebf57 | 1469 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1470 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1471 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1472 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1473 | |
b2cff0db CW |
1474 | return 0; |
1475 | } | |
1476 | ||
1362877e MK |
1477 | static void print_rc6_res(struct seq_file *m, |
1478 | const char *title, | |
1479 | const i915_reg_t reg) | |
1480 | { | |
1481 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1482 | ||
1483 | seq_printf(m, "%s %u (%llu us)\n", | |
1484 | title, I915_READ(reg), | |
1485 | intel_rc6_residency_us(dev_priv, reg)); | |
1486 | } | |
1487 | ||
b2cff0db CW |
1488 | static int vlv_drpc_info(struct seq_file *m) |
1489 | { | |
36cdd013 | 1490 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1491 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1492 | |
6b312cd3 | 1493 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1494 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1495 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1496 | ||
1497 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1498 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1499 | seq_printf(m, "Turbo enabled: %s\n", | |
1500 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1501 | seq_printf(m, "HW control enabled: %s\n", | |
1502 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1503 | seq_printf(m, "SW control enabled: %s\n", | |
1504 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1505 | GEN6_RP_MEDIA_SW_MODE)); | |
1506 | seq_printf(m, "RC6 Enabled: %s\n", | |
1507 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1508 | GEN6_RC_CTL_EI_MODE(1)))); | |
1509 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1510 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1511 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1512 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1513 | |
1362877e MK |
1514 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1515 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1516 | |
f65367b5 | 1517 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1518 | } |
1519 | ||
4d85529d BW |
1520 | static int gen6_drpc_info(struct seq_file *m) |
1521 | { | |
36cdd013 | 1522 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ecd8faea | 1523 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1524 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1525 | unsigned forcewake_count; |
cf632bd6 | 1526 | int count = 0; |
93b525dc | 1527 | |
cf632bd6 | 1528 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1529 | if (forcewake_count) { |
267f0c90 DL |
1530 | seq_puts(m, "RC information inaccurate because somebody " |
1531 | "holds a forcewake reference \n"); | |
4d85529d BW |
1532 | } else { |
1533 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1534 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1535 | udelay(10); | |
1536 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1537 | } | |
1538 | ||
75aa3f63 | 1539 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1540 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1541 | |
1542 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1543 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1544 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1545 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1546 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1547 | } | |
cf632bd6 | 1548 | |
44cbd338 BW |
1549 | mutex_lock(&dev_priv->rps.hw_lock); |
1550 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1551 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1552 | |
1553 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1554 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1555 | seq_printf(m, "HW control enabled: %s\n", | |
1556 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1557 | seq_printf(m, "SW control enabled: %s\n", | |
1558 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1559 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1560 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1561 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1562 | seq_printf(m, "RC6 Enabled: %s\n", | |
1563 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1564 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1565 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1566 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1567 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1568 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1569 | } | |
4d85529d BW |
1570 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1571 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1572 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1573 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1574 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1575 | switch (gt_core_status & GEN6_RCn_MASK) { |
1576 | case GEN6_RC0: | |
1577 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1578 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1579 | else |
267f0c90 | 1580 | seq_puts(m, "on\n"); |
4d85529d BW |
1581 | break; |
1582 | case GEN6_RC3: | |
267f0c90 | 1583 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1584 | break; |
1585 | case GEN6_RC6: | |
267f0c90 | 1586 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1587 | break; |
1588 | case GEN6_RC7: | |
267f0c90 | 1589 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1590 | break; |
1591 | default: | |
267f0c90 | 1592 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1593 | break; |
1594 | } | |
1595 | ||
1596 | seq_printf(m, "Core Power Down: %s\n", | |
1597 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1598 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1599 | seq_printf(m, "Render Power Well: %s\n", |
1600 | (gen9_powergate_status & | |
1601 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1602 | seq_printf(m, "Media Power Well: %s\n", | |
1603 | (gen9_powergate_status & | |
1604 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1605 | } | |
cce66a28 BW |
1606 | |
1607 | /* Not exactly sure what this is */ | |
1362877e MK |
1608 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1609 | GEN6_GT_GFX_RC6_LOCKED); | |
1610 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1611 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1612 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1613 | |
ecd8faea BW |
1614 | seq_printf(m, "RC6 voltage: %dmV\n", |
1615 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1616 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1617 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1618 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1619 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1620 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1621 | } |
1622 | ||
1623 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1624 | { | |
36cdd013 | 1625 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1626 | int err; |
1627 | ||
1628 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1629 | |
36cdd013 | 1630 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1631 | err = vlv_drpc_info(m); |
36cdd013 | 1632 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1633 | err = gen6_drpc_info(m); |
4d85529d | 1634 | else |
cf632bd6 CW |
1635 | err = ironlake_drpc_info(m); |
1636 | ||
1637 | intel_runtime_pm_put(dev_priv); | |
1638 | ||
1639 | return err; | |
4d85529d BW |
1640 | } |
1641 | ||
9a851789 DV |
1642 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1643 | { | |
36cdd013 | 1644 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1645 | |
1646 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1647 | dev_priv->fb_tracking.busy_bits); | |
1648 | ||
1649 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1650 | dev_priv->fb_tracking.flip_bits); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
b5e50c3f JB |
1655 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1656 | { | |
36cdd013 | 1657 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1658 | |
36cdd013 | 1659 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1660 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1661 | return 0; |
1662 | } | |
1663 | ||
36623ef8 | 1664 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1665 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1666 | |
0e631adc | 1667 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1668 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1669 | else |
1670 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1671 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1672 | |
0fc6a9dc PZ |
1673 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1674 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1675 | BDW_FBC_COMPRESSION_MASK : | |
1676 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1677 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1678 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1679 | } | |
31b9df10 | 1680 | |
25ad93fd | 1681 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1682 | intel_runtime_pm_put(dev_priv); |
1683 | ||
b5e50c3f JB |
1684 | return 0; |
1685 | } | |
1686 | ||
da46f936 RV |
1687 | static int i915_fbc_fc_get(void *data, u64 *val) |
1688 | { | |
36cdd013 | 1689 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1690 | |
36cdd013 | 1691 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1692 | return -ENODEV; |
1693 | ||
da46f936 | 1694 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1695 | |
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | static int i915_fbc_fc_set(void *data, u64 val) | |
1700 | { | |
36cdd013 | 1701 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1702 | u32 reg; |
1703 | ||
36cdd013 | 1704 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1705 | return -ENODEV; |
1706 | ||
25ad93fd | 1707 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1708 | |
1709 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1710 | dev_priv->fbc.false_color = val; | |
1711 | ||
1712 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1713 | (reg | FBC_CTL_FALSE_COLOR) : | |
1714 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1715 | ||
25ad93fd | 1716 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1717 | return 0; |
1718 | } | |
1719 | ||
1720 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1721 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1722 | "%llu\n"); | |
1723 | ||
92d44621 PZ |
1724 | static int i915_ips_status(struct seq_file *m, void *unused) |
1725 | { | |
36cdd013 | 1726 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1727 | |
36cdd013 | 1728 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1729 | seq_puts(m, "not supported\n"); |
1730 | return 0; | |
1731 | } | |
1732 | ||
36623ef8 PZ |
1733 | intel_runtime_pm_get(dev_priv); |
1734 | ||
0eaa53f0 RV |
1735 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1736 | yesno(i915.enable_ips)); | |
1737 | ||
36cdd013 | 1738 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1739 | seq_puts(m, "Currently: unknown\n"); |
1740 | } else { | |
1741 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1742 | seq_puts(m, "Currently: enabled\n"); | |
1743 | else | |
1744 | seq_puts(m, "Currently: disabled\n"); | |
1745 | } | |
92d44621 | 1746 | |
36623ef8 PZ |
1747 | intel_runtime_pm_put(dev_priv); |
1748 | ||
92d44621 PZ |
1749 | return 0; |
1750 | } | |
1751 | ||
4a9bef37 JB |
1752 | static int i915_sr_status(struct seq_file *m, void *unused) |
1753 | { | |
36cdd013 | 1754 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1755 | bool sr_enabled = false; |
1756 | ||
36623ef8 | 1757 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1758 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1759 | |
7342a72c CW |
1760 | if (INTEL_GEN(dev_priv) >= 9) |
1761 | /* no global SR status; inspect per-plane WM */; | |
1762 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1763 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1764 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1765 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1766 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1767 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1768 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1769 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1770 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1771 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1772 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1773 | |
9c870d03 | 1774 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1775 | intel_runtime_pm_put(dev_priv); |
1776 | ||
08c4d7fc | 1777 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1778 | |
1779 | return 0; | |
1780 | } | |
1781 | ||
7648fa99 JB |
1782 | static int i915_emon_status(struct seq_file *m, void *unused) |
1783 | { | |
36cdd013 DW |
1784 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1785 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1786 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1787 | int ret; |
1788 | ||
36cdd013 | 1789 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1790 | return -ENODEV; |
1791 | ||
de227ef0 CW |
1792 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1793 | if (ret) | |
1794 | return ret; | |
7648fa99 JB |
1795 | |
1796 | temp = i915_mch_val(dev_priv); | |
1797 | chipset = i915_chipset_val(dev_priv); | |
1798 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1799 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1800 | |
1801 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1802 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1803 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1804 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1805 | ||
1806 | return 0; | |
1807 | } | |
1808 | ||
23b2f8bb JB |
1809 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1810 | { | |
36cdd013 | 1811 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1812 | int ret = 0; |
23b2f8bb | 1813 | int gpu_freq, ia_freq; |
f936ec34 | 1814 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1815 | |
26310346 | 1816 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1817 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1818 | return 0; |
1819 | } | |
1820 | ||
5bfa0199 PZ |
1821 | intel_runtime_pm_get(dev_priv); |
1822 | ||
4fc688ce | 1823 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1824 | if (ret) |
5bfa0199 | 1825 | goto out; |
23b2f8bb | 1826 | |
b976dc53 | 1827 | if (IS_GEN9_BC(dev_priv)) { |
f936ec34 AG |
1828 | /* Convert GT frequency to 50 HZ units */ |
1829 | min_gpu_freq = | |
1830 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1831 | max_gpu_freq = | |
1832 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1833 | } else { | |
1834 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1835 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1836 | } | |
1837 | ||
267f0c90 | 1838 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1839 | |
f936ec34 | 1840 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1841 | ia_freq = gpu_freq; |
1842 | sandybridge_pcode_read(dev_priv, | |
1843 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1844 | &ia_freq); | |
3ebecd07 | 1845 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1846 | intel_gpu_freq(dev_priv, (gpu_freq * |
b976dc53 RV |
1847 | (IS_GEN9_BC(dev_priv) ? |
1848 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1849 | ((ia_freq >> 0) & 0xff) * 100, |
1850 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1851 | } |
1852 | ||
4fc688ce | 1853 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1854 | |
5bfa0199 PZ |
1855 | out: |
1856 | intel_runtime_pm_put(dev_priv); | |
1857 | return ret; | |
23b2f8bb JB |
1858 | } |
1859 | ||
44834a67 CW |
1860 | static int i915_opregion(struct seq_file *m, void *unused) |
1861 | { | |
36cdd013 DW |
1862 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1863 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1864 | struct intel_opregion *opregion = &dev_priv->opregion; |
1865 | int ret; | |
1866 | ||
1867 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1868 | if (ret) | |
0d38f009 | 1869 | goto out; |
44834a67 | 1870 | |
2455a8e4 JN |
1871 | if (opregion->header) |
1872 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1873 | |
1874 | mutex_unlock(&dev->struct_mutex); | |
1875 | ||
0d38f009 | 1876 | out: |
44834a67 CW |
1877 | return 0; |
1878 | } | |
1879 | ||
ada8f955 JN |
1880 | static int i915_vbt(struct seq_file *m, void *unused) |
1881 | { | |
36cdd013 | 1882 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1883 | |
1884 | if (opregion->vbt) | |
1885 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1886 | ||
1887 | return 0; | |
1888 | } | |
1889 | ||
37811fcc CW |
1890 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1891 | { | |
36cdd013 DW |
1892 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1893 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1894 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1895 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1896 | int ret; |
1897 | ||
1898 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1899 | if (ret) | |
1900 | return ret; | |
37811fcc | 1901 | |
0695726e | 1902 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1903 | if (dev_priv->fbdev) { |
1904 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1905 | |
1906 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1907 | fbdev_fb->base.width, | |
1908 | fbdev_fb->base.height, | |
b00c600e | 1909 | fbdev_fb->base.format->depth, |
272725c7 | 1910 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1911 | fbdev_fb->base.modifier, |
25bcce94 CW |
1912 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1913 | describe_obj(m, fbdev_fb->obj); | |
1914 | seq_putc(m, '\n'); | |
1915 | } | |
4520f53a | 1916 | #endif |
37811fcc | 1917 | |
4b096ac1 | 1918 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1919 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1920 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1921 | if (fb == fbdev_fb) | |
37811fcc CW |
1922 | continue; |
1923 | ||
c1ca506d | 1924 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1925 | fb->base.width, |
1926 | fb->base.height, | |
b00c600e | 1927 | fb->base.format->depth, |
272725c7 | 1928 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1929 | fb->base.modifier, |
747a598f | 1930 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1931 | describe_obj(m, fb->obj); |
267f0c90 | 1932 | seq_putc(m, '\n'); |
37811fcc | 1933 | } |
4b096ac1 | 1934 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1935 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1936 | |
1937 | return 0; | |
1938 | } | |
1939 | ||
7e37f889 | 1940 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1941 | { |
fe085f13 CW |
1942 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1943 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1944 | } |
1945 | ||
e76d3630 BW |
1946 | static int i915_context_status(struct seq_file *m, void *unused) |
1947 | { | |
36cdd013 DW |
1948 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1949 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1950 | struct intel_engine_cs *engine; |
e2efd130 | 1951 | struct i915_gem_context *ctx; |
3b3f1650 | 1952 | enum intel_engine_id id; |
c3232b18 | 1953 | int ret; |
e76d3630 | 1954 | |
f3d28878 | 1955 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1956 | if (ret) |
1957 | return ret; | |
1958 | ||
a33afea5 | 1959 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1960 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1961 | if (ctx->pid) { |
d28b99ab CW |
1962 | struct task_struct *task; |
1963 | ||
c84455b4 | 1964 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1965 | if (task) { |
1966 | seq_printf(m, "(%s [%d]) ", | |
1967 | task->comm, task->pid); | |
1968 | put_task_struct(task); | |
1969 | } | |
c84455b4 CW |
1970 | } else if (IS_ERR(ctx->file_priv)) { |
1971 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1972 | } else { |
1973 | seq_puts(m, "(kernel) "); | |
1974 | } | |
1975 | ||
bca44d80 CW |
1976 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1977 | seq_putc(m, '\n'); | |
c9fe99bd | 1978 | |
3b3f1650 | 1979 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1980 | struct intel_context *ce = &ctx->engine[engine->id]; |
1981 | ||
1982 | seq_printf(m, "%s: ", engine->name); | |
1983 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1984 | if (ce->state) | |
bf3783e5 | 1985 | describe_obj(m, ce->state->obj); |
dca33ecc | 1986 | if (ce->ring) |
7e37f889 | 1987 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1988 | seq_putc(m, '\n'); |
c9fe99bd | 1989 | } |
a33afea5 | 1990 | |
a33afea5 | 1991 | seq_putc(m, '\n'); |
a168c293 BW |
1992 | } |
1993 | ||
f3d28878 | 1994 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1995 | |
1996 | return 0; | |
1997 | } | |
1998 | ||
064ca1d2 | 1999 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2000 | struct i915_gem_context *ctx, |
0bc40be8 | 2001 | struct intel_engine_cs *engine) |
064ca1d2 | 2002 | { |
bf3783e5 | 2003 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2004 | struct page *page; |
064ca1d2 | 2005 | int j; |
064ca1d2 | 2006 | |
7069b144 CW |
2007 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2008 | ||
bf3783e5 CW |
2009 | if (!vma) { |
2010 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2011 | return; |
2012 | } | |
2013 | ||
bf3783e5 CW |
2014 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2015 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2016 | i915_ggtt_offset(vma)); |
064ca1d2 | 2017 | |
a4f5ea64 | 2018 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2019 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2020 | return; |
2021 | } | |
2022 | ||
bf3783e5 CW |
2023 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2024 | if (page) { | |
2025 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2026 | |
2027 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2028 | seq_printf(m, |
2029 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2030 | j * 4, | |
064ca1d2 TD |
2031 | reg_state[j], reg_state[j + 1], |
2032 | reg_state[j + 2], reg_state[j + 3]); | |
2033 | } | |
2034 | kunmap_atomic(reg_state); | |
2035 | } | |
2036 | ||
a4f5ea64 | 2037 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2038 | seq_putc(m, '\n'); |
2039 | } | |
2040 | ||
c0ab1ae9 BW |
2041 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2042 | { | |
36cdd013 DW |
2043 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2044 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2045 | struct intel_engine_cs *engine; |
e2efd130 | 2046 | struct i915_gem_context *ctx; |
3b3f1650 | 2047 | enum intel_engine_id id; |
b4ac5afc | 2048 | int ret; |
c0ab1ae9 BW |
2049 | |
2050 | if (!i915.enable_execlists) { | |
2051 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2052 | return 0; | |
2053 | } | |
2054 | ||
2055 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2056 | if (ret) | |
2057 | return ret; | |
2058 | ||
e28e404c | 2059 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2060 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2061 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2062 | |
2063 | mutex_unlock(&dev->struct_mutex); | |
2064 | ||
2065 | return 0; | |
2066 | } | |
2067 | ||
ea16a3cd DV |
2068 | static const char *swizzle_string(unsigned swizzle) |
2069 | { | |
aee56cff | 2070 | switch (swizzle) { |
ea16a3cd DV |
2071 | case I915_BIT_6_SWIZZLE_NONE: |
2072 | return "none"; | |
2073 | case I915_BIT_6_SWIZZLE_9: | |
2074 | return "bit9"; | |
2075 | case I915_BIT_6_SWIZZLE_9_10: | |
2076 | return "bit9/bit10"; | |
2077 | case I915_BIT_6_SWIZZLE_9_11: | |
2078 | return "bit9/bit11"; | |
2079 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2080 | return "bit9/bit10/bit11"; | |
2081 | case I915_BIT_6_SWIZZLE_9_17: | |
2082 | return "bit9/bit17"; | |
2083 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2084 | return "bit9/bit10/bit17"; | |
2085 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2086 | return "unknown"; |
ea16a3cd DV |
2087 | } |
2088 | ||
2089 | return "bug"; | |
2090 | } | |
2091 | ||
2092 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2093 | { | |
36cdd013 | 2094 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2095 | |
c8c8fb33 | 2096 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2097 | |
ea16a3cd DV |
2098 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2099 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2100 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2101 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2102 | ||
36cdd013 | 2103 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2104 | seq_printf(m, "DDC = 0x%08x\n", |
2105 | I915_READ(DCC)); | |
656bfa3a DV |
2106 | seq_printf(m, "DDC2 = 0x%08x\n", |
2107 | I915_READ(DCC2)); | |
ea16a3cd DV |
2108 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2109 | I915_READ16(C0DRB3)); | |
2110 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2111 | I915_READ16(C1DRB3)); | |
36cdd013 | 2112 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2113 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2114 | I915_READ(MAD_DIMM_C0)); | |
2115 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2116 | I915_READ(MAD_DIMM_C1)); | |
2117 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2118 | I915_READ(MAD_DIMM_C2)); | |
2119 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2120 | I915_READ(TILECTL)); | |
36cdd013 | 2121 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2122 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2123 | I915_READ(GAMTARBMODE)); | |
2124 | else | |
2125 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2126 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2127 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2128 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2129 | } |
656bfa3a DV |
2130 | |
2131 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2132 | seq_puts(m, "L-shaped memory detected\n"); | |
2133 | ||
c8c8fb33 | 2134 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2135 | |
2136 | return 0; | |
2137 | } | |
2138 | ||
1c60fef5 BW |
2139 | static int per_file_ctx(int id, void *ptr, void *data) |
2140 | { | |
e2efd130 | 2141 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2142 | struct seq_file *m = data; |
ae6c4806 DV |
2143 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2144 | ||
2145 | if (!ppgtt) { | |
2146 | seq_printf(m, " no ppgtt for context %d\n", | |
2147 | ctx->user_handle); | |
2148 | return 0; | |
2149 | } | |
1c60fef5 | 2150 | |
f83d6518 OM |
2151 | if (i915_gem_context_is_default(ctx)) |
2152 | seq_puts(m, " default context:\n"); | |
2153 | else | |
821d66dd | 2154 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2155 | ppgtt->debug_dump(ppgtt, m); |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
36cdd013 DW |
2160 | static void gen8_ppgtt_info(struct seq_file *m, |
2161 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2162 | { |
77df6772 | 2163 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2164 | struct intel_engine_cs *engine; |
2165 | enum intel_engine_id id; | |
b4ac5afc | 2166 | int i; |
3cf17fc5 | 2167 | |
77df6772 BW |
2168 | if (!ppgtt) |
2169 | return; | |
2170 | ||
3b3f1650 | 2171 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2172 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2173 | for (i = 0; i < 4; i++) { |
e2f80391 | 2174 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2175 | pdp <<= 32; |
e2f80391 | 2176 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2177 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2178 | } |
2179 | } | |
2180 | } | |
2181 | ||
36cdd013 DW |
2182 | static void gen6_ppgtt_info(struct seq_file *m, |
2183 | struct drm_i915_private *dev_priv) | |
77df6772 | 2184 | { |
e2f80391 | 2185 | struct intel_engine_cs *engine; |
3b3f1650 | 2186 | enum intel_engine_id id; |
3cf17fc5 | 2187 | |
7e22dbbb | 2188 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2189 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2190 | ||
3b3f1650 | 2191 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2192 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2193 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2194 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2195 | I915_READ(RING_MODE_GEN7(engine))); | |
2196 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2197 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2198 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2199 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2200 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2201 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2202 | } |
2203 | if (dev_priv->mm.aliasing_ppgtt) { | |
2204 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2205 | ||
267f0c90 | 2206 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2207 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2208 | |
87d60b63 | 2209 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2210 | } |
1c60fef5 | 2211 | |
3cf17fc5 | 2212 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2213 | } |
2214 | ||
2215 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2216 | { | |
36cdd013 DW |
2217 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2218 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2219 | struct drm_file *file; |
637ee29e | 2220 | int ret; |
77df6772 | 2221 | |
637ee29e CW |
2222 | mutex_lock(&dev->filelist_mutex); |
2223 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2224 | if (ret) |
637ee29e CW |
2225 | goto out_unlock; |
2226 | ||
c8c8fb33 | 2227 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2228 | |
36cdd013 DW |
2229 | if (INTEL_GEN(dev_priv) >= 8) |
2230 | gen8_ppgtt_info(m, dev_priv); | |
2231 | else if (INTEL_GEN(dev_priv) >= 6) | |
2232 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2233 | |
ea91e401 MT |
2234 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2235 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2236 | struct task_struct *task; |
ea91e401 | 2237 | |
7cb5dff8 | 2238 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2239 | if (!task) { |
2240 | ret = -ESRCH; | |
637ee29e | 2241 | goto out_rpm; |
06812760 | 2242 | } |
7cb5dff8 GT |
2243 | seq_printf(m, "\nproc: %s\n", task->comm); |
2244 | put_task_struct(task); | |
ea91e401 MT |
2245 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2246 | (void *)(unsigned long)m); | |
2247 | } | |
2248 | ||
637ee29e | 2249 | out_rpm: |
c8c8fb33 | 2250 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2251 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2252 | out_unlock: |
2253 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2254 | return ret; |
3cf17fc5 DV |
2255 | } |
2256 | ||
f5a4c67d CW |
2257 | static int count_irq_waiters(struct drm_i915_private *i915) |
2258 | { | |
e2f80391 | 2259 | struct intel_engine_cs *engine; |
3b3f1650 | 2260 | enum intel_engine_id id; |
f5a4c67d | 2261 | int count = 0; |
f5a4c67d | 2262 | |
3b3f1650 | 2263 | for_each_engine(engine, i915, id) |
688e6c72 | 2264 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2265 | |
2266 | return count; | |
2267 | } | |
2268 | ||
7466c291 CW |
2269 | static const char *rps_power_to_str(unsigned int power) |
2270 | { | |
2271 | static const char * const strings[] = { | |
2272 | [LOW_POWER] = "low power", | |
2273 | [BETWEEN] = "mixed", | |
2274 | [HIGH_POWER] = "high power", | |
2275 | }; | |
2276 | ||
2277 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2278 | return "unknown"; | |
2279 | ||
2280 | return strings[power]; | |
2281 | } | |
2282 | ||
1854d5ca CW |
2283 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2284 | { | |
36cdd013 DW |
2285 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2286 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2287 | struct drm_file *file; |
1854d5ca | 2288 | |
f5a4c67d | 2289 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2290 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2291 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2292 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2293 | seq_printf(m, "Frequency requested %d\n", |
2294 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2295 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2296 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2297 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2298 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2299 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2300 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2301 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2302 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2303 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2304 | |
2305 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2306 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2307 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2308 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2309 | struct task_struct *task; | |
2310 | ||
2311 | rcu_read_lock(); | |
2312 | task = pid_task(file->pid, PIDTYPE_PID); | |
2313 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2314 | task ? task->comm : "<unknown>", | |
2315 | task ? task->pid : -1, | |
2e1b8730 CW |
2316 | file_priv->rps.boosts, |
2317 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2318 | rcu_read_unlock(); |
2319 | } | |
197be2ae | 2320 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2321 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2322 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2323 | |
7466c291 CW |
2324 | if (INTEL_GEN(dev_priv) >= 6 && |
2325 | dev_priv->rps.enabled && | |
28176ef4 | 2326 | dev_priv->gt.active_requests) { |
7466c291 CW |
2327 | u32 rpup, rpupei; |
2328 | u32 rpdown, rpdownei; | |
2329 | ||
2330 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2331 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2332 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2333 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2334 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2335 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2336 | ||
2337 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2338 | rps_power_to_str(dev_priv->rps.power)); | |
2339 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2340 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2341 | dev_priv->rps.up_threshold); |
2342 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2343 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2344 | dev_priv->rps.down_threshold); |
2345 | } else { | |
2346 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2347 | } | |
2348 | ||
8d3afd7d | 2349 | return 0; |
1854d5ca CW |
2350 | } |
2351 | ||
63573eb7 BW |
2352 | static int i915_llc(struct seq_file *m, void *data) |
2353 | { | |
36cdd013 | 2354 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2355 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2356 | |
36cdd013 | 2357 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2358 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2359 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2360 | |
2361 | return 0; | |
2362 | } | |
2363 | ||
0509ead1 AS |
2364 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2365 | { | |
2366 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2367 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2368 | ||
2369 | if (!HAS_HUC_UCODE(dev_priv)) | |
2370 | return 0; | |
2371 | ||
2372 | seq_puts(m, "HuC firmware status:\n"); | |
2373 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2374 | seq_printf(m, "\tfetch: %s\n", | |
2375 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2376 | seq_printf(m, "\tload: %s\n", | |
2377 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2378 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2379 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2380 | seq_printf(m, "\tversion found: %d.%d\n", | |
2381 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2382 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2383 | huc_fw->header_offset, huc_fw->header_size); | |
2384 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2385 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2386 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2387 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2388 | ||
3582ad13 | 2389 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2390 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2391 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2392 | |
2393 | return 0; | |
2394 | } | |
2395 | ||
fdf5d357 AD |
2396 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2397 | { | |
36cdd013 | 2398 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2399 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2400 | u32 tmp, i; |
2401 | ||
2d1fe073 | 2402 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2403 | return 0; |
2404 | ||
2405 | seq_printf(m, "GuC firmware status:\n"); | |
2406 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2407 | guc_fw->path); |
fdf5d357 | 2408 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2409 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2410 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2411 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2412 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2413 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2414 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2415 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2416 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2417 | guc_fw->header_offset, guc_fw->header_size); | |
2418 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2419 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2420 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2421 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2422 | |
3582ad13 | 2423 | intel_runtime_pm_get(dev_priv); |
2424 | ||
fdf5d357 AD |
2425 | tmp = I915_READ(GUC_STATUS); |
2426 | ||
2427 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2428 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2429 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2430 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2431 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2432 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2433 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2434 | seq_puts(m, "\nScratch registers:\n"); | |
2435 | for (i = 0; i < 16; i++) | |
2436 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2437 | ||
3582ad13 | 2438 | intel_runtime_pm_put(dev_priv); |
2439 | ||
fdf5d357 AD |
2440 | return 0; |
2441 | } | |
2442 | ||
5aa1ee4b AG |
2443 | static void i915_guc_log_info(struct seq_file *m, |
2444 | struct drm_i915_private *dev_priv) | |
2445 | { | |
2446 | struct intel_guc *guc = &dev_priv->guc; | |
2447 | ||
2448 | seq_puts(m, "\nGuC logging stats:\n"); | |
2449 | ||
2450 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2451 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2452 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2453 | ||
2454 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2455 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2456 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2457 | ||
2458 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2459 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2460 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2461 | ||
2462 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2463 | guc->log.flush_interrupt_count); | |
2464 | ||
2465 | seq_printf(m, "\tCapture miss count: %u\n", | |
2466 | guc->log.capture_miss_count); | |
2467 | } | |
2468 | ||
8b417c26 DG |
2469 | static void i915_guc_client_info(struct seq_file *m, |
2470 | struct drm_i915_private *dev_priv, | |
2471 | struct i915_guc_client *client) | |
2472 | { | |
e2f80391 | 2473 | struct intel_engine_cs *engine; |
c18468c4 | 2474 | enum intel_engine_id id; |
8b417c26 | 2475 | uint64_t tot = 0; |
8b417c26 | 2476 | |
b09935a6 OM |
2477 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2478 | client->priority, client->stage_id, client->proc_desc_offset); | |
abddffdf | 2479 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n", |
357248bf | 2480 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2481 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2482 | client->wq_size, client->wq_offset, client->wq_tail); | |
2483 | ||
551aaecd | 2484 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2485 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2486 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2487 | ||
3b3f1650 | 2488 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2489 | u64 submissions = client->submissions[id]; |
2490 | tot += submissions; | |
8b417c26 | 2491 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2492 | submissions, engine->name); |
8b417c26 DG |
2493 | } |
2494 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2495 | } | |
2496 | ||
2497 | static int i915_guc_info(struct seq_file *m, void *data) | |
2498 | { | |
36cdd013 | 2499 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2500 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2501 | struct intel_engine_cs *engine; |
c18468c4 | 2502 | enum intel_engine_id id; |
334636c6 | 2503 | u64 total; |
8b417c26 | 2504 | |
334636c6 CW |
2505 | if (!guc->execbuf_client) { |
2506 | seq_printf(m, "GuC submission %s\n", | |
2507 | HAS_GUC_SCHED(dev_priv) ? | |
2508 | "disabled" : | |
2509 | "not supported"); | |
5a843307 | 2510 | return 0; |
334636c6 | 2511 | } |
8b417c26 | 2512 | |
9636f6db | 2513 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2514 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2515 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2516 | |
334636c6 CW |
2517 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2518 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2519 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2520 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2521 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2522 | |
334636c6 | 2523 | total = 0; |
8b417c26 | 2524 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2525 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2526 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2527 | total += submissions; |
397097b0 | 2528 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2529 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2530 | } |
2531 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2532 | ||
334636c6 CW |
2533 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2534 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2535 | |
5aa1ee4b AG |
2536 | i915_guc_log_info(m, dev_priv); |
2537 | ||
8b417c26 DG |
2538 | /* Add more as required ... */ |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
4c7e77fc AD |
2543 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2544 | { | |
36cdd013 | 2545 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2546 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2547 | int i = 0, pg; |
2548 | ||
d6b40b4b | 2549 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2550 | return 0; |
2551 | ||
d6b40b4b | 2552 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2553 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2554 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2555 | |
2556 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2557 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2558 | *(log + i), *(log + i + 1), | |
2559 | *(log + i + 2), *(log + i + 3)); | |
2560 | ||
2561 | kunmap_atomic(log); | |
2562 | } | |
2563 | ||
2564 | seq_putc(m, '\n'); | |
2565 | ||
2566 | return 0; | |
2567 | } | |
2568 | ||
685534ef SAK |
2569 | static int i915_guc_log_control_get(void *data, u64 *val) |
2570 | { | |
bcc36d8a | 2571 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2572 | |
2573 | if (!dev_priv->guc.log.vma) | |
2574 | return -EINVAL; | |
2575 | ||
2576 | *val = i915.guc_log_level; | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
2581 | static int i915_guc_log_control_set(void *data, u64 val) | |
2582 | { | |
bcc36d8a | 2583 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2584 | int ret; |
2585 | ||
2586 | if (!dev_priv->guc.log.vma) | |
2587 | return -EINVAL; | |
2588 | ||
bcc36d8a | 2589 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2590 | if (ret) |
2591 | return ret; | |
2592 | ||
2593 | intel_runtime_pm_get(dev_priv); | |
2594 | ret = i915_guc_log_control(dev_priv, val); | |
2595 | intel_runtime_pm_put(dev_priv); | |
2596 | ||
bcc36d8a | 2597 | mutex_unlock(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2598 | return ret; |
2599 | } | |
2600 | ||
2601 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2602 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2603 | "%lld\n"); | |
2604 | ||
b86bef20 CW |
2605 | static const char *psr2_live_status(u32 val) |
2606 | { | |
2607 | static const char * const live_status[] = { | |
2608 | "IDLE", | |
2609 | "CAPTURE", | |
2610 | "CAPTURE_FS", | |
2611 | "SLEEP", | |
2612 | "BUFON_FW", | |
2613 | "ML_UP", | |
2614 | "SU_STANDBY", | |
2615 | "FAST_SLEEP", | |
2616 | "DEEP_SLEEP", | |
2617 | "BUF_ON", | |
2618 | "TG_ON" | |
2619 | }; | |
2620 | ||
2621 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2622 | if (val < ARRAY_SIZE(live_status)) | |
2623 | return live_status[val]; | |
2624 | ||
2625 | return "unknown"; | |
2626 | } | |
2627 | ||
e91fd8c6 RV |
2628 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2629 | { | |
36cdd013 | 2630 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2631 | u32 psrperf = 0; |
a6cbdb8e RV |
2632 | u32 stat[3]; |
2633 | enum pipe pipe; | |
a031d709 | 2634 | bool enabled = false; |
e91fd8c6 | 2635 | |
36cdd013 | 2636 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2637 | seq_puts(m, "PSR not supported\n"); |
2638 | return 0; | |
2639 | } | |
2640 | ||
c8c8fb33 PZ |
2641 | intel_runtime_pm_get(dev_priv); |
2642 | ||
fa128fa6 | 2643 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2644 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2645 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2646 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2647 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2648 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2649 | dev_priv->psr.busy_frontbuffer_bits); | |
2650 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2651 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2652 | |
7e3eb599 NV |
2653 | if (HAS_DDI(dev_priv)) { |
2654 | if (dev_priv->psr.psr2_support) | |
2655 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2656 | else | |
2657 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2658 | } else { | |
3553a8ea | 2659 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2660 | enum transcoder cpu_transcoder = |
2661 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2662 | enum intel_display_power_domain power_domain; | |
2663 | ||
2664 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2665 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2666 | power_domain)) | |
2667 | continue; | |
2668 | ||
3553a8ea DL |
2669 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2670 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2671 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2672 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2673 | enabled = true; | |
9c870d03 CW |
2674 | |
2675 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2676 | } |
2677 | } | |
60e5ffe3 RV |
2678 | |
2679 | seq_printf(m, "Main link in standby mode: %s\n", | |
2680 | yesno(dev_priv->psr.link_standby)); | |
2681 | ||
a6cbdb8e RV |
2682 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2683 | ||
36cdd013 | 2684 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2685 | for_each_pipe(dev_priv, pipe) { |
2686 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2687 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2688 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2689 | } | |
2690 | seq_puts(m, "\n"); | |
e91fd8c6 | 2691 | |
05eec3c2 RV |
2692 | /* |
2693 | * VLV/CHV PSR has no kind of performance counter | |
2694 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2695 | */ | |
36cdd013 | 2696 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2697 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2698 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2699 | |
2700 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2701 | } | |
6ba1f9e1 | 2702 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2703 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2704 | ||
2705 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2706 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2707 | } |
fa128fa6 | 2708 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2709 | |
c8c8fb33 | 2710 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2711 | return 0; |
2712 | } | |
2713 | ||
d2e216d0 RV |
2714 | static int i915_sink_crc(struct seq_file *m, void *data) |
2715 | { | |
36cdd013 DW |
2716 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2717 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2718 | struct intel_connector *connector; |
3f6a5e1e | 2719 | struct drm_connector_list_iter conn_iter; |
d2e216d0 RV |
2720 | struct intel_dp *intel_dp = NULL; |
2721 | int ret; | |
2722 | u8 crc[6]; | |
2723 | ||
2724 | drm_modeset_lock_all(dev); | |
3f6a5e1e DV |
2725 | drm_connector_list_iter_begin(dev, &conn_iter); |
2726 | for_each_intel_connector_iter(connector, &conn_iter) { | |
26c17cf6 | 2727 | struct drm_crtc *crtc; |
d2e216d0 | 2728 | |
26c17cf6 | 2729 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2730 | continue; |
2731 | ||
26c17cf6 ML |
2732 | crtc = connector->base.state->crtc; |
2733 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2734 | continue; |
2735 | ||
26c17cf6 | 2736 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2737 | continue; |
2738 | ||
26c17cf6 | 2739 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2740 | |
2741 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2742 | if (ret) | |
2743 | goto out; | |
2744 | ||
2745 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2746 | crc[0], crc[1], crc[2], | |
2747 | crc[3], crc[4], crc[5]); | |
2748 | goto out; | |
2749 | } | |
2750 | ret = -ENODEV; | |
2751 | out: | |
3f6a5e1e | 2752 | drm_connector_list_iter_end(&conn_iter); |
d2e216d0 RV |
2753 | drm_modeset_unlock_all(dev); |
2754 | return ret; | |
2755 | } | |
2756 | ||
ec013e7f JB |
2757 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2758 | { | |
36cdd013 | 2759 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2760 | u64 power; |
2761 | u32 units; | |
2762 | ||
36cdd013 | 2763 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2764 | return -ENODEV; |
2765 | ||
36623ef8 PZ |
2766 | intel_runtime_pm_get(dev_priv); |
2767 | ||
ec013e7f JB |
2768 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2769 | power = (power & 0x1f00) >> 8; | |
2770 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2771 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2772 | power *= units; | |
2773 | ||
36623ef8 PZ |
2774 | intel_runtime_pm_put(dev_priv); |
2775 | ||
ec013e7f | 2776 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2777 | |
2778 | return 0; | |
2779 | } | |
2780 | ||
6455c870 | 2781 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2782 | { |
36cdd013 | 2783 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2784 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2785 | |
a156e64d CW |
2786 | if (!HAS_RUNTIME_PM(dev_priv)) |
2787 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2788 | |
67d97da3 | 2789 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2790 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2791 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2792 | #ifdef CONFIG_PM |
a6aaec8b | 2793 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2794 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2795 | #else |
2796 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2797 | #endif | |
a156e64d | 2798 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2799 | pci_power_name(pdev->current_state), |
2800 | pdev->current_state); | |
371db66a | 2801 | |
ec013e7f JB |
2802 | return 0; |
2803 | } | |
2804 | ||
1da51581 ID |
2805 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2806 | { | |
36cdd013 | 2807 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2808 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2809 | int i; | |
2810 | ||
2811 | mutex_lock(&power_domains->lock); | |
2812 | ||
2813 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2814 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2815 | struct i915_power_well *power_well; | |
2816 | enum intel_display_power_domain power_domain; | |
2817 | ||
2818 | power_well = &power_domains->power_wells[i]; | |
2819 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2820 | power_well->count); | |
2821 | ||
8385c2ec | 2822 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2823 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2824 | intel_display_power_domain_str(power_domain), |
1da51581 | 2825 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2826 | } |
2827 | ||
2828 | mutex_unlock(&power_domains->lock); | |
2829 | ||
2830 | return 0; | |
2831 | } | |
2832 | ||
b7cec66d DL |
2833 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2834 | { | |
36cdd013 | 2835 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2836 | struct intel_csr *csr; |
2837 | ||
36cdd013 | 2838 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2839 | seq_puts(m, "not supported\n"); |
2840 | return 0; | |
2841 | } | |
2842 | ||
2843 | csr = &dev_priv->csr; | |
2844 | ||
6fb403de MK |
2845 | intel_runtime_pm_get(dev_priv); |
2846 | ||
b7cec66d DL |
2847 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2848 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2849 | ||
2850 | if (!csr->dmc_payload) | |
6fb403de | 2851 | goto out; |
b7cec66d DL |
2852 | |
2853 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2854 | CSR_VERSION_MINOR(csr->version)); | |
2855 | ||
36cdd013 | 2856 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2857 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2858 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2859 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2860 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2861 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2862 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2863 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2864 | } |
2865 | ||
6fb403de MK |
2866 | out: |
2867 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2868 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2869 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2870 | ||
8337206d DL |
2871 | intel_runtime_pm_put(dev_priv); |
2872 | ||
b7cec66d DL |
2873 | return 0; |
2874 | } | |
2875 | ||
53f5e3ca JB |
2876 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2877 | struct drm_display_mode *mode) | |
2878 | { | |
2879 | int i; | |
2880 | ||
2881 | for (i = 0; i < tabs; i++) | |
2882 | seq_putc(m, '\t'); | |
2883 | ||
2884 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2885 | mode->base.id, mode->name, | |
2886 | mode->vrefresh, mode->clock, | |
2887 | mode->hdisplay, mode->hsync_start, | |
2888 | mode->hsync_end, mode->htotal, | |
2889 | mode->vdisplay, mode->vsync_start, | |
2890 | mode->vsync_end, mode->vtotal, | |
2891 | mode->type, mode->flags); | |
2892 | } | |
2893 | ||
2894 | static void intel_encoder_info(struct seq_file *m, | |
2895 | struct intel_crtc *intel_crtc, | |
2896 | struct intel_encoder *intel_encoder) | |
2897 | { | |
36cdd013 DW |
2898 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2899 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2900 | struct drm_crtc *crtc = &intel_crtc->base; |
2901 | struct intel_connector *intel_connector; | |
2902 | struct drm_encoder *encoder; | |
2903 | ||
2904 | encoder = &intel_encoder->base; | |
2905 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2906 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2907 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2908 | struct drm_connector *connector = &intel_connector->base; | |
2909 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2910 | connector->base.id, | |
c23cc417 | 2911 | connector->name, |
53f5e3ca JB |
2912 | drm_get_connector_status_name(connector->status)); |
2913 | if (connector->status == connector_status_connected) { | |
2914 | struct drm_display_mode *mode = &crtc->mode; | |
2915 | seq_printf(m, ", mode:\n"); | |
2916 | intel_seq_print_mode(m, 2, mode); | |
2917 | } else { | |
2918 | seq_putc(m, '\n'); | |
2919 | } | |
2920 | } | |
2921 | } | |
2922 | ||
2923 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2924 | { | |
36cdd013 DW |
2925 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2926 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2927 | struct drm_crtc *crtc = &intel_crtc->base; |
2928 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2929 | struct drm_plane_state *plane_state = crtc->primary->state; |
2930 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2931 | |
23a48d53 | 2932 | if (fb) |
5aa8a937 | 2933 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2934 | fb->base.id, plane_state->src_x >> 16, |
2935 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2936 | else |
2937 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2938 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2939 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2940 | } | |
2941 | ||
2942 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2943 | { | |
2944 | struct drm_display_mode *mode = panel->fixed_mode; | |
2945 | ||
2946 | seq_printf(m, "\tfixed mode:\n"); | |
2947 | intel_seq_print_mode(m, 2, mode); | |
2948 | } | |
2949 | ||
2950 | static void intel_dp_info(struct seq_file *m, | |
2951 | struct intel_connector *intel_connector) | |
2952 | { | |
2953 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2954 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2955 | ||
2956 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2957 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2958 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2959 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2960 | |
2961 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2962 | &intel_dp->aux); | |
53f5e3ca JB |
2963 | } |
2964 | ||
9a148a96 LY |
2965 | static void intel_dp_mst_info(struct seq_file *m, |
2966 | struct intel_connector *intel_connector) | |
2967 | { | |
2968 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2969 | struct intel_dp_mst_encoder *intel_mst = | |
2970 | enc_to_mst(&intel_encoder->base); | |
2971 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2972 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2973 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2974 | intel_connector->port); | |
2975 | ||
2976 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2977 | } | |
2978 | ||
53f5e3ca JB |
2979 | static void intel_hdmi_info(struct seq_file *m, |
2980 | struct intel_connector *intel_connector) | |
2981 | { | |
2982 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2983 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2984 | ||
742f491d | 2985 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2986 | } |
2987 | ||
2988 | static void intel_lvds_info(struct seq_file *m, | |
2989 | struct intel_connector *intel_connector) | |
2990 | { | |
2991 | intel_panel_info(m, &intel_connector->panel); | |
2992 | } | |
2993 | ||
2994 | static void intel_connector_info(struct seq_file *m, | |
2995 | struct drm_connector *connector) | |
2996 | { | |
2997 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2998 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2999 | struct drm_display_mode *mode; |
53f5e3ca JB |
3000 | |
3001 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3002 | connector->base.id, connector->name, |
53f5e3ca JB |
3003 | drm_get_connector_status_name(connector->status)); |
3004 | if (connector->status == connector_status_connected) { | |
3005 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3006 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3007 | connector->display_info.width_mm, | |
3008 | connector->display_info.height_mm); | |
3009 | seq_printf(m, "\tsubpixel order: %s\n", | |
3010 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3011 | seq_printf(m, "\tCEA rev: %d\n", | |
3012 | connector->display_info.cea_rev); | |
3013 | } | |
ee648a74 ML |
3014 | |
3015 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3016 | return; | |
3017 | ||
3018 | switch (connector->connector_type) { | |
3019 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3020 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3021 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3022 | intel_dp_mst_info(m, intel_connector); | |
3023 | else | |
3024 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3025 | break; |
3026 | case DRM_MODE_CONNECTOR_LVDS: | |
3027 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3028 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3029 | break; |
3030 | case DRM_MODE_CONNECTOR_HDMIA: | |
3031 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3032 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3033 | intel_hdmi_info(m, intel_connector); | |
3034 | break; | |
3035 | default: | |
3036 | break; | |
36cd7444 | 3037 | } |
53f5e3ca | 3038 | |
f103fc7d JB |
3039 | seq_printf(m, "\tmodes:\n"); |
3040 | list_for_each_entry(mode, &connector->modes, head) | |
3041 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3042 | } |
3043 | ||
36cdd013 | 3044 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 3045 | { |
065f2ec2 CW |
3046 | u32 state; |
3047 | ||
2a307c2e | 3048 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3049 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3050 | else |
5efb3e28 | 3051 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3052 | |
3053 | return state; | |
3054 | } | |
3055 | ||
36cdd013 DW |
3056 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3057 | int pipe, int *x, int *y) | |
065f2ec2 | 3058 | { |
065f2ec2 CW |
3059 | u32 pos; |
3060 | ||
5efb3e28 | 3061 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3062 | |
3063 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3064 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3065 | *x = -*x; | |
3066 | ||
3067 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3068 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3069 | *y = -*y; | |
3070 | ||
36cdd013 | 3071 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3072 | } |
3073 | ||
3abc4e09 RF |
3074 | static const char *plane_type(enum drm_plane_type type) |
3075 | { | |
3076 | switch (type) { | |
3077 | case DRM_PLANE_TYPE_OVERLAY: | |
3078 | return "OVL"; | |
3079 | case DRM_PLANE_TYPE_PRIMARY: | |
3080 | return "PRI"; | |
3081 | case DRM_PLANE_TYPE_CURSOR: | |
3082 | return "CUR"; | |
3083 | /* | |
3084 | * Deliberately omitting default: to generate compiler warnings | |
3085 | * when a new drm_plane_type gets added. | |
3086 | */ | |
3087 | } | |
3088 | ||
3089 | return "unknown"; | |
3090 | } | |
3091 | ||
3092 | static const char *plane_rotation(unsigned int rotation) | |
3093 | { | |
3094 | static char buf[48]; | |
3095 | /* | |
3096 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3097 | * will print them all to visualize if the values are misused | |
3098 | */ | |
3099 | snprintf(buf, sizeof(buf), | |
3100 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3101 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3102 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3103 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3104 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3105 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3106 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3107 | rotation); |
3108 | ||
3109 | return buf; | |
3110 | } | |
3111 | ||
3112 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3113 | { | |
36cdd013 DW |
3114 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3115 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3116 | struct intel_plane *intel_plane; |
3117 | ||
3118 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3119 | struct drm_plane_state *state; | |
3120 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3121 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3122 | |
3123 | if (!plane->state) { | |
3124 | seq_puts(m, "plane->state is NULL!\n"); | |
3125 | continue; | |
3126 | } | |
3127 | ||
3128 | state = plane->state; | |
3129 | ||
90844f00 | 3130 | if (state->fb) { |
438b74a5 VS |
3131 | drm_get_format_name(state->fb->format->format, |
3132 | &format_name); | |
90844f00 | 3133 | } else { |
b3c11ac2 | 3134 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3135 | } |
3136 | ||
3abc4e09 RF |
3137 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3138 | plane->base.id, | |
3139 | plane_type(intel_plane->base.type), | |
3140 | state->crtc_x, state->crtc_y, | |
3141 | state->crtc_w, state->crtc_h, | |
3142 | (state->src_x >> 16), | |
3143 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3144 | (state->src_y >> 16), | |
3145 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3146 | (state->src_w >> 16), | |
3147 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3148 | (state->src_h >> 16), | |
3149 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3150 | format_name.str, |
3abc4e09 RF |
3151 | plane_rotation(state->rotation)); |
3152 | } | |
3153 | } | |
3154 | ||
3155 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3156 | { | |
3157 | struct intel_crtc_state *pipe_config; | |
3158 | int num_scalers = intel_crtc->num_scalers; | |
3159 | int i; | |
3160 | ||
3161 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3162 | ||
3163 | /* Not all platformas have a scaler */ | |
3164 | if (num_scalers) { | |
3165 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3166 | num_scalers, | |
3167 | pipe_config->scaler_state.scaler_users, | |
3168 | pipe_config->scaler_state.scaler_id); | |
3169 | ||
58415918 | 3170 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3171 | struct intel_scaler *sc = |
3172 | &pipe_config->scaler_state.scalers[i]; | |
3173 | ||
3174 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3175 | i, yesno(sc->in_use), sc->mode); | |
3176 | } | |
3177 | seq_puts(m, "\n"); | |
3178 | } else { | |
3179 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3180 | } | |
3181 | } | |
3182 | ||
53f5e3ca JB |
3183 | static int i915_display_info(struct seq_file *m, void *unused) |
3184 | { | |
36cdd013 DW |
3185 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3186 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3187 | struct intel_crtc *crtc; |
53f5e3ca | 3188 | struct drm_connector *connector; |
3f6a5e1e | 3189 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3190 | |
b0e5ddf3 | 3191 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3192 | seq_printf(m, "CRTC info\n"); |
3193 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3194 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3195 | bool active; |
f77076c9 | 3196 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3197 | int x, y; |
53f5e3ca | 3198 | |
3f6a5e1e | 3199 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3200 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3201 | ||
3abc4e09 | 3202 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3203 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3204 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3205 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3206 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3207 | ||
f77076c9 | 3208 | if (pipe_config->base.active) { |
065f2ec2 CW |
3209 | intel_crtc_info(m, crtc); |
3210 | ||
36cdd013 | 3211 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3212 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3213 | yesno(crtc->cursor_base), |
3dd512fb MR |
3214 | x, y, crtc->base.cursor->state->crtc_w, |
3215 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3216 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3217 | intel_scaler_info(m, crtc); |
3218 | intel_plane_info(m, crtc); | |
a23dc658 | 3219 | } |
cace841c DV |
3220 | |
3221 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3222 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3223 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3224 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3225 | } |
3226 | ||
3227 | seq_printf(m, "\n"); | |
3228 | seq_printf(m, "Connector info\n"); | |
3229 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3230 | mutex_lock(&dev->mode_config.mutex); |
3231 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3232 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3233 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3234 | drm_connector_list_iter_end(&conn_iter); |
3235 | mutex_unlock(&dev->mode_config.mutex); | |
3236 | ||
b0e5ddf3 | 3237 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3238 | |
3239 | return 0; | |
3240 | } | |
3241 | ||
1b36595f CW |
3242 | static int i915_engine_info(struct seq_file *m, void *unused) |
3243 | { | |
3244 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3245 | struct intel_engine_cs *engine; | |
3b3f1650 | 3246 | enum intel_engine_id id; |
1b36595f | 3247 | |
9c870d03 CW |
3248 | intel_runtime_pm_get(dev_priv); |
3249 | ||
f73b5674 CW |
3250 | seq_printf(m, "GT awake? %s\n", |
3251 | yesno(dev_priv->gt.awake)); | |
3252 | seq_printf(m, "Global active requests: %d\n", | |
3253 | dev_priv->gt.active_requests); | |
3254 | ||
3b3f1650 | 3255 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3256 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3257 | struct drm_i915_gem_request *rq; | |
3258 | struct rb_node *rb; | |
3259 | u64 addr; | |
3260 | ||
3261 | seq_printf(m, "%s\n", engine->name); | |
f73b5674 | 3262 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", |
1b36595f | 3263 | intel_engine_get_seqno(engine), |
cb399eab | 3264 | intel_engine_last_submit(engine), |
1b36595f | 3265 | engine->hangcheck.seqno, |
f73b5674 CW |
3266 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), |
3267 | engine->timeline->inflight_seqnos); | |
1b36595f CW |
3268 | |
3269 | rcu_read_lock(); | |
3270 | ||
3271 | seq_printf(m, "\tRequests:\n"); | |
3272 | ||
73cb9701 CW |
3273 | rq = list_first_entry(&engine->timeline->requests, |
3274 | struct drm_i915_gem_request, link); | |
3275 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3276 | print_request(m, rq, "\t\tfirst "); |
3277 | ||
73cb9701 CW |
3278 | rq = list_last_entry(&engine->timeline->requests, |
3279 | struct drm_i915_gem_request, link); | |
3280 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3281 | print_request(m, rq, "\t\tlast "); |
3282 | ||
3283 | rq = i915_gem_find_active_request(engine); | |
3284 | if (rq) { | |
3285 | print_request(m, rq, "\t\tactive "); | |
3286 | seq_printf(m, | |
3287 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3288 | rq->head, rq->postfix, rq->tail, | |
3289 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3290 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3291 | } | |
3292 | ||
3293 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3294 | I915_READ(RING_START(engine->mmio_base)), | |
3295 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3296 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3297 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3298 | rq ? rq->ring->head : 0); | |
3299 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3300 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3301 | rq ? rq->ring->tail : 0); | |
3302 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3303 | I915_READ(RING_CTL(engine->mmio_base)), | |
3304 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3305 | ||
3306 | rcu_read_unlock(); | |
3307 | ||
3308 | addr = intel_engine_get_active_head(engine); | |
3309 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3310 | upper_32_bits(addr), lower_32_bits(addr)); | |
3311 | addr = intel_engine_get_last_batch_head(engine); | |
3312 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3313 | upper_32_bits(addr), lower_32_bits(addr)); | |
3314 | ||
3315 | if (i915.enable_execlists) { | |
3316 | u32 ptr, read, write; | |
20311bd3 | 3317 | struct rb_node *rb; |
1b36595f CW |
3318 | |
3319 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3320 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3321 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3322 | ||
3323 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3324 | read = GEN8_CSB_READ_PTR(ptr); | |
3325 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3326 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3327 | read, write); | |
3328 | if (read >= GEN8_CSB_ENTRIES) | |
3329 | read = 0; | |
3330 | if (write >= GEN8_CSB_ENTRIES) | |
3331 | write = 0; | |
3332 | if (read > write) | |
3333 | write += GEN8_CSB_ENTRIES; | |
3334 | while (read < write) { | |
3335 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3336 | ||
3337 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3338 | idx, | |
3339 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3340 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3341 | } | |
3342 | ||
3343 | rcu_read_lock(); | |
3344 | rq = READ_ONCE(engine->execlist_port[0].request); | |
816ee798 CW |
3345 | if (rq) { |
3346 | seq_printf(m, "\t\tELSP[0] count=%d, ", | |
3347 | engine->execlist_port[0].count); | |
3348 | print_request(m, rq, "rq: "); | |
3349 | } else { | |
1b36595f | 3350 | seq_printf(m, "\t\tELSP[0] idle\n"); |
816ee798 | 3351 | } |
1b36595f | 3352 | rq = READ_ONCE(engine->execlist_port[1].request); |
816ee798 CW |
3353 | if (rq) { |
3354 | seq_printf(m, "\t\tELSP[1] count=%d, ", | |
3355 | engine->execlist_port[1].count); | |
3356 | print_request(m, rq, "rq: "); | |
3357 | } else { | |
1b36595f | 3358 | seq_printf(m, "\t\tELSP[1] idle\n"); |
816ee798 | 3359 | } |
1b36595f | 3360 | rcu_read_unlock(); |
c8247c06 | 3361 | |
663f71e7 | 3362 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3363 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3364 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3365 | print_request(m, rq, "\t\tQ "); |
3366 | } | |
663f71e7 | 3367 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3368 | } else if (INTEL_GEN(dev_priv) > 6) { |
3369 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3370 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3371 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3372 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3373 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3374 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3375 | } | |
3376 | ||
61d3dc70 | 3377 | spin_lock_irq(&b->rb_lock); |
1b36595f | 3378 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3379 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3380 | |
3381 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3382 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3383 | } | |
61d3dc70 | 3384 | spin_unlock_irq(&b->rb_lock); |
1b36595f CW |
3385 | |
3386 | seq_puts(m, "\n"); | |
3387 | } | |
3388 | ||
9c870d03 CW |
3389 | intel_runtime_pm_put(dev_priv); |
3390 | ||
1b36595f CW |
3391 | return 0; |
3392 | } | |
3393 | ||
e04934cf BW |
3394 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3395 | { | |
36cdd013 DW |
3396 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3397 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3398 | struct intel_engine_cs *engine; |
36cdd013 | 3399 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3400 | enum intel_engine_id id; |
3401 | int j, ret; | |
e04934cf | 3402 | |
39df9190 | 3403 | if (!i915.semaphores) { |
e04934cf BW |
3404 | seq_puts(m, "Semaphores are disabled\n"); |
3405 | return 0; | |
3406 | } | |
3407 | ||
3408 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3409 | if (ret) | |
3410 | return ret; | |
03872064 | 3411 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3412 | |
36cdd013 | 3413 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3414 | struct page *page; |
3415 | uint64_t *seqno; | |
3416 | ||
51d545d0 | 3417 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3418 | |
3419 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3420 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3421 | uint64_t offset; |
3422 | ||
e2f80391 | 3423 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3424 | |
3425 | seq_puts(m, " Last signal:"); | |
3426 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3427 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3428 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3429 | seqno[offset], offset * 8); | |
3430 | } | |
3431 | seq_putc(m, '\n'); | |
3432 | ||
3433 | seq_puts(m, " Last wait: "); | |
3434 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3435 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3436 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3437 | seqno[offset], offset * 8); | |
3438 | } | |
3439 | seq_putc(m, '\n'); | |
3440 | ||
3441 | } | |
3442 | kunmap_atomic(seqno); | |
3443 | } else { | |
3444 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3445 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3446 | for (j = 0; j < num_rings; j++) |
3447 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3448 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3449 | seq_putc(m, '\n'); |
3450 | } | |
3451 | ||
03872064 | 3452 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3453 | mutex_unlock(&dev->struct_mutex); |
3454 | return 0; | |
3455 | } | |
3456 | ||
728e29d7 DV |
3457 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3458 | { | |
36cdd013 DW |
3459 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3460 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3461 | int i; |
3462 | ||
3463 | drm_modeset_lock_all(dev); | |
3464 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3465 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3466 | ||
3467 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3468 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3469 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3470 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3471 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3472 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3473 | pll->state.hw_state.dpll_md); |
3474 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3475 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3476 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3477 | } |
3478 | drm_modeset_unlock_all(dev); | |
3479 | ||
3480 | return 0; | |
3481 | } | |
3482 | ||
1ed1ef9d | 3483 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3484 | { |
3485 | int i; | |
3486 | int ret; | |
e2f80391 | 3487 | struct intel_engine_cs *engine; |
36cdd013 DW |
3488 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3489 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3490 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3491 | enum intel_engine_id id; |
888b5995 | 3492 | |
888b5995 AS |
3493 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3494 | if (ret) | |
3495 | return ret; | |
3496 | ||
3497 | intel_runtime_pm_get(dev_priv); | |
3498 | ||
33136b06 | 3499 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3500 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3501 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3502 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3503 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3504 | i915_reg_t addr; |
3505 | u32 mask, value, read; | |
2fa60f6d | 3506 | bool ok; |
888b5995 | 3507 | |
33136b06 AS |
3508 | addr = workarounds->reg[i].addr; |
3509 | mask = workarounds->reg[i].mask; | |
3510 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3511 | read = I915_READ(addr); |
3512 | ok = (value & mask) == (read & mask); | |
3513 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3514 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3515 | } |
3516 | ||
3517 | intel_runtime_pm_put(dev_priv); | |
3518 | mutex_unlock(&dev->struct_mutex); | |
3519 | ||
3520 | return 0; | |
3521 | } | |
3522 | ||
c5511e44 DL |
3523 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3524 | { | |
36cdd013 DW |
3525 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3526 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3527 | struct skl_ddb_allocation *ddb; |
3528 | struct skl_ddb_entry *entry; | |
3529 | enum pipe pipe; | |
3530 | int plane; | |
3531 | ||
36cdd013 | 3532 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3533 | return 0; |
3534 | ||
c5511e44 DL |
3535 | drm_modeset_lock_all(dev); |
3536 | ||
3537 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3538 | ||
3539 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3540 | ||
3541 | for_each_pipe(dev_priv, pipe) { | |
3542 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3543 | ||
8b364b41 | 3544 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3545 | entry = &ddb->plane[pipe][plane]; |
3546 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3547 | entry->start, entry->end, | |
3548 | skl_ddb_entry_size(entry)); | |
3549 | } | |
3550 | ||
4969d33e | 3551 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3552 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3553 | entry->end, skl_ddb_entry_size(entry)); | |
3554 | } | |
3555 | ||
3556 | drm_modeset_unlock_all(dev); | |
3557 | ||
3558 | return 0; | |
3559 | } | |
3560 | ||
a54746e3 | 3561 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3562 | struct drm_device *dev, |
3563 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3564 | { |
fac5e23e | 3565 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3566 | struct i915_drrs *drrs = &dev_priv->drrs; |
3567 | int vrefresh = 0; | |
26875fe5 | 3568 | struct drm_connector *connector; |
3f6a5e1e | 3569 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3570 | |
3f6a5e1e DV |
3571 | drm_connector_list_iter_begin(dev, &conn_iter); |
3572 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3573 | if (connector->state->crtc != &intel_crtc->base) |
3574 | continue; | |
3575 | ||
3576 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3577 | } |
3f6a5e1e | 3578 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3579 | |
3580 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3581 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3582 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3583 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3584 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3585 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3586 | else | |
3587 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3588 | ||
3589 | seq_puts(m, "\n\n"); | |
3590 | ||
f77076c9 | 3591 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3592 | struct intel_panel *panel; |
3593 | ||
3594 | mutex_lock(&drrs->mutex); | |
3595 | /* DRRS Supported */ | |
3596 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3597 | ||
3598 | /* disable_drrs() will make drrs->dp NULL */ | |
3599 | if (!drrs->dp) { | |
3600 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3601 | mutex_unlock(&drrs->mutex); | |
3602 | return; | |
3603 | } | |
3604 | ||
3605 | panel = &drrs->dp->attached_connector->panel; | |
3606 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3607 | drrs->busy_frontbuffer_bits); | |
3608 | ||
3609 | seq_puts(m, "\n\t\t"); | |
3610 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3611 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3612 | vrefresh = panel->fixed_mode->vrefresh; | |
3613 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3614 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3615 | vrefresh = panel->downclock_mode->vrefresh; | |
3616 | } else { | |
3617 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3618 | drrs->refresh_rate_type); | |
3619 | mutex_unlock(&drrs->mutex); | |
3620 | return; | |
3621 | } | |
3622 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3623 | ||
3624 | seq_puts(m, "\n\t\t"); | |
3625 | mutex_unlock(&drrs->mutex); | |
3626 | } else { | |
3627 | /* DRRS not supported. Print the VBT parameter*/ | |
3628 | seq_puts(m, "\tDRRS Supported : No"); | |
3629 | } | |
3630 | seq_puts(m, "\n"); | |
3631 | } | |
3632 | ||
3633 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3634 | { | |
36cdd013 DW |
3635 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3636 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3637 | struct intel_crtc *intel_crtc; |
3638 | int active_crtc_cnt = 0; | |
3639 | ||
26875fe5 | 3640 | drm_modeset_lock_all(dev); |
a54746e3 | 3641 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3642 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3643 | active_crtc_cnt++; |
3644 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3645 | ||
3646 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3647 | } | |
a54746e3 | 3648 | } |
26875fe5 | 3649 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3650 | |
3651 | if (!active_crtc_cnt) | |
3652 | seq_puts(m, "No active crtc found\n"); | |
3653 | ||
3654 | return 0; | |
3655 | } | |
3656 | ||
11bed958 DA |
3657 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3658 | { | |
36cdd013 DW |
3659 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3660 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3661 | struct intel_encoder *intel_encoder; |
3662 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3663 | struct drm_connector *connector; |
3f6a5e1e | 3664 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3665 | |
3f6a5e1e DV |
3666 | drm_connector_list_iter_begin(dev, &conn_iter); |
3667 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3668 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3669 | continue; |
b6dabe3b ML |
3670 | |
3671 | intel_encoder = intel_attached_encoder(connector); | |
3672 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3673 | continue; | |
3674 | ||
3675 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3676 | if (!intel_dig_port->dp.can_mst) |
3677 | continue; | |
b6dabe3b | 3678 | |
40ae80cc JB |
3679 | seq_printf(m, "MST Source Port %c\n", |
3680 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3681 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3682 | } | |
3f6a5e1e DV |
3683 | drm_connector_list_iter_end(&conn_iter); |
3684 | ||
11bed958 DA |
3685 | return 0; |
3686 | } | |
3687 | ||
eb3394fa | 3688 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3689 | const char __user *ubuf, |
3690 | size_t len, loff_t *offp) | |
eb3394fa TP |
3691 | { |
3692 | char *input_buffer; | |
3693 | int status = 0; | |
eb3394fa TP |
3694 | struct drm_device *dev; |
3695 | struct drm_connector *connector; | |
3f6a5e1e | 3696 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3697 | struct intel_dp *intel_dp; |
3698 | int val = 0; | |
3699 | ||
9aaffa34 | 3700 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3701 | |
eb3394fa TP |
3702 | if (len == 0) |
3703 | return 0; | |
3704 | ||
261aeba8 GT |
3705 | input_buffer = memdup_user_nul(ubuf, len); |
3706 | if (IS_ERR(input_buffer)) | |
3707 | return PTR_ERR(input_buffer); | |
eb3394fa | 3708 | |
eb3394fa TP |
3709 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3710 | ||
3f6a5e1e DV |
3711 | drm_connector_list_iter_begin(dev, &conn_iter); |
3712 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3713 | if (connector->connector_type != |
3714 | DRM_MODE_CONNECTOR_DisplayPort) | |
3715 | continue; | |
3716 | ||
b8bb08ec | 3717 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3718 | connector->encoder != NULL) { |
3719 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3720 | status = kstrtoint(input_buffer, 10, &val); | |
3721 | if (status < 0) | |
3f6a5e1e | 3722 | break; |
eb3394fa TP |
3723 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3724 | /* To prevent erroneous activation of the compliance | |
3725 | * testing code, only accept an actual value of 1 here | |
3726 | */ | |
3727 | if (val == 1) | |
c1617abc | 3728 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3729 | else |
c1617abc | 3730 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3731 | } |
3732 | } | |
3f6a5e1e | 3733 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3734 | kfree(input_buffer); |
3735 | if (status < 0) | |
3736 | return status; | |
3737 | ||
3738 | *offp += len; | |
3739 | return len; | |
3740 | } | |
3741 | ||
3742 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3743 | { | |
3744 | struct drm_device *dev = m->private; | |
3745 | struct drm_connector *connector; | |
3f6a5e1e | 3746 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3747 | struct intel_dp *intel_dp; |
3748 | ||
3f6a5e1e DV |
3749 | drm_connector_list_iter_begin(dev, &conn_iter); |
3750 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3751 | if (connector->connector_type != |
3752 | DRM_MODE_CONNECTOR_DisplayPort) | |
3753 | continue; | |
3754 | ||
3755 | if (connector->status == connector_status_connected && | |
3756 | connector->encoder != NULL) { | |
3757 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3758 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3759 | seq_puts(m, "1"); |
3760 | else | |
3761 | seq_puts(m, "0"); | |
3762 | } else | |
3763 | seq_puts(m, "0"); | |
3764 | } | |
3f6a5e1e | 3765 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3766 | |
3767 | return 0; | |
3768 | } | |
3769 | ||
3770 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3771 | struct file *file) |
eb3394fa | 3772 | { |
36cdd013 | 3773 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3774 | |
36cdd013 DW |
3775 | return single_open(file, i915_displayport_test_active_show, |
3776 | &dev_priv->drm); | |
eb3394fa TP |
3777 | } |
3778 | ||
3779 | static const struct file_operations i915_displayport_test_active_fops = { | |
3780 | .owner = THIS_MODULE, | |
3781 | .open = i915_displayport_test_active_open, | |
3782 | .read = seq_read, | |
3783 | .llseek = seq_lseek, | |
3784 | .release = single_release, | |
3785 | .write = i915_displayport_test_active_write | |
3786 | }; | |
3787 | ||
3788 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3789 | { | |
3790 | struct drm_device *dev = m->private; | |
3791 | struct drm_connector *connector; | |
3f6a5e1e | 3792 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3793 | struct intel_dp *intel_dp; |
3794 | ||
3f6a5e1e DV |
3795 | drm_connector_list_iter_begin(dev, &conn_iter); |
3796 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3797 | if (connector->connector_type != |
3798 | DRM_MODE_CONNECTOR_DisplayPort) | |
3799 | continue; | |
3800 | ||
3801 | if (connector->status == connector_status_connected && | |
3802 | connector->encoder != NULL) { | |
3803 | intel_dp = enc_to_intel_dp(connector->encoder); | |
b48a5ba9 MN |
3804 | if (intel_dp->compliance.test_type == |
3805 | DP_TEST_LINK_EDID_READ) | |
3806 | seq_printf(m, "%lx", | |
3807 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3808 | else if (intel_dp->compliance.test_type == |
3809 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3810 | seq_printf(m, "hdisplay: %d\n", | |
3811 | intel_dp->compliance.test_data.hdisplay); | |
3812 | seq_printf(m, "vdisplay: %d\n", | |
3813 | intel_dp->compliance.test_data.vdisplay); | |
3814 | seq_printf(m, "bpc: %u\n", | |
3815 | intel_dp->compliance.test_data.bpc); | |
3816 | } | |
eb3394fa TP |
3817 | } else |
3818 | seq_puts(m, "0"); | |
3819 | } | |
3f6a5e1e | 3820 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3821 | |
3822 | return 0; | |
3823 | } | |
3824 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3825 | struct file *file) |
eb3394fa | 3826 | { |
36cdd013 | 3827 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3828 | |
36cdd013 DW |
3829 | return single_open(file, i915_displayport_test_data_show, |
3830 | &dev_priv->drm); | |
eb3394fa TP |
3831 | } |
3832 | ||
3833 | static const struct file_operations i915_displayport_test_data_fops = { | |
3834 | .owner = THIS_MODULE, | |
3835 | .open = i915_displayport_test_data_open, | |
3836 | .read = seq_read, | |
3837 | .llseek = seq_lseek, | |
3838 | .release = single_release | |
3839 | }; | |
3840 | ||
3841 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3842 | { | |
3843 | struct drm_device *dev = m->private; | |
3844 | struct drm_connector *connector; | |
3f6a5e1e | 3845 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3846 | struct intel_dp *intel_dp; |
3847 | ||
3f6a5e1e DV |
3848 | drm_connector_list_iter_begin(dev, &conn_iter); |
3849 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3850 | if (connector->connector_type != |
3851 | DRM_MODE_CONNECTOR_DisplayPort) | |
3852 | continue; | |
3853 | ||
3854 | if (connector->status == connector_status_connected && | |
3855 | connector->encoder != NULL) { | |
3856 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3857 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3858 | } else |
3859 | seq_puts(m, "0"); | |
3860 | } | |
3f6a5e1e | 3861 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3862 | |
3863 | return 0; | |
3864 | } | |
3865 | ||
3866 | static int i915_displayport_test_type_open(struct inode *inode, | |
3867 | struct file *file) | |
3868 | { | |
36cdd013 | 3869 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3870 | |
36cdd013 DW |
3871 | return single_open(file, i915_displayport_test_type_show, |
3872 | &dev_priv->drm); | |
eb3394fa TP |
3873 | } |
3874 | ||
3875 | static const struct file_operations i915_displayport_test_type_fops = { | |
3876 | .owner = THIS_MODULE, | |
3877 | .open = i915_displayport_test_type_open, | |
3878 | .read = seq_read, | |
3879 | .llseek = seq_lseek, | |
3880 | .release = single_release | |
3881 | }; | |
3882 | ||
97e94b22 | 3883 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3884 | { |
36cdd013 DW |
3885 | struct drm_i915_private *dev_priv = m->private; |
3886 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3887 | int level; |
de38b95c VS |
3888 | int num_levels; |
3889 | ||
36cdd013 | 3890 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3891 | num_levels = 3; |
36cdd013 | 3892 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3893 | num_levels = 1; |
3894 | else | |
5db94019 | 3895 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3896 | |
3897 | drm_modeset_lock_all(dev); | |
3898 | ||
3899 | for (level = 0; level < num_levels; level++) { | |
3900 | unsigned int latency = wm[level]; | |
3901 | ||
97e94b22 DL |
3902 | /* |
3903 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3904 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3905 | */ |
36cdd013 DW |
3906 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3907 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3908 | latency *= 10; |
3909 | else if (level > 0) | |
369a1342 VS |
3910 | latency *= 5; |
3911 | ||
3912 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3913 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3914 | } |
3915 | ||
3916 | drm_modeset_unlock_all(dev); | |
3917 | } | |
3918 | ||
3919 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3920 | { | |
36cdd013 | 3921 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3922 | const uint16_t *latencies; |
3923 | ||
36cdd013 | 3924 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3925 | latencies = dev_priv->wm.skl_latency; |
3926 | else | |
36cdd013 | 3927 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3928 | |
97e94b22 | 3929 | wm_latency_show(m, latencies); |
369a1342 VS |
3930 | |
3931 | return 0; | |
3932 | } | |
3933 | ||
3934 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3935 | { | |
36cdd013 | 3936 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3937 | const uint16_t *latencies; |
3938 | ||
36cdd013 | 3939 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3940 | latencies = dev_priv->wm.skl_latency; |
3941 | else | |
36cdd013 | 3942 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3943 | |
97e94b22 | 3944 | wm_latency_show(m, latencies); |
369a1342 VS |
3945 | |
3946 | return 0; | |
3947 | } | |
3948 | ||
3949 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3950 | { | |
36cdd013 | 3951 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3952 | const uint16_t *latencies; |
3953 | ||
36cdd013 | 3954 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3955 | latencies = dev_priv->wm.skl_latency; |
3956 | else | |
36cdd013 | 3957 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3958 | |
97e94b22 | 3959 | wm_latency_show(m, latencies); |
369a1342 VS |
3960 | |
3961 | return 0; | |
3962 | } | |
3963 | ||
3964 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3965 | { | |
36cdd013 | 3966 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3967 | |
36cdd013 | 3968 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3969 | return -ENODEV; |
3970 | ||
36cdd013 | 3971 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3972 | } |
3973 | ||
3974 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3975 | { | |
36cdd013 | 3976 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3977 | |
36cdd013 | 3978 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3979 | return -ENODEV; |
3980 | ||
36cdd013 | 3981 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3982 | } |
3983 | ||
3984 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3985 | { | |
36cdd013 | 3986 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3987 | |
36cdd013 | 3988 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3989 | return -ENODEV; |
3990 | ||
36cdd013 | 3991 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3992 | } |
3993 | ||
3994 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3995 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3996 | { |
3997 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3998 | struct drm_i915_private *dev_priv = m->private; |
3999 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4000 | uint16_t new[8] = { 0 }; |
de38b95c | 4001 | int num_levels; |
369a1342 VS |
4002 | int level; |
4003 | int ret; | |
4004 | char tmp[32]; | |
4005 | ||
36cdd013 | 4006 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4007 | num_levels = 3; |
36cdd013 | 4008 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4009 | num_levels = 1; |
4010 | else | |
5db94019 | 4011 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4012 | |
369a1342 VS |
4013 | if (len >= sizeof(tmp)) |
4014 | return -EINVAL; | |
4015 | ||
4016 | if (copy_from_user(tmp, ubuf, len)) | |
4017 | return -EFAULT; | |
4018 | ||
4019 | tmp[len] = '\0'; | |
4020 | ||
97e94b22 DL |
4021 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4022 | &new[0], &new[1], &new[2], &new[3], | |
4023 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4024 | if (ret != num_levels) |
4025 | return -EINVAL; | |
4026 | ||
4027 | drm_modeset_lock_all(dev); | |
4028 | ||
4029 | for (level = 0; level < num_levels; level++) | |
4030 | wm[level] = new[level]; | |
4031 | ||
4032 | drm_modeset_unlock_all(dev); | |
4033 | ||
4034 | return len; | |
4035 | } | |
4036 | ||
4037 | ||
4038 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4039 | size_t len, loff_t *offp) | |
4040 | { | |
4041 | struct seq_file *m = file->private_data; | |
36cdd013 | 4042 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4043 | uint16_t *latencies; |
369a1342 | 4044 | |
36cdd013 | 4045 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4046 | latencies = dev_priv->wm.skl_latency; |
4047 | else | |
36cdd013 | 4048 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4049 | |
4050 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4051 | } |
4052 | ||
4053 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4054 | size_t len, loff_t *offp) | |
4055 | { | |
4056 | struct seq_file *m = file->private_data; | |
36cdd013 | 4057 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4058 | uint16_t *latencies; |
369a1342 | 4059 | |
36cdd013 | 4060 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4061 | latencies = dev_priv->wm.skl_latency; |
4062 | else | |
36cdd013 | 4063 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4064 | |
4065 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4066 | } |
4067 | ||
4068 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4069 | size_t len, loff_t *offp) | |
4070 | { | |
4071 | struct seq_file *m = file->private_data; | |
36cdd013 | 4072 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4073 | uint16_t *latencies; |
4074 | ||
36cdd013 | 4075 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4076 | latencies = dev_priv->wm.skl_latency; |
4077 | else | |
36cdd013 | 4078 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4079 | |
97e94b22 | 4080 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4081 | } |
4082 | ||
4083 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4084 | .owner = THIS_MODULE, | |
4085 | .open = pri_wm_latency_open, | |
4086 | .read = seq_read, | |
4087 | .llseek = seq_lseek, | |
4088 | .release = single_release, | |
4089 | .write = pri_wm_latency_write | |
4090 | }; | |
4091 | ||
4092 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4093 | .owner = THIS_MODULE, | |
4094 | .open = spr_wm_latency_open, | |
4095 | .read = seq_read, | |
4096 | .llseek = seq_lseek, | |
4097 | .release = single_release, | |
4098 | .write = spr_wm_latency_write | |
4099 | }; | |
4100 | ||
4101 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4102 | .owner = THIS_MODULE, | |
4103 | .open = cur_wm_latency_open, | |
4104 | .read = seq_read, | |
4105 | .llseek = seq_lseek, | |
4106 | .release = single_release, | |
4107 | .write = cur_wm_latency_write | |
4108 | }; | |
4109 | ||
647416f9 KC |
4110 | static int |
4111 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4112 | { |
36cdd013 | 4113 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4114 | |
d98c52cf | 4115 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4116 | |
647416f9 | 4117 | return 0; |
f3cd474b CW |
4118 | } |
4119 | ||
647416f9 KC |
4120 | static int |
4121 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4122 | { |
598b6b5a CW |
4123 | struct drm_i915_private *i915 = data; |
4124 | struct intel_engine_cs *engine; | |
4125 | unsigned int tmp; | |
d46c0517 | 4126 | |
b8d24a06 MK |
4127 | /* |
4128 | * There is no safeguard against this debugfs entry colliding | |
4129 | * with the hangcheck calling same i915_handle_error() in | |
4130 | * parallel, causing an explosion. For now we assume that the | |
4131 | * test harness is responsible enough not to inject gpu hangs | |
4132 | * while it is writing to 'i915_wedged' | |
4133 | */ | |
4134 | ||
598b6b5a | 4135 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
4136 | return -EAGAIN; |
4137 | ||
598b6b5a CW |
4138 | for_each_engine_masked(engine, i915, val, tmp) { |
4139 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
4140 | engine->hangcheck.stalled = true; | |
4141 | } | |
4142 | ||
4143 | i915_handle_error(i915, val, "Manually setting wedged to %llu", val); | |
d46c0517 | 4144 | |
598b6b5a | 4145 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
4146 | I915_RESET_HANDOFF, |
4147 | TASK_UNINTERRUPTIBLE); | |
4148 | ||
647416f9 | 4149 | return 0; |
f3cd474b CW |
4150 | } |
4151 | ||
647416f9 KC |
4152 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4153 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4154 | "%llu\n"); |
f3cd474b | 4155 | |
64486ae7 CW |
4156 | static int |
4157 | fault_irq_set(struct drm_i915_private *i915, | |
4158 | unsigned long *irq, | |
4159 | unsigned long val) | |
4160 | { | |
4161 | int err; | |
4162 | ||
4163 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4164 | if (err) | |
4165 | return err; | |
4166 | ||
4167 | err = i915_gem_wait_for_idle(i915, | |
4168 | I915_WAIT_LOCKED | | |
4169 | I915_WAIT_INTERRUPTIBLE); | |
4170 | if (err) | |
4171 | goto err_unlock; | |
4172 | ||
64486ae7 CW |
4173 | *irq = val; |
4174 | mutex_unlock(&i915->drm.struct_mutex); | |
4175 | ||
4176 | /* Flush idle worker to disarm irq */ | |
4177 | while (flush_delayed_work(&i915->gt.idle_work)) | |
4178 | ; | |
4179 | ||
4180 | return 0; | |
4181 | ||
4182 | err_unlock: | |
4183 | mutex_unlock(&i915->drm.struct_mutex); | |
4184 | return err; | |
4185 | } | |
4186 | ||
094f9a54 CW |
4187 | static int |
4188 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4189 | { | |
36cdd013 | 4190 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4191 | |
4192 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4193 | return 0; | |
4194 | } | |
4195 | ||
4196 | static int | |
4197 | i915_ring_missed_irq_set(void *data, u64 val) | |
4198 | { | |
64486ae7 | 4199 | struct drm_i915_private *i915 = data; |
094f9a54 | 4200 | |
64486ae7 | 4201 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4202 | } |
4203 | ||
4204 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4205 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4206 | "0x%08llx\n"); | |
4207 | ||
4208 | static int | |
4209 | i915_ring_test_irq_get(void *data, u64 *val) | |
4210 | { | |
36cdd013 | 4211 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4212 | |
4213 | *val = dev_priv->gpu_error.test_irq_rings; | |
4214 | ||
4215 | return 0; | |
4216 | } | |
4217 | ||
4218 | static int | |
4219 | i915_ring_test_irq_set(void *data, u64 val) | |
4220 | { | |
64486ae7 | 4221 | struct drm_i915_private *i915 = data; |
094f9a54 | 4222 | |
64486ae7 | 4223 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4224 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4225 | |
64486ae7 | 4226 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4227 | } |
4228 | ||
4229 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4230 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4231 | "0x%08llx\n"); | |
4232 | ||
dd624afd CW |
4233 | #define DROP_UNBOUND 0x1 |
4234 | #define DROP_BOUND 0x2 | |
4235 | #define DROP_RETIRE 0x4 | |
4236 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 | 4237 | #define DROP_FREED 0x10 |
8eadc19b | 4238 | #define DROP_SHRINK_ALL 0x20 |
fbbd37b3 CW |
4239 | #define DROP_ALL (DROP_UNBOUND | \ |
4240 | DROP_BOUND | \ | |
4241 | DROP_RETIRE | \ | |
4242 | DROP_ACTIVE | \ | |
8eadc19b CW |
4243 | DROP_FREED | \ |
4244 | DROP_SHRINK_ALL) | |
647416f9 KC |
4245 | static int |
4246 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4247 | { |
647416f9 | 4248 | *val = DROP_ALL; |
dd624afd | 4249 | |
647416f9 | 4250 | return 0; |
dd624afd CW |
4251 | } |
4252 | ||
647416f9 KC |
4253 | static int |
4254 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4255 | { |
36cdd013 DW |
4256 | struct drm_i915_private *dev_priv = data; |
4257 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4258 | int ret; |
dd624afd | 4259 | |
2f9fe5ff | 4260 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4261 | |
4262 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4263 | * on ioctls on -EAGAIN. */ | |
4264 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4265 | if (ret) | |
4266 | return ret; | |
4267 | ||
4268 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4269 | ret = i915_gem_wait_for_idle(dev_priv, |
4270 | I915_WAIT_INTERRUPTIBLE | | |
4271 | I915_WAIT_LOCKED); | |
dd624afd CW |
4272 | if (ret) |
4273 | goto unlock; | |
4274 | } | |
4275 | ||
72022a70 | 4276 | if (val & DROP_RETIRE) |
c033666a | 4277 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4278 | |
05df49e7 | 4279 | lockdep_set_current_reclaim_state(GFP_KERNEL); |
21ab4e74 CW |
4280 | if (val & DROP_BOUND) |
4281 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4282 | |
21ab4e74 CW |
4283 | if (val & DROP_UNBOUND) |
4284 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd | 4285 | |
8eadc19b CW |
4286 | if (val & DROP_SHRINK_ALL) |
4287 | i915_gem_shrink_all(dev_priv); | |
05df49e7 | 4288 | lockdep_clear_current_reclaim_state(); |
8eadc19b | 4289 | |
dd624afd CW |
4290 | unlock: |
4291 | mutex_unlock(&dev->struct_mutex); | |
4292 | ||
fbbd37b3 CW |
4293 | if (val & DROP_FREED) { |
4294 | synchronize_rcu(); | |
bdeb9785 | 4295 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4296 | } |
4297 | ||
647416f9 | 4298 | return ret; |
dd624afd CW |
4299 | } |
4300 | ||
647416f9 KC |
4301 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4302 | i915_drop_caches_get, i915_drop_caches_set, | |
4303 | "0x%08llx\n"); | |
dd624afd | 4304 | |
647416f9 KC |
4305 | static int |
4306 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4307 | { |
36cdd013 | 4308 | struct drm_i915_private *dev_priv = data; |
004777cb | 4309 | |
36cdd013 | 4310 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4311 | return -ENODEV; |
4312 | ||
7c59a9c1 | 4313 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4314 | return 0; |
358733e9 JB |
4315 | } |
4316 | ||
647416f9 KC |
4317 | static int |
4318 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4319 | { |
36cdd013 | 4320 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4321 | u32 hw_max, hw_min; |
647416f9 | 4322 | int ret; |
004777cb | 4323 | |
36cdd013 | 4324 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4325 | return -ENODEV; |
358733e9 | 4326 | |
647416f9 | 4327 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4328 | |
4fc688ce | 4329 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4330 | if (ret) |
4331 | return ret; | |
4332 | ||
358733e9 JB |
4333 | /* |
4334 | * Turbo will still be enabled, but won't go above the set value. | |
4335 | */ | |
bc4d91f6 | 4336 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4337 | |
bc4d91f6 AG |
4338 | hw_max = dev_priv->rps.max_freq; |
4339 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4340 | |
b39fb297 | 4341 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4342 | mutex_unlock(&dev_priv->rps.hw_lock); |
4343 | return -EINVAL; | |
0a073b84 JB |
4344 | } |
4345 | ||
b39fb297 | 4346 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4347 | |
9fcee2f7 CW |
4348 | if (intel_set_rps(dev_priv, val)) |
4349 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4350 | |
4fc688ce | 4351 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4352 | |
647416f9 | 4353 | return 0; |
358733e9 JB |
4354 | } |
4355 | ||
647416f9 KC |
4356 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4357 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4358 | "%llu\n"); |
358733e9 | 4359 | |
647416f9 KC |
4360 | static int |
4361 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4362 | { |
36cdd013 | 4363 | struct drm_i915_private *dev_priv = data; |
004777cb | 4364 | |
62e1baa1 | 4365 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4366 | return -ENODEV; |
4367 | ||
7c59a9c1 | 4368 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4369 | return 0; |
1523c310 JB |
4370 | } |
4371 | ||
647416f9 KC |
4372 | static int |
4373 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4374 | { |
36cdd013 | 4375 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4376 | u32 hw_max, hw_min; |
647416f9 | 4377 | int ret; |
004777cb | 4378 | |
62e1baa1 | 4379 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4380 | return -ENODEV; |
1523c310 | 4381 | |
647416f9 | 4382 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4383 | |
4fc688ce | 4384 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4385 | if (ret) |
4386 | return ret; | |
4387 | ||
1523c310 JB |
4388 | /* |
4389 | * Turbo will still be enabled, but won't go below the set value. | |
4390 | */ | |
bc4d91f6 | 4391 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4392 | |
bc4d91f6 AG |
4393 | hw_max = dev_priv->rps.max_freq; |
4394 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4395 | |
36cdd013 DW |
4396 | if (val < hw_min || |
4397 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4398 | mutex_unlock(&dev_priv->rps.hw_lock); |
4399 | return -EINVAL; | |
0a073b84 | 4400 | } |
dd0a1aa1 | 4401 | |
b39fb297 | 4402 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4403 | |
9fcee2f7 CW |
4404 | if (intel_set_rps(dev_priv, val)) |
4405 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4406 | |
4fc688ce | 4407 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4408 | |
647416f9 | 4409 | return 0; |
1523c310 JB |
4410 | } |
4411 | ||
647416f9 KC |
4412 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4413 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4414 | "%llu\n"); |
1523c310 | 4415 | |
647416f9 KC |
4416 | static int |
4417 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4418 | { |
36cdd013 | 4419 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4420 | u32 snpcr; |
07b7ddd9 | 4421 | |
36cdd013 | 4422 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4423 | return -ENODEV; |
4424 | ||
c8c8fb33 | 4425 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4426 | |
07b7ddd9 | 4427 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4428 | |
4429 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4430 | |
647416f9 | 4431 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4432 | |
647416f9 | 4433 | return 0; |
07b7ddd9 JB |
4434 | } |
4435 | ||
647416f9 KC |
4436 | static int |
4437 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4438 | { |
36cdd013 | 4439 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4440 | u32 snpcr; |
07b7ddd9 | 4441 | |
36cdd013 | 4442 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4443 | return -ENODEV; |
4444 | ||
647416f9 | 4445 | if (val > 3) |
07b7ddd9 JB |
4446 | return -EINVAL; |
4447 | ||
c8c8fb33 | 4448 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4449 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4450 | |
4451 | /* Update the cache sharing policy here as well */ | |
4452 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4453 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4454 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4455 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4456 | ||
c8c8fb33 | 4457 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4458 | return 0; |
07b7ddd9 JB |
4459 | } |
4460 | ||
647416f9 KC |
4461 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4462 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4463 | "%llu\n"); | |
07b7ddd9 | 4464 | |
36cdd013 | 4465 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4466 | struct sseu_dev_info *sseu) |
5d39525a | 4467 | { |
0a0b457f | 4468 | int ss_max = 2; |
5d39525a JM |
4469 | int ss; |
4470 | u32 sig1[ss_max], sig2[ss_max]; | |
4471 | ||
4472 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4473 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4474 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4475 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4476 | ||
4477 | for (ss = 0; ss < ss_max; ss++) { | |
4478 | unsigned int eu_cnt; | |
4479 | ||
4480 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4481 | /* skip disabled subslice */ | |
4482 | continue; | |
4483 | ||
f08a0c92 | 4484 | sseu->slice_mask = BIT(0); |
57ec171e | 4485 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4486 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4487 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4488 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4489 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4490 | sseu->eu_total += eu_cnt; |
4491 | sseu->eu_per_subslice = max_t(unsigned int, | |
4492 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4493 | } |
5d39525a JM |
4494 | } |
4495 | ||
36cdd013 | 4496 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4497 | struct sseu_dev_info *sseu) |
5d39525a | 4498 | { |
1c046bc1 | 4499 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4500 | int s, ss; |
4501 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4502 | ||
1c046bc1 | 4503 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4504 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4505 | s_max = 1; |
4506 | ss_max = 3; | |
4507 | } | |
4508 | ||
4509 | for (s = 0; s < s_max; s++) { | |
4510 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4511 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4512 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4513 | } | |
4514 | ||
5d39525a JM |
4515 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4516 | GEN9_PGCTL_SSA_EU19_ACK | | |
4517 | GEN9_PGCTL_SSA_EU210_ACK | | |
4518 | GEN9_PGCTL_SSA_EU311_ACK; | |
4519 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4520 | GEN9_PGCTL_SSB_EU19_ACK | | |
4521 | GEN9_PGCTL_SSB_EU210_ACK | | |
4522 | GEN9_PGCTL_SSB_EU311_ACK; | |
4523 | ||
4524 | for (s = 0; s < s_max; s++) { | |
4525 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4526 | /* skip disabled slice */ | |
4527 | continue; | |
4528 | ||
f08a0c92 | 4529 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4530 | |
b976dc53 | 4531 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4532 | sseu->subslice_mask = |
4533 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4534 | |
5d39525a JM |
4535 | for (ss = 0; ss < ss_max; ss++) { |
4536 | unsigned int eu_cnt; | |
4537 | ||
cc3f90f0 | 4538 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4539 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4540 | /* skip disabled subslice */ | |
4541 | continue; | |
1c046bc1 | 4542 | |
57ec171e ID |
4543 | sseu->subslice_mask |= BIT(ss); |
4544 | } | |
1c046bc1 | 4545 | |
5d39525a JM |
4546 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4547 | eu_mask[ss%2]); | |
915490d5 ID |
4548 | sseu->eu_total += eu_cnt; |
4549 | sseu->eu_per_subslice = max_t(unsigned int, | |
4550 | sseu->eu_per_subslice, | |
4551 | eu_cnt); | |
5d39525a JM |
4552 | } |
4553 | } | |
4554 | } | |
4555 | ||
36cdd013 | 4556 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4557 | struct sseu_dev_info *sseu) |
91bedd34 | 4558 | { |
91bedd34 | 4559 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4560 | int s; |
91bedd34 | 4561 | |
f08a0c92 | 4562 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4563 | |
f08a0c92 | 4564 | if (sseu->slice_mask) { |
57ec171e | 4565 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4566 | sseu->eu_per_subslice = |
4567 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4568 | sseu->eu_total = sseu->eu_per_subslice * |
4569 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4570 | |
4571 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4572 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4573 | u8 subslice_7eu = |
4574 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4575 | |
915490d5 | 4576 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4577 | } |
4578 | } | |
4579 | } | |
4580 | ||
615d8908 ID |
4581 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4582 | const struct sseu_dev_info *sseu) | |
4583 | { | |
4584 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4585 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4586 | ||
c67ba538 ID |
4587 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4588 | sseu->slice_mask); | |
615d8908 | 4589 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4590 | hweight8(sseu->slice_mask)); |
615d8908 | 4591 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4592 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4593 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4594 | sseu->subslice_mask); | |
615d8908 | 4595 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4596 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4597 | seq_printf(m, " %s EU Total: %u\n", type, |
4598 | sseu->eu_total); | |
4599 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4600 | sseu->eu_per_subslice); | |
4601 | ||
4602 | if (!is_available_info) | |
4603 | return; | |
4604 | ||
4605 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4606 | if (HAS_POOLED_EU(dev_priv)) | |
4607 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4608 | ||
4609 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4610 | yesno(sseu->has_slice_pg)); | |
4611 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4612 | yesno(sseu->has_subslice_pg)); | |
4613 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4614 | yesno(sseu->has_eu_pg)); | |
4615 | } | |
4616 | ||
3873218f JM |
4617 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4618 | { | |
36cdd013 | 4619 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4620 | struct sseu_dev_info sseu; |
3873218f | 4621 | |
36cdd013 | 4622 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4623 | return -ENODEV; |
4624 | ||
4625 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4626 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4627 | |
7f992aba | 4628 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4629 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4630 | |
4631 | intel_runtime_pm_get(dev_priv); | |
4632 | ||
36cdd013 | 4633 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4634 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4635 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4636 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4637 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4638 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4639 | } |
238010ed DW |
4640 | |
4641 | intel_runtime_pm_put(dev_priv); | |
4642 | ||
615d8908 | 4643 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4644 | |
3873218f JM |
4645 | return 0; |
4646 | } | |
4647 | ||
6d794d42 BW |
4648 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4649 | { | |
36cdd013 | 4650 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4651 | |
36cdd013 | 4652 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4653 | return 0; |
4654 | ||
6daccb0b | 4655 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4656 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4657 | |
4658 | return 0; | |
4659 | } | |
4660 | ||
c43b5634 | 4661 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4662 | { |
36cdd013 | 4663 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4664 | |
36cdd013 | 4665 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4666 | return 0; |
4667 | ||
59bad947 | 4668 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4669 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4670 | |
4671 | return 0; | |
4672 | } | |
4673 | ||
4674 | static const struct file_operations i915_forcewake_fops = { | |
4675 | .owner = THIS_MODULE, | |
4676 | .open = i915_forcewake_open, | |
4677 | .release = i915_forcewake_release, | |
4678 | }; | |
4679 | ||
317eaa95 L |
4680 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4681 | { | |
4682 | struct drm_i915_private *dev_priv = m->private; | |
4683 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4684 | ||
4685 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4686 | seq_printf(m, "Detected: %s\n", | |
4687 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4688 | ||
4689 | return 0; | |
4690 | } | |
4691 | ||
4692 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4693 | const char __user *ubuf, size_t len, | |
4694 | loff_t *offp) | |
4695 | { | |
4696 | struct seq_file *m = file->private_data; | |
4697 | struct drm_i915_private *dev_priv = m->private; | |
4698 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4699 | unsigned int new_threshold; | |
4700 | int i; | |
4701 | char *newline; | |
4702 | char tmp[16]; | |
4703 | ||
4704 | if (len >= sizeof(tmp)) | |
4705 | return -EINVAL; | |
4706 | ||
4707 | if (copy_from_user(tmp, ubuf, len)) | |
4708 | return -EFAULT; | |
4709 | ||
4710 | tmp[len] = '\0'; | |
4711 | ||
4712 | /* Strip newline, if any */ | |
4713 | newline = strchr(tmp, '\n'); | |
4714 | if (newline) | |
4715 | *newline = '\0'; | |
4716 | ||
4717 | if (strcmp(tmp, "reset") == 0) | |
4718 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4719 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4720 | return -EINVAL; | |
4721 | ||
4722 | if (new_threshold > 0) | |
4723 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4724 | new_threshold); | |
4725 | else | |
4726 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4727 | ||
4728 | spin_lock_irq(&dev_priv->irq_lock); | |
4729 | hotplug->hpd_storm_threshold = new_threshold; | |
4730 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4731 | for_each_hpd_pin(i) | |
4732 | hotplug->stats[i].count = 0; | |
4733 | spin_unlock_irq(&dev_priv->irq_lock); | |
4734 | ||
4735 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4736 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4737 | ||
4738 | return len; | |
4739 | } | |
4740 | ||
4741 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4742 | { | |
4743 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4744 | } | |
4745 | ||
4746 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4747 | .owner = THIS_MODULE, | |
4748 | .open = i915_hpd_storm_ctl_open, | |
4749 | .read = seq_read, | |
4750 | .llseek = seq_lseek, | |
4751 | .release = single_release, | |
4752 | .write = i915_hpd_storm_ctl_write | |
4753 | }; | |
4754 | ||
06c5bf8c | 4755 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4756 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4757 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4758 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4759 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4760 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4761 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4762 | {"i915_gem_request", i915_gem_request_info, 0}, |
4763 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4764 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4765 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4766 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4767 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4768 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4769 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
0509ead1 | 4770 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4771 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4772 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4773 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4774 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4775 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4776 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4777 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4778 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4779 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4780 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4781 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4782 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4783 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4784 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4785 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4786 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4787 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4788 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4789 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4790 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4791 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4792 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4793 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4794 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4795 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4796 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4797 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4798 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4799 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4800 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4801 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4802 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4803 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4804 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4805 | }; |
27c202ad | 4806 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4807 | |
06c5bf8c | 4808 | static const struct i915_debugfs_files { |
34b9674c DV |
4809 | const char *name; |
4810 | const struct file_operations *fops; | |
4811 | } i915_debugfs_files[] = { | |
4812 | {"i915_wedged", &i915_wedged_fops}, | |
4813 | {"i915_max_freq", &i915_max_freq_fops}, | |
4814 | {"i915_min_freq", &i915_min_freq_fops}, | |
4815 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4816 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4817 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4818 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4819 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4820 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4821 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4822 | #endif |
34b9674c | 4823 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4824 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4825 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4826 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4827 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4828 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4829 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4830 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4831 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4832 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4833 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4834 | }; |
4835 | ||
1dac891c | 4836 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4837 | { |
91c8a326 | 4838 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4839 | struct dentry *ent; |
34b9674c | 4840 | int ret, i; |
f3cd474b | 4841 | |
b05eeb0f NT |
4842 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4843 | minor->debugfs_root, to_i915(minor->dev), | |
4844 | &i915_forcewake_fops); | |
4845 | if (!ent) | |
4846 | return -ENOMEM; | |
6a9c308d | 4847 | |
731035fe TV |
4848 | ret = intel_pipe_crc_create(minor); |
4849 | if (ret) | |
4850 | return ret; | |
07144428 | 4851 | |
34b9674c | 4852 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4853 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4854 | S_IRUGO | S_IWUSR, | |
4855 | minor->debugfs_root, | |
4856 | to_i915(minor->dev), | |
34b9674c | 4857 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4858 | if (!ent) |
4859 | return -ENOMEM; | |
34b9674c | 4860 | } |
40633219 | 4861 | |
27c202ad BG |
4862 | return drm_debugfs_create_files(i915_debugfs_list, |
4863 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4864 | minor->debugfs_root, minor); |
4865 | } | |
4866 | ||
aa7471d2 JN |
4867 | struct dpcd_block { |
4868 | /* DPCD dump start address. */ | |
4869 | unsigned int offset; | |
4870 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4871 | unsigned int end; | |
4872 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4873 | size_t size; | |
4874 | /* Only valid for eDP. */ | |
4875 | bool edp; | |
4876 | }; | |
4877 | ||
4878 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4879 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4880 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4881 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4882 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4883 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4884 | { .offset = DP_SET_POWER }, | |
4885 | { .offset = DP_EDP_DPCD_REV }, | |
4886 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4887 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4888 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4889 | }; | |
4890 | ||
4891 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4892 | { | |
4893 | struct drm_connector *connector = m->private; | |
4894 | struct intel_dp *intel_dp = | |
4895 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4896 | uint8_t buf[16]; | |
4897 | ssize_t err; | |
4898 | int i; | |
4899 | ||
5c1a8875 MK |
4900 | if (connector->status != connector_status_connected) |
4901 | return -ENODEV; | |
4902 | ||
aa7471d2 JN |
4903 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4904 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4905 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4906 | ||
4907 | if (b->edp && | |
4908 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4909 | continue; | |
4910 | ||
4911 | /* low tech for now */ | |
4912 | if (WARN_ON(size > sizeof(buf))) | |
4913 | continue; | |
4914 | ||
4915 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4916 | if (err <= 0) { | |
4917 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4918 | size, b->offset, err); | |
4919 | continue; | |
4920 | } | |
4921 | ||
4922 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4923 | } |
aa7471d2 JN |
4924 | |
4925 | return 0; | |
4926 | } | |
4927 | ||
4928 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4929 | { | |
4930 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4931 | } | |
4932 | ||
4933 | static const struct file_operations i915_dpcd_fops = { | |
4934 | .owner = THIS_MODULE, | |
4935 | .open = i915_dpcd_open, | |
4936 | .read = seq_read, | |
4937 | .llseek = seq_lseek, | |
4938 | .release = single_release, | |
4939 | }; | |
4940 | ||
ecbd6781 DW |
4941 | static int i915_panel_show(struct seq_file *m, void *data) |
4942 | { | |
4943 | struct drm_connector *connector = m->private; | |
4944 | struct intel_dp *intel_dp = | |
4945 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4946 | ||
4947 | if (connector->status != connector_status_connected) | |
4948 | return -ENODEV; | |
4949 | ||
4950 | seq_printf(m, "Panel power up delay: %d\n", | |
4951 | intel_dp->panel_power_up_delay); | |
4952 | seq_printf(m, "Panel power down delay: %d\n", | |
4953 | intel_dp->panel_power_down_delay); | |
4954 | seq_printf(m, "Backlight on delay: %d\n", | |
4955 | intel_dp->backlight_on_delay); | |
4956 | seq_printf(m, "Backlight off delay: %d\n", | |
4957 | intel_dp->backlight_off_delay); | |
4958 | ||
4959 | return 0; | |
4960 | } | |
4961 | ||
4962 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4963 | { | |
4964 | return single_open(file, i915_panel_show, inode->i_private); | |
4965 | } | |
4966 | ||
4967 | static const struct file_operations i915_panel_fops = { | |
4968 | .owner = THIS_MODULE, | |
4969 | .open = i915_panel_open, | |
4970 | .read = seq_read, | |
4971 | .llseek = seq_lseek, | |
4972 | .release = single_release, | |
4973 | }; | |
4974 | ||
aa7471d2 JN |
4975 | /** |
4976 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4977 | * @connector: pointer to a registered drm_connector | |
4978 | * | |
4979 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4980 | * drm_debugfs_connector_remove(). | |
4981 | * | |
4982 | * Returns 0 on success, negative error codes on error. | |
4983 | */ | |
4984 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4985 | { | |
4986 | struct dentry *root = connector->debugfs_entry; | |
4987 | ||
4988 | /* The connector must have been registered beforehands. */ | |
4989 | if (!root) | |
4990 | return -ENODEV; | |
4991 | ||
4992 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4993 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4994 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4995 | connector, &i915_dpcd_fops); | |
4996 | ||
4997 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4998 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4999 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5000 | |
5001 | return 0; | |
5002 | } |