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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
760285e7 | 33 | #include <drm/drmP.h> |
4e5359cd | 34 | #include "intel_drv.h" |
e5c65260 | 35 | #include "intel_ringbuffer.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
2017263e BG |
37 | #include "i915_drv.h" |
38 | ||
39 | #define DRM_I915_RING_DEBUG 1 | |
40 | ||
41 | ||
42 | #if defined(CONFIG_DEBUG_FS) | |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 | 46 | INACTIVE_LIST, |
d21d5975 | 47 | PINNED_LIST, |
f13d3f73 | 48 | }; |
2017263e | 49 | |
70d39fe4 CW |
50 | static const char *yesno(int v) |
51 | { | |
52 | return v ? "yes" : "no"; | |
53 | } | |
54 | ||
55 | static int i915_capabilities(struct seq_file *m, void *data) | |
56 | { | |
57 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
58 | struct drm_device *dev = node->minor->dev; | |
59 | const struct intel_device_info *info = INTEL_INFO(dev); | |
60 | ||
61 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
c96ea64e DV |
63 | #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
64 | #define DEV_INFO_SEP ; | |
65 | DEV_INFO_FLAGS; | |
66 | #undef DEV_INFO_FLAG | |
67 | #undef DEV_INFO_SEP | |
70d39fe4 CW |
68 | |
69 | return 0; | |
70 | } | |
2017263e | 71 | |
05394f39 | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 73 | { |
05394f39 | 74 | if (obj->user_pin_count > 0) |
a6172a80 | 75 | return "P"; |
05394f39 | 76 | else if (obj->pin_count > 0) |
a6172a80 CW |
77 | return "p"; |
78 | else | |
79 | return " "; | |
80 | } | |
81 | ||
05394f39 | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 83 | { |
0206e353 AJ |
84 | switch (obj->tiling_mode) { |
85 | default: | |
86 | case I915_TILING_NONE: return " "; | |
87 | case I915_TILING_X: return "X"; | |
88 | case I915_TILING_Y: return "Y"; | |
89 | } | |
a6172a80 CW |
90 | } |
91 | ||
93dfb40c | 92 | static const char *cache_level_str(int type) |
08c18323 CW |
93 | { |
94 | switch (type) { | |
93dfb40c CW |
95 | case I915_CACHE_NONE: return " uncached"; |
96 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
97 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
98 | default: return ""; |
99 | } | |
100 | } | |
101 | ||
37811fcc CW |
102 | static void |
103 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
104 | { | |
04b97b34 | 105 | seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
37811fcc CW |
106 | &obj->base, |
107 | get_pin_flag(obj), | |
108 | get_tiling_flag(obj), | |
a05a5862 | 109 | obj->base.size / 1024, |
37811fcc CW |
110 | obj->base.read_domains, |
111 | obj->base.write_domain, | |
0201f1ec CW |
112 | obj->last_read_seqno, |
113 | obj->last_write_seqno, | |
caea7476 | 114 | obj->last_fenced_seqno, |
93dfb40c | 115 | cache_level_str(obj->cache_level), |
37811fcc CW |
116 | obj->dirty ? " dirty" : "", |
117 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
118 | if (obj->base.name) | |
119 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
120 | if (obj->pin_count) |
121 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
122 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
123 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
124 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
125 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
126 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
c1ad11fc CW |
127 | if (obj->stolen) |
128 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
129 | if (obj->pin_mappable || obj->fault_mappable) { |
130 | char s[3], *t = s; | |
131 | if (obj->pin_mappable) | |
132 | *t++ = 'p'; | |
133 | if (obj->fault_mappable) | |
134 | *t++ = 'f'; | |
135 | *t = '\0'; | |
136 | seq_printf(m, " (%s mappable)", s); | |
137 | } | |
69dc4987 CW |
138 | if (obj->ring != NULL) |
139 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
140 | } |
141 | ||
433e12f7 | 142 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
143 | { |
144 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
145 | uintptr_t list = (uintptr_t) node->info_ent->data; |
146 | struct list_head *head; | |
2017263e BG |
147 | struct drm_device *dev = node->minor->dev; |
148 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 149 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
150 | size_t total_obj_size, total_gtt_size; |
151 | int count, ret; | |
de227ef0 CW |
152 | |
153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
154 | if (ret) | |
155 | return ret; | |
2017263e | 156 | |
433e12f7 BG |
157 | switch (list) { |
158 | case ACTIVE_LIST: | |
159 | seq_printf(m, "Active:\n"); | |
69dc4987 | 160 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
161 | break; |
162 | case INACTIVE_LIST: | |
a17458fc | 163 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
164 | head = &dev_priv->mm.inactive_list; |
165 | break; | |
433e12f7 | 166 | default: |
de227ef0 CW |
167 | mutex_unlock(&dev->struct_mutex); |
168 | return -EINVAL; | |
2017263e | 169 | } |
2017263e | 170 | |
8f2480fb | 171 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 172 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 173 | seq_printf(m, " "); |
05394f39 | 174 | describe_obj(m, obj); |
f4ceda89 | 175 | seq_printf(m, "\n"); |
05394f39 CW |
176 | total_obj_size += obj->base.size; |
177 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 178 | count++; |
2017263e | 179 | } |
de227ef0 | 180 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 181 | |
8f2480fb CW |
182 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
183 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
184 | return 0; |
185 | } | |
186 | ||
6299f992 CW |
187 | #define count_objects(list, member) do { \ |
188 | list_for_each_entry(obj, list, member) { \ | |
189 | size += obj->gtt_space->size; \ | |
190 | ++count; \ | |
191 | if (obj->map_and_fenceable) { \ | |
192 | mappable_size += obj->gtt_space->size; \ | |
193 | ++mappable_count; \ | |
194 | } \ | |
195 | } \ | |
0206e353 | 196 | } while (0) |
6299f992 | 197 | |
73aa808f CW |
198 | static int i915_gem_object_info(struct seq_file *m, void* data) |
199 | { | |
200 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
201 | struct drm_device *dev = node->minor->dev; | |
202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
203 | u32 count, mappable_count, purgeable_count; |
204 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 205 | struct drm_i915_gem_object *obj; |
73aa808f CW |
206 | int ret; |
207 | ||
208 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
209 | if (ret) | |
210 | return ret; | |
211 | ||
6299f992 CW |
212 | seq_printf(m, "%u objects, %zu bytes\n", |
213 | dev_priv->mm.object_count, | |
214 | dev_priv->mm.object_memory); | |
215 | ||
216 | size = count = mappable_size = mappable_count = 0; | |
6c085a72 | 217 | count_objects(&dev_priv->mm.bound_list, gtt_list); |
6299f992 CW |
218 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
219 | count, mappable_count, size, mappable_size); | |
220 | ||
221 | size = count = mappable_size = mappable_count = 0; | |
222 | count_objects(&dev_priv->mm.active_list, mm_list); | |
6299f992 CW |
223 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
224 | count, mappable_count, size, mappable_size); | |
225 | ||
6299f992 CW |
226 | size = count = mappable_size = mappable_count = 0; |
227 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
228 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
229 | count, mappable_count, size, mappable_size); | |
230 | ||
b7abb714 CW |
231 | size = count = purgeable_size = purgeable_count = 0; |
232 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) { | |
6c085a72 | 233 | size += obj->base.size, ++count; |
b7abb714 CW |
234 | if (obj->madv == I915_MADV_DONTNEED) |
235 | purgeable_size += obj->base.size, ++purgeable_count; | |
236 | } | |
6c085a72 CW |
237 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
238 | ||
6299f992 | 239 | size = count = mappable_size = mappable_count = 0; |
6c085a72 | 240 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
6299f992 CW |
241 | if (obj->fault_mappable) { |
242 | size += obj->gtt_space->size; | |
243 | ++count; | |
244 | } | |
245 | if (obj->pin_mappable) { | |
246 | mappable_size += obj->gtt_space->size; | |
247 | ++mappable_count; | |
248 | } | |
b7abb714 CW |
249 | if (obj->madv == I915_MADV_DONTNEED) { |
250 | purgeable_size += obj->base.size; | |
251 | ++purgeable_count; | |
252 | } | |
6299f992 | 253 | } |
b7abb714 CW |
254 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
255 | purgeable_count, purgeable_size); | |
6299f992 CW |
256 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
257 | mappable_count, mappable_size); | |
258 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
259 | count, size); | |
260 | ||
261 | seq_printf(m, "%zu [%zu] gtt total\n", | |
262 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
263 | |
264 | mutex_unlock(&dev->struct_mutex); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
08c18323 CW |
269 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
270 | { | |
271 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
272 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 273 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
274 | struct drm_i915_private *dev_priv = dev->dev_private; |
275 | struct drm_i915_gem_object *obj; | |
276 | size_t total_obj_size, total_gtt_size; | |
277 | int count, ret; | |
278 | ||
279 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
280 | if (ret) | |
281 | return ret; | |
282 | ||
283 | total_obj_size = total_gtt_size = count = 0; | |
6c085a72 | 284 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
1b50247a CW |
285 | if (list == PINNED_LIST && obj->pin_count == 0) |
286 | continue; | |
287 | ||
08c18323 CW |
288 | seq_printf(m, " "); |
289 | describe_obj(m, obj); | |
290 | seq_printf(m, "\n"); | |
291 | total_obj_size += obj->base.size; | |
292 | total_gtt_size += obj->gtt_space->size; | |
293 | count++; | |
294 | } | |
295 | ||
296 | mutex_unlock(&dev->struct_mutex); | |
297 | ||
298 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
299 | count, total_obj_size, total_gtt_size); | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
4e5359cd SF |
304 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
305 | { | |
306 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
307 | struct drm_device *dev = node->minor->dev; | |
308 | unsigned long flags; | |
309 | struct intel_crtc *crtc; | |
310 | ||
311 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
312 | const char pipe = pipe_name(crtc->pipe); |
313 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
314 | struct intel_unpin_work *work; |
315 | ||
316 | spin_lock_irqsave(&dev->event_lock, flags); | |
317 | work = crtc->unpin_work; | |
318 | if (work == NULL) { | |
9db4a9c7 | 319 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
320 | pipe, plane); |
321 | } else { | |
322 | if (!work->pending) { | |
9db4a9c7 | 323 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
324 | pipe, plane); |
325 | } else { | |
9db4a9c7 | 326 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
327 | pipe, plane); |
328 | } | |
329 | if (work->enable_stall_check) | |
330 | seq_printf(m, "Stall check enabled, "); | |
331 | else | |
332 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
333 | seq_printf(m, "%d prepares\n", work->pending); | |
334 | ||
335 | if (work->old_fb_obj) { | |
05394f39 CW |
336 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
337 | if (obj) | |
338 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
339 | } |
340 | if (work->pending_flip_obj) { | |
05394f39 CW |
341 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
342 | if (obj) | |
343 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
344 | } |
345 | } | |
346 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
2017263e BG |
352 | static int i915_gem_request_info(struct seq_file *m, void *data) |
353 | { | |
354 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
355 | struct drm_device *dev = node->minor->dev; | |
356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 357 | struct intel_ring_buffer *ring; |
2017263e | 358 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 359 | int ret, count, i; |
de227ef0 CW |
360 | |
361 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
362 | if (ret) | |
363 | return ret; | |
2017263e | 364 | |
c2c347a9 | 365 | count = 0; |
a2c7f6fd CW |
366 | for_each_ring(ring, dev_priv, i) { |
367 | if (list_empty(&ring->request_list)) | |
368 | continue; | |
369 | ||
370 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 371 | list_for_each_entry(gem_request, |
a2c7f6fd | 372 | &ring->request_list, |
c2c347a9 CW |
373 | list) { |
374 | seq_printf(m, " %d @ %d\n", | |
375 | gem_request->seqno, | |
376 | (int) (jiffies - gem_request->emitted_jiffies)); | |
377 | } | |
378 | count++; | |
2017263e | 379 | } |
de227ef0 CW |
380 | mutex_unlock(&dev->struct_mutex); |
381 | ||
c2c347a9 CW |
382 | if (count == 0) |
383 | seq_printf(m, "No requests\n"); | |
384 | ||
2017263e BG |
385 | return 0; |
386 | } | |
387 | ||
b2223497 CW |
388 | static void i915_ring_seqno_info(struct seq_file *m, |
389 | struct intel_ring_buffer *ring) | |
390 | { | |
391 | if (ring->get_seqno) { | |
392 | seq_printf(m, "Current sequence (%s): %d\n", | |
b2eadbc8 | 393 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
394 | } |
395 | } | |
396 | ||
2017263e BG |
397 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
398 | { | |
399 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
400 | struct drm_device *dev = node->minor->dev; | |
401 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 402 | struct intel_ring_buffer *ring; |
1ec14ad3 | 403 | int ret, i; |
de227ef0 CW |
404 | |
405 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
406 | if (ret) | |
407 | return ret; | |
2017263e | 408 | |
a2c7f6fd CW |
409 | for_each_ring(ring, dev_priv, i) |
410 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
411 | |
412 | mutex_unlock(&dev->struct_mutex); | |
413 | ||
2017263e BG |
414 | return 0; |
415 | } | |
416 | ||
417 | ||
418 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
419 | { | |
420 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
421 | struct drm_device *dev = node->minor->dev; | |
422 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 423 | struct intel_ring_buffer *ring; |
9db4a9c7 | 424 | int ret, i, pipe; |
de227ef0 CW |
425 | |
426 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
427 | if (ret) | |
428 | return ret; | |
2017263e | 429 | |
7e231dbe JB |
430 | if (IS_VALLEYVIEW(dev)) { |
431 | seq_printf(m, "Display IER:\t%08x\n", | |
432 | I915_READ(VLV_IER)); | |
433 | seq_printf(m, "Display IIR:\t%08x\n", | |
434 | I915_READ(VLV_IIR)); | |
435 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
436 | I915_READ(VLV_IIR_RW)); | |
437 | seq_printf(m, "Display IMR:\t%08x\n", | |
438 | I915_READ(VLV_IMR)); | |
439 | for_each_pipe(pipe) | |
440 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
441 | pipe_name(pipe), | |
442 | I915_READ(PIPESTAT(pipe))); | |
443 | ||
444 | seq_printf(m, "Master IER:\t%08x\n", | |
445 | I915_READ(VLV_MASTER_IER)); | |
446 | ||
447 | seq_printf(m, "Render IER:\t%08x\n", | |
448 | I915_READ(GTIER)); | |
449 | seq_printf(m, "Render IIR:\t%08x\n", | |
450 | I915_READ(GTIIR)); | |
451 | seq_printf(m, "Render IMR:\t%08x\n", | |
452 | I915_READ(GTIMR)); | |
453 | ||
454 | seq_printf(m, "PM IER:\t\t%08x\n", | |
455 | I915_READ(GEN6_PMIER)); | |
456 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
457 | I915_READ(GEN6_PMIIR)); | |
458 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
459 | I915_READ(GEN6_PMIMR)); | |
460 | ||
461 | seq_printf(m, "Port hotplug:\t%08x\n", | |
462 | I915_READ(PORT_HOTPLUG_EN)); | |
463 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
464 | I915_READ(VLV_DPFLIPSTAT)); | |
465 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
466 | I915_READ(DPINVGTT)); | |
467 | ||
468 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
469 | seq_printf(m, "Interrupt enable: %08x\n", |
470 | I915_READ(IER)); | |
471 | seq_printf(m, "Interrupt identity: %08x\n", | |
472 | I915_READ(IIR)); | |
473 | seq_printf(m, "Interrupt mask: %08x\n", | |
474 | I915_READ(IMR)); | |
9db4a9c7 JB |
475 | for_each_pipe(pipe) |
476 | seq_printf(m, "Pipe %c stat: %08x\n", | |
477 | pipe_name(pipe), | |
478 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
479 | } else { |
480 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
481 | I915_READ(DEIER)); | |
482 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
483 | I915_READ(DEIIR)); | |
484 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
485 | I915_READ(DEIMR)); | |
486 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
487 | I915_READ(SDEIER)); | |
488 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
489 | I915_READ(SDEIIR)); | |
490 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
491 | I915_READ(SDEIMR)); | |
492 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
493 | I915_READ(GTIER)); | |
494 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
495 | I915_READ(GTIIR)); | |
496 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
497 | I915_READ(GTIMR)); | |
498 | } | |
2017263e BG |
499 | seq_printf(m, "Interrupts received: %d\n", |
500 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 501 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 502 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
503 | seq_printf(m, |
504 | "Graphics Interrupt mask (%s): %08x\n", | |
505 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 506 | } |
a2c7f6fd | 507 | i915_ring_seqno_info(m, ring); |
9862e600 | 508 | } |
de227ef0 CW |
509 | mutex_unlock(&dev->struct_mutex); |
510 | ||
2017263e BG |
511 | return 0; |
512 | } | |
513 | ||
a6172a80 CW |
514 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
515 | { | |
516 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
517 | struct drm_device *dev = node->minor->dev; | |
518 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
519 | int i, ret; |
520 | ||
521 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
522 | if (ret) | |
523 | return ret; | |
a6172a80 CW |
524 | |
525 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
526 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
527 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 528 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 529 | |
6c085a72 CW |
530 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
531 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 CW |
532 | if (obj == NULL) |
533 | seq_printf(m, "unused"); | |
534 | else | |
05394f39 | 535 | describe_obj(m, obj); |
c2c347a9 | 536 | seq_printf(m, "\n"); |
a6172a80 CW |
537 | } |
538 | ||
05394f39 | 539 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
540 | return 0; |
541 | } | |
542 | ||
2017263e BG |
543 | static int i915_hws_info(struct seq_file *m, void *data) |
544 | { | |
545 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
546 | struct drm_device *dev = node->minor->dev; | |
547 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 548 | struct intel_ring_buffer *ring; |
1a240d4d | 549 | const u32 *hws; |
4066c0ae CW |
550 | int i; |
551 | ||
1ec14ad3 | 552 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 553 | hws = ring->status_page.page_addr; |
2017263e BG |
554 | if (hws == NULL) |
555 | return 0; | |
556 | ||
557 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
558 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
559 | i * 4, | |
560 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | ||
e5c65260 CW |
565 | static const char *ring_str(int ring) |
566 | { | |
567 | switch (ring) { | |
96154f2f DV |
568 | case RCS: return "render"; |
569 | case VCS: return "bsd"; | |
570 | case BCS: return "blt"; | |
e5c65260 CW |
571 | default: return ""; |
572 | } | |
573 | } | |
574 | ||
9df30794 CW |
575 | static const char *pin_flag(int pinned) |
576 | { | |
577 | if (pinned > 0) | |
578 | return " P"; | |
579 | else if (pinned < 0) | |
580 | return " p"; | |
581 | else | |
582 | return ""; | |
583 | } | |
584 | ||
585 | static const char *tiling_flag(int tiling) | |
586 | { | |
587 | switch (tiling) { | |
588 | default: | |
589 | case I915_TILING_NONE: return ""; | |
590 | case I915_TILING_X: return " X"; | |
591 | case I915_TILING_Y: return " Y"; | |
592 | } | |
593 | } | |
594 | ||
595 | static const char *dirty_flag(int dirty) | |
596 | { | |
597 | return dirty ? " dirty" : ""; | |
598 | } | |
599 | ||
600 | static const char *purgeable_flag(int purgeable) | |
601 | { | |
602 | return purgeable ? " purgeable" : ""; | |
603 | } | |
604 | ||
c724e8a9 CW |
605 | static void print_error_buffers(struct seq_file *m, |
606 | const char *name, | |
607 | struct drm_i915_error_buffer *err, | |
608 | int count) | |
609 | { | |
610 | seq_printf(m, "%s [%d]:\n", name, count); | |
611 | ||
612 | while (count--) { | |
04b97b34 | 613 | seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s", |
c724e8a9 CW |
614 | err->gtt_offset, |
615 | err->size, | |
616 | err->read_domains, | |
617 | err->write_domain, | |
0201f1ec | 618 | err->rseqno, err->wseqno, |
c724e8a9 CW |
619 | pin_flag(err->pinned), |
620 | tiling_flag(err->tiling), | |
621 | dirty_flag(err->dirty), | |
622 | purgeable_flag(err->purgeable), | |
96154f2f | 623 | err->ring != -1 ? " " : "", |
a779e5ab | 624 | ring_str(err->ring), |
93dfb40c | 625 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
626 | |
627 | if (err->name) | |
628 | seq_printf(m, " (name: %d)", err->name); | |
629 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
630 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
631 | ||
632 | seq_printf(m, "\n"); | |
633 | err++; | |
634 | } | |
635 | } | |
636 | ||
d27b1e0e DV |
637 | static void i915_ring_error_state(struct seq_file *m, |
638 | struct drm_device *dev, | |
639 | struct drm_i915_error_state *error, | |
640 | unsigned ring) | |
641 | { | |
ec34a01d | 642 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 643 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
644 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
645 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
d27b1e0e DV |
646 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
647 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
648 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
649 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
050ee91f | 650 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) |
c1cd90ed | 651 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); |
050ee91f | 652 | |
c1cd90ed DV |
653 | if (INTEL_INFO(dev)->gen >= 4) |
654 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
655 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 656 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 657 | if (INTEL_INFO(dev)->gen >= 6) { |
12f55818 | 658 | seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); |
33f3f518 | 659 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
df2b23d9 CW |
660 | seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
661 | error->semaphore_mboxes[ring][0], | |
662 | error->semaphore_seqno[ring][0]); | |
663 | seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", | |
664 | error->semaphore_mboxes[ring][1], | |
665 | error->semaphore_seqno[ring][1]); | |
33f3f518 | 666 | } |
d27b1e0e | 667 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
9574b3fe | 668 | seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); |
7e3b8737 DV |
669 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
670 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
671 | } |
672 | ||
d5442303 DV |
673 | struct i915_error_state_file_priv { |
674 | struct drm_device *dev; | |
675 | struct drm_i915_error_state *error; | |
676 | }; | |
677 | ||
63eeaf38 JB |
678 | static int i915_error_state(struct seq_file *m, void *unused) |
679 | { | |
d5442303 DV |
680 | struct i915_error_state_file_priv *error_priv = m->private; |
681 | struct drm_device *dev = error_priv->dev; | |
63eeaf38 | 682 | drm_i915_private_t *dev_priv = dev->dev_private; |
d5442303 | 683 | struct drm_i915_error_state *error = error_priv->error; |
b4519513 | 684 | struct intel_ring_buffer *ring; |
52d39a21 | 685 | int i, j, page, offset, elt; |
63eeaf38 | 686 | |
742cbee8 | 687 | if (!error) { |
63eeaf38 | 688 | seq_printf(m, "no error state collected\n"); |
742cbee8 | 689 | return 0; |
63eeaf38 JB |
690 | } |
691 | ||
8a905236 JB |
692 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
693 | error->time.tv_usec); | |
9df30794 | 694 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 | 695 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
be998e2e | 696 | seq_printf(m, "IER: 0x%08x\n", error->ier); |
1d8f38f4 | 697 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
b9a3906b | 698 | seq_printf(m, "CCID: 0x%08x\n", error->ccid); |
9df30794 | 699 | |
bf3301ab | 700 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
701 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
702 | ||
050ee91f BW |
703 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) |
704 | seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]); | |
705 | ||
33f3f518 | 706 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 707 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
708 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
709 | } | |
d27b1e0e | 710 | |
71e172e8 BW |
711 | if (INTEL_INFO(dev)->gen == 7) |
712 | seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int); | |
713 | ||
b4519513 CW |
714 | for_each_ring(ring, dev_priv, i) |
715 | i915_ring_error_state(m, dev, error, i); | |
d27b1e0e | 716 | |
c724e8a9 CW |
717 | if (error->active_bo) |
718 | print_error_buffers(m, "Active", | |
719 | error->active_bo, | |
720 | error->active_bo_count); | |
721 | ||
722 | if (error->pinned_bo) | |
723 | print_error_buffers(m, "Pinned", | |
724 | error->pinned_bo, | |
725 | error->pinned_bo_count); | |
9df30794 | 726 | |
52d39a21 CW |
727 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
728 | struct drm_i915_error_object *obj; | |
9df30794 | 729 | |
52d39a21 | 730 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
731 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
732 | dev_priv->ring[i].name, | |
733 | obj->gtt_offset); | |
9df30794 CW |
734 | offset = 0; |
735 | for (page = 0; page < obj->page_count; page++) { | |
736 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
737 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
738 | offset += 4; | |
739 | } | |
740 | } | |
741 | } | |
9df30794 | 742 | |
52d39a21 CW |
743 | if (error->ring[i].num_requests) { |
744 | seq_printf(m, "%s --- %d requests\n", | |
745 | dev_priv->ring[i].name, | |
746 | error->ring[i].num_requests); | |
747 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 748 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 749 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
750 | error->ring[i].requests[j].jiffies, |
751 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
752 | } |
753 | } | |
754 | ||
755 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
756 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
757 | dev_priv->ring[i].name, | |
758 | obj->gtt_offset); | |
759 | offset = 0; | |
760 | for (page = 0; page < obj->page_count; page++) { | |
761 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
762 | seq_printf(m, "%08x : %08x\n", | |
763 | offset, | |
764 | obj->pages[page][elt]); | |
765 | offset += 4; | |
766 | } | |
9df30794 CW |
767 | } |
768 | } | |
769 | } | |
63eeaf38 | 770 | |
6ef3d427 CW |
771 | if (error->overlay) |
772 | intel_overlay_print_error_state(m, error->overlay); | |
773 | ||
c4a1d9e4 CW |
774 | if (error->display) |
775 | intel_display_print_error_state(m, dev, error->display); | |
776 | ||
63eeaf38 JB |
777 | return 0; |
778 | } | |
6911a9b8 | 779 | |
d5442303 DV |
780 | static ssize_t |
781 | i915_error_state_write(struct file *filp, | |
782 | const char __user *ubuf, | |
783 | size_t cnt, | |
784 | loff_t *ppos) | |
785 | { | |
786 | struct seq_file *m = filp->private_data; | |
787 | struct i915_error_state_file_priv *error_priv = m->private; | |
788 | struct drm_device *dev = error_priv->dev; | |
22bcfc6a | 789 | int ret; |
d5442303 DV |
790 | |
791 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
792 | ||
22bcfc6a DV |
793 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
794 | if (ret) | |
795 | return ret; | |
796 | ||
d5442303 DV |
797 | i915_destroy_error_state(dev); |
798 | mutex_unlock(&dev->struct_mutex); | |
799 | ||
800 | return cnt; | |
801 | } | |
802 | ||
803 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
804 | { | |
805 | struct drm_device *dev = inode->i_private; | |
806 | drm_i915_private_t *dev_priv = dev->dev_private; | |
807 | struct i915_error_state_file_priv *error_priv; | |
808 | unsigned long flags; | |
809 | ||
810 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
811 | if (!error_priv) | |
812 | return -ENOMEM; | |
813 | ||
814 | error_priv->dev = dev; | |
815 | ||
816 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
817 | error_priv->error = dev_priv->first_error; | |
818 | if (error_priv->error) | |
819 | kref_get(&error_priv->error->ref); | |
820 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
821 | ||
822 | return single_open(file, i915_error_state, error_priv); | |
823 | } | |
824 | ||
825 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
826 | { | |
827 | struct seq_file *m = file->private_data; | |
828 | struct i915_error_state_file_priv *error_priv = m->private; | |
829 | ||
830 | if (error_priv->error) | |
831 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
832 | kfree(error_priv); | |
833 | ||
834 | return single_release(inode, file); | |
835 | } | |
836 | ||
837 | static const struct file_operations i915_error_state_fops = { | |
838 | .owner = THIS_MODULE, | |
839 | .open = i915_error_state_open, | |
840 | .read = seq_read, | |
841 | .write = i915_error_state_write, | |
842 | .llseek = default_llseek, | |
843 | .release = i915_error_state_release, | |
844 | }; | |
845 | ||
f97108d1 JB |
846 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
847 | { | |
848 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
849 | struct drm_device *dev = node->minor->dev; | |
850 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
851 | u16 crstanddelay; |
852 | int ret; | |
853 | ||
854 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
855 | if (ret) | |
856 | return ret; | |
857 | ||
858 | crstanddelay = I915_READ16(CRSTANDVID); | |
859 | ||
860 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
861 | |
862 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
867 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
868 | { | |
869 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
870 | struct drm_device *dev = node->minor->dev; | |
871 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 872 | int ret; |
3b8d8d91 JB |
873 | |
874 | if (IS_GEN5(dev)) { | |
875 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
876 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
877 | ||
878 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
879 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
880 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
881 | MEMSTAT_VID_SHIFT); | |
882 | seq_printf(m, "Current P-state: %d\n", | |
883 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 884 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
885 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
886 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
887 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
888 | u32 rpstat; |
889 | u32 rpupei, rpcurup, rpprevup; | |
890 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
891 | int max_freq; |
892 | ||
893 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
894 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
895 | if (ret) | |
896 | return ret; | |
897 | ||
fcca7926 | 898 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 899 | |
ccab5c82 JB |
900 | rpstat = I915_READ(GEN6_RPSTAT1); |
901 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
902 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
903 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
904 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
905 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
906 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
907 | ||
d1ebd816 BW |
908 | gen6_gt_force_wake_put(dev_priv); |
909 | mutex_unlock(&dev->struct_mutex); | |
910 | ||
3b8d8d91 | 911 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 912 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
913 | seq_printf(m, "Render p-state ratio: %d\n", |
914 | (gt_perf_status & 0xff00) >> 8); | |
915 | seq_printf(m, "Render p-state VID: %d\n", | |
916 | gt_perf_status & 0xff); | |
917 | seq_printf(m, "Render p-state limit: %d\n", | |
918 | rp_state_limits & 0xff); | |
ccab5c82 | 919 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
c8735b0c | 920 | GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER); |
ccab5c82 JB |
921 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
922 | GEN6_CURICONT_MASK); | |
923 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
924 | GEN6_CURBSYTAVG_MASK); | |
925 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
926 | GEN6_CURBSYTAVG_MASK); | |
927 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
928 | GEN6_CURIAVG_MASK); | |
929 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
930 | GEN6_CURBSYTAVG_MASK); | |
931 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
932 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
933 | |
934 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
935 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 936 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
937 | |
938 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
939 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 940 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
941 | |
942 | max_freq = rp_state_cap & 0xff; | |
943 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 944 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
945 | } else { |
946 | seq_printf(m, "no P-state info available\n"); | |
947 | } | |
f97108d1 JB |
948 | |
949 | return 0; | |
950 | } | |
951 | ||
952 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
953 | { | |
954 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
955 | struct drm_device *dev = node->minor->dev; | |
956 | drm_i915_private_t *dev_priv = dev->dev_private; | |
957 | u32 delayfreq; | |
616fdb5a BW |
958 | int ret, i; |
959 | ||
960 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
961 | if (ret) | |
962 | return ret; | |
f97108d1 JB |
963 | |
964 | for (i = 0; i < 16; i++) { | |
965 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
966 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
967 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
968 | } |
969 | ||
616fdb5a BW |
970 | mutex_unlock(&dev->struct_mutex); |
971 | ||
f97108d1 JB |
972 | return 0; |
973 | } | |
974 | ||
975 | static inline int MAP_TO_MV(int map) | |
976 | { | |
977 | return 1250 - (map * 25); | |
978 | } | |
979 | ||
980 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
981 | { | |
982 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
983 | struct drm_device *dev = node->minor->dev; | |
984 | drm_i915_private_t *dev_priv = dev->dev_private; | |
985 | u32 inttoext; | |
616fdb5a BW |
986 | int ret, i; |
987 | ||
988 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
989 | if (ret) | |
990 | return ret; | |
f97108d1 JB |
991 | |
992 | for (i = 1; i <= 32; i++) { | |
993 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
994 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
995 | } | |
996 | ||
616fdb5a BW |
997 | mutex_unlock(&dev->struct_mutex); |
998 | ||
f97108d1 JB |
999 | return 0; |
1000 | } | |
1001 | ||
4d85529d | 1002 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1003 | { |
1004 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1005 | struct drm_device *dev = node->minor->dev; | |
1006 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1007 | u32 rgvmodectl, rstdbyctl; |
1008 | u16 crstandvid; | |
1009 | int ret; | |
1010 | ||
1011 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
1015 | rgvmodectl = I915_READ(MEMMODECTL); | |
1016 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1017 | crstandvid = I915_READ16(CRSTANDVID); | |
1018 | ||
1019 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1020 | |
1021 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1022 | "yes" : "no"); | |
1023 | seq_printf(m, "Boost freq: %d\n", | |
1024 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1025 | MEMMODE_BOOST_FREQ_SHIFT); | |
1026 | seq_printf(m, "HW control enabled: %s\n", | |
1027 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1028 | seq_printf(m, "SW control enabled: %s\n", | |
1029 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1030 | seq_printf(m, "Gated voltage change: %s\n", | |
1031 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1032 | seq_printf(m, "Starting frequency: P%d\n", | |
1033 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1034 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1035 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1036 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1037 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1038 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1039 | seq_printf(m, "Render standby enabled: %s\n", | |
1040 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1041 | seq_printf(m, "Current RS state: "); |
1042 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1043 | case RSX_STATUS_ON: | |
1044 | seq_printf(m, "on\n"); | |
1045 | break; | |
1046 | case RSX_STATUS_RC1: | |
1047 | seq_printf(m, "RC1\n"); | |
1048 | break; | |
1049 | case RSX_STATUS_RC1E: | |
1050 | seq_printf(m, "RC1E\n"); | |
1051 | break; | |
1052 | case RSX_STATUS_RS1: | |
1053 | seq_printf(m, "RS1\n"); | |
1054 | break; | |
1055 | case RSX_STATUS_RS2: | |
1056 | seq_printf(m, "RS2 (RC6)\n"); | |
1057 | break; | |
1058 | case RSX_STATUS_RS3: | |
1059 | seq_printf(m, "RC3 (RC6+)\n"); | |
1060 | break; | |
1061 | default: | |
1062 | seq_printf(m, "unknown\n"); | |
1063 | break; | |
1064 | } | |
f97108d1 JB |
1065 | |
1066 | return 0; | |
1067 | } | |
1068 | ||
4d85529d BW |
1069 | static int gen6_drpc_info(struct seq_file *m) |
1070 | { | |
1071 | ||
1072 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1073 | struct drm_device *dev = node->minor->dev; | |
1074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1075 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1076 | unsigned forcewake_count; |
4d85529d BW |
1077 | int count=0, ret; |
1078 | ||
1079 | ||
1080 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1081 | if (ret) | |
1082 | return ret; | |
1083 | ||
93b525dc DV |
1084 | spin_lock_irq(&dev_priv->gt_lock); |
1085 | forcewake_count = dev_priv->forcewake_count; | |
1086 | spin_unlock_irq(&dev_priv->gt_lock); | |
1087 | ||
1088 | if (forcewake_count) { | |
1089 | seq_printf(m, "RC information inaccurate because somebody " | |
1090 | "holds a forcewake reference \n"); | |
4d85529d BW |
1091 | } else { |
1092 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1093 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1094 | udelay(10); | |
1095 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1096 | } | |
1097 | ||
1098 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1099 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1100 | ||
1101 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1102 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1103 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1104 | mutex_lock(&dev_priv->rps.hw_lock); |
1105 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1106 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1107 | |
1108 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1109 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1110 | seq_printf(m, "HW control enabled: %s\n", | |
1111 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1112 | seq_printf(m, "SW control enabled: %s\n", | |
1113 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1114 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1115 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1116 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1117 | seq_printf(m, "RC6 Enabled: %s\n", | |
1118 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1119 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1120 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1121 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1122 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1123 | seq_printf(m, "Current RC state: "); | |
1124 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1125 | case GEN6_RC0: | |
1126 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1127 | seq_printf(m, "Core Power Down\n"); | |
1128 | else | |
1129 | seq_printf(m, "on\n"); | |
1130 | break; | |
1131 | case GEN6_RC3: | |
1132 | seq_printf(m, "RC3\n"); | |
1133 | break; | |
1134 | case GEN6_RC6: | |
1135 | seq_printf(m, "RC6\n"); | |
1136 | break; | |
1137 | case GEN6_RC7: | |
1138 | seq_printf(m, "RC7\n"); | |
1139 | break; | |
1140 | default: | |
1141 | seq_printf(m, "Unknown\n"); | |
1142 | break; | |
1143 | } | |
1144 | ||
1145 | seq_printf(m, "Core Power Down: %s\n", | |
1146 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1147 | |
1148 | /* Not exactly sure what this is */ | |
1149 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1150 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1151 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1152 | I915_READ(GEN6_GT_GFX_RC6)); | |
1153 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1154 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1155 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1156 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1157 | ||
ecd8faea BW |
1158 | seq_printf(m, "RC6 voltage: %dmV\n", |
1159 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1160 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1161 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1162 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1163 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1164 | return 0; |
1165 | } | |
1166 | ||
1167 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1168 | { | |
1169 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1170 | struct drm_device *dev = node->minor->dev; | |
1171 | ||
1172 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1173 | return gen6_drpc_info(m); | |
1174 | else | |
1175 | return ironlake_drpc_info(m); | |
1176 | } | |
1177 | ||
b5e50c3f JB |
1178 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1179 | { | |
1180 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1181 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1182 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1183 | |
ee5382ae | 1184 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1185 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1186 | return 0; | |
1187 | } | |
1188 | ||
ee5382ae | 1189 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1190 | seq_printf(m, "FBC enabled\n"); |
1191 | } else { | |
1192 | seq_printf(m, "FBC disabled: "); | |
1193 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1194 | case FBC_NO_OUTPUT: |
1195 | seq_printf(m, "no outputs"); | |
1196 | break; | |
b5e50c3f JB |
1197 | case FBC_STOLEN_TOO_SMALL: |
1198 | seq_printf(m, "not enough stolen memory"); | |
1199 | break; | |
1200 | case FBC_UNSUPPORTED_MODE: | |
1201 | seq_printf(m, "mode not supported"); | |
1202 | break; | |
1203 | case FBC_MODE_TOO_LARGE: | |
1204 | seq_printf(m, "mode too large"); | |
1205 | break; | |
1206 | case FBC_BAD_PLANE: | |
1207 | seq_printf(m, "FBC unsupported on plane"); | |
1208 | break; | |
1209 | case FBC_NOT_TILED: | |
1210 | seq_printf(m, "scanout buffer not tiled"); | |
1211 | break; | |
9c928d16 JB |
1212 | case FBC_MULTIPLE_PIPES: |
1213 | seq_printf(m, "multiple pipes are enabled"); | |
1214 | break; | |
c1a9f047 JB |
1215 | case FBC_MODULE_PARAM: |
1216 | seq_printf(m, "disabled per module param (default off)"); | |
1217 | break; | |
b5e50c3f JB |
1218 | default: |
1219 | seq_printf(m, "unknown reason"); | |
1220 | } | |
1221 | seq_printf(m, "\n"); | |
1222 | } | |
1223 | return 0; | |
1224 | } | |
1225 | ||
4a9bef37 JB |
1226 | static int i915_sr_status(struct seq_file *m, void *unused) |
1227 | { | |
1228 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1229 | struct drm_device *dev = node->minor->dev; | |
1230 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1231 | bool sr_enabled = false; | |
1232 | ||
1398261a | 1233 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1234 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1235 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1236 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1237 | else if (IS_I915GM(dev)) | |
1238 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1239 | else if (IS_PINEVIEW(dev)) | |
1240 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1241 | ||
5ba2aaaa CW |
1242 | seq_printf(m, "self-refresh: %s\n", |
1243 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1244 | |
1245 | return 0; | |
1246 | } | |
1247 | ||
7648fa99 JB |
1248 | static int i915_emon_status(struct seq_file *m, void *unused) |
1249 | { | |
1250 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1251 | struct drm_device *dev = node->minor->dev; | |
1252 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1253 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1254 | int ret; |
1255 | ||
582be6b4 CW |
1256 | if (!IS_GEN5(dev)) |
1257 | return -ENODEV; | |
1258 | ||
de227ef0 CW |
1259 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1260 | if (ret) | |
1261 | return ret; | |
7648fa99 JB |
1262 | |
1263 | temp = i915_mch_val(dev_priv); | |
1264 | chipset = i915_chipset_val(dev_priv); | |
1265 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1266 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1267 | |
1268 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1269 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1270 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1271 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
23b2f8bb JB |
1276 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1277 | { | |
1278 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1279 | struct drm_device *dev = node->minor->dev; | |
1280 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1281 | int ret; | |
1282 | int gpu_freq, ia_freq; | |
1283 | ||
1c70c0ce | 1284 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1285 | seq_printf(m, "unsupported on this chipset\n"); |
1286 | return 0; | |
1287 | } | |
1288 | ||
4fc688ce | 1289 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1290 | if (ret) |
1291 | return ret; | |
1292 | ||
1293 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1294 | ||
c6a828d3 DV |
1295 | for (gpu_freq = dev_priv->rps.min_delay; |
1296 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1297 | gpu_freq++) { |
42c0526c BW |
1298 | ia_freq = gpu_freq; |
1299 | sandybridge_pcode_read(dev_priv, | |
1300 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1301 | &ia_freq); | |
c8735b0c | 1302 | seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100); |
23b2f8bb JB |
1303 | } |
1304 | ||
4fc688ce | 1305 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
7648fa99 JB |
1310 | static int i915_gfxec(struct seq_file *m, void *unused) |
1311 | { | |
1312 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1313 | struct drm_device *dev = node->minor->dev; | |
1314 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1315 | int ret; |
1316 | ||
1317 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1318 | if (ret) | |
1319 | return ret; | |
7648fa99 JB |
1320 | |
1321 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1322 | ||
616fdb5a BW |
1323 | mutex_unlock(&dev->struct_mutex); |
1324 | ||
7648fa99 JB |
1325 | return 0; |
1326 | } | |
1327 | ||
44834a67 CW |
1328 | static int i915_opregion(struct seq_file *m, void *unused) |
1329 | { | |
1330 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1331 | struct drm_device *dev = node->minor->dev; | |
1332 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1333 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1334 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1335 | int ret; |
1336 | ||
0d38f009 DV |
1337 | if (data == NULL) |
1338 | return -ENOMEM; | |
1339 | ||
44834a67 CW |
1340 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1341 | if (ret) | |
0d38f009 | 1342 | goto out; |
44834a67 | 1343 | |
0d38f009 DV |
1344 | if (opregion->header) { |
1345 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1346 | seq_write(m, data, OPREGION_SIZE); | |
1347 | } | |
44834a67 CW |
1348 | |
1349 | mutex_unlock(&dev->struct_mutex); | |
1350 | ||
0d38f009 DV |
1351 | out: |
1352 | kfree(data); | |
44834a67 CW |
1353 | return 0; |
1354 | } | |
1355 | ||
37811fcc CW |
1356 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1357 | { | |
1358 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1359 | struct drm_device *dev = node->minor->dev; | |
1360 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1361 | struct intel_fbdev *ifbdev; | |
1362 | struct intel_framebuffer *fb; | |
1363 | int ret; | |
1364 | ||
1365 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1366 | if (ret) | |
1367 | return ret; | |
1368 | ||
1369 | ifbdev = dev_priv->fbdev; | |
1370 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1371 | ||
1372 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1373 | fb->base.width, | |
1374 | fb->base.height, | |
1375 | fb->base.depth, | |
1376 | fb->base.bits_per_pixel); | |
05394f39 | 1377 | describe_obj(m, fb->obj); |
37811fcc CW |
1378 | seq_printf(m, "\n"); |
1379 | ||
1380 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1381 | if (&fb->base == ifbdev->helper.fb) | |
1382 | continue; | |
1383 | ||
1384 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1385 | fb->base.width, | |
1386 | fb->base.height, | |
1387 | fb->base.depth, | |
1388 | fb->base.bits_per_pixel); | |
05394f39 | 1389 | describe_obj(m, fb->obj); |
37811fcc CW |
1390 | seq_printf(m, "\n"); |
1391 | } | |
1392 | ||
1393 | mutex_unlock(&dev->mode_config.mutex); | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
e76d3630 BW |
1398 | static int i915_context_status(struct seq_file *m, void *unused) |
1399 | { | |
1400 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1401 | struct drm_device *dev = node->minor->dev; | |
1402 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1403 | int ret; | |
1404 | ||
1405 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1406 | if (ret) | |
1407 | return ret; | |
1408 | ||
3e373948 | 1409 | if (dev_priv->ips.pwrctx) { |
dc501fbc | 1410 | seq_printf(m, "power context "); |
3e373948 | 1411 | describe_obj(m, dev_priv->ips.pwrctx); |
dc501fbc BW |
1412 | seq_printf(m, "\n"); |
1413 | } | |
e76d3630 | 1414 | |
3e373948 | 1415 | if (dev_priv->ips.renderctx) { |
dc501fbc | 1416 | seq_printf(m, "render context "); |
3e373948 | 1417 | describe_obj(m, dev_priv->ips.renderctx); |
dc501fbc BW |
1418 | seq_printf(m, "\n"); |
1419 | } | |
e76d3630 BW |
1420 | |
1421 | mutex_unlock(&dev->mode_config.mutex); | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
6d794d42 BW |
1426 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1427 | { | |
1428 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1429 | struct drm_device *dev = node->minor->dev; | |
1430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1431 | unsigned forcewake_count; |
6d794d42 | 1432 | |
9f1f46a4 DV |
1433 | spin_lock_irq(&dev_priv->gt_lock); |
1434 | forcewake_count = dev_priv->forcewake_count; | |
1435 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1436 | |
9f1f46a4 | 1437 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1438 | |
1439 | return 0; | |
1440 | } | |
1441 | ||
ea16a3cd DV |
1442 | static const char *swizzle_string(unsigned swizzle) |
1443 | { | |
1444 | switch(swizzle) { | |
1445 | case I915_BIT_6_SWIZZLE_NONE: | |
1446 | return "none"; | |
1447 | case I915_BIT_6_SWIZZLE_9: | |
1448 | return "bit9"; | |
1449 | case I915_BIT_6_SWIZZLE_9_10: | |
1450 | return "bit9/bit10"; | |
1451 | case I915_BIT_6_SWIZZLE_9_11: | |
1452 | return "bit9/bit11"; | |
1453 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1454 | return "bit9/bit10/bit11"; | |
1455 | case I915_BIT_6_SWIZZLE_9_17: | |
1456 | return "bit9/bit17"; | |
1457 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1458 | return "bit9/bit10/bit17"; | |
1459 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1460 | return "unkown"; | |
1461 | } | |
1462 | ||
1463 | return "bug"; | |
1464 | } | |
1465 | ||
1466 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1467 | { | |
1468 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1469 | struct drm_device *dev = node->minor->dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1471 | int ret; |
1472 | ||
1473 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1474 | if (ret) | |
1475 | return ret; | |
ea16a3cd | 1476 | |
ea16a3cd DV |
1477 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1478 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1479 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1480 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1481 | ||
1482 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1483 | seq_printf(m, "DDC = 0x%08x\n", | |
1484 | I915_READ(DCC)); | |
1485 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1486 | I915_READ16(C0DRB3)); | |
1487 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1488 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1489 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1490 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1491 | I915_READ(MAD_DIMM_C0)); | |
1492 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1493 | I915_READ(MAD_DIMM_C1)); | |
1494 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1495 | I915_READ(MAD_DIMM_C2)); | |
1496 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1497 | I915_READ(TILECTL)); | |
1498 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1499 | I915_READ(ARB_MODE)); | |
1500 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1501 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1502 | } |
1503 | mutex_unlock(&dev->struct_mutex); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
3cf17fc5 DV |
1508 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1509 | { | |
1510 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1511 | struct drm_device *dev = node->minor->dev; | |
1512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1513 | struct intel_ring_buffer *ring; | |
1514 | int i, ret; | |
1515 | ||
1516 | ||
1517 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1518 | if (ret) | |
1519 | return ret; | |
1520 | if (INTEL_INFO(dev)->gen == 6) | |
1521 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1522 | ||
a2c7f6fd | 1523 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1524 | seq_printf(m, "%s\n", ring->name); |
1525 | if (INTEL_INFO(dev)->gen == 7) | |
1526 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1527 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1528 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1529 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1530 | } | |
1531 | if (dev_priv->mm.aliasing_ppgtt) { | |
1532 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1533 | ||
1534 | seq_printf(m, "aliasing PPGTT:\n"); | |
1535 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1536 | } | |
1537 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1538 | mutex_unlock(&dev->struct_mutex); | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
57f350b6 JB |
1543 | static int i915_dpio_info(struct seq_file *m, void *data) |
1544 | { | |
1545 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1546 | struct drm_device *dev = node->minor->dev; | |
1547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1548 | int ret; | |
1549 | ||
1550 | ||
1551 | if (!IS_VALLEYVIEW(dev)) { | |
1552 | seq_printf(m, "unsupported\n"); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1557 | if (ret) | |
1558 | return ret; | |
1559 | ||
1560 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1561 | ||
1562 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1563 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1564 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1565 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1566 | ||
1567 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1568 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1569 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1570 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1571 | ||
1572 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1573 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1574 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1575 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1576 | ||
1577 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1578 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1579 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1580 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1581 | ||
1582 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1583 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1584 | ||
1585 | mutex_unlock(&dev->mode_config.mutex); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | ||
f3cd474b CW |
1590 | static ssize_t |
1591 | i915_wedged_read(struct file *filp, | |
1592 | char __user *ubuf, | |
1593 | size_t max, | |
1594 | loff_t *ppos) | |
1595 | { | |
1596 | struct drm_device *dev = filp->private_data; | |
1597 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1598 | char buf[80]; | |
1599 | int len; | |
1600 | ||
0206e353 | 1601 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1602 | "wedged : %d\n", |
1603 | atomic_read(&dev_priv->mm.wedged)); | |
1604 | ||
0206e353 AJ |
1605 | if (len > sizeof(buf)) |
1606 | len = sizeof(buf); | |
f4433a8d | 1607 | |
f3cd474b CW |
1608 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1609 | } | |
1610 | ||
1611 | static ssize_t | |
1612 | i915_wedged_write(struct file *filp, | |
1613 | const char __user *ubuf, | |
1614 | size_t cnt, | |
1615 | loff_t *ppos) | |
1616 | { | |
1617 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1618 | char buf[20]; |
1619 | int val = 1; | |
1620 | ||
1621 | if (cnt > 0) { | |
0206e353 | 1622 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1623 | return -EINVAL; |
1624 | ||
1625 | if (copy_from_user(buf, ubuf, cnt)) | |
1626 | return -EFAULT; | |
1627 | buf[cnt] = 0; | |
1628 | ||
1629 | val = simple_strtoul(buf, NULL, 0); | |
1630 | } | |
1631 | ||
1632 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1633 | i915_handle_error(dev, val); |
f3cd474b CW |
1634 | |
1635 | return cnt; | |
1636 | } | |
1637 | ||
1638 | static const struct file_operations i915_wedged_fops = { | |
1639 | .owner = THIS_MODULE, | |
234e3405 | 1640 | .open = simple_open, |
f3cd474b CW |
1641 | .read = i915_wedged_read, |
1642 | .write = i915_wedged_write, | |
6038f373 | 1643 | .llseek = default_llseek, |
f3cd474b CW |
1644 | }; |
1645 | ||
e5eb3d63 DV |
1646 | static ssize_t |
1647 | i915_ring_stop_read(struct file *filp, | |
1648 | char __user *ubuf, | |
1649 | size_t max, | |
1650 | loff_t *ppos) | |
1651 | { | |
1652 | struct drm_device *dev = filp->private_data; | |
1653 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1654 | char buf[20]; | |
1655 | int len; | |
1656 | ||
1657 | len = snprintf(buf, sizeof(buf), | |
1658 | "0x%08x\n", dev_priv->stop_rings); | |
1659 | ||
1660 | if (len > sizeof(buf)) | |
1661 | len = sizeof(buf); | |
1662 | ||
1663 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1664 | } | |
1665 | ||
1666 | static ssize_t | |
1667 | i915_ring_stop_write(struct file *filp, | |
1668 | const char __user *ubuf, | |
1669 | size_t cnt, | |
1670 | loff_t *ppos) | |
1671 | { | |
1672 | struct drm_device *dev = filp->private_data; | |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | char buf[20]; | |
22bcfc6a | 1675 | int val = 0, ret; |
e5eb3d63 DV |
1676 | |
1677 | if (cnt > 0) { | |
1678 | if (cnt > sizeof(buf) - 1) | |
1679 | return -EINVAL; | |
1680 | ||
1681 | if (copy_from_user(buf, ubuf, cnt)) | |
1682 | return -EFAULT; | |
1683 | buf[cnt] = 0; | |
1684 | ||
1685 | val = simple_strtoul(buf, NULL, 0); | |
1686 | } | |
1687 | ||
1688 | DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val); | |
1689 | ||
22bcfc6a DV |
1690 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1691 | if (ret) | |
1692 | return ret; | |
1693 | ||
e5eb3d63 DV |
1694 | dev_priv->stop_rings = val; |
1695 | mutex_unlock(&dev->struct_mutex); | |
1696 | ||
1697 | return cnt; | |
1698 | } | |
1699 | ||
1700 | static const struct file_operations i915_ring_stop_fops = { | |
1701 | .owner = THIS_MODULE, | |
1702 | .open = simple_open, | |
1703 | .read = i915_ring_stop_read, | |
1704 | .write = i915_ring_stop_write, | |
1705 | .llseek = default_llseek, | |
1706 | }; | |
d5442303 | 1707 | |
358733e9 JB |
1708 | static ssize_t |
1709 | i915_max_freq_read(struct file *filp, | |
1710 | char __user *ubuf, | |
1711 | size_t max, | |
1712 | loff_t *ppos) | |
1713 | { | |
1714 | struct drm_device *dev = filp->private_data; | |
1715 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1716 | char buf[80]; | |
004777cb DV |
1717 | int len, ret; |
1718 | ||
1719 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1720 | return -ENODEV; | |
1721 | ||
4fc688ce | 1722 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1723 | if (ret) |
1724 | return ret; | |
358733e9 | 1725 | |
0206e353 | 1726 | len = snprintf(buf, sizeof(buf), |
c8735b0c | 1727 | "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1728 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1729 | |
0206e353 AJ |
1730 | if (len > sizeof(buf)) |
1731 | len = sizeof(buf); | |
358733e9 JB |
1732 | |
1733 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1734 | } | |
1735 | ||
1736 | static ssize_t | |
1737 | i915_max_freq_write(struct file *filp, | |
1738 | const char __user *ubuf, | |
1739 | size_t cnt, | |
1740 | loff_t *ppos) | |
1741 | { | |
1742 | struct drm_device *dev = filp->private_data; | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | char buf[20]; | |
004777cb DV |
1745 | int val = 1, ret; |
1746 | ||
1747 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1748 | return -ENODEV; | |
358733e9 JB |
1749 | |
1750 | if (cnt > 0) { | |
0206e353 | 1751 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1752 | return -EINVAL; |
1753 | ||
1754 | if (copy_from_user(buf, ubuf, cnt)) | |
1755 | return -EFAULT; | |
1756 | buf[cnt] = 0; | |
1757 | ||
1758 | val = simple_strtoul(buf, NULL, 0); | |
1759 | } | |
1760 | ||
1761 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1762 | ||
4fc688ce | 1763 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1764 | if (ret) |
1765 | return ret; | |
1766 | ||
358733e9 JB |
1767 | /* |
1768 | * Turbo will still be enabled, but won't go above the set value. | |
1769 | */ | |
c8735b0c | 1770 | dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER; |
358733e9 | 1771 | |
c8735b0c | 1772 | gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1773 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 JB |
1774 | |
1775 | return cnt; | |
1776 | } | |
1777 | ||
1778 | static const struct file_operations i915_max_freq_fops = { | |
1779 | .owner = THIS_MODULE, | |
234e3405 | 1780 | .open = simple_open, |
358733e9 JB |
1781 | .read = i915_max_freq_read, |
1782 | .write = i915_max_freq_write, | |
1783 | .llseek = default_llseek, | |
1784 | }; | |
1785 | ||
1523c310 JB |
1786 | static ssize_t |
1787 | i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max, | |
1788 | loff_t *ppos) | |
1789 | { | |
1790 | struct drm_device *dev = filp->private_data; | |
1791 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1792 | char buf[80]; | |
004777cb DV |
1793 | int len, ret; |
1794 | ||
1795 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1796 | return -ENODEV; | |
1797 | ||
4fc688ce | 1798 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1799 | if (ret) |
1800 | return ret; | |
1523c310 JB |
1801 | |
1802 | len = snprintf(buf, sizeof(buf), | |
c8735b0c | 1803 | "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1804 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 JB |
1805 | |
1806 | if (len > sizeof(buf)) | |
1807 | len = sizeof(buf); | |
1808 | ||
1809 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1810 | } | |
1811 | ||
1812 | static ssize_t | |
1813 | i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt, | |
1814 | loff_t *ppos) | |
1815 | { | |
1816 | struct drm_device *dev = filp->private_data; | |
1817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1818 | char buf[20]; | |
004777cb DV |
1819 | int val = 1, ret; |
1820 | ||
1821 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1822 | return -ENODEV; | |
1523c310 JB |
1823 | |
1824 | if (cnt > 0) { | |
1825 | if (cnt > sizeof(buf) - 1) | |
1826 | return -EINVAL; | |
1827 | ||
1828 | if (copy_from_user(buf, ubuf, cnt)) | |
1829 | return -EFAULT; | |
1830 | buf[cnt] = 0; | |
1831 | ||
1832 | val = simple_strtoul(buf, NULL, 0); | |
1833 | } | |
1834 | ||
1835 | DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val); | |
1836 | ||
4fc688ce | 1837 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1838 | if (ret) |
1839 | return ret; | |
1840 | ||
1523c310 JB |
1841 | /* |
1842 | * Turbo will still be enabled, but won't go below the set value. | |
1843 | */ | |
c8735b0c | 1844 | dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER; |
1523c310 | 1845 | |
c8735b0c | 1846 | gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1847 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 JB |
1848 | |
1849 | return cnt; | |
1850 | } | |
1851 | ||
1852 | static const struct file_operations i915_min_freq_fops = { | |
1853 | .owner = THIS_MODULE, | |
1854 | .open = simple_open, | |
1855 | .read = i915_min_freq_read, | |
1856 | .write = i915_min_freq_write, | |
1857 | .llseek = default_llseek, | |
1858 | }; | |
1859 | ||
07b7ddd9 JB |
1860 | static ssize_t |
1861 | i915_cache_sharing_read(struct file *filp, | |
1862 | char __user *ubuf, | |
1863 | size_t max, | |
1864 | loff_t *ppos) | |
1865 | { | |
1866 | struct drm_device *dev = filp->private_data; | |
1867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1868 | char buf[80]; | |
1869 | u32 snpcr; | |
22bcfc6a | 1870 | int len, ret; |
07b7ddd9 | 1871 | |
004777cb DV |
1872 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1873 | return -ENODEV; | |
1874 | ||
22bcfc6a DV |
1875 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1876 | if (ret) | |
1877 | return ret; | |
1878 | ||
07b7ddd9 JB |
1879 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
1880 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1881 | ||
0206e353 | 1882 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1883 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1884 | GEN6_MBC_SNPCR_SHIFT); | |
1885 | ||
0206e353 AJ |
1886 | if (len > sizeof(buf)) |
1887 | len = sizeof(buf); | |
07b7ddd9 JB |
1888 | |
1889 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1890 | } | |
1891 | ||
1892 | static ssize_t | |
1893 | i915_cache_sharing_write(struct file *filp, | |
1894 | const char __user *ubuf, | |
1895 | size_t cnt, | |
1896 | loff_t *ppos) | |
1897 | { | |
1898 | struct drm_device *dev = filp->private_data; | |
1899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1900 | char buf[20]; | |
1901 | u32 snpcr; | |
1902 | int val = 1; | |
1903 | ||
004777cb DV |
1904 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1905 | return -ENODEV; | |
1906 | ||
07b7ddd9 | 1907 | if (cnt > 0) { |
0206e353 | 1908 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1909 | return -EINVAL; |
1910 | ||
1911 | if (copy_from_user(buf, ubuf, cnt)) | |
1912 | return -EFAULT; | |
1913 | buf[cnt] = 0; | |
1914 | ||
1915 | val = simple_strtoul(buf, NULL, 0); | |
1916 | } | |
1917 | ||
1918 | if (val < 0 || val > 3) | |
1919 | return -EINVAL; | |
1920 | ||
1921 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1922 | ||
1923 | /* Update the cache sharing policy here as well */ | |
1924 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1925 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1926 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1927 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1928 | ||
1929 | return cnt; | |
1930 | } | |
1931 | ||
1932 | static const struct file_operations i915_cache_sharing_fops = { | |
1933 | .owner = THIS_MODULE, | |
234e3405 | 1934 | .open = simple_open, |
07b7ddd9 JB |
1935 | .read = i915_cache_sharing_read, |
1936 | .write = i915_cache_sharing_write, | |
1937 | .llseek = default_llseek, | |
1938 | }; | |
1939 | ||
f3cd474b CW |
1940 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1941 | * allocated we need to hook into the minor for release. */ | |
1942 | static int | |
1943 | drm_add_fake_info_node(struct drm_minor *minor, | |
1944 | struct dentry *ent, | |
1945 | const void *key) | |
1946 | { | |
1947 | struct drm_info_node *node; | |
1948 | ||
1949 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1950 | if (node == NULL) { | |
1951 | debugfs_remove(ent); | |
1952 | return -ENOMEM; | |
1953 | } | |
1954 | ||
1955 | node->minor = minor; | |
1956 | node->dent = ent; | |
1957 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1958 | |
1959 | mutex_lock(&minor->debugfs_lock); | |
1960 | list_add(&node->list, &minor->debugfs_list); | |
1961 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1962 | |
1963 | return 0; | |
1964 | } | |
1965 | ||
6d794d42 BW |
1966 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1967 | { | |
1968 | struct drm_device *dev = inode->i_private; | |
1969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 1970 | |
075edca4 | 1971 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1972 | return 0; |
1973 | ||
6d794d42 | 1974 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
1975 | |
1976 | return 0; | |
1977 | } | |
1978 | ||
c43b5634 | 1979 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
1980 | { |
1981 | struct drm_device *dev = inode->i_private; | |
1982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1983 | ||
075edca4 | 1984 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1985 | return 0; |
1986 | ||
6d794d42 | 1987 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
1988 | |
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | static const struct file_operations i915_forcewake_fops = { | |
1993 | .owner = THIS_MODULE, | |
1994 | .open = i915_forcewake_open, | |
1995 | .release = i915_forcewake_release, | |
1996 | }; | |
1997 | ||
1998 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1999 | { | |
2000 | struct drm_device *dev = minor->dev; | |
2001 | struct dentry *ent; | |
2002 | ||
2003 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2004 | S_IRUSR, |
6d794d42 BW |
2005 | root, dev, |
2006 | &i915_forcewake_fops); | |
2007 | if (IS_ERR(ent)) | |
2008 | return PTR_ERR(ent); | |
2009 | ||
8eb57294 | 2010 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2011 | } |
2012 | ||
6a9c308d DV |
2013 | static int i915_debugfs_create(struct dentry *root, |
2014 | struct drm_minor *minor, | |
2015 | const char *name, | |
2016 | const struct file_operations *fops) | |
07b7ddd9 JB |
2017 | { |
2018 | struct drm_device *dev = minor->dev; | |
2019 | struct dentry *ent; | |
2020 | ||
6a9c308d | 2021 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2022 | S_IRUGO | S_IWUSR, |
2023 | root, dev, | |
6a9c308d | 2024 | fops); |
07b7ddd9 JB |
2025 | if (IS_ERR(ent)) |
2026 | return PTR_ERR(ent); | |
2027 | ||
6a9c308d | 2028 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2029 | } |
2030 | ||
27c202ad | 2031 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2032 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2033 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2034 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2035 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2036 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2037 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 2038 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2039 | {"i915_gem_request", i915_gem_request_info, 0}, |
2040 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2041 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2042 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2043 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2044 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2045 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
f97108d1 JB |
2046 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2047 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2048 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2049 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2050 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2051 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2052 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2053 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2054 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 2055 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2056 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2057 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2058 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2059 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2060 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2061 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2062 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 2063 | }; |
27c202ad | 2064 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2065 | |
27c202ad | 2066 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2067 | { |
f3cd474b CW |
2068 | int ret; |
2069 | ||
6a9c308d DV |
2070 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2071 | "i915_wedged", | |
2072 | &i915_wedged_fops); | |
f3cd474b CW |
2073 | if (ret) |
2074 | return ret; | |
2075 | ||
6d794d42 | 2076 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2077 | if (ret) |
2078 | return ret; | |
6a9c308d DV |
2079 | |
2080 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2081 | "i915_max_freq", | |
2082 | &i915_max_freq_fops); | |
07b7ddd9 JB |
2083 | if (ret) |
2084 | return ret; | |
6a9c308d | 2085 | |
1523c310 JB |
2086 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2087 | "i915_min_freq", | |
2088 | &i915_min_freq_fops); | |
2089 | if (ret) | |
2090 | return ret; | |
2091 | ||
6a9c308d DV |
2092 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2093 | "i915_cache_sharing", | |
2094 | &i915_cache_sharing_fops); | |
6d794d42 BW |
2095 | if (ret) |
2096 | return ret; | |
004777cb | 2097 | |
e5eb3d63 DV |
2098 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2099 | "i915_ring_stop", | |
2100 | &i915_ring_stop_fops); | |
2101 | if (ret) | |
2102 | return ret; | |
6d794d42 | 2103 | |
d5442303 DV |
2104 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2105 | "i915_error_state", | |
2106 | &i915_error_state_fops); | |
2107 | if (ret) | |
2108 | return ret; | |
2109 | ||
27c202ad BG |
2110 | return drm_debugfs_create_files(i915_debugfs_list, |
2111 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2112 | minor->debugfs_root, minor); |
2113 | } | |
2114 | ||
27c202ad | 2115 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2116 | { |
27c202ad BG |
2117 | drm_debugfs_remove_files(i915_debugfs_list, |
2118 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2119 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2120 | 1, minor); | |
33db679b KH |
2121 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
2122 | 1, minor); | |
358733e9 JB |
2123 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
2124 | 1, minor); | |
1523c310 JB |
2125 | drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops, |
2126 | 1, minor); | |
07b7ddd9 JB |
2127 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
2128 | 1, minor); | |
e5eb3d63 DV |
2129 | drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, |
2130 | 1, minor); | |
6bd459df DV |
2131 | drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops, |
2132 | 1, minor); | |
2017263e BG |
2133 | } |
2134 | ||
2135 | #endif /* CONFIG_DEBUG_FS */ |