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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
4518f611 | 33 | #include <generated/utsrelease.h> |
760285e7 | 34 | #include <drm/drmP.h> |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
2017263e BG |
38 | #include "i915_drv.h" |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
56 | static int i915_capabilities(struct seq_file *m, void *data) | |
57 | { | |
58 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
59 | struct drm_device *dev = node->minor->dev; | |
60 | const struct intel_device_info *info = INTEL_INFO(dev); | |
61 | ||
62 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 63 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
65 | #define SEP_SEMICOLON ; | |
66 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
67 | #undef PRINT_FLAG | |
68 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
69 | |
70 | return 0; | |
71 | } | |
2017263e | 72 | |
05394f39 | 73 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 74 | { |
05394f39 | 75 | if (obj->user_pin_count > 0) |
a6172a80 | 76 | return "P"; |
05394f39 | 77 | else if (obj->pin_count > 0) |
a6172a80 CW |
78 | return "p"; |
79 | else | |
80 | return " "; | |
81 | } | |
82 | ||
05394f39 | 83 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 84 | { |
0206e353 AJ |
85 | switch (obj->tiling_mode) { |
86 | default: | |
87 | case I915_TILING_NONE: return " "; | |
88 | case I915_TILING_X: return "X"; | |
89 | case I915_TILING_Y: return "Y"; | |
90 | } | |
a6172a80 CW |
91 | } |
92 | ||
93dfb40c | 93 | static const char *cache_level_str(int type) |
08c18323 CW |
94 | { |
95 | switch (type) { | |
93dfb40c CW |
96 | case I915_CACHE_NONE: return " uncached"; |
97 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
98 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
99 | default: return ""; |
100 | } | |
101 | } | |
102 | ||
37811fcc CW |
103 | static void |
104 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
105 | { | |
2563a452 | 106 | seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
37811fcc CW |
107 | &obj->base, |
108 | get_pin_flag(obj), | |
109 | get_tiling_flag(obj), | |
a05a5862 | 110 | obj->base.size / 1024, |
37811fcc CW |
111 | obj->base.read_domains, |
112 | obj->base.write_domain, | |
0201f1ec CW |
113 | obj->last_read_seqno, |
114 | obj->last_write_seqno, | |
caea7476 | 115 | obj->last_fenced_seqno, |
93dfb40c | 116 | cache_level_str(obj->cache_level), |
37811fcc CW |
117 | obj->dirty ? " dirty" : "", |
118 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
119 | if (obj->base.name) | |
120 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
121 | if (obj->pin_count) |
122 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
124 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
125 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
126 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
127 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
c1ad11fc CW |
128 | if (obj->stolen) |
129 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
130 | if (obj->pin_mappable || obj->fault_mappable) { |
131 | char s[3], *t = s; | |
132 | if (obj->pin_mappable) | |
133 | *t++ = 'p'; | |
134 | if (obj->fault_mappable) | |
135 | *t++ = 'f'; | |
136 | *t = '\0'; | |
137 | seq_printf(m, " (%s mappable)", s); | |
138 | } | |
69dc4987 CW |
139 | if (obj->ring != NULL) |
140 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
141 | } |
142 | ||
433e12f7 | 143 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
144 | { |
145 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
146 | uintptr_t list = (uintptr_t) node->info_ent->data; |
147 | struct list_head *head; | |
2017263e BG |
148 | struct drm_device *dev = node->minor->dev; |
149 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 150 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
151 | size_t total_obj_size, total_gtt_size; |
152 | int count, ret; | |
de227ef0 CW |
153 | |
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
2017263e | 157 | |
433e12f7 BG |
158 | switch (list) { |
159 | case ACTIVE_LIST: | |
267f0c90 | 160 | seq_puts(m, "Active:\n"); |
69dc4987 | 161 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
162 | break; |
163 | case INACTIVE_LIST: | |
267f0c90 | 164 | seq_puts(m, "Inactive:\n"); |
433e12f7 BG |
165 | head = &dev_priv->mm.inactive_list; |
166 | break; | |
433e12f7 | 167 | default: |
de227ef0 CW |
168 | mutex_unlock(&dev->struct_mutex); |
169 | return -EINVAL; | |
2017263e | 170 | } |
2017263e | 171 | |
8f2480fb | 172 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 173 | list_for_each_entry(obj, head, mm_list) { |
267f0c90 | 174 | seq_puts(m, " "); |
05394f39 | 175 | describe_obj(m, obj); |
267f0c90 | 176 | seq_putc(m, '\n'); |
05394f39 CW |
177 | total_obj_size += obj->base.size; |
178 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 179 | count++; |
2017263e | 180 | } |
de227ef0 | 181 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 182 | |
8f2480fb CW |
183 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
184 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
185 | return 0; |
186 | } | |
187 | ||
6299f992 CW |
188 | #define count_objects(list, member) do { \ |
189 | list_for_each_entry(obj, list, member) { \ | |
190 | size += obj->gtt_space->size; \ | |
191 | ++count; \ | |
192 | if (obj->map_and_fenceable) { \ | |
193 | mappable_size += obj->gtt_space->size; \ | |
194 | ++mappable_count; \ | |
195 | } \ | |
196 | } \ | |
0206e353 | 197 | } while (0) |
6299f992 | 198 | |
2db8e9d6 CW |
199 | struct file_stats { |
200 | int count; | |
201 | size_t total, active, inactive, unbound; | |
202 | }; | |
203 | ||
204 | static int per_file_stats(int id, void *ptr, void *data) | |
205 | { | |
206 | struct drm_i915_gem_object *obj = ptr; | |
207 | struct file_stats *stats = data; | |
208 | ||
209 | stats->count++; | |
210 | stats->total += obj->base.size; | |
211 | ||
212 | if (obj->gtt_space) { | |
213 | if (!list_empty(&obj->ring_list)) | |
214 | stats->active += obj->base.size; | |
215 | else | |
216 | stats->inactive += obj->base.size; | |
217 | } else { | |
218 | if (!list_empty(&obj->global_list)) | |
219 | stats->unbound += obj->base.size; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
73aa808f CW |
225 | static int i915_gem_object_info(struct seq_file *m, void* data) |
226 | { | |
227 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
228 | struct drm_device *dev = node->minor->dev; | |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
230 | u32 count, mappable_count, purgeable_count; |
231 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 232 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 233 | struct drm_file *file; |
73aa808f CW |
234 | int ret; |
235 | ||
236 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
6299f992 CW |
240 | seq_printf(m, "%u objects, %zu bytes\n", |
241 | dev_priv->mm.object_count, | |
242 | dev_priv->mm.object_memory); | |
243 | ||
244 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 245 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
246 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
247 | count, mappable_count, size, mappable_size); | |
248 | ||
249 | size = count = mappable_size = mappable_count = 0; | |
250 | count_objects(&dev_priv->mm.active_list, mm_list); | |
6299f992 CW |
251 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
252 | count, mappable_count, size, mappable_size); | |
253 | ||
6299f992 CW |
254 | size = count = mappable_size = mappable_count = 0; |
255 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
256 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
257 | count, mappable_count, size, mappable_size); | |
258 | ||
b7abb714 | 259 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 260 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 261 | size += obj->base.size, ++count; |
b7abb714 CW |
262 | if (obj->madv == I915_MADV_DONTNEED) |
263 | purgeable_size += obj->base.size, ++purgeable_count; | |
264 | } | |
6c085a72 CW |
265 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
266 | ||
6299f992 | 267 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 268 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 CW |
269 | if (obj->fault_mappable) { |
270 | size += obj->gtt_space->size; | |
271 | ++count; | |
272 | } | |
273 | if (obj->pin_mappable) { | |
274 | mappable_size += obj->gtt_space->size; | |
275 | ++mappable_count; | |
276 | } | |
b7abb714 CW |
277 | if (obj->madv == I915_MADV_DONTNEED) { |
278 | purgeable_size += obj->base.size; | |
279 | ++purgeable_count; | |
280 | } | |
6299f992 | 281 | } |
b7abb714 CW |
282 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
283 | purgeable_count, purgeable_size); | |
6299f992 CW |
284 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
285 | mappable_count, mappable_size); | |
286 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
287 | count, size); | |
288 | ||
93d18799 | 289 | seq_printf(m, "%zu [%lu] gtt total\n", |
5d4545ae BW |
290 | dev_priv->gtt.total, |
291 | dev_priv->gtt.mappable_end - dev_priv->gtt.start); | |
73aa808f | 292 | |
267f0c90 | 293 | seq_putc(m, '\n'); |
2db8e9d6 CW |
294 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
295 | struct file_stats stats; | |
296 | ||
297 | memset(&stats, 0, sizeof(stats)); | |
298 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
299 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
300 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
301 | stats.count, | |
302 | stats.total, | |
303 | stats.active, | |
304 | stats.inactive, | |
305 | stats.unbound); | |
306 | } | |
307 | ||
73aa808f CW |
308 | mutex_unlock(&dev->struct_mutex); |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
08c18323 CW |
313 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
314 | { | |
315 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
316 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 317 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
318 | struct drm_i915_private *dev_priv = dev->dev_private; |
319 | struct drm_i915_gem_object *obj; | |
320 | size_t total_obj_size, total_gtt_size; | |
321 | int count, ret; | |
322 | ||
323 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
324 | if (ret) | |
325 | return ret; | |
326 | ||
327 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 328 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
329 | if (list == PINNED_LIST && obj->pin_count == 0) |
330 | continue; | |
331 | ||
267f0c90 | 332 | seq_puts(m, " "); |
08c18323 | 333 | describe_obj(m, obj); |
267f0c90 | 334 | seq_putc(m, '\n'); |
08c18323 CW |
335 | total_obj_size += obj->base.size; |
336 | total_gtt_size += obj->gtt_space->size; | |
337 | count++; | |
338 | } | |
339 | ||
340 | mutex_unlock(&dev->struct_mutex); | |
341 | ||
342 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
343 | count, total_obj_size, total_gtt_size); | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
4e5359cd SF |
348 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
349 | { | |
350 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
351 | struct drm_device *dev = node->minor->dev; | |
352 | unsigned long flags; | |
353 | struct intel_crtc *crtc; | |
354 | ||
355 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
356 | const char pipe = pipe_name(crtc->pipe); |
357 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
358 | struct intel_unpin_work *work; |
359 | ||
360 | spin_lock_irqsave(&dev->event_lock, flags); | |
361 | work = crtc->unpin_work; | |
362 | if (work == NULL) { | |
9db4a9c7 | 363 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
364 | pipe, plane); |
365 | } else { | |
e7d841ca | 366 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 367 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
368 | pipe, plane); |
369 | } else { | |
9db4a9c7 | 370 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
371 | pipe, plane); |
372 | } | |
373 | if (work->enable_stall_check) | |
267f0c90 | 374 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 375 | else |
267f0c90 | 376 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 377 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
378 | |
379 | if (work->old_fb_obj) { | |
05394f39 CW |
380 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
381 | if (obj) | |
382 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
383 | } |
384 | if (work->pending_flip_obj) { | |
05394f39 CW |
385 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
386 | if (obj) | |
387 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
388 | } |
389 | } | |
390 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
2017263e BG |
396 | static int i915_gem_request_info(struct seq_file *m, void *data) |
397 | { | |
398 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
399 | struct drm_device *dev = node->minor->dev; | |
400 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 401 | struct intel_ring_buffer *ring; |
2017263e | 402 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 403 | int ret, count, i; |
de227ef0 CW |
404 | |
405 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
406 | if (ret) | |
407 | return ret; | |
2017263e | 408 | |
c2c347a9 | 409 | count = 0; |
a2c7f6fd CW |
410 | for_each_ring(ring, dev_priv, i) { |
411 | if (list_empty(&ring->request_list)) | |
412 | continue; | |
413 | ||
414 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 415 | list_for_each_entry(gem_request, |
a2c7f6fd | 416 | &ring->request_list, |
c2c347a9 CW |
417 | list) { |
418 | seq_printf(m, " %d @ %d\n", | |
419 | gem_request->seqno, | |
420 | (int) (jiffies - gem_request->emitted_jiffies)); | |
421 | } | |
422 | count++; | |
2017263e | 423 | } |
de227ef0 CW |
424 | mutex_unlock(&dev->struct_mutex); |
425 | ||
c2c347a9 | 426 | if (count == 0) |
267f0c90 | 427 | seq_puts(m, "No requests\n"); |
c2c347a9 | 428 | |
2017263e BG |
429 | return 0; |
430 | } | |
431 | ||
b2223497 CW |
432 | static void i915_ring_seqno_info(struct seq_file *m, |
433 | struct intel_ring_buffer *ring) | |
434 | { | |
435 | if (ring->get_seqno) { | |
43a7b924 | 436 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 437 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
438 | } |
439 | } | |
440 | ||
2017263e BG |
441 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
442 | { | |
443 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
444 | struct drm_device *dev = node->minor->dev; | |
445 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 446 | struct intel_ring_buffer *ring; |
1ec14ad3 | 447 | int ret, i; |
de227ef0 CW |
448 | |
449 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
450 | if (ret) | |
451 | return ret; | |
2017263e | 452 | |
a2c7f6fd CW |
453 | for_each_ring(ring, dev_priv, i) |
454 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
455 | |
456 | mutex_unlock(&dev->struct_mutex); | |
457 | ||
2017263e BG |
458 | return 0; |
459 | } | |
460 | ||
461 | ||
462 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
463 | { | |
464 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
465 | struct drm_device *dev = node->minor->dev; | |
466 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 467 | struct intel_ring_buffer *ring; |
9db4a9c7 | 468 | int ret, i, pipe; |
de227ef0 CW |
469 | |
470 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
471 | if (ret) | |
472 | return ret; | |
2017263e | 473 | |
7e231dbe JB |
474 | if (IS_VALLEYVIEW(dev)) { |
475 | seq_printf(m, "Display IER:\t%08x\n", | |
476 | I915_READ(VLV_IER)); | |
477 | seq_printf(m, "Display IIR:\t%08x\n", | |
478 | I915_READ(VLV_IIR)); | |
479 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
480 | I915_READ(VLV_IIR_RW)); | |
481 | seq_printf(m, "Display IMR:\t%08x\n", | |
482 | I915_READ(VLV_IMR)); | |
483 | for_each_pipe(pipe) | |
484 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
485 | pipe_name(pipe), | |
486 | I915_READ(PIPESTAT(pipe))); | |
487 | ||
488 | seq_printf(m, "Master IER:\t%08x\n", | |
489 | I915_READ(VLV_MASTER_IER)); | |
490 | ||
491 | seq_printf(m, "Render IER:\t%08x\n", | |
492 | I915_READ(GTIER)); | |
493 | seq_printf(m, "Render IIR:\t%08x\n", | |
494 | I915_READ(GTIIR)); | |
495 | seq_printf(m, "Render IMR:\t%08x\n", | |
496 | I915_READ(GTIMR)); | |
497 | ||
498 | seq_printf(m, "PM IER:\t\t%08x\n", | |
499 | I915_READ(GEN6_PMIER)); | |
500 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
501 | I915_READ(GEN6_PMIIR)); | |
502 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
503 | I915_READ(GEN6_PMIMR)); | |
504 | ||
505 | seq_printf(m, "Port hotplug:\t%08x\n", | |
506 | I915_READ(PORT_HOTPLUG_EN)); | |
507 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
508 | I915_READ(VLV_DPFLIPSTAT)); | |
509 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
510 | I915_READ(DPINVGTT)); | |
511 | ||
512 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
513 | seq_printf(m, "Interrupt enable: %08x\n", |
514 | I915_READ(IER)); | |
515 | seq_printf(m, "Interrupt identity: %08x\n", | |
516 | I915_READ(IIR)); | |
517 | seq_printf(m, "Interrupt mask: %08x\n", | |
518 | I915_READ(IMR)); | |
9db4a9c7 JB |
519 | for_each_pipe(pipe) |
520 | seq_printf(m, "Pipe %c stat: %08x\n", | |
521 | pipe_name(pipe), | |
522 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
523 | } else { |
524 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
525 | I915_READ(DEIER)); | |
526 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
527 | I915_READ(DEIIR)); | |
528 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
529 | I915_READ(DEIMR)); | |
530 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
531 | I915_READ(SDEIER)); | |
532 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
533 | I915_READ(SDEIIR)); | |
534 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
535 | I915_READ(SDEIMR)); | |
536 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
537 | I915_READ(GTIER)); | |
538 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
539 | I915_READ(GTIIR)); | |
540 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
541 | I915_READ(GTIMR)); | |
542 | } | |
2017263e BG |
543 | seq_printf(m, "Interrupts received: %d\n", |
544 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 545 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 546 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
547 | seq_printf(m, |
548 | "Graphics Interrupt mask (%s): %08x\n", | |
549 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 550 | } |
a2c7f6fd | 551 | i915_ring_seqno_info(m, ring); |
9862e600 | 552 | } |
de227ef0 CW |
553 | mutex_unlock(&dev->struct_mutex); |
554 | ||
2017263e BG |
555 | return 0; |
556 | } | |
557 | ||
a6172a80 CW |
558 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
559 | { | |
560 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
561 | struct drm_device *dev = node->minor->dev; | |
562 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
563 | int i, ret; |
564 | ||
565 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
566 | if (ret) | |
567 | return ret; | |
a6172a80 CW |
568 | |
569 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
570 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
571 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 572 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 573 | |
6c085a72 CW |
574 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
575 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 576 | if (obj == NULL) |
267f0c90 | 577 | seq_puts(m, "unused"); |
c2c347a9 | 578 | else |
05394f39 | 579 | describe_obj(m, obj); |
267f0c90 | 580 | seq_putc(m, '\n'); |
a6172a80 CW |
581 | } |
582 | ||
05394f39 | 583 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
584 | return 0; |
585 | } | |
586 | ||
2017263e BG |
587 | static int i915_hws_info(struct seq_file *m, void *data) |
588 | { | |
589 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
590 | struct drm_device *dev = node->minor->dev; | |
591 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 592 | struct intel_ring_buffer *ring; |
1a240d4d | 593 | const u32 *hws; |
4066c0ae CW |
594 | int i; |
595 | ||
1ec14ad3 | 596 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 597 | hws = ring->status_page.page_addr; |
2017263e BG |
598 | if (hws == NULL) |
599 | return 0; | |
600 | ||
601 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
602 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
603 | i * 4, | |
604 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
605 | } | |
606 | return 0; | |
607 | } | |
608 | ||
e5c65260 CW |
609 | static const char *ring_str(int ring) |
610 | { | |
611 | switch (ring) { | |
96154f2f DV |
612 | case RCS: return "render"; |
613 | case VCS: return "bsd"; | |
614 | case BCS: return "blt"; | |
9010ebfd | 615 | case VECS: return "vebox"; |
e5c65260 CW |
616 | default: return ""; |
617 | } | |
618 | } | |
619 | ||
9df30794 CW |
620 | static const char *pin_flag(int pinned) |
621 | { | |
622 | if (pinned > 0) | |
623 | return " P"; | |
624 | else if (pinned < 0) | |
625 | return " p"; | |
626 | else | |
627 | return ""; | |
628 | } | |
629 | ||
630 | static const char *tiling_flag(int tiling) | |
631 | { | |
632 | switch (tiling) { | |
633 | default: | |
634 | case I915_TILING_NONE: return ""; | |
635 | case I915_TILING_X: return " X"; | |
636 | case I915_TILING_Y: return " Y"; | |
637 | } | |
638 | } | |
639 | ||
640 | static const char *dirty_flag(int dirty) | |
641 | { | |
642 | return dirty ? " dirty" : ""; | |
643 | } | |
644 | ||
645 | static const char *purgeable_flag(int purgeable) | |
646 | { | |
647 | return purgeable ? " purgeable" : ""; | |
648 | } | |
649 | ||
baf27f9b | 650 | static bool __i915_error_ok(struct drm_i915_error_state_buf *e) |
edc3d884 | 651 | { |
edc3d884 MK |
652 | |
653 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { | |
654 | e->err = -ENOSPC; | |
baf27f9b | 655 | return false; |
edc3d884 MK |
656 | } |
657 | ||
658 | if (e->bytes == e->size - 1 || e->err) | |
baf27f9b | 659 | return false; |
edc3d884 | 660 | |
baf27f9b CW |
661 | return true; |
662 | } | |
edc3d884 | 663 | |
baf27f9b CW |
664 | static bool __i915_error_seek(struct drm_i915_error_state_buf *e, |
665 | unsigned len) | |
666 | { | |
667 | if (e->pos + len <= e->start) { | |
668 | e->pos += len; | |
669 | return false; | |
edc3d884 MK |
670 | } |
671 | ||
baf27f9b CW |
672 | /* First vsnprintf needs to fit in its entirety for memmove */ |
673 | if (len >= e->size) { | |
674 | e->err = -EIO; | |
675 | return false; | |
676 | } | |
edc3d884 | 677 | |
baf27f9b CW |
678 | return true; |
679 | } | |
680 | ||
681 | static void __i915_error_advance(struct drm_i915_error_state_buf *e, | |
682 | unsigned len) | |
683 | { | |
edc3d884 MK |
684 | /* If this is first printf in this window, adjust it so that |
685 | * start position matches start of the buffer | |
686 | */ | |
baf27f9b | 687 | |
edc3d884 MK |
688 | if (e->pos < e->start) { |
689 | const size_t off = e->start - e->pos; | |
690 | ||
691 | /* Should not happen but be paranoid */ | |
692 | if (off > len || e->bytes) { | |
693 | e->err = -EIO; | |
694 | return; | |
695 | } | |
696 | ||
697 | memmove(e->buf, e->buf + off, len - off); | |
698 | e->bytes = len - off; | |
699 | e->pos = e->start; | |
700 | return; | |
701 | } | |
702 | ||
703 | e->bytes += len; | |
704 | e->pos += len; | |
705 | } | |
706 | ||
baf27f9b CW |
707 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, |
708 | const char *f, va_list args) | |
709 | { | |
710 | unsigned len; | |
711 | ||
712 | if (!__i915_error_ok(e)) | |
713 | return; | |
714 | ||
715 | /* Seek the first printf which is hits start position */ | |
716 | if (e->pos < e->start) { | |
717 | len = vsnprintf(NULL, 0, f, args); | |
718 | if (!__i915_error_seek(e, len)) | |
719 | return; | |
720 | } | |
721 | ||
722 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); | |
723 | if (len >= e->size - e->bytes) | |
724 | len = e->size - e->bytes - 1; | |
725 | ||
726 | __i915_error_advance(e, len); | |
727 | } | |
728 | ||
729 | static void i915_error_puts(struct drm_i915_error_state_buf *e, | |
730 | const char *str) | |
731 | { | |
732 | unsigned len; | |
733 | ||
734 | if (!__i915_error_ok(e)) | |
735 | return; | |
736 | ||
737 | len = strlen(str); | |
738 | ||
739 | /* Seek the first printf which is hits start position */ | |
740 | if (e->pos < e->start) { | |
741 | if (!__i915_error_seek(e, len)) | |
742 | return; | |
743 | } | |
744 | ||
745 | if (len >= e->size - e->bytes) | |
746 | len = e->size - e->bytes - 1; | |
747 | memcpy(e->buf + e->bytes, str, len); | |
748 | ||
749 | __i915_error_advance(e, len); | |
750 | } | |
751 | ||
edc3d884 MK |
752 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) |
753 | { | |
754 | va_list args; | |
755 | ||
756 | va_start(args, f); | |
757 | i915_error_vprintf(e, f, args); | |
758 | va_end(args); | |
759 | } | |
760 | ||
761 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
baf27f9b | 762 | #define err_puts(e, s) i915_error_puts(e, s) |
edc3d884 MK |
763 | |
764 | static void print_error_buffers(struct drm_i915_error_state_buf *m, | |
c724e8a9 CW |
765 | const char *name, |
766 | struct drm_i915_error_buffer *err, | |
767 | int count) | |
768 | { | |
edc3d884 | 769 | err_printf(m, "%s [%d]:\n", name, count); |
c724e8a9 CW |
770 | |
771 | while (count--) { | |
baf27f9b | 772 | err_printf(m, " %08x %8u %02x %02x %x %x", |
c724e8a9 CW |
773 | err->gtt_offset, |
774 | err->size, | |
775 | err->read_domains, | |
776 | err->write_domain, | |
baf27f9b CW |
777 | err->rseqno, err->wseqno); |
778 | err_puts(m, pin_flag(err->pinned)); | |
779 | err_puts(m, tiling_flag(err->tiling)); | |
780 | err_puts(m, dirty_flag(err->dirty)); | |
781 | err_puts(m, purgeable_flag(err->purgeable)); | |
782 | err_puts(m, err->ring != -1 ? " " : ""); | |
783 | err_puts(m, ring_str(err->ring)); | |
784 | err_puts(m, cache_level_str(err->cache_level)); | |
c724e8a9 CW |
785 | |
786 | if (err->name) | |
edc3d884 | 787 | err_printf(m, " (name: %d)", err->name); |
c724e8a9 | 788 | if (err->fence_reg != I915_FENCE_REG_NONE) |
edc3d884 | 789 | err_printf(m, " (fence: %d)", err->fence_reg); |
c724e8a9 | 790 | |
baf27f9b | 791 | err_puts(m, "\n"); |
c724e8a9 CW |
792 | err++; |
793 | } | |
794 | } | |
795 | ||
edc3d884 | 796 | static void i915_ring_error_state(struct drm_i915_error_state_buf *m, |
d27b1e0e DV |
797 | struct drm_device *dev, |
798 | struct drm_i915_error_state *error, | |
799 | unsigned ring) | |
800 | { | |
ec34a01d | 801 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
edc3d884 MK |
802 | err_printf(m, "%s command stream:\n", ring_str(ring)); |
803 | err_printf(m, " HEAD: 0x%08x\n", error->head[ring]); | |
804 | err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
805 | err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); | |
806 | err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); | |
807 | err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
808 | err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
809 | err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
050ee91f | 810 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) |
edc3d884 | 811 | err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); |
050ee91f | 812 | |
c1cd90ed | 813 | if (INTEL_INFO(dev)->gen >= 4) |
edc3d884 MK |
814 | err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); |
815 | err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
816 | err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); | |
33f3f518 | 817 | if (INTEL_INFO(dev)->gen >= 6) { |
edc3d884 MK |
818 | err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); |
819 | err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); | |
820 | err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", | |
df2b23d9 CW |
821 | error->semaphore_mboxes[ring][0], |
822 | error->semaphore_seqno[ring][0]); | |
edc3d884 | 823 | err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", |
df2b23d9 CW |
824 | error->semaphore_mboxes[ring][1], |
825 | error->semaphore_seqno[ring][1]); | |
33f3f518 | 826 | } |
edc3d884 MK |
827 | err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
828 | err_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); | |
829 | err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); | |
830 | err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
831 | } |
832 | ||
d5442303 DV |
833 | struct i915_error_state_file_priv { |
834 | struct drm_device *dev; | |
835 | struct drm_i915_error_state *error; | |
836 | }; | |
837 | ||
edc3d884 MK |
838 | |
839 | static int i915_error_state(struct i915_error_state_file_priv *error_priv, | |
840 | struct drm_i915_error_state_buf *m) | |
841 | ||
63eeaf38 | 842 | { |
d5442303 | 843 | struct drm_device *dev = error_priv->dev; |
63eeaf38 | 844 | drm_i915_private_t *dev_priv = dev->dev_private; |
d5442303 | 845 | struct drm_i915_error_state *error = error_priv->error; |
b4519513 | 846 | struct intel_ring_buffer *ring; |
52d39a21 | 847 | int i, j, page, offset, elt; |
63eeaf38 | 848 | |
742cbee8 | 849 | if (!error) { |
edc3d884 | 850 | err_printf(m, "no error state collected\n"); |
742cbee8 | 851 | return 0; |
63eeaf38 JB |
852 | } |
853 | ||
edc3d884 | 854 | err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
8a905236 | 855 | error->time.tv_usec); |
edc3d884 MK |
856 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); |
857 | err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); | |
858 | err_printf(m, "EIR: 0x%08x\n", error->eir); | |
859 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
860 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
861 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
862 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
863 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
9df30794 | 864 | |
bf3301ab | 865 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
edc3d884 | 866 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
748ebc60 | 867 | |
050ee91f | 868 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) |
edc3d884 MK |
869 | err_printf(m, " INSTDONE_%d: 0x%08x\n", i, |
870 | error->extra_instdone[i]); | |
050ee91f | 871 | |
33f3f518 | 872 | if (INTEL_INFO(dev)->gen >= 6) { |
edc3d884 MK |
873 | err_printf(m, "ERROR: 0x%08x\n", error->error); |
874 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); | |
33f3f518 | 875 | } |
d27b1e0e | 876 | |
71e172e8 | 877 | if (INTEL_INFO(dev)->gen == 7) |
edc3d884 | 878 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); |
71e172e8 | 879 | |
b4519513 CW |
880 | for_each_ring(ring, dev_priv, i) |
881 | i915_ring_error_state(m, dev, error, i); | |
d27b1e0e | 882 | |
c724e8a9 CW |
883 | if (error->active_bo) |
884 | print_error_buffers(m, "Active", | |
885 | error->active_bo, | |
886 | error->active_bo_count); | |
887 | ||
888 | if (error->pinned_bo) | |
889 | print_error_buffers(m, "Pinned", | |
890 | error->pinned_bo, | |
891 | error->pinned_bo_count); | |
9df30794 | 892 | |
52d39a21 CW |
893 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
894 | struct drm_i915_error_object *obj; | |
9df30794 | 895 | |
52d39a21 | 896 | if ((obj = error->ring[i].batchbuffer)) { |
edc3d884 | 897 | err_printf(m, "%s --- gtt_offset = 0x%08x\n", |
bcfb2e28 CW |
898 | dev_priv->ring[i].name, |
899 | obj->gtt_offset); | |
9df30794 CW |
900 | offset = 0; |
901 | for (page = 0; page < obj->page_count; page++) { | |
902 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
edc3d884 MK |
903 | err_printf(m, "%08x : %08x\n", offset, |
904 | obj->pages[page][elt]); | |
9df30794 CW |
905 | offset += 4; |
906 | } | |
907 | } | |
908 | } | |
9df30794 | 909 | |
52d39a21 | 910 | if (error->ring[i].num_requests) { |
edc3d884 | 911 | err_printf(m, "%s --- %d requests\n", |
52d39a21 CW |
912 | dev_priv->ring[i].name, |
913 | error->ring[i].num_requests); | |
914 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
edc3d884 | 915 | err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 916 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
917 | error->ring[i].requests[j].jiffies, |
918 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
919 | } |
920 | } | |
921 | ||
922 | if ((obj = error->ring[i].ringbuffer)) { | |
edc3d884 | 923 | err_printf(m, "%s --- ringbuffer = 0x%08x\n", |
e2f973d5 CW |
924 | dev_priv->ring[i].name, |
925 | obj->gtt_offset); | |
926 | offset = 0; | |
927 | for (page = 0; page < obj->page_count; page++) { | |
928 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
edc3d884 | 929 | err_printf(m, "%08x : %08x\n", |
e2f973d5 CW |
930 | offset, |
931 | obj->pages[page][elt]); | |
932 | offset += 4; | |
933 | } | |
9df30794 CW |
934 | } |
935 | } | |
8c123e54 BW |
936 | |
937 | obj = error->ring[i].ctx; | |
938 | if (obj) { | |
edc3d884 | 939 | err_printf(m, "%s --- HW Context = 0x%08x\n", |
8c123e54 BW |
940 | dev_priv->ring[i].name, |
941 | obj->gtt_offset); | |
942 | offset = 0; | |
943 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
edc3d884 | 944 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", |
8c123e54 BW |
945 | offset, |
946 | obj->pages[0][elt], | |
947 | obj->pages[0][elt+1], | |
948 | obj->pages[0][elt+2], | |
949 | obj->pages[0][elt+3]); | |
950 | offset += 16; | |
951 | } | |
952 | } | |
9df30794 | 953 | } |
63eeaf38 | 954 | |
6ef3d427 CW |
955 | if (error->overlay) |
956 | intel_overlay_print_error_state(m, error->overlay); | |
957 | ||
c4a1d9e4 CW |
958 | if (error->display) |
959 | intel_display_print_error_state(m, dev, error->display); | |
960 | ||
63eeaf38 JB |
961 | return 0; |
962 | } | |
6911a9b8 | 963 | |
d5442303 DV |
964 | static ssize_t |
965 | i915_error_state_write(struct file *filp, | |
966 | const char __user *ubuf, | |
967 | size_t cnt, | |
968 | loff_t *ppos) | |
969 | { | |
edc3d884 | 970 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 971 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 972 | int ret; |
d5442303 DV |
973 | |
974 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
975 | ||
22bcfc6a DV |
976 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
977 | if (ret) | |
978 | return ret; | |
979 | ||
d5442303 DV |
980 | i915_destroy_error_state(dev); |
981 | mutex_unlock(&dev->struct_mutex); | |
982 | ||
983 | return cnt; | |
984 | } | |
985 | ||
986 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
987 | { | |
988 | struct drm_device *dev = inode->i_private; | |
989 | drm_i915_private_t *dev_priv = dev->dev_private; | |
990 | struct i915_error_state_file_priv *error_priv; | |
991 | unsigned long flags; | |
992 | ||
993 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
994 | if (!error_priv) | |
995 | return -ENOMEM; | |
996 | ||
997 | error_priv->dev = dev; | |
998 | ||
99584db3 DV |
999 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1000 | error_priv->error = dev_priv->gpu_error.first_error; | |
d5442303 DV |
1001 | if (error_priv->error) |
1002 | kref_get(&error_priv->error->ref); | |
99584db3 | 1003 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
d5442303 | 1004 | |
edc3d884 MK |
1005 | file->private_data = error_priv; |
1006 | ||
1007 | return 0; | |
d5442303 DV |
1008 | } |
1009 | ||
1010 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1011 | { | |
edc3d884 | 1012 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 DV |
1013 | |
1014 | if (error_priv->error) | |
1015 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
1016 | kfree(error_priv); | |
1017 | ||
edc3d884 MK |
1018 | return 0; |
1019 | } | |
1020 | ||
1021 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, | |
1022 | size_t count, loff_t *pos) | |
1023 | { | |
1024 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1025 | struct drm_i915_error_state_buf error_str; | |
1026 | loff_t tmp_pos = 0; | |
1027 | ssize_t ret_count = 0; | |
1028 | int ret = 0; | |
1029 | ||
1030 | memset(&error_str, 0, sizeof(error_str)); | |
1031 | ||
1032 | /* We need to have enough room to store any i915_error_state printf | |
1033 | * so that we can move it to start position. | |
1034 | */ | |
1035 | error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; | |
1036 | error_str.buf = kmalloc(error_str.size, | |
1037 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); | |
1038 | ||
1039 | if (error_str.buf == NULL) { | |
1040 | error_str.size = PAGE_SIZE; | |
1041 | error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY); | |
1042 | } | |
1043 | ||
1044 | if (error_str.buf == NULL) { | |
1045 | error_str.size = 128; | |
1046 | error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY); | |
1047 | } | |
1048 | ||
1049 | if (error_str.buf == NULL) | |
1050 | return -ENOMEM; | |
1051 | ||
1052 | error_str.start = *pos; | |
1053 | ||
1054 | ret = i915_error_state(error_priv, &error_str); | |
1055 | if (ret) | |
1056 | goto out; | |
1057 | ||
1058 | if (error_str.bytes == 0 && error_str.err) { | |
1059 | ret = error_str.err; | |
1060 | goto out; | |
1061 | } | |
1062 | ||
1063 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, | |
1064 | error_str.buf, | |
1065 | error_str.bytes); | |
1066 | ||
1067 | if (ret_count < 0) | |
1068 | ret = ret_count; | |
1069 | else | |
1070 | *pos = error_str.start + ret_count; | |
1071 | out: | |
1072 | kfree(error_str.buf); | |
1073 | return ret ?: ret_count; | |
d5442303 DV |
1074 | } |
1075 | ||
1076 | static const struct file_operations i915_error_state_fops = { | |
1077 | .owner = THIS_MODULE, | |
1078 | .open = i915_error_state_open, | |
edc3d884 | 1079 | .read = i915_error_state_read, |
d5442303 DV |
1080 | .write = i915_error_state_write, |
1081 | .llseek = default_llseek, | |
1082 | .release = i915_error_state_release, | |
1083 | }; | |
1084 | ||
647416f9 KC |
1085 | static int |
1086 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1087 | { |
647416f9 | 1088 | struct drm_device *dev = data; |
40633219 | 1089 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
1090 | int ret; |
1091 | ||
1092 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | ||
647416f9 | 1096 | *val = dev_priv->next_seqno; |
40633219 MK |
1097 | mutex_unlock(&dev->struct_mutex); |
1098 | ||
647416f9 | 1099 | return 0; |
40633219 MK |
1100 | } |
1101 | ||
647416f9 KC |
1102 | static int |
1103 | i915_next_seqno_set(void *data, u64 val) | |
1104 | { | |
1105 | struct drm_device *dev = data; | |
40633219 MK |
1106 | int ret; |
1107 | ||
40633219 MK |
1108 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1109 | if (ret) | |
1110 | return ret; | |
1111 | ||
e94fbaa8 | 1112 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1113 | mutex_unlock(&dev->struct_mutex); |
1114 | ||
647416f9 | 1115 | return ret; |
40633219 MK |
1116 | } |
1117 | ||
647416f9 KC |
1118 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1119 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1120 | "0x%llx\n"); |
40633219 | 1121 | |
f97108d1 JB |
1122 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
1123 | { | |
1124 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1125 | struct drm_device *dev = node->minor->dev; | |
1126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1127 | u16 crstanddelay; |
1128 | int ret; | |
1129 | ||
1130 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1131 | if (ret) | |
1132 | return ret; | |
1133 | ||
1134 | crstanddelay = I915_READ16(CRSTANDVID); | |
1135 | ||
1136 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1137 | |
1138 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
1144 | { | |
1145 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1146 | struct drm_device *dev = node->minor->dev; | |
1147 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 1148 | int ret; |
3b8d8d91 JB |
1149 | |
1150 | if (IS_GEN5(dev)) { | |
1151 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1152 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1153 | ||
1154 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1155 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1156 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1157 | MEMSTAT_VID_SHIFT); | |
1158 | seq_printf(m, "Current P-state: %d\n", | |
1159 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 1160 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
1161 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1162 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1163 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 1164 | u32 rpstat, cagf; |
ccab5c82 JB |
1165 | u32 rpupei, rpcurup, rpprevup; |
1166 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
1167 | int max_freq; |
1168 | ||
1169 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1170 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1171 | if (ret) | |
1172 | return ret; | |
1173 | ||
fcca7926 | 1174 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 1175 | |
ccab5c82 JB |
1176 | rpstat = I915_READ(GEN6_RPSTAT1); |
1177 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1178 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1179 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1180 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1181 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1182 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
1183 | if (IS_HASWELL(dev)) |
1184 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
1185 | else | |
1186 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1187 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1188 | |
d1ebd816 BW |
1189 | gen6_gt_force_wake_put(dev_priv); |
1190 | mutex_unlock(&dev->struct_mutex); | |
1191 | ||
3b8d8d91 | 1192 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 1193 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
1194 | seq_printf(m, "Render p-state ratio: %d\n", |
1195 | (gt_perf_status & 0xff00) >> 8); | |
1196 | seq_printf(m, "Render p-state VID: %d\n", | |
1197 | gt_perf_status & 0xff); | |
1198 | seq_printf(m, "Render p-state limit: %d\n", | |
1199 | rp_state_limits & 0xff); | |
f82855d3 | 1200 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1201 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1202 | GEN6_CURICONT_MASK); | |
1203 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1204 | GEN6_CURBSYTAVG_MASK); | |
1205 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1206 | GEN6_CURBSYTAVG_MASK); | |
1207 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1208 | GEN6_CURIAVG_MASK); | |
1209 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1210 | GEN6_CURBSYTAVG_MASK); | |
1211 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1212 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1213 | |
1214 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1215 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1216 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1217 | |
1218 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1219 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1220 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1221 | |
1222 | max_freq = rp_state_cap & 0xff; | |
1223 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1224 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1225 | |
1226 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
1227 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
1228 | } else if (IS_VALLEYVIEW(dev)) { |
1229 | u32 freq_sts, val; | |
1230 | ||
259bd5d4 | 1231 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1232 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1233 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1234 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1235 | ||
64936258 | 1236 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
1237 | seq_printf(m, "max GPU freq: %d MHz\n", |
1238 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
1239 | ||
64936258 | 1240 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
1241 | seq_printf(m, "min GPU freq: %d MHz\n", |
1242 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
1243 | ||
1244 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1245 | vlv_gpu_freq(dev_priv->mem_freq, | |
1246 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 1247 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1248 | } else { |
267f0c90 | 1249 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1250 | } |
f97108d1 JB |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1256 | { | |
1257 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1258 | struct drm_device *dev = node->minor->dev; | |
1259 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1260 | u32 delayfreq; | |
616fdb5a BW |
1261 | int ret, i; |
1262 | ||
1263 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1264 | if (ret) | |
1265 | return ret; | |
f97108d1 JB |
1266 | |
1267 | for (i = 0; i < 16; i++) { | |
1268 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1269 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1270 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1271 | } |
1272 | ||
616fdb5a BW |
1273 | mutex_unlock(&dev->struct_mutex); |
1274 | ||
f97108d1 JB |
1275 | return 0; |
1276 | } | |
1277 | ||
1278 | static inline int MAP_TO_MV(int map) | |
1279 | { | |
1280 | return 1250 - (map * 25); | |
1281 | } | |
1282 | ||
1283 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1284 | { | |
1285 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1286 | struct drm_device *dev = node->minor->dev; | |
1287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1288 | u32 inttoext; | |
616fdb5a BW |
1289 | int ret, i; |
1290 | ||
1291 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1292 | if (ret) | |
1293 | return ret; | |
f97108d1 JB |
1294 | |
1295 | for (i = 1; i <= 32; i++) { | |
1296 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1297 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1298 | } | |
1299 | ||
616fdb5a BW |
1300 | mutex_unlock(&dev->struct_mutex); |
1301 | ||
f97108d1 JB |
1302 | return 0; |
1303 | } | |
1304 | ||
4d85529d | 1305 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1306 | { |
1307 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1308 | struct drm_device *dev = node->minor->dev; | |
1309 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1310 | u32 rgvmodectl, rstdbyctl; |
1311 | u16 crstandvid; | |
1312 | int ret; | |
1313 | ||
1314 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
1318 | rgvmodectl = I915_READ(MEMMODECTL); | |
1319 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1320 | crstandvid = I915_READ16(CRSTANDVID); | |
1321 | ||
1322 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1323 | |
1324 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1325 | "yes" : "no"); | |
1326 | seq_printf(m, "Boost freq: %d\n", | |
1327 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1328 | MEMMODE_BOOST_FREQ_SHIFT); | |
1329 | seq_printf(m, "HW control enabled: %s\n", | |
1330 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1331 | seq_printf(m, "SW control enabled: %s\n", | |
1332 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1333 | seq_printf(m, "Gated voltage change: %s\n", | |
1334 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1335 | seq_printf(m, "Starting frequency: P%d\n", | |
1336 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1337 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1338 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1339 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1340 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1341 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1342 | seq_printf(m, "Render standby enabled: %s\n", | |
1343 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1344 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1345 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1346 | case RSX_STATUS_ON: | |
267f0c90 | 1347 | seq_puts(m, "on\n"); |
88271da3 JB |
1348 | break; |
1349 | case RSX_STATUS_RC1: | |
267f0c90 | 1350 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1351 | break; |
1352 | case RSX_STATUS_RC1E: | |
267f0c90 | 1353 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1354 | break; |
1355 | case RSX_STATUS_RS1: | |
267f0c90 | 1356 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1357 | break; |
1358 | case RSX_STATUS_RS2: | |
267f0c90 | 1359 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1360 | break; |
1361 | case RSX_STATUS_RS3: | |
267f0c90 | 1362 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1363 | break; |
1364 | default: | |
267f0c90 | 1365 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1366 | break; |
1367 | } | |
f97108d1 JB |
1368 | |
1369 | return 0; | |
1370 | } | |
1371 | ||
4d85529d BW |
1372 | static int gen6_drpc_info(struct seq_file *m) |
1373 | { | |
1374 | ||
1375 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1376 | struct drm_device *dev = node->minor->dev; | |
1377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1378 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1379 | unsigned forcewake_count; |
4d85529d BW |
1380 | int count=0, ret; |
1381 | ||
1382 | ||
1383 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1384 | if (ret) | |
1385 | return ret; | |
1386 | ||
93b525dc DV |
1387 | spin_lock_irq(&dev_priv->gt_lock); |
1388 | forcewake_count = dev_priv->forcewake_count; | |
1389 | spin_unlock_irq(&dev_priv->gt_lock); | |
1390 | ||
1391 | if (forcewake_count) { | |
267f0c90 DL |
1392 | seq_puts(m, "RC information inaccurate because somebody " |
1393 | "holds a forcewake reference \n"); | |
4d85529d BW |
1394 | } else { |
1395 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1396 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1397 | udelay(10); | |
1398 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1399 | } | |
1400 | ||
1401 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1402 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1403 | ||
1404 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1405 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1406 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1407 | mutex_lock(&dev_priv->rps.hw_lock); |
1408 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1409 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1410 | |
1411 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1412 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1413 | seq_printf(m, "HW control enabled: %s\n", | |
1414 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1415 | seq_printf(m, "SW control enabled: %s\n", | |
1416 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1417 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1418 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1419 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1420 | seq_printf(m, "RC6 Enabled: %s\n", | |
1421 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1422 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1423 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1424 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1425 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1426 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1427 | switch (gt_core_status & GEN6_RCn_MASK) { |
1428 | case GEN6_RC0: | |
1429 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1430 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1431 | else |
267f0c90 | 1432 | seq_puts(m, "on\n"); |
4d85529d BW |
1433 | break; |
1434 | case GEN6_RC3: | |
267f0c90 | 1435 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1436 | break; |
1437 | case GEN6_RC6: | |
267f0c90 | 1438 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1439 | break; |
1440 | case GEN6_RC7: | |
267f0c90 | 1441 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1442 | break; |
1443 | default: | |
267f0c90 | 1444 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1445 | break; |
1446 | } | |
1447 | ||
1448 | seq_printf(m, "Core Power Down: %s\n", | |
1449 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1450 | |
1451 | /* Not exactly sure what this is */ | |
1452 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1453 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1454 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1455 | I915_READ(GEN6_GT_GFX_RC6)); | |
1456 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1457 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1458 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1459 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1460 | ||
ecd8faea BW |
1461 | seq_printf(m, "RC6 voltage: %dmV\n", |
1462 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1463 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1464 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1465 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1466 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1467 | return 0; |
1468 | } | |
1469 | ||
1470 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1471 | { | |
1472 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1473 | struct drm_device *dev = node->minor->dev; | |
1474 | ||
1475 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1476 | return gen6_drpc_info(m); | |
1477 | else | |
1478 | return ironlake_drpc_info(m); | |
1479 | } | |
1480 | ||
b5e50c3f JB |
1481 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1482 | { | |
1483 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1484 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1485 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1486 | |
ee5382ae | 1487 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1488 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1489 | return 0; |
1490 | } | |
1491 | ||
ee5382ae | 1492 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1493 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1494 | } else { |
267f0c90 | 1495 | seq_puts(m, "FBC disabled: "); |
b5e50c3f | 1496 | switch (dev_priv->no_fbc_reason) { |
bed4a673 | 1497 | case FBC_NO_OUTPUT: |
267f0c90 | 1498 | seq_puts(m, "no outputs"); |
bed4a673 | 1499 | break; |
b5e50c3f | 1500 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1501 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1502 | break; |
1503 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1504 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1505 | break; |
1506 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1507 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1508 | break; |
1509 | case FBC_BAD_PLANE: | |
267f0c90 | 1510 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1511 | break; |
1512 | case FBC_NOT_TILED: | |
267f0c90 | 1513 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1514 | break; |
9c928d16 | 1515 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1516 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1517 | break; |
c1a9f047 | 1518 | case FBC_MODULE_PARAM: |
267f0c90 | 1519 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1520 | break; |
8a5729a3 | 1521 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1522 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1523 | break; |
b5e50c3f | 1524 | default: |
267f0c90 | 1525 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1526 | } |
267f0c90 | 1527 | seq_putc(m, '\n'); |
b5e50c3f JB |
1528 | } |
1529 | return 0; | |
1530 | } | |
1531 | ||
92d44621 PZ |
1532 | static int i915_ips_status(struct seq_file *m, void *unused) |
1533 | { | |
1534 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1535 | struct drm_device *dev = node->minor->dev; | |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | ||
f5adf94e | 1538 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1539 | seq_puts(m, "not supported\n"); |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1544 | seq_puts(m, "enabled\n"); | |
1545 | else | |
1546 | seq_puts(m, "disabled\n"); | |
1547 | ||
1548 | return 0; | |
1549 | } | |
1550 | ||
4a9bef37 JB |
1551 | static int i915_sr_status(struct seq_file *m, void *unused) |
1552 | { | |
1553 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1554 | struct drm_device *dev = node->minor->dev; | |
1555 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1556 | bool sr_enabled = false; | |
1557 | ||
1398261a | 1558 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1559 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1560 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1561 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1562 | else if (IS_I915GM(dev)) | |
1563 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1564 | else if (IS_PINEVIEW(dev)) | |
1565 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1566 | ||
5ba2aaaa CW |
1567 | seq_printf(m, "self-refresh: %s\n", |
1568 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1569 | |
1570 | return 0; | |
1571 | } | |
1572 | ||
7648fa99 JB |
1573 | static int i915_emon_status(struct seq_file *m, void *unused) |
1574 | { | |
1575 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1576 | struct drm_device *dev = node->minor->dev; | |
1577 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1578 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1579 | int ret; |
1580 | ||
582be6b4 CW |
1581 | if (!IS_GEN5(dev)) |
1582 | return -ENODEV; | |
1583 | ||
de227ef0 CW |
1584 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1585 | if (ret) | |
1586 | return ret; | |
7648fa99 JB |
1587 | |
1588 | temp = i915_mch_val(dev_priv); | |
1589 | chipset = i915_chipset_val(dev_priv); | |
1590 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1591 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1592 | |
1593 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1594 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1595 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1596 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
23b2f8bb JB |
1601 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1602 | { | |
1603 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1604 | struct drm_device *dev = node->minor->dev; | |
1605 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1606 | int ret; | |
1607 | int gpu_freq, ia_freq; | |
1608 | ||
1c70c0ce | 1609 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1610 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1611 | return 0; |
1612 | } | |
1613 | ||
4fc688ce | 1614 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1615 | if (ret) |
1616 | return ret; | |
1617 | ||
267f0c90 | 1618 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1619 | |
c6a828d3 DV |
1620 | for (gpu_freq = dev_priv->rps.min_delay; |
1621 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1622 | gpu_freq++) { |
42c0526c BW |
1623 | ia_freq = gpu_freq; |
1624 | sandybridge_pcode_read(dev_priv, | |
1625 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1626 | &ia_freq); | |
3ebecd07 CW |
1627 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1628 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1629 | ((ia_freq >> 0) & 0xff) * 100, | |
1630 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1631 | } |
1632 | ||
4fc688ce | 1633 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1634 | |
1635 | return 0; | |
1636 | } | |
1637 | ||
7648fa99 JB |
1638 | static int i915_gfxec(struct seq_file *m, void *unused) |
1639 | { | |
1640 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1641 | struct drm_device *dev = node->minor->dev; | |
1642 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1643 | int ret; |
1644 | ||
1645 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1646 | if (ret) | |
1647 | return ret; | |
7648fa99 JB |
1648 | |
1649 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1650 | ||
616fdb5a BW |
1651 | mutex_unlock(&dev->struct_mutex); |
1652 | ||
7648fa99 JB |
1653 | return 0; |
1654 | } | |
1655 | ||
44834a67 CW |
1656 | static int i915_opregion(struct seq_file *m, void *unused) |
1657 | { | |
1658 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1659 | struct drm_device *dev = node->minor->dev; | |
1660 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1661 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1662 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1663 | int ret; |
1664 | ||
0d38f009 DV |
1665 | if (data == NULL) |
1666 | return -ENOMEM; | |
1667 | ||
44834a67 CW |
1668 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1669 | if (ret) | |
0d38f009 | 1670 | goto out; |
44834a67 | 1671 | |
0d38f009 DV |
1672 | if (opregion->header) { |
1673 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1674 | seq_write(m, data, OPREGION_SIZE); | |
1675 | } | |
44834a67 CW |
1676 | |
1677 | mutex_unlock(&dev->struct_mutex); | |
1678 | ||
0d38f009 DV |
1679 | out: |
1680 | kfree(data); | |
44834a67 CW |
1681 | return 0; |
1682 | } | |
1683 | ||
37811fcc CW |
1684 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1685 | { | |
1686 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1687 | struct drm_device *dev = node->minor->dev; | |
1688 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1689 | struct intel_fbdev *ifbdev; | |
1690 | struct intel_framebuffer *fb; | |
1691 | int ret; | |
1692 | ||
1693 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1694 | if (ret) | |
1695 | return ret; | |
1696 | ||
1697 | ifbdev = dev_priv->fbdev; | |
1698 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1699 | ||
623f9783 | 1700 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1701 | fb->base.width, |
1702 | fb->base.height, | |
1703 | fb->base.depth, | |
623f9783 DV |
1704 | fb->base.bits_per_pixel, |
1705 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1706 | describe_obj(m, fb->obj); |
267f0c90 | 1707 | seq_putc(m, '\n'); |
4b096ac1 | 1708 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1709 | |
4b096ac1 | 1710 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1711 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1712 | if (&fb->base == ifbdev->helper.fb) | |
1713 | continue; | |
1714 | ||
623f9783 | 1715 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1716 | fb->base.width, |
1717 | fb->base.height, | |
1718 | fb->base.depth, | |
623f9783 DV |
1719 | fb->base.bits_per_pixel, |
1720 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1721 | describe_obj(m, fb->obj); |
267f0c90 | 1722 | seq_putc(m, '\n'); |
37811fcc | 1723 | } |
4b096ac1 | 1724 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1725 | |
1726 | return 0; | |
1727 | } | |
1728 | ||
e76d3630 BW |
1729 | static int i915_context_status(struct seq_file *m, void *unused) |
1730 | { | |
1731 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1732 | struct drm_device *dev = node->minor->dev; | |
1733 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1734 | struct intel_ring_buffer *ring; |
1735 | int ret, i; | |
e76d3630 BW |
1736 | |
1737 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1738 | if (ret) | |
1739 | return ret; | |
1740 | ||
3e373948 | 1741 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1742 | seq_puts(m, "power context "); |
3e373948 | 1743 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1744 | seq_putc(m, '\n'); |
dc501fbc | 1745 | } |
e76d3630 | 1746 | |
3e373948 | 1747 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1748 | seq_puts(m, "render context "); |
3e373948 | 1749 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1750 | seq_putc(m, '\n'); |
dc501fbc | 1751 | } |
e76d3630 | 1752 | |
a168c293 BW |
1753 | for_each_ring(ring, dev_priv, i) { |
1754 | if (ring->default_context) { | |
1755 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1756 | describe_obj(m, ring->default_context->obj); | |
267f0c90 | 1757 | seq_putc(m, '\n'); |
a168c293 BW |
1758 | } |
1759 | } | |
1760 | ||
e76d3630 BW |
1761 | mutex_unlock(&dev->mode_config.mutex); |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
6d794d42 BW |
1766 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1767 | { | |
1768 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1769 | struct drm_device *dev = node->minor->dev; | |
1770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1771 | unsigned forcewake_count; |
6d794d42 | 1772 | |
9f1f46a4 DV |
1773 | spin_lock_irq(&dev_priv->gt_lock); |
1774 | forcewake_count = dev_priv->forcewake_count; | |
1775 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1776 | |
9f1f46a4 | 1777 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1778 | |
1779 | return 0; | |
1780 | } | |
1781 | ||
ea16a3cd DV |
1782 | static const char *swizzle_string(unsigned swizzle) |
1783 | { | |
1784 | switch(swizzle) { | |
1785 | case I915_BIT_6_SWIZZLE_NONE: | |
1786 | return "none"; | |
1787 | case I915_BIT_6_SWIZZLE_9: | |
1788 | return "bit9"; | |
1789 | case I915_BIT_6_SWIZZLE_9_10: | |
1790 | return "bit9/bit10"; | |
1791 | case I915_BIT_6_SWIZZLE_9_11: | |
1792 | return "bit9/bit11"; | |
1793 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1794 | return "bit9/bit10/bit11"; | |
1795 | case I915_BIT_6_SWIZZLE_9_17: | |
1796 | return "bit9/bit17"; | |
1797 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1798 | return "bit9/bit10/bit17"; | |
1799 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1800 | return "unknown"; |
ea16a3cd DV |
1801 | } |
1802 | ||
1803 | return "bug"; | |
1804 | } | |
1805 | ||
1806 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1807 | { | |
1808 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1809 | struct drm_device *dev = node->minor->dev; | |
1810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1811 | int ret; |
1812 | ||
1813 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1814 | if (ret) | |
1815 | return ret; | |
ea16a3cd | 1816 | |
ea16a3cd DV |
1817 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1818 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1819 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1820 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1821 | ||
1822 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1823 | seq_printf(m, "DDC = 0x%08x\n", | |
1824 | I915_READ(DCC)); | |
1825 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1826 | I915_READ16(C0DRB3)); | |
1827 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1828 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1829 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1830 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1831 | I915_READ(MAD_DIMM_C0)); | |
1832 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1833 | I915_READ(MAD_DIMM_C1)); | |
1834 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1835 | I915_READ(MAD_DIMM_C2)); | |
1836 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1837 | I915_READ(TILECTL)); | |
1838 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1839 | I915_READ(ARB_MODE)); | |
1840 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1841 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1842 | } |
1843 | mutex_unlock(&dev->struct_mutex); | |
1844 | ||
1845 | return 0; | |
1846 | } | |
1847 | ||
3cf17fc5 DV |
1848 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1849 | { | |
1850 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1851 | struct drm_device *dev = node->minor->dev; | |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1853 | struct intel_ring_buffer *ring; | |
1854 | int i, ret; | |
1855 | ||
1856 | ||
1857 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1858 | if (ret) | |
1859 | return ret; | |
1860 | if (INTEL_INFO(dev)->gen == 6) | |
1861 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1862 | ||
a2c7f6fd | 1863 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1864 | seq_printf(m, "%s\n", ring->name); |
1865 | if (INTEL_INFO(dev)->gen == 7) | |
1866 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1867 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1868 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1869 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1870 | } | |
1871 | if (dev_priv->mm.aliasing_ppgtt) { | |
1872 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1873 | ||
267f0c90 | 1874 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1875 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1876 | } | |
1877 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1878 | mutex_unlock(&dev->struct_mutex); | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
57f350b6 JB |
1883 | static int i915_dpio_info(struct seq_file *m, void *data) |
1884 | { | |
1885 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1886 | struct drm_device *dev = node->minor->dev; | |
1887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1888 | int ret; | |
1889 | ||
1890 | ||
1891 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1892 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1893 | return 0; |
1894 | } | |
1895 | ||
09153000 | 1896 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1897 | if (ret) |
1898 | return ret; | |
1899 | ||
1900 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1901 | ||
1902 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
ae99258f | 1903 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
57f350b6 | 1904 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
ae99258f | 1905 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
57f350b6 JB |
1906 | |
1907 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
ae99258f | 1908 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
57f350b6 | 1909 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
ae99258f | 1910 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
57f350b6 JB |
1911 | |
1912 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
ae99258f | 1913 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
57f350b6 | 1914 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
ae99258f | 1915 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
57f350b6 | 1916 | |
4abb2c39 VS |
1917 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
1918 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); | |
1919 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", | |
1920 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); | |
57f350b6 JB |
1921 | |
1922 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ae99258f | 1923 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1924 | |
09153000 | 1925 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1926 | |
1927 | return 0; | |
1928 | } | |
1929 | ||
647416f9 KC |
1930 | static int |
1931 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1932 | { |
647416f9 | 1933 | struct drm_device *dev = data; |
f3cd474b | 1934 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1935 | |
647416f9 | 1936 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1937 | |
647416f9 | 1938 | return 0; |
f3cd474b CW |
1939 | } |
1940 | ||
647416f9 KC |
1941 | static int |
1942 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1943 | { |
647416f9 | 1944 | struct drm_device *dev = data; |
f3cd474b | 1945 | |
647416f9 | 1946 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1947 | i915_handle_error(dev, val); |
f3cd474b | 1948 | |
647416f9 | 1949 | return 0; |
f3cd474b CW |
1950 | } |
1951 | ||
647416f9 KC |
1952 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1953 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1954 | "%llu\n"); |
f3cd474b | 1955 | |
647416f9 KC |
1956 | static int |
1957 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1958 | { |
647416f9 | 1959 | struct drm_device *dev = data; |
e5eb3d63 | 1960 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1961 | |
647416f9 | 1962 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1963 | |
647416f9 | 1964 | return 0; |
e5eb3d63 DV |
1965 | } |
1966 | ||
647416f9 KC |
1967 | static int |
1968 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1969 | { |
647416f9 | 1970 | struct drm_device *dev = data; |
e5eb3d63 | 1971 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1972 | int ret; |
e5eb3d63 | 1973 | |
647416f9 | 1974 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1975 | |
22bcfc6a DV |
1976 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1977 | if (ret) | |
1978 | return ret; | |
1979 | ||
99584db3 | 1980 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1981 | mutex_unlock(&dev->struct_mutex); |
1982 | ||
647416f9 | 1983 | return 0; |
e5eb3d63 DV |
1984 | } |
1985 | ||
647416f9 KC |
1986 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1987 | i915_ring_stop_get, i915_ring_stop_set, | |
1988 | "0x%08llx\n"); | |
d5442303 | 1989 | |
dd624afd CW |
1990 | #define DROP_UNBOUND 0x1 |
1991 | #define DROP_BOUND 0x2 | |
1992 | #define DROP_RETIRE 0x4 | |
1993 | #define DROP_ACTIVE 0x8 | |
1994 | #define DROP_ALL (DROP_UNBOUND | \ | |
1995 | DROP_BOUND | \ | |
1996 | DROP_RETIRE | \ | |
1997 | DROP_ACTIVE) | |
647416f9 KC |
1998 | static int |
1999 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2000 | { |
647416f9 | 2001 | *val = DROP_ALL; |
dd624afd | 2002 | |
647416f9 | 2003 | return 0; |
dd624afd CW |
2004 | } |
2005 | ||
647416f9 KC |
2006 | static int |
2007 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2008 | { |
647416f9 | 2009 | struct drm_device *dev = data; |
dd624afd CW |
2010 | struct drm_i915_private *dev_priv = dev->dev_private; |
2011 | struct drm_i915_gem_object *obj, *next; | |
647416f9 | 2012 | int ret; |
dd624afd | 2013 | |
647416f9 | 2014 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2015 | |
2016 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2017 | * on ioctls on -EAGAIN. */ | |
2018 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2019 | if (ret) | |
2020 | return ret; | |
2021 | ||
2022 | if (val & DROP_ACTIVE) { | |
2023 | ret = i915_gpu_idle(dev); | |
2024 | if (ret) | |
2025 | goto unlock; | |
2026 | } | |
2027 | ||
2028 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2029 | i915_gem_retire_requests(dev); | |
2030 | ||
2031 | if (val & DROP_BOUND) { | |
2032 | list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list) | |
2033 | if (obj->pin_count == 0) { | |
2034 | ret = i915_gem_object_unbind(obj); | |
2035 | if (ret) | |
2036 | goto unlock; | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2041 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2042 | global_list) | |
dd624afd CW |
2043 | if (obj->pages_pin_count == 0) { |
2044 | ret = i915_gem_object_put_pages(obj); | |
2045 | if (ret) | |
2046 | goto unlock; | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | unlock: | |
2051 | mutex_unlock(&dev->struct_mutex); | |
2052 | ||
647416f9 | 2053 | return ret; |
dd624afd CW |
2054 | } |
2055 | ||
647416f9 KC |
2056 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2057 | i915_drop_caches_get, i915_drop_caches_set, | |
2058 | "0x%08llx\n"); | |
dd624afd | 2059 | |
647416f9 KC |
2060 | static int |
2061 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2062 | { |
647416f9 | 2063 | struct drm_device *dev = data; |
358733e9 | 2064 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2065 | int ret; |
004777cb DV |
2066 | |
2067 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2068 | return -ENODEV; | |
2069 | ||
4fc688ce | 2070 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2071 | if (ret) |
2072 | return ret; | |
358733e9 | 2073 | |
0a073b84 JB |
2074 | if (IS_VALLEYVIEW(dev)) |
2075 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2076 | dev_priv->rps.max_delay); | |
2077 | else | |
2078 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2079 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2080 | |
647416f9 | 2081 | return 0; |
358733e9 JB |
2082 | } |
2083 | ||
647416f9 KC |
2084 | static int |
2085 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2086 | { |
647416f9 | 2087 | struct drm_device *dev = data; |
358733e9 | 2088 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2089 | int ret; |
004777cb DV |
2090 | |
2091 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2092 | return -ENODEV; | |
358733e9 | 2093 | |
647416f9 | 2094 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2095 | |
4fc688ce | 2096 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2097 | if (ret) |
2098 | return ret; | |
2099 | ||
358733e9 JB |
2100 | /* |
2101 | * Turbo will still be enabled, but won't go above the set value. | |
2102 | */ | |
0a073b84 JB |
2103 | if (IS_VALLEYVIEW(dev)) { |
2104 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2105 | dev_priv->rps.max_delay = val; | |
2106 | gen6_set_rps(dev, val); | |
2107 | } else { | |
2108 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2109 | dev_priv->rps.max_delay = val; | |
2110 | gen6_set_rps(dev, val); | |
2111 | } | |
2112 | ||
4fc688ce | 2113 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2114 | |
647416f9 | 2115 | return 0; |
358733e9 JB |
2116 | } |
2117 | ||
647416f9 KC |
2118 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2119 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2120 | "%llu\n"); |
358733e9 | 2121 | |
647416f9 KC |
2122 | static int |
2123 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2124 | { |
647416f9 | 2125 | struct drm_device *dev = data; |
1523c310 | 2126 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2127 | int ret; |
004777cb DV |
2128 | |
2129 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2130 | return -ENODEV; | |
2131 | ||
4fc688ce | 2132 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2133 | if (ret) |
2134 | return ret; | |
1523c310 | 2135 | |
0a073b84 JB |
2136 | if (IS_VALLEYVIEW(dev)) |
2137 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2138 | dev_priv->rps.min_delay); | |
2139 | else | |
2140 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2141 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2142 | |
647416f9 | 2143 | return 0; |
1523c310 JB |
2144 | } |
2145 | ||
647416f9 KC |
2146 | static int |
2147 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2148 | { |
647416f9 | 2149 | struct drm_device *dev = data; |
1523c310 | 2150 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2151 | int ret; |
004777cb DV |
2152 | |
2153 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2154 | return -ENODEV; | |
1523c310 | 2155 | |
647416f9 | 2156 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2157 | |
4fc688ce | 2158 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2159 | if (ret) |
2160 | return ret; | |
2161 | ||
1523c310 JB |
2162 | /* |
2163 | * Turbo will still be enabled, but won't go below the set value. | |
2164 | */ | |
0a073b84 JB |
2165 | if (IS_VALLEYVIEW(dev)) { |
2166 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2167 | dev_priv->rps.min_delay = val; | |
2168 | valleyview_set_rps(dev, val); | |
2169 | } else { | |
2170 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2171 | dev_priv->rps.min_delay = val; | |
2172 | gen6_set_rps(dev, val); | |
2173 | } | |
4fc688ce | 2174 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2175 | |
647416f9 | 2176 | return 0; |
1523c310 JB |
2177 | } |
2178 | ||
647416f9 KC |
2179 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2180 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2181 | "%llu\n"); |
1523c310 | 2182 | |
647416f9 KC |
2183 | static int |
2184 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2185 | { |
647416f9 | 2186 | struct drm_device *dev = data; |
07b7ddd9 | 2187 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2188 | u32 snpcr; |
647416f9 | 2189 | int ret; |
07b7ddd9 | 2190 | |
004777cb DV |
2191 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2192 | return -ENODEV; | |
2193 | ||
22bcfc6a DV |
2194 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2195 | if (ret) | |
2196 | return ret; | |
2197 | ||
07b7ddd9 JB |
2198 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2199 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2200 | ||
647416f9 | 2201 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2202 | |
647416f9 | 2203 | return 0; |
07b7ddd9 JB |
2204 | } |
2205 | ||
647416f9 KC |
2206 | static int |
2207 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2208 | { |
647416f9 | 2209 | struct drm_device *dev = data; |
07b7ddd9 | 2210 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2211 | u32 snpcr; |
07b7ddd9 | 2212 | |
004777cb DV |
2213 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2214 | return -ENODEV; | |
2215 | ||
647416f9 | 2216 | if (val > 3) |
07b7ddd9 JB |
2217 | return -EINVAL; |
2218 | ||
647416f9 | 2219 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2220 | |
2221 | /* Update the cache sharing policy here as well */ | |
2222 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2223 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2224 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2225 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2226 | ||
647416f9 | 2227 | return 0; |
07b7ddd9 JB |
2228 | } |
2229 | ||
647416f9 KC |
2230 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2231 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2232 | "%llu\n"); | |
07b7ddd9 | 2233 | |
f3cd474b CW |
2234 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2235 | * allocated we need to hook into the minor for release. */ | |
2236 | static int | |
2237 | drm_add_fake_info_node(struct drm_minor *minor, | |
2238 | struct dentry *ent, | |
2239 | const void *key) | |
2240 | { | |
2241 | struct drm_info_node *node; | |
2242 | ||
2243 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2244 | if (node == NULL) { | |
2245 | debugfs_remove(ent); | |
2246 | return -ENOMEM; | |
2247 | } | |
2248 | ||
2249 | node->minor = minor; | |
2250 | node->dent = ent; | |
2251 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2252 | |
2253 | mutex_lock(&minor->debugfs_lock); | |
2254 | list_add(&node->list, &minor->debugfs_list); | |
2255 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2256 | |
2257 | return 0; | |
2258 | } | |
2259 | ||
6d794d42 BW |
2260 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2261 | { | |
2262 | struct drm_device *dev = inode->i_private; | |
2263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2264 | |
075edca4 | 2265 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2266 | return 0; |
2267 | ||
6d794d42 | 2268 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2269 | |
2270 | return 0; | |
2271 | } | |
2272 | ||
c43b5634 | 2273 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2274 | { |
2275 | struct drm_device *dev = inode->i_private; | |
2276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2277 | ||
075edca4 | 2278 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2279 | return 0; |
2280 | ||
6d794d42 | 2281 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2282 | |
2283 | return 0; | |
2284 | } | |
2285 | ||
2286 | static const struct file_operations i915_forcewake_fops = { | |
2287 | .owner = THIS_MODULE, | |
2288 | .open = i915_forcewake_open, | |
2289 | .release = i915_forcewake_release, | |
2290 | }; | |
2291 | ||
2292 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2293 | { | |
2294 | struct drm_device *dev = minor->dev; | |
2295 | struct dentry *ent; | |
2296 | ||
2297 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2298 | S_IRUSR, |
6d794d42 BW |
2299 | root, dev, |
2300 | &i915_forcewake_fops); | |
2301 | if (IS_ERR(ent)) | |
2302 | return PTR_ERR(ent); | |
2303 | ||
8eb57294 | 2304 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2305 | } |
2306 | ||
6a9c308d DV |
2307 | static int i915_debugfs_create(struct dentry *root, |
2308 | struct drm_minor *minor, | |
2309 | const char *name, | |
2310 | const struct file_operations *fops) | |
07b7ddd9 JB |
2311 | { |
2312 | struct drm_device *dev = minor->dev; | |
2313 | struct dentry *ent; | |
2314 | ||
6a9c308d | 2315 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2316 | S_IRUGO | S_IWUSR, |
2317 | root, dev, | |
6a9c308d | 2318 | fops); |
07b7ddd9 JB |
2319 | if (IS_ERR(ent)) |
2320 | return PTR_ERR(ent); | |
2321 | ||
6a9c308d | 2322 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2323 | } |
2324 | ||
27c202ad | 2325 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2326 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2327 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2328 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2329 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2330 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2331 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 2332 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2333 | {"i915_gem_request", i915_gem_request_info, 0}, |
2334 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2335 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2336 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2337 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2338 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2339 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2340 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2341 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2342 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2343 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2344 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2345 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2346 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2347 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2348 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2349 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2350 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2351 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2352 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2353 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2354 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2355 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2356 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2357 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2358 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 2359 | }; |
27c202ad | 2360 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2361 | |
27c202ad | 2362 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2363 | { |
f3cd474b CW |
2364 | int ret; |
2365 | ||
6a9c308d DV |
2366 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2367 | "i915_wedged", | |
2368 | &i915_wedged_fops); | |
f3cd474b CW |
2369 | if (ret) |
2370 | return ret; | |
2371 | ||
6d794d42 | 2372 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2373 | if (ret) |
2374 | return ret; | |
6a9c308d DV |
2375 | |
2376 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2377 | "i915_max_freq", | |
2378 | &i915_max_freq_fops); | |
07b7ddd9 JB |
2379 | if (ret) |
2380 | return ret; | |
6a9c308d | 2381 | |
1523c310 JB |
2382 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2383 | "i915_min_freq", | |
2384 | &i915_min_freq_fops); | |
2385 | if (ret) | |
2386 | return ret; | |
2387 | ||
6a9c308d DV |
2388 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2389 | "i915_cache_sharing", | |
2390 | &i915_cache_sharing_fops); | |
6d794d42 BW |
2391 | if (ret) |
2392 | return ret; | |
004777cb | 2393 | |
e5eb3d63 DV |
2394 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2395 | "i915_ring_stop", | |
2396 | &i915_ring_stop_fops); | |
2397 | if (ret) | |
2398 | return ret; | |
6d794d42 | 2399 | |
dd624afd CW |
2400 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2401 | "i915_gem_drop_caches", | |
2402 | &i915_drop_caches_fops); | |
2403 | if (ret) | |
2404 | return ret; | |
2405 | ||
d5442303 DV |
2406 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2407 | "i915_error_state", | |
2408 | &i915_error_state_fops); | |
2409 | if (ret) | |
2410 | return ret; | |
2411 | ||
40633219 MK |
2412 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2413 | "i915_next_seqno", | |
2414 | &i915_next_seqno_fops); | |
2415 | if (ret) | |
2416 | return ret; | |
2417 | ||
27c202ad BG |
2418 | return drm_debugfs_create_files(i915_debugfs_list, |
2419 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2420 | minor->debugfs_root, minor); |
2421 | } | |
2422 | ||
27c202ad | 2423 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2424 | { |
27c202ad BG |
2425 | drm_debugfs_remove_files(i915_debugfs_list, |
2426 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2427 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2428 | 1, minor); | |
33db679b KH |
2429 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
2430 | 1, minor); | |
358733e9 JB |
2431 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
2432 | 1, minor); | |
1523c310 JB |
2433 | drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops, |
2434 | 1, minor); | |
07b7ddd9 JB |
2435 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
2436 | 1, minor); | |
dd624afd CW |
2437 | drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops, |
2438 | 1, minor); | |
e5eb3d63 DV |
2439 | drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, |
2440 | 1, minor); | |
6bd459df DV |
2441 | drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops, |
2442 | 1, minor); | |
40633219 MK |
2443 | drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops, |
2444 | 1, minor); | |
2017263e BG |
2445 | } |
2446 | ||
2447 | #endif /* CONFIG_DEBUG_FS */ |