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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
6d2b8885 | 30 | #include <linux/list_sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
418e3cd8 CW |
38 | static __always_inline void seq_print_param(struct seq_file *m, |
39 | const char *name, | |
40 | const char *type, | |
41 | const void *x) | |
42 | { | |
43 | if (!__builtin_strcmp(type, "bool")) | |
44 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
45 | else if (!__builtin_strcmp(type, "int")) | |
46 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
47 | else if (!__builtin_strcmp(type, "unsigned int")) | |
48 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
49 | else if (!__builtin_strcmp(type, "char *")) |
50 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
51 | else |
52 | BUILD_BUG(); | |
53 | } | |
54 | ||
70d39fe4 CW |
55 | static int i915_capabilities(struct seq_file *m, void *data) |
56 | { | |
36cdd013 DW |
57 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
58 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 59 | |
36cdd013 | 60 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 61 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 63 | |
79fc46df | 64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 66 | #undef PRINT_FLAG |
70d39fe4 | 67 | |
418e3cd8 CW |
68 | kernel_param_lock(THIS_MODULE); |
69 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
70 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
71 | #undef PRINT_PARAM | |
72 | kernel_param_unlock(THIS_MODULE); | |
73 | ||
70d39fe4 CW |
74 | return 0; |
75 | } | |
2017263e | 76 | |
a7363de7 | 77 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 78 | { |
573adb39 | 79 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
80 | } |
81 | ||
a7363de7 | 82 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
83 | { |
84 | return obj->pin_display ? 'p' : ' '; | |
85 | } | |
86 | ||
a7363de7 | 87 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 88 | { |
3e510a8e | 89 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 90 | default: |
be12a86b TU |
91 | case I915_TILING_NONE: return ' '; |
92 | case I915_TILING_X: return 'X'; | |
93 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 94 | } |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 98 | { |
275f039d | 99 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
100 | } |
101 | ||
a7363de7 | 102 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 103 | { |
a4f5ea64 | 104 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
105 | } |
106 | ||
ca1543be TU |
107 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
108 | { | |
109 | u64 size = 0; | |
110 | struct i915_vma *vma; | |
111 | ||
1c7f4bca | 112 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 113 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
114 | size += vma->node.size; |
115 | } | |
116 | ||
117 | return size; | |
118 | } | |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
b4716185 | 123 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 124 | struct intel_engine_cs *engine; |
1d693bcc | 125 | struct i915_vma *vma; |
faf5bf0a | 126 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
127 | int pin_count = 0; |
128 | ||
188c1ab7 CW |
129 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
130 | ||
d07f0e59 | 131 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 132 | &obj->base, |
be12a86b | 133 | get_active_flag(obj), |
37811fcc CW |
134 | get_pin_flag(obj), |
135 | get_tiling_flag(obj), | |
1d693bcc | 136 | get_global_flag(obj), |
be12a86b | 137 | get_pin_mapped_flag(obj), |
a05a5862 | 138 | obj->base.size / 1024, |
37811fcc | 139 | obj->base.read_domains, |
d07f0e59 | 140 | obj->base.write_domain, |
36cdd013 | 141 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
142 | obj->mm.dirty ? " dirty" : "", |
143 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
144 | if (obj->base.name) |
145 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 146 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 147 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 148 | pin_count++; |
ba0635ff DC |
149 | } |
150 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
151 | if (obj->pin_display) |
152 | seq_printf(m, " (display)"); | |
1c7f4bca | 153 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
154 | if (!drm_mm_node_allocated(&vma->node)) |
155 | continue; | |
156 | ||
8d2fdc3f | 157 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 158 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 159 | vma->node.start, vma->node.size); |
21976853 CW |
160 | if (i915_vma_is_ggtt(vma)) { |
161 | switch (vma->ggtt_view.type) { | |
162 | case I915_GGTT_VIEW_NORMAL: | |
163 | seq_puts(m, ", normal"); | |
164 | break; | |
165 | ||
166 | case I915_GGTT_VIEW_PARTIAL: | |
167 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
168 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
169 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
170 | break; |
171 | ||
172 | case I915_GGTT_VIEW_ROTATED: | |
173 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
174 | vma->ggtt_view.rotated.plane[0].width, |
175 | vma->ggtt_view.rotated.plane[0].height, | |
176 | vma->ggtt_view.rotated.plane[0].stride, | |
177 | vma->ggtt_view.rotated.plane[0].offset, | |
178 | vma->ggtt_view.rotated.plane[1].width, | |
179 | vma->ggtt_view.rotated.plane[1].height, | |
180 | vma->ggtt_view.rotated.plane[1].stride, | |
181 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
182 | break; |
183 | ||
184 | default: | |
185 | MISSING_CASE(vma->ggtt_view.type); | |
186 | break; | |
187 | } | |
188 | } | |
49ef5294 CW |
189 | if (vma->fence) |
190 | seq_printf(m, " , fence: %d%s", | |
191 | vma->fence->id, | |
192 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 193 | seq_puts(m, ")"); |
1d693bcc | 194 | } |
c1ad11fc | 195 | if (obj->stolen) |
440fd528 | 196 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 197 | |
d07f0e59 | 198 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
199 | if (engine) |
200 | seq_printf(m, " (%s)", engine->name); | |
201 | ||
faf5bf0a CW |
202 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
203 | if (frontbuffer_bits) | |
204 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
205 | } |
206 | ||
6d2b8885 CW |
207 | static int obj_rank_by_stolen(void *priv, |
208 | struct list_head *A, struct list_head *B) | |
209 | { | |
210 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 211 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 212 | struct drm_i915_gem_object *b = |
b25cb2f8 | 213 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 214 | |
2d05fa16 RV |
215 | if (a->stolen->start < b->stolen->start) |
216 | return -1; | |
217 | if (a->stolen->start > b->stolen->start) | |
218 | return 1; | |
219 | return 0; | |
6d2b8885 CW |
220 | } |
221 | ||
222 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
223 | { | |
36cdd013 DW |
224 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
225 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 226 | struct drm_i915_gem_object *obj; |
c44ef60e | 227 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
228 | LIST_HEAD(stolen); |
229 | int count, ret; | |
230 | ||
231 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
232 | if (ret) | |
233 | return ret; | |
234 | ||
235 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 236 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
237 | if (obj->stolen == NULL) |
238 | continue; | |
239 | ||
b25cb2f8 | 240 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
241 | |
242 | total_obj_size += obj->base.size; | |
ca1543be | 243 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
244 | count++; |
245 | } | |
56cea323 | 246 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
247 | if (obj->stolen == NULL) |
248 | continue; | |
249 | ||
b25cb2f8 | 250 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
251 | |
252 | total_obj_size += obj->base.size; | |
253 | count++; | |
254 | } | |
255 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
256 | seq_puts(m, "Stolen:\n"); | |
257 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 258 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
259 | seq_puts(m, " "); |
260 | describe_obj(m, obj); | |
261 | seq_putc(m, '\n'); | |
b25cb2f8 | 262 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
263 | } |
264 | mutex_unlock(&dev->struct_mutex); | |
265 | ||
c44ef60e | 266 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
267 | count, total_obj_size, total_gtt_size); |
268 | return 0; | |
269 | } | |
270 | ||
2db8e9d6 | 271 | struct file_stats { |
6313c204 | 272 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
273 | unsigned long count; |
274 | u64 total, unbound; | |
275 | u64 global, shared; | |
276 | u64 active, inactive; | |
2db8e9d6 CW |
277 | }; |
278 | ||
279 | static int per_file_stats(int id, void *ptr, void *data) | |
280 | { | |
281 | struct drm_i915_gem_object *obj = ptr; | |
282 | struct file_stats *stats = data; | |
6313c204 | 283 | struct i915_vma *vma; |
2db8e9d6 CW |
284 | |
285 | stats->count++; | |
286 | stats->total += obj->base.size; | |
15717de2 CW |
287 | if (!obj->bind_count) |
288 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
289 | if (obj->base.name || obj->base.dma_buf) |
290 | stats->shared += obj->base.size; | |
291 | ||
894eeecc CW |
292 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
293 | if (!drm_mm_node_allocated(&vma->node)) | |
294 | continue; | |
6313c204 | 295 | |
3272db53 | 296 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
297 | stats->global += vma->node.size; |
298 | } else { | |
299 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 300 | |
2bfa996e | 301 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 302 | continue; |
6313c204 | 303 | } |
894eeecc | 304 | |
b0decaf7 | 305 | if (i915_vma_is_active(vma)) |
894eeecc CW |
306 | stats->active += vma->node.size; |
307 | else | |
308 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
309 | } |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
b0da1b79 CW |
314 | #define print_file_stats(m, name, stats) do { \ |
315 | if (stats.count) \ | |
c44ef60e | 316 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
317 | name, \ |
318 | stats.count, \ | |
319 | stats.total, \ | |
320 | stats.active, \ | |
321 | stats.inactive, \ | |
322 | stats.global, \ | |
323 | stats.shared, \ | |
324 | stats.unbound); \ | |
325 | } while (0) | |
493018dc BV |
326 | |
327 | static void print_batch_pool_stats(struct seq_file *m, | |
328 | struct drm_i915_private *dev_priv) | |
329 | { | |
330 | struct drm_i915_gem_object *obj; | |
331 | struct file_stats stats; | |
e2f80391 | 332 | struct intel_engine_cs *engine; |
3b3f1650 | 333 | enum intel_engine_id id; |
b4ac5afc | 334 | int j; |
493018dc BV |
335 | |
336 | memset(&stats, 0, sizeof(stats)); | |
337 | ||
3b3f1650 | 338 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 339 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 340 | list_for_each_entry(obj, |
e2f80391 | 341 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
342 | batch_pool_link) |
343 | per_file_stats(0, obj, &stats); | |
344 | } | |
06fbca71 | 345 | } |
493018dc | 346 | |
b0da1b79 | 347 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
348 | } |
349 | ||
15da9565 CW |
350 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
351 | { | |
352 | struct i915_gem_context *ctx = ptr; | |
353 | int n; | |
354 | ||
355 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
356 | if (ctx->engine[n].state) | |
bf3783e5 | 357 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 358 | if (ctx->engine[n].ring) |
57e88531 | 359 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
360 | } |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static void print_context_stats(struct seq_file *m, | |
366 | struct drm_i915_private *dev_priv) | |
367 | { | |
36cdd013 | 368 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
369 | struct file_stats stats; |
370 | struct drm_file *file; | |
371 | ||
372 | memset(&stats, 0, sizeof(stats)); | |
373 | ||
36cdd013 | 374 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
375 | if (dev_priv->kernel_context) |
376 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
377 | ||
36cdd013 | 378 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
379 | struct drm_i915_file_private *fpriv = file->driver_priv; |
380 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
381 | } | |
36cdd013 | 382 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
383 | |
384 | print_file_stats(m, "[k]contexts", stats); | |
385 | } | |
386 | ||
36cdd013 | 387 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 388 | { |
36cdd013 DW |
389 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
390 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 391 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
392 | u32 count, mapped_count, purgeable_count, dpy_count; |
393 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 394 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 395 | struct drm_file *file; |
73aa808f CW |
396 | int ret; |
397 | ||
398 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
399 | if (ret) | |
400 | return ret; | |
401 | ||
3ef7f228 | 402 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
403 | dev_priv->mm.object_count, |
404 | dev_priv->mm.object_memory); | |
405 | ||
1544c42e CW |
406 | size = count = 0; |
407 | mapped_size = mapped_count = 0; | |
408 | purgeable_size = purgeable_count = 0; | |
56cea323 | 409 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
410 | size += obj->base.size; |
411 | ++count; | |
412 | ||
a4f5ea64 | 413 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
414 | purgeable_size += obj->base.size; |
415 | ++purgeable_count; | |
416 | } | |
417 | ||
a4f5ea64 | 418 | if (obj->mm.mapping) { |
2bd160a1 CW |
419 | mapped_count++; |
420 | mapped_size += obj->base.size; | |
be19b10d | 421 | } |
b7abb714 | 422 | } |
c44ef60e | 423 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 424 | |
2bd160a1 | 425 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 426 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
427 | size += obj->base.size; |
428 | ++count; | |
429 | ||
30154650 | 430 | if (obj->pin_display) { |
2bd160a1 CW |
431 | dpy_size += obj->base.size; |
432 | ++dpy_count; | |
6299f992 | 433 | } |
2bd160a1 | 434 | |
a4f5ea64 | 435 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
436 | purgeable_size += obj->base.size; |
437 | ++purgeable_count; | |
438 | } | |
2bd160a1 | 439 | |
a4f5ea64 | 440 | if (obj->mm.mapping) { |
2bd160a1 CW |
441 | mapped_count++; |
442 | mapped_size += obj->base.size; | |
be19b10d | 443 | } |
6299f992 | 444 | } |
2bd160a1 CW |
445 | seq_printf(m, "%u bound objects, %llu bytes\n", |
446 | count, size); | |
c44ef60e | 447 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 448 | purgeable_count, purgeable_size); |
2bd160a1 CW |
449 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
450 | mapped_count, mapped_size); | |
451 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
452 | dpy_count, dpy_size); | |
6299f992 | 453 | |
c44ef60e | 454 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 455 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 456 | |
493018dc BV |
457 | seq_putc(m, '\n'); |
458 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
459 | mutex_unlock(&dev->struct_mutex); |
460 | ||
461 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 462 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
463 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
464 | struct file_stats stats; | |
c84455b4 CW |
465 | struct drm_i915_file_private *file_priv = file->driver_priv; |
466 | struct drm_i915_gem_request *request; | |
3ec2f427 | 467 | struct task_struct *task; |
2db8e9d6 CW |
468 | |
469 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 470 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 471 | spin_lock(&file->table_lock); |
2db8e9d6 | 472 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 473 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
474 | /* |
475 | * Although we have a valid reference on file->pid, that does | |
476 | * not guarantee that the task_struct who called get_pid() is | |
477 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
478 | * Therefore, we need to protect this ->comm access using RCU. | |
479 | */ | |
c84455b4 CW |
480 | mutex_lock(&dev->struct_mutex); |
481 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
482 | struct drm_i915_gem_request, | |
c8659efa | 483 | client_link); |
3ec2f427 | 484 | rcu_read_lock(); |
c84455b4 CW |
485 | task = pid_task(request && request->ctx->pid ? |
486 | request->ctx->pid : file->pid, | |
487 | PIDTYPE_PID); | |
493018dc | 488 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 489 | rcu_read_unlock(); |
c84455b4 | 490 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 491 | } |
1d2ac403 | 492 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
493 | |
494 | return 0; | |
495 | } | |
496 | ||
aee56cff | 497 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 498 | { |
9f25d007 | 499 | struct drm_info_node *node = m->private; |
36cdd013 DW |
500 | struct drm_i915_private *dev_priv = node_to_i915(node); |
501 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 502 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 503 | struct drm_i915_gem_object *obj; |
c44ef60e | 504 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
505 | int count, ret; |
506 | ||
507 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 512 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 513 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
514 | continue; |
515 | ||
267f0c90 | 516 | seq_puts(m, " "); |
08c18323 | 517 | describe_obj(m, obj); |
267f0c90 | 518 | seq_putc(m, '\n'); |
08c18323 | 519 | total_obj_size += obj->base.size; |
ca1543be | 520 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
521 | count++; |
522 | } | |
523 | ||
524 | mutex_unlock(&dev->struct_mutex); | |
525 | ||
c44ef60e | 526 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
527 | count, total_obj_size, total_gtt_size); |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
4e5359cd SF |
532 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
533 | { | |
36cdd013 DW |
534 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
535 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 536 | struct intel_crtc *crtc; |
8a270ebf DV |
537 | int ret; |
538 | ||
539 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
540 | if (ret) | |
541 | return ret; | |
4e5359cd | 542 | |
d3fcc808 | 543 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
544 | const char pipe = pipe_name(crtc->pipe); |
545 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 546 | struct intel_flip_work *work; |
4e5359cd | 547 | |
5e2d7afc | 548 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
549 | work = crtc->flip_work; |
550 | if (work == NULL) { | |
9db4a9c7 | 551 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
552 | pipe, plane); |
553 | } else { | |
5a21b665 DV |
554 | u32 pending; |
555 | u32 addr; | |
556 | ||
557 | pending = atomic_read(&work->pending); | |
558 | if (pending) { | |
559 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
560 | pipe, plane); | |
561 | } else { | |
562 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
563 | pipe, plane); | |
564 | } | |
565 | if (work->flip_queued_req) { | |
24327f83 | 566 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 567 | |
312c3c47 | 568 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 569 | engine->name, |
24327f83 | 570 | work->flip_queued_req->global_seqno, |
312c3c47 | 571 | intel_engine_last_submit(engine), |
1b7744e7 | 572 | intel_engine_get_seqno(engine), |
f69a02c9 | 573 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
574 | } else |
575 | seq_printf(m, "Flip not associated with any ring\n"); | |
576 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
577 | work->flip_queued_vblank, | |
578 | work->flip_ready_vblank, | |
579 | intel_crtc_get_vblank_counter(crtc)); | |
580 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
581 | ||
36cdd013 | 582 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
583 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
584 | else | |
585 | addr = I915_READ(DSPADDR(crtc->plane)); | |
586 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
587 | ||
588 | if (work->pending_flip_obj) { | |
589 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
590 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
591 | } |
592 | } | |
5e2d7afc | 593 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
594 | } |
595 | ||
8a270ebf DV |
596 | mutex_unlock(&dev->struct_mutex); |
597 | ||
4e5359cd SF |
598 | return 0; |
599 | } | |
600 | ||
493018dc BV |
601 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
602 | { | |
36cdd013 DW |
603 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
604 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 605 | struct drm_i915_gem_object *obj; |
e2f80391 | 606 | struct intel_engine_cs *engine; |
3b3f1650 | 607 | enum intel_engine_id id; |
8d9d5744 | 608 | int total = 0; |
b4ac5afc | 609 | int ret, j; |
493018dc BV |
610 | |
611 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
612 | if (ret) | |
613 | return ret; | |
614 | ||
3b3f1650 | 615 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 616 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
617 | int count; |
618 | ||
619 | count = 0; | |
620 | list_for_each_entry(obj, | |
e2f80391 | 621 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
622 | batch_pool_link) |
623 | count++; | |
624 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 625 | engine->name, j, count); |
8d9d5744 CW |
626 | |
627 | list_for_each_entry(obj, | |
e2f80391 | 628 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
629 | batch_pool_link) { |
630 | seq_puts(m, " "); | |
631 | describe_obj(m, obj); | |
632 | seq_putc(m, '\n'); | |
633 | } | |
634 | ||
635 | total += count; | |
06fbca71 | 636 | } |
493018dc BV |
637 | } |
638 | ||
8d9d5744 | 639 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
640 | |
641 | mutex_unlock(&dev->struct_mutex); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
1b36595f CW |
646 | static void print_request(struct seq_file *m, |
647 | struct drm_i915_gem_request *rq, | |
648 | const char *prefix) | |
649 | { | |
20311bd3 | 650 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 651 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 652 | rq->priotree.priority, |
1b36595f | 653 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 654 | rq->timeline->common->name); |
1b36595f CW |
655 | } |
656 | ||
2017263e BG |
657 | static int i915_gem_request_info(struct seq_file *m, void *data) |
658 | { | |
36cdd013 DW |
659 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
660 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 661 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
662 | struct intel_engine_cs *engine; |
663 | enum intel_engine_id id; | |
b4ac5afc | 664 | int ret, any; |
de227ef0 CW |
665 | |
666 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
667 | if (ret) | |
668 | return ret; | |
2017263e | 669 | |
2d1070b2 | 670 | any = 0; |
3b3f1650 | 671 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
672 | int count; |
673 | ||
674 | count = 0; | |
73cb9701 | 675 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
676 | count++; |
677 | if (count == 0) | |
a2c7f6fd CW |
678 | continue; |
679 | ||
e2f80391 | 680 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 681 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 682 | print_request(m, req, " "); |
2d1070b2 CW |
683 | |
684 | any++; | |
2017263e | 685 | } |
de227ef0 CW |
686 | mutex_unlock(&dev->struct_mutex); |
687 | ||
2d1070b2 | 688 | if (any == 0) |
267f0c90 | 689 | seq_puts(m, "No requests\n"); |
c2c347a9 | 690 | |
2017263e BG |
691 | return 0; |
692 | } | |
693 | ||
b2223497 | 694 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 695 | struct intel_engine_cs *engine) |
b2223497 | 696 | { |
688e6c72 CW |
697 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
698 | struct rb_node *rb; | |
699 | ||
12471ba8 | 700 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 701 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 702 | |
61d3dc70 | 703 | spin_lock_irq(&b->rb_lock); |
688e6c72 | 704 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 705 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
706 | |
707 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
708 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
709 | } | |
61d3dc70 | 710 | spin_unlock_irq(&b->rb_lock); |
b2223497 CW |
711 | } |
712 | ||
2017263e BG |
713 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
714 | { | |
36cdd013 | 715 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 716 | struct intel_engine_cs *engine; |
3b3f1650 | 717 | enum intel_engine_id id; |
2017263e | 718 | |
3b3f1650 | 719 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 720 | i915_ring_seqno_info(m, engine); |
de227ef0 | 721 | |
2017263e BG |
722 | return 0; |
723 | } | |
724 | ||
725 | ||
726 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
727 | { | |
36cdd013 | 728 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 729 | struct intel_engine_cs *engine; |
3b3f1650 | 730 | enum intel_engine_id id; |
4bb05040 | 731 | int i, pipe; |
de227ef0 | 732 | |
c8c8fb33 | 733 | intel_runtime_pm_get(dev_priv); |
2017263e | 734 | |
36cdd013 | 735 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
736 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
737 | I915_READ(GEN8_MASTER_IRQ)); | |
738 | ||
739 | seq_printf(m, "Display IER:\t%08x\n", | |
740 | I915_READ(VLV_IER)); | |
741 | seq_printf(m, "Display IIR:\t%08x\n", | |
742 | I915_READ(VLV_IIR)); | |
743 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
744 | I915_READ(VLV_IIR_RW)); | |
745 | seq_printf(m, "Display IMR:\t%08x\n", | |
746 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
747 | for_each_pipe(dev_priv, pipe) { |
748 | enum intel_display_power_domain power_domain; | |
749 | ||
750 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
751 | if (!intel_display_power_get_if_enabled(dev_priv, | |
752 | power_domain)) { | |
753 | seq_printf(m, "Pipe %c power disabled\n", | |
754 | pipe_name(pipe)); | |
755 | continue; | |
756 | } | |
757 | ||
74e1ca8c VS |
758 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
759 | pipe_name(pipe), | |
760 | I915_READ(PIPESTAT(pipe))); | |
761 | ||
9c870d03 CW |
762 | intel_display_power_put(dev_priv, power_domain); |
763 | } | |
764 | ||
765 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
766 | seq_printf(m, "Port hotplug:\t%08x\n", |
767 | I915_READ(PORT_HOTPLUG_EN)); | |
768 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
769 | I915_READ(VLV_DPFLIPSTAT)); | |
770 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
771 | I915_READ(DPINVGTT)); | |
9c870d03 | 772 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
773 | |
774 | for (i = 0; i < 4; i++) { | |
775 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
776 | i, I915_READ(GEN8_GT_IMR(i))); | |
777 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
778 | i, I915_READ(GEN8_GT_IIR(i))); | |
779 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
780 | i, I915_READ(GEN8_GT_IER(i))); | |
781 | } | |
782 | ||
783 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
784 | I915_READ(GEN8_PCU_IMR)); | |
785 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
786 | I915_READ(GEN8_PCU_IIR)); | |
787 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
788 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 789 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
790 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
791 | I915_READ(GEN8_MASTER_IRQ)); | |
792 | ||
793 | for (i = 0; i < 4; i++) { | |
794 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
795 | i, I915_READ(GEN8_GT_IMR(i))); | |
796 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
797 | i, I915_READ(GEN8_GT_IIR(i))); | |
798 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
799 | i, I915_READ(GEN8_GT_IER(i))); | |
800 | } | |
801 | ||
055e393f | 802 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
803 | enum intel_display_power_domain power_domain; |
804 | ||
805 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
806 | if (!intel_display_power_get_if_enabled(dev_priv, | |
807 | power_domain)) { | |
22c59960 PZ |
808 | seq_printf(m, "Pipe %c power disabled\n", |
809 | pipe_name(pipe)); | |
810 | continue; | |
811 | } | |
a123f157 | 812 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
813 | pipe_name(pipe), |
814 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 815 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
816 | pipe_name(pipe), |
817 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 818 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
819 | pipe_name(pipe), |
820 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
821 | |
822 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
823 | } |
824 | ||
825 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
826 | I915_READ(GEN8_DE_PORT_IMR)); | |
827 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
828 | I915_READ(GEN8_DE_PORT_IIR)); | |
829 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
830 | I915_READ(GEN8_DE_PORT_IER)); | |
831 | ||
832 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
833 | I915_READ(GEN8_DE_MISC_IMR)); | |
834 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
835 | I915_READ(GEN8_DE_MISC_IIR)); | |
836 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
837 | I915_READ(GEN8_DE_MISC_IER)); | |
838 | ||
839 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
840 | I915_READ(GEN8_PCU_IMR)); | |
841 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
842 | I915_READ(GEN8_PCU_IIR)); | |
843 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
844 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 845 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
846 | seq_printf(m, "Display IER:\t%08x\n", |
847 | I915_READ(VLV_IER)); | |
848 | seq_printf(m, "Display IIR:\t%08x\n", | |
849 | I915_READ(VLV_IIR)); | |
850 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
851 | I915_READ(VLV_IIR_RW)); | |
852 | seq_printf(m, "Display IMR:\t%08x\n", | |
853 | I915_READ(VLV_IMR)); | |
4f4631af CW |
854 | for_each_pipe(dev_priv, pipe) { |
855 | enum intel_display_power_domain power_domain; | |
856 | ||
857 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
858 | if (!intel_display_power_get_if_enabled(dev_priv, | |
859 | power_domain)) { | |
860 | seq_printf(m, "Pipe %c power disabled\n", | |
861 | pipe_name(pipe)); | |
862 | continue; | |
863 | } | |
864 | ||
7e231dbe JB |
865 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
866 | pipe_name(pipe), | |
867 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
868 | intel_display_power_put(dev_priv, power_domain); |
869 | } | |
7e231dbe JB |
870 | |
871 | seq_printf(m, "Master IER:\t%08x\n", | |
872 | I915_READ(VLV_MASTER_IER)); | |
873 | ||
874 | seq_printf(m, "Render IER:\t%08x\n", | |
875 | I915_READ(GTIER)); | |
876 | seq_printf(m, "Render IIR:\t%08x\n", | |
877 | I915_READ(GTIIR)); | |
878 | seq_printf(m, "Render IMR:\t%08x\n", | |
879 | I915_READ(GTIMR)); | |
880 | ||
881 | seq_printf(m, "PM IER:\t\t%08x\n", | |
882 | I915_READ(GEN6_PMIER)); | |
883 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
884 | I915_READ(GEN6_PMIIR)); | |
885 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
886 | I915_READ(GEN6_PMIMR)); | |
887 | ||
888 | seq_printf(m, "Port hotplug:\t%08x\n", | |
889 | I915_READ(PORT_HOTPLUG_EN)); | |
890 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
891 | I915_READ(VLV_DPFLIPSTAT)); | |
892 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
893 | I915_READ(DPINVGTT)); | |
894 | ||
36cdd013 | 895 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
896 | seq_printf(m, "Interrupt enable: %08x\n", |
897 | I915_READ(IER)); | |
898 | seq_printf(m, "Interrupt identity: %08x\n", | |
899 | I915_READ(IIR)); | |
900 | seq_printf(m, "Interrupt mask: %08x\n", | |
901 | I915_READ(IMR)); | |
055e393f | 902 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
903 | seq_printf(m, "Pipe %c stat: %08x\n", |
904 | pipe_name(pipe), | |
905 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
906 | } else { |
907 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
908 | I915_READ(DEIER)); | |
909 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
910 | I915_READ(DEIIR)); | |
911 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
912 | I915_READ(DEIMR)); | |
913 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
914 | I915_READ(SDEIER)); | |
915 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
916 | I915_READ(SDEIIR)); | |
917 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
918 | I915_READ(SDEIMR)); | |
919 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
920 | I915_READ(GTIER)); | |
921 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
922 | I915_READ(GTIIR)); | |
923 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
924 | I915_READ(GTIMR)); | |
925 | } | |
3b3f1650 | 926 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 927 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
928 | seq_printf(m, |
929 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 930 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 931 | } |
e2f80391 | 932 | i915_ring_seqno_info(m, engine); |
9862e600 | 933 | } |
c8c8fb33 | 934 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 935 | |
2017263e BG |
936 | return 0; |
937 | } | |
938 | ||
a6172a80 CW |
939 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
940 | { | |
36cdd013 DW |
941 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
942 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
943 | int i, ret; |
944 | ||
945 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
946 | if (ret) | |
947 | return ret; | |
a6172a80 | 948 | |
a6172a80 CW |
949 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
950 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 951 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 952 | |
6c085a72 CW |
953 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
954 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 955 | if (!vma) |
267f0c90 | 956 | seq_puts(m, "unused"); |
c2c347a9 | 957 | else |
49ef5294 | 958 | describe_obj(m, vma->obj); |
267f0c90 | 959 | seq_putc(m, '\n'); |
a6172a80 CW |
960 | } |
961 | ||
05394f39 | 962 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
963 | return 0; |
964 | } | |
965 | ||
98a2f411 | 966 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
967 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
968 | size_t count, loff_t *pos) | |
d5442303 | 969 | { |
5a4c6f1b CW |
970 | struct i915_gpu_state *error = file->private_data; |
971 | struct drm_i915_error_state_buf str; | |
972 | ssize_t ret; | |
973 | loff_t tmp; | |
d5442303 | 974 | |
5a4c6f1b CW |
975 | if (!error) |
976 | return 0; | |
d5442303 | 977 | |
5a4c6f1b CW |
978 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
979 | if (ret) | |
980 | return ret; | |
d5442303 | 981 | |
5a4c6f1b CW |
982 | ret = i915_error_state_to_str(&str, error); |
983 | if (ret) | |
984 | goto out; | |
d5442303 | 985 | |
5a4c6f1b CW |
986 | tmp = 0; |
987 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
988 | if (ret < 0) | |
989 | goto out; | |
d5442303 | 990 | |
5a4c6f1b CW |
991 | *pos = str.start + ret; |
992 | out: | |
993 | i915_error_state_buf_release(&str); | |
994 | return ret; | |
995 | } | |
edc3d884 | 996 | |
5a4c6f1b CW |
997 | static int gpu_state_release(struct inode *inode, struct file *file) |
998 | { | |
999 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1000 | return 0; |
d5442303 DV |
1001 | } |
1002 | ||
5a4c6f1b | 1003 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1004 | { |
5a4c6f1b | 1005 | struct i915_gpu_state *gpu; |
d5442303 | 1006 | |
5a4c6f1b CW |
1007 | gpu = i915_capture_gpu_state(inode->i_private); |
1008 | if (!gpu) | |
1009 | return -ENOMEM; | |
d5442303 | 1010 | |
5a4c6f1b | 1011 | file->private_data = gpu; |
edc3d884 MK |
1012 | return 0; |
1013 | } | |
1014 | ||
5a4c6f1b CW |
1015 | static const struct file_operations i915_gpu_info_fops = { |
1016 | .owner = THIS_MODULE, | |
1017 | .open = i915_gpu_info_open, | |
1018 | .read = gpu_state_read, | |
1019 | .llseek = default_llseek, | |
1020 | .release = gpu_state_release, | |
1021 | }; | |
1022 | ||
1023 | static ssize_t | |
1024 | i915_error_state_write(struct file *filp, | |
1025 | const char __user *ubuf, | |
1026 | size_t cnt, | |
1027 | loff_t *ppos) | |
4dc955f7 | 1028 | { |
5a4c6f1b | 1029 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1030 | |
5a4c6f1b CW |
1031 | if (!error) |
1032 | return 0; | |
edc3d884 | 1033 | |
5a4c6f1b CW |
1034 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1035 | i915_reset_error_state(error->i915); | |
edc3d884 | 1036 | |
5a4c6f1b CW |
1037 | return cnt; |
1038 | } | |
edc3d884 | 1039 | |
5a4c6f1b CW |
1040 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1041 | { | |
1042 | file->private_data = i915_first_error_state(inode->i_private); | |
1043 | return 0; | |
d5442303 DV |
1044 | } |
1045 | ||
1046 | static const struct file_operations i915_error_state_fops = { | |
1047 | .owner = THIS_MODULE, | |
1048 | .open = i915_error_state_open, | |
5a4c6f1b | 1049 | .read = gpu_state_read, |
d5442303 DV |
1050 | .write = i915_error_state_write, |
1051 | .llseek = default_llseek, | |
5a4c6f1b | 1052 | .release = gpu_state_release, |
d5442303 | 1053 | }; |
98a2f411 CW |
1054 | #endif |
1055 | ||
647416f9 KC |
1056 | static int |
1057 | i915_next_seqno_set(void *data, u64 val) | |
1058 | { | |
36cdd013 DW |
1059 | struct drm_i915_private *dev_priv = data; |
1060 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1061 | int ret; |
1062 | ||
40633219 MK |
1063 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1064 | if (ret) | |
1065 | return ret; | |
1066 | ||
73cb9701 | 1067 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1068 | mutex_unlock(&dev->struct_mutex); |
1069 | ||
647416f9 | 1070 | return ret; |
40633219 MK |
1071 | } |
1072 | ||
647416f9 | 1073 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1074 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1075 | "0x%llx\n"); |
40633219 | 1076 | |
adb4bd12 | 1077 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1078 | { |
36cdd013 | 1079 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1080 | int ret = 0; |
1081 | ||
1082 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1083 | |
36cdd013 | 1084 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1085 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1086 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1087 | ||
1088 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1089 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1090 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1091 | MEMSTAT_VID_SHIFT); | |
1092 | seq_printf(m, "Current P-state: %d\n", | |
1093 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1094 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1095 | u32 freq_sts; |
1096 | ||
1097 | mutex_lock(&dev_priv->rps.hw_lock); | |
1098 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1099 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1100 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1101 | ||
1102 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1103 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1104 | ||
1105 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1106 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1107 | ||
1108 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1109 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1110 | ||
1111 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1112 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1113 | ||
1114 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1115 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1116 | ||
1117 | seq_printf(m, | |
1118 | "efficient (RPe) frequency: %d MHz\n", | |
1119 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1120 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1121 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1122 | u32 rp_state_limits; |
1123 | u32 gt_perf_status; | |
1124 | u32 rp_state_cap; | |
0d8f9491 | 1125 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1126 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1127 | u32 rpupei, rpcurup, rpprevup; |
1128 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1129 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1130 | int max_freq; |
1131 | ||
35040562 | 1132 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1133 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1134 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1135 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1136 | } else { | |
1137 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1138 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1139 | } | |
1140 | ||
3b8d8d91 | 1141 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1142 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1143 | |
8e8c06cd | 1144 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1145 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1146 | reqf >>= 23; |
1147 | else { | |
1148 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1149 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1150 | reqf >>= 24; |
1151 | else | |
1152 | reqf >>= 25; | |
1153 | } | |
7c59a9c1 | 1154 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1155 | |
0d8f9491 CW |
1156 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1157 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1158 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1159 | ||
ccab5c82 | 1160 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1161 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1162 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1163 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1164 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1165 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1166 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1167 | if (IS_GEN9(dev_priv)) |
60260a5b | 1168 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1169 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1170 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1171 | else | |
1172 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1173 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1174 | |
59bad947 | 1175 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1176 | |
36cdd013 | 1177 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1178 | pm_ier = I915_READ(GEN6_PMIER); |
1179 | pm_imr = I915_READ(GEN6_PMIMR); | |
1180 | pm_isr = I915_READ(GEN6_PMISR); | |
1181 | pm_iir = I915_READ(GEN6_PMIIR); | |
1182 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1183 | } else { | |
1184 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1185 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1186 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1187 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1188 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1189 | } | |
0d8f9491 | 1190 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1191 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 SAK |
1192 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
1193 | dev_priv->rps.pm_intrmsk_mbz); | |
3b8d8d91 | 1194 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1195 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1196 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1197 | seq_printf(m, "Render p-state VID: %d\n", |
1198 | gt_perf_status & 0xff); | |
1199 | seq_printf(m, "Render p-state limit: %d\n", | |
1200 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1201 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1202 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1203 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1204 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1205 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1206 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1207 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1208 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1209 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1210 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1211 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1212 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1213 | seq_printf(m, "Up threshold: %d%%\n", |
1214 | dev_priv->rps.up_threshold); | |
1215 | ||
d6cda9c7 AG |
1216 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1217 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1218 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1219 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1220 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1221 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1222 | seq_printf(m, "Down threshold: %d%%\n", |
1223 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1224 | |
cc3f90f0 | 1225 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1226 | rp_state_cap >> 16) & 0xff; |
b976dc53 | 1227 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1228 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1229 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1230 | |
1231 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
b976dc53 | 1232 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1233 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1234 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1235 | |
cc3f90f0 | 1236 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1237 | rp_state_cap >> 0) & 0xff; |
b976dc53 | 1238 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1239 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1240 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1241 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1242 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1243 | |
d86ed34a CW |
1244 | seq_printf(m, "Current freq: %d MHz\n", |
1245 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1246 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1247 | seq_printf(m, "Idle freq: %d MHz\n", |
1248 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1249 | seq_printf(m, "Min freq: %d MHz\n", |
1250 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1251 | seq_printf(m, "Boost freq: %d MHz\n", |
1252 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1253 | seq_printf(m, "Max freq: %d MHz\n", |
1254 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1255 | seq_printf(m, | |
1256 | "efficient (RPe) frequency: %d MHz\n", | |
1257 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1258 | } else { |
267f0c90 | 1259 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1260 | } |
f97108d1 | 1261 | |
49cd97a3 | 1262 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1263 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1264 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1265 | ||
c8c8fb33 PZ |
1266 | intel_runtime_pm_put(dev_priv); |
1267 | return ret; | |
f97108d1 JB |
1268 | } |
1269 | ||
d636951e BW |
1270 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1271 | struct seq_file *m, | |
1272 | struct intel_instdone *instdone) | |
1273 | { | |
f9e61372 BW |
1274 | int slice; |
1275 | int subslice; | |
1276 | ||
d636951e BW |
1277 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1278 | instdone->instdone); | |
1279 | ||
1280 | if (INTEL_GEN(dev_priv) <= 3) | |
1281 | return; | |
1282 | ||
1283 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1284 | instdone->slice_common); | |
1285 | ||
1286 | if (INTEL_GEN(dev_priv) <= 6) | |
1287 | return; | |
1288 | ||
f9e61372 BW |
1289 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1290 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1291 | slice, subslice, instdone->sampler[slice][subslice]); | |
1292 | ||
1293 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1294 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1295 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1296 | } |
1297 | ||
f654449a CW |
1298 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1299 | { | |
36cdd013 | 1300 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1301 | struct intel_engine_cs *engine; |
666796da TU |
1302 | u64 acthd[I915_NUM_ENGINES]; |
1303 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1304 | struct intel_instdone instdone; |
c3232b18 | 1305 | enum intel_engine_id id; |
f654449a | 1306 | |
8af29b0c | 1307 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1308 | seq_puts(m, "Wedged\n"); |
1309 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1310 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1311 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1312 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1313 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1314 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1315 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1316 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1317 | |
f654449a | 1318 | if (!i915.enable_hangcheck) { |
8c185eca | 1319 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1320 | return 0; |
1321 | } | |
1322 | ||
ebbc7546 MK |
1323 | intel_runtime_pm_get(dev_priv); |
1324 | ||
3b3f1650 | 1325 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1326 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1327 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1328 | } |
1329 | ||
3b3f1650 | 1330 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1331 | |
ebbc7546 MK |
1332 | intel_runtime_pm_put(dev_priv); |
1333 | ||
8352aea3 CW |
1334 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1335 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1336 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1337 | jiffies)); | |
8352aea3 CW |
1338 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1339 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1340 | else | |
1341 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1342 | |
f73b5674 CW |
1343 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1344 | ||
3b3f1650 | 1345 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1346 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1347 | struct rb_node *rb; | |
1348 | ||
e2f80391 | 1349 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1350 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1351 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1352 | intel_engine_last_submit(engine), |
1353 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1354 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1355 | yesno(intel_engine_has_waiter(engine)), |
1356 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1357 | &dev_priv->gpu_error.missed_irq_rings)), |
1358 | yesno(engine->hangcheck.stalled)); | |
1359 | ||
61d3dc70 | 1360 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1361 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1362 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1363 | |
1364 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1365 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1366 | } | |
61d3dc70 | 1367 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1368 | |
f654449a | 1369 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1370 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1371 | (long long)acthd[id]); |
3fe3b030 MK |
1372 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1373 | hangcheck_action_to_str(engine->hangcheck.action), | |
1374 | engine->hangcheck.action, | |
1375 | jiffies_to_msecs(jiffies - | |
1376 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1377 | |
e2f80391 | 1378 | if (engine->id == RCS) { |
d636951e | 1379 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1380 | |
d636951e | 1381 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1382 | |
d636951e | 1383 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1384 | |
d636951e BW |
1385 | i915_instdone_info(dev_priv, m, |
1386 | &engine->hangcheck.instdone); | |
61642ff0 | 1387 | } |
f654449a CW |
1388 | } |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
4d85529d | 1393 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1394 | { |
36cdd013 | 1395 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1396 | u32 rgvmodectl, rstdbyctl; |
1397 | u16 crstandvid; | |
616fdb5a | 1398 | |
616fdb5a BW |
1399 | rgvmodectl = I915_READ(MEMMODECTL); |
1400 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1401 | crstandvid = I915_READ16(CRSTANDVID); | |
1402 | ||
742f491d | 1403 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1404 | seq_printf(m, "Boost freq: %d\n", |
1405 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1406 | MEMMODE_BOOST_FREQ_SHIFT); | |
1407 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1408 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1409 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1410 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1411 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1412 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1413 | seq_printf(m, "Starting frequency: P%d\n", |
1414 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1415 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1416 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1417 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1418 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1419 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1420 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1421 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1422 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1423 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1424 | case RSX_STATUS_ON: | |
267f0c90 | 1425 | seq_puts(m, "on\n"); |
88271da3 JB |
1426 | break; |
1427 | case RSX_STATUS_RC1: | |
267f0c90 | 1428 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1429 | break; |
1430 | case RSX_STATUS_RC1E: | |
267f0c90 | 1431 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1432 | break; |
1433 | case RSX_STATUS_RS1: | |
267f0c90 | 1434 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1435 | break; |
1436 | case RSX_STATUS_RS2: | |
267f0c90 | 1437 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1438 | break; |
1439 | case RSX_STATUS_RS3: | |
267f0c90 | 1440 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1441 | break; |
1442 | default: | |
267f0c90 | 1443 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1444 | break; |
1445 | } | |
f97108d1 JB |
1446 | |
1447 | return 0; | |
1448 | } | |
1449 | ||
f65367b5 | 1450 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1451 | { |
36cdd013 | 1452 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1453 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1454 | |
1455 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1456 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1457 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1458 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1459 | fw_domain->wake_count); |
1460 | } | |
1461 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1462 | |
b2cff0db CW |
1463 | return 0; |
1464 | } | |
1465 | ||
1362877e MK |
1466 | static void print_rc6_res(struct seq_file *m, |
1467 | const char *title, | |
1468 | const i915_reg_t reg) | |
1469 | { | |
1470 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1471 | ||
1472 | seq_printf(m, "%s %u (%llu us)\n", | |
1473 | title, I915_READ(reg), | |
1474 | intel_rc6_residency_us(dev_priv, reg)); | |
1475 | } | |
1476 | ||
b2cff0db CW |
1477 | static int vlv_drpc_info(struct seq_file *m) |
1478 | { | |
36cdd013 | 1479 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1480 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1481 | |
6b312cd3 | 1482 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1483 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1484 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1485 | ||
1486 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1487 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1488 | seq_printf(m, "Turbo enabled: %s\n", | |
1489 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1490 | seq_printf(m, "HW control enabled: %s\n", | |
1491 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1492 | seq_printf(m, "SW control enabled: %s\n", | |
1493 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1494 | GEN6_RP_MEDIA_SW_MODE)); | |
1495 | seq_printf(m, "RC6 Enabled: %s\n", | |
1496 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1497 | GEN6_RC_CTL_EI_MODE(1)))); | |
1498 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1499 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1500 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1501 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1502 | |
1362877e MK |
1503 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1504 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1505 | |
f65367b5 | 1506 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1507 | } |
1508 | ||
4d85529d BW |
1509 | static int gen6_drpc_info(struct seq_file *m) |
1510 | { | |
36cdd013 | 1511 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ecd8faea | 1512 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1513 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1514 | unsigned forcewake_count; |
cf632bd6 | 1515 | int count = 0; |
93b525dc | 1516 | |
cf632bd6 | 1517 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1518 | if (forcewake_count) { |
267f0c90 DL |
1519 | seq_puts(m, "RC information inaccurate because somebody " |
1520 | "holds a forcewake reference \n"); | |
4d85529d BW |
1521 | } else { |
1522 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1523 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1524 | udelay(10); | |
1525 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1526 | } | |
1527 | ||
75aa3f63 | 1528 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1529 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1530 | |
1531 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1532 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1533 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1534 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1535 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1536 | } | |
cf632bd6 | 1537 | |
44cbd338 BW |
1538 | mutex_lock(&dev_priv->rps.hw_lock); |
1539 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1540 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1541 | |
1542 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1543 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1544 | seq_printf(m, "HW control enabled: %s\n", | |
1545 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1546 | seq_printf(m, "SW control enabled: %s\n", | |
1547 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1548 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1549 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1550 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1551 | seq_printf(m, "RC6 Enabled: %s\n", | |
1552 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1553 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1554 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1555 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1556 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1557 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1558 | } | |
4d85529d BW |
1559 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1560 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1561 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1562 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1563 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1564 | switch (gt_core_status & GEN6_RCn_MASK) { |
1565 | case GEN6_RC0: | |
1566 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1567 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1568 | else |
267f0c90 | 1569 | seq_puts(m, "on\n"); |
4d85529d BW |
1570 | break; |
1571 | case GEN6_RC3: | |
267f0c90 | 1572 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1573 | break; |
1574 | case GEN6_RC6: | |
267f0c90 | 1575 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1576 | break; |
1577 | case GEN6_RC7: | |
267f0c90 | 1578 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1579 | break; |
1580 | default: | |
267f0c90 | 1581 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1582 | break; |
1583 | } | |
1584 | ||
1585 | seq_printf(m, "Core Power Down: %s\n", | |
1586 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1587 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1588 | seq_printf(m, "Render Power Well: %s\n", |
1589 | (gen9_powergate_status & | |
1590 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1591 | seq_printf(m, "Media Power Well: %s\n", | |
1592 | (gen9_powergate_status & | |
1593 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1594 | } | |
cce66a28 BW |
1595 | |
1596 | /* Not exactly sure what this is */ | |
1362877e MK |
1597 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1598 | GEN6_GT_GFX_RC6_LOCKED); | |
1599 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1600 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1601 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1602 | |
ecd8faea BW |
1603 | seq_printf(m, "RC6 voltage: %dmV\n", |
1604 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1605 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1606 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1607 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1608 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1609 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1610 | } |
1611 | ||
1612 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1613 | { | |
36cdd013 | 1614 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1615 | int err; |
1616 | ||
1617 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1618 | |
36cdd013 | 1619 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1620 | err = vlv_drpc_info(m); |
36cdd013 | 1621 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1622 | err = gen6_drpc_info(m); |
4d85529d | 1623 | else |
cf632bd6 CW |
1624 | err = ironlake_drpc_info(m); |
1625 | ||
1626 | intel_runtime_pm_put(dev_priv); | |
1627 | ||
1628 | return err; | |
4d85529d BW |
1629 | } |
1630 | ||
9a851789 DV |
1631 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1632 | { | |
36cdd013 | 1633 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1634 | |
1635 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1636 | dev_priv->fb_tracking.busy_bits); | |
1637 | ||
1638 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1639 | dev_priv->fb_tracking.flip_bits); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
b5e50c3f JB |
1644 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1645 | { | |
36cdd013 | 1646 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1647 | |
36cdd013 | 1648 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1649 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1650 | return 0; |
1651 | } | |
1652 | ||
36623ef8 | 1653 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1654 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1655 | |
0e631adc | 1656 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1657 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1658 | else |
1659 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1660 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1661 | |
0fc6a9dc PZ |
1662 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1663 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1664 | BDW_FBC_COMPRESSION_MASK : | |
1665 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1666 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1667 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1668 | } | |
31b9df10 | 1669 | |
25ad93fd | 1670 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1671 | intel_runtime_pm_put(dev_priv); |
1672 | ||
b5e50c3f JB |
1673 | return 0; |
1674 | } | |
1675 | ||
da46f936 RV |
1676 | static int i915_fbc_fc_get(void *data, u64 *val) |
1677 | { | |
36cdd013 | 1678 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1679 | |
36cdd013 | 1680 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1681 | return -ENODEV; |
1682 | ||
da46f936 | 1683 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1684 | |
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | static int i915_fbc_fc_set(void *data, u64 val) | |
1689 | { | |
36cdd013 | 1690 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1691 | u32 reg; |
1692 | ||
36cdd013 | 1693 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1694 | return -ENODEV; |
1695 | ||
25ad93fd | 1696 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1697 | |
1698 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1699 | dev_priv->fbc.false_color = val; | |
1700 | ||
1701 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1702 | (reg | FBC_CTL_FALSE_COLOR) : | |
1703 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1704 | ||
25ad93fd | 1705 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1706 | return 0; |
1707 | } | |
1708 | ||
1709 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1710 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1711 | "%llu\n"); | |
1712 | ||
92d44621 PZ |
1713 | static int i915_ips_status(struct seq_file *m, void *unused) |
1714 | { | |
36cdd013 | 1715 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1716 | |
36cdd013 | 1717 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1718 | seq_puts(m, "not supported\n"); |
1719 | return 0; | |
1720 | } | |
1721 | ||
36623ef8 PZ |
1722 | intel_runtime_pm_get(dev_priv); |
1723 | ||
0eaa53f0 RV |
1724 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1725 | yesno(i915.enable_ips)); | |
1726 | ||
36cdd013 | 1727 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1728 | seq_puts(m, "Currently: unknown\n"); |
1729 | } else { | |
1730 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1731 | seq_puts(m, "Currently: enabled\n"); | |
1732 | else | |
1733 | seq_puts(m, "Currently: disabled\n"); | |
1734 | } | |
92d44621 | 1735 | |
36623ef8 PZ |
1736 | intel_runtime_pm_put(dev_priv); |
1737 | ||
92d44621 PZ |
1738 | return 0; |
1739 | } | |
1740 | ||
4a9bef37 JB |
1741 | static int i915_sr_status(struct seq_file *m, void *unused) |
1742 | { | |
36cdd013 | 1743 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1744 | bool sr_enabled = false; |
1745 | ||
36623ef8 | 1746 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1747 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1748 | |
7342a72c CW |
1749 | if (INTEL_GEN(dev_priv) >= 9) |
1750 | /* no global SR status; inspect per-plane WM */; | |
1751 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1752 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1753 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1754 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1755 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1756 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1757 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1758 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1759 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1760 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1761 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1762 | |
9c870d03 | 1763 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1764 | intel_runtime_pm_put(dev_priv); |
1765 | ||
08c4d7fc | 1766 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1767 | |
1768 | return 0; | |
1769 | } | |
1770 | ||
7648fa99 JB |
1771 | static int i915_emon_status(struct seq_file *m, void *unused) |
1772 | { | |
36cdd013 DW |
1773 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1774 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1775 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1776 | int ret; |
1777 | ||
36cdd013 | 1778 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1779 | return -ENODEV; |
1780 | ||
de227ef0 CW |
1781 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1782 | if (ret) | |
1783 | return ret; | |
7648fa99 JB |
1784 | |
1785 | temp = i915_mch_val(dev_priv); | |
1786 | chipset = i915_chipset_val(dev_priv); | |
1787 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1788 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1789 | |
1790 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1791 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1792 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1793 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | ||
23b2f8bb JB |
1798 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1799 | { | |
36cdd013 | 1800 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1801 | int ret = 0; |
23b2f8bb | 1802 | int gpu_freq, ia_freq; |
f936ec34 | 1803 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1804 | |
26310346 | 1805 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1806 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1807 | return 0; |
1808 | } | |
1809 | ||
5bfa0199 PZ |
1810 | intel_runtime_pm_get(dev_priv); |
1811 | ||
4fc688ce | 1812 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1813 | if (ret) |
5bfa0199 | 1814 | goto out; |
23b2f8bb | 1815 | |
b976dc53 | 1816 | if (IS_GEN9_BC(dev_priv)) { |
f936ec34 AG |
1817 | /* Convert GT frequency to 50 HZ units */ |
1818 | min_gpu_freq = | |
1819 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1820 | max_gpu_freq = | |
1821 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1822 | } else { | |
1823 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1824 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1825 | } | |
1826 | ||
267f0c90 | 1827 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1828 | |
f936ec34 | 1829 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1830 | ia_freq = gpu_freq; |
1831 | sandybridge_pcode_read(dev_priv, | |
1832 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1833 | &ia_freq); | |
3ebecd07 | 1834 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1835 | intel_gpu_freq(dev_priv, (gpu_freq * |
b976dc53 RV |
1836 | (IS_GEN9_BC(dev_priv) ? |
1837 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1838 | ((ia_freq >> 0) & 0xff) * 100, |
1839 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1840 | } |
1841 | ||
4fc688ce | 1842 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1843 | |
5bfa0199 PZ |
1844 | out: |
1845 | intel_runtime_pm_put(dev_priv); | |
1846 | return ret; | |
23b2f8bb JB |
1847 | } |
1848 | ||
44834a67 CW |
1849 | static int i915_opregion(struct seq_file *m, void *unused) |
1850 | { | |
36cdd013 DW |
1851 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1852 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1853 | struct intel_opregion *opregion = &dev_priv->opregion; |
1854 | int ret; | |
1855 | ||
1856 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1857 | if (ret) | |
0d38f009 | 1858 | goto out; |
44834a67 | 1859 | |
2455a8e4 JN |
1860 | if (opregion->header) |
1861 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1862 | |
1863 | mutex_unlock(&dev->struct_mutex); | |
1864 | ||
0d38f009 | 1865 | out: |
44834a67 CW |
1866 | return 0; |
1867 | } | |
1868 | ||
ada8f955 JN |
1869 | static int i915_vbt(struct seq_file *m, void *unused) |
1870 | { | |
36cdd013 | 1871 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1872 | |
1873 | if (opregion->vbt) | |
1874 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1875 | ||
1876 | return 0; | |
1877 | } | |
1878 | ||
37811fcc CW |
1879 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1880 | { | |
36cdd013 DW |
1881 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1882 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1883 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1884 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1885 | int ret; |
1886 | ||
1887 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1888 | if (ret) | |
1889 | return ret; | |
37811fcc | 1890 | |
0695726e | 1891 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1892 | if (dev_priv->fbdev) { |
1893 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1894 | |
1895 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1896 | fbdev_fb->base.width, | |
1897 | fbdev_fb->base.height, | |
b00c600e | 1898 | fbdev_fb->base.format->depth, |
272725c7 | 1899 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1900 | fbdev_fb->base.modifier, |
25bcce94 CW |
1901 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1902 | describe_obj(m, fbdev_fb->obj); | |
1903 | seq_putc(m, '\n'); | |
1904 | } | |
4520f53a | 1905 | #endif |
37811fcc | 1906 | |
4b096ac1 | 1907 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1908 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1909 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1910 | if (fb == fbdev_fb) | |
37811fcc CW |
1911 | continue; |
1912 | ||
c1ca506d | 1913 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1914 | fb->base.width, |
1915 | fb->base.height, | |
b00c600e | 1916 | fb->base.format->depth, |
272725c7 | 1917 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1918 | fb->base.modifier, |
747a598f | 1919 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1920 | describe_obj(m, fb->obj); |
267f0c90 | 1921 | seq_putc(m, '\n'); |
37811fcc | 1922 | } |
4b096ac1 | 1923 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1924 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1925 | |
1926 | return 0; | |
1927 | } | |
1928 | ||
7e37f889 | 1929 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1930 | { |
1931 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1932 | ring->space, ring->head, ring->tail, |
1933 | ring->last_retired_head); | |
c9fe99bd OM |
1934 | } |
1935 | ||
e76d3630 BW |
1936 | static int i915_context_status(struct seq_file *m, void *unused) |
1937 | { | |
36cdd013 DW |
1938 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1939 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1940 | struct intel_engine_cs *engine; |
e2efd130 | 1941 | struct i915_gem_context *ctx; |
3b3f1650 | 1942 | enum intel_engine_id id; |
c3232b18 | 1943 | int ret; |
e76d3630 | 1944 | |
f3d28878 | 1945 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1946 | if (ret) |
1947 | return ret; | |
1948 | ||
a33afea5 | 1949 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1950 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1951 | if (ctx->pid) { |
d28b99ab CW |
1952 | struct task_struct *task; |
1953 | ||
c84455b4 | 1954 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1955 | if (task) { |
1956 | seq_printf(m, "(%s [%d]) ", | |
1957 | task->comm, task->pid); | |
1958 | put_task_struct(task); | |
1959 | } | |
c84455b4 CW |
1960 | } else if (IS_ERR(ctx->file_priv)) { |
1961 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1962 | } else { |
1963 | seq_puts(m, "(kernel) "); | |
1964 | } | |
1965 | ||
bca44d80 CW |
1966 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1967 | seq_putc(m, '\n'); | |
c9fe99bd | 1968 | |
3b3f1650 | 1969 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1970 | struct intel_context *ce = &ctx->engine[engine->id]; |
1971 | ||
1972 | seq_printf(m, "%s: ", engine->name); | |
1973 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1974 | if (ce->state) | |
bf3783e5 | 1975 | describe_obj(m, ce->state->obj); |
dca33ecc | 1976 | if (ce->ring) |
7e37f889 | 1977 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1978 | seq_putc(m, '\n'); |
c9fe99bd | 1979 | } |
a33afea5 | 1980 | |
a33afea5 | 1981 | seq_putc(m, '\n'); |
a168c293 BW |
1982 | } |
1983 | ||
f3d28878 | 1984 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1985 | |
1986 | return 0; | |
1987 | } | |
1988 | ||
064ca1d2 | 1989 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1990 | struct i915_gem_context *ctx, |
0bc40be8 | 1991 | struct intel_engine_cs *engine) |
064ca1d2 | 1992 | { |
bf3783e5 | 1993 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1994 | struct page *page; |
064ca1d2 | 1995 | int j; |
064ca1d2 | 1996 | |
7069b144 CW |
1997 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1998 | ||
bf3783e5 CW |
1999 | if (!vma) { |
2000 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2001 | return; |
2002 | } | |
2003 | ||
bf3783e5 CW |
2004 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2005 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2006 | i915_ggtt_offset(vma)); |
064ca1d2 | 2007 | |
a4f5ea64 | 2008 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2009 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2010 | return; |
2011 | } | |
2012 | ||
bf3783e5 CW |
2013 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2014 | if (page) { | |
2015 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2016 | |
2017 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2018 | seq_printf(m, |
2019 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2020 | j * 4, | |
064ca1d2 TD |
2021 | reg_state[j], reg_state[j + 1], |
2022 | reg_state[j + 2], reg_state[j + 3]); | |
2023 | } | |
2024 | kunmap_atomic(reg_state); | |
2025 | } | |
2026 | ||
a4f5ea64 | 2027 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2028 | seq_putc(m, '\n'); |
2029 | } | |
2030 | ||
c0ab1ae9 BW |
2031 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2032 | { | |
36cdd013 DW |
2033 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2034 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2035 | struct intel_engine_cs *engine; |
e2efd130 | 2036 | struct i915_gem_context *ctx; |
3b3f1650 | 2037 | enum intel_engine_id id; |
b4ac5afc | 2038 | int ret; |
c0ab1ae9 BW |
2039 | |
2040 | if (!i915.enable_execlists) { | |
2041 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2046 | if (ret) | |
2047 | return ret; | |
2048 | ||
e28e404c | 2049 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2050 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2051 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2052 | |
2053 | mutex_unlock(&dev->struct_mutex); | |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
ea16a3cd DV |
2058 | static const char *swizzle_string(unsigned swizzle) |
2059 | { | |
aee56cff | 2060 | switch (swizzle) { |
ea16a3cd DV |
2061 | case I915_BIT_6_SWIZZLE_NONE: |
2062 | return "none"; | |
2063 | case I915_BIT_6_SWIZZLE_9: | |
2064 | return "bit9"; | |
2065 | case I915_BIT_6_SWIZZLE_9_10: | |
2066 | return "bit9/bit10"; | |
2067 | case I915_BIT_6_SWIZZLE_9_11: | |
2068 | return "bit9/bit11"; | |
2069 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2070 | return "bit9/bit10/bit11"; | |
2071 | case I915_BIT_6_SWIZZLE_9_17: | |
2072 | return "bit9/bit17"; | |
2073 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2074 | return "bit9/bit10/bit17"; | |
2075 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2076 | return "unknown"; |
ea16a3cd DV |
2077 | } |
2078 | ||
2079 | return "bug"; | |
2080 | } | |
2081 | ||
2082 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2083 | { | |
36cdd013 | 2084 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2085 | |
c8c8fb33 | 2086 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2087 | |
ea16a3cd DV |
2088 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2089 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2090 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2091 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2092 | ||
36cdd013 | 2093 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2094 | seq_printf(m, "DDC = 0x%08x\n", |
2095 | I915_READ(DCC)); | |
656bfa3a DV |
2096 | seq_printf(m, "DDC2 = 0x%08x\n", |
2097 | I915_READ(DCC2)); | |
ea16a3cd DV |
2098 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2099 | I915_READ16(C0DRB3)); | |
2100 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2101 | I915_READ16(C1DRB3)); | |
36cdd013 | 2102 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2103 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2104 | I915_READ(MAD_DIMM_C0)); | |
2105 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2106 | I915_READ(MAD_DIMM_C1)); | |
2107 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2108 | I915_READ(MAD_DIMM_C2)); | |
2109 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2110 | I915_READ(TILECTL)); | |
36cdd013 | 2111 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2112 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2113 | I915_READ(GAMTARBMODE)); | |
2114 | else | |
2115 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2116 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2117 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2118 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2119 | } |
656bfa3a DV |
2120 | |
2121 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2122 | seq_puts(m, "L-shaped memory detected\n"); | |
2123 | ||
c8c8fb33 | 2124 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2125 | |
2126 | return 0; | |
2127 | } | |
2128 | ||
1c60fef5 BW |
2129 | static int per_file_ctx(int id, void *ptr, void *data) |
2130 | { | |
e2efd130 | 2131 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2132 | struct seq_file *m = data; |
ae6c4806 DV |
2133 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2134 | ||
2135 | if (!ppgtt) { | |
2136 | seq_printf(m, " no ppgtt for context %d\n", | |
2137 | ctx->user_handle); | |
2138 | return 0; | |
2139 | } | |
1c60fef5 | 2140 | |
f83d6518 OM |
2141 | if (i915_gem_context_is_default(ctx)) |
2142 | seq_puts(m, " default context:\n"); | |
2143 | else | |
821d66dd | 2144 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2145 | ppgtt->debug_dump(ppgtt, m); |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
36cdd013 DW |
2150 | static void gen8_ppgtt_info(struct seq_file *m, |
2151 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2152 | { |
77df6772 | 2153 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2154 | struct intel_engine_cs *engine; |
2155 | enum intel_engine_id id; | |
b4ac5afc | 2156 | int i; |
3cf17fc5 | 2157 | |
77df6772 BW |
2158 | if (!ppgtt) |
2159 | return; | |
2160 | ||
3b3f1650 | 2161 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2162 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2163 | for (i = 0; i < 4; i++) { |
e2f80391 | 2164 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2165 | pdp <<= 32; |
e2f80391 | 2166 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2167 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2168 | } |
2169 | } | |
2170 | } | |
2171 | ||
36cdd013 DW |
2172 | static void gen6_ppgtt_info(struct seq_file *m, |
2173 | struct drm_i915_private *dev_priv) | |
77df6772 | 2174 | { |
e2f80391 | 2175 | struct intel_engine_cs *engine; |
3b3f1650 | 2176 | enum intel_engine_id id; |
3cf17fc5 | 2177 | |
7e22dbbb | 2178 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2179 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2180 | ||
3b3f1650 | 2181 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2182 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2183 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2184 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2185 | I915_READ(RING_MODE_GEN7(engine))); | |
2186 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2187 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2188 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2189 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2190 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2191 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2192 | } |
2193 | if (dev_priv->mm.aliasing_ppgtt) { | |
2194 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2195 | ||
267f0c90 | 2196 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2197 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2198 | |
87d60b63 | 2199 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2200 | } |
1c60fef5 | 2201 | |
3cf17fc5 | 2202 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2203 | } |
2204 | ||
2205 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2206 | { | |
36cdd013 DW |
2207 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2208 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2209 | struct drm_file *file; |
637ee29e | 2210 | int ret; |
77df6772 | 2211 | |
637ee29e CW |
2212 | mutex_lock(&dev->filelist_mutex); |
2213 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2214 | if (ret) |
637ee29e CW |
2215 | goto out_unlock; |
2216 | ||
c8c8fb33 | 2217 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2218 | |
36cdd013 DW |
2219 | if (INTEL_GEN(dev_priv) >= 8) |
2220 | gen8_ppgtt_info(m, dev_priv); | |
2221 | else if (INTEL_GEN(dev_priv) >= 6) | |
2222 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2223 | |
ea91e401 MT |
2224 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2225 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2226 | struct task_struct *task; |
ea91e401 | 2227 | |
7cb5dff8 | 2228 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2229 | if (!task) { |
2230 | ret = -ESRCH; | |
637ee29e | 2231 | goto out_rpm; |
06812760 | 2232 | } |
7cb5dff8 GT |
2233 | seq_printf(m, "\nproc: %s\n", task->comm); |
2234 | put_task_struct(task); | |
ea91e401 MT |
2235 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2236 | (void *)(unsigned long)m); | |
2237 | } | |
2238 | ||
637ee29e | 2239 | out_rpm: |
c8c8fb33 | 2240 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2241 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2242 | out_unlock: |
2243 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2244 | return ret; |
3cf17fc5 DV |
2245 | } |
2246 | ||
f5a4c67d CW |
2247 | static int count_irq_waiters(struct drm_i915_private *i915) |
2248 | { | |
e2f80391 | 2249 | struct intel_engine_cs *engine; |
3b3f1650 | 2250 | enum intel_engine_id id; |
f5a4c67d | 2251 | int count = 0; |
f5a4c67d | 2252 | |
3b3f1650 | 2253 | for_each_engine(engine, i915, id) |
688e6c72 | 2254 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2255 | |
2256 | return count; | |
2257 | } | |
2258 | ||
7466c291 CW |
2259 | static const char *rps_power_to_str(unsigned int power) |
2260 | { | |
2261 | static const char * const strings[] = { | |
2262 | [LOW_POWER] = "low power", | |
2263 | [BETWEEN] = "mixed", | |
2264 | [HIGH_POWER] = "high power", | |
2265 | }; | |
2266 | ||
2267 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2268 | return "unknown"; | |
2269 | ||
2270 | return strings[power]; | |
2271 | } | |
2272 | ||
1854d5ca CW |
2273 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2274 | { | |
36cdd013 DW |
2275 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2276 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2277 | struct drm_file *file; |
1854d5ca | 2278 | |
f5a4c67d | 2279 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2280 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2281 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2282 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2283 | seq_printf(m, "Frequency requested %d\n", |
2284 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2285 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2286 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2287 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2288 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2289 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2290 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2291 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2292 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2293 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2294 | |
2295 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2296 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2297 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2298 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2299 | struct task_struct *task; | |
2300 | ||
2301 | rcu_read_lock(); | |
2302 | task = pid_task(file->pid, PIDTYPE_PID); | |
2303 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2304 | task ? task->comm : "<unknown>", | |
2305 | task ? task->pid : -1, | |
2e1b8730 CW |
2306 | file_priv->rps.boosts, |
2307 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2308 | rcu_read_unlock(); |
2309 | } | |
197be2ae | 2310 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2311 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2312 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2313 | |
7466c291 CW |
2314 | if (INTEL_GEN(dev_priv) >= 6 && |
2315 | dev_priv->rps.enabled && | |
28176ef4 | 2316 | dev_priv->gt.active_requests) { |
7466c291 CW |
2317 | u32 rpup, rpupei; |
2318 | u32 rpdown, rpdownei; | |
2319 | ||
2320 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2321 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2322 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2323 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2324 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2325 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2326 | ||
2327 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2328 | rps_power_to_str(dev_priv->rps.power)); | |
2329 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2330 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2331 | dev_priv->rps.up_threshold); |
2332 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2333 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2334 | dev_priv->rps.down_threshold); |
2335 | } else { | |
2336 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2337 | } | |
2338 | ||
8d3afd7d | 2339 | return 0; |
1854d5ca CW |
2340 | } |
2341 | ||
63573eb7 BW |
2342 | static int i915_llc(struct seq_file *m, void *data) |
2343 | { | |
36cdd013 | 2344 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2345 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2346 | |
36cdd013 | 2347 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2348 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2349 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2350 | |
2351 | return 0; | |
2352 | } | |
2353 | ||
0509ead1 AS |
2354 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2355 | { | |
2356 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2357 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2358 | ||
2359 | if (!HAS_HUC_UCODE(dev_priv)) | |
2360 | return 0; | |
2361 | ||
2362 | seq_puts(m, "HuC firmware status:\n"); | |
2363 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2364 | seq_printf(m, "\tfetch: %s\n", | |
2365 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2366 | seq_printf(m, "\tload: %s\n", | |
2367 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2368 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2369 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2370 | seq_printf(m, "\tversion found: %d.%d\n", | |
2371 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2372 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2373 | huc_fw->header_offset, huc_fw->header_size); | |
2374 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2375 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2376 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2377 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2378 | ||
3582ad13 | 2379 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2380 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2381 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2382 | |
2383 | return 0; | |
2384 | } | |
2385 | ||
fdf5d357 AD |
2386 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2387 | { | |
36cdd013 | 2388 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2389 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2390 | u32 tmp, i; |
2391 | ||
2d1fe073 | 2392 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2393 | return 0; |
2394 | ||
2395 | seq_printf(m, "GuC firmware status:\n"); | |
2396 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2397 | guc_fw->path); |
fdf5d357 | 2398 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2399 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2400 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2401 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2402 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2403 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2404 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2405 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2406 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2407 | guc_fw->header_offset, guc_fw->header_size); | |
2408 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2409 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2410 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2411 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2412 | |
3582ad13 | 2413 | intel_runtime_pm_get(dev_priv); |
2414 | ||
fdf5d357 AD |
2415 | tmp = I915_READ(GUC_STATUS); |
2416 | ||
2417 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2418 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2419 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2420 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2421 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2422 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2423 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2424 | seq_puts(m, "\nScratch registers:\n"); | |
2425 | for (i = 0; i < 16; i++) | |
2426 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2427 | ||
3582ad13 | 2428 | intel_runtime_pm_put(dev_priv); |
2429 | ||
fdf5d357 AD |
2430 | return 0; |
2431 | } | |
2432 | ||
5aa1ee4b AG |
2433 | static void i915_guc_log_info(struct seq_file *m, |
2434 | struct drm_i915_private *dev_priv) | |
2435 | { | |
2436 | struct intel_guc *guc = &dev_priv->guc; | |
2437 | ||
2438 | seq_puts(m, "\nGuC logging stats:\n"); | |
2439 | ||
2440 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2441 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2442 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2443 | ||
2444 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2445 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2446 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2447 | ||
2448 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2449 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2450 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2451 | ||
2452 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2453 | guc->log.flush_interrupt_count); | |
2454 | ||
2455 | seq_printf(m, "\tCapture miss count: %u\n", | |
2456 | guc->log.capture_miss_count); | |
2457 | } | |
2458 | ||
8b417c26 DG |
2459 | static void i915_guc_client_info(struct seq_file *m, |
2460 | struct drm_i915_private *dev_priv, | |
2461 | struct i915_guc_client *client) | |
2462 | { | |
e2f80391 | 2463 | struct intel_engine_cs *engine; |
c18468c4 | 2464 | enum intel_engine_id id; |
8b417c26 | 2465 | uint64_t tot = 0; |
8b417c26 DG |
2466 | |
2467 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2468 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2469 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2470 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2471 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2472 | client->wq_size, client->wq_offset, client->wq_tail); | |
2473 | ||
551aaecd | 2474 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2475 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2476 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2477 | ||
3b3f1650 | 2478 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2479 | u64 submissions = client->submissions[id]; |
2480 | tot += submissions; | |
8b417c26 | 2481 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2482 | submissions, engine->name); |
8b417c26 DG |
2483 | } |
2484 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2485 | } | |
2486 | ||
2487 | static int i915_guc_info(struct seq_file *m, void *data) | |
2488 | { | |
36cdd013 | 2489 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2490 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2491 | struct intel_engine_cs *engine; |
c18468c4 | 2492 | enum intel_engine_id id; |
334636c6 | 2493 | u64 total; |
8b417c26 | 2494 | |
334636c6 CW |
2495 | if (!guc->execbuf_client) { |
2496 | seq_printf(m, "GuC submission %s\n", | |
2497 | HAS_GUC_SCHED(dev_priv) ? | |
2498 | "disabled" : | |
2499 | "not supported"); | |
5a843307 | 2500 | return 0; |
334636c6 | 2501 | } |
8b417c26 | 2502 | |
9636f6db | 2503 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2504 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2505 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2506 | |
334636c6 CW |
2507 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2508 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2509 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2510 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2511 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2512 | |
334636c6 | 2513 | total = 0; |
8b417c26 | 2514 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2515 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2516 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2517 | total += submissions; |
397097b0 | 2518 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2519 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2520 | } |
2521 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2522 | ||
334636c6 CW |
2523 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2524 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2525 | |
5aa1ee4b AG |
2526 | i915_guc_log_info(m, dev_priv); |
2527 | ||
8b417c26 DG |
2528 | /* Add more as required ... */ |
2529 | ||
2530 | return 0; | |
2531 | } | |
2532 | ||
4c7e77fc AD |
2533 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2534 | { | |
36cdd013 | 2535 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2536 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2537 | int i = 0, pg; |
2538 | ||
d6b40b4b | 2539 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2540 | return 0; |
2541 | ||
d6b40b4b | 2542 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2543 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2544 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2545 | |
2546 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2547 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2548 | *(log + i), *(log + i + 1), | |
2549 | *(log + i + 2), *(log + i + 3)); | |
2550 | ||
2551 | kunmap_atomic(log); | |
2552 | } | |
2553 | ||
2554 | seq_putc(m, '\n'); | |
2555 | ||
2556 | return 0; | |
2557 | } | |
2558 | ||
685534ef SAK |
2559 | static int i915_guc_log_control_get(void *data, u64 *val) |
2560 | { | |
2561 | struct drm_device *dev = data; | |
2562 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2563 | ||
2564 | if (!dev_priv->guc.log.vma) | |
2565 | return -EINVAL; | |
2566 | ||
2567 | *val = i915.guc_log_level; | |
2568 | ||
2569 | return 0; | |
2570 | } | |
2571 | ||
2572 | static int i915_guc_log_control_set(void *data, u64 val) | |
2573 | { | |
2574 | struct drm_device *dev = data; | |
2575 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2576 | int ret; | |
2577 | ||
2578 | if (!dev_priv->guc.log.vma) | |
2579 | return -EINVAL; | |
2580 | ||
2581 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2582 | if (ret) | |
2583 | return ret; | |
2584 | ||
2585 | intel_runtime_pm_get(dev_priv); | |
2586 | ret = i915_guc_log_control(dev_priv, val); | |
2587 | intel_runtime_pm_put(dev_priv); | |
2588 | ||
2589 | mutex_unlock(&dev->struct_mutex); | |
2590 | return ret; | |
2591 | } | |
2592 | ||
2593 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2594 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2595 | "%lld\n"); | |
2596 | ||
b86bef20 CW |
2597 | static const char *psr2_live_status(u32 val) |
2598 | { | |
2599 | static const char * const live_status[] = { | |
2600 | "IDLE", | |
2601 | "CAPTURE", | |
2602 | "CAPTURE_FS", | |
2603 | "SLEEP", | |
2604 | "BUFON_FW", | |
2605 | "ML_UP", | |
2606 | "SU_STANDBY", | |
2607 | "FAST_SLEEP", | |
2608 | "DEEP_SLEEP", | |
2609 | "BUF_ON", | |
2610 | "TG_ON" | |
2611 | }; | |
2612 | ||
2613 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2614 | if (val < ARRAY_SIZE(live_status)) | |
2615 | return live_status[val]; | |
2616 | ||
2617 | return "unknown"; | |
2618 | } | |
2619 | ||
e91fd8c6 RV |
2620 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2621 | { | |
36cdd013 | 2622 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2623 | u32 psrperf = 0; |
a6cbdb8e RV |
2624 | u32 stat[3]; |
2625 | enum pipe pipe; | |
a031d709 | 2626 | bool enabled = false; |
e91fd8c6 | 2627 | |
36cdd013 | 2628 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2629 | seq_puts(m, "PSR not supported\n"); |
2630 | return 0; | |
2631 | } | |
2632 | ||
c8c8fb33 PZ |
2633 | intel_runtime_pm_get(dev_priv); |
2634 | ||
fa128fa6 | 2635 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2636 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2637 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2638 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2639 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2640 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2641 | dev_priv->psr.busy_frontbuffer_bits); | |
2642 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2643 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2644 | |
7e3eb599 NV |
2645 | if (HAS_DDI(dev_priv)) { |
2646 | if (dev_priv->psr.psr2_support) | |
2647 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2648 | else | |
2649 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2650 | } else { | |
3553a8ea | 2651 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2652 | enum transcoder cpu_transcoder = |
2653 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2654 | enum intel_display_power_domain power_domain; | |
2655 | ||
2656 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2657 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2658 | power_domain)) | |
2659 | continue; | |
2660 | ||
3553a8ea DL |
2661 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2662 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2663 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2664 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2665 | enabled = true; | |
9c870d03 CW |
2666 | |
2667 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2668 | } |
2669 | } | |
60e5ffe3 RV |
2670 | |
2671 | seq_printf(m, "Main link in standby mode: %s\n", | |
2672 | yesno(dev_priv->psr.link_standby)); | |
2673 | ||
a6cbdb8e RV |
2674 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2675 | ||
36cdd013 | 2676 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2677 | for_each_pipe(dev_priv, pipe) { |
2678 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2679 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2680 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2681 | } | |
2682 | seq_puts(m, "\n"); | |
e91fd8c6 | 2683 | |
05eec3c2 RV |
2684 | /* |
2685 | * VLV/CHV PSR has no kind of performance counter | |
2686 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2687 | */ | |
36cdd013 | 2688 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2689 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2690 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2691 | |
2692 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2693 | } | |
6ba1f9e1 | 2694 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2695 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2696 | ||
2697 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2698 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2699 | } |
fa128fa6 | 2700 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2701 | |
c8c8fb33 | 2702 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2703 | return 0; |
2704 | } | |
2705 | ||
d2e216d0 RV |
2706 | static int i915_sink_crc(struct seq_file *m, void *data) |
2707 | { | |
36cdd013 DW |
2708 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2709 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2710 | struct intel_connector *connector; |
3f6a5e1e | 2711 | struct drm_connector_list_iter conn_iter; |
d2e216d0 RV |
2712 | struct intel_dp *intel_dp = NULL; |
2713 | int ret; | |
2714 | u8 crc[6]; | |
2715 | ||
2716 | drm_modeset_lock_all(dev); | |
3f6a5e1e DV |
2717 | drm_connector_list_iter_begin(dev, &conn_iter); |
2718 | for_each_intel_connector_iter(connector, &conn_iter) { | |
26c17cf6 | 2719 | struct drm_crtc *crtc; |
d2e216d0 | 2720 | |
26c17cf6 | 2721 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2722 | continue; |
2723 | ||
26c17cf6 ML |
2724 | crtc = connector->base.state->crtc; |
2725 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2726 | continue; |
2727 | ||
26c17cf6 | 2728 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2729 | continue; |
2730 | ||
26c17cf6 | 2731 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2732 | |
2733 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2734 | if (ret) | |
2735 | goto out; | |
2736 | ||
2737 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2738 | crc[0], crc[1], crc[2], | |
2739 | crc[3], crc[4], crc[5]); | |
2740 | goto out; | |
2741 | } | |
2742 | ret = -ENODEV; | |
2743 | out: | |
3f6a5e1e | 2744 | drm_connector_list_iter_end(&conn_iter); |
d2e216d0 RV |
2745 | drm_modeset_unlock_all(dev); |
2746 | return ret; | |
2747 | } | |
2748 | ||
ec013e7f JB |
2749 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2750 | { | |
36cdd013 | 2751 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2752 | u64 power; |
2753 | u32 units; | |
2754 | ||
36cdd013 | 2755 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2756 | return -ENODEV; |
2757 | ||
36623ef8 PZ |
2758 | intel_runtime_pm_get(dev_priv); |
2759 | ||
ec013e7f JB |
2760 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2761 | power = (power & 0x1f00) >> 8; | |
2762 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2763 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2764 | power *= units; | |
2765 | ||
36623ef8 PZ |
2766 | intel_runtime_pm_put(dev_priv); |
2767 | ||
ec013e7f | 2768 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2769 | |
2770 | return 0; | |
2771 | } | |
2772 | ||
6455c870 | 2773 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2774 | { |
36cdd013 | 2775 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2776 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2777 | |
a156e64d CW |
2778 | if (!HAS_RUNTIME_PM(dev_priv)) |
2779 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2780 | |
67d97da3 | 2781 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2782 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2783 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2784 | #ifdef CONFIG_PM |
a6aaec8b | 2785 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2786 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2787 | #else |
2788 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2789 | #endif | |
a156e64d | 2790 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2791 | pci_power_name(pdev->current_state), |
2792 | pdev->current_state); | |
371db66a | 2793 | |
ec013e7f JB |
2794 | return 0; |
2795 | } | |
2796 | ||
1da51581 ID |
2797 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2798 | { | |
36cdd013 | 2799 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2800 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2801 | int i; | |
2802 | ||
2803 | mutex_lock(&power_domains->lock); | |
2804 | ||
2805 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2806 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2807 | struct i915_power_well *power_well; | |
2808 | enum intel_display_power_domain power_domain; | |
2809 | ||
2810 | power_well = &power_domains->power_wells[i]; | |
2811 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2812 | power_well->count); | |
2813 | ||
8385c2ec | 2814 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2815 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2816 | intel_display_power_domain_str(power_domain), |
1da51581 | 2817 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2818 | } |
2819 | ||
2820 | mutex_unlock(&power_domains->lock); | |
2821 | ||
2822 | return 0; | |
2823 | } | |
2824 | ||
b7cec66d DL |
2825 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2826 | { | |
36cdd013 | 2827 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2828 | struct intel_csr *csr; |
2829 | ||
36cdd013 | 2830 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2831 | seq_puts(m, "not supported\n"); |
2832 | return 0; | |
2833 | } | |
2834 | ||
2835 | csr = &dev_priv->csr; | |
2836 | ||
6fb403de MK |
2837 | intel_runtime_pm_get(dev_priv); |
2838 | ||
b7cec66d DL |
2839 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2840 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2841 | ||
2842 | if (!csr->dmc_payload) | |
6fb403de | 2843 | goto out; |
b7cec66d DL |
2844 | |
2845 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2846 | CSR_VERSION_MINOR(csr->version)); | |
2847 | ||
36cdd013 | 2848 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2849 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2850 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2851 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2852 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2853 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2854 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2855 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2856 | } |
2857 | ||
6fb403de MK |
2858 | out: |
2859 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2860 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2861 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2862 | ||
8337206d DL |
2863 | intel_runtime_pm_put(dev_priv); |
2864 | ||
b7cec66d DL |
2865 | return 0; |
2866 | } | |
2867 | ||
53f5e3ca JB |
2868 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2869 | struct drm_display_mode *mode) | |
2870 | { | |
2871 | int i; | |
2872 | ||
2873 | for (i = 0; i < tabs; i++) | |
2874 | seq_putc(m, '\t'); | |
2875 | ||
2876 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2877 | mode->base.id, mode->name, | |
2878 | mode->vrefresh, mode->clock, | |
2879 | mode->hdisplay, mode->hsync_start, | |
2880 | mode->hsync_end, mode->htotal, | |
2881 | mode->vdisplay, mode->vsync_start, | |
2882 | mode->vsync_end, mode->vtotal, | |
2883 | mode->type, mode->flags); | |
2884 | } | |
2885 | ||
2886 | static void intel_encoder_info(struct seq_file *m, | |
2887 | struct intel_crtc *intel_crtc, | |
2888 | struct intel_encoder *intel_encoder) | |
2889 | { | |
36cdd013 DW |
2890 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2891 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2892 | struct drm_crtc *crtc = &intel_crtc->base; |
2893 | struct intel_connector *intel_connector; | |
2894 | struct drm_encoder *encoder; | |
2895 | ||
2896 | encoder = &intel_encoder->base; | |
2897 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2898 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2899 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2900 | struct drm_connector *connector = &intel_connector->base; | |
2901 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2902 | connector->base.id, | |
c23cc417 | 2903 | connector->name, |
53f5e3ca JB |
2904 | drm_get_connector_status_name(connector->status)); |
2905 | if (connector->status == connector_status_connected) { | |
2906 | struct drm_display_mode *mode = &crtc->mode; | |
2907 | seq_printf(m, ", mode:\n"); | |
2908 | intel_seq_print_mode(m, 2, mode); | |
2909 | } else { | |
2910 | seq_putc(m, '\n'); | |
2911 | } | |
2912 | } | |
2913 | } | |
2914 | ||
2915 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2916 | { | |
36cdd013 DW |
2917 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2918 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2919 | struct drm_crtc *crtc = &intel_crtc->base; |
2920 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2921 | struct drm_plane_state *plane_state = crtc->primary->state; |
2922 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2923 | |
23a48d53 | 2924 | if (fb) |
5aa8a937 | 2925 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2926 | fb->base.id, plane_state->src_x >> 16, |
2927 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2928 | else |
2929 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2930 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2931 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2932 | } | |
2933 | ||
2934 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2935 | { | |
2936 | struct drm_display_mode *mode = panel->fixed_mode; | |
2937 | ||
2938 | seq_printf(m, "\tfixed mode:\n"); | |
2939 | intel_seq_print_mode(m, 2, mode); | |
2940 | } | |
2941 | ||
2942 | static void intel_dp_info(struct seq_file *m, | |
2943 | struct intel_connector *intel_connector) | |
2944 | { | |
2945 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2946 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2947 | ||
2948 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2949 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2950 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2951 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2952 | |
2953 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2954 | &intel_dp->aux); | |
53f5e3ca JB |
2955 | } |
2956 | ||
9a148a96 LY |
2957 | static void intel_dp_mst_info(struct seq_file *m, |
2958 | struct intel_connector *intel_connector) | |
2959 | { | |
2960 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2961 | struct intel_dp_mst_encoder *intel_mst = | |
2962 | enc_to_mst(&intel_encoder->base); | |
2963 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2964 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2965 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2966 | intel_connector->port); | |
2967 | ||
2968 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2969 | } | |
2970 | ||
53f5e3ca JB |
2971 | static void intel_hdmi_info(struct seq_file *m, |
2972 | struct intel_connector *intel_connector) | |
2973 | { | |
2974 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2975 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2976 | ||
742f491d | 2977 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2978 | } |
2979 | ||
2980 | static void intel_lvds_info(struct seq_file *m, | |
2981 | struct intel_connector *intel_connector) | |
2982 | { | |
2983 | intel_panel_info(m, &intel_connector->panel); | |
2984 | } | |
2985 | ||
2986 | static void intel_connector_info(struct seq_file *m, | |
2987 | struct drm_connector *connector) | |
2988 | { | |
2989 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2990 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2991 | struct drm_display_mode *mode; |
53f5e3ca JB |
2992 | |
2993 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2994 | connector->base.id, connector->name, |
53f5e3ca JB |
2995 | drm_get_connector_status_name(connector->status)); |
2996 | if (connector->status == connector_status_connected) { | |
2997 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2998 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2999 | connector->display_info.width_mm, | |
3000 | connector->display_info.height_mm); | |
3001 | seq_printf(m, "\tsubpixel order: %s\n", | |
3002 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3003 | seq_printf(m, "\tCEA rev: %d\n", | |
3004 | connector->display_info.cea_rev); | |
3005 | } | |
ee648a74 ML |
3006 | |
3007 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3008 | return; | |
3009 | ||
3010 | switch (connector->connector_type) { | |
3011 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3012 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3013 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3014 | intel_dp_mst_info(m, intel_connector); | |
3015 | else | |
3016 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3017 | break; |
3018 | case DRM_MODE_CONNECTOR_LVDS: | |
3019 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3020 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3021 | break; |
3022 | case DRM_MODE_CONNECTOR_HDMIA: | |
3023 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3024 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3025 | intel_hdmi_info(m, intel_connector); | |
3026 | break; | |
3027 | default: | |
3028 | break; | |
36cd7444 | 3029 | } |
53f5e3ca | 3030 | |
f103fc7d JB |
3031 | seq_printf(m, "\tmodes:\n"); |
3032 | list_for_each_entry(mode, &connector->modes, head) | |
3033 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3034 | } |
3035 | ||
36cdd013 | 3036 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 3037 | { |
065f2ec2 CW |
3038 | u32 state; |
3039 | ||
2a307c2e | 3040 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3041 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3042 | else |
5efb3e28 | 3043 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3044 | |
3045 | return state; | |
3046 | } | |
3047 | ||
36cdd013 DW |
3048 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3049 | int pipe, int *x, int *y) | |
065f2ec2 | 3050 | { |
065f2ec2 CW |
3051 | u32 pos; |
3052 | ||
5efb3e28 | 3053 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3054 | |
3055 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3056 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3057 | *x = -*x; | |
3058 | ||
3059 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3060 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3061 | *y = -*y; | |
3062 | ||
36cdd013 | 3063 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3064 | } |
3065 | ||
3abc4e09 RF |
3066 | static const char *plane_type(enum drm_plane_type type) |
3067 | { | |
3068 | switch (type) { | |
3069 | case DRM_PLANE_TYPE_OVERLAY: | |
3070 | return "OVL"; | |
3071 | case DRM_PLANE_TYPE_PRIMARY: | |
3072 | return "PRI"; | |
3073 | case DRM_PLANE_TYPE_CURSOR: | |
3074 | return "CUR"; | |
3075 | /* | |
3076 | * Deliberately omitting default: to generate compiler warnings | |
3077 | * when a new drm_plane_type gets added. | |
3078 | */ | |
3079 | } | |
3080 | ||
3081 | return "unknown"; | |
3082 | } | |
3083 | ||
3084 | static const char *plane_rotation(unsigned int rotation) | |
3085 | { | |
3086 | static char buf[48]; | |
3087 | /* | |
3088 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3089 | * will print them all to visualize if the values are misused | |
3090 | */ | |
3091 | snprintf(buf, sizeof(buf), | |
3092 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3093 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3094 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3095 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3096 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3097 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3098 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3099 | rotation); |
3100 | ||
3101 | return buf; | |
3102 | } | |
3103 | ||
3104 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3105 | { | |
36cdd013 DW |
3106 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3107 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3108 | struct intel_plane *intel_plane; |
3109 | ||
3110 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3111 | struct drm_plane_state *state; | |
3112 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3113 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3114 | |
3115 | if (!plane->state) { | |
3116 | seq_puts(m, "plane->state is NULL!\n"); | |
3117 | continue; | |
3118 | } | |
3119 | ||
3120 | state = plane->state; | |
3121 | ||
90844f00 | 3122 | if (state->fb) { |
438b74a5 VS |
3123 | drm_get_format_name(state->fb->format->format, |
3124 | &format_name); | |
90844f00 | 3125 | } else { |
b3c11ac2 | 3126 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3127 | } |
3128 | ||
3abc4e09 RF |
3129 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3130 | plane->base.id, | |
3131 | plane_type(intel_plane->base.type), | |
3132 | state->crtc_x, state->crtc_y, | |
3133 | state->crtc_w, state->crtc_h, | |
3134 | (state->src_x >> 16), | |
3135 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3136 | (state->src_y >> 16), | |
3137 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3138 | (state->src_w >> 16), | |
3139 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3140 | (state->src_h >> 16), | |
3141 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3142 | format_name.str, |
3abc4e09 RF |
3143 | plane_rotation(state->rotation)); |
3144 | } | |
3145 | } | |
3146 | ||
3147 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3148 | { | |
3149 | struct intel_crtc_state *pipe_config; | |
3150 | int num_scalers = intel_crtc->num_scalers; | |
3151 | int i; | |
3152 | ||
3153 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3154 | ||
3155 | /* Not all platformas have a scaler */ | |
3156 | if (num_scalers) { | |
3157 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3158 | num_scalers, | |
3159 | pipe_config->scaler_state.scaler_users, | |
3160 | pipe_config->scaler_state.scaler_id); | |
3161 | ||
58415918 | 3162 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3163 | struct intel_scaler *sc = |
3164 | &pipe_config->scaler_state.scalers[i]; | |
3165 | ||
3166 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3167 | i, yesno(sc->in_use), sc->mode); | |
3168 | } | |
3169 | seq_puts(m, "\n"); | |
3170 | } else { | |
3171 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3172 | } | |
3173 | } | |
3174 | ||
53f5e3ca JB |
3175 | static int i915_display_info(struct seq_file *m, void *unused) |
3176 | { | |
36cdd013 DW |
3177 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3178 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3179 | struct intel_crtc *crtc; |
53f5e3ca | 3180 | struct drm_connector *connector; |
3f6a5e1e | 3181 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3182 | |
b0e5ddf3 | 3183 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3184 | seq_printf(m, "CRTC info\n"); |
3185 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3186 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3187 | bool active; |
f77076c9 | 3188 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3189 | int x, y; |
53f5e3ca | 3190 | |
3f6a5e1e | 3191 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3192 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3193 | ||
3abc4e09 | 3194 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3195 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3196 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3197 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3198 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3199 | ||
f77076c9 | 3200 | if (pipe_config->base.active) { |
065f2ec2 CW |
3201 | intel_crtc_info(m, crtc); |
3202 | ||
36cdd013 | 3203 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3204 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3205 | yesno(crtc->cursor_base), |
3dd512fb MR |
3206 | x, y, crtc->base.cursor->state->crtc_w, |
3207 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3208 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3209 | intel_scaler_info(m, crtc); |
3210 | intel_plane_info(m, crtc); | |
a23dc658 | 3211 | } |
cace841c DV |
3212 | |
3213 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3214 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3215 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3216 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3217 | } |
3218 | ||
3219 | seq_printf(m, "\n"); | |
3220 | seq_printf(m, "Connector info\n"); | |
3221 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3222 | mutex_lock(&dev->mode_config.mutex); |
3223 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3224 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3225 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3226 | drm_connector_list_iter_end(&conn_iter); |
3227 | mutex_unlock(&dev->mode_config.mutex); | |
3228 | ||
b0e5ddf3 | 3229 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3230 | |
3231 | return 0; | |
3232 | } | |
3233 | ||
1b36595f CW |
3234 | static int i915_engine_info(struct seq_file *m, void *unused) |
3235 | { | |
3236 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3237 | struct intel_engine_cs *engine; | |
3b3f1650 | 3238 | enum intel_engine_id id; |
1b36595f | 3239 | |
9c870d03 CW |
3240 | intel_runtime_pm_get(dev_priv); |
3241 | ||
f73b5674 CW |
3242 | seq_printf(m, "GT awake? %s\n", |
3243 | yesno(dev_priv->gt.awake)); | |
3244 | seq_printf(m, "Global active requests: %d\n", | |
3245 | dev_priv->gt.active_requests); | |
3246 | ||
3b3f1650 | 3247 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3248 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3249 | struct drm_i915_gem_request *rq; | |
3250 | struct rb_node *rb; | |
3251 | u64 addr; | |
3252 | ||
3253 | seq_printf(m, "%s\n", engine->name); | |
f73b5674 | 3254 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", |
1b36595f | 3255 | intel_engine_get_seqno(engine), |
cb399eab | 3256 | intel_engine_last_submit(engine), |
1b36595f | 3257 | engine->hangcheck.seqno, |
f73b5674 CW |
3258 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), |
3259 | engine->timeline->inflight_seqnos); | |
1b36595f CW |
3260 | |
3261 | rcu_read_lock(); | |
3262 | ||
3263 | seq_printf(m, "\tRequests:\n"); | |
3264 | ||
73cb9701 CW |
3265 | rq = list_first_entry(&engine->timeline->requests, |
3266 | struct drm_i915_gem_request, link); | |
3267 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3268 | print_request(m, rq, "\t\tfirst "); |
3269 | ||
73cb9701 CW |
3270 | rq = list_last_entry(&engine->timeline->requests, |
3271 | struct drm_i915_gem_request, link); | |
3272 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3273 | print_request(m, rq, "\t\tlast "); |
3274 | ||
3275 | rq = i915_gem_find_active_request(engine); | |
3276 | if (rq) { | |
3277 | print_request(m, rq, "\t\tactive "); | |
3278 | seq_printf(m, | |
3279 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3280 | rq->head, rq->postfix, rq->tail, | |
3281 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3282 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3283 | } | |
3284 | ||
3285 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3286 | I915_READ(RING_START(engine->mmio_base)), | |
3287 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3288 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3289 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3290 | rq ? rq->ring->head : 0); | |
3291 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3292 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3293 | rq ? rq->ring->tail : 0); | |
3294 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3295 | I915_READ(RING_CTL(engine->mmio_base)), | |
3296 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3297 | ||
3298 | rcu_read_unlock(); | |
3299 | ||
3300 | addr = intel_engine_get_active_head(engine); | |
3301 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3302 | upper_32_bits(addr), lower_32_bits(addr)); | |
3303 | addr = intel_engine_get_last_batch_head(engine); | |
3304 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3305 | upper_32_bits(addr), lower_32_bits(addr)); | |
3306 | ||
3307 | if (i915.enable_execlists) { | |
3308 | u32 ptr, read, write; | |
20311bd3 | 3309 | struct rb_node *rb; |
1b36595f CW |
3310 | |
3311 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3312 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3313 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3314 | ||
3315 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3316 | read = GEN8_CSB_READ_PTR(ptr); | |
3317 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3318 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3319 | read, write); | |
3320 | if (read >= GEN8_CSB_ENTRIES) | |
3321 | read = 0; | |
3322 | if (write >= GEN8_CSB_ENTRIES) | |
3323 | write = 0; | |
3324 | if (read > write) | |
3325 | write += GEN8_CSB_ENTRIES; | |
3326 | while (read < write) { | |
3327 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3328 | ||
3329 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3330 | idx, | |
3331 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3332 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3333 | } | |
3334 | ||
3335 | rcu_read_lock(); | |
3336 | rq = READ_ONCE(engine->execlist_port[0].request); | |
816ee798 CW |
3337 | if (rq) { |
3338 | seq_printf(m, "\t\tELSP[0] count=%d, ", | |
3339 | engine->execlist_port[0].count); | |
3340 | print_request(m, rq, "rq: "); | |
3341 | } else { | |
1b36595f | 3342 | seq_printf(m, "\t\tELSP[0] idle\n"); |
816ee798 | 3343 | } |
1b36595f | 3344 | rq = READ_ONCE(engine->execlist_port[1].request); |
816ee798 CW |
3345 | if (rq) { |
3346 | seq_printf(m, "\t\tELSP[1] count=%d, ", | |
3347 | engine->execlist_port[1].count); | |
3348 | print_request(m, rq, "rq: "); | |
3349 | } else { | |
1b36595f | 3350 | seq_printf(m, "\t\tELSP[1] idle\n"); |
816ee798 | 3351 | } |
1b36595f | 3352 | rcu_read_unlock(); |
c8247c06 | 3353 | |
663f71e7 | 3354 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3355 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3356 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3357 | print_request(m, rq, "\t\tQ "); |
3358 | } | |
663f71e7 | 3359 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3360 | } else if (INTEL_GEN(dev_priv) > 6) { |
3361 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3362 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3363 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3364 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3365 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3366 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3367 | } | |
3368 | ||
61d3dc70 | 3369 | spin_lock_irq(&b->rb_lock); |
1b36595f | 3370 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3371 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3372 | |
3373 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3374 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3375 | } | |
61d3dc70 | 3376 | spin_unlock_irq(&b->rb_lock); |
1b36595f CW |
3377 | |
3378 | seq_puts(m, "\n"); | |
3379 | } | |
3380 | ||
9c870d03 CW |
3381 | intel_runtime_pm_put(dev_priv); |
3382 | ||
1b36595f CW |
3383 | return 0; |
3384 | } | |
3385 | ||
e04934cf BW |
3386 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3387 | { | |
36cdd013 DW |
3388 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3389 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3390 | struct intel_engine_cs *engine; |
36cdd013 | 3391 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3392 | enum intel_engine_id id; |
3393 | int j, ret; | |
e04934cf | 3394 | |
39df9190 | 3395 | if (!i915.semaphores) { |
e04934cf BW |
3396 | seq_puts(m, "Semaphores are disabled\n"); |
3397 | return 0; | |
3398 | } | |
3399 | ||
3400 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3401 | if (ret) | |
3402 | return ret; | |
03872064 | 3403 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3404 | |
36cdd013 | 3405 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3406 | struct page *page; |
3407 | uint64_t *seqno; | |
3408 | ||
51d545d0 | 3409 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3410 | |
3411 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3412 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3413 | uint64_t offset; |
3414 | ||
e2f80391 | 3415 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3416 | |
3417 | seq_puts(m, " Last signal:"); | |
3418 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3419 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3420 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3421 | seqno[offset], offset * 8); | |
3422 | } | |
3423 | seq_putc(m, '\n'); | |
3424 | ||
3425 | seq_puts(m, " Last wait: "); | |
3426 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3427 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3428 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3429 | seqno[offset], offset * 8); | |
3430 | } | |
3431 | seq_putc(m, '\n'); | |
3432 | ||
3433 | } | |
3434 | kunmap_atomic(seqno); | |
3435 | } else { | |
3436 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3437 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3438 | for (j = 0; j < num_rings; j++) |
3439 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3440 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3441 | seq_putc(m, '\n'); |
3442 | } | |
3443 | ||
03872064 | 3444 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3445 | mutex_unlock(&dev->struct_mutex); |
3446 | return 0; | |
3447 | } | |
3448 | ||
728e29d7 DV |
3449 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3450 | { | |
36cdd013 DW |
3451 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3452 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3453 | int i; |
3454 | ||
3455 | drm_modeset_lock_all(dev); | |
3456 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3457 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3458 | ||
3459 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3460 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3461 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3462 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3463 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3464 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3465 | pll->state.hw_state.dpll_md); |
3466 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3467 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3468 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3469 | } |
3470 | drm_modeset_unlock_all(dev); | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
1ed1ef9d | 3475 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3476 | { |
3477 | int i; | |
3478 | int ret; | |
e2f80391 | 3479 | struct intel_engine_cs *engine; |
36cdd013 DW |
3480 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3481 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3482 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3483 | enum intel_engine_id id; |
888b5995 | 3484 | |
888b5995 AS |
3485 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3486 | if (ret) | |
3487 | return ret; | |
3488 | ||
3489 | intel_runtime_pm_get(dev_priv); | |
3490 | ||
33136b06 | 3491 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3492 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3493 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3494 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3495 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3496 | i915_reg_t addr; |
3497 | u32 mask, value, read; | |
2fa60f6d | 3498 | bool ok; |
888b5995 | 3499 | |
33136b06 AS |
3500 | addr = workarounds->reg[i].addr; |
3501 | mask = workarounds->reg[i].mask; | |
3502 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3503 | read = I915_READ(addr); |
3504 | ok = (value & mask) == (read & mask); | |
3505 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3506 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3507 | } |
3508 | ||
3509 | intel_runtime_pm_put(dev_priv); | |
3510 | mutex_unlock(&dev->struct_mutex); | |
3511 | ||
3512 | return 0; | |
3513 | } | |
3514 | ||
c5511e44 DL |
3515 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3516 | { | |
36cdd013 DW |
3517 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3518 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3519 | struct skl_ddb_allocation *ddb; |
3520 | struct skl_ddb_entry *entry; | |
3521 | enum pipe pipe; | |
3522 | int plane; | |
3523 | ||
36cdd013 | 3524 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3525 | return 0; |
3526 | ||
c5511e44 DL |
3527 | drm_modeset_lock_all(dev); |
3528 | ||
3529 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3530 | ||
3531 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3532 | ||
3533 | for_each_pipe(dev_priv, pipe) { | |
3534 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3535 | ||
8b364b41 | 3536 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3537 | entry = &ddb->plane[pipe][plane]; |
3538 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3539 | entry->start, entry->end, | |
3540 | skl_ddb_entry_size(entry)); | |
3541 | } | |
3542 | ||
4969d33e | 3543 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3544 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3545 | entry->end, skl_ddb_entry_size(entry)); | |
3546 | } | |
3547 | ||
3548 | drm_modeset_unlock_all(dev); | |
3549 | ||
3550 | return 0; | |
3551 | } | |
3552 | ||
a54746e3 | 3553 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3554 | struct drm_device *dev, |
3555 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3556 | { |
fac5e23e | 3557 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3558 | struct i915_drrs *drrs = &dev_priv->drrs; |
3559 | int vrefresh = 0; | |
26875fe5 | 3560 | struct drm_connector *connector; |
3f6a5e1e | 3561 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3562 | |
3f6a5e1e DV |
3563 | drm_connector_list_iter_begin(dev, &conn_iter); |
3564 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3565 | if (connector->state->crtc != &intel_crtc->base) |
3566 | continue; | |
3567 | ||
3568 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3569 | } |
3f6a5e1e | 3570 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3571 | |
3572 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3573 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3574 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3575 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3576 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3577 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3578 | else | |
3579 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3580 | ||
3581 | seq_puts(m, "\n\n"); | |
3582 | ||
f77076c9 | 3583 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3584 | struct intel_panel *panel; |
3585 | ||
3586 | mutex_lock(&drrs->mutex); | |
3587 | /* DRRS Supported */ | |
3588 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3589 | ||
3590 | /* disable_drrs() will make drrs->dp NULL */ | |
3591 | if (!drrs->dp) { | |
3592 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3593 | mutex_unlock(&drrs->mutex); | |
3594 | return; | |
3595 | } | |
3596 | ||
3597 | panel = &drrs->dp->attached_connector->panel; | |
3598 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3599 | drrs->busy_frontbuffer_bits); | |
3600 | ||
3601 | seq_puts(m, "\n\t\t"); | |
3602 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3603 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3604 | vrefresh = panel->fixed_mode->vrefresh; | |
3605 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3606 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3607 | vrefresh = panel->downclock_mode->vrefresh; | |
3608 | } else { | |
3609 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3610 | drrs->refresh_rate_type); | |
3611 | mutex_unlock(&drrs->mutex); | |
3612 | return; | |
3613 | } | |
3614 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3615 | ||
3616 | seq_puts(m, "\n\t\t"); | |
3617 | mutex_unlock(&drrs->mutex); | |
3618 | } else { | |
3619 | /* DRRS not supported. Print the VBT parameter*/ | |
3620 | seq_puts(m, "\tDRRS Supported : No"); | |
3621 | } | |
3622 | seq_puts(m, "\n"); | |
3623 | } | |
3624 | ||
3625 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3626 | { | |
36cdd013 DW |
3627 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3628 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3629 | struct intel_crtc *intel_crtc; |
3630 | int active_crtc_cnt = 0; | |
3631 | ||
26875fe5 | 3632 | drm_modeset_lock_all(dev); |
a54746e3 | 3633 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3634 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3635 | active_crtc_cnt++; |
3636 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3637 | ||
3638 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3639 | } | |
a54746e3 | 3640 | } |
26875fe5 | 3641 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3642 | |
3643 | if (!active_crtc_cnt) | |
3644 | seq_puts(m, "No active crtc found\n"); | |
3645 | ||
3646 | return 0; | |
3647 | } | |
3648 | ||
11bed958 DA |
3649 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3650 | { | |
36cdd013 DW |
3651 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3652 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3653 | struct intel_encoder *intel_encoder; |
3654 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3655 | struct drm_connector *connector; |
3f6a5e1e | 3656 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3657 | |
3f6a5e1e DV |
3658 | drm_connector_list_iter_begin(dev, &conn_iter); |
3659 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3660 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3661 | continue; |
b6dabe3b ML |
3662 | |
3663 | intel_encoder = intel_attached_encoder(connector); | |
3664 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3665 | continue; | |
3666 | ||
3667 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3668 | if (!intel_dig_port->dp.can_mst) |
3669 | continue; | |
b6dabe3b | 3670 | |
40ae80cc JB |
3671 | seq_printf(m, "MST Source Port %c\n", |
3672 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3673 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3674 | } | |
3f6a5e1e DV |
3675 | drm_connector_list_iter_end(&conn_iter); |
3676 | ||
11bed958 DA |
3677 | return 0; |
3678 | } | |
3679 | ||
eb3394fa | 3680 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3681 | const char __user *ubuf, |
3682 | size_t len, loff_t *offp) | |
eb3394fa TP |
3683 | { |
3684 | char *input_buffer; | |
3685 | int status = 0; | |
eb3394fa TP |
3686 | struct drm_device *dev; |
3687 | struct drm_connector *connector; | |
3f6a5e1e | 3688 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3689 | struct intel_dp *intel_dp; |
3690 | int val = 0; | |
3691 | ||
9aaffa34 | 3692 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3693 | |
eb3394fa TP |
3694 | if (len == 0) |
3695 | return 0; | |
3696 | ||
3697 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3698 | if (!input_buffer) | |
3699 | return -ENOMEM; | |
3700 | ||
3701 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3702 | status = -EFAULT; | |
3703 | goto out; | |
3704 | } | |
3705 | ||
3706 | input_buffer[len] = '\0'; | |
3707 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3708 | ||
3f6a5e1e DV |
3709 | drm_connector_list_iter_begin(dev, &conn_iter); |
3710 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3711 | if (connector->connector_type != |
3712 | DRM_MODE_CONNECTOR_DisplayPort) | |
3713 | continue; | |
3714 | ||
b8bb08ec | 3715 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3716 | connector->encoder != NULL) { |
3717 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3718 | status = kstrtoint(input_buffer, 10, &val); | |
3719 | if (status < 0) | |
3f6a5e1e | 3720 | break; |
eb3394fa TP |
3721 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3722 | /* To prevent erroneous activation of the compliance | |
3723 | * testing code, only accept an actual value of 1 here | |
3724 | */ | |
3725 | if (val == 1) | |
c1617abc | 3726 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3727 | else |
c1617abc | 3728 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3729 | } |
3730 | } | |
3f6a5e1e | 3731 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3732 | out: |
3733 | kfree(input_buffer); | |
3734 | if (status < 0) | |
3735 | return status; | |
3736 | ||
3737 | *offp += len; | |
3738 | return len; | |
3739 | } | |
3740 | ||
3741 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3742 | { | |
3743 | struct drm_device *dev = m->private; | |
3744 | struct drm_connector *connector; | |
3f6a5e1e | 3745 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3746 | struct intel_dp *intel_dp; |
3747 | ||
3f6a5e1e DV |
3748 | drm_connector_list_iter_begin(dev, &conn_iter); |
3749 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3750 | if (connector->connector_type != |
3751 | DRM_MODE_CONNECTOR_DisplayPort) | |
3752 | continue; | |
3753 | ||
3754 | if (connector->status == connector_status_connected && | |
3755 | connector->encoder != NULL) { | |
3756 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3757 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3758 | seq_puts(m, "1"); |
3759 | else | |
3760 | seq_puts(m, "0"); | |
3761 | } else | |
3762 | seq_puts(m, "0"); | |
3763 | } | |
3f6a5e1e | 3764 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3765 | |
3766 | return 0; | |
3767 | } | |
3768 | ||
3769 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3770 | struct file *file) |
eb3394fa | 3771 | { |
36cdd013 | 3772 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3773 | |
36cdd013 DW |
3774 | return single_open(file, i915_displayport_test_active_show, |
3775 | &dev_priv->drm); | |
eb3394fa TP |
3776 | } |
3777 | ||
3778 | static const struct file_operations i915_displayport_test_active_fops = { | |
3779 | .owner = THIS_MODULE, | |
3780 | .open = i915_displayport_test_active_open, | |
3781 | .read = seq_read, | |
3782 | .llseek = seq_lseek, | |
3783 | .release = single_release, | |
3784 | .write = i915_displayport_test_active_write | |
3785 | }; | |
3786 | ||
3787 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3788 | { | |
3789 | struct drm_device *dev = m->private; | |
3790 | struct drm_connector *connector; | |
3f6a5e1e | 3791 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3792 | struct intel_dp *intel_dp; |
3793 | ||
3f6a5e1e DV |
3794 | drm_connector_list_iter_begin(dev, &conn_iter); |
3795 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3796 | if (connector->connector_type != |
3797 | DRM_MODE_CONNECTOR_DisplayPort) | |
3798 | continue; | |
3799 | ||
3800 | if (connector->status == connector_status_connected && | |
3801 | connector->encoder != NULL) { | |
3802 | intel_dp = enc_to_intel_dp(connector->encoder); | |
b48a5ba9 MN |
3803 | if (intel_dp->compliance.test_type == |
3804 | DP_TEST_LINK_EDID_READ) | |
3805 | seq_printf(m, "%lx", | |
3806 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3807 | else if (intel_dp->compliance.test_type == |
3808 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3809 | seq_printf(m, "hdisplay: %d\n", | |
3810 | intel_dp->compliance.test_data.hdisplay); | |
3811 | seq_printf(m, "vdisplay: %d\n", | |
3812 | intel_dp->compliance.test_data.vdisplay); | |
3813 | seq_printf(m, "bpc: %u\n", | |
3814 | intel_dp->compliance.test_data.bpc); | |
3815 | } | |
eb3394fa TP |
3816 | } else |
3817 | seq_puts(m, "0"); | |
3818 | } | |
3f6a5e1e | 3819 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3820 | |
3821 | return 0; | |
3822 | } | |
3823 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3824 | struct file *file) |
eb3394fa | 3825 | { |
36cdd013 | 3826 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3827 | |
36cdd013 DW |
3828 | return single_open(file, i915_displayport_test_data_show, |
3829 | &dev_priv->drm); | |
eb3394fa TP |
3830 | } |
3831 | ||
3832 | static const struct file_operations i915_displayport_test_data_fops = { | |
3833 | .owner = THIS_MODULE, | |
3834 | .open = i915_displayport_test_data_open, | |
3835 | .read = seq_read, | |
3836 | .llseek = seq_lseek, | |
3837 | .release = single_release | |
3838 | }; | |
3839 | ||
3840 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3841 | { | |
3842 | struct drm_device *dev = m->private; | |
3843 | struct drm_connector *connector; | |
3f6a5e1e | 3844 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3845 | struct intel_dp *intel_dp; |
3846 | ||
3f6a5e1e DV |
3847 | drm_connector_list_iter_begin(dev, &conn_iter); |
3848 | drm_for_each_connector_iter(connector, &conn_iter) { | |
eb3394fa TP |
3849 | if (connector->connector_type != |
3850 | DRM_MODE_CONNECTOR_DisplayPort) | |
3851 | continue; | |
3852 | ||
3853 | if (connector->status == connector_status_connected && | |
3854 | connector->encoder != NULL) { | |
3855 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3856 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3857 | } else |
3858 | seq_puts(m, "0"); | |
3859 | } | |
3f6a5e1e | 3860 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3861 | |
3862 | return 0; | |
3863 | } | |
3864 | ||
3865 | static int i915_displayport_test_type_open(struct inode *inode, | |
3866 | struct file *file) | |
3867 | { | |
36cdd013 | 3868 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3869 | |
36cdd013 DW |
3870 | return single_open(file, i915_displayport_test_type_show, |
3871 | &dev_priv->drm); | |
eb3394fa TP |
3872 | } |
3873 | ||
3874 | static const struct file_operations i915_displayport_test_type_fops = { | |
3875 | .owner = THIS_MODULE, | |
3876 | .open = i915_displayport_test_type_open, | |
3877 | .read = seq_read, | |
3878 | .llseek = seq_lseek, | |
3879 | .release = single_release | |
3880 | }; | |
3881 | ||
97e94b22 | 3882 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3883 | { |
36cdd013 DW |
3884 | struct drm_i915_private *dev_priv = m->private; |
3885 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3886 | int level; |
de38b95c VS |
3887 | int num_levels; |
3888 | ||
36cdd013 | 3889 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3890 | num_levels = 3; |
36cdd013 | 3891 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3892 | num_levels = 1; |
3893 | else | |
5db94019 | 3894 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3895 | |
3896 | drm_modeset_lock_all(dev); | |
3897 | ||
3898 | for (level = 0; level < num_levels; level++) { | |
3899 | unsigned int latency = wm[level]; | |
3900 | ||
97e94b22 DL |
3901 | /* |
3902 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3903 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3904 | */ |
36cdd013 DW |
3905 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3906 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3907 | latency *= 10; |
3908 | else if (level > 0) | |
369a1342 VS |
3909 | latency *= 5; |
3910 | ||
3911 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3912 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3913 | } |
3914 | ||
3915 | drm_modeset_unlock_all(dev); | |
3916 | } | |
3917 | ||
3918 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3919 | { | |
36cdd013 | 3920 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3921 | const uint16_t *latencies; |
3922 | ||
36cdd013 | 3923 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3924 | latencies = dev_priv->wm.skl_latency; |
3925 | else | |
36cdd013 | 3926 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3927 | |
97e94b22 | 3928 | wm_latency_show(m, latencies); |
369a1342 VS |
3929 | |
3930 | return 0; | |
3931 | } | |
3932 | ||
3933 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3934 | { | |
36cdd013 | 3935 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3936 | const uint16_t *latencies; |
3937 | ||
36cdd013 | 3938 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3939 | latencies = dev_priv->wm.skl_latency; |
3940 | else | |
36cdd013 | 3941 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3942 | |
97e94b22 | 3943 | wm_latency_show(m, latencies); |
369a1342 VS |
3944 | |
3945 | return 0; | |
3946 | } | |
3947 | ||
3948 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3949 | { | |
36cdd013 | 3950 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3951 | const uint16_t *latencies; |
3952 | ||
36cdd013 | 3953 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3954 | latencies = dev_priv->wm.skl_latency; |
3955 | else | |
36cdd013 | 3956 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3957 | |
97e94b22 | 3958 | wm_latency_show(m, latencies); |
369a1342 VS |
3959 | |
3960 | return 0; | |
3961 | } | |
3962 | ||
3963 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3964 | { | |
36cdd013 | 3965 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3966 | |
36cdd013 | 3967 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3968 | return -ENODEV; |
3969 | ||
36cdd013 | 3970 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3971 | } |
3972 | ||
3973 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3974 | { | |
36cdd013 | 3975 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3976 | |
36cdd013 | 3977 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3978 | return -ENODEV; |
3979 | ||
36cdd013 | 3980 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3981 | } |
3982 | ||
3983 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3984 | { | |
36cdd013 | 3985 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3986 | |
36cdd013 | 3987 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3988 | return -ENODEV; |
3989 | ||
36cdd013 | 3990 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3991 | } |
3992 | ||
3993 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3994 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3995 | { |
3996 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3997 | struct drm_i915_private *dev_priv = m->private; |
3998 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3999 | uint16_t new[8] = { 0 }; |
de38b95c | 4000 | int num_levels; |
369a1342 VS |
4001 | int level; |
4002 | int ret; | |
4003 | char tmp[32]; | |
4004 | ||
36cdd013 | 4005 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4006 | num_levels = 3; |
36cdd013 | 4007 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4008 | num_levels = 1; |
4009 | else | |
5db94019 | 4010 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4011 | |
369a1342 VS |
4012 | if (len >= sizeof(tmp)) |
4013 | return -EINVAL; | |
4014 | ||
4015 | if (copy_from_user(tmp, ubuf, len)) | |
4016 | return -EFAULT; | |
4017 | ||
4018 | tmp[len] = '\0'; | |
4019 | ||
97e94b22 DL |
4020 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4021 | &new[0], &new[1], &new[2], &new[3], | |
4022 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4023 | if (ret != num_levels) |
4024 | return -EINVAL; | |
4025 | ||
4026 | drm_modeset_lock_all(dev); | |
4027 | ||
4028 | for (level = 0; level < num_levels; level++) | |
4029 | wm[level] = new[level]; | |
4030 | ||
4031 | drm_modeset_unlock_all(dev); | |
4032 | ||
4033 | return len; | |
4034 | } | |
4035 | ||
4036 | ||
4037 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4038 | size_t len, loff_t *offp) | |
4039 | { | |
4040 | struct seq_file *m = file->private_data; | |
36cdd013 | 4041 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4042 | uint16_t *latencies; |
369a1342 | 4043 | |
36cdd013 | 4044 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4045 | latencies = dev_priv->wm.skl_latency; |
4046 | else | |
36cdd013 | 4047 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4048 | |
4049 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4050 | } |
4051 | ||
4052 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4053 | size_t len, loff_t *offp) | |
4054 | { | |
4055 | struct seq_file *m = file->private_data; | |
36cdd013 | 4056 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4057 | uint16_t *latencies; |
369a1342 | 4058 | |
36cdd013 | 4059 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4060 | latencies = dev_priv->wm.skl_latency; |
4061 | else | |
36cdd013 | 4062 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4063 | |
4064 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4065 | } |
4066 | ||
4067 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4068 | size_t len, loff_t *offp) | |
4069 | { | |
4070 | struct seq_file *m = file->private_data; | |
36cdd013 | 4071 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4072 | uint16_t *latencies; |
4073 | ||
36cdd013 | 4074 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4075 | latencies = dev_priv->wm.skl_latency; |
4076 | else | |
36cdd013 | 4077 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4078 | |
97e94b22 | 4079 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4080 | } |
4081 | ||
4082 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4083 | .owner = THIS_MODULE, | |
4084 | .open = pri_wm_latency_open, | |
4085 | .read = seq_read, | |
4086 | .llseek = seq_lseek, | |
4087 | .release = single_release, | |
4088 | .write = pri_wm_latency_write | |
4089 | }; | |
4090 | ||
4091 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4092 | .owner = THIS_MODULE, | |
4093 | .open = spr_wm_latency_open, | |
4094 | .read = seq_read, | |
4095 | .llseek = seq_lseek, | |
4096 | .release = single_release, | |
4097 | .write = spr_wm_latency_write | |
4098 | }; | |
4099 | ||
4100 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4101 | .owner = THIS_MODULE, | |
4102 | .open = cur_wm_latency_open, | |
4103 | .read = seq_read, | |
4104 | .llseek = seq_lseek, | |
4105 | .release = single_release, | |
4106 | .write = cur_wm_latency_write | |
4107 | }; | |
4108 | ||
647416f9 KC |
4109 | static int |
4110 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4111 | { |
36cdd013 | 4112 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4113 | |
d98c52cf | 4114 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4115 | |
647416f9 | 4116 | return 0; |
f3cd474b CW |
4117 | } |
4118 | ||
647416f9 KC |
4119 | static int |
4120 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4121 | { |
36cdd013 | 4122 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4123 | |
b8d24a06 MK |
4124 | /* |
4125 | * There is no safeguard against this debugfs entry colliding | |
4126 | * with the hangcheck calling same i915_handle_error() in | |
4127 | * parallel, causing an explosion. For now we assume that the | |
4128 | * test harness is responsible enough not to inject gpu hangs | |
4129 | * while it is writing to 'i915_wedged' | |
4130 | */ | |
4131 | ||
8c185eca | 4132 | if (i915_reset_backoff(&dev_priv->gpu_error)) |
b8d24a06 MK |
4133 | return -EAGAIN; |
4134 | ||
c033666a | 4135 | i915_handle_error(dev_priv, val, |
58174462 | 4136 | "Manually setting wedged to %llu", val); |
d46c0517 | 4137 | |
647416f9 | 4138 | return 0; |
f3cd474b CW |
4139 | } |
4140 | ||
647416f9 KC |
4141 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4142 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4143 | "%llu\n"); |
f3cd474b | 4144 | |
64486ae7 CW |
4145 | static int |
4146 | fault_irq_set(struct drm_i915_private *i915, | |
4147 | unsigned long *irq, | |
4148 | unsigned long val) | |
4149 | { | |
4150 | int err; | |
4151 | ||
4152 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4153 | if (err) | |
4154 | return err; | |
4155 | ||
4156 | err = i915_gem_wait_for_idle(i915, | |
4157 | I915_WAIT_LOCKED | | |
4158 | I915_WAIT_INTERRUPTIBLE); | |
4159 | if (err) | |
4160 | goto err_unlock; | |
4161 | ||
4162 | /* Retire to kick idle work */ | |
4163 | i915_gem_retire_requests(i915); | |
4164 | GEM_BUG_ON(i915->gt.active_requests); | |
4165 | ||
4166 | *irq = val; | |
4167 | mutex_unlock(&i915->drm.struct_mutex); | |
4168 | ||
4169 | /* Flush idle worker to disarm irq */ | |
4170 | while (flush_delayed_work(&i915->gt.idle_work)) | |
4171 | ; | |
4172 | ||
4173 | return 0; | |
4174 | ||
4175 | err_unlock: | |
4176 | mutex_unlock(&i915->drm.struct_mutex); | |
4177 | return err; | |
4178 | } | |
4179 | ||
094f9a54 CW |
4180 | static int |
4181 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4182 | { | |
36cdd013 | 4183 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4184 | |
4185 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4186 | return 0; | |
4187 | } | |
4188 | ||
4189 | static int | |
4190 | i915_ring_missed_irq_set(void *data, u64 val) | |
4191 | { | |
64486ae7 | 4192 | struct drm_i915_private *i915 = data; |
094f9a54 | 4193 | |
64486ae7 | 4194 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4195 | } |
4196 | ||
4197 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4198 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4199 | "0x%08llx\n"); | |
4200 | ||
4201 | static int | |
4202 | i915_ring_test_irq_get(void *data, u64 *val) | |
4203 | { | |
36cdd013 | 4204 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4205 | |
4206 | *val = dev_priv->gpu_error.test_irq_rings; | |
4207 | ||
4208 | return 0; | |
4209 | } | |
4210 | ||
4211 | static int | |
4212 | i915_ring_test_irq_set(void *data, u64 val) | |
4213 | { | |
64486ae7 | 4214 | struct drm_i915_private *i915 = data; |
094f9a54 | 4215 | |
64486ae7 | 4216 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4217 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4218 | |
64486ae7 | 4219 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4220 | } |
4221 | ||
4222 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4223 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4224 | "0x%08llx\n"); | |
4225 | ||
dd624afd CW |
4226 | #define DROP_UNBOUND 0x1 |
4227 | #define DROP_BOUND 0x2 | |
4228 | #define DROP_RETIRE 0x4 | |
4229 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 | 4230 | #define DROP_FREED 0x10 |
8eadc19b | 4231 | #define DROP_SHRINK_ALL 0x20 |
fbbd37b3 CW |
4232 | #define DROP_ALL (DROP_UNBOUND | \ |
4233 | DROP_BOUND | \ | |
4234 | DROP_RETIRE | \ | |
4235 | DROP_ACTIVE | \ | |
8eadc19b CW |
4236 | DROP_FREED | \ |
4237 | DROP_SHRINK_ALL) | |
647416f9 KC |
4238 | static int |
4239 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4240 | { |
647416f9 | 4241 | *val = DROP_ALL; |
dd624afd | 4242 | |
647416f9 | 4243 | return 0; |
dd624afd CW |
4244 | } |
4245 | ||
647416f9 KC |
4246 | static int |
4247 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4248 | { |
36cdd013 DW |
4249 | struct drm_i915_private *dev_priv = data; |
4250 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4251 | int ret; |
dd624afd | 4252 | |
2f9fe5ff | 4253 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4254 | |
4255 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4256 | * on ioctls on -EAGAIN. */ | |
4257 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4258 | if (ret) | |
4259 | return ret; | |
4260 | ||
4261 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4262 | ret = i915_gem_wait_for_idle(dev_priv, |
4263 | I915_WAIT_INTERRUPTIBLE | | |
4264 | I915_WAIT_LOCKED); | |
dd624afd CW |
4265 | if (ret) |
4266 | goto unlock; | |
4267 | } | |
4268 | ||
4269 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4270 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4271 | |
05df49e7 | 4272 | lockdep_set_current_reclaim_state(GFP_KERNEL); |
21ab4e74 CW |
4273 | if (val & DROP_BOUND) |
4274 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4275 | |
21ab4e74 CW |
4276 | if (val & DROP_UNBOUND) |
4277 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd | 4278 | |
8eadc19b CW |
4279 | if (val & DROP_SHRINK_ALL) |
4280 | i915_gem_shrink_all(dev_priv); | |
05df49e7 | 4281 | lockdep_clear_current_reclaim_state(); |
8eadc19b | 4282 | |
dd624afd CW |
4283 | unlock: |
4284 | mutex_unlock(&dev->struct_mutex); | |
4285 | ||
fbbd37b3 CW |
4286 | if (val & DROP_FREED) { |
4287 | synchronize_rcu(); | |
bdeb9785 | 4288 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4289 | } |
4290 | ||
647416f9 | 4291 | return ret; |
dd624afd CW |
4292 | } |
4293 | ||
647416f9 KC |
4294 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4295 | i915_drop_caches_get, i915_drop_caches_set, | |
4296 | "0x%08llx\n"); | |
dd624afd | 4297 | |
647416f9 KC |
4298 | static int |
4299 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4300 | { |
36cdd013 | 4301 | struct drm_i915_private *dev_priv = data; |
004777cb | 4302 | |
36cdd013 | 4303 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4304 | return -ENODEV; |
4305 | ||
7c59a9c1 | 4306 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4307 | return 0; |
358733e9 JB |
4308 | } |
4309 | ||
647416f9 KC |
4310 | static int |
4311 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4312 | { |
36cdd013 | 4313 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4314 | u32 hw_max, hw_min; |
647416f9 | 4315 | int ret; |
004777cb | 4316 | |
36cdd013 | 4317 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4318 | return -ENODEV; |
358733e9 | 4319 | |
647416f9 | 4320 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4321 | |
4fc688ce | 4322 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4323 | if (ret) |
4324 | return ret; | |
4325 | ||
358733e9 JB |
4326 | /* |
4327 | * Turbo will still be enabled, but won't go above the set value. | |
4328 | */ | |
bc4d91f6 | 4329 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4330 | |
bc4d91f6 AG |
4331 | hw_max = dev_priv->rps.max_freq; |
4332 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4333 | |
b39fb297 | 4334 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4335 | mutex_unlock(&dev_priv->rps.hw_lock); |
4336 | return -EINVAL; | |
0a073b84 JB |
4337 | } |
4338 | ||
b39fb297 | 4339 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4340 | |
9fcee2f7 CW |
4341 | if (intel_set_rps(dev_priv, val)) |
4342 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4343 | |
4fc688ce | 4344 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4345 | |
647416f9 | 4346 | return 0; |
358733e9 JB |
4347 | } |
4348 | ||
647416f9 KC |
4349 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4350 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4351 | "%llu\n"); |
358733e9 | 4352 | |
647416f9 KC |
4353 | static int |
4354 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4355 | { |
36cdd013 | 4356 | struct drm_i915_private *dev_priv = data; |
004777cb | 4357 | |
62e1baa1 | 4358 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4359 | return -ENODEV; |
4360 | ||
7c59a9c1 | 4361 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4362 | return 0; |
1523c310 JB |
4363 | } |
4364 | ||
647416f9 KC |
4365 | static int |
4366 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4367 | { |
36cdd013 | 4368 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4369 | u32 hw_max, hw_min; |
647416f9 | 4370 | int ret; |
004777cb | 4371 | |
62e1baa1 | 4372 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4373 | return -ENODEV; |
1523c310 | 4374 | |
647416f9 | 4375 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4376 | |
4fc688ce | 4377 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4378 | if (ret) |
4379 | return ret; | |
4380 | ||
1523c310 JB |
4381 | /* |
4382 | * Turbo will still be enabled, but won't go below the set value. | |
4383 | */ | |
bc4d91f6 | 4384 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4385 | |
bc4d91f6 AG |
4386 | hw_max = dev_priv->rps.max_freq; |
4387 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4388 | |
36cdd013 DW |
4389 | if (val < hw_min || |
4390 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4391 | mutex_unlock(&dev_priv->rps.hw_lock); |
4392 | return -EINVAL; | |
0a073b84 | 4393 | } |
dd0a1aa1 | 4394 | |
b39fb297 | 4395 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4396 | |
9fcee2f7 CW |
4397 | if (intel_set_rps(dev_priv, val)) |
4398 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4399 | |
4fc688ce | 4400 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4401 | |
647416f9 | 4402 | return 0; |
1523c310 JB |
4403 | } |
4404 | ||
647416f9 KC |
4405 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4406 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4407 | "%llu\n"); |
1523c310 | 4408 | |
647416f9 KC |
4409 | static int |
4410 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4411 | { |
36cdd013 | 4412 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4413 | u32 snpcr; |
07b7ddd9 | 4414 | |
36cdd013 | 4415 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4416 | return -ENODEV; |
4417 | ||
c8c8fb33 | 4418 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4419 | |
07b7ddd9 | 4420 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4421 | |
4422 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4423 | |
647416f9 | 4424 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4425 | |
647416f9 | 4426 | return 0; |
07b7ddd9 JB |
4427 | } |
4428 | ||
647416f9 KC |
4429 | static int |
4430 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4431 | { |
36cdd013 | 4432 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4433 | u32 snpcr; |
07b7ddd9 | 4434 | |
36cdd013 | 4435 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4436 | return -ENODEV; |
4437 | ||
647416f9 | 4438 | if (val > 3) |
07b7ddd9 JB |
4439 | return -EINVAL; |
4440 | ||
c8c8fb33 | 4441 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4442 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4443 | |
4444 | /* Update the cache sharing policy here as well */ | |
4445 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4446 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4447 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4448 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4449 | ||
c8c8fb33 | 4450 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4451 | return 0; |
07b7ddd9 JB |
4452 | } |
4453 | ||
647416f9 KC |
4454 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4455 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4456 | "%llu\n"); | |
07b7ddd9 | 4457 | |
36cdd013 | 4458 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4459 | struct sseu_dev_info *sseu) |
5d39525a | 4460 | { |
0a0b457f | 4461 | int ss_max = 2; |
5d39525a JM |
4462 | int ss; |
4463 | u32 sig1[ss_max], sig2[ss_max]; | |
4464 | ||
4465 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4466 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4467 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4468 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4469 | ||
4470 | for (ss = 0; ss < ss_max; ss++) { | |
4471 | unsigned int eu_cnt; | |
4472 | ||
4473 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4474 | /* skip disabled subslice */ | |
4475 | continue; | |
4476 | ||
f08a0c92 | 4477 | sseu->slice_mask = BIT(0); |
57ec171e | 4478 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4479 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4480 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4481 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4482 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4483 | sseu->eu_total += eu_cnt; |
4484 | sseu->eu_per_subslice = max_t(unsigned int, | |
4485 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4486 | } |
5d39525a JM |
4487 | } |
4488 | ||
36cdd013 | 4489 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4490 | struct sseu_dev_info *sseu) |
5d39525a | 4491 | { |
1c046bc1 | 4492 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4493 | int s, ss; |
4494 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4495 | ||
1c046bc1 | 4496 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4497 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4498 | s_max = 1; |
4499 | ss_max = 3; | |
4500 | } | |
4501 | ||
4502 | for (s = 0; s < s_max; s++) { | |
4503 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4504 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4505 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4506 | } | |
4507 | ||
5d39525a JM |
4508 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4509 | GEN9_PGCTL_SSA_EU19_ACK | | |
4510 | GEN9_PGCTL_SSA_EU210_ACK | | |
4511 | GEN9_PGCTL_SSA_EU311_ACK; | |
4512 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4513 | GEN9_PGCTL_SSB_EU19_ACK | | |
4514 | GEN9_PGCTL_SSB_EU210_ACK | | |
4515 | GEN9_PGCTL_SSB_EU311_ACK; | |
4516 | ||
4517 | for (s = 0; s < s_max; s++) { | |
4518 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4519 | /* skip disabled slice */ | |
4520 | continue; | |
4521 | ||
f08a0c92 | 4522 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4523 | |
b976dc53 | 4524 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4525 | sseu->subslice_mask = |
4526 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4527 | |
5d39525a JM |
4528 | for (ss = 0; ss < ss_max; ss++) { |
4529 | unsigned int eu_cnt; | |
4530 | ||
cc3f90f0 | 4531 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4532 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4533 | /* skip disabled subslice */ | |
4534 | continue; | |
1c046bc1 | 4535 | |
57ec171e ID |
4536 | sseu->subslice_mask |= BIT(ss); |
4537 | } | |
1c046bc1 | 4538 | |
5d39525a JM |
4539 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4540 | eu_mask[ss%2]); | |
915490d5 ID |
4541 | sseu->eu_total += eu_cnt; |
4542 | sseu->eu_per_subslice = max_t(unsigned int, | |
4543 | sseu->eu_per_subslice, | |
4544 | eu_cnt); | |
5d39525a JM |
4545 | } |
4546 | } | |
4547 | } | |
4548 | ||
36cdd013 | 4549 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4550 | struct sseu_dev_info *sseu) |
91bedd34 | 4551 | { |
91bedd34 | 4552 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4553 | int s; |
91bedd34 | 4554 | |
f08a0c92 | 4555 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4556 | |
f08a0c92 | 4557 | if (sseu->slice_mask) { |
57ec171e | 4558 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4559 | sseu->eu_per_subslice = |
4560 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4561 | sseu->eu_total = sseu->eu_per_subslice * |
4562 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4563 | |
4564 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4565 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4566 | u8 subslice_7eu = |
4567 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4568 | |
915490d5 | 4569 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4570 | } |
4571 | } | |
4572 | } | |
4573 | ||
615d8908 ID |
4574 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4575 | const struct sseu_dev_info *sseu) | |
4576 | { | |
4577 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4578 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4579 | ||
c67ba538 ID |
4580 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4581 | sseu->slice_mask); | |
615d8908 | 4582 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4583 | hweight8(sseu->slice_mask)); |
615d8908 | 4584 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4585 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4586 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4587 | sseu->subslice_mask); | |
615d8908 | 4588 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4589 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4590 | seq_printf(m, " %s EU Total: %u\n", type, |
4591 | sseu->eu_total); | |
4592 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4593 | sseu->eu_per_subslice); | |
4594 | ||
4595 | if (!is_available_info) | |
4596 | return; | |
4597 | ||
4598 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4599 | if (HAS_POOLED_EU(dev_priv)) | |
4600 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4601 | ||
4602 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4603 | yesno(sseu->has_slice_pg)); | |
4604 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4605 | yesno(sseu->has_subslice_pg)); | |
4606 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4607 | yesno(sseu->has_eu_pg)); | |
4608 | } | |
4609 | ||
3873218f JM |
4610 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4611 | { | |
36cdd013 | 4612 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4613 | struct sseu_dev_info sseu; |
3873218f | 4614 | |
36cdd013 | 4615 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4616 | return -ENODEV; |
4617 | ||
4618 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4619 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4620 | |
7f992aba | 4621 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4622 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4623 | |
4624 | intel_runtime_pm_get(dev_priv); | |
4625 | ||
36cdd013 | 4626 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4627 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4628 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4629 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4630 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4631 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4632 | } |
238010ed DW |
4633 | |
4634 | intel_runtime_pm_put(dev_priv); | |
4635 | ||
615d8908 | 4636 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4637 | |
3873218f JM |
4638 | return 0; |
4639 | } | |
4640 | ||
6d794d42 BW |
4641 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4642 | { | |
36cdd013 | 4643 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4644 | |
36cdd013 | 4645 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4646 | return 0; |
4647 | ||
6daccb0b | 4648 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4649 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4650 | |
4651 | return 0; | |
4652 | } | |
4653 | ||
c43b5634 | 4654 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4655 | { |
36cdd013 | 4656 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4657 | |
36cdd013 | 4658 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4659 | return 0; |
4660 | ||
59bad947 | 4661 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4662 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4663 | |
4664 | return 0; | |
4665 | } | |
4666 | ||
4667 | static const struct file_operations i915_forcewake_fops = { | |
4668 | .owner = THIS_MODULE, | |
4669 | .open = i915_forcewake_open, | |
4670 | .release = i915_forcewake_release, | |
4671 | }; | |
4672 | ||
317eaa95 L |
4673 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4674 | { | |
4675 | struct drm_i915_private *dev_priv = m->private; | |
4676 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4677 | ||
4678 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4679 | seq_printf(m, "Detected: %s\n", | |
4680 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4681 | ||
4682 | return 0; | |
4683 | } | |
4684 | ||
4685 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4686 | const char __user *ubuf, size_t len, | |
4687 | loff_t *offp) | |
4688 | { | |
4689 | struct seq_file *m = file->private_data; | |
4690 | struct drm_i915_private *dev_priv = m->private; | |
4691 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4692 | unsigned int new_threshold; | |
4693 | int i; | |
4694 | char *newline; | |
4695 | char tmp[16]; | |
4696 | ||
4697 | if (len >= sizeof(tmp)) | |
4698 | return -EINVAL; | |
4699 | ||
4700 | if (copy_from_user(tmp, ubuf, len)) | |
4701 | return -EFAULT; | |
4702 | ||
4703 | tmp[len] = '\0'; | |
4704 | ||
4705 | /* Strip newline, if any */ | |
4706 | newline = strchr(tmp, '\n'); | |
4707 | if (newline) | |
4708 | *newline = '\0'; | |
4709 | ||
4710 | if (strcmp(tmp, "reset") == 0) | |
4711 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4712 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4713 | return -EINVAL; | |
4714 | ||
4715 | if (new_threshold > 0) | |
4716 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4717 | new_threshold); | |
4718 | else | |
4719 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4720 | ||
4721 | spin_lock_irq(&dev_priv->irq_lock); | |
4722 | hotplug->hpd_storm_threshold = new_threshold; | |
4723 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4724 | for_each_hpd_pin(i) | |
4725 | hotplug->stats[i].count = 0; | |
4726 | spin_unlock_irq(&dev_priv->irq_lock); | |
4727 | ||
4728 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4729 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4730 | ||
4731 | return len; | |
4732 | } | |
4733 | ||
4734 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4735 | { | |
4736 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4737 | } | |
4738 | ||
4739 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4740 | .owner = THIS_MODULE, | |
4741 | .open = i915_hpd_storm_ctl_open, | |
4742 | .read = seq_read, | |
4743 | .llseek = seq_lseek, | |
4744 | .release = single_release, | |
4745 | .write = i915_hpd_storm_ctl_write | |
4746 | }; | |
4747 | ||
06c5bf8c | 4748 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4749 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4750 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4751 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4752 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4753 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4754 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4755 | {"i915_gem_request", i915_gem_request_info, 0}, |
4756 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4757 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4758 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4759 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4760 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4761 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4762 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
0509ead1 | 4763 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4764 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4765 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4766 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4767 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4768 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4769 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4770 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4771 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4772 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4773 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4774 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4775 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4776 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4777 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4778 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4779 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4780 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4781 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4782 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4783 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4784 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4785 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4786 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4787 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4788 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4789 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4790 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4791 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4792 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4793 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4794 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4795 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4796 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4797 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4798 | }; |
27c202ad | 4799 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4800 | |
06c5bf8c | 4801 | static const struct i915_debugfs_files { |
34b9674c DV |
4802 | const char *name; |
4803 | const struct file_operations *fops; | |
4804 | } i915_debugfs_files[] = { | |
4805 | {"i915_wedged", &i915_wedged_fops}, | |
4806 | {"i915_max_freq", &i915_max_freq_fops}, | |
4807 | {"i915_min_freq", &i915_min_freq_fops}, | |
4808 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4809 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4810 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4811 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4812 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4813 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4814 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4815 | #endif |
34b9674c | 4816 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4817 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4818 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4819 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4820 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4821 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4822 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4823 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4824 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4825 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4826 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4827 | }; |
4828 | ||
1dac891c | 4829 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4830 | { |
91c8a326 | 4831 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4832 | struct dentry *ent; |
34b9674c | 4833 | int ret, i; |
f3cd474b | 4834 | |
b05eeb0f NT |
4835 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4836 | minor->debugfs_root, to_i915(minor->dev), | |
4837 | &i915_forcewake_fops); | |
4838 | if (!ent) | |
4839 | return -ENOMEM; | |
6a9c308d | 4840 | |
731035fe TV |
4841 | ret = intel_pipe_crc_create(minor); |
4842 | if (ret) | |
4843 | return ret; | |
07144428 | 4844 | |
34b9674c | 4845 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4846 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4847 | S_IRUGO | S_IWUSR, | |
4848 | minor->debugfs_root, | |
4849 | to_i915(minor->dev), | |
34b9674c | 4850 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4851 | if (!ent) |
4852 | return -ENOMEM; | |
34b9674c | 4853 | } |
40633219 | 4854 | |
27c202ad BG |
4855 | return drm_debugfs_create_files(i915_debugfs_list, |
4856 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4857 | minor->debugfs_root, minor); |
4858 | } | |
4859 | ||
aa7471d2 JN |
4860 | struct dpcd_block { |
4861 | /* DPCD dump start address. */ | |
4862 | unsigned int offset; | |
4863 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4864 | unsigned int end; | |
4865 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4866 | size_t size; | |
4867 | /* Only valid for eDP. */ | |
4868 | bool edp; | |
4869 | }; | |
4870 | ||
4871 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4872 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4873 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4874 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4875 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4876 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4877 | { .offset = DP_SET_POWER }, | |
4878 | { .offset = DP_EDP_DPCD_REV }, | |
4879 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4880 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4881 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4882 | }; | |
4883 | ||
4884 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4885 | { | |
4886 | struct drm_connector *connector = m->private; | |
4887 | struct intel_dp *intel_dp = | |
4888 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4889 | uint8_t buf[16]; | |
4890 | ssize_t err; | |
4891 | int i; | |
4892 | ||
5c1a8875 MK |
4893 | if (connector->status != connector_status_connected) |
4894 | return -ENODEV; | |
4895 | ||
aa7471d2 JN |
4896 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4897 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4898 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4899 | ||
4900 | if (b->edp && | |
4901 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4902 | continue; | |
4903 | ||
4904 | /* low tech for now */ | |
4905 | if (WARN_ON(size > sizeof(buf))) | |
4906 | continue; | |
4907 | ||
4908 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4909 | if (err <= 0) { | |
4910 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4911 | size, b->offset, err); | |
4912 | continue; | |
4913 | } | |
4914 | ||
4915 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4916 | } |
aa7471d2 JN |
4917 | |
4918 | return 0; | |
4919 | } | |
4920 | ||
4921 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4922 | { | |
4923 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4924 | } | |
4925 | ||
4926 | static const struct file_operations i915_dpcd_fops = { | |
4927 | .owner = THIS_MODULE, | |
4928 | .open = i915_dpcd_open, | |
4929 | .read = seq_read, | |
4930 | .llseek = seq_lseek, | |
4931 | .release = single_release, | |
4932 | }; | |
4933 | ||
ecbd6781 DW |
4934 | static int i915_panel_show(struct seq_file *m, void *data) |
4935 | { | |
4936 | struct drm_connector *connector = m->private; | |
4937 | struct intel_dp *intel_dp = | |
4938 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4939 | ||
4940 | if (connector->status != connector_status_connected) | |
4941 | return -ENODEV; | |
4942 | ||
4943 | seq_printf(m, "Panel power up delay: %d\n", | |
4944 | intel_dp->panel_power_up_delay); | |
4945 | seq_printf(m, "Panel power down delay: %d\n", | |
4946 | intel_dp->panel_power_down_delay); | |
4947 | seq_printf(m, "Backlight on delay: %d\n", | |
4948 | intel_dp->backlight_on_delay); | |
4949 | seq_printf(m, "Backlight off delay: %d\n", | |
4950 | intel_dp->backlight_off_delay); | |
4951 | ||
4952 | return 0; | |
4953 | } | |
4954 | ||
4955 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4956 | { | |
4957 | return single_open(file, i915_panel_show, inode->i_private); | |
4958 | } | |
4959 | ||
4960 | static const struct file_operations i915_panel_fops = { | |
4961 | .owner = THIS_MODULE, | |
4962 | .open = i915_panel_open, | |
4963 | .read = seq_read, | |
4964 | .llseek = seq_lseek, | |
4965 | .release = single_release, | |
4966 | }; | |
4967 | ||
aa7471d2 JN |
4968 | /** |
4969 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4970 | * @connector: pointer to a registered drm_connector | |
4971 | * | |
4972 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4973 | * drm_debugfs_connector_remove(). | |
4974 | * | |
4975 | * Returns 0 on success, negative error codes on error. | |
4976 | */ | |
4977 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4978 | { | |
4979 | struct dentry *root = connector->debugfs_entry; | |
4980 | ||
4981 | /* The connector must have been registered beforehands. */ | |
4982 | if (!root) | |
4983 | return -ENODEV; | |
4984 | ||
4985 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4986 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4987 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4988 | connector, &i915_dpcd_fops); | |
4989 | ||
4990 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4991 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4992 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4993 | |
4994 | return 0; | |
4995 | } |