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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
36cdd013 DW |
43 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
44 | { | |
45 | return to_i915(node->minor->dev); | |
46 | } | |
47 | ||
497666d8 DL |
48 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
49 | * allocated we need to hook into the minor for release. */ | |
50 | static int | |
51 | drm_add_fake_info_node(struct drm_minor *minor, | |
52 | struct dentry *ent, | |
53 | const void *key) | |
54 | { | |
55 | struct drm_info_node *node; | |
56 | ||
57 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
58 | if (node == NULL) { | |
59 | debugfs_remove(ent); | |
60 | return -ENOMEM; | |
61 | } | |
62 | ||
63 | node->minor = minor; | |
64 | node->dent = ent; | |
36cdd013 | 65 | node->info_ent = (void *)key; |
497666d8 DL |
66 | |
67 | mutex_lock(&minor->debugfs_lock); | |
68 | list_add(&node->list, &minor->debugfs_list); | |
69 | mutex_unlock(&minor->debugfs_lock); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
70d39fe4 CW |
74 | static int i915_capabilities(struct seq_file *m, void *data) |
75 | { | |
36cdd013 DW |
76 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
77 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 78 | |
36cdd013 DW |
79 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
80 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); | |
79fc46df | 81 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 82 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 83 | #undef PRINT_FLAG |
70d39fe4 CW |
84 | |
85 | return 0; | |
86 | } | |
2017263e | 87 | |
a7363de7 | 88 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 89 | { |
573adb39 | 90 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
91 | } |
92 | ||
a7363de7 | 93 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
94 | { |
95 | return obj->pin_display ? 'p' : ' '; | |
96 | } | |
97 | ||
a7363de7 | 98 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 99 | { |
3e510a8e | 100 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 101 | default: |
be12a86b TU |
102 | case I915_TILING_NONE: return ' '; |
103 | case I915_TILING_X: return 'X'; | |
104 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 105 | } |
a6172a80 CW |
106 | } |
107 | ||
a7363de7 | 108 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 109 | { |
275f039d | 110 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
111 | } |
112 | ||
a7363de7 | 113 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 114 | { |
a4f5ea64 | 115 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
116 | } |
117 | ||
ca1543be TU |
118 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
119 | { | |
120 | u64 size = 0; | |
121 | struct i915_vma *vma; | |
122 | ||
1c7f4bca | 123 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 124 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
125 | size += vma->node.size; |
126 | } | |
127 | ||
128 | return size; | |
129 | } | |
130 | ||
37811fcc CW |
131 | static void |
132 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
133 | { | |
b4716185 | 134 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 135 | struct intel_engine_cs *engine; |
1d693bcc | 136 | struct i915_vma *vma; |
faf5bf0a | 137 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
138 | int pin_count = 0; |
139 | ||
188c1ab7 CW |
140 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
141 | ||
d07f0e59 | 142 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 143 | &obj->base, |
be12a86b | 144 | get_active_flag(obj), |
37811fcc CW |
145 | get_pin_flag(obj), |
146 | get_tiling_flag(obj), | |
1d693bcc | 147 | get_global_flag(obj), |
be12a86b | 148 | get_pin_mapped_flag(obj), |
a05a5862 | 149 | obj->base.size / 1024, |
37811fcc | 150 | obj->base.read_domains, |
d07f0e59 | 151 | obj->base.write_domain, |
36cdd013 | 152 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
153 | obj->mm.dirty ? " dirty" : "", |
154 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
155 | if (obj->base.name) |
156 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 157 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 158 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 159 | pin_count++; |
ba0635ff DC |
160 | } |
161 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
162 | if (obj->pin_display) |
163 | seq_printf(m, " (display)"); | |
1c7f4bca | 164 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
165 | if (!drm_mm_node_allocated(&vma->node)) |
166 | continue; | |
167 | ||
8d2fdc3f | 168 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 169 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 170 | vma->node.start, vma->node.size); |
3272db53 | 171 | if (i915_vma_is_ggtt(vma)) |
596c5923 | 172 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
49ef5294 CW |
173 | if (vma->fence) |
174 | seq_printf(m, " , fence: %d%s", | |
175 | vma->fence->id, | |
176 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 177 | seq_puts(m, ")"); |
1d693bcc | 178 | } |
c1ad11fc | 179 | if (obj->stolen) |
440fd528 | 180 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 181 | |
d07f0e59 | 182 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
183 | if (engine) |
184 | seq_printf(m, " (%s)", engine->name); | |
185 | ||
faf5bf0a CW |
186 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
187 | if (frontbuffer_bits) | |
188 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
189 | } |
190 | ||
6d2b8885 CW |
191 | static int obj_rank_by_stolen(void *priv, |
192 | struct list_head *A, struct list_head *B) | |
193 | { | |
194 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 195 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 196 | struct drm_i915_gem_object *b = |
b25cb2f8 | 197 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 198 | |
2d05fa16 RV |
199 | if (a->stolen->start < b->stolen->start) |
200 | return -1; | |
201 | if (a->stolen->start > b->stolen->start) | |
202 | return 1; | |
203 | return 0; | |
6d2b8885 CW |
204 | } |
205 | ||
206 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
207 | { | |
36cdd013 DW |
208 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
209 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 210 | struct drm_i915_gem_object *obj; |
c44ef60e | 211 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
212 | LIST_HEAD(stolen); |
213 | int count, ret; | |
214 | ||
215 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
216 | if (ret) | |
217 | return ret; | |
218 | ||
219 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 220 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
221 | if (obj->stolen == NULL) |
222 | continue; | |
223 | ||
b25cb2f8 | 224 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
225 | |
226 | total_obj_size += obj->base.size; | |
ca1543be | 227 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
228 | count++; |
229 | } | |
56cea323 | 230 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
231 | if (obj->stolen == NULL) |
232 | continue; | |
233 | ||
b25cb2f8 | 234 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
235 | |
236 | total_obj_size += obj->base.size; | |
237 | count++; | |
238 | } | |
239 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
240 | seq_puts(m, "Stolen:\n"); | |
241 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 242 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
243 | seq_puts(m, " "); |
244 | describe_obj(m, obj); | |
245 | seq_putc(m, '\n'); | |
b25cb2f8 | 246 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
247 | } |
248 | mutex_unlock(&dev->struct_mutex); | |
249 | ||
c44ef60e | 250 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
251 | count, total_obj_size, total_gtt_size); |
252 | return 0; | |
253 | } | |
254 | ||
2db8e9d6 | 255 | struct file_stats { |
6313c204 | 256 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
257 | unsigned long count; |
258 | u64 total, unbound; | |
259 | u64 global, shared; | |
260 | u64 active, inactive; | |
2db8e9d6 CW |
261 | }; |
262 | ||
263 | static int per_file_stats(int id, void *ptr, void *data) | |
264 | { | |
265 | struct drm_i915_gem_object *obj = ptr; | |
266 | struct file_stats *stats = data; | |
6313c204 | 267 | struct i915_vma *vma; |
2db8e9d6 CW |
268 | |
269 | stats->count++; | |
270 | stats->total += obj->base.size; | |
15717de2 CW |
271 | if (!obj->bind_count) |
272 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
273 | if (obj->base.name || obj->base.dma_buf) |
274 | stats->shared += obj->base.size; | |
275 | ||
894eeecc CW |
276 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
277 | if (!drm_mm_node_allocated(&vma->node)) | |
278 | continue; | |
6313c204 | 279 | |
3272db53 | 280 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
281 | stats->global += vma->node.size; |
282 | } else { | |
283 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 284 | |
2bfa996e | 285 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 286 | continue; |
6313c204 | 287 | } |
894eeecc | 288 | |
b0decaf7 | 289 | if (i915_vma_is_active(vma)) |
894eeecc CW |
290 | stats->active += vma->node.size; |
291 | else | |
292 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
293 | } |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
b0da1b79 CW |
298 | #define print_file_stats(m, name, stats) do { \ |
299 | if (stats.count) \ | |
c44ef60e | 300 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
301 | name, \ |
302 | stats.count, \ | |
303 | stats.total, \ | |
304 | stats.active, \ | |
305 | stats.inactive, \ | |
306 | stats.global, \ | |
307 | stats.shared, \ | |
308 | stats.unbound); \ | |
309 | } while (0) | |
493018dc BV |
310 | |
311 | static void print_batch_pool_stats(struct seq_file *m, | |
312 | struct drm_i915_private *dev_priv) | |
313 | { | |
314 | struct drm_i915_gem_object *obj; | |
315 | struct file_stats stats; | |
e2f80391 | 316 | struct intel_engine_cs *engine; |
3b3f1650 | 317 | enum intel_engine_id id; |
b4ac5afc | 318 | int j; |
493018dc BV |
319 | |
320 | memset(&stats, 0, sizeof(stats)); | |
321 | ||
3b3f1650 | 322 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 323 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 324 | list_for_each_entry(obj, |
e2f80391 | 325 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
326 | batch_pool_link) |
327 | per_file_stats(0, obj, &stats); | |
328 | } | |
06fbca71 | 329 | } |
493018dc | 330 | |
b0da1b79 | 331 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
332 | } |
333 | ||
15da9565 CW |
334 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
335 | { | |
336 | struct i915_gem_context *ctx = ptr; | |
337 | int n; | |
338 | ||
339 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
340 | if (ctx->engine[n].state) | |
bf3783e5 | 341 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 342 | if (ctx->engine[n].ring) |
57e88531 | 343 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
344 | } |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | static void print_context_stats(struct seq_file *m, | |
350 | struct drm_i915_private *dev_priv) | |
351 | { | |
36cdd013 | 352 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
353 | struct file_stats stats; |
354 | struct drm_file *file; | |
355 | ||
356 | memset(&stats, 0, sizeof(stats)); | |
357 | ||
36cdd013 | 358 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
359 | if (dev_priv->kernel_context) |
360 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
361 | ||
36cdd013 | 362 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
363 | struct drm_i915_file_private *fpriv = file->driver_priv; |
364 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
365 | } | |
36cdd013 | 366 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
367 | |
368 | print_file_stats(m, "[k]contexts", stats); | |
369 | } | |
370 | ||
36cdd013 | 371 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 372 | { |
36cdd013 DW |
373 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
374 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 375 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
376 | u32 count, mapped_count, purgeable_count, dpy_count; |
377 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 378 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 379 | struct drm_file *file; |
73aa808f CW |
380 | int ret; |
381 | ||
382 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
383 | if (ret) | |
384 | return ret; | |
385 | ||
3ef7f228 | 386 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
387 | dev_priv->mm.object_count, |
388 | dev_priv->mm.object_memory); | |
389 | ||
1544c42e CW |
390 | size = count = 0; |
391 | mapped_size = mapped_count = 0; | |
392 | purgeable_size = purgeable_count = 0; | |
56cea323 | 393 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
394 | size += obj->base.size; |
395 | ++count; | |
396 | ||
a4f5ea64 | 397 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
398 | purgeable_size += obj->base.size; |
399 | ++purgeable_count; | |
400 | } | |
401 | ||
a4f5ea64 | 402 | if (obj->mm.mapping) { |
2bd160a1 CW |
403 | mapped_count++; |
404 | mapped_size += obj->base.size; | |
be19b10d | 405 | } |
b7abb714 | 406 | } |
c44ef60e | 407 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 408 | |
2bd160a1 | 409 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 410 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
411 | size += obj->base.size; |
412 | ++count; | |
413 | ||
30154650 | 414 | if (obj->pin_display) { |
2bd160a1 CW |
415 | dpy_size += obj->base.size; |
416 | ++dpy_count; | |
6299f992 | 417 | } |
2bd160a1 | 418 | |
a4f5ea64 | 419 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
420 | purgeable_size += obj->base.size; |
421 | ++purgeable_count; | |
422 | } | |
2bd160a1 | 423 | |
a4f5ea64 | 424 | if (obj->mm.mapping) { |
2bd160a1 CW |
425 | mapped_count++; |
426 | mapped_size += obj->base.size; | |
be19b10d | 427 | } |
6299f992 | 428 | } |
2bd160a1 CW |
429 | seq_printf(m, "%u bound objects, %llu bytes\n", |
430 | count, size); | |
c44ef60e | 431 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 432 | purgeable_count, purgeable_size); |
2bd160a1 CW |
433 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
434 | mapped_count, mapped_size); | |
435 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
436 | dpy_count, dpy_size); | |
6299f992 | 437 | |
c44ef60e | 438 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 439 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 440 | |
493018dc BV |
441 | seq_putc(m, '\n'); |
442 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
443 | mutex_unlock(&dev->struct_mutex); |
444 | ||
445 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 446 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
447 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
448 | struct file_stats stats; | |
c84455b4 CW |
449 | struct drm_i915_file_private *file_priv = file->driver_priv; |
450 | struct drm_i915_gem_request *request; | |
3ec2f427 | 451 | struct task_struct *task; |
2db8e9d6 CW |
452 | |
453 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 454 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 455 | spin_lock(&file->table_lock); |
2db8e9d6 | 456 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 457 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
458 | /* |
459 | * Although we have a valid reference on file->pid, that does | |
460 | * not guarantee that the task_struct who called get_pid() is | |
461 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
462 | * Therefore, we need to protect this ->comm access using RCU. | |
463 | */ | |
c84455b4 CW |
464 | mutex_lock(&dev->struct_mutex); |
465 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
466 | struct drm_i915_gem_request, | |
467 | client_list); | |
3ec2f427 | 468 | rcu_read_lock(); |
c84455b4 CW |
469 | task = pid_task(request && request->ctx->pid ? |
470 | request->ctx->pid : file->pid, | |
471 | PIDTYPE_PID); | |
493018dc | 472 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 473 | rcu_read_unlock(); |
c84455b4 | 474 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 475 | } |
1d2ac403 | 476 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
477 | |
478 | return 0; | |
479 | } | |
480 | ||
aee56cff | 481 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 482 | { |
9f25d007 | 483 | struct drm_info_node *node = m->private; |
36cdd013 DW |
484 | struct drm_i915_private *dev_priv = node_to_i915(node); |
485 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 486 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 487 | struct drm_i915_gem_object *obj; |
c44ef60e | 488 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
489 | int count, ret; |
490 | ||
491 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
492 | if (ret) | |
493 | return ret; | |
494 | ||
495 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 496 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 497 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
498 | continue; |
499 | ||
267f0c90 | 500 | seq_puts(m, " "); |
08c18323 | 501 | describe_obj(m, obj); |
267f0c90 | 502 | seq_putc(m, '\n'); |
08c18323 | 503 | total_obj_size += obj->base.size; |
ca1543be | 504 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
505 | count++; |
506 | } | |
507 | ||
508 | mutex_unlock(&dev->struct_mutex); | |
509 | ||
c44ef60e | 510 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
511 | count, total_obj_size, total_gtt_size); |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
4e5359cd SF |
516 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
517 | { | |
36cdd013 DW |
518 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
519 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 520 | struct intel_crtc *crtc; |
8a270ebf DV |
521 | int ret; |
522 | ||
523 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
524 | if (ret) | |
525 | return ret; | |
4e5359cd | 526 | |
d3fcc808 | 527 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
528 | const char pipe = pipe_name(crtc->pipe); |
529 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 530 | struct intel_flip_work *work; |
4e5359cd | 531 | |
5e2d7afc | 532 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
533 | work = crtc->flip_work; |
534 | if (work == NULL) { | |
9db4a9c7 | 535 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
536 | pipe, plane); |
537 | } else { | |
5a21b665 DV |
538 | u32 pending; |
539 | u32 addr; | |
540 | ||
541 | pending = atomic_read(&work->pending); | |
542 | if (pending) { | |
543 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
544 | pipe, plane); | |
545 | } else { | |
546 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
547 | pipe, plane); | |
548 | } | |
549 | if (work->flip_queued_req) { | |
24327f83 | 550 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 DV |
551 | |
552 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
553 | engine->name, | |
24327f83 | 554 | work->flip_queued_req->global_seqno, |
28176ef4 | 555 | atomic_read(&dev_priv->gt.global_timeline.next_seqno), |
1b7744e7 | 556 | intel_engine_get_seqno(engine), |
f69a02c9 | 557 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
558 | } else |
559 | seq_printf(m, "Flip not associated with any ring\n"); | |
560 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
561 | work->flip_queued_vblank, | |
562 | work->flip_ready_vblank, | |
563 | intel_crtc_get_vblank_counter(crtc)); | |
564 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
565 | ||
36cdd013 | 566 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
567 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
568 | else | |
569 | addr = I915_READ(DSPADDR(crtc->plane)); | |
570 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
571 | ||
572 | if (work->pending_flip_obj) { | |
573 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
574 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
575 | } |
576 | } | |
5e2d7afc | 577 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
578 | } |
579 | ||
8a270ebf DV |
580 | mutex_unlock(&dev->struct_mutex); |
581 | ||
4e5359cd SF |
582 | return 0; |
583 | } | |
584 | ||
493018dc BV |
585 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
586 | { | |
36cdd013 DW |
587 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
588 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 589 | struct drm_i915_gem_object *obj; |
e2f80391 | 590 | struct intel_engine_cs *engine; |
3b3f1650 | 591 | enum intel_engine_id id; |
8d9d5744 | 592 | int total = 0; |
b4ac5afc | 593 | int ret, j; |
493018dc BV |
594 | |
595 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
596 | if (ret) | |
597 | return ret; | |
598 | ||
3b3f1650 | 599 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 600 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
601 | int count; |
602 | ||
603 | count = 0; | |
604 | list_for_each_entry(obj, | |
e2f80391 | 605 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
606 | batch_pool_link) |
607 | count++; | |
608 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 609 | engine->name, j, count); |
8d9d5744 CW |
610 | |
611 | list_for_each_entry(obj, | |
e2f80391 | 612 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
613 | batch_pool_link) { |
614 | seq_puts(m, " "); | |
615 | describe_obj(m, obj); | |
616 | seq_putc(m, '\n'); | |
617 | } | |
618 | ||
619 | total += count; | |
06fbca71 | 620 | } |
493018dc BV |
621 | } |
622 | ||
8d9d5744 | 623 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
624 | |
625 | mutex_unlock(&dev->struct_mutex); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
1b36595f CW |
630 | static void print_request(struct seq_file *m, |
631 | struct drm_i915_gem_request *rq, | |
632 | const char *prefix) | |
633 | { | |
20311bd3 | 634 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 635 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 636 | rq->priotree.priority, |
1b36595f | 637 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 638 | rq->timeline->common->name); |
1b36595f CW |
639 | } |
640 | ||
2017263e BG |
641 | static int i915_gem_request_info(struct seq_file *m, void *data) |
642 | { | |
36cdd013 DW |
643 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
644 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 645 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
646 | struct intel_engine_cs *engine; |
647 | enum intel_engine_id id; | |
b4ac5afc | 648 | int ret, any; |
de227ef0 CW |
649 | |
650 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
651 | if (ret) | |
652 | return ret; | |
2017263e | 653 | |
2d1070b2 | 654 | any = 0; |
3b3f1650 | 655 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
656 | int count; |
657 | ||
658 | count = 0; | |
73cb9701 | 659 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
660 | count++; |
661 | if (count == 0) | |
a2c7f6fd CW |
662 | continue; |
663 | ||
e2f80391 | 664 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 665 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 666 | print_request(m, req, " "); |
2d1070b2 CW |
667 | |
668 | any++; | |
2017263e | 669 | } |
de227ef0 CW |
670 | mutex_unlock(&dev->struct_mutex); |
671 | ||
2d1070b2 | 672 | if (any == 0) |
267f0c90 | 673 | seq_puts(m, "No requests\n"); |
c2c347a9 | 674 | |
2017263e BG |
675 | return 0; |
676 | } | |
677 | ||
b2223497 | 678 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 679 | struct intel_engine_cs *engine) |
b2223497 | 680 | { |
688e6c72 CW |
681 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
682 | struct rb_node *rb; | |
683 | ||
12471ba8 | 684 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 685 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 686 | |
f6168e33 | 687 | spin_lock_irq(&b->lock); |
688e6c72 CW |
688 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
689 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
690 | ||
691 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
692 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
693 | } | |
f6168e33 | 694 | spin_unlock_irq(&b->lock); |
b2223497 CW |
695 | } |
696 | ||
2017263e BG |
697 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
698 | { | |
36cdd013 | 699 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 700 | struct intel_engine_cs *engine; |
3b3f1650 | 701 | enum intel_engine_id id; |
2017263e | 702 | |
3b3f1650 | 703 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 704 | i915_ring_seqno_info(m, engine); |
de227ef0 | 705 | |
2017263e BG |
706 | return 0; |
707 | } | |
708 | ||
709 | ||
710 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
711 | { | |
36cdd013 | 712 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 713 | struct intel_engine_cs *engine; |
3b3f1650 | 714 | enum intel_engine_id id; |
4bb05040 | 715 | int i, pipe; |
de227ef0 | 716 | |
c8c8fb33 | 717 | intel_runtime_pm_get(dev_priv); |
2017263e | 718 | |
36cdd013 | 719 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
720 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
721 | I915_READ(GEN8_MASTER_IRQ)); | |
722 | ||
723 | seq_printf(m, "Display IER:\t%08x\n", | |
724 | I915_READ(VLV_IER)); | |
725 | seq_printf(m, "Display IIR:\t%08x\n", | |
726 | I915_READ(VLV_IIR)); | |
727 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
728 | I915_READ(VLV_IIR_RW)); | |
729 | seq_printf(m, "Display IMR:\t%08x\n", | |
730 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
731 | for_each_pipe(dev_priv, pipe) { |
732 | enum intel_display_power_domain power_domain; | |
733 | ||
734 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
735 | if (!intel_display_power_get_if_enabled(dev_priv, | |
736 | power_domain)) { | |
737 | seq_printf(m, "Pipe %c power disabled\n", | |
738 | pipe_name(pipe)); | |
739 | continue; | |
740 | } | |
741 | ||
74e1ca8c VS |
742 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
743 | pipe_name(pipe), | |
744 | I915_READ(PIPESTAT(pipe))); | |
745 | ||
9c870d03 CW |
746 | intel_display_power_put(dev_priv, power_domain); |
747 | } | |
748 | ||
749 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
750 | seq_printf(m, "Port hotplug:\t%08x\n", |
751 | I915_READ(PORT_HOTPLUG_EN)); | |
752 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
753 | I915_READ(VLV_DPFLIPSTAT)); | |
754 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
755 | I915_READ(DPINVGTT)); | |
9c870d03 | 756 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
757 | |
758 | for (i = 0; i < 4; i++) { | |
759 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
760 | i, I915_READ(GEN8_GT_IMR(i))); | |
761 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
762 | i, I915_READ(GEN8_GT_IIR(i))); | |
763 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
764 | i, I915_READ(GEN8_GT_IER(i))); | |
765 | } | |
766 | ||
767 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
768 | I915_READ(GEN8_PCU_IMR)); | |
769 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
770 | I915_READ(GEN8_PCU_IIR)); | |
771 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
772 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 773 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
774 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
775 | I915_READ(GEN8_MASTER_IRQ)); | |
776 | ||
777 | for (i = 0; i < 4; i++) { | |
778 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
779 | i, I915_READ(GEN8_GT_IMR(i))); | |
780 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
781 | i, I915_READ(GEN8_GT_IIR(i))); | |
782 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
783 | i, I915_READ(GEN8_GT_IER(i))); | |
784 | } | |
785 | ||
055e393f | 786 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
787 | enum intel_display_power_domain power_domain; |
788 | ||
789 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
790 | if (!intel_display_power_get_if_enabled(dev_priv, | |
791 | power_domain)) { | |
22c59960 PZ |
792 | seq_printf(m, "Pipe %c power disabled\n", |
793 | pipe_name(pipe)); | |
794 | continue; | |
795 | } | |
a123f157 | 796 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
797 | pipe_name(pipe), |
798 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 799 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
800 | pipe_name(pipe), |
801 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 802 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
803 | pipe_name(pipe), |
804 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
805 | |
806 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
807 | } |
808 | ||
809 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
810 | I915_READ(GEN8_DE_PORT_IMR)); | |
811 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
812 | I915_READ(GEN8_DE_PORT_IIR)); | |
813 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
814 | I915_READ(GEN8_DE_PORT_IER)); | |
815 | ||
816 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
817 | I915_READ(GEN8_DE_MISC_IMR)); | |
818 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
819 | I915_READ(GEN8_DE_MISC_IIR)); | |
820 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
821 | I915_READ(GEN8_DE_MISC_IER)); | |
822 | ||
823 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
824 | I915_READ(GEN8_PCU_IMR)); | |
825 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
826 | I915_READ(GEN8_PCU_IIR)); | |
827 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
828 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 829 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
830 | seq_printf(m, "Display IER:\t%08x\n", |
831 | I915_READ(VLV_IER)); | |
832 | seq_printf(m, "Display IIR:\t%08x\n", | |
833 | I915_READ(VLV_IIR)); | |
834 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
835 | I915_READ(VLV_IIR_RW)); | |
836 | seq_printf(m, "Display IMR:\t%08x\n", | |
837 | I915_READ(VLV_IMR)); | |
055e393f | 838 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
839 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
840 | pipe_name(pipe), | |
841 | I915_READ(PIPESTAT(pipe))); | |
842 | ||
843 | seq_printf(m, "Master IER:\t%08x\n", | |
844 | I915_READ(VLV_MASTER_IER)); | |
845 | ||
846 | seq_printf(m, "Render IER:\t%08x\n", | |
847 | I915_READ(GTIER)); | |
848 | seq_printf(m, "Render IIR:\t%08x\n", | |
849 | I915_READ(GTIIR)); | |
850 | seq_printf(m, "Render IMR:\t%08x\n", | |
851 | I915_READ(GTIMR)); | |
852 | ||
853 | seq_printf(m, "PM IER:\t\t%08x\n", | |
854 | I915_READ(GEN6_PMIER)); | |
855 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
856 | I915_READ(GEN6_PMIIR)); | |
857 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
858 | I915_READ(GEN6_PMIMR)); | |
859 | ||
860 | seq_printf(m, "Port hotplug:\t%08x\n", | |
861 | I915_READ(PORT_HOTPLUG_EN)); | |
862 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
863 | I915_READ(VLV_DPFLIPSTAT)); | |
864 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
865 | I915_READ(DPINVGTT)); | |
866 | ||
36cdd013 | 867 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
868 | seq_printf(m, "Interrupt enable: %08x\n", |
869 | I915_READ(IER)); | |
870 | seq_printf(m, "Interrupt identity: %08x\n", | |
871 | I915_READ(IIR)); | |
872 | seq_printf(m, "Interrupt mask: %08x\n", | |
873 | I915_READ(IMR)); | |
055e393f | 874 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
875 | seq_printf(m, "Pipe %c stat: %08x\n", |
876 | pipe_name(pipe), | |
877 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
878 | } else { |
879 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
880 | I915_READ(DEIER)); | |
881 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
882 | I915_READ(DEIIR)); | |
883 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
884 | I915_READ(DEIMR)); | |
885 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
886 | I915_READ(SDEIER)); | |
887 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
888 | I915_READ(SDEIIR)); | |
889 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
890 | I915_READ(SDEIMR)); | |
891 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
892 | I915_READ(GTIER)); | |
893 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
894 | I915_READ(GTIIR)); | |
895 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
896 | I915_READ(GTIMR)); | |
897 | } | |
3b3f1650 | 898 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 899 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
900 | seq_printf(m, |
901 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 902 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 903 | } |
e2f80391 | 904 | i915_ring_seqno_info(m, engine); |
9862e600 | 905 | } |
c8c8fb33 | 906 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 907 | |
2017263e BG |
908 | return 0; |
909 | } | |
910 | ||
a6172a80 CW |
911 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
912 | { | |
36cdd013 DW |
913 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
914 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
915 | int i, ret; |
916 | ||
917 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
918 | if (ret) | |
919 | return ret; | |
a6172a80 | 920 | |
a6172a80 CW |
921 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
922 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 923 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 924 | |
6c085a72 CW |
925 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
926 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 927 | if (!vma) |
267f0c90 | 928 | seq_puts(m, "unused"); |
c2c347a9 | 929 | else |
49ef5294 | 930 | describe_obj(m, vma->obj); |
267f0c90 | 931 | seq_putc(m, '\n'); |
a6172a80 CW |
932 | } |
933 | ||
05394f39 | 934 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
935 | return 0; |
936 | } | |
937 | ||
2017263e BG |
938 | static int i915_hws_info(struct seq_file *m, void *data) |
939 | { | |
9f25d007 | 940 | struct drm_info_node *node = m->private; |
36cdd013 | 941 | struct drm_i915_private *dev_priv = node_to_i915(node); |
e2f80391 | 942 | struct intel_engine_cs *engine; |
1a240d4d | 943 | const u32 *hws; |
4066c0ae CW |
944 | int i; |
945 | ||
3b3f1650 | 946 | engine = dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 947 | hws = engine->status_page.page_addr; |
2017263e BG |
948 | if (hws == NULL) |
949 | return 0; | |
950 | ||
951 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
952 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
953 | i * 4, | |
954 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
955 | } | |
956 | return 0; | |
957 | } | |
958 | ||
98a2f411 CW |
959 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
960 | ||
d5442303 DV |
961 | static ssize_t |
962 | i915_error_state_write(struct file *filp, | |
963 | const char __user *ubuf, | |
964 | size_t cnt, | |
965 | loff_t *ppos) | |
966 | { | |
edc3d884 | 967 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
968 | |
969 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
662d19e7 | 970 | i915_destroy_error_state(error_priv->dev); |
d5442303 DV |
971 | |
972 | return cnt; | |
973 | } | |
974 | ||
975 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
976 | { | |
36cdd013 | 977 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 978 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
979 | |
980 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
981 | if (!error_priv) | |
982 | return -ENOMEM; | |
983 | ||
36cdd013 | 984 | error_priv->dev = &dev_priv->drm; |
d5442303 | 985 | |
36cdd013 | 986 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 987 | |
edc3d884 MK |
988 | file->private_data = error_priv; |
989 | ||
990 | return 0; | |
d5442303 DV |
991 | } |
992 | ||
993 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
994 | { | |
edc3d884 | 995 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 996 | |
95d5bfb3 | 997 | i915_error_state_put(error_priv); |
d5442303 DV |
998 | kfree(error_priv); |
999 | ||
edc3d884 MK |
1000 | return 0; |
1001 | } | |
1002 | ||
4dc955f7 MK |
1003 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1004 | size_t count, loff_t *pos) | |
1005 | { | |
1006 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1007 | struct drm_i915_error_state_buf error_str; | |
1008 | loff_t tmp_pos = 0; | |
1009 | ssize_t ret_count = 0; | |
1010 | int ret; | |
1011 | ||
36cdd013 DW |
1012 | ret = i915_error_state_buf_init(&error_str, |
1013 | to_i915(error_priv->dev), count, *pos); | |
4dc955f7 MK |
1014 | if (ret) |
1015 | return ret; | |
edc3d884 | 1016 | |
fc16b48b | 1017 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1018 | if (ret) |
1019 | goto out; | |
1020 | ||
edc3d884 MK |
1021 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1022 | error_str.buf, | |
1023 | error_str.bytes); | |
1024 | ||
1025 | if (ret_count < 0) | |
1026 | ret = ret_count; | |
1027 | else | |
1028 | *pos = error_str.start + ret_count; | |
1029 | out: | |
4dc955f7 | 1030 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1031 | return ret ?: ret_count; |
d5442303 DV |
1032 | } |
1033 | ||
1034 | static const struct file_operations i915_error_state_fops = { | |
1035 | .owner = THIS_MODULE, | |
1036 | .open = i915_error_state_open, | |
edc3d884 | 1037 | .read = i915_error_state_read, |
d5442303 DV |
1038 | .write = i915_error_state_write, |
1039 | .llseek = default_llseek, | |
1040 | .release = i915_error_state_release, | |
1041 | }; | |
1042 | ||
98a2f411 CW |
1043 | #endif |
1044 | ||
647416f9 KC |
1045 | static int |
1046 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1047 | { |
36cdd013 | 1048 | struct drm_i915_private *dev_priv = data; |
40633219 | 1049 | |
28176ef4 | 1050 | *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno); |
647416f9 | 1051 | return 0; |
40633219 MK |
1052 | } |
1053 | ||
647416f9 KC |
1054 | static int |
1055 | i915_next_seqno_set(void *data, u64 val) | |
1056 | { | |
36cdd013 DW |
1057 | struct drm_i915_private *dev_priv = data; |
1058 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1059 | int ret; |
1060 | ||
40633219 MK |
1061 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1062 | if (ret) | |
1063 | return ret; | |
1064 | ||
73cb9701 | 1065 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1066 | mutex_unlock(&dev->struct_mutex); |
1067 | ||
647416f9 | 1068 | return ret; |
40633219 MK |
1069 | } |
1070 | ||
647416f9 KC |
1071 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1072 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1073 | "0x%llx\n"); |
40633219 | 1074 | |
adb4bd12 | 1075 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1076 | { |
36cdd013 DW |
1077 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1078 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1079 | int ret = 0; |
1080 | ||
1081 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1082 | |
36cdd013 | 1083 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1084 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1085 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1086 | ||
1087 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1088 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1089 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1090 | MEMSTAT_VID_SHIFT); | |
1091 | seq_printf(m, "Current P-state: %d\n", | |
1092 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1093 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1094 | u32 freq_sts; |
1095 | ||
1096 | mutex_lock(&dev_priv->rps.hw_lock); | |
1097 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1098 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1099 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1100 | ||
1101 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1102 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1103 | ||
1104 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1105 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1106 | ||
1107 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1108 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1109 | ||
1110 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1111 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1112 | ||
1113 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1114 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1115 | ||
1116 | seq_printf(m, | |
1117 | "efficient (RPe) frequency: %d MHz\n", | |
1118 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1119 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1120 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1121 | u32 rp_state_limits; |
1122 | u32 gt_perf_status; | |
1123 | u32 rp_state_cap; | |
0d8f9491 | 1124 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1125 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1126 | u32 rpupei, rpcurup, rpprevup; |
1127 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1128 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1129 | int max_freq; |
1130 | ||
35040562 | 1131 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
36cdd013 | 1132 | if (IS_BROXTON(dev_priv)) { |
35040562 BP |
1133 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1134 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1135 | } else { | |
1136 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1137 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1138 | } | |
1139 | ||
3b8d8d91 | 1140 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1141 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1142 | if (ret) | |
c8c8fb33 | 1143 | goto out; |
d1ebd816 | 1144 | |
59bad947 | 1145 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1146 | |
8e8c06cd | 1147 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1148 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1149 | reqf >>= 23; |
1150 | else { | |
1151 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1152 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1153 | reqf >>= 24; |
1154 | else | |
1155 | reqf >>= 25; | |
1156 | } | |
7c59a9c1 | 1157 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1158 | |
0d8f9491 CW |
1159 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1160 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1161 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1162 | ||
ccab5c82 | 1163 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1164 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1165 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1166 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1167 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1168 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1169 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1170 | if (IS_GEN9(dev_priv)) |
60260a5b | 1171 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1172 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1173 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1174 | else | |
1175 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1176 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1177 | |
59bad947 | 1178 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1179 | mutex_unlock(&dev->struct_mutex); |
1180 | ||
36cdd013 | 1181 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1182 | pm_ier = I915_READ(GEN6_PMIER); |
1183 | pm_imr = I915_READ(GEN6_PMIMR); | |
1184 | pm_isr = I915_READ(GEN6_PMISR); | |
1185 | pm_iir = I915_READ(GEN6_PMIIR); | |
1186 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1187 | } else { | |
1188 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1189 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1190 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1191 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1192 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1193 | } | |
0d8f9491 | 1194 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1195 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1196 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1197 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1198 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1199 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1200 | seq_printf(m, "Render p-state VID: %d\n", |
1201 | gt_perf_status & 0xff); | |
1202 | seq_printf(m, "Render p-state limit: %d\n", | |
1203 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1204 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1205 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1206 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1207 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1208 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1209 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1210 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1211 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1212 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1213 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1214 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1215 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1216 | seq_printf(m, "Up threshold: %d%%\n", |
1217 | dev_priv->rps.up_threshold); | |
1218 | ||
d6cda9c7 AG |
1219 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1220 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1221 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1222 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1223 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1224 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1225 | seq_printf(m, "Down threshold: %d%%\n", |
1226 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1227 | |
36cdd013 | 1228 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1229 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1230 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1231 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1232 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1233 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1234 | |
1235 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1236 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1237 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1238 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1239 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1240 | |
36cdd013 | 1241 | max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1242 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1243 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1244 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1245 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1246 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1247 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1248 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1249 | |
d86ed34a CW |
1250 | seq_printf(m, "Current freq: %d MHz\n", |
1251 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1252 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1253 | seq_printf(m, "Idle freq: %d MHz\n", |
1254 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1255 | seq_printf(m, "Min freq: %d MHz\n", |
1256 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1257 | seq_printf(m, "Boost freq: %d MHz\n", |
1258 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1259 | seq_printf(m, "Max freq: %d MHz\n", |
1260 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1261 | seq_printf(m, | |
1262 | "efficient (RPe) frequency: %d MHz\n", | |
1263 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1264 | } else { |
267f0c90 | 1265 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1266 | } |
f97108d1 | 1267 | |
1170f28c MK |
1268 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1269 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1270 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1271 | ||
c8c8fb33 PZ |
1272 | out: |
1273 | intel_runtime_pm_put(dev_priv); | |
1274 | return ret; | |
f97108d1 JB |
1275 | } |
1276 | ||
d636951e BW |
1277 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1278 | struct seq_file *m, | |
1279 | struct intel_instdone *instdone) | |
1280 | { | |
f9e61372 BW |
1281 | int slice; |
1282 | int subslice; | |
1283 | ||
d636951e BW |
1284 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1285 | instdone->instdone); | |
1286 | ||
1287 | if (INTEL_GEN(dev_priv) <= 3) | |
1288 | return; | |
1289 | ||
1290 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1291 | instdone->slice_common); | |
1292 | ||
1293 | if (INTEL_GEN(dev_priv) <= 6) | |
1294 | return; | |
1295 | ||
f9e61372 BW |
1296 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1297 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1298 | slice, subslice, instdone->sampler[slice][subslice]); | |
1299 | ||
1300 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1301 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1302 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1303 | } |
1304 | ||
f654449a CW |
1305 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1306 | { | |
36cdd013 | 1307 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1308 | struct intel_engine_cs *engine; |
666796da TU |
1309 | u64 acthd[I915_NUM_ENGINES]; |
1310 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1311 | struct intel_instdone instdone; |
c3232b18 | 1312 | enum intel_engine_id id; |
f654449a | 1313 | |
8af29b0c CW |
1314 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1315 | seq_printf(m, "Wedged\n"); | |
1316 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1317 | seq_printf(m, "Reset in progress\n"); | |
1318 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1319 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1320 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1321 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1322 | ||
f654449a CW |
1323 | if (!i915.enable_hangcheck) { |
1324 | seq_printf(m, "Hangcheck disabled\n"); | |
1325 | return 0; | |
1326 | } | |
1327 | ||
ebbc7546 MK |
1328 | intel_runtime_pm_get(dev_priv); |
1329 | ||
3b3f1650 | 1330 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1331 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1332 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1333 | } |
1334 | ||
3b3f1650 | 1335 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1336 | |
ebbc7546 MK |
1337 | intel_runtime_pm_put(dev_priv); |
1338 | ||
f654449a CW |
1339 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1340 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1341 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1342 | jiffies)); | |
1343 | } else | |
1344 | seq_printf(m, "Hangcheck inactive\n"); | |
1345 | ||
3b3f1650 | 1346 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1347 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1348 | struct rb_node *rb; | |
1349 | ||
e2f80391 | 1350 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d | 1351 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
cb399eab CW |
1352 | engine->hangcheck.seqno, seqno[id], |
1353 | intel_engine_last_submit(engine)); | |
83348ba8 CW |
1354 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1355 | yesno(intel_engine_has_waiter(engine)), | |
1356 | yesno(test_bit(engine->id, | |
1357 | &dev_priv->gpu_error.missed_irq_rings))); | |
f6168e33 | 1358 | spin_lock_irq(&b->lock); |
33f53719 CW |
1359 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
1360 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
1361 | ||
1362 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1363 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1364 | } | |
f6168e33 | 1365 | spin_unlock_irq(&b->lock); |
33f53719 | 1366 | |
f654449a | 1367 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1368 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1369 | (long long)acthd[id]); |
e2f80391 TU |
1370 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1371 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1372 | |
e2f80391 | 1373 | if (engine->id == RCS) { |
d636951e | 1374 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1375 | |
d636951e | 1376 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1377 | |
d636951e | 1378 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1379 | |
d636951e BW |
1380 | i915_instdone_info(dev_priv, m, |
1381 | &engine->hangcheck.instdone); | |
61642ff0 | 1382 | } |
f654449a CW |
1383 | } |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
4d85529d | 1388 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1389 | { |
36cdd013 | 1390 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1391 | u32 rgvmodectl, rstdbyctl; |
1392 | u16 crstandvid; | |
616fdb5a | 1393 | |
c8c8fb33 | 1394 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1395 | |
1396 | rgvmodectl = I915_READ(MEMMODECTL); | |
1397 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1398 | crstandvid = I915_READ16(CRSTANDVID); | |
1399 | ||
c8c8fb33 | 1400 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1401 | |
742f491d | 1402 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1403 | seq_printf(m, "Boost freq: %d\n", |
1404 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1405 | MEMMODE_BOOST_FREQ_SHIFT); | |
1406 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1407 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1408 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1409 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1410 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1411 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1412 | seq_printf(m, "Starting frequency: P%d\n", |
1413 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1414 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1415 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1416 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1417 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1418 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1419 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1420 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1421 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1422 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1423 | case RSX_STATUS_ON: | |
267f0c90 | 1424 | seq_puts(m, "on\n"); |
88271da3 JB |
1425 | break; |
1426 | case RSX_STATUS_RC1: | |
267f0c90 | 1427 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1428 | break; |
1429 | case RSX_STATUS_RC1E: | |
267f0c90 | 1430 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1431 | break; |
1432 | case RSX_STATUS_RS1: | |
267f0c90 | 1433 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1434 | break; |
1435 | case RSX_STATUS_RS2: | |
267f0c90 | 1436 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1437 | break; |
1438 | case RSX_STATUS_RS3: | |
267f0c90 | 1439 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1440 | break; |
1441 | default: | |
267f0c90 | 1442 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1443 | break; |
1444 | } | |
f97108d1 JB |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
f65367b5 | 1449 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1450 | { |
36cdd013 | 1451 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1452 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1453 | |
1454 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1455 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1456 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1457 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1458 | fw_domain->wake_count); |
1459 | } | |
1460 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1461 | |
b2cff0db CW |
1462 | return 0; |
1463 | } | |
1464 | ||
1465 | static int vlv_drpc_info(struct seq_file *m) | |
1466 | { | |
36cdd013 | 1467 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1468 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1469 | |
d46c0517 ID |
1470 | intel_runtime_pm_get(dev_priv); |
1471 | ||
6b312cd3 | 1472 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1473 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1474 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1475 | ||
d46c0517 ID |
1476 | intel_runtime_pm_put(dev_priv); |
1477 | ||
669ab5aa D |
1478 | seq_printf(m, "Video Turbo Mode: %s\n", |
1479 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1480 | seq_printf(m, "Turbo enabled: %s\n", | |
1481 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1482 | seq_printf(m, "HW control enabled: %s\n", | |
1483 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1484 | seq_printf(m, "SW control enabled: %s\n", | |
1485 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1486 | GEN6_RP_MEDIA_SW_MODE)); | |
1487 | seq_printf(m, "RC6 Enabled: %s\n", | |
1488 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1489 | GEN6_RC_CTL_EI_MODE(1)))); | |
1490 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1491 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1492 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1493 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1494 | |
9cc19be5 ID |
1495 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1496 | I915_READ(VLV_GT_RENDER_RC6)); | |
1497 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1498 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1499 | ||
f65367b5 | 1500 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1501 | } |
1502 | ||
4d85529d BW |
1503 | static int gen6_drpc_info(struct seq_file *m) |
1504 | { | |
36cdd013 DW |
1505 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1506 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1507 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1508 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1509 | unsigned forcewake_count; |
aee56cff | 1510 | int count = 0, ret; |
4d85529d BW |
1511 | |
1512 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1513 | if (ret) | |
1514 | return ret; | |
c8c8fb33 | 1515 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1516 | |
907b28c5 | 1517 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1518 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1519 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1520 | |
1521 | if (forcewake_count) { | |
267f0c90 DL |
1522 | seq_puts(m, "RC information inaccurate because somebody " |
1523 | "holds a forcewake reference \n"); | |
4d85529d BW |
1524 | } else { |
1525 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1526 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1527 | udelay(10); | |
1528 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1529 | } | |
1530 | ||
75aa3f63 | 1531 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1532 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1533 | |
1534 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1535 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1536 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1537 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1538 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1539 | } | |
4d85529d | 1540 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1541 | mutex_lock(&dev_priv->rps.hw_lock); |
1542 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1543 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1544 | |
c8c8fb33 PZ |
1545 | intel_runtime_pm_put(dev_priv); |
1546 | ||
4d85529d BW |
1547 | seq_printf(m, "Video Turbo Mode: %s\n", |
1548 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1549 | seq_printf(m, "HW control enabled: %s\n", | |
1550 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1551 | seq_printf(m, "SW control enabled: %s\n", | |
1552 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1553 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1554 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1555 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1556 | seq_printf(m, "RC6 Enabled: %s\n", | |
1557 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1558 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1559 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1560 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1561 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1562 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1563 | } | |
4d85529d BW |
1564 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1565 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1566 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1567 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1568 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1569 | switch (gt_core_status & GEN6_RCn_MASK) { |
1570 | case GEN6_RC0: | |
1571 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1572 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1573 | else |
267f0c90 | 1574 | seq_puts(m, "on\n"); |
4d85529d BW |
1575 | break; |
1576 | case GEN6_RC3: | |
267f0c90 | 1577 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1578 | break; |
1579 | case GEN6_RC6: | |
267f0c90 | 1580 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1581 | break; |
1582 | case GEN6_RC7: | |
267f0c90 | 1583 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1584 | break; |
1585 | default: | |
267f0c90 | 1586 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1587 | break; |
1588 | } | |
1589 | ||
1590 | seq_printf(m, "Core Power Down: %s\n", | |
1591 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1592 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1593 | seq_printf(m, "Render Power Well: %s\n", |
1594 | (gen9_powergate_status & | |
1595 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1596 | seq_printf(m, "Media Power Well: %s\n", | |
1597 | (gen9_powergate_status & | |
1598 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1599 | } | |
cce66a28 BW |
1600 | |
1601 | /* Not exactly sure what this is */ | |
1602 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1603 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1604 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1605 | I915_READ(GEN6_GT_GFX_RC6)); | |
1606 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1607 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1608 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1609 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1610 | ||
ecd8faea BW |
1611 | seq_printf(m, "RC6 voltage: %dmV\n", |
1612 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1613 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1614 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1615 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1616 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1617 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1618 | } |
1619 | ||
1620 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1621 | { | |
36cdd013 | 1622 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1623 | |
36cdd013 | 1624 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1625 | return vlv_drpc_info(m); |
36cdd013 | 1626 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1627 | return gen6_drpc_info(m); |
1628 | else | |
1629 | return ironlake_drpc_info(m); | |
1630 | } | |
1631 | ||
9a851789 DV |
1632 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1633 | { | |
36cdd013 | 1634 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1635 | |
1636 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1637 | dev_priv->fb_tracking.busy_bits); | |
1638 | ||
1639 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1640 | dev_priv->fb_tracking.flip_bits); | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
b5e50c3f JB |
1645 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1646 | { | |
36cdd013 | 1647 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1648 | |
36cdd013 | 1649 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1650 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1651 | return 0; |
1652 | } | |
1653 | ||
36623ef8 | 1654 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1655 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1656 | |
0e631adc | 1657 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1658 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1659 | else |
1660 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1661 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1662 | |
0fc6a9dc PZ |
1663 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1664 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1665 | BDW_FBC_COMPRESSION_MASK : | |
1666 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1667 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1668 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1669 | } | |
31b9df10 | 1670 | |
25ad93fd | 1671 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1672 | intel_runtime_pm_put(dev_priv); |
1673 | ||
b5e50c3f JB |
1674 | return 0; |
1675 | } | |
1676 | ||
da46f936 RV |
1677 | static int i915_fbc_fc_get(void *data, u64 *val) |
1678 | { | |
36cdd013 | 1679 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1680 | |
36cdd013 | 1681 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1682 | return -ENODEV; |
1683 | ||
da46f936 | 1684 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1685 | |
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | static int i915_fbc_fc_set(void *data, u64 val) | |
1690 | { | |
36cdd013 | 1691 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1692 | u32 reg; |
1693 | ||
36cdd013 | 1694 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1695 | return -ENODEV; |
1696 | ||
25ad93fd | 1697 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1698 | |
1699 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1700 | dev_priv->fbc.false_color = val; | |
1701 | ||
1702 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1703 | (reg | FBC_CTL_FALSE_COLOR) : | |
1704 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1705 | ||
25ad93fd | 1706 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1707 | return 0; |
1708 | } | |
1709 | ||
1710 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1711 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1712 | "%llu\n"); | |
1713 | ||
92d44621 PZ |
1714 | static int i915_ips_status(struct seq_file *m, void *unused) |
1715 | { | |
36cdd013 | 1716 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1717 | |
36cdd013 | 1718 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1719 | seq_puts(m, "not supported\n"); |
1720 | return 0; | |
1721 | } | |
1722 | ||
36623ef8 PZ |
1723 | intel_runtime_pm_get(dev_priv); |
1724 | ||
0eaa53f0 RV |
1725 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1726 | yesno(i915.enable_ips)); | |
1727 | ||
36cdd013 | 1728 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1729 | seq_puts(m, "Currently: unknown\n"); |
1730 | } else { | |
1731 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1732 | seq_puts(m, "Currently: enabled\n"); | |
1733 | else | |
1734 | seq_puts(m, "Currently: disabled\n"); | |
1735 | } | |
92d44621 | 1736 | |
36623ef8 PZ |
1737 | intel_runtime_pm_put(dev_priv); |
1738 | ||
92d44621 PZ |
1739 | return 0; |
1740 | } | |
1741 | ||
4a9bef37 JB |
1742 | static int i915_sr_status(struct seq_file *m, void *unused) |
1743 | { | |
36cdd013 | 1744 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1745 | bool sr_enabled = false; |
1746 | ||
36623ef8 | 1747 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1748 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1749 | |
36cdd013 | 1750 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1751 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
36cdd013 DW |
1752 | else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || |
1753 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) | |
4a9bef37 | 1754 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1755 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1756 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1757 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1758 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1759 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1760 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1761 | |
9c870d03 | 1762 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1763 | intel_runtime_pm_put(dev_priv); |
1764 | ||
08c4d7fc | 1765 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1766 | |
1767 | return 0; | |
1768 | } | |
1769 | ||
7648fa99 JB |
1770 | static int i915_emon_status(struct seq_file *m, void *unused) |
1771 | { | |
36cdd013 DW |
1772 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1773 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1774 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1775 | int ret; |
1776 | ||
36cdd013 | 1777 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1778 | return -ENODEV; |
1779 | ||
de227ef0 CW |
1780 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1781 | if (ret) | |
1782 | return ret; | |
7648fa99 JB |
1783 | |
1784 | temp = i915_mch_val(dev_priv); | |
1785 | chipset = i915_chipset_val(dev_priv); | |
1786 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1787 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1788 | |
1789 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1790 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1791 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1792 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
23b2f8bb JB |
1797 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1798 | { | |
36cdd013 | 1799 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1800 | int ret = 0; |
23b2f8bb | 1801 | int gpu_freq, ia_freq; |
f936ec34 | 1802 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1803 | |
26310346 | 1804 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1805 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1806 | return 0; |
1807 | } | |
1808 | ||
5bfa0199 PZ |
1809 | intel_runtime_pm_get(dev_priv); |
1810 | ||
4fc688ce | 1811 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1812 | if (ret) |
5bfa0199 | 1813 | goto out; |
23b2f8bb | 1814 | |
36cdd013 | 1815 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1816 | /* Convert GT frequency to 50 HZ units */ |
1817 | min_gpu_freq = | |
1818 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1819 | max_gpu_freq = | |
1820 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1821 | } else { | |
1822 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1823 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1824 | } | |
1825 | ||
267f0c90 | 1826 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1827 | |
f936ec34 | 1828 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1829 | ia_freq = gpu_freq; |
1830 | sandybridge_pcode_read(dev_priv, | |
1831 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1832 | &ia_freq); | |
3ebecd07 | 1833 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1834 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1835 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1836 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1837 | ((ia_freq >> 0) & 0xff) * 100, |
1838 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1839 | } |
1840 | ||
4fc688ce | 1841 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1842 | |
5bfa0199 PZ |
1843 | out: |
1844 | intel_runtime_pm_put(dev_priv); | |
1845 | return ret; | |
23b2f8bb JB |
1846 | } |
1847 | ||
44834a67 CW |
1848 | static int i915_opregion(struct seq_file *m, void *unused) |
1849 | { | |
36cdd013 DW |
1850 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1851 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1852 | struct intel_opregion *opregion = &dev_priv->opregion; |
1853 | int ret; | |
1854 | ||
1855 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1856 | if (ret) | |
0d38f009 | 1857 | goto out; |
44834a67 | 1858 | |
2455a8e4 JN |
1859 | if (opregion->header) |
1860 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1861 | |
1862 | mutex_unlock(&dev->struct_mutex); | |
1863 | ||
0d38f009 | 1864 | out: |
44834a67 CW |
1865 | return 0; |
1866 | } | |
1867 | ||
ada8f955 JN |
1868 | static int i915_vbt(struct seq_file *m, void *unused) |
1869 | { | |
36cdd013 | 1870 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1871 | |
1872 | if (opregion->vbt) | |
1873 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
37811fcc CW |
1878 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1879 | { | |
36cdd013 DW |
1880 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1881 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1882 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1883 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1884 | int ret; |
1885 | ||
1886 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1887 | if (ret) | |
1888 | return ret; | |
37811fcc | 1889 | |
0695726e | 1890 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1891 | if (dev_priv->fbdev) { |
1892 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1893 | |
1894 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1895 | fbdev_fb->base.width, | |
1896 | fbdev_fb->base.height, | |
1897 | fbdev_fb->base.depth, | |
1898 | fbdev_fb->base.bits_per_pixel, | |
1899 | fbdev_fb->base.modifier[0], | |
1900 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1901 | describe_obj(m, fbdev_fb->obj); | |
1902 | seq_putc(m, '\n'); | |
1903 | } | |
4520f53a | 1904 | #endif |
37811fcc | 1905 | |
4b096ac1 | 1906 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1907 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1908 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1909 | if (fb == fbdev_fb) | |
37811fcc CW |
1910 | continue; |
1911 | ||
c1ca506d | 1912 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1913 | fb->base.width, |
1914 | fb->base.height, | |
1915 | fb->base.depth, | |
623f9783 | 1916 | fb->base.bits_per_pixel, |
c1ca506d | 1917 | fb->base.modifier[0], |
747a598f | 1918 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1919 | describe_obj(m, fb->obj); |
267f0c90 | 1920 | seq_putc(m, '\n'); |
37811fcc | 1921 | } |
4b096ac1 | 1922 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1923 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1924 | |
1925 | return 0; | |
1926 | } | |
1927 | ||
7e37f889 | 1928 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1929 | { |
1930 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1931 | ring->space, ring->head, ring->tail, |
1932 | ring->last_retired_head); | |
c9fe99bd OM |
1933 | } |
1934 | ||
e76d3630 BW |
1935 | static int i915_context_status(struct seq_file *m, void *unused) |
1936 | { | |
36cdd013 DW |
1937 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1938 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1939 | struct intel_engine_cs *engine; |
e2efd130 | 1940 | struct i915_gem_context *ctx; |
3b3f1650 | 1941 | enum intel_engine_id id; |
c3232b18 | 1942 | int ret; |
e76d3630 | 1943 | |
f3d28878 | 1944 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1945 | if (ret) |
1946 | return ret; | |
1947 | ||
a33afea5 | 1948 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1949 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1950 | if (ctx->pid) { |
d28b99ab CW |
1951 | struct task_struct *task; |
1952 | ||
c84455b4 | 1953 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1954 | if (task) { |
1955 | seq_printf(m, "(%s [%d]) ", | |
1956 | task->comm, task->pid); | |
1957 | put_task_struct(task); | |
1958 | } | |
c84455b4 CW |
1959 | } else if (IS_ERR(ctx->file_priv)) { |
1960 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1961 | } else { |
1962 | seq_puts(m, "(kernel) "); | |
1963 | } | |
1964 | ||
bca44d80 CW |
1965 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1966 | seq_putc(m, '\n'); | |
c9fe99bd | 1967 | |
3b3f1650 | 1968 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1969 | struct intel_context *ce = &ctx->engine[engine->id]; |
1970 | ||
1971 | seq_printf(m, "%s: ", engine->name); | |
1972 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1973 | if (ce->state) | |
bf3783e5 | 1974 | describe_obj(m, ce->state->obj); |
dca33ecc | 1975 | if (ce->ring) |
7e37f889 | 1976 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1977 | seq_putc(m, '\n'); |
c9fe99bd | 1978 | } |
a33afea5 | 1979 | |
a33afea5 | 1980 | seq_putc(m, '\n'); |
a168c293 BW |
1981 | } |
1982 | ||
f3d28878 | 1983 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1984 | |
1985 | return 0; | |
1986 | } | |
1987 | ||
064ca1d2 | 1988 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1989 | struct i915_gem_context *ctx, |
0bc40be8 | 1990 | struct intel_engine_cs *engine) |
064ca1d2 | 1991 | { |
bf3783e5 | 1992 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1993 | struct page *page; |
064ca1d2 | 1994 | int j; |
064ca1d2 | 1995 | |
7069b144 CW |
1996 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1997 | ||
bf3783e5 CW |
1998 | if (!vma) { |
1999 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2000 | return; |
2001 | } | |
2002 | ||
bf3783e5 CW |
2003 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2004 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2005 | i915_ggtt_offset(vma)); |
064ca1d2 | 2006 | |
a4f5ea64 | 2007 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2008 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2009 | return; |
2010 | } | |
2011 | ||
bf3783e5 CW |
2012 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2013 | if (page) { | |
2014 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2015 | |
2016 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2017 | seq_printf(m, |
2018 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2019 | j * 4, | |
064ca1d2 TD |
2020 | reg_state[j], reg_state[j + 1], |
2021 | reg_state[j + 2], reg_state[j + 3]); | |
2022 | } | |
2023 | kunmap_atomic(reg_state); | |
2024 | } | |
2025 | ||
a4f5ea64 | 2026 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2027 | seq_putc(m, '\n'); |
2028 | } | |
2029 | ||
c0ab1ae9 BW |
2030 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2031 | { | |
36cdd013 DW |
2032 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2033 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2034 | struct intel_engine_cs *engine; |
e2efd130 | 2035 | struct i915_gem_context *ctx; |
3b3f1650 | 2036 | enum intel_engine_id id; |
b4ac5afc | 2037 | int ret; |
c0ab1ae9 BW |
2038 | |
2039 | if (!i915.enable_execlists) { | |
2040 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2041 | return 0; | |
2042 | } | |
2043 | ||
2044 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2045 | if (ret) | |
2046 | return ret; | |
2047 | ||
e28e404c | 2048 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2049 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2050 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2051 | |
2052 | mutex_unlock(&dev->struct_mutex); | |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
ea16a3cd DV |
2057 | static const char *swizzle_string(unsigned swizzle) |
2058 | { | |
aee56cff | 2059 | switch (swizzle) { |
ea16a3cd DV |
2060 | case I915_BIT_6_SWIZZLE_NONE: |
2061 | return "none"; | |
2062 | case I915_BIT_6_SWIZZLE_9: | |
2063 | return "bit9"; | |
2064 | case I915_BIT_6_SWIZZLE_9_10: | |
2065 | return "bit9/bit10"; | |
2066 | case I915_BIT_6_SWIZZLE_9_11: | |
2067 | return "bit9/bit11"; | |
2068 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2069 | return "bit9/bit10/bit11"; | |
2070 | case I915_BIT_6_SWIZZLE_9_17: | |
2071 | return "bit9/bit17"; | |
2072 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2073 | return "bit9/bit10/bit17"; | |
2074 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2075 | return "unknown"; |
ea16a3cd DV |
2076 | } |
2077 | ||
2078 | return "bug"; | |
2079 | } | |
2080 | ||
2081 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2082 | { | |
36cdd013 | 2083 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2084 | |
c8c8fb33 | 2085 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2086 | |
ea16a3cd DV |
2087 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2088 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2089 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2090 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2091 | ||
36cdd013 | 2092 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2093 | seq_printf(m, "DDC = 0x%08x\n", |
2094 | I915_READ(DCC)); | |
656bfa3a DV |
2095 | seq_printf(m, "DDC2 = 0x%08x\n", |
2096 | I915_READ(DCC2)); | |
ea16a3cd DV |
2097 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2098 | I915_READ16(C0DRB3)); | |
2099 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2100 | I915_READ16(C1DRB3)); | |
36cdd013 | 2101 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2102 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2103 | I915_READ(MAD_DIMM_C0)); | |
2104 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2105 | I915_READ(MAD_DIMM_C1)); | |
2106 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2107 | I915_READ(MAD_DIMM_C2)); | |
2108 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2109 | I915_READ(TILECTL)); | |
36cdd013 | 2110 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2111 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2112 | I915_READ(GAMTARBMODE)); | |
2113 | else | |
2114 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2115 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2116 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2117 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2118 | } |
656bfa3a DV |
2119 | |
2120 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2121 | seq_puts(m, "L-shaped memory detected\n"); | |
2122 | ||
c8c8fb33 | 2123 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2124 | |
2125 | return 0; | |
2126 | } | |
2127 | ||
1c60fef5 BW |
2128 | static int per_file_ctx(int id, void *ptr, void *data) |
2129 | { | |
e2efd130 | 2130 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2131 | struct seq_file *m = data; |
ae6c4806 DV |
2132 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2133 | ||
2134 | if (!ppgtt) { | |
2135 | seq_printf(m, " no ppgtt for context %d\n", | |
2136 | ctx->user_handle); | |
2137 | return 0; | |
2138 | } | |
1c60fef5 | 2139 | |
f83d6518 OM |
2140 | if (i915_gem_context_is_default(ctx)) |
2141 | seq_puts(m, " default context:\n"); | |
2142 | else | |
821d66dd | 2143 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2144 | ppgtt->debug_dump(ppgtt, m); |
2145 | ||
2146 | return 0; | |
2147 | } | |
2148 | ||
36cdd013 DW |
2149 | static void gen8_ppgtt_info(struct seq_file *m, |
2150 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2151 | { |
77df6772 | 2152 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2153 | struct intel_engine_cs *engine; |
2154 | enum intel_engine_id id; | |
b4ac5afc | 2155 | int i; |
3cf17fc5 | 2156 | |
77df6772 BW |
2157 | if (!ppgtt) |
2158 | return; | |
2159 | ||
3b3f1650 | 2160 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2161 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2162 | for (i = 0; i < 4; i++) { |
e2f80391 | 2163 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2164 | pdp <<= 32; |
e2f80391 | 2165 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2166 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2167 | } |
2168 | } | |
2169 | } | |
2170 | ||
36cdd013 DW |
2171 | static void gen6_ppgtt_info(struct seq_file *m, |
2172 | struct drm_i915_private *dev_priv) | |
77df6772 | 2173 | { |
e2f80391 | 2174 | struct intel_engine_cs *engine; |
3b3f1650 | 2175 | enum intel_engine_id id; |
3cf17fc5 | 2176 | |
7e22dbbb | 2177 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2178 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2179 | ||
3b3f1650 | 2180 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2181 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2182 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2183 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2184 | I915_READ(RING_MODE_GEN7(engine))); | |
2185 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2186 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2187 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2188 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2189 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2190 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2191 | } |
2192 | if (dev_priv->mm.aliasing_ppgtt) { | |
2193 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2194 | ||
267f0c90 | 2195 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2196 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2197 | |
87d60b63 | 2198 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2199 | } |
1c60fef5 | 2200 | |
3cf17fc5 | 2201 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2202 | } |
2203 | ||
2204 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2205 | { | |
36cdd013 DW |
2206 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2207 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2208 | struct drm_file *file; |
637ee29e | 2209 | int ret; |
77df6772 | 2210 | |
637ee29e CW |
2211 | mutex_lock(&dev->filelist_mutex); |
2212 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2213 | if (ret) |
637ee29e CW |
2214 | goto out_unlock; |
2215 | ||
c8c8fb33 | 2216 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2217 | |
36cdd013 DW |
2218 | if (INTEL_GEN(dev_priv) >= 8) |
2219 | gen8_ppgtt_info(m, dev_priv); | |
2220 | else if (INTEL_GEN(dev_priv) >= 6) | |
2221 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2222 | |
ea91e401 MT |
2223 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2224 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2225 | struct task_struct *task; |
ea91e401 | 2226 | |
7cb5dff8 | 2227 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2228 | if (!task) { |
2229 | ret = -ESRCH; | |
637ee29e | 2230 | goto out_rpm; |
06812760 | 2231 | } |
7cb5dff8 GT |
2232 | seq_printf(m, "\nproc: %s\n", task->comm); |
2233 | put_task_struct(task); | |
ea91e401 MT |
2234 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2235 | (void *)(unsigned long)m); | |
2236 | } | |
2237 | ||
637ee29e | 2238 | out_rpm: |
c8c8fb33 | 2239 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2240 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2241 | out_unlock: |
2242 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2243 | return ret; |
3cf17fc5 DV |
2244 | } |
2245 | ||
f5a4c67d CW |
2246 | static int count_irq_waiters(struct drm_i915_private *i915) |
2247 | { | |
e2f80391 | 2248 | struct intel_engine_cs *engine; |
3b3f1650 | 2249 | enum intel_engine_id id; |
f5a4c67d | 2250 | int count = 0; |
f5a4c67d | 2251 | |
3b3f1650 | 2252 | for_each_engine(engine, i915, id) |
688e6c72 | 2253 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2254 | |
2255 | return count; | |
2256 | } | |
2257 | ||
7466c291 CW |
2258 | static const char *rps_power_to_str(unsigned int power) |
2259 | { | |
2260 | static const char * const strings[] = { | |
2261 | [LOW_POWER] = "low power", | |
2262 | [BETWEEN] = "mixed", | |
2263 | [HIGH_POWER] = "high power", | |
2264 | }; | |
2265 | ||
2266 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2267 | return "unknown"; | |
2268 | ||
2269 | return strings[power]; | |
2270 | } | |
2271 | ||
1854d5ca CW |
2272 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2273 | { | |
36cdd013 DW |
2274 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2275 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2276 | struct drm_file *file; |
1854d5ca | 2277 | |
f5a4c67d | 2278 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2279 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2280 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2281 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2282 | seq_printf(m, "Frequency requested %d\n", |
2283 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2284 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2285 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2286 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2287 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2288 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2289 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2290 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2291 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2292 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2293 | |
2294 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2295 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2296 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2297 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2298 | struct task_struct *task; | |
2299 | ||
2300 | rcu_read_lock(); | |
2301 | task = pid_task(file->pid, PIDTYPE_PID); | |
2302 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2303 | task ? task->comm : "<unknown>", | |
2304 | task ? task->pid : -1, | |
2e1b8730 CW |
2305 | file_priv->rps.boosts, |
2306 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2307 | rcu_read_unlock(); |
2308 | } | |
197be2ae | 2309 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2310 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2311 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2312 | |
7466c291 CW |
2313 | if (INTEL_GEN(dev_priv) >= 6 && |
2314 | dev_priv->rps.enabled && | |
28176ef4 | 2315 | dev_priv->gt.active_requests) { |
7466c291 CW |
2316 | u32 rpup, rpupei; |
2317 | u32 rpdown, rpdownei; | |
2318 | ||
2319 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2320 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2321 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2322 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2323 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2324 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2325 | ||
2326 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2327 | rps_power_to_str(dev_priv->rps.power)); | |
2328 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2329 | 100 * rpup / rpupei, | |
2330 | dev_priv->rps.up_threshold); | |
2331 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2332 | 100 * rpdown / rpdownei, | |
2333 | dev_priv->rps.down_threshold); | |
2334 | } else { | |
2335 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2336 | } | |
2337 | ||
8d3afd7d | 2338 | return 0; |
1854d5ca CW |
2339 | } |
2340 | ||
63573eb7 BW |
2341 | static int i915_llc(struct seq_file *m, void *data) |
2342 | { | |
36cdd013 | 2343 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2344 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2345 | |
36cdd013 | 2346 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2347 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2348 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2349 | |
2350 | return 0; | |
2351 | } | |
2352 | ||
fdf5d357 AD |
2353 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2354 | { | |
36cdd013 | 2355 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2356 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2357 | u32 tmp, i; | |
2358 | ||
2d1fe073 | 2359 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2360 | return 0; |
2361 | ||
2362 | seq_printf(m, "GuC firmware status:\n"); | |
2363 | seq_printf(m, "\tpath: %s\n", | |
2364 | guc_fw->guc_fw_path); | |
2365 | seq_printf(m, "\tfetch: %s\n", | |
2366 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2367 | seq_printf(m, "\tload: %s\n", | |
2368 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2369 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2370 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2371 | seq_printf(m, "\tversion found: %d.%d\n", | |
2372 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2373 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2374 | guc_fw->header_offset, guc_fw->header_size); | |
2375 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2376 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2377 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2378 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2379 | |
2380 | tmp = I915_READ(GUC_STATUS); | |
2381 | ||
2382 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2383 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2384 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2385 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2386 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2387 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2388 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2389 | seq_puts(m, "\nScratch registers:\n"); | |
2390 | for (i = 0; i < 16; i++) | |
2391 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2392 | ||
2393 | return 0; | |
2394 | } | |
2395 | ||
5aa1ee4b AG |
2396 | static void i915_guc_log_info(struct seq_file *m, |
2397 | struct drm_i915_private *dev_priv) | |
2398 | { | |
2399 | struct intel_guc *guc = &dev_priv->guc; | |
2400 | ||
2401 | seq_puts(m, "\nGuC logging stats:\n"); | |
2402 | ||
2403 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2404 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2405 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2406 | ||
2407 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2408 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2409 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2410 | ||
2411 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2412 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2413 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2414 | ||
2415 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2416 | guc->log.flush_interrupt_count); | |
2417 | ||
2418 | seq_printf(m, "\tCapture miss count: %u\n", | |
2419 | guc->log.capture_miss_count); | |
2420 | } | |
2421 | ||
8b417c26 DG |
2422 | static void i915_guc_client_info(struct seq_file *m, |
2423 | struct drm_i915_private *dev_priv, | |
2424 | struct i915_guc_client *client) | |
2425 | { | |
e2f80391 | 2426 | struct intel_engine_cs *engine; |
c18468c4 | 2427 | enum intel_engine_id id; |
8b417c26 | 2428 | uint64_t tot = 0; |
8b417c26 DG |
2429 | |
2430 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2431 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2432 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2433 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2434 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2435 | client->wq_size, client->wq_offset, client->wq_tail); | |
2436 | ||
551aaecd | 2437 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2438 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2439 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2440 | ||
3b3f1650 | 2441 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2442 | u64 submissions = client->submissions[id]; |
2443 | tot += submissions; | |
8b417c26 | 2444 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2445 | submissions, engine->name); |
8b417c26 DG |
2446 | } |
2447 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2448 | } | |
2449 | ||
2450 | static int i915_guc_info(struct seq_file *m, void *data) | |
2451 | { | |
36cdd013 DW |
2452 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2453 | struct drm_device *dev = &dev_priv->drm; | |
8b417c26 | 2454 | struct intel_guc guc; |
0a0b457f | 2455 | struct i915_guc_client client = {}; |
e2f80391 | 2456 | struct intel_engine_cs *engine; |
c18468c4 | 2457 | enum intel_engine_id id; |
8b417c26 DG |
2458 | u64 total = 0; |
2459 | ||
2d1fe073 | 2460 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2461 | return 0; |
2462 | ||
5a843307 AD |
2463 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2464 | return 0; | |
2465 | ||
8b417c26 | 2466 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2467 | guc = dev_priv->guc; |
5a843307 | 2468 | if (guc.execbuf_client) |
8b417c26 | 2469 | client = *guc.execbuf_client; |
5a843307 AD |
2470 | |
2471 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2472 | |
9636f6db DG |
2473 | seq_printf(m, "Doorbell map:\n"); |
2474 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2475 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2476 | ||
8b417c26 DG |
2477 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2478 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2479 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2480 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2481 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2482 | ||
2483 | seq_printf(m, "\nGuC submissions:\n"); | |
3b3f1650 | 2484 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2485 | u64 submissions = guc.submissions[id]; |
2486 | total += submissions; | |
397097b0 | 2487 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2488 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2489 | } |
2490 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2491 | ||
2492 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2493 | i915_guc_client_info(m, dev_priv, &client); | |
2494 | ||
5aa1ee4b AG |
2495 | i915_guc_log_info(m, dev_priv); |
2496 | ||
8b417c26 DG |
2497 | /* Add more as required ... */ |
2498 | ||
2499 | return 0; | |
2500 | } | |
2501 | ||
4c7e77fc AD |
2502 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2503 | { | |
36cdd013 | 2504 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2505 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2506 | int i = 0, pg; |
2507 | ||
d6b40b4b | 2508 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2509 | return 0; |
2510 | ||
d6b40b4b | 2511 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2512 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2513 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2514 | |
2515 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2516 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2517 | *(log + i), *(log + i + 1), | |
2518 | *(log + i + 2), *(log + i + 3)); | |
2519 | ||
2520 | kunmap_atomic(log); | |
2521 | } | |
2522 | ||
2523 | seq_putc(m, '\n'); | |
2524 | ||
2525 | return 0; | |
2526 | } | |
2527 | ||
685534ef SAK |
2528 | static int i915_guc_log_control_get(void *data, u64 *val) |
2529 | { | |
2530 | struct drm_device *dev = data; | |
2531 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2532 | ||
2533 | if (!dev_priv->guc.log.vma) | |
2534 | return -EINVAL; | |
2535 | ||
2536 | *val = i915.guc_log_level; | |
2537 | ||
2538 | return 0; | |
2539 | } | |
2540 | ||
2541 | static int i915_guc_log_control_set(void *data, u64 val) | |
2542 | { | |
2543 | struct drm_device *dev = data; | |
2544 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2545 | int ret; | |
2546 | ||
2547 | if (!dev_priv->guc.log.vma) | |
2548 | return -EINVAL; | |
2549 | ||
2550 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2551 | if (ret) | |
2552 | return ret; | |
2553 | ||
2554 | intel_runtime_pm_get(dev_priv); | |
2555 | ret = i915_guc_log_control(dev_priv, val); | |
2556 | intel_runtime_pm_put(dev_priv); | |
2557 | ||
2558 | mutex_unlock(&dev->struct_mutex); | |
2559 | return ret; | |
2560 | } | |
2561 | ||
2562 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2563 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2564 | "%lld\n"); | |
2565 | ||
e91fd8c6 RV |
2566 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2567 | { | |
36cdd013 | 2568 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2569 | u32 psrperf = 0; |
a6cbdb8e RV |
2570 | u32 stat[3]; |
2571 | enum pipe pipe; | |
a031d709 | 2572 | bool enabled = false; |
e91fd8c6 | 2573 | |
36cdd013 | 2574 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2575 | seq_puts(m, "PSR not supported\n"); |
2576 | return 0; | |
2577 | } | |
2578 | ||
c8c8fb33 PZ |
2579 | intel_runtime_pm_get(dev_priv); |
2580 | ||
fa128fa6 | 2581 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2582 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2583 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2584 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2585 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2586 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2587 | dev_priv->psr.busy_frontbuffer_bits); | |
2588 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2589 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2590 | |
36cdd013 | 2591 | if (HAS_DDI(dev_priv)) |
443a389f | 2592 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2593 | else { |
2594 | for_each_pipe(dev_priv, pipe) { | |
9c870d03 CW |
2595 | enum transcoder cpu_transcoder = |
2596 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2597 | enum intel_display_power_domain power_domain; | |
2598 | ||
2599 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2600 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2601 | power_domain)) | |
2602 | continue; | |
2603 | ||
3553a8ea DL |
2604 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2605 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2606 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2607 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2608 | enabled = true; | |
9c870d03 CW |
2609 | |
2610 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2611 | } |
2612 | } | |
60e5ffe3 RV |
2613 | |
2614 | seq_printf(m, "Main link in standby mode: %s\n", | |
2615 | yesno(dev_priv->psr.link_standby)); | |
2616 | ||
a6cbdb8e RV |
2617 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2618 | ||
36cdd013 | 2619 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2620 | for_each_pipe(dev_priv, pipe) { |
2621 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2622 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2623 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2624 | } | |
2625 | seq_puts(m, "\n"); | |
e91fd8c6 | 2626 | |
05eec3c2 RV |
2627 | /* |
2628 | * VLV/CHV PSR has no kind of performance counter | |
2629 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2630 | */ | |
36cdd013 | 2631 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2632 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2633 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2634 | |
2635 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2636 | } | |
fa128fa6 | 2637 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2638 | |
c8c8fb33 | 2639 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2640 | return 0; |
2641 | } | |
2642 | ||
d2e216d0 RV |
2643 | static int i915_sink_crc(struct seq_file *m, void *data) |
2644 | { | |
36cdd013 DW |
2645 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2646 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2647 | struct intel_connector *connector; |
2648 | struct intel_dp *intel_dp = NULL; | |
2649 | int ret; | |
2650 | u8 crc[6]; | |
2651 | ||
2652 | drm_modeset_lock_all(dev); | |
aca5e361 | 2653 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2654 | struct drm_crtc *crtc; |
d2e216d0 | 2655 | |
26c17cf6 | 2656 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2657 | continue; |
2658 | ||
26c17cf6 ML |
2659 | crtc = connector->base.state->crtc; |
2660 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2661 | continue; |
2662 | ||
26c17cf6 | 2663 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2664 | continue; |
2665 | ||
26c17cf6 | 2666 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2667 | |
2668 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2669 | if (ret) | |
2670 | goto out; | |
2671 | ||
2672 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2673 | crc[0], crc[1], crc[2], | |
2674 | crc[3], crc[4], crc[5]); | |
2675 | goto out; | |
2676 | } | |
2677 | ret = -ENODEV; | |
2678 | out: | |
2679 | drm_modeset_unlock_all(dev); | |
2680 | return ret; | |
2681 | } | |
2682 | ||
ec013e7f JB |
2683 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2684 | { | |
36cdd013 | 2685 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2686 | u64 power; |
2687 | u32 units; | |
2688 | ||
36cdd013 | 2689 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2690 | return -ENODEV; |
2691 | ||
36623ef8 PZ |
2692 | intel_runtime_pm_get(dev_priv); |
2693 | ||
ec013e7f JB |
2694 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2695 | power = (power & 0x1f00) >> 8; | |
2696 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2697 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2698 | power *= units; | |
2699 | ||
36623ef8 PZ |
2700 | intel_runtime_pm_put(dev_priv); |
2701 | ||
ec013e7f | 2702 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2703 | |
2704 | return 0; | |
2705 | } | |
2706 | ||
6455c870 | 2707 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2708 | { |
36cdd013 | 2709 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2710 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2711 | |
a156e64d CW |
2712 | if (!HAS_RUNTIME_PM(dev_priv)) |
2713 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2714 | |
67d97da3 | 2715 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2716 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2717 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2718 | #ifdef CONFIG_PM |
a6aaec8b | 2719 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2720 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2721 | #else |
2722 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2723 | #endif | |
a156e64d | 2724 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2725 | pci_power_name(pdev->current_state), |
2726 | pdev->current_state); | |
371db66a | 2727 | |
ec013e7f JB |
2728 | return 0; |
2729 | } | |
2730 | ||
1da51581 ID |
2731 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2732 | { | |
36cdd013 | 2733 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2734 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2735 | int i; | |
2736 | ||
2737 | mutex_lock(&power_domains->lock); | |
2738 | ||
2739 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2740 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2741 | struct i915_power_well *power_well; | |
2742 | enum intel_display_power_domain power_domain; | |
2743 | ||
2744 | power_well = &power_domains->power_wells[i]; | |
2745 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2746 | power_well->count); | |
2747 | ||
2748 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2749 | power_domain++) { | |
2750 | if (!(BIT(power_domain) & power_well->domains)) | |
2751 | continue; | |
2752 | ||
2753 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2754 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2755 | power_domains->domain_use_count[power_domain]); |
2756 | } | |
2757 | } | |
2758 | ||
2759 | mutex_unlock(&power_domains->lock); | |
2760 | ||
2761 | return 0; | |
2762 | } | |
2763 | ||
b7cec66d DL |
2764 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2765 | { | |
36cdd013 | 2766 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2767 | struct intel_csr *csr; |
2768 | ||
36cdd013 | 2769 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2770 | seq_puts(m, "not supported\n"); |
2771 | return 0; | |
2772 | } | |
2773 | ||
2774 | csr = &dev_priv->csr; | |
2775 | ||
6fb403de MK |
2776 | intel_runtime_pm_get(dev_priv); |
2777 | ||
b7cec66d DL |
2778 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2779 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2780 | ||
2781 | if (!csr->dmc_payload) | |
6fb403de | 2782 | goto out; |
b7cec66d DL |
2783 | |
2784 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2785 | CSR_VERSION_MINOR(csr->version)); | |
2786 | ||
36cdd013 | 2787 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2788 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2789 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2790 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2791 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2792 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2793 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2794 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2795 | } |
2796 | ||
6fb403de MK |
2797 | out: |
2798 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2799 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2800 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2801 | ||
8337206d DL |
2802 | intel_runtime_pm_put(dev_priv); |
2803 | ||
b7cec66d DL |
2804 | return 0; |
2805 | } | |
2806 | ||
53f5e3ca JB |
2807 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2808 | struct drm_display_mode *mode) | |
2809 | { | |
2810 | int i; | |
2811 | ||
2812 | for (i = 0; i < tabs; i++) | |
2813 | seq_putc(m, '\t'); | |
2814 | ||
2815 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2816 | mode->base.id, mode->name, | |
2817 | mode->vrefresh, mode->clock, | |
2818 | mode->hdisplay, mode->hsync_start, | |
2819 | mode->hsync_end, mode->htotal, | |
2820 | mode->vdisplay, mode->vsync_start, | |
2821 | mode->vsync_end, mode->vtotal, | |
2822 | mode->type, mode->flags); | |
2823 | } | |
2824 | ||
2825 | static void intel_encoder_info(struct seq_file *m, | |
2826 | struct intel_crtc *intel_crtc, | |
2827 | struct intel_encoder *intel_encoder) | |
2828 | { | |
36cdd013 DW |
2829 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2830 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2831 | struct drm_crtc *crtc = &intel_crtc->base; |
2832 | struct intel_connector *intel_connector; | |
2833 | struct drm_encoder *encoder; | |
2834 | ||
2835 | encoder = &intel_encoder->base; | |
2836 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2837 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2838 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2839 | struct drm_connector *connector = &intel_connector->base; | |
2840 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2841 | connector->base.id, | |
c23cc417 | 2842 | connector->name, |
53f5e3ca JB |
2843 | drm_get_connector_status_name(connector->status)); |
2844 | if (connector->status == connector_status_connected) { | |
2845 | struct drm_display_mode *mode = &crtc->mode; | |
2846 | seq_printf(m, ", mode:\n"); | |
2847 | intel_seq_print_mode(m, 2, mode); | |
2848 | } else { | |
2849 | seq_putc(m, '\n'); | |
2850 | } | |
2851 | } | |
2852 | } | |
2853 | ||
2854 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2855 | { | |
36cdd013 DW |
2856 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2857 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2858 | struct drm_crtc *crtc = &intel_crtc->base; |
2859 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2860 | struct drm_plane_state *plane_state = crtc->primary->state; |
2861 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2862 | |
23a48d53 | 2863 | if (fb) |
5aa8a937 | 2864 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2865 | fb->base.id, plane_state->src_x >> 16, |
2866 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2867 | else |
2868 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2869 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2870 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2871 | } | |
2872 | ||
2873 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2874 | { | |
2875 | struct drm_display_mode *mode = panel->fixed_mode; | |
2876 | ||
2877 | seq_printf(m, "\tfixed mode:\n"); | |
2878 | intel_seq_print_mode(m, 2, mode); | |
2879 | } | |
2880 | ||
2881 | static void intel_dp_info(struct seq_file *m, | |
2882 | struct intel_connector *intel_connector) | |
2883 | { | |
2884 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2885 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2886 | ||
2887 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2888 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2889 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2890 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2891 | |
2892 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2893 | &intel_dp->aux); | |
53f5e3ca JB |
2894 | } |
2895 | ||
2896 | static void intel_hdmi_info(struct seq_file *m, | |
2897 | struct intel_connector *intel_connector) | |
2898 | { | |
2899 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2900 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2901 | ||
742f491d | 2902 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2903 | } |
2904 | ||
2905 | static void intel_lvds_info(struct seq_file *m, | |
2906 | struct intel_connector *intel_connector) | |
2907 | { | |
2908 | intel_panel_info(m, &intel_connector->panel); | |
2909 | } | |
2910 | ||
2911 | static void intel_connector_info(struct seq_file *m, | |
2912 | struct drm_connector *connector) | |
2913 | { | |
2914 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2915 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2916 | struct drm_display_mode *mode; |
53f5e3ca JB |
2917 | |
2918 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2919 | connector->base.id, connector->name, |
53f5e3ca JB |
2920 | drm_get_connector_status_name(connector->status)); |
2921 | if (connector->status == connector_status_connected) { | |
2922 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2923 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2924 | connector->display_info.width_mm, | |
2925 | connector->display_info.height_mm); | |
2926 | seq_printf(m, "\tsubpixel order: %s\n", | |
2927 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2928 | seq_printf(m, "\tCEA rev: %d\n", | |
2929 | connector->display_info.cea_rev); | |
2930 | } | |
ee648a74 ML |
2931 | |
2932 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2933 | return; | |
2934 | ||
2935 | switch (connector->connector_type) { | |
2936 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2937 | case DRM_MODE_CONNECTOR_eDP: | |
be754b10 | 2938 | intel_dp_info(m, intel_connector); |
ee648a74 ML |
2939 | break; |
2940 | case DRM_MODE_CONNECTOR_LVDS: | |
2941 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2942 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2943 | break; |
2944 | case DRM_MODE_CONNECTOR_HDMIA: | |
2945 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2946 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2947 | intel_hdmi_info(m, intel_connector); | |
2948 | break; | |
2949 | default: | |
2950 | break; | |
36cd7444 | 2951 | } |
53f5e3ca | 2952 | |
f103fc7d JB |
2953 | seq_printf(m, "\tmodes:\n"); |
2954 | list_for_each_entry(mode, &connector->modes, head) | |
2955 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2956 | } |
2957 | ||
36cdd013 | 2958 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2959 | { |
065f2ec2 CW |
2960 | u32 state; |
2961 | ||
36cdd013 | 2962 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 2963 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2964 | else |
5efb3e28 | 2965 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2966 | |
2967 | return state; | |
2968 | } | |
2969 | ||
36cdd013 DW |
2970 | static bool cursor_position(struct drm_i915_private *dev_priv, |
2971 | int pipe, int *x, int *y) | |
065f2ec2 | 2972 | { |
065f2ec2 CW |
2973 | u32 pos; |
2974 | ||
5efb3e28 | 2975 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2976 | |
2977 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2978 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2979 | *x = -*x; | |
2980 | ||
2981 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2982 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2983 | *y = -*y; | |
2984 | ||
36cdd013 | 2985 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
2986 | } |
2987 | ||
3abc4e09 RF |
2988 | static const char *plane_type(enum drm_plane_type type) |
2989 | { | |
2990 | switch (type) { | |
2991 | case DRM_PLANE_TYPE_OVERLAY: | |
2992 | return "OVL"; | |
2993 | case DRM_PLANE_TYPE_PRIMARY: | |
2994 | return "PRI"; | |
2995 | case DRM_PLANE_TYPE_CURSOR: | |
2996 | return "CUR"; | |
2997 | /* | |
2998 | * Deliberately omitting default: to generate compiler warnings | |
2999 | * when a new drm_plane_type gets added. | |
3000 | */ | |
3001 | } | |
3002 | ||
3003 | return "unknown"; | |
3004 | } | |
3005 | ||
3006 | static const char *plane_rotation(unsigned int rotation) | |
3007 | { | |
3008 | static char buf[48]; | |
3009 | /* | |
3010 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3011 | * will print them all to visualize if the values are misused | |
3012 | */ | |
3013 | snprintf(buf, sizeof(buf), | |
3014 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3015 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3016 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3017 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3018 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3019 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3020 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3021 | rotation); |
3022 | ||
3023 | return buf; | |
3024 | } | |
3025 | ||
3026 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3027 | { | |
36cdd013 DW |
3028 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3029 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3030 | struct intel_plane *intel_plane; |
3031 | ||
3032 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3033 | struct drm_plane_state *state; | |
3034 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3035 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3036 | |
3037 | if (!plane->state) { | |
3038 | seq_puts(m, "plane->state is NULL!\n"); | |
3039 | continue; | |
3040 | } | |
3041 | ||
3042 | state = plane->state; | |
3043 | ||
90844f00 | 3044 | if (state->fb) { |
b3c11ac2 | 3045 | drm_get_format_name(state->fb->pixel_format, &format_name); |
90844f00 | 3046 | } else { |
b3c11ac2 | 3047 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3048 | } |
3049 | ||
3abc4e09 RF |
3050 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3051 | plane->base.id, | |
3052 | plane_type(intel_plane->base.type), | |
3053 | state->crtc_x, state->crtc_y, | |
3054 | state->crtc_w, state->crtc_h, | |
3055 | (state->src_x >> 16), | |
3056 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3057 | (state->src_y >> 16), | |
3058 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3059 | (state->src_w >> 16), | |
3060 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3061 | (state->src_h >> 16), | |
3062 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3063 | format_name.str, |
3abc4e09 RF |
3064 | plane_rotation(state->rotation)); |
3065 | } | |
3066 | } | |
3067 | ||
3068 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3069 | { | |
3070 | struct intel_crtc_state *pipe_config; | |
3071 | int num_scalers = intel_crtc->num_scalers; | |
3072 | int i; | |
3073 | ||
3074 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3075 | ||
3076 | /* Not all platformas have a scaler */ | |
3077 | if (num_scalers) { | |
3078 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3079 | num_scalers, | |
3080 | pipe_config->scaler_state.scaler_users, | |
3081 | pipe_config->scaler_state.scaler_id); | |
3082 | ||
3083 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3084 | struct intel_scaler *sc = | |
3085 | &pipe_config->scaler_state.scalers[i]; | |
3086 | ||
3087 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3088 | i, yesno(sc->in_use), sc->mode); | |
3089 | } | |
3090 | seq_puts(m, "\n"); | |
3091 | } else { | |
3092 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3093 | } | |
3094 | } | |
3095 | ||
53f5e3ca JB |
3096 | static int i915_display_info(struct seq_file *m, void *unused) |
3097 | { | |
36cdd013 DW |
3098 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3099 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3100 | struct intel_crtc *crtc; |
53f5e3ca JB |
3101 | struct drm_connector *connector; |
3102 | ||
b0e5ddf3 | 3103 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3104 | drm_modeset_lock_all(dev); |
3105 | seq_printf(m, "CRTC info\n"); | |
3106 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3107 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3108 | bool active; |
f77076c9 | 3109 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3110 | int x, y; |
53f5e3ca | 3111 | |
f77076c9 ML |
3112 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3113 | ||
3abc4e09 | 3114 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3115 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3116 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3117 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3118 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3119 | ||
f77076c9 | 3120 | if (pipe_config->base.active) { |
065f2ec2 CW |
3121 | intel_crtc_info(m, crtc); |
3122 | ||
36cdd013 | 3123 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3124 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3125 | yesno(crtc->cursor_base), |
3dd512fb MR |
3126 | x, y, crtc->base.cursor->state->crtc_w, |
3127 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3128 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3129 | intel_scaler_info(m, crtc); |
3130 | intel_plane_info(m, crtc); | |
a23dc658 | 3131 | } |
cace841c DV |
3132 | |
3133 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3134 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3135 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3136 | } |
3137 | ||
3138 | seq_printf(m, "\n"); | |
3139 | seq_printf(m, "Connector info\n"); | |
3140 | seq_printf(m, "--------------\n"); | |
3141 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3142 | intel_connector_info(m, connector); | |
3143 | } | |
3144 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3145 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3146 | |
3147 | return 0; | |
3148 | } | |
3149 | ||
1b36595f CW |
3150 | static int i915_engine_info(struct seq_file *m, void *unused) |
3151 | { | |
3152 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3153 | struct intel_engine_cs *engine; | |
3b3f1650 | 3154 | enum intel_engine_id id; |
1b36595f | 3155 | |
9c870d03 CW |
3156 | intel_runtime_pm_get(dev_priv); |
3157 | ||
3b3f1650 | 3158 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3159 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3160 | struct drm_i915_gem_request *rq; | |
3161 | struct rb_node *rb; | |
3162 | u64 addr; | |
3163 | ||
3164 | seq_printf(m, "%s\n", engine->name); | |
3165 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n", | |
3166 | intel_engine_get_seqno(engine), | |
cb399eab | 3167 | intel_engine_last_submit(engine), |
1b36595f CW |
3168 | engine->hangcheck.seqno, |
3169 | engine->hangcheck.score); | |
3170 | ||
3171 | rcu_read_lock(); | |
3172 | ||
3173 | seq_printf(m, "\tRequests:\n"); | |
3174 | ||
73cb9701 CW |
3175 | rq = list_first_entry(&engine->timeline->requests, |
3176 | struct drm_i915_gem_request, link); | |
3177 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3178 | print_request(m, rq, "\t\tfirst "); |
3179 | ||
73cb9701 CW |
3180 | rq = list_last_entry(&engine->timeline->requests, |
3181 | struct drm_i915_gem_request, link); | |
3182 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3183 | print_request(m, rq, "\t\tlast "); |
3184 | ||
3185 | rq = i915_gem_find_active_request(engine); | |
3186 | if (rq) { | |
3187 | print_request(m, rq, "\t\tactive "); | |
3188 | seq_printf(m, | |
3189 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3190 | rq->head, rq->postfix, rq->tail, | |
3191 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3192 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3193 | } | |
3194 | ||
3195 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3196 | I915_READ(RING_START(engine->mmio_base)), | |
3197 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3198 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3199 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3200 | rq ? rq->ring->head : 0); | |
3201 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3202 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3203 | rq ? rq->ring->tail : 0); | |
3204 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3205 | I915_READ(RING_CTL(engine->mmio_base)), | |
3206 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3207 | ||
3208 | rcu_read_unlock(); | |
3209 | ||
3210 | addr = intel_engine_get_active_head(engine); | |
3211 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3212 | upper_32_bits(addr), lower_32_bits(addr)); | |
3213 | addr = intel_engine_get_last_batch_head(engine); | |
3214 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3215 | upper_32_bits(addr), lower_32_bits(addr)); | |
3216 | ||
3217 | if (i915.enable_execlists) { | |
3218 | u32 ptr, read, write; | |
20311bd3 | 3219 | struct rb_node *rb; |
1b36595f CW |
3220 | |
3221 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3222 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3223 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3224 | ||
3225 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3226 | read = GEN8_CSB_READ_PTR(ptr); | |
3227 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3228 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3229 | read, write); | |
3230 | if (read >= GEN8_CSB_ENTRIES) | |
3231 | read = 0; | |
3232 | if (write >= GEN8_CSB_ENTRIES) | |
3233 | write = 0; | |
3234 | if (read > write) | |
3235 | write += GEN8_CSB_ENTRIES; | |
3236 | while (read < write) { | |
3237 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3238 | ||
3239 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3240 | idx, | |
3241 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3242 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3243 | } | |
3244 | ||
3245 | rcu_read_lock(); | |
3246 | rq = READ_ONCE(engine->execlist_port[0].request); | |
3247 | if (rq) | |
3248 | print_request(m, rq, "\t\tELSP[0] "); | |
3249 | else | |
3250 | seq_printf(m, "\t\tELSP[0] idle\n"); | |
3251 | rq = READ_ONCE(engine->execlist_port[1].request); | |
3252 | if (rq) | |
3253 | print_request(m, rq, "\t\tELSP[1] "); | |
3254 | else | |
3255 | seq_printf(m, "\t\tELSP[1] idle\n"); | |
3256 | rcu_read_unlock(); | |
c8247c06 | 3257 | |
663f71e7 | 3258 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3259 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3260 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3261 | print_request(m, rq, "\t\tQ "); |
3262 | } | |
663f71e7 | 3263 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3264 | } else if (INTEL_GEN(dev_priv) > 6) { |
3265 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3266 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3267 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3268 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3269 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3270 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3271 | } | |
3272 | ||
f6168e33 | 3273 | spin_lock_irq(&b->lock); |
1b36595f CW |
3274 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
3275 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
3276 | ||
3277 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3278 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3279 | } | |
f6168e33 | 3280 | spin_unlock_irq(&b->lock); |
1b36595f CW |
3281 | |
3282 | seq_puts(m, "\n"); | |
3283 | } | |
3284 | ||
9c870d03 CW |
3285 | intel_runtime_pm_put(dev_priv); |
3286 | ||
1b36595f CW |
3287 | return 0; |
3288 | } | |
3289 | ||
e04934cf BW |
3290 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3291 | { | |
36cdd013 DW |
3292 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3293 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3294 | struct intel_engine_cs *engine; |
36cdd013 | 3295 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3296 | enum intel_engine_id id; |
3297 | int j, ret; | |
e04934cf | 3298 | |
39df9190 | 3299 | if (!i915.semaphores) { |
e04934cf BW |
3300 | seq_puts(m, "Semaphores are disabled\n"); |
3301 | return 0; | |
3302 | } | |
3303 | ||
3304 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3305 | if (ret) | |
3306 | return ret; | |
03872064 | 3307 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3308 | |
36cdd013 | 3309 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3310 | struct page *page; |
3311 | uint64_t *seqno; | |
3312 | ||
51d545d0 | 3313 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3314 | |
3315 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3316 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3317 | uint64_t offset; |
3318 | ||
e2f80391 | 3319 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3320 | |
3321 | seq_puts(m, " Last signal:"); | |
3322 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3323 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3324 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3325 | seqno[offset], offset * 8); | |
3326 | } | |
3327 | seq_putc(m, '\n'); | |
3328 | ||
3329 | seq_puts(m, " Last wait: "); | |
3330 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3331 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3332 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3333 | seqno[offset], offset * 8); | |
3334 | } | |
3335 | seq_putc(m, '\n'); | |
3336 | ||
3337 | } | |
3338 | kunmap_atomic(seqno); | |
3339 | } else { | |
3340 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3341 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3342 | for (j = 0; j < num_rings; j++) |
3343 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3344 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3345 | seq_putc(m, '\n'); |
3346 | } | |
3347 | ||
03872064 | 3348 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3349 | mutex_unlock(&dev->struct_mutex); |
3350 | return 0; | |
3351 | } | |
3352 | ||
728e29d7 DV |
3353 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3354 | { | |
36cdd013 DW |
3355 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3356 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3357 | int i; |
3358 | ||
3359 | drm_modeset_lock_all(dev); | |
3360 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3361 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3362 | ||
3363 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3364 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3365 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3366 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3367 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3368 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3369 | pll->config.hw_state.dpll_md); | |
3370 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3371 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3372 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3373 | } |
3374 | drm_modeset_unlock_all(dev); | |
3375 | ||
3376 | return 0; | |
3377 | } | |
3378 | ||
1ed1ef9d | 3379 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3380 | { |
3381 | int i; | |
3382 | int ret; | |
e2f80391 | 3383 | struct intel_engine_cs *engine; |
36cdd013 DW |
3384 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3385 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3386 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3387 | enum intel_engine_id id; |
888b5995 | 3388 | |
888b5995 AS |
3389 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3390 | if (ret) | |
3391 | return ret; | |
3392 | ||
3393 | intel_runtime_pm_get(dev_priv); | |
3394 | ||
33136b06 | 3395 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3396 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3397 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3398 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3399 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3400 | i915_reg_t addr; |
3401 | u32 mask, value, read; | |
2fa60f6d | 3402 | bool ok; |
888b5995 | 3403 | |
33136b06 AS |
3404 | addr = workarounds->reg[i].addr; |
3405 | mask = workarounds->reg[i].mask; | |
3406 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3407 | read = I915_READ(addr); |
3408 | ok = (value & mask) == (read & mask); | |
3409 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3410 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3411 | } |
3412 | ||
3413 | intel_runtime_pm_put(dev_priv); | |
3414 | mutex_unlock(&dev->struct_mutex); | |
3415 | ||
3416 | return 0; | |
3417 | } | |
3418 | ||
c5511e44 DL |
3419 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3420 | { | |
36cdd013 DW |
3421 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3422 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3423 | struct skl_ddb_allocation *ddb; |
3424 | struct skl_ddb_entry *entry; | |
3425 | enum pipe pipe; | |
3426 | int plane; | |
3427 | ||
36cdd013 | 3428 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3429 | return 0; |
3430 | ||
c5511e44 DL |
3431 | drm_modeset_lock_all(dev); |
3432 | ||
3433 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3434 | ||
3435 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3436 | ||
3437 | for_each_pipe(dev_priv, pipe) { | |
3438 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3439 | ||
8b364b41 | 3440 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3441 | entry = &ddb->plane[pipe][plane]; |
3442 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3443 | entry->start, entry->end, | |
3444 | skl_ddb_entry_size(entry)); | |
3445 | } | |
3446 | ||
4969d33e | 3447 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3448 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3449 | entry->end, skl_ddb_entry_size(entry)); | |
3450 | } | |
3451 | ||
3452 | drm_modeset_unlock_all(dev); | |
3453 | ||
3454 | return 0; | |
3455 | } | |
3456 | ||
a54746e3 | 3457 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3458 | struct drm_device *dev, |
3459 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3460 | { |
fac5e23e | 3461 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3462 | struct i915_drrs *drrs = &dev_priv->drrs; |
3463 | int vrefresh = 0; | |
26875fe5 | 3464 | struct drm_connector *connector; |
a54746e3 | 3465 | |
26875fe5 ML |
3466 | drm_for_each_connector(connector, dev) { |
3467 | if (connector->state->crtc != &intel_crtc->base) | |
3468 | continue; | |
3469 | ||
3470 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3471 | } |
3472 | ||
3473 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3474 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3475 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3476 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3477 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3478 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3479 | else | |
3480 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3481 | ||
3482 | seq_puts(m, "\n\n"); | |
3483 | ||
f77076c9 | 3484 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3485 | struct intel_panel *panel; |
3486 | ||
3487 | mutex_lock(&drrs->mutex); | |
3488 | /* DRRS Supported */ | |
3489 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3490 | ||
3491 | /* disable_drrs() will make drrs->dp NULL */ | |
3492 | if (!drrs->dp) { | |
3493 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3494 | mutex_unlock(&drrs->mutex); | |
3495 | return; | |
3496 | } | |
3497 | ||
3498 | panel = &drrs->dp->attached_connector->panel; | |
3499 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3500 | drrs->busy_frontbuffer_bits); | |
3501 | ||
3502 | seq_puts(m, "\n\t\t"); | |
3503 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3504 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3505 | vrefresh = panel->fixed_mode->vrefresh; | |
3506 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3507 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3508 | vrefresh = panel->downclock_mode->vrefresh; | |
3509 | } else { | |
3510 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3511 | drrs->refresh_rate_type); | |
3512 | mutex_unlock(&drrs->mutex); | |
3513 | return; | |
3514 | } | |
3515 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3516 | ||
3517 | seq_puts(m, "\n\t\t"); | |
3518 | mutex_unlock(&drrs->mutex); | |
3519 | } else { | |
3520 | /* DRRS not supported. Print the VBT parameter*/ | |
3521 | seq_puts(m, "\tDRRS Supported : No"); | |
3522 | } | |
3523 | seq_puts(m, "\n"); | |
3524 | } | |
3525 | ||
3526 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3527 | { | |
36cdd013 DW |
3528 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3529 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3530 | struct intel_crtc *intel_crtc; |
3531 | int active_crtc_cnt = 0; | |
3532 | ||
26875fe5 | 3533 | drm_modeset_lock_all(dev); |
a54746e3 | 3534 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3535 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3536 | active_crtc_cnt++; |
3537 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3538 | ||
3539 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3540 | } | |
a54746e3 | 3541 | } |
26875fe5 | 3542 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3543 | |
3544 | if (!active_crtc_cnt) | |
3545 | seq_puts(m, "No active crtc found\n"); | |
3546 | ||
3547 | return 0; | |
3548 | } | |
3549 | ||
07144428 DL |
3550 | struct pipe_crc_info { |
3551 | const char *name; | |
36cdd013 | 3552 | struct drm_i915_private *dev_priv; |
07144428 DL |
3553 | enum pipe pipe; |
3554 | }; | |
3555 | ||
11bed958 DA |
3556 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3557 | { | |
36cdd013 DW |
3558 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3559 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3560 | struct intel_encoder *intel_encoder; |
3561 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3562 | struct drm_connector *connector; |
3563 | ||
11bed958 | 3564 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3565 | drm_for_each_connector(connector, dev) { |
3566 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3567 | continue; |
b6dabe3b ML |
3568 | |
3569 | intel_encoder = intel_attached_encoder(connector); | |
3570 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3571 | continue; | |
3572 | ||
3573 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3574 | if (!intel_dig_port->dp.can_mst) |
3575 | continue; | |
b6dabe3b | 3576 | |
40ae80cc JB |
3577 | seq_printf(m, "MST Source Port %c\n", |
3578 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3579 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3580 | } | |
3581 | drm_modeset_unlock_all(dev); | |
3582 | return 0; | |
3583 | } | |
3584 | ||
07144428 DL |
3585 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3586 | { | |
be5c7a90 | 3587 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3588 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3589 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3590 | ||
36cdd013 | 3591 | if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) |
7eb1c496 DV |
3592 | return -ENODEV; |
3593 | ||
d538bbdf DL |
3594 | spin_lock_irq(&pipe_crc->lock); |
3595 | ||
3596 | if (pipe_crc->opened) { | |
3597 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3598 | return -EBUSY; /* already open */ |
3599 | } | |
3600 | ||
d538bbdf | 3601 | pipe_crc->opened = true; |
07144428 DL |
3602 | filep->private_data = inode->i_private; |
3603 | ||
d538bbdf DL |
3604 | spin_unlock_irq(&pipe_crc->lock); |
3605 | ||
07144428 DL |
3606 | return 0; |
3607 | } | |
3608 | ||
3609 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3610 | { | |
be5c7a90 | 3611 | struct pipe_crc_info *info = inode->i_private; |
36cdd013 | 3612 | struct drm_i915_private *dev_priv = info->dev_priv; |
be5c7a90 DL |
3613 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3614 | ||
d538bbdf DL |
3615 | spin_lock_irq(&pipe_crc->lock); |
3616 | pipe_crc->opened = false; | |
3617 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3618 | |
07144428 DL |
3619 | return 0; |
3620 | } | |
3621 | ||
3622 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3623 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3624 | /* account for \'0' */ | |
3625 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3626 | ||
3627 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3628 | { |
d538bbdf DL |
3629 | assert_spin_locked(&pipe_crc->lock); |
3630 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3631 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3632 | } |
3633 | ||
3634 | static ssize_t | |
3635 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3636 | loff_t *pos) | |
3637 | { | |
3638 | struct pipe_crc_info *info = filep->private_data; | |
36cdd013 | 3639 | struct drm_i915_private *dev_priv = info->dev_priv; |
07144428 DL |
3640 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3641 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3642 | int n_entries; |
07144428 DL |
3643 | ssize_t bytes_read; |
3644 | ||
3645 | /* | |
3646 | * Don't allow user space to provide buffers not big enough to hold | |
3647 | * a line of data. | |
3648 | */ | |
3649 | if (count < PIPE_CRC_LINE_LEN) | |
3650 | return -EINVAL; | |
3651 | ||
3652 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3653 | return 0; |
07144428 DL |
3654 | |
3655 | /* nothing to read */ | |
d538bbdf | 3656 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3657 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3658 | int ret; |
3659 | ||
3660 | if (filep->f_flags & O_NONBLOCK) { | |
3661 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3662 | return -EAGAIN; |
d538bbdf | 3663 | } |
07144428 | 3664 | |
d538bbdf DL |
3665 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3666 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3667 | if (ret) { | |
3668 | spin_unlock_irq(&pipe_crc->lock); | |
3669 | return ret; | |
3670 | } | |
8bf1e9f1 SH |
3671 | } |
3672 | ||
07144428 | 3673 | /* We now have one or more entries to read */ |
9ad6d99f | 3674 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3675 | |
07144428 | 3676 | bytes_read = 0; |
9ad6d99f VS |
3677 | while (n_entries > 0) { |
3678 | struct intel_pipe_crc_entry *entry = | |
3679 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3680 | |
9ad6d99f VS |
3681 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3682 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3683 | break; | |
3684 | ||
3685 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3686 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3687 | ||
07144428 DL |
3688 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3689 | "%8u %8x %8x %8x %8x %8x\n", | |
3690 | entry->frame, entry->crc[0], | |
3691 | entry->crc[1], entry->crc[2], | |
3692 | entry->crc[3], entry->crc[4]); | |
3693 | ||
9ad6d99f VS |
3694 | spin_unlock_irq(&pipe_crc->lock); |
3695 | ||
4e9121e6 | 3696 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3697 | return -EFAULT; |
b2c88f5b | 3698 | |
9ad6d99f VS |
3699 | user_buf += PIPE_CRC_LINE_LEN; |
3700 | n_entries--; | |
3701 | ||
3702 | spin_lock_irq(&pipe_crc->lock); | |
3703 | } | |
8bf1e9f1 | 3704 | |
d538bbdf DL |
3705 | spin_unlock_irq(&pipe_crc->lock); |
3706 | ||
07144428 DL |
3707 | return bytes_read; |
3708 | } | |
3709 | ||
3710 | static const struct file_operations i915_pipe_crc_fops = { | |
3711 | .owner = THIS_MODULE, | |
3712 | .open = i915_pipe_crc_open, | |
3713 | .read = i915_pipe_crc_read, | |
3714 | .release = i915_pipe_crc_release, | |
3715 | }; | |
3716 | ||
3717 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3718 | { | |
3719 | .name = "i915_pipe_A_crc", | |
3720 | .pipe = PIPE_A, | |
3721 | }, | |
3722 | { | |
3723 | .name = "i915_pipe_B_crc", | |
3724 | .pipe = PIPE_B, | |
3725 | }, | |
3726 | { | |
3727 | .name = "i915_pipe_C_crc", | |
3728 | .pipe = PIPE_C, | |
3729 | }, | |
3730 | }; | |
3731 | ||
3732 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3733 | enum pipe pipe) | |
3734 | { | |
36cdd013 | 3735 | struct drm_i915_private *dev_priv = to_i915(minor->dev); |
07144428 DL |
3736 | struct dentry *ent; |
3737 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3738 | ||
36cdd013 | 3739 | info->dev_priv = dev_priv; |
07144428 DL |
3740 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
3741 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3742 | if (!ent) |
3743 | return -ENOMEM; | |
07144428 DL |
3744 | |
3745 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3746 | } |
3747 | ||
e8dfcf78 | 3748 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3749 | "none", |
3750 | "plane1", | |
3751 | "plane2", | |
3752 | "pf", | |
5b3a856b | 3753 | "pipe", |
3d099a05 DV |
3754 | "TV", |
3755 | "DP-B", | |
3756 | "DP-C", | |
3757 | "DP-D", | |
46a19188 | 3758 | "auto", |
926321d5 DV |
3759 | }; |
3760 | ||
3761 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3762 | { | |
3763 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3764 | return pipe_crc_sources[source]; | |
3765 | } | |
3766 | ||
bd9db02f | 3767 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 | 3768 | { |
36cdd013 | 3769 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
3770 | int i; |
3771 | ||
3772 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3773 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3774 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3775 | ||
3776 | return 0; | |
3777 | } | |
3778 | ||
bd9db02f | 3779 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 | 3780 | { |
36cdd013 | 3781 | return single_open(file, display_crc_ctl_show, inode->i_private); |
926321d5 DV |
3782 | } |
3783 | ||
46a19188 | 3784 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3785 | uint32_t *val) |
3786 | { | |
46a19188 DV |
3787 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3788 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3789 | ||
3790 | switch (*source) { | |
52f843f6 DV |
3791 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3792 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3793 | break; | |
3794 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3795 | *val = 0; | |
3796 | break; | |
3797 | default: | |
3798 | return -EINVAL; | |
3799 | } | |
3800 | ||
3801 | return 0; | |
3802 | } | |
3803 | ||
36cdd013 DW |
3804 | static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, |
3805 | enum pipe pipe, | |
46a19188 DV |
3806 | enum intel_pipe_crc_source *source) |
3807 | { | |
36cdd013 | 3808 | struct drm_device *dev = &dev_priv->drm; |
46a19188 DV |
3809 | struct intel_encoder *encoder; |
3810 | struct intel_crtc *crtc; | |
26756809 | 3811 | struct intel_digital_port *dig_port; |
46a19188 DV |
3812 | int ret = 0; |
3813 | ||
3814 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3815 | ||
6e9f798d | 3816 | drm_modeset_lock_all(dev); |
b2784e15 | 3817 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3818 | if (!encoder->base.crtc) |
3819 | continue; | |
3820 | ||
3821 | crtc = to_intel_crtc(encoder->base.crtc); | |
3822 | ||
3823 | if (crtc->pipe != pipe) | |
3824 | continue; | |
3825 | ||
3826 | switch (encoder->type) { | |
3827 | case INTEL_OUTPUT_TVOUT: | |
3828 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3829 | break; | |
cca0502b | 3830 | case INTEL_OUTPUT_DP: |
46a19188 | 3831 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3832 | dig_port = enc_to_dig_port(&encoder->base); |
3833 | switch (dig_port->port) { | |
3834 | case PORT_B: | |
3835 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3836 | break; | |
3837 | case PORT_C: | |
3838 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3839 | break; | |
3840 | case PORT_D: | |
3841 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3842 | break; | |
3843 | default: | |
3844 | WARN(1, "nonexisting DP port %c\n", | |
3845 | port_name(dig_port->port)); | |
3846 | break; | |
3847 | } | |
46a19188 | 3848 | break; |
6847d71b PZ |
3849 | default: |
3850 | break; | |
46a19188 DV |
3851 | } |
3852 | } | |
6e9f798d | 3853 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3854 | |
3855 | return ret; | |
3856 | } | |
3857 | ||
36cdd013 | 3858 | static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3859 | enum pipe pipe, |
3860 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3861 | uint32_t *val) |
3862 | { | |
8d2f24ca DV |
3863 | bool need_stable_symbols = false; |
3864 | ||
46a19188 | 3865 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3866 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3867 | if (ret) |
3868 | return ret; | |
3869 | } | |
3870 | ||
3871 | switch (*source) { | |
7ac0129b DV |
3872 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3873 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3874 | break; | |
3875 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3876 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3877 | need_stable_symbols = true; |
7ac0129b DV |
3878 | break; |
3879 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3880 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3881 | need_stable_symbols = true; |
7ac0129b | 3882 | break; |
2be57922 | 3883 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
36cdd013 | 3884 | if (!IS_CHERRYVIEW(dev_priv)) |
2be57922 VS |
3885 | return -EINVAL; |
3886 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3887 | need_stable_symbols = true; | |
3888 | break; | |
7ac0129b DV |
3889 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3890 | *val = 0; | |
3891 | break; | |
3892 | default: | |
3893 | return -EINVAL; | |
3894 | } | |
3895 | ||
8d2f24ca DV |
3896 | /* |
3897 | * When the pipe CRC tap point is after the transcoders we need | |
3898 | * to tweak symbol-level features to produce a deterministic series of | |
3899 | * symbols for a given frame. We need to reset those features only once | |
3900 | * a frame (instead of every nth symbol): | |
3901 | * - DC-balance: used to ensure a better clock recovery from the data | |
3902 | * link (SDVO) | |
3903 | * - DisplayPort scrambling: used for EMI reduction | |
3904 | */ | |
3905 | if (need_stable_symbols) { | |
3906 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3907 | ||
8d2f24ca | 3908 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3909 | switch (pipe) { |
3910 | case PIPE_A: | |
8d2f24ca | 3911 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3912 | break; |
3913 | case PIPE_B: | |
8d2f24ca | 3914 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3915 | break; |
3916 | case PIPE_C: | |
3917 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3918 | break; | |
3919 | default: | |
3920 | return -EINVAL; | |
3921 | } | |
8d2f24ca DV |
3922 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3923 | } | |
3924 | ||
7ac0129b DV |
3925 | return 0; |
3926 | } | |
3927 | ||
36cdd013 | 3928 | static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
46a19188 DV |
3929 | enum pipe pipe, |
3930 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3931 | uint32_t *val) |
3932 | { | |
84093603 DV |
3933 | bool need_stable_symbols = false; |
3934 | ||
46a19188 | 3935 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
36cdd013 | 3936 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); |
46a19188 DV |
3937 | if (ret) |
3938 | return ret; | |
3939 | } | |
3940 | ||
3941 | switch (*source) { | |
4b79ebf7 DV |
3942 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3943 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3944 | break; | |
3945 | case INTEL_PIPE_CRC_SOURCE_TV: | |
36cdd013 | 3946 | if (!SUPPORTS_TV(dev_priv)) |
4b79ebf7 DV |
3947 | return -EINVAL; |
3948 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3949 | break; | |
3950 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
36cdd013 | 3951 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3952 | return -EINVAL; |
3953 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3954 | need_stable_symbols = true; |
4b79ebf7 DV |
3955 | break; |
3956 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
36cdd013 | 3957 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3958 | return -EINVAL; |
3959 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3960 | need_stable_symbols = true; |
4b79ebf7 DV |
3961 | break; |
3962 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
36cdd013 | 3963 | if (!IS_G4X(dev_priv)) |
4b79ebf7 DV |
3964 | return -EINVAL; |
3965 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3966 | need_stable_symbols = true; |
4b79ebf7 DV |
3967 | break; |
3968 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3969 | *val = 0; | |
3970 | break; | |
3971 | default: | |
3972 | return -EINVAL; | |
3973 | } | |
3974 | ||
84093603 DV |
3975 | /* |
3976 | * When the pipe CRC tap point is after the transcoders we need | |
3977 | * to tweak symbol-level features to produce a deterministic series of | |
3978 | * symbols for a given frame. We need to reset those features only once | |
3979 | * a frame (instead of every nth symbol): | |
3980 | * - DC-balance: used to ensure a better clock recovery from the data | |
3981 | * link (SDVO) | |
3982 | * - DisplayPort scrambling: used for EMI reduction | |
3983 | */ | |
3984 | if (need_stable_symbols) { | |
3985 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3986 | ||
36cdd013 | 3987 | WARN_ON(!IS_G4X(dev_priv)); |
84093603 DV |
3988 | |
3989 | I915_WRITE(PORT_DFT_I9XX, | |
3990 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3991 | ||
3992 | if (pipe == PIPE_A) | |
3993 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3994 | else | |
3995 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3996 | ||
3997 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3998 | } | |
3999 | ||
4b79ebf7 DV |
4000 | return 0; |
4001 | } | |
4002 | ||
36cdd013 | 4003 | static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
8d2f24ca DV |
4004 | enum pipe pipe) |
4005 | { | |
8d2f24ca DV |
4006 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
4007 | ||
eb736679 VS |
4008 | switch (pipe) { |
4009 | case PIPE_A: | |
8d2f24ca | 4010 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
4011 | break; |
4012 | case PIPE_B: | |
8d2f24ca | 4013 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
4014 | break; |
4015 | case PIPE_C: | |
4016 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
4017 | break; | |
4018 | default: | |
4019 | return; | |
4020 | } | |
8d2f24ca DV |
4021 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
4022 | tmp &= ~DC_BALANCE_RESET_VLV; | |
4023 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
4024 | ||
4025 | } | |
4026 | ||
36cdd013 | 4027 | static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, |
84093603 DV |
4028 | enum pipe pipe) |
4029 | { | |
84093603 DV |
4030 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
4031 | ||
4032 | if (pipe == PIPE_A) | |
4033 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
4034 | else | |
4035 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
4036 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
4037 | ||
4038 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
4039 | I915_WRITE(PORT_DFT_I9XX, | |
4040 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
4041 | } | |
4042 | } | |
4043 | ||
46a19188 | 4044 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
4045 | uint32_t *val) |
4046 | { | |
46a19188 DV |
4047 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4048 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
4049 | ||
4050 | switch (*source) { | |
5b3a856b DV |
4051 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4052 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
4053 | break; | |
4054 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4055 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
4056 | break; | |
5b3a856b DV |
4057 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
4058 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
4059 | break; | |
3d099a05 | 4060 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4061 | *val = 0; |
4062 | break; | |
3d099a05 DV |
4063 | default: |
4064 | return -EINVAL; | |
5b3a856b DV |
4065 | } |
4066 | ||
4067 | return 0; | |
4068 | } | |
4069 | ||
36cdd013 DW |
4070 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, |
4071 | bool enable) | |
fabf6e51 | 4072 | { |
36cdd013 | 4073 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 4074 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); |
f77076c9 | 4075 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
4076 | struct drm_atomic_state *state; |
4077 | int ret = 0; | |
fabf6e51 DV |
4078 | |
4079 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
4080 | state = drm_atomic_state_alloc(dev); |
4081 | if (!state) { | |
4082 | ret = -ENOMEM; | |
4083 | goto out; | |
fabf6e51 | 4084 | } |
fabf6e51 | 4085 | |
c4e2d043 ML |
4086 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
4087 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
4088 | if (IS_ERR(pipe_config)) { | |
4089 | ret = PTR_ERR(pipe_config); | |
4090 | goto out; | |
4091 | } | |
fabf6e51 | 4092 | |
c4e2d043 ML |
4093 | pipe_config->pch_pfit.force_thru = enable; |
4094 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4095 | pipe_config->pch_pfit.enabled != enable) | |
4096 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4097 | |
c4e2d043 ML |
4098 | ret = drm_atomic_commit(state); |
4099 | out: | |
c4e2d043 | 4100 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
0853695c CW |
4101 | drm_modeset_unlock_all(dev); |
4102 | drm_atomic_state_put(state); | |
fabf6e51 DV |
4103 | } |
4104 | ||
36cdd013 | 4105 | static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, |
fabf6e51 DV |
4106 | enum pipe pipe, |
4107 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4108 | uint32_t *val) |
4109 | { | |
46a19188 DV |
4110 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4111 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4112 | ||
4113 | switch (*source) { | |
5b3a856b DV |
4114 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4115 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4116 | break; | |
4117 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4118 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4119 | break; | |
4120 | case INTEL_PIPE_CRC_SOURCE_PF: | |
36cdd013 DW |
4121 | if (IS_HASWELL(dev_priv) && pipe == PIPE_A) |
4122 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); | |
fabf6e51 | 4123 | |
5b3a856b DV |
4124 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4125 | break; | |
3d099a05 | 4126 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4127 | *val = 0; |
4128 | break; | |
3d099a05 DV |
4129 | default: |
4130 | return -EINVAL; | |
5b3a856b DV |
4131 | } |
4132 | ||
4133 | return 0; | |
4134 | } | |
4135 | ||
36cdd013 DW |
4136 | static int pipe_crc_set_source(struct drm_i915_private *dev_priv, |
4137 | enum pipe pipe, | |
926321d5 DV |
4138 | enum intel_pipe_crc_source source) |
4139 | { | |
cc3da175 | 4140 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
b91eb5cc | 4141 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e129649b | 4142 | enum intel_display_power_domain power_domain; |
432f3342 | 4143 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4144 | int ret; |
926321d5 | 4145 | |
cc3da175 DL |
4146 | if (pipe_crc->source == source) |
4147 | return 0; | |
4148 | ||
ae676fcd DL |
4149 | /* forbid changing the source without going back to 'none' */ |
4150 | if (pipe_crc->source && source) | |
4151 | return -EINVAL; | |
4152 | ||
e129649b ID |
4153 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4154 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4155 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4156 | return -EIO; | |
4157 | } | |
4158 | ||
36cdd013 | 4159 | if (IS_GEN2(dev_priv)) |
46a19188 | 4160 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
36cdd013 DW |
4161 | else if (INTEL_GEN(dev_priv) < 5) |
4162 | ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4163 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4164 | ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); | |
4165 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) | |
46a19188 | 4166 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4167 | else |
36cdd013 | 4168 | ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); |
5b3a856b DV |
4169 | |
4170 | if (ret != 0) | |
e129649b | 4171 | goto out; |
5b3a856b | 4172 | |
4b584369 DL |
4173 | /* none -> real source transition */ |
4174 | if (source) { | |
4252fbc3 VS |
4175 | struct intel_pipe_crc_entry *entries; |
4176 | ||
7cd6ccff DL |
4177 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4178 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4179 | ||
3cf54b34 VS |
4180 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4181 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4182 | GFP_KERNEL); |
e129649b ID |
4183 | if (!entries) { |
4184 | ret = -ENOMEM; | |
4185 | goto out; | |
4186 | } | |
e5f75aca | 4187 | |
8c740dce PZ |
4188 | /* |
4189 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4190 | * enabled and disabled dynamically based on package C states, | |
4191 | * user space can't make reliable use of the CRCs, so let's just | |
4192 | * completely disable it. | |
4193 | */ | |
4194 | hsw_disable_ips(crtc); | |
4195 | ||
d538bbdf | 4196 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4197 | kfree(pipe_crc->entries); |
4252fbc3 | 4198 | pipe_crc->entries = entries; |
d538bbdf DL |
4199 | pipe_crc->head = 0; |
4200 | pipe_crc->tail = 0; | |
4201 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4202 | } |
4203 | ||
cc3da175 | 4204 | pipe_crc->source = source; |
926321d5 | 4205 | |
926321d5 DV |
4206 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4207 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4208 | ||
e5f75aca DL |
4209 | /* real source -> none transition */ |
4210 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4211 | struct intel_pipe_crc_entry *entries; |
98187836 VS |
4212 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
4213 | pipe); | |
d538bbdf | 4214 | |
7cd6ccff DL |
4215 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4216 | pipe_name(pipe)); | |
4217 | ||
a33d7105 | 4218 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4219 | if (crtc->base.state->active) |
0f0f74bc | 4220 | intel_wait_for_vblank(dev_priv, pipe); |
a33d7105 | 4221 | drm_modeset_unlock(&crtc->base.mutex); |
bcf17ab2 | 4222 | |
d538bbdf DL |
4223 | spin_lock_irq(&pipe_crc->lock); |
4224 | entries = pipe_crc->entries; | |
e5f75aca | 4225 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4226 | pipe_crc->head = 0; |
4227 | pipe_crc->tail = 0; | |
d538bbdf DL |
4228 | spin_unlock_irq(&pipe_crc->lock); |
4229 | ||
4230 | kfree(entries); | |
84093603 | 4231 | |
36cdd013 DW |
4232 | if (IS_G4X(dev_priv)) |
4233 | g4x_undo_pipe_scramble_reset(dev_priv, pipe); | |
4234 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4235 | vlv_undo_pipe_scramble_reset(dev_priv, pipe); | |
4236 | else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
4237 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
8c740dce PZ |
4238 | |
4239 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4240 | } |
4241 | ||
e129649b ID |
4242 | ret = 0; |
4243 | ||
4244 | out: | |
4245 | intel_display_power_put(dev_priv, power_domain); | |
4246 | ||
4247 | return ret; | |
926321d5 DV |
4248 | } |
4249 | ||
4250 | /* | |
4251 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4252 | * command: wsp* object wsp+ name wsp+ source wsp* |
4253 | * object: 'pipe' | |
4254 | * name: (A | B | C) | |
926321d5 DV |
4255 | * source: (none | plane1 | plane2 | pf) |
4256 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4257 | * | |
4258 | * eg.: | |
b94dec87 DL |
4259 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4260 | * "pipe A none" -> Stop CRC | |
926321d5 | 4261 | */ |
bd9db02f | 4262 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4263 | { |
4264 | int n_words = 0; | |
4265 | ||
4266 | while (*buf) { | |
4267 | char *end; | |
4268 | ||
4269 | /* skip leading white space */ | |
4270 | buf = skip_spaces(buf); | |
4271 | if (!*buf) | |
4272 | break; /* end of buffer */ | |
4273 | ||
4274 | /* find end of word */ | |
4275 | for (end = buf; *end && !isspace(*end); end++) | |
4276 | ; | |
4277 | ||
4278 | if (n_words == max_words) { | |
4279 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4280 | max_words); | |
4281 | return -EINVAL; /* ran out of words[] before bytes */ | |
4282 | } | |
4283 | ||
4284 | if (*end) | |
4285 | *end++ = '\0'; | |
4286 | words[n_words++] = buf; | |
4287 | buf = end; | |
4288 | } | |
4289 | ||
4290 | return n_words; | |
4291 | } | |
4292 | ||
b94dec87 DL |
4293 | enum intel_pipe_crc_object { |
4294 | PIPE_CRC_OBJECT_PIPE, | |
4295 | }; | |
4296 | ||
e8dfcf78 | 4297 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4298 | "pipe", |
4299 | }; | |
4300 | ||
4301 | static int | |
bd9db02f | 4302 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4303 | { |
4304 | int i; | |
4305 | ||
4306 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4307 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4308 | *o = i; |
b94dec87 DL |
4309 | return 0; |
4310 | } | |
4311 | ||
4312 | return -EINVAL; | |
4313 | } | |
4314 | ||
bd9db02f | 4315 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4316 | { |
4317 | const char name = buf[0]; | |
4318 | ||
4319 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4320 | return -EINVAL; | |
4321 | ||
4322 | *pipe = name - 'A'; | |
4323 | ||
4324 | return 0; | |
4325 | } | |
4326 | ||
4327 | static int | |
bd9db02f | 4328 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4329 | { |
4330 | int i; | |
4331 | ||
4332 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4333 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4334 | *s = i; |
926321d5 DV |
4335 | return 0; |
4336 | } | |
4337 | ||
4338 | return -EINVAL; | |
4339 | } | |
4340 | ||
36cdd013 DW |
4341 | static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, |
4342 | char *buf, size_t len) | |
926321d5 | 4343 | { |
b94dec87 | 4344 | #define N_WORDS 3 |
926321d5 | 4345 | int n_words; |
b94dec87 | 4346 | char *words[N_WORDS]; |
926321d5 | 4347 | enum pipe pipe; |
b94dec87 | 4348 | enum intel_pipe_crc_object object; |
926321d5 DV |
4349 | enum intel_pipe_crc_source source; |
4350 | ||
bd9db02f | 4351 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4352 | if (n_words != N_WORDS) { |
4353 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4354 | N_WORDS); | |
4355 | return -EINVAL; | |
4356 | } | |
4357 | ||
bd9db02f | 4358 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4359 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4360 | return -EINVAL; |
4361 | } | |
4362 | ||
bd9db02f | 4363 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4364 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4365 | return -EINVAL; |
4366 | } | |
4367 | ||
bd9db02f | 4368 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4369 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4370 | return -EINVAL; |
4371 | } | |
4372 | ||
36cdd013 | 4373 | return pipe_crc_set_source(dev_priv, pipe, source); |
926321d5 DV |
4374 | } |
4375 | ||
bd9db02f DL |
4376 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4377 | size_t len, loff_t *offp) | |
926321d5 DV |
4378 | { |
4379 | struct seq_file *m = file->private_data; | |
36cdd013 | 4380 | struct drm_i915_private *dev_priv = m->private; |
926321d5 DV |
4381 | char *tmpbuf; |
4382 | int ret; | |
4383 | ||
4384 | if (len == 0) | |
4385 | return 0; | |
4386 | ||
4387 | if (len > PAGE_SIZE - 1) { | |
4388 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4389 | PAGE_SIZE); | |
4390 | return -E2BIG; | |
4391 | } | |
4392 | ||
4393 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4394 | if (!tmpbuf) | |
4395 | return -ENOMEM; | |
4396 | ||
4397 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4398 | ret = -EFAULT; | |
4399 | goto out; | |
4400 | } | |
4401 | tmpbuf[len] = '\0'; | |
4402 | ||
36cdd013 | 4403 | ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); |
926321d5 DV |
4404 | |
4405 | out: | |
4406 | kfree(tmpbuf); | |
4407 | if (ret < 0) | |
4408 | return ret; | |
4409 | ||
4410 | *offp += len; | |
4411 | return len; | |
4412 | } | |
4413 | ||
bd9db02f | 4414 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4415 | .owner = THIS_MODULE, |
bd9db02f | 4416 | .open = display_crc_ctl_open, |
926321d5 DV |
4417 | .read = seq_read, |
4418 | .llseek = seq_lseek, | |
4419 | .release = single_release, | |
bd9db02f | 4420 | .write = display_crc_ctl_write |
926321d5 DV |
4421 | }; |
4422 | ||
eb3394fa | 4423 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
4424 | const char __user *ubuf, |
4425 | size_t len, loff_t *offp) | |
eb3394fa TP |
4426 | { |
4427 | char *input_buffer; | |
4428 | int status = 0; | |
eb3394fa TP |
4429 | struct drm_device *dev; |
4430 | struct drm_connector *connector; | |
4431 | struct list_head *connector_list; | |
4432 | struct intel_dp *intel_dp; | |
4433 | int val = 0; | |
4434 | ||
9aaffa34 | 4435 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4436 | |
eb3394fa TP |
4437 | connector_list = &dev->mode_config.connector_list; |
4438 | ||
4439 | if (len == 0) | |
4440 | return 0; | |
4441 | ||
4442 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4443 | if (!input_buffer) | |
4444 | return -ENOMEM; | |
4445 | ||
4446 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4447 | status = -EFAULT; | |
4448 | goto out; | |
4449 | } | |
4450 | ||
4451 | input_buffer[len] = '\0'; | |
4452 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4453 | ||
4454 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
4455 | if (connector->connector_type != |
4456 | DRM_MODE_CONNECTOR_DisplayPort) | |
4457 | continue; | |
4458 | ||
b8bb08ec | 4459 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4460 | connector->encoder != NULL) { |
4461 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4462 | status = kstrtoint(input_buffer, 10, &val); | |
4463 | if (status < 0) | |
4464 | goto out; | |
4465 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4466 | /* To prevent erroneous activation of the compliance | |
4467 | * testing code, only accept an actual value of 1 here | |
4468 | */ | |
4469 | if (val == 1) | |
4470 | intel_dp->compliance_test_active = 1; | |
4471 | else | |
4472 | intel_dp->compliance_test_active = 0; | |
4473 | } | |
4474 | } | |
4475 | out: | |
4476 | kfree(input_buffer); | |
4477 | if (status < 0) | |
4478 | return status; | |
4479 | ||
4480 | *offp += len; | |
4481 | return len; | |
4482 | } | |
4483 | ||
4484 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4485 | { | |
4486 | struct drm_device *dev = m->private; | |
4487 | struct drm_connector *connector; | |
4488 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4489 | struct intel_dp *intel_dp; | |
4490 | ||
eb3394fa | 4491 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4492 | if (connector->connector_type != |
4493 | DRM_MODE_CONNECTOR_DisplayPort) | |
4494 | continue; | |
4495 | ||
4496 | if (connector->status == connector_status_connected && | |
4497 | connector->encoder != NULL) { | |
4498 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4499 | if (intel_dp->compliance_test_active) | |
4500 | seq_puts(m, "1"); | |
4501 | else | |
4502 | seq_puts(m, "0"); | |
4503 | } else | |
4504 | seq_puts(m, "0"); | |
4505 | } | |
4506 | ||
4507 | return 0; | |
4508 | } | |
4509 | ||
4510 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 4511 | struct file *file) |
eb3394fa | 4512 | { |
36cdd013 | 4513 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4514 | |
36cdd013 DW |
4515 | return single_open(file, i915_displayport_test_active_show, |
4516 | &dev_priv->drm); | |
eb3394fa TP |
4517 | } |
4518 | ||
4519 | static const struct file_operations i915_displayport_test_active_fops = { | |
4520 | .owner = THIS_MODULE, | |
4521 | .open = i915_displayport_test_active_open, | |
4522 | .read = seq_read, | |
4523 | .llseek = seq_lseek, | |
4524 | .release = single_release, | |
4525 | .write = i915_displayport_test_active_write | |
4526 | }; | |
4527 | ||
4528 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4529 | { | |
4530 | struct drm_device *dev = m->private; | |
4531 | struct drm_connector *connector; | |
4532 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4533 | struct intel_dp *intel_dp; | |
4534 | ||
eb3394fa | 4535 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4536 | if (connector->connector_type != |
4537 | DRM_MODE_CONNECTOR_DisplayPort) | |
4538 | continue; | |
4539 | ||
4540 | if (connector->status == connector_status_connected && | |
4541 | connector->encoder != NULL) { | |
4542 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4543 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4544 | } else | |
4545 | seq_puts(m, "0"); | |
4546 | } | |
4547 | ||
4548 | return 0; | |
4549 | } | |
4550 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 4551 | struct file *file) |
eb3394fa | 4552 | { |
36cdd013 | 4553 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4554 | |
36cdd013 DW |
4555 | return single_open(file, i915_displayport_test_data_show, |
4556 | &dev_priv->drm); | |
eb3394fa TP |
4557 | } |
4558 | ||
4559 | static const struct file_operations i915_displayport_test_data_fops = { | |
4560 | .owner = THIS_MODULE, | |
4561 | .open = i915_displayport_test_data_open, | |
4562 | .read = seq_read, | |
4563 | .llseek = seq_lseek, | |
4564 | .release = single_release | |
4565 | }; | |
4566 | ||
4567 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4568 | { | |
4569 | struct drm_device *dev = m->private; | |
4570 | struct drm_connector *connector; | |
4571 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4572 | struct intel_dp *intel_dp; | |
4573 | ||
eb3394fa | 4574 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
4575 | if (connector->connector_type != |
4576 | DRM_MODE_CONNECTOR_DisplayPort) | |
4577 | continue; | |
4578 | ||
4579 | if (connector->status == connector_status_connected && | |
4580 | connector->encoder != NULL) { | |
4581 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4582 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4583 | } else | |
4584 | seq_puts(m, "0"); | |
4585 | } | |
4586 | ||
4587 | return 0; | |
4588 | } | |
4589 | ||
4590 | static int i915_displayport_test_type_open(struct inode *inode, | |
4591 | struct file *file) | |
4592 | { | |
36cdd013 | 4593 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 4594 | |
36cdd013 DW |
4595 | return single_open(file, i915_displayport_test_type_show, |
4596 | &dev_priv->drm); | |
eb3394fa TP |
4597 | } |
4598 | ||
4599 | static const struct file_operations i915_displayport_test_type_fops = { | |
4600 | .owner = THIS_MODULE, | |
4601 | .open = i915_displayport_test_type_open, | |
4602 | .read = seq_read, | |
4603 | .llseek = seq_lseek, | |
4604 | .release = single_release | |
4605 | }; | |
4606 | ||
97e94b22 | 4607 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 4608 | { |
36cdd013 DW |
4609 | struct drm_i915_private *dev_priv = m->private; |
4610 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 4611 | int level; |
de38b95c VS |
4612 | int num_levels; |
4613 | ||
36cdd013 | 4614 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4615 | num_levels = 3; |
36cdd013 | 4616 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4617 | num_levels = 1; |
4618 | else | |
5db94019 | 4619 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
4620 | |
4621 | drm_modeset_lock_all(dev); | |
4622 | ||
4623 | for (level = 0; level < num_levels; level++) { | |
4624 | unsigned int latency = wm[level]; | |
4625 | ||
97e94b22 DL |
4626 | /* |
4627 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4628 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4629 | */ |
36cdd013 DW |
4630 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
4631 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
4632 | latency *= 10; |
4633 | else if (level > 0) | |
369a1342 VS |
4634 | latency *= 5; |
4635 | ||
4636 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4637 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4638 | } |
4639 | ||
4640 | drm_modeset_unlock_all(dev); | |
4641 | } | |
4642 | ||
4643 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4644 | { | |
36cdd013 | 4645 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4646 | const uint16_t *latencies; |
4647 | ||
36cdd013 | 4648 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4649 | latencies = dev_priv->wm.skl_latency; |
4650 | else | |
36cdd013 | 4651 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 4652 | |
97e94b22 | 4653 | wm_latency_show(m, latencies); |
369a1342 VS |
4654 | |
4655 | return 0; | |
4656 | } | |
4657 | ||
4658 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4659 | { | |
36cdd013 | 4660 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4661 | const uint16_t *latencies; |
4662 | ||
36cdd013 | 4663 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4664 | latencies = dev_priv->wm.skl_latency; |
4665 | else | |
36cdd013 | 4666 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 4667 | |
97e94b22 | 4668 | wm_latency_show(m, latencies); |
369a1342 VS |
4669 | |
4670 | return 0; | |
4671 | } | |
4672 | ||
4673 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4674 | { | |
36cdd013 | 4675 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4676 | const uint16_t *latencies; |
4677 | ||
36cdd013 | 4678 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4679 | latencies = dev_priv->wm.skl_latency; |
4680 | else | |
36cdd013 | 4681 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4682 | |
97e94b22 | 4683 | wm_latency_show(m, latencies); |
369a1342 VS |
4684 | |
4685 | return 0; | |
4686 | } | |
4687 | ||
4688 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4689 | { | |
36cdd013 | 4690 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4691 | |
36cdd013 | 4692 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
4693 | return -ENODEV; |
4694 | ||
36cdd013 | 4695 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
4696 | } |
4697 | ||
4698 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4699 | { | |
36cdd013 | 4700 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4701 | |
36cdd013 | 4702 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4703 | return -ENODEV; |
4704 | ||
36cdd013 | 4705 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
4706 | } |
4707 | ||
4708 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4709 | { | |
36cdd013 | 4710 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4711 | |
36cdd013 | 4712 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4713 | return -ENODEV; |
4714 | ||
36cdd013 | 4715 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4716 | } |
4717 | ||
4718 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4719 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4720 | { |
4721 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4722 | struct drm_i915_private *dev_priv = m->private; |
4723 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4724 | uint16_t new[8] = { 0 }; |
de38b95c | 4725 | int num_levels; |
369a1342 VS |
4726 | int level; |
4727 | int ret; | |
4728 | char tmp[32]; | |
4729 | ||
36cdd013 | 4730 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4731 | num_levels = 3; |
36cdd013 | 4732 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4733 | num_levels = 1; |
4734 | else | |
5db94019 | 4735 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4736 | |
369a1342 VS |
4737 | if (len >= sizeof(tmp)) |
4738 | return -EINVAL; | |
4739 | ||
4740 | if (copy_from_user(tmp, ubuf, len)) | |
4741 | return -EFAULT; | |
4742 | ||
4743 | tmp[len] = '\0'; | |
4744 | ||
97e94b22 DL |
4745 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4746 | &new[0], &new[1], &new[2], &new[3], | |
4747 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4748 | if (ret != num_levels) |
4749 | return -EINVAL; | |
4750 | ||
4751 | drm_modeset_lock_all(dev); | |
4752 | ||
4753 | for (level = 0; level < num_levels; level++) | |
4754 | wm[level] = new[level]; | |
4755 | ||
4756 | drm_modeset_unlock_all(dev); | |
4757 | ||
4758 | return len; | |
4759 | } | |
4760 | ||
4761 | ||
4762 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4763 | size_t len, loff_t *offp) | |
4764 | { | |
4765 | struct seq_file *m = file->private_data; | |
36cdd013 | 4766 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4767 | uint16_t *latencies; |
369a1342 | 4768 | |
36cdd013 | 4769 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4770 | latencies = dev_priv->wm.skl_latency; |
4771 | else | |
36cdd013 | 4772 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4773 | |
4774 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4775 | } |
4776 | ||
4777 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4778 | size_t len, loff_t *offp) | |
4779 | { | |
4780 | struct seq_file *m = file->private_data; | |
36cdd013 | 4781 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4782 | uint16_t *latencies; |
369a1342 | 4783 | |
36cdd013 | 4784 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4785 | latencies = dev_priv->wm.skl_latency; |
4786 | else | |
36cdd013 | 4787 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4788 | |
4789 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4790 | } |
4791 | ||
4792 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4793 | size_t len, loff_t *offp) | |
4794 | { | |
4795 | struct seq_file *m = file->private_data; | |
36cdd013 | 4796 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4797 | uint16_t *latencies; |
4798 | ||
36cdd013 | 4799 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4800 | latencies = dev_priv->wm.skl_latency; |
4801 | else | |
36cdd013 | 4802 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4803 | |
97e94b22 | 4804 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4805 | } |
4806 | ||
4807 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4808 | .owner = THIS_MODULE, | |
4809 | .open = pri_wm_latency_open, | |
4810 | .read = seq_read, | |
4811 | .llseek = seq_lseek, | |
4812 | .release = single_release, | |
4813 | .write = pri_wm_latency_write | |
4814 | }; | |
4815 | ||
4816 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4817 | .owner = THIS_MODULE, | |
4818 | .open = spr_wm_latency_open, | |
4819 | .read = seq_read, | |
4820 | .llseek = seq_lseek, | |
4821 | .release = single_release, | |
4822 | .write = spr_wm_latency_write | |
4823 | }; | |
4824 | ||
4825 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4826 | .owner = THIS_MODULE, | |
4827 | .open = cur_wm_latency_open, | |
4828 | .read = seq_read, | |
4829 | .llseek = seq_lseek, | |
4830 | .release = single_release, | |
4831 | .write = cur_wm_latency_write | |
4832 | }; | |
4833 | ||
647416f9 KC |
4834 | static int |
4835 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4836 | { |
36cdd013 | 4837 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4838 | |
d98c52cf | 4839 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4840 | |
647416f9 | 4841 | return 0; |
f3cd474b CW |
4842 | } |
4843 | ||
647416f9 KC |
4844 | static int |
4845 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4846 | { |
36cdd013 | 4847 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4848 | |
b8d24a06 MK |
4849 | /* |
4850 | * There is no safeguard against this debugfs entry colliding | |
4851 | * with the hangcheck calling same i915_handle_error() in | |
4852 | * parallel, causing an explosion. For now we assume that the | |
4853 | * test harness is responsible enough not to inject gpu hangs | |
4854 | * while it is writing to 'i915_wedged' | |
4855 | */ | |
4856 | ||
d98c52cf | 4857 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4858 | return -EAGAIN; |
4859 | ||
c033666a | 4860 | i915_handle_error(dev_priv, val, |
58174462 | 4861 | "Manually setting wedged to %llu", val); |
d46c0517 | 4862 | |
647416f9 | 4863 | return 0; |
f3cd474b CW |
4864 | } |
4865 | ||
647416f9 KC |
4866 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4867 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4868 | "%llu\n"); |
f3cd474b | 4869 | |
094f9a54 CW |
4870 | static int |
4871 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4872 | { | |
36cdd013 | 4873 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4874 | |
4875 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4876 | return 0; | |
4877 | } | |
4878 | ||
4879 | static int | |
4880 | i915_ring_missed_irq_set(void *data, u64 val) | |
4881 | { | |
36cdd013 DW |
4882 | struct drm_i915_private *dev_priv = data; |
4883 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4884 | int ret; |
4885 | ||
4886 | /* Lock against concurrent debugfs callers */ | |
4887 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4888 | if (ret) | |
4889 | return ret; | |
4890 | dev_priv->gpu_error.missed_irq_rings = val; | |
4891 | mutex_unlock(&dev->struct_mutex); | |
4892 | ||
4893 | return 0; | |
4894 | } | |
4895 | ||
4896 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4897 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4898 | "0x%08llx\n"); | |
4899 | ||
4900 | static int | |
4901 | i915_ring_test_irq_get(void *data, u64 *val) | |
4902 | { | |
36cdd013 | 4903 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4904 | |
4905 | *val = dev_priv->gpu_error.test_irq_rings; | |
4906 | ||
4907 | return 0; | |
4908 | } | |
4909 | ||
4910 | static int | |
4911 | i915_ring_test_irq_set(void *data, u64 val) | |
4912 | { | |
36cdd013 | 4913 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4914 | |
3a122c27 | 4915 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4916 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4917 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4918 | |
4919 | return 0; | |
4920 | } | |
4921 | ||
4922 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4923 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4924 | "0x%08llx\n"); | |
4925 | ||
dd624afd CW |
4926 | #define DROP_UNBOUND 0x1 |
4927 | #define DROP_BOUND 0x2 | |
4928 | #define DROP_RETIRE 0x4 | |
4929 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4930 | #define DROP_FREED 0x10 |
4931 | #define DROP_ALL (DROP_UNBOUND | \ | |
4932 | DROP_BOUND | \ | |
4933 | DROP_RETIRE | \ | |
4934 | DROP_ACTIVE | \ | |
4935 | DROP_FREED) | |
647416f9 KC |
4936 | static int |
4937 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4938 | { |
647416f9 | 4939 | *val = DROP_ALL; |
dd624afd | 4940 | |
647416f9 | 4941 | return 0; |
dd624afd CW |
4942 | } |
4943 | ||
647416f9 KC |
4944 | static int |
4945 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4946 | { |
36cdd013 DW |
4947 | struct drm_i915_private *dev_priv = data; |
4948 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4949 | int ret; |
dd624afd | 4950 | |
2f9fe5ff | 4951 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4952 | |
4953 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4954 | * on ioctls on -EAGAIN. */ | |
4955 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4956 | if (ret) | |
4957 | return ret; | |
4958 | ||
4959 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4960 | ret = i915_gem_wait_for_idle(dev_priv, |
4961 | I915_WAIT_INTERRUPTIBLE | | |
4962 | I915_WAIT_LOCKED); | |
dd624afd CW |
4963 | if (ret) |
4964 | goto unlock; | |
4965 | } | |
4966 | ||
4967 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4968 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4969 | |
21ab4e74 CW |
4970 | if (val & DROP_BOUND) |
4971 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4972 | |
21ab4e74 CW |
4973 | if (val & DROP_UNBOUND) |
4974 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4975 | |
4976 | unlock: | |
4977 | mutex_unlock(&dev->struct_mutex); | |
4978 | ||
fbbd37b3 CW |
4979 | if (val & DROP_FREED) { |
4980 | synchronize_rcu(); | |
4981 | flush_work(&dev_priv->mm.free_work); | |
4982 | } | |
4983 | ||
647416f9 | 4984 | return ret; |
dd624afd CW |
4985 | } |
4986 | ||
647416f9 KC |
4987 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4988 | i915_drop_caches_get, i915_drop_caches_set, | |
4989 | "0x%08llx\n"); | |
dd624afd | 4990 | |
647416f9 KC |
4991 | static int |
4992 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4993 | { |
36cdd013 | 4994 | struct drm_i915_private *dev_priv = data; |
004777cb | 4995 | |
36cdd013 | 4996 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4997 | return -ENODEV; |
4998 | ||
7c59a9c1 | 4999 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 5000 | return 0; |
358733e9 JB |
5001 | } |
5002 | ||
647416f9 KC |
5003 | static int |
5004 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 5005 | { |
36cdd013 | 5006 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 5007 | u32 hw_max, hw_min; |
647416f9 | 5008 | int ret; |
004777cb | 5009 | |
36cdd013 | 5010 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 5011 | return -ENODEV; |
358733e9 | 5012 | |
647416f9 | 5013 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 5014 | |
4fc688ce | 5015 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5016 | if (ret) |
5017 | return ret; | |
5018 | ||
358733e9 JB |
5019 | /* |
5020 | * Turbo will still be enabled, but won't go above the set value. | |
5021 | */ | |
bc4d91f6 | 5022 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5023 | |
bc4d91f6 AG |
5024 | hw_max = dev_priv->rps.max_freq; |
5025 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5026 | |
b39fb297 | 5027 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
5028 | mutex_unlock(&dev_priv->rps.hw_lock); |
5029 | return -EINVAL; | |
0a073b84 JB |
5030 | } |
5031 | ||
b39fb297 | 5032 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 5033 | |
dc97997a | 5034 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5035 | |
4fc688ce | 5036 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 5037 | |
647416f9 | 5038 | return 0; |
358733e9 JB |
5039 | } |
5040 | ||
647416f9 KC |
5041 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
5042 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 5043 | "%llu\n"); |
358733e9 | 5044 | |
647416f9 KC |
5045 | static int |
5046 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5047 | { |
36cdd013 | 5048 | struct drm_i915_private *dev_priv = data; |
004777cb | 5049 | |
62e1baa1 | 5050 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
5051 | return -ENODEV; |
5052 | ||
7c59a9c1 | 5053 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 5054 | return 0; |
1523c310 JB |
5055 | } |
5056 | ||
647416f9 KC |
5057 | static int |
5058 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5059 | { |
36cdd013 | 5060 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 5061 | u32 hw_max, hw_min; |
647416f9 | 5062 | int ret; |
004777cb | 5063 | |
62e1baa1 | 5064 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 5065 | return -ENODEV; |
1523c310 | 5066 | |
647416f9 | 5067 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5068 | |
4fc688ce | 5069 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5070 | if (ret) |
5071 | return ret; | |
5072 | ||
1523c310 JB |
5073 | /* |
5074 | * Turbo will still be enabled, but won't go below the set value. | |
5075 | */ | |
bc4d91f6 | 5076 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5077 | |
bc4d91f6 AG |
5078 | hw_max = dev_priv->rps.max_freq; |
5079 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5080 | |
36cdd013 DW |
5081 | if (val < hw_min || |
5082 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
5083 | mutex_unlock(&dev_priv->rps.hw_lock); |
5084 | return -EINVAL; | |
0a073b84 | 5085 | } |
dd0a1aa1 | 5086 | |
b39fb297 | 5087 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5088 | |
dc97997a | 5089 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5090 | |
4fc688ce | 5091 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5092 | |
647416f9 | 5093 | return 0; |
1523c310 JB |
5094 | } |
5095 | ||
647416f9 KC |
5096 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5097 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5098 | "%llu\n"); |
1523c310 | 5099 | |
647416f9 KC |
5100 | static int |
5101 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5102 | { |
36cdd013 | 5103 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 5104 | u32 snpcr; |
07b7ddd9 | 5105 | |
36cdd013 | 5106 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
5107 | return -ENODEV; |
5108 | ||
c8c8fb33 | 5109 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5110 | |
07b7ddd9 | 5111 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5112 | |
5113 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 5114 | |
647416f9 | 5115 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5116 | |
647416f9 | 5117 | return 0; |
07b7ddd9 JB |
5118 | } |
5119 | ||
647416f9 KC |
5120 | static int |
5121 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5122 | { |
36cdd013 | 5123 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 5124 | u32 snpcr; |
07b7ddd9 | 5125 | |
36cdd013 | 5126 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
5127 | return -ENODEV; |
5128 | ||
647416f9 | 5129 | if (val > 3) |
07b7ddd9 JB |
5130 | return -EINVAL; |
5131 | ||
c8c8fb33 | 5132 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5133 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5134 | |
5135 | /* Update the cache sharing policy here as well */ | |
5136 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5137 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5138 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5139 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5140 | ||
c8c8fb33 | 5141 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5142 | return 0; |
07b7ddd9 JB |
5143 | } |
5144 | ||
647416f9 KC |
5145 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5146 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5147 | "%llu\n"); | |
07b7ddd9 | 5148 | |
36cdd013 | 5149 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5150 | struct sseu_dev_info *sseu) |
5d39525a | 5151 | { |
0a0b457f | 5152 | int ss_max = 2; |
5d39525a JM |
5153 | int ss; |
5154 | u32 sig1[ss_max], sig2[ss_max]; | |
5155 | ||
5156 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5157 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5158 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5159 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5160 | ||
5161 | for (ss = 0; ss < ss_max; ss++) { | |
5162 | unsigned int eu_cnt; | |
5163 | ||
5164 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5165 | /* skip disabled subslice */ | |
5166 | continue; | |
5167 | ||
f08a0c92 | 5168 | sseu->slice_mask = BIT(0); |
57ec171e | 5169 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
5170 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
5171 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5172 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5173 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
5174 | sseu->eu_total += eu_cnt; |
5175 | sseu->eu_per_subslice = max_t(unsigned int, | |
5176 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 5177 | } |
5d39525a JM |
5178 | } |
5179 | ||
36cdd013 | 5180 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5181 | struct sseu_dev_info *sseu) |
5d39525a | 5182 | { |
1c046bc1 | 5183 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5184 | int s, ss; |
5185 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5186 | ||
1c046bc1 | 5187 | /* BXT has a single slice and at most 3 subslices. */ |
36cdd013 | 5188 | if (IS_BROXTON(dev_priv)) { |
1c046bc1 JM |
5189 | s_max = 1; |
5190 | ss_max = 3; | |
5191 | } | |
5192 | ||
5193 | for (s = 0; s < s_max; s++) { | |
5194 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5195 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5196 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5197 | } | |
5198 | ||
5d39525a JM |
5199 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5200 | GEN9_PGCTL_SSA_EU19_ACK | | |
5201 | GEN9_PGCTL_SSA_EU210_ACK | | |
5202 | GEN9_PGCTL_SSA_EU311_ACK; | |
5203 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5204 | GEN9_PGCTL_SSB_EU19_ACK | | |
5205 | GEN9_PGCTL_SSB_EU210_ACK | | |
5206 | GEN9_PGCTL_SSB_EU311_ACK; | |
5207 | ||
5208 | for (s = 0; s < s_max; s++) { | |
5209 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
5210 | /* skip disabled slice */ | |
5211 | continue; | |
5212 | ||
f08a0c92 | 5213 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 5214 | |
36cdd013 | 5215 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
5216 | sseu->subslice_mask = |
5217 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 5218 | |
5d39525a JM |
5219 | for (ss = 0; ss < ss_max; ss++) { |
5220 | unsigned int eu_cnt; | |
5221 | ||
57ec171e ID |
5222 | if (IS_BROXTON(dev_priv)) { |
5223 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5224 | /* skip disabled subslice */ | |
5225 | continue; | |
1c046bc1 | 5226 | |
57ec171e ID |
5227 | sseu->subslice_mask |= BIT(ss); |
5228 | } | |
1c046bc1 | 5229 | |
5d39525a JM |
5230 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5231 | eu_mask[ss%2]); | |
915490d5 ID |
5232 | sseu->eu_total += eu_cnt; |
5233 | sseu->eu_per_subslice = max_t(unsigned int, | |
5234 | sseu->eu_per_subslice, | |
5235 | eu_cnt); | |
5d39525a JM |
5236 | } |
5237 | } | |
5238 | } | |
5239 | ||
36cdd013 | 5240 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 5241 | struct sseu_dev_info *sseu) |
91bedd34 | 5242 | { |
91bedd34 | 5243 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 5244 | int s; |
91bedd34 | 5245 | |
f08a0c92 | 5246 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 5247 | |
f08a0c92 | 5248 | if (sseu->slice_mask) { |
57ec171e | 5249 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
5250 | sseu->eu_per_subslice = |
5251 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
5252 | sseu->eu_total = sseu->eu_per_subslice * |
5253 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
5254 | |
5255 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 5256 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
5257 | u8 subslice_7eu = |
5258 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 5259 | |
915490d5 | 5260 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
5261 | } |
5262 | } | |
5263 | } | |
5264 | ||
615d8908 ID |
5265 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
5266 | const struct sseu_dev_info *sseu) | |
5267 | { | |
5268 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
5269 | const char *type = is_available_info ? "Available" : "Enabled"; | |
5270 | ||
c67ba538 ID |
5271 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
5272 | sseu->slice_mask); | |
615d8908 | 5273 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 5274 | hweight8(sseu->slice_mask)); |
615d8908 | 5275 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 5276 | sseu_subslice_total(sseu)); |
c67ba538 ID |
5277 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
5278 | sseu->subslice_mask); | |
615d8908 | 5279 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 5280 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
5281 | seq_printf(m, " %s EU Total: %u\n", type, |
5282 | sseu->eu_total); | |
5283 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
5284 | sseu->eu_per_subslice); | |
5285 | ||
5286 | if (!is_available_info) | |
5287 | return; | |
5288 | ||
5289 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
5290 | if (HAS_POOLED_EU(dev_priv)) | |
5291 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
5292 | ||
5293 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5294 | yesno(sseu->has_slice_pg)); | |
5295 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5296 | yesno(sseu->has_subslice_pg)); | |
5297 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5298 | yesno(sseu->has_eu_pg)); | |
5299 | } | |
5300 | ||
3873218f JM |
5301 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5302 | { | |
36cdd013 | 5303 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 5304 | struct sseu_dev_info sseu; |
3873218f | 5305 | |
36cdd013 | 5306 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
5307 | return -ENODEV; |
5308 | ||
5309 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 5310 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 5311 | |
7f992aba | 5312 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 5313 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
5314 | |
5315 | intel_runtime_pm_get(dev_priv); | |
5316 | ||
36cdd013 | 5317 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 5318 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5319 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 5320 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 5321 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 5322 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 5323 | } |
238010ed DW |
5324 | |
5325 | intel_runtime_pm_put(dev_priv); | |
5326 | ||
615d8908 | 5327 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 5328 | |
3873218f JM |
5329 | return 0; |
5330 | } | |
5331 | ||
6d794d42 BW |
5332 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5333 | { | |
36cdd013 | 5334 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5335 | |
36cdd013 | 5336 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5337 | return 0; |
5338 | ||
6daccb0b | 5339 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5340 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5341 | |
5342 | return 0; | |
5343 | } | |
5344 | ||
c43b5634 | 5345 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 5346 | { |
36cdd013 | 5347 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 5348 | |
36cdd013 | 5349 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
5350 | return 0; |
5351 | ||
59bad947 | 5352 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5353 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5354 | |
5355 | return 0; | |
5356 | } | |
5357 | ||
5358 | static const struct file_operations i915_forcewake_fops = { | |
5359 | .owner = THIS_MODULE, | |
5360 | .open = i915_forcewake_open, | |
5361 | .release = i915_forcewake_release, | |
5362 | }; | |
5363 | ||
5364 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5365 | { | |
6d794d42 BW |
5366 | struct dentry *ent; |
5367 | ||
5368 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5369 | S_IRUSR, |
36cdd013 | 5370 | root, to_i915(minor->dev), |
6d794d42 | 5371 | &i915_forcewake_fops); |
f3c5fe97 WY |
5372 | if (!ent) |
5373 | return -ENOMEM; | |
6d794d42 | 5374 | |
8eb57294 | 5375 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5376 | } |
5377 | ||
6a9c308d DV |
5378 | static int i915_debugfs_create(struct dentry *root, |
5379 | struct drm_minor *minor, | |
5380 | const char *name, | |
5381 | const struct file_operations *fops) | |
07b7ddd9 | 5382 | { |
07b7ddd9 JB |
5383 | struct dentry *ent; |
5384 | ||
6a9c308d | 5385 | ent = debugfs_create_file(name, |
07b7ddd9 | 5386 | S_IRUGO | S_IWUSR, |
36cdd013 | 5387 | root, to_i915(minor->dev), |
6a9c308d | 5388 | fops); |
f3c5fe97 WY |
5389 | if (!ent) |
5390 | return -ENOMEM; | |
07b7ddd9 | 5391 | |
6a9c308d | 5392 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5393 | } |
5394 | ||
06c5bf8c | 5395 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5396 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5397 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5398 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 5399 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 5400 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5401 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5402 | {"i915_gem_request", i915_gem_request_info, 0}, |
5403 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5404 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5405 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5406 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5407 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5408 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5409 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5410 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5411 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5412 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5413 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5414 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5415 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5416 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5417 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5418 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5419 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5420 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5421 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5422 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5423 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5424 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5425 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5426 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5427 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 5428 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5429 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5430 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5431 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5432 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5433 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5434 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5435 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5436 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5437 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5438 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 5439 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 5440 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5441 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5442 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5443 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5444 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5445 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5446 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5447 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5448 | }; |
27c202ad | 5449 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5450 | |
06c5bf8c | 5451 | static const struct i915_debugfs_files { |
34b9674c DV |
5452 | const char *name; |
5453 | const struct file_operations *fops; | |
5454 | } i915_debugfs_files[] = { | |
5455 | {"i915_wedged", &i915_wedged_fops}, | |
5456 | {"i915_max_freq", &i915_max_freq_fops}, | |
5457 | {"i915_min_freq", &i915_min_freq_fops}, | |
5458 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5459 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5460 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 5461 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 5462 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 5463 | {"i915_error_state", &i915_error_state_fops}, |
98a2f411 | 5464 | #endif |
34b9674c | 5465 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 5466 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5467 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5468 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5469 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5470 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5471 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5472 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef SAK |
5473 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
5474 | {"i915_guc_log_control", &i915_guc_log_control_fops} | |
34b9674c DV |
5475 | }; |
5476 | ||
36cdd013 | 5477 | void intel_display_crc_init(struct drm_i915_private *dev_priv) |
07144428 | 5478 | { |
b378360e | 5479 | enum pipe pipe; |
07144428 | 5480 | |
055e393f | 5481 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5482 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5483 | |
d538bbdf DL |
5484 | pipe_crc->opened = false; |
5485 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5486 | init_waitqueue_head(&pipe_crc->wq); |
5487 | } | |
5488 | } | |
5489 | ||
1dac891c | 5490 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5491 | { |
91c8a326 | 5492 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5493 | int ret, i; |
f3cd474b | 5494 | |
6d794d42 | 5495 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5496 | if (ret) |
5497 | return ret; | |
6a9c308d | 5498 | |
07144428 DL |
5499 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5500 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5501 | if (ret) | |
5502 | return ret; | |
5503 | } | |
5504 | ||
34b9674c DV |
5505 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5506 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5507 | i915_debugfs_files[i].name, | |
5508 | i915_debugfs_files[i].fops); | |
5509 | if (ret) | |
5510 | return ret; | |
5511 | } | |
40633219 | 5512 | |
27c202ad BG |
5513 | return drm_debugfs_create_files(i915_debugfs_list, |
5514 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5515 | minor->debugfs_root, minor); |
5516 | } | |
5517 | ||
1dac891c | 5518 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5519 | { |
91c8a326 | 5520 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5521 | int i; |
5522 | ||
27c202ad BG |
5523 | drm_debugfs_remove_files(i915_debugfs_list, |
5524 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5525 | |
36cdd013 | 5526 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 5527 | 1, minor); |
07144428 | 5528 | |
e309a997 | 5529 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5530 | struct drm_info_list *info_list = |
5531 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5532 | ||
5533 | drm_debugfs_remove_files(info_list, 1, minor); | |
5534 | } | |
5535 | ||
34b9674c DV |
5536 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5537 | struct drm_info_list *info_list = | |
36cdd013 | 5538 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
5539 | |
5540 | drm_debugfs_remove_files(info_list, 1, minor); | |
5541 | } | |
2017263e | 5542 | } |
aa7471d2 JN |
5543 | |
5544 | struct dpcd_block { | |
5545 | /* DPCD dump start address. */ | |
5546 | unsigned int offset; | |
5547 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5548 | unsigned int end; | |
5549 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5550 | size_t size; | |
5551 | /* Only valid for eDP. */ | |
5552 | bool edp; | |
5553 | }; | |
5554 | ||
5555 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5556 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5557 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5558 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5559 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5560 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5561 | { .offset = DP_SET_POWER }, | |
5562 | { .offset = DP_EDP_DPCD_REV }, | |
5563 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5564 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5565 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5566 | }; | |
5567 | ||
5568 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5569 | { | |
5570 | struct drm_connector *connector = m->private; | |
5571 | struct intel_dp *intel_dp = | |
5572 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5573 | uint8_t buf[16]; | |
5574 | ssize_t err; | |
5575 | int i; | |
5576 | ||
5c1a8875 MK |
5577 | if (connector->status != connector_status_connected) |
5578 | return -ENODEV; | |
5579 | ||
aa7471d2 JN |
5580 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5581 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5582 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5583 | ||
5584 | if (b->edp && | |
5585 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5586 | continue; | |
5587 | ||
5588 | /* low tech for now */ | |
5589 | if (WARN_ON(size > sizeof(buf))) | |
5590 | continue; | |
5591 | ||
5592 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5593 | if (err <= 0) { | |
5594 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5595 | size, b->offset, err); | |
5596 | continue; | |
5597 | } | |
5598 | ||
5599 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5600 | } |
aa7471d2 JN |
5601 | |
5602 | return 0; | |
5603 | } | |
5604 | ||
5605 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5606 | { | |
5607 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5608 | } | |
5609 | ||
5610 | static const struct file_operations i915_dpcd_fops = { | |
5611 | .owner = THIS_MODULE, | |
5612 | .open = i915_dpcd_open, | |
5613 | .read = seq_read, | |
5614 | .llseek = seq_lseek, | |
5615 | .release = single_release, | |
5616 | }; | |
5617 | ||
ecbd6781 DW |
5618 | static int i915_panel_show(struct seq_file *m, void *data) |
5619 | { | |
5620 | struct drm_connector *connector = m->private; | |
5621 | struct intel_dp *intel_dp = | |
5622 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5623 | ||
5624 | if (connector->status != connector_status_connected) | |
5625 | return -ENODEV; | |
5626 | ||
5627 | seq_printf(m, "Panel power up delay: %d\n", | |
5628 | intel_dp->panel_power_up_delay); | |
5629 | seq_printf(m, "Panel power down delay: %d\n", | |
5630 | intel_dp->panel_power_down_delay); | |
5631 | seq_printf(m, "Backlight on delay: %d\n", | |
5632 | intel_dp->backlight_on_delay); | |
5633 | seq_printf(m, "Backlight off delay: %d\n", | |
5634 | intel_dp->backlight_off_delay); | |
5635 | ||
5636 | return 0; | |
5637 | } | |
5638 | ||
5639 | static int i915_panel_open(struct inode *inode, struct file *file) | |
5640 | { | |
5641 | return single_open(file, i915_panel_show, inode->i_private); | |
5642 | } | |
5643 | ||
5644 | static const struct file_operations i915_panel_fops = { | |
5645 | .owner = THIS_MODULE, | |
5646 | .open = i915_panel_open, | |
5647 | .read = seq_read, | |
5648 | .llseek = seq_lseek, | |
5649 | .release = single_release, | |
5650 | }; | |
5651 | ||
aa7471d2 JN |
5652 | /** |
5653 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5654 | * @connector: pointer to a registered drm_connector | |
5655 | * | |
5656 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5657 | * drm_debugfs_connector_remove(). | |
5658 | * | |
5659 | * Returns 0 on success, negative error codes on error. | |
5660 | */ | |
5661 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5662 | { | |
5663 | struct dentry *root = connector->debugfs_entry; | |
5664 | ||
5665 | /* The connector must have been registered beforehands. */ | |
5666 | if (!root) | |
5667 | return -ENODEV; | |
5668 | ||
5669 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5670 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5671 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5672 | connector, &i915_dpcd_fops); | |
5673 | ||
5674 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5675 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5676 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5677 | |
5678 | return 0; | |
5679 | } |