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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
6d2b8885 | 30 | #include <linux/list_sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
497666d8 DL |
38 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
39 | * allocated we need to hook into the minor for release. */ | |
40 | static int | |
41 | drm_add_fake_info_node(struct drm_minor *minor, | |
42 | struct dentry *ent, | |
43 | const void *key) | |
44 | { | |
45 | struct drm_info_node *node; | |
46 | ||
47 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
48 | if (node == NULL) { | |
49 | debugfs_remove(ent); | |
50 | return -ENOMEM; | |
51 | } | |
52 | ||
53 | node->minor = minor; | |
54 | node->dent = ent; | |
36cdd013 | 55 | node->info_ent = (void *)key; |
497666d8 DL |
56 | |
57 | mutex_lock(&minor->debugfs_lock); | |
58 | list_add(&node->list, &minor->debugfs_list); | |
59 | mutex_unlock(&minor->debugfs_lock); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
70d39fe4 CW |
64 | static int i915_capabilities(struct seq_file *m, void *data) |
65 | { | |
36cdd013 DW |
66 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
67 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 68 | |
36cdd013 | 69 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 70 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 71 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
79fc46df | 72 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 73 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 74 | #undef PRINT_FLAG |
70d39fe4 CW |
75 | |
76 | return 0; | |
77 | } | |
2017263e | 78 | |
a7363de7 | 79 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 80 | { |
573adb39 | 81 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
82 | } |
83 | ||
a7363de7 | 84 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
85 | { |
86 | return obj->pin_display ? 'p' : ' '; | |
87 | } | |
88 | ||
a7363de7 | 89 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 90 | { |
3e510a8e | 91 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 92 | default: |
be12a86b TU |
93 | case I915_TILING_NONE: return ' '; |
94 | case I915_TILING_X: return 'X'; | |
95 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 96 | } |
a6172a80 CW |
97 | } |
98 | ||
a7363de7 | 99 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 100 | { |
275f039d | 101 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
102 | } |
103 | ||
a7363de7 | 104 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 105 | { |
a4f5ea64 | 106 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
107 | } |
108 | ||
ca1543be TU |
109 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
110 | { | |
111 | u64 size = 0; | |
112 | struct i915_vma *vma; | |
113 | ||
1c7f4bca | 114 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 115 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
116 | size += vma->node.size; |
117 | } | |
118 | ||
119 | return size; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
b4716185 | 125 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 126 | struct intel_engine_cs *engine; |
1d693bcc | 127 | struct i915_vma *vma; |
faf5bf0a | 128 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
129 | int pin_count = 0; |
130 | ||
188c1ab7 CW |
131 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
132 | ||
d07f0e59 | 133 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 134 | &obj->base, |
be12a86b | 135 | get_active_flag(obj), |
37811fcc CW |
136 | get_pin_flag(obj), |
137 | get_tiling_flag(obj), | |
1d693bcc | 138 | get_global_flag(obj), |
be12a86b | 139 | get_pin_mapped_flag(obj), |
a05a5862 | 140 | obj->base.size / 1024, |
37811fcc | 141 | obj->base.read_domains, |
d07f0e59 | 142 | obj->base.write_domain, |
36cdd013 | 143 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
144 | obj->mm.dirty ? " dirty" : "", |
145 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
146 | if (obj->base.name) |
147 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 148 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 149 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 150 | pin_count++; |
ba0635ff DC |
151 | } |
152 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
153 | if (obj->pin_display) |
154 | seq_printf(m, " (display)"); | |
1c7f4bca | 155 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
156 | if (!drm_mm_node_allocated(&vma->node)) |
157 | continue; | |
158 | ||
8d2fdc3f | 159 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 160 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 161 | vma->node.start, vma->node.size); |
21976853 CW |
162 | if (i915_vma_is_ggtt(vma)) { |
163 | switch (vma->ggtt_view.type) { | |
164 | case I915_GGTT_VIEW_NORMAL: | |
165 | seq_puts(m, ", normal"); | |
166 | break; | |
167 | ||
168 | case I915_GGTT_VIEW_PARTIAL: | |
169 | seq_printf(m, ", partial [%08llx+%x]", | |
170 | vma->ggtt_view.params.partial.offset << PAGE_SHIFT, | |
171 | vma->ggtt_view.params.partial.size << PAGE_SHIFT); | |
172 | break; | |
173 | ||
174 | case I915_GGTT_VIEW_ROTATED: | |
175 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
176 | vma->ggtt_view.params.rotated.plane[0].width, | |
177 | vma->ggtt_view.params.rotated.plane[0].height, | |
178 | vma->ggtt_view.params.rotated.plane[0].stride, | |
179 | vma->ggtt_view.params.rotated.plane[0].offset, | |
180 | vma->ggtt_view.params.rotated.plane[1].width, | |
181 | vma->ggtt_view.params.rotated.plane[1].height, | |
182 | vma->ggtt_view.params.rotated.plane[1].stride, | |
183 | vma->ggtt_view.params.rotated.plane[1].offset); | |
184 | break; | |
185 | ||
186 | default: | |
187 | MISSING_CASE(vma->ggtt_view.type); | |
188 | break; | |
189 | } | |
190 | } | |
49ef5294 CW |
191 | if (vma->fence) |
192 | seq_printf(m, " , fence: %d%s", | |
193 | vma->fence->id, | |
194 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 195 | seq_puts(m, ")"); |
1d693bcc | 196 | } |
c1ad11fc | 197 | if (obj->stolen) |
440fd528 | 198 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 199 | |
d07f0e59 | 200 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
201 | if (engine) |
202 | seq_printf(m, " (%s)", engine->name); | |
203 | ||
faf5bf0a CW |
204 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
205 | if (frontbuffer_bits) | |
206 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
207 | } |
208 | ||
6d2b8885 CW |
209 | static int obj_rank_by_stolen(void *priv, |
210 | struct list_head *A, struct list_head *B) | |
211 | { | |
212 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 213 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 214 | struct drm_i915_gem_object *b = |
b25cb2f8 | 215 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 216 | |
2d05fa16 RV |
217 | if (a->stolen->start < b->stolen->start) |
218 | return -1; | |
219 | if (a->stolen->start > b->stolen->start) | |
220 | return 1; | |
221 | return 0; | |
6d2b8885 CW |
222 | } |
223 | ||
224 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
225 | { | |
36cdd013 DW |
226 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
227 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 228 | struct drm_i915_gem_object *obj; |
c44ef60e | 229 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
230 | LIST_HEAD(stolen); |
231 | int count, ret; | |
232 | ||
233 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
234 | if (ret) | |
235 | return ret; | |
236 | ||
237 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 238 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
239 | if (obj->stolen == NULL) |
240 | continue; | |
241 | ||
b25cb2f8 | 242 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
243 | |
244 | total_obj_size += obj->base.size; | |
ca1543be | 245 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
246 | count++; |
247 | } | |
56cea323 | 248 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
249 | if (obj->stolen == NULL) |
250 | continue; | |
251 | ||
b25cb2f8 | 252 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
253 | |
254 | total_obj_size += obj->base.size; | |
255 | count++; | |
256 | } | |
257 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
258 | seq_puts(m, "Stolen:\n"); | |
259 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 260 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
261 | seq_puts(m, " "); |
262 | describe_obj(m, obj); | |
263 | seq_putc(m, '\n'); | |
b25cb2f8 | 264 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
265 | } |
266 | mutex_unlock(&dev->struct_mutex); | |
267 | ||
c44ef60e | 268 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
269 | count, total_obj_size, total_gtt_size); |
270 | return 0; | |
271 | } | |
272 | ||
2db8e9d6 | 273 | struct file_stats { |
6313c204 | 274 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
275 | unsigned long count; |
276 | u64 total, unbound; | |
277 | u64 global, shared; | |
278 | u64 active, inactive; | |
2db8e9d6 CW |
279 | }; |
280 | ||
281 | static int per_file_stats(int id, void *ptr, void *data) | |
282 | { | |
283 | struct drm_i915_gem_object *obj = ptr; | |
284 | struct file_stats *stats = data; | |
6313c204 | 285 | struct i915_vma *vma; |
2db8e9d6 CW |
286 | |
287 | stats->count++; | |
288 | stats->total += obj->base.size; | |
15717de2 CW |
289 | if (!obj->bind_count) |
290 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
291 | if (obj->base.name || obj->base.dma_buf) |
292 | stats->shared += obj->base.size; | |
293 | ||
894eeecc CW |
294 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
295 | if (!drm_mm_node_allocated(&vma->node)) | |
296 | continue; | |
6313c204 | 297 | |
3272db53 | 298 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
299 | stats->global += vma->node.size; |
300 | } else { | |
301 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 302 | |
2bfa996e | 303 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 304 | continue; |
6313c204 | 305 | } |
894eeecc | 306 | |
b0decaf7 | 307 | if (i915_vma_is_active(vma)) |
894eeecc CW |
308 | stats->active += vma->node.size; |
309 | else | |
310 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
311 | } |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
b0da1b79 CW |
316 | #define print_file_stats(m, name, stats) do { \ |
317 | if (stats.count) \ | |
c44ef60e | 318 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
319 | name, \ |
320 | stats.count, \ | |
321 | stats.total, \ | |
322 | stats.active, \ | |
323 | stats.inactive, \ | |
324 | stats.global, \ | |
325 | stats.shared, \ | |
326 | stats.unbound); \ | |
327 | } while (0) | |
493018dc BV |
328 | |
329 | static void print_batch_pool_stats(struct seq_file *m, | |
330 | struct drm_i915_private *dev_priv) | |
331 | { | |
332 | struct drm_i915_gem_object *obj; | |
333 | struct file_stats stats; | |
e2f80391 | 334 | struct intel_engine_cs *engine; |
3b3f1650 | 335 | enum intel_engine_id id; |
b4ac5afc | 336 | int j; |
493018dc BV |
337 | |
338 | memset(&stats, 0, sizeof(stats)); | |
339 | ||
3b3f1650 | 340 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 341 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 342 | list_for_each_entry(obj, |
e2f80391 | 343 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
344 | batch_pool_link) |
345 | per_file_stats(0, obj, &stats); | |
346 | } | |
06fbca71 | 347 | } |
493018dc | 348 | |
b0da1b79 | 349 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
350 | } |
351 | ||
15da9565 CW |
352 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
353 | { | |
354 | struct i915_gem_context *ctx = ptr; | |
355 | int n; | |
356 | ||
357 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
358 | if (ctx->engine[n].state) | |
bf3783e5 | 359 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 360 | if (ctx->engine[n].ring) |
57e88531 | 361 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
362 | } |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static void print_context_stats(struct seq_file *m, | |
368 | struct drm_i915_private *dev_priv) | |
369 | { | |
36cdd013 | 370 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
371 | struct file_stats stats; |
372 | struct drm_file *file; | |
373 | ||
374 | memset(&stats, 0, sizeof(stats)); | |
375 | ||
36cdd013 | 376 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
377 | if (dev_priv->kernel_context) |
378 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
379 | ||
36cdd013 | 380 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
381 | struct drm_i915_file_private *fpriv = file->driver_priv; |
382 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
383 | } | |
36cdd013 | 384 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
385 | |
386 | print_file_stats(m, "[k]contexts", stats); | |
387 | } | |
388 | ||
36cdd013 | 389 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 390 | { |
36cdd013 DW |
391 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
392 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 393 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
394 | u32 count, mapped_count, purgeable_count, dpy_count; |
395 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 396 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 397 | struct drm_file *file; |
73aa808f CW |
398 | int ret; |
399 | ||
400 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
401 | if (ret) | |
402 | return ret; | |
403 | ||
3ef7f228 | 404 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
405 | dev_priv->mm.object_count, |
406 | dev_priv->mm.object_memory); | |
407 | ||
1544c42e CW |
408 | size = count = 0; |
409 | mapped_size = mapped_count = 0; | |
410 | purgeable_size = purgeable_count = 0; | |
56cea323 | 411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
412 | size += obj->base.size; |
413 | ++count; | |
414 | ||
a4f5ea64 | 415 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
416 | purgeable_size += obj->base.size; |
417 | ++purgeable_count; | |
418 | } | |
419 | ||
a4f5ea64 | 420 | if (obj->mm.mapping) { |
2bd160a1 CW |
421 | mapped_count++; |
422 | mapped_size += obj->base.size; | |
be19b10d | 423 | } |
b7abb714 | 424 | } |
c44ef60e | 425 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 426 | |
2bd160a1 | 427 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 428 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
429 | size += obj->base.size; |
430 | ++count; | |
431 | ||
30154650 | 432 | if (obj->pin_display) { |
2bd160a1 CW |
433 | dpy_size += obj->base.size; |
434 | ++dpy_count; | |
6299f992 | 435 | } |
2bd160a1 | 436 | |
a4f5ea64 | 437 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
438 | purgeable_size += obj->base.size; |
439 | ++purgeable_count; | |
440 | } | |
2bd160a1 | 441 | |
a4f5ea64 | 442 | if (obj->mm.mapping) { |
2bd160a1 CW |
443 | mapped_count++; |
444 | mapped_size += obj->base.size; | |
be19b10d | 445 | } |
6299f992 | 446 | } |
2bd160a1 CW |
447 | seq_printf(m, "%u bound objects, %llu bytes\n", |
448 | count, size); | |
c44ef60e | 449 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 450 | purgeable_count, purgeable_size); |
2bd160a1 CW |
451 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
452 | mapped_count, mapped_size); | |
453 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
454 | dpy_count, dpy_size); | |
6299f992 | 455 | |
c44ef60e | 456 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 457 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 458 | |
493018dc BV |
459 | seq_putc(m, '\n'); |
460 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
461 | mutex_unlock(&dev->struct_mutex); |
462 | ||
463 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 464 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
465 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
466 | struct file_stats stats; | |
c84455b4 CW |
467 | struct drm_i915_file_private *file_priv = file->driver_priv; |
468 | struct drm_i915_gem_request *request; | |
3ec2f427 | 469 | struct task_struct *task; |
2db8e9d6 CW |
470 | |
471 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 472 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 473 | spin_lock(&file->table_lock); |
2db8e9d6 | 474 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 475 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
476 | /* |
477 | * Although we have a valid reference on file->pid, that does | |
478 | * not guarantee that the task_struct who called get_pid() is | |
479 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
480 | * Therefore, we need to protect this ->comm access using RCU. | |
481 | */ | |
c84455b4 CW |
482 | mutex_lock(&dev->struct_mutex); |
483 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
484 | struct drm_i915_gem_request, | |
485 | client_list); | |
3ec2f427 | 486 | rcu_read_lock(); |
c84455b4 CW |
487 | task = pid_task(request && request->ctx->pid ? |
488 | request->ctx->pid : file->pid, | |
489 | PIDTYPE_PID); | |
493018dc | 490 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 491 | rcu_read_unlock(); |
c84455b4 | 492 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 493 | } |
1d2ac403 | 494 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
495 | |
496 | return 0; | |
497 | } | |
498 | ||
aee56cff | 499 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 500 | { |
9f25d007 | 501 | struct drm_info_node *node = m->private; |
36cdd013 DW |
502 | struct drm_i915_private *dev_priv = node_to_i915(node); |
503 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 504 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 505 | struct drm_i915_gem_object *obj; |
c44ef60e | 506 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
507 | int count, ret; |
508 | ||
509 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
510 | if (ret) | |
511 | return ret; | |
512 | ||
513 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 514 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 515 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
516 | continue; |
517 | ||
267f0c90 | 518 | seq_puts(m, " "); |
08c18323 | 519 | describe_obj(m, obj); |
267f0c90 | 520 | seq_putc(m, '\n'); |
08c18323 | 521 | total_obj_size += obj->base.size; |
ca1543be | 522 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
523 | count++; |
524 | } | |
525 | ||
526 | mutex_unlock(&dev->struct_mutex); | |
527 | ||
c44ef60e | 528 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
529 | count, total_obj_size, total_gtt_size); |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
4e5359cd SF |
534 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
535 | { | |
36cdd013 DW |
536 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
537 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 538 | struct intel_crtc *crtc; |
8a270ebf DV |
539 | int ret; |
540 | ||
541 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
542 | if (ret) | |
543 | return ret; | |
4e5359cd | 544 | |
d3fcc808 | 545 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
546 | const char pipe = pipe_name(crtc->pipe); |
547 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 548 | struct intel_flip_work *work; |
4e5359cd | 549 | |
5e2d7afc | 550 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
551 | work = crtc->flip_work; |
552 | if (work == NULL) { | |
9db4a9c7 | 553 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
554 | pipe, plane); |
555 | } else { | |
5a21b665 DV |
556 | u32 pending; |
557 | u32 addr; | |
558 | ||
559 | pending = atomic_read(&work->pending); | |
560 | if (pending) { | |
561 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
562 | pipe, plane); | |
563 | } else { | |
564 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
565 | pipe, plane); | |
566 | } | |
567 | if (work->flip_queued_req) { | |
24327f83 | 568 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 569 | |
312c3c47 | 570 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 571 | engine->name, |
24327f83 | 572 | work->flip_queued_req->global_seqno, |
312c3c47 | 573 | intel_engine_last_submit(engine), |
1b7744e7 | 574 | intel_engine_get_seqno(engine), |
f69a02c9 | 575 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
576 | } else |
577 | seq_printf(m, "Flip not associated with any ring\n"); | |
578 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
579 | work->flip_queued_vblank, | |
580 | work->flip_ready_vblank, | |
581 | intel_crtc_get_vblank_counter(crtc)); | |
582 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
583 | ||
36cdd013 | 584 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
585 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
586 | else | |
587 | addr = I915_READ(DSPADDR(crtc->plane)); | |
588 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
589 | ||
590 | if (work->pending_flip_obj) { | |
591 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
592 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
593 | } |
594 | } | |
5e2d7afc | 595 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
596 | } |
597 | ||
8a270ebf DV |
598 | mutex_unlock(&dev->struct_mutex); |
599 | ||
4e5359cd SF |
600 | return 0; |
601 | } | |
602 | ||
493018dc BV |
603 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
604 | { | |
36cdd013 DW |
605 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
606 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 607 | struct drm_i915_gem_object *obj; |
e2f80391 | 608 | struct intel_engine_cs *engine; |
3b3f1650 | 609 | enum intel_engine_id id; |
8d9d5744 | 610 | int total = 0; |
b4ac5afc | 611 | int ret, j; |
493018dc BV |
612 | |
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
3b3f1650 | 617 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 618 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
619 | int count; |
620 | ||
621 | count = 0; | |
622 | list_for_each_entry(obj, | |
e2f80391 | 623 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
624 | batch_pool_link) |
625 | count++; | |
626 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 627 | engine->name, j, count); |
8d9d5744 CW |
628 | |
629 | list_for_each_entry(obj, | |
e2f80391 | 630 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
631 | batch_pool_link) { |
632 | seq_puts(m, " "); | |
633 | describe_obj(m, obj); | |
634 | seq_putc(m, '\n'); | |
635 | } | |
636 | ||
637 | total += count; | |
06fbca71 | 638 | } |
493018dc BV |
639 | } |
640 | ||
8d9d5744 | 641 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
642 | |
643 | mutex_unlock(&dev->struct_mutex); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
1b36595f CW |
648 | static void print_request(struct seq_file *m, |
649 | struct drm_i915_gem_request *rq, | |
650 | const char *prefix) | |
651 | { | |
20311bd3 | 652 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 653 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 654 | rq->priotree.priority, |
1b36595f | 655 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 656 | rq->timeline->common->name); |
1b36595f CW |
657 | } |
658 | ||
2017263e BG |
659 | static int i915_gem_request_info(struct seq_file *m, void *data) |
660 | { | |
36cdd013 DW |
661 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
662 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 663 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
664 | struct intel_engine_cs *engine; |
665 | enum intel_engine_id id; | |
b4ac5afc | 666 | int ret, any; |
de227ef0 CW |
667 | |
668 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
669 | if (ret) | |
670 | return ret; | |
2017263e | 671 | |
2d1070b2 | 672 | any = 0; |
3b3f1650 | 673 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
674 | int count; |
675 | ||
676 | count = 0; | |
73cb9701 | 677 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
678 | count++; |
679 | if (count == 0) | |
a2c7f6fd CW |
680 | continue; |
681 | ||
e2f80391 | 682 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 683 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 684 | print_request(m, req, " "); |
2d1070b2 CW |
685 | |
686 | any++; | |
2017263e | 687 | } |
de227ef0 CW |
688 | mutex_unlock(&dev->struct_mutex); |
689 | ||
2d1070b2 | 690 | if (any == 0) |
267f0c90 | 691 | seq_puts(m, "No requests\n"); |
c2c347a9 | 692 | |
2017263e BG |
693 | return 0; |
694 | } | |
695 | ||
b2223497 | 696 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 697 | struct intel_engine_cs *engine) |
b2223497 | 698 | { |
688e6c72 CW |
699 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
700 | struct rb_node *rb; | |
701 | ||
12471ba8 | 702 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 703 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 704 | |
f6168e33 | 705 | spin_lock_irq(&b->lock); |
688e6c72 | 706 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 707 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
708 | |
709 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
710 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
711 | } | |
f6168e33 | 712 | spin_unlock_irq(&b->lock); |
b2223497 CW |
713 | } |
714 | ||
2017263e BG |
715 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
716 | { | |
36cdd013 | 717 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 718 | struct intel_engine_cs *engine; |
3b3f1650 | 719 | enum intel_engine_id id; |
2017263e | 720 | |
3b3f1650 | 721 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 722 | i915_ring_seqno_info(m, engine); |
de227ef0 | 723 | |
2017263e BG |
724 | return 0; |
725 | } | |
726 | ||
727 | ||
728 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
729 | { | |
36cdd013 | 730 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 731 | struct intel_engine_cs *engine; |
3b3f1650 | 732 | enum intel_engine_id id; |
4bb05040 | 733 | int i, pipe; |
de227ef0 | 734 | |
c8c8fb33 | 735 | intel_runtime_pm_get(dev_priv); |
2017263e | 736 | |
36cdd013 | 737 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
738 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
739 | I915_READ(GEN8_MASTER_IRQ)); | |
740 | ||
741 | seq_printf(m, "Display IER:\t%08x\n", | |
742 | I915_READ(VLV_IER)); | |
743 | seq_printf(m, "Display IIR:\t%08x\n", | |
744 | I915_READ(VLV_IIR)); | |
745 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
746 | I915_READ(VLV_IIR_RW)); | |
747 | seq_printf(m, "Display IMR:\t%08x\n", | |
748 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
749 | for_each_pipe(dev_priv, pipe) { |
750 | enum intel_display_power_domain power_domain; | |
751 | ||
752 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
753 | if (!intel_display_power_get_if_enabled(dev_priv, | |
754 | power_domain)) { | |
755 | seq_printf(m, "Pipe %c power disabled\n", | |
756 | pipe_name(pipe)); | |
757 | continue; | |
758 | } | |
759 | ||
74e1ca8c VS |
760 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
761 | pipe_name(pipe), | |
762 | I915_READ(PIPESTAT(pipe))); | |
763 | ||
9c870d03 CW |
764 | intel_display_power_put(dev_priv, power_domain); |
765 | } | |
766 | ||
767 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
768 | seq_printf(m, "Port hotplug:\t%08x\n", |
769 | I915_READ(PORT_HOTPLUG_EN)); | |
770 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
771 | I915_READ(VLV_DPFLIPSTAT)); | |
772 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
773 | I915_READ(DPINVGTT)); | |
9c870d03 | 774 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
775 | |
776 | for (i = 0; i < 4; i++) { | |
777 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
778 | i, I915_READ(GEN8_GT_IMR(i))); | |
779 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
780 | i, I915_READ(GEN8_GT_IIR(i))); | |
781 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
782 | i, I915_READ(GEN8_GT_IER(i))); | |
783 | } | |
784 | ||
785 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
786 | I915_READ(GEN8_PCU_IMR)); | |
787 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
788 | I915_READ(GEN8_PCU_IIR)); | |
789 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
790 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 791 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
792 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
793 | I915_READ(GEN8_MASTER_IRQ)); | |
794 | ||
795 | for (i = 0; i < 4; i++) { | |
796 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
797 | i, I915_READ(GEN8_GT_IMR(i))); | |
798 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
799 | i, I915_READ(GEN8_GT_IIR(i))); | |
800 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
801 | i, I915_READ(GEN8_GT_IER(i))); | |
802 | } | |
803 | ||
055e393f | 804 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
805 | enum intel_display_power_domain power_domain; |
806 | ||
807 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
808 | if (!intel_display_power_get_if_enabled(dev_priv, | |
809 | power_domain)) { | |
22c59960 PZ |
810 | seq_printf(m, "Pipe %c power disabled\n", |
811 | pipe_name(pipe)); | |
812 | continue; | |
813 | } | |
a123f157 | 814 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
815 | pipe_name(pipe), |
816 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 817 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
818 | pipe_name(pipe), |
819 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 820 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
821 | pipe_name(pipe), |
822 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
823 | |
824 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
825 | } |
826 | ||
827 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
828 | I915_READ(GEN8_DE_PORT_IMR)); | |
829 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
830 | I915_READ(GEN8_DE_PORT_IIR)); | |
831 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
832 | I915_READ(GEN8_DE_PORT_IER)); | |
833 | ||
834 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
835 | I915_READ(GEN8_DE_MISC_IMR)); | |
836 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
837 | I915_READ(GEN8_DE_MISC_IIR)); | |
838 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
839 | I915_READ(GEN8_DE_MISC_IER)); | |
840 | ||
841 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
842 | I915_READ(GEN8_PCU_IMR)); | |
843 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
844 | I915_READ(GEN8_PCU_IIR)); | |
845 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
846 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 847 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
848 | seq_printf(m, "Display IER:\t%08x\n", |
849 | I915_READ(VLV_IER)); | |
850 | seq_printf(m, "Display IIR:\t%08x\n", | |
851 | I915_READ(VLV_IIR)); | |
852 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
853 | I915_READ(VLV_IIR_RW)); | |
854 | seq_printf(m, "Display IMR:\t%08x\n", | |
855 | I915_READ(VLV_IMR)); | |
055e393f | 856 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
857 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
858 | pipe_name(pipe), | |
859 | I915_READ(PIPESTAT(pipe))); | |
860 | ||
861 | seq_printf(m, "Master IER:\t%08x\n", | |
862 | I915_READ(VLV_MASTER_IER)); | |
863 | ||
864 | seq_printf(m, "Render IER:\t%08x\n", | |
865 | I915_READ(GTIER)); | |
866 | seq_printf(m, "Render IIR:\t%08x\n", | |
867 | I915_READ(GTIIR)); | |
868 | seq_printf(m, "Render IMR:\t%08x\n", | |
869 | I915_READ(GTIMR)); | |
870 | ||
871 | seq_printf(m, "PM IER:\t\t%08x\n", | |
872 | I915_READ(GEN6_PMIER)); | |
873 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
874 | I915_READ(GEN6_PMIIR)); | |
875 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
876 | I915_READ(GEN6_PMIMR)); | |
877 | ||
878 | seq_printf(m, "Port hotplug:\t%08x\n", | |
879 | I915_READ(PORT_HOTPLUG_EN)); | |
880 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
881 | I915_READ(VLV_DPFLIPSTAT)); | |
882 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
883 | I915_READ(DPINVGTT)); | |
884 | ||
36cdd013 | 885 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
886 | seq_printf(m, "Interrupt enable: %08x\n", |
887 | I915_READ(IER)); | |
888 | seq_printf(m, "Interrupt identity: %08x\n", | |
889 | I915_READ(IIR)); | |
890 | seq_printf(m, "Interrupt mask: %08x\n", | |
891 | I915_READ(IMR)); | |
055e393f | 892 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
893 | seq_printf(m, "Pipe %c stat: %08x\n", |
894 | pipe_name(pipe), | |
895 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
896 | } else { |
897 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
898 | I915_READ(DEIER)); | |
899 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
900 | I915_READ(DEIIR)); | |
901 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
902 | I915_READ(DEIMR)); | |
903 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
904 | I915_READ(SDEIER)); | |
905 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
906 | I915_READ(SDEIIR)); | |
907 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
908 | I915_READ(SDEIMR)); | |
909 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
910 | I915_READ(GTIER)); | |
911 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
912 | I915_READ(GTIIR)); | |
913 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
914 | I915_READ(GTIMR)); | |
915 | } | |
3b3f1650 | 916 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 917 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
918 | seq_printf(m, |
919 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 920 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 921 | } |
e2f80391 | 922 | i915_ring_seqno_info(m, engine); |
9862e600 | 923 | } |
c8c8fb33 | 924 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 925 | |
2017263e BG |
926 | return 0; |
927 | } | |
928 | ||
a6172a80 CW |
929 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
930 | { | |
36cdd013 DW |
931 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
932 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
933 | int i, ret; |
934 | ||
935 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
936 | if (ret) | |
937 | return ret; | |
a6172a80 | 938 | |
a6172a80 CW |
939 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
940 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 941 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 942 | |
6c085a72 CW |
943 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
944 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 945 | if (!vma) |
267f0c90 | 946 | seq_puts(m, "unused"); |
c2c347a9 | 947 | else |
49ef5294 | 948 | describe_obj(m, vma->obj); |
267f0c90 | 949 | seq_putc(m, '\n'); |
a6172a80 CW |
950 | } |
951 | ||
05394f39 | 952 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
953 | return 0; |
954 | } | |
955 | ||
98a2f411 CW |
956 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
957 | ||
d5442303 DV |
958 | static ssize_t |
959 | i915_error_state_write(struct file *filp, | |
960 | const char __user *ubuf, | |
961 | size_t cnt, | |
962 | loff_t *ppos) | |
963 | { | |
edc3d884 | 964 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
965 | |
966 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
12ff05e7 | 967 | i915_destroy_error_state(error_priv->i915); |
d5442303 DV |
968 | |
969 | return cnt; | |
970 | } | |
971 | ||
972 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
973 | { | |
36cdd013 | 974 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 975 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
976 | |
977 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
978 | if (!error_priv) | |
979 | return -ENOMEM; | |
980 | ||
12ff05e7 | 981 | error_priv->i915 = dev_priv; |
d5442303 | 982 | |
36cdd013 | 983 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 984 | |
edc3d884 MK |
985 | file->private_data = error_priv; |
986 | ||
987 | return 0; | |
d5442303 DV |
988 | } |
989 | ||
990 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
991 | { | |
edc3d884 | 992 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 993 | |
95d5bfb3 | 994 | i915_error_state_put(error_priv); |
d5442303 DV |
995 | kfree(error_priv); |
996 | ||
edc3d884 MK |
997 | return 0; |
998 | } | |
999 | ||
4dc955f7 MK |
1000 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1001 | size_t count, loff_t *pos) | |
1002 | { | |
1003 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1004 | struct drm_i915_error_state_buf error_str; | |
1005 | loff_t tmp_pos = 0; | |
1006 | ssize_t ret_count = 0; | |
1007 | int ret; | |
1008 | ||
12ff05e7 TU |
1009 | ret = i915_error_state_buf_init(&error_str, error_priv->i915, |
1010 | count, *pos); | |
4dc955f7 MK |
1011 | if (ret) |
1012 | return ret; | |
edc3d884 | 1013 | |
fc16b48b | 1014 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1015 | if (ret) |
1016 | goto out; | |
1017 | ||
edc3d884 MK |
1018 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1019 | error_str.buf, | |
1020 | error_str.bytes); | |
1021 | ||
1022 | if (ret_count < 0) | |
1023 | ret = ret_count; | |
1024 | else | |
1025 | *pos = error_str.start + ret_count; | |
1026 | out: | |
4dc955f7 | 1027 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1028 | return ret ?: ret_count; |
d5442303 DV |
1029 | } |
1030 | ||
1031 | static const struct file_operations i915_error_state_fops = { | |
1032 | .owner = THIS_MODULE, | |
1033 | .open = i915_error_state_open, | |
edc3d884 | 1034 | .read = i915_error_state_read, |
d5442303 DV |
1035 | .write = i915_error_state_write, |
1036 | .llseek = default_llseek, | |
1037 | .release = i915_error_state_release, | |
1038 | }; | |
1039 | ||
98a2f411 CW |
1040 | #endif |
1041 | ||
647416f9 KC |
1042 | static int |
1043 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1044 | { |
36cdd013 | 1045 | struct drm_i915_private *dev_priv = data; |
40633219 | 1046 | |
4c266edb | 1047 | *val = 1 + atomic_read(&dev_priv->gt.global_timeline.seqno); |
647416f9 | 1048 | return 0; |
40633219 MK |
1049 | } |
1050 | ||
647416f9 KC |
1051 | static int |
1052 | i915_next_seqno_set(void *data, u64 val) | |
1053 | { | |
36cdd013 DW |
1054 | struct drm_i915_private *dev_priv = data; |
1055 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1056 | int ret; |
1057 | ||
40633219 MK |
1058 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1059 | if (ret) | |
1060 | return ret; | |
1061 | ||
73cb9701 | 1062 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1063 | mutex_unlock(&dev->struct_mutex); |
1064 | ||
647416f9 | 1065 | return ret; |
40633219 MK |
1066 | } |
1067 | ||
647416f9 KC |
1068 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1069 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1070 | "0x%llx\n"); |
40633219 | 1071 | |
adb4bd12 | 1072 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1073 | { |
36cdd013 DW |
1074 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1075 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1076 | int ret = 0; |
1077 | ||
1078 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1079 | |
36cdd013 | 1080 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1081 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1082 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1083 | ||
1084 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1085 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1086 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1087 | MEMSTAT_VID_SHIFT); | |
1088 | seq_printf(m, "Current P-state: %d\n", | |
1089 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1090 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1091 | u32 freq_sts; |
1092 | ||
1093 | mutex_lock(&dev_priv->rps.hw_lock); | |
1094 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1095 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1096 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1097 | ||
1098 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1099 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1100 | ||
1101 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1102 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1103 | ||
1104 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1105 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1106 | ||
1107 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1108 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1109 | ||
1110 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1111 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1112 | ||
1113 | seq_printf(m, | |
1114 | "efficient (RPe) frequency: %d MHz\n", | |
1115 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1116 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1117 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1118 | u32 rp_state_limits; |
1119 | u32 gt_perf_status; | |
1120 | u32 rp_state_cap; | |
0d8f9491 | 1121 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1122 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1123 | u32 rpupei, rpcurup, rpprevup; |
1124 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1125 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1126 | int max_freq; |
1127 | ||
35040562 | 1128 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1129 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1130 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1131 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1132 | } else { | |
1133 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1134 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1135 | } | |
1136 | ||
3b8d8d91 | 1137 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1138 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1139 | if (ret) | |
c8c8fb33 | 1140 | goto out; |
d1ebd816 | 1141 | |
59bad947 | 1142 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1143 | |
8e8c06cd | 1144 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1145 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1146 | reqf >>= 23; |
1147 | else { | |
1148 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1149 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1150 | reqf >>= 24; |
1151 | else | |
1152 | reqf >>= 25; | |
1153 | } | |
7c59a9c1 | 1154 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1155 | |
0d8f9491 CW |
1156 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1157 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1158 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1159 | ||
ccab5c82 | 1160 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1161 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1162 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1163 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1164 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1165 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1166 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1167 | if (IS_GEN9(dev_priv)) |
60260a5b | 1168 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1169 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1170 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1171 | else | |
1172 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1173 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1174 | |
59bad947 | 1175 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1176 | mutex_unlock(&dev->struct_mutex); |
1177 | ||
36cdd013 | 1178 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1179 | pm_ier = I915_READ(GEN6_PMIER); |
1180 | pm_imr = I915_READ(GEN6_PMIMR); | |
1181 | pm_isr = I915_READ(GEN6_PMISR); | |
1182 | pm_iir = I915_READ(GEN6_PMIIR); | |
1183 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1184 | } else { | |
1185 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1186 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1187 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1188 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1189 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1190 | } | |
0d8f9491 | 1191 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1192 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1193 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1194 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1195 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1196 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1197 | seq_printf(m, "Render p-state VID: %d\n", |
1198 | gt_perf_status & 0xff); | |
1199 | seq_printf(m, "Render p-state limit: %d\n", | |
1200 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1201 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1202 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1203 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1204 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1205 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1206 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1207 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1208 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1209 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1210 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1211 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1212 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1213 | seq_printf(m, "Up threshold: %d%%\n", |
1214 | dev_priv->rps.up_threshold); | |
1215 | ||
d6cda9c7 AG |
1216 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1217 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1218 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1219 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1220 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1221 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1222 | seq_printf(m, "Down threshold: %d%%\n", |
1223 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1224 | |
cc3f90f0 | 1225 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1226 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1227 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1228 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1229 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1230 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1231 | |
1232 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1233 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1234 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1235 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1236 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1237 | |
cc3f90f0 | 1238 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1239 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1240 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1241 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1242 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1243 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1244 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1245 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1246 | |
d86ed34a CW |
1247 | seq_printf(m, "Current freq: %d MHz\n", |
1248 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1249 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1250 | seq_printf(m, "Idle freq: %d MHz\n", |
1251 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1252 | seq_printf(m, "Min freq: %d MHz\n", |
1253 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1254 | seq_printf(m, "Boost freq: %d MHz\n", |
1255 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1256 | seq_printf(m, "Max freq: %d MHz\n", |
1257 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1258 | seq_printf(m, | |
1259 | "efficient (RPe) frequency: %d MHz\n", | |
1260 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1261 | } else { |
267f0c90 | 1262 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1263 | } |
f97108d1 | 1264 | |
1170f28c MK |
1265 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1266 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1267 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1268 | ||
c8c8fb33 PZ |
1269 | out: |
1270 | intel_runtime_pm_put(dev_priv); | |
1271 | return ret; | |
f97108d1 JB |
1272 | } |
1273 | ||
d636951e BW |
1274 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1275 | struct seq_file *m, | |
1276 | struct intel_instdone *instdone) | |
1277 | { | |
f9e61372 BW |
1278 | int slice; |
1279 | int subslice; | |
1280 | ||
d636951e BW |
1281 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1282 | instdone->instdone); | |
1283 | ||
1284 | if (INTEL_GEN(dev_priv) <= 3) | |
1285 | return; | |
1286 | ||
1287 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1288 | instdone->slice_common); | |
1289 | ||
1290 | if (INTEL_GEN(dev_priv) <= 6) | |
1291 | return; | |
1292 | ||
f9e61372 BW |
1293 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1294 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1295 | slice, subslice, instdone->sampler[slice][subslice]); | |
1296 | ||
1297 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1298 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1299 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1300 | } |
1301 | ||
f654449a CW |
1302 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1303 | { | |
36cdd013 | 1304 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1305 | struct intel_engine_cs *engine; |
666796da TU |
1306 | u64 acthd[I915_NUM_ENGINES]; |
1307 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1308 | struct intel_instdone instdone; |
c3232b18 | 1309 | enum intel_engine_id id; |
f654449a | 1310 | |
8af29b0c CW |
1311 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1312 | seq_printf(m, "Wedged\n"); | |
1313 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1314 | seq_printf(m, "Reset in progress\n"); | |
1315 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1316 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1317 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1318 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1319 | ||
f654449a CW |
1320 | if (!i915.enable_hangcheck) { |
1321 | seq_printf(m, "Hangcheck disabled\n"); | |
1322 | return 0; | |
1323 | } | |
1324 | ||
ebbc7546 MK |
1325 | intel_runtime_pm_get(dev_priv); |
1326 | ||
3b3f1650 | 1327 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1328 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1329 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1330 | } |
1331 | ||
3b3f1650 | 1332 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1333 | |
ebbc7546 MK |
1334 | intel_runtime_pm_put(dev_priv); |
1335 | ||
f654449a CW |
1336 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1337 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1338 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1339 | jiffies)); | |
1340 | } else | |
1341 | seq_printf(m, "Hangcheck inactive\n"); | |
1342 | ||
3b3f1650 | 1343 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1344 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1345 | struct rb_node *rb; | |
1346 | ||
e2f80391 | 1347 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d | 1348 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
cb399eab CW |
1349 | engine->hangcheck.seqno, seqno[id], |
1350 | intel_engine_last_submit(engine)); | |
3fe3b030 | 1351 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1352 | yesno(intel_engine_has_waiter(engine)), |
1353 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1354 | &dev_priv->gpu_error.missed_irq_rings)), |
1355 | yesno(engine->hangcheck.stalled)); | |
1356 | ||
f6168e33 | 1357 | spin_lock_irq(&b->lock); |
33f53719 | 1358 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1359 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1360 | |
1361 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1362 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1363 | } | |
f6168e33 | 1364 | spin_unlock_irq(&b->lock); |
33f53719 | 1365 | |
f654449a | 1366 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1367 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1368 | (long long)acthd[id]); |
3fe3b030 MK |
1369 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1370 | hangcheck_action_to_str(engine->hangcheck.action), | |
1371 | engine->hangcheck.action, | |
1372 | jiffies_to_msecs(jiffies - | |
1373 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1374 | |
e2f80391 | 1375 | if (engine->id == RCS) { |
d636951e | 1376 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1377 | |
d636951e | 1378 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1379 | |
d636951e | 1380 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1381 | |
d636951e BW |
1382 | i915_instdone_info(dev_priv, m, |
1383 | &engine->hangcheck.instdone); | |
61642ff0 | 1384 | } |
f654449a CW |
1385 | } |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
4d85529d | 1390 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1391 | { |
36cdd013 | 1392 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1393 | u32 rgvmodectl, rstdbyctl; |
1394 | u16 crstandvid; | |
616fdb5a | 1395 | |
c8c8fb33 | 1396 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1397 | |
1398 | rgvmodectl = I915_READ(MEMMODECTL); | |
1399 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1400 | crstandvid = I915_READ16(CRSTANDVID); | |
1401 | ||
c8c8fb33 | 1402 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1403 | |
742f491d | 1404 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1405 | seq_printf(m, "Boost freq: %d\n", |
1406 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1407 | MEMMODE_BOOST_FREQ_SHIFT); | |
1408 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1409 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1410 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1411 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1412 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1413 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1414 | seq_printf(m, "Starting frequency: P%d\n", |
1415 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1416 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1417 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1418 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1419 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1420 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1421 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1422 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1423 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1424 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1425 | case RSX_STATUS_ON: | |
267f0c90 | 1426 | seq_puts(m, "on\n"); |
88271da3 JB |
1427 | break; |
1428 | case RSX_STATUS_RC1: | |
267f0c90 | 1429 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1430 | break; |
1431 | case RSX_STATUS_RC1E: | |
267f0c90 | 1432 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1433 | break; |
1434 | case RSX_STATUS_RS1: | |
267f0c90 | 1435 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1436 | break; |
1437 | case RSX_STATUS_RS2: | |
267f0c90 | 1438 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1439 | break; |
1440 | case RSX_STATUS_RS3: | |
267f0c90 | 1441 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1442 | break; |
1443 | default: | |
267f0c90 | 1444 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1445 | break; |
1446 | } | |
f97108d1 JB |
1447 | |
1448 | return 0; | |
1449 | } | |
1450 | ||
f65367b5 | 1451 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1452 | { |
36cdd013 | 1453 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1454 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1455 | |
1456 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1457 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1458 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1459 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1460 | fw_domain->wake_count); |
1461 | } | |
1462 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1463 | |
b2cff0db CW |
1464 | return 0; |
1465 | } | |
1466 | ||
1467 | static int vlv_drpc_info(struct seq_file *m) | |
1468 | { | |
36cdd013 | 1469 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1470 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1471 | |
d46c0517 ID |
1472 | intel_runtime_pm_get(dev_priv); |
1473 | ||
6b312cd3 | 1474 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1475 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1476 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1477 | ||
d46c0517 ID |
1478 | intel_runtime_pm_put(dev_priv); |
1479 | ||
669ab5aa D |
1480 | seq_printf(m, "Video Turbo Mode: %s\n", |
1481 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1482 | seq_printf(m, "Turbo enabled: %s\n", | |
1483 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1484 | seq_printf(m, "HW control enabled: %s\n", | |
1485 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1486 | seq_printf(m, "SW control enabled: %s\n", | |
1487 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1488 | GEN6_RP_MEDIA_SW_MODE)); | |
1489 | seq_printf(m, "RC6 Enabled: %s\n", | |
1490 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1491 | GEN6_RC_CTL_EI_MODE(1)))); | |
1492 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1493 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1494 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1495 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1496 | |
9cc19be5 ID |
1497 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1498 | I915_READ(VLV_GT_RENDER_RC6)); | |
1499 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1500 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1501 | ||
f65367b5 | 1502 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1503 | } |
1504 | ||
4d85529d BW |
1505 | static int gen6_drpc_info(struct seq_file *m) |
1506 | { | |
36cdd013 DW |
1507 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1508 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1509 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1510 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1511 | unsigned forcewake_count; |
aee56cff | 1512 | int count = 0, ret; |
4d85529d BW |
1513 | |
1514 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1515 | if (ret) | |
1516 | return ret; | |
c8c8fb33 | 1517 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1518 | |
907b28c5 | 1519 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1520 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1521 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1522 | |
1523 | if (forcewake_count) { | |
267f0c90 DL |
1524 | seq_puts(m, "RC information inaccurate because somebody " |
1525 | "holds a forcewake reference \n"); | |
4d85529d BW |
1526 | } else { |
1527 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1528 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1529 | udelay(10); | |
1530 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1531 | } | |
1532 | ||
75aa3f63 | 1533 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1534 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1535 | |
1536 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1537 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1538 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1539 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1540 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1541 | } | |
4d85529d | 1542 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1543 | mutex_lock(&dev_priv->rps.hw_lock); |
1544 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1545 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1546 | |
c8c8fb33 PZ |
1547 | intel_runtime_pm_put(dev_priv); |
1548 | ||
4d85529d BW |
1549 | seq_printf(m, "Video Turbo Mode: %s\n", |
1550 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1551 | seq_printf(m, "HW control enabled: %s\n", | |
1552 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1553 | seq_printf(m, "SW control enabled: %s\n", | |
1554 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1555 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1556 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1557 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1558 | seq_printf(m, "RC6 Enabled: %s\n", | |
1559 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1560 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1561 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1562 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1563 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1564 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1565 | } | |
4d85529d BW |
1566 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1567 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1568 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1569 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1570 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1571 | switch (gt_core_status & GEN6_RCn_MASK) { |
1572 | case GEN6_RC0: | |
1573 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1574 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1575 | else |
267f0c90 | 1576 | seq_puts(m, "on\n"); |
4d85529d BW |
1577 | break; |
1578 | case GEN6_RC3: | |
267f0c90 | 1579 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1580 | break; |
1581 | case GEN6_RC6: | |
267f0c90 | 1582 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1583 | break; |
1584 | case GEN6_RC7: | |
267f0c90 | 1585 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1586 | break; |
1587 | default: | |
267f0c90 | 1588 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1589 | break; |
1590 | } | |
1591 | ||
1592 | seq_printf(m, "Core Power Down: %s\n", | |
1593 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1594 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1595 | seq_printf(m, "Render Power Well: %s\n", |
1596 | (gen9_powergate_status & | |
1597 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1598 | seq_printf(m, "Media Power Well: %s\n", | |
1599 | (gen9_powergate_status & | |
1600 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1601 | } | |
cce66a28 BW |
1602 | |
1603 | /* Not exactly sure what this is */ | |
1604 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1605 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1606 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1607 | I915_READ(GEN6_GT_GFX_RC6)); | |
1608 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1609 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1610 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1611 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1612 | ||
ecd8faea BW |
1613 | seq_printf(m, "RC6 voltage: %dmV\n", |
1614 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1615 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1616 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1617 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1618 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1619 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1620 | } |
1621 | ||
1622 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1623 | { | |
36cdd013 | 1624 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1625 | |
36cdd013 | 1626 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1627 | return vlv_drpc_info(m); |
36cdd013 | 1628 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1629 | return gen6_drpc_info(m); |
1630 | else | |
1631 | return ironlake_drpc_info(m); | |
1632 | } | |
1633 | ||
9a851789 DV |
1634 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1635 | { | |
36cdd013 | 1636 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1637 | |
1638 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1639 | dev_priv->fb_tracking.busy_bits); | |
1640 | ||
1641 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1642 | dev_priv->fb_tracking.flip_bits); | |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | ||
b5e50c3f JB |
1647 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1648 | { | |
36cdd013 | 1649 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1650 | |
36cdd013 | 1651 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1652 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1653 | return 0; |
1654 | } | |
1655 | ||
36623ef8 | 1656 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1657 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1658 | |
0e631adc | 1659 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1660 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1661 | else |
1662 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1663 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1664 | |
0fc6a9dc PZ |
1665 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1666 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1667 | BDW_FBC_COMPRESSION_MASK : | |
1668 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1669 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1670 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1671 | } | |
31b9df10 | 1672 | |
25ad93fd | 1673 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1674 | intel_runtime_pm_put(dev_priv); |
1675 | ||
b5e50c3f JB |
1676 | return 0; |
1677 | } | |
1678 | ||
da46f936 RV |
1679 | static int i915_fbc_fc_get(void *data, u64 *val) |
1680 | { | |
36cdd013 | 1681 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1682 | |
36cdd013 | 1683 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1684 | return -ENODEV; |
1685 | ||
da46f936 | 1686 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1687 | |
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | static int i915_fbc_fc_set(void *data, u64 val) | |
1692 | { | |
36cdd013 | 1693 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1694 | u32 reg; |
1695 | ||
36cdd013 | 1696 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1697 | return -ENODEV; |
1698 | ||
25ad93fd | 1699 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1700 | |
1701 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1702 | dev_priv->fbc.false_color = val; | |
1703 | ||
1704 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1705 | (reg | FBC_CTL_FALSE_COLOR) : | |
1706 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1707 | ||
25ad93fd | 1708 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1709 | return 0; |
1710 | } | |
1711 | ||
1712 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1713 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1714 | "%llu\n"); | |
1715 | ||
92d44621 PZ |
1716 | static int i915_ips_status(struct seq_file *m, void *unused) |
1717 | { | |
36cdd013 | 1718 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1719 | |
36cdd013 | 1720 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1721 | seq_puts(m, "not supported\n"); |
1722 | return 0; | |
1723 | } | |
1724 | ||
36623ef8 PZ |
1725 | intel_runtime_pm_get(dev_priv); |
1726 | ||
0eaa53f0 RV |
1727 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1728 | yesno(i915.enable_ips)); | |
1729 | ||
36cdd013 | 1730 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1731 | seq_puts(m, "Currently: unknown\n"); |
1732 | } else { | |
1733 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1734 | seq_puts(m, "Currently: enabled\n"); | |
1735 | else | |
1736 | seq_puts(m, "Currently: disabled\n"); | |
1737 | } | |
92d44621 | 1738 | |
36623ef8 PZ |
1739 | intel_runtime_pm_put(dev_priv); |
1740 | ||
92d44621 PZ |
1741 | return 0; |
1742 | } | |
1743 | ||
4a9bef37 JB |
1744 | static int i915_sr_status(struct seq_file *m, void *unused) |
1745 | { | |
36cdd013 | 1746 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1747 | bool sr_enabled = false; |
1748 | ||
36623ef8 | 1749 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1750 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1751 | |
36cdd013 | 1752 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1753 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1754 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1755 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1756 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1757 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1758 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1759 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1760 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1761 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1762 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1763 | |
9c870d03 | 1764 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1765 | intel_runtime_pm_put(dev_priv); |
1766 | ||
08c4d7fc | 1767 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1768 | |
1769 | return 0; | |
1770 | } | |
1771 | ||
7648fa99 JB |
1772 | static int i915_emon_status(struct seq_file *m, void *unused) |
1773 | { | |
36cdd013 DW |
1774 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1775 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1776 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1777 | int ret; |
1778 | ||
36cdd013 | 1779 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1780 | return -ENODEV; |
1781 | ||
de227ef0 CW |
1782 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1783 | if (ret) | |
1784 | return ret; | |
7648fa99 JB |
1785 | |
1786 | temp = i915_mch_val(dev_priv); | |
1787 | chipset = i915_chipset_val(dev_priv); | |
1788 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1789 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1790 | |
1791 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1792 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1793 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1794 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
23b2f8bb JB |
1799 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1800 | { | |
36cdd013 | 1801 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1802 | int ret = 0; |
23b2f8bb | 1803 | int gpu_freq, ia_freq; |
f936ec34 | 1804 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1805 | |
26310346 | 1806 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1807 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1808 | return 0; |
1809 | } | |
1810 | ||
5bfa0199 PZ |
1811 | intel_runtime_pm_get(dev_priv); |
1812 | ||
4fc688ce | 1813 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1814 | if (ret) |
5bfa0199 | 1815 | goto out; |
23b2f8bb | 1816 | |
36cdd013 | 1817 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1818 | /* Convert GT frequency to 50 HZ units */ |
1819 | min_gpu_freq = | |
1820 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1821 | max_gpu_freq = | |
1822 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1823 | } else { | |
1824 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1825 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1826 | } | |
1827 | ||
267f0c90 | 1828 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1829 | |
f936ec34 | 1830 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1831 | ia_freq = gpu_freq; |
1832 | sandybridge_pcode_read(dev_priv, | |
1833 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1834 | &ia_freq); | |
3ebecd07 | 1835 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1836 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1837 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1838 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1839 | ((ia_freq >> 0) & 0xff) * 100, |
1840 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1841 | } |
1842 | ||
4fc688ce | 1843 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1844 | |
5bfa0199 PZ |
1845 | out: |
1846 | intel_runtime_pm_put(dev_priv); | |
1847 | return ret; | |
23b2f8bb JB |
1848 | } |
1849 | ||
44834a67 CW |
1850 | static int i915_opregion(struct seq_file *m, void *unused) |
1851 | { | |
36cdd013 DW |
1852 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1853 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1854 | struct intel_opregion *opregion = &dev_priv->opregion; |
1855 | int ret; | |
1856 | ||
1857 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1858 | if (ret) | |
0d38f009 | 1859 | goto out; |
44834a67 | 1860 | |
2455a8e4 JN |
1861 | if (opregion->header) |
1862 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1863 | |
1864 | mutex_unlock(&dev->struct_mutex); | |
1865 | ||
0d38f009 | 1866 | out: |
44834a67 CW |
1867 | return 0; |
1868 | } | |
1869 | ||
ada8f955 JN |
1870 | static int i915_vbt(struct seq_file *m, void *unused) |
1871 | { | |
36cdd013 | 1872 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1873 | |
1874 | if (opregion->vbt) | |
1875 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1876 | ||
1877 | return 0; | |
1878 | } | |
1879 | ||
37811fcc CW |
1880 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1881 | { | |
36cdd013 DW |
1882 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1883 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1884 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1885 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1886 | int ret; |
1887 | ||
1888 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1889 | if (ret) | |
1890 | return ret; | |
37811fcc | 1891 | |
0695726e | 1892 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1893 | if (dev_priv->fbdev) { |
1894 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1895 | |
1896 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1897 | fbdev_fb->base.width, | |
1898 | fbdev_fb->base.height, | |
b00c600e | 1899 | fbdev_fb->base.format->depth, |
272725c7 | 1900 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1901 | fbdev_fb->base.modifier, |
25bcce94 CW |
1902 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1903 | describe_obj(m, fbdev_fb->obj); | |
1904 | seq_putc(m, '\n'); | |
1905 | } | |
4520f53a | 1906 | #endif |
37811fcc | 1907 | |
4b096ac1 | 1908 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1909 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1910 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1911 | if (fb == fbdev_fb) | |
37811fcc CW |
1912 | continue; |
1913 | ||
c1ca506d | 1914 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1915 | fb->base.width, |
1916 | fb->base.height, | |
b00c600e | 1917 | fb->base.format->depth, |
272725c7 | 1918 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1919 | fb->base.modifier, |
747a598f | 1920 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1921 | describe_obj(m, fb->obj); |
267f0c90 | 1922 | seq_putc(m, '\n'); |
37811fcc | 1923 | } |
4b096ac1 | 1924 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1925 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1926 | |
1927 | return 0; | |
1928 | } | |
1929 | ||
7e37f889 | 1930 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1931 | { |
1932 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1933 | ring->space, ring->head, ring->tail, |
1934 | ring->last_retired_head); | |
c9fe99bd OM |
1935 | } |
1936 | ||
e76d3630 BW |
1937 | static int i915_context_status(struct seq_file *m, void *unused) |
1938 | { | |
36cdd013 DW |
1939 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1940 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1941 | struct intel_engine_cs *engine; |
e2efd130 | 1942 | struct i915_gem_context *ctx; |
3b3f1650 | 1943 | enum intel_engine_id id; |
c3232b18 | 1944 | int ret; |
e76d3630 | 1945 | |
f3d28878 | 1946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1947 | if (ret) |
1948 | return ret; | |
1949 | ||
a33afea5 | 1950 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1951 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1952 | if (ctx->pid) { |
d28b99ab CW |
1953 | struct task_struct *task; |
1954 | ||
c84455b4 | 1955 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1956 | if (task) { |
1957 | seq_printf(m, "(%s [%d]) ", | |
1958 | task->comm, task->pid); | |
1959 | put_task_struct(task); | |
1960 | } | |
c84455b4 CW |
1961 | } else if (IS_ERR(ctx->file_priv)) { |
1962 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1963 | } else { |
1964 | seq_puts(m, "(kernel) "); | |
1965 | } | |
1966 | ||
bca44d80 CW |
1967 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1968 | seq_putc(m, '\n'); | |
c9fe99bd | 1969 | |
3b3f1650 | 1970 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1971 | struct intel_context *ce = &ctx->engine[engine->id]; |
1972 | ||
1973 | seq_printf(m, "%s: ", engine->name); | |
1974 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1975 | if (ce->state) | |
bf3783e5 | 1976 | describe_obj(m, ce->state->obj); |
dca33ecc | 1977 | if (ce->ring) |
7e37f889 | 1978 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1979 | seq_putc(m, '\n'); |
c9fe99bd | 1980 | } |
a33afea5 | 1981 | |
a33afea5 | 1982 | seq_putc(m, '\n'); |
a168c293 BW |
1983 | } |
1984 | ||
f3d28878 | 1985 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1986 | |
1987 | return 0; | |
1988 | } | |
1989 | ||
064ca1d2 | 1990 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1991 | struct i915_gem_context *ctx, |
0bc40be8 | 1992 | struct intel_engine_cs *engine) |
064ca1d2 | 1993 | { |
bf3783e5 | 1994 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1995 | struct page *page; |
064ca1d2 | 1996 | int j; |
064ca1d2 | 1997 | |
7069b144 CW |
1998 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1999 | ||
bf3783e5 CW |
2000 | if (!vma) { |
2001 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2002 | return; |
2003 | } | |
2004 | ||
bf3783e5 CW |
2005 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2006 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2007 | i915_ggtt_offset(vma)); |
064ca1d2 | 2008 | |
a4f5ea64 | 2009 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2010 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2011 | return; |
2012 | } | |
2013 | ||
bf3783e5 CW |
2014 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2015 | if (page) { | |
2016 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2017 | |
2018 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2019 | seq_printf(m, |
2020 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2021 | j * 4, | |
064ca1d2 TD |
2022 | reg_state[j], reg_state[j + 1], |
2023 | reg_state[j + 2], reg_state[j + 3]); | |
2024 | } | |
2025 | kunmap_atomic(reg_state); | |
2026 | } | |
2027 | ||
a4f5ea64 | 2028 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2029 | seq_putc(m, '\n'); |
2030 | } | |
2031 | ||
c0ab1ae9 BW |
2032 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2033 | { | |
36cdd013 DW |
2034 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2035 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2036 | struct intel_engine_cs *engine; |
e2efd130 | 2037 | struct i915_gem_context *ctx; |
3b3f1650 | 2038 | enum intel_engine_id id; |
b4ac5afc | 2039 | int ret; |
c0ab1ae9 BW |
2040 | |
2041 | if (!i915.enable_execlists) { | |
2042 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2043 | return 0; | |
2044 | } | |
2045 | ||
2046 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2047 | if (ret) | |
2048 | return ret; | |
2049 | ||
e28e404c | 2050 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2051 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2052 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2053 | |
2054 | mutex_unlock(&dev->struct_mutex); | |
2055 | ||
2056 | return 0; | |
2057 | } | |
2058 | ||
ea16a3cd DV |
2059 | static const char *swizzle_string(unsigned swizzle) |
2060 | { | |
aee56cff | 2061 | switch (swizzle) { |
ea16a3cd DV |
2062 | case I915_BIT_6_SWIZZLE_NONE: |
2063 | return "none"; | |
2064 | case I915_BIT_6_SWIZZLE_9: | |
2065 | return "bit9"; | |
2066 | case I915_BIT_6_SWIZZLE_9_10: | |
2067 | return "bit9/bit10"; | |
2068 | case I915_BIT_6_SWIZZLE_9_11: | |
2069 | return "bit9/bit11"; | |
2070 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2071 | return "bit9/bit10/bit11"; | |
2072 | case I915_BIT_6_SWIZZLE_9_17: | |
2073 | return "bit9/bit17"; | |
2074 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2075 | return "bit9/bit10/bit17"; | |
2076 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2077 | return "unknown"; |
ea16a3cd DV |
2078 | } |
2079 | ||
2080 | return "bug"; | |
2081 | } | |
2082 | ||
2083 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2084 | { | |
36cdd013 | 2085 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2086 | |
c8c8fb33 | 2087 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2088 | |
ea16a3cd DV |
2089 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2090 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2091 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2092 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2093 | ||
36cdd013 | 2094 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2095 | seq_printf(m, "DDC = 0x%08x\n", |
2096 | I915_READ(DCC)); | |
656bfa3a DV |
2097 | seq_printf(m, "DDC2 = 0x%08x\n", |
2098 | I915_READ(DCC2)); | |
ea16a3cd DV |
2099 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2100 | I915_READ16(C0DRB3)); | |
2101 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2102 | I915_READ16(C1DRB3)); | |
36cdd013 | 2103 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2104 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2105 | I915_READ(MAD_DIMM_C0)); | |
2106 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2107 | I915_READ(MAD_DIMM_C1)); | |
2108 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2109 | I915_READ(MAD_DIMM_C2)); | |
2110 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2111 | I915_READ(TILECTL)); | |
36cdd013 | 2112 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2113 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2114 | I915_READ(GAMTARBMODE)); | |
2115 | else | |
2116 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2117 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2118 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2119 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2120 | } |
656bfa3a DV |
2121 | |
2122 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2123 | seq_puts(m, "L-shaped memory detected\n"); | |
2124 | ||
c8c8fb33 | 2125 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2126 | |
2127 | return 0; | |
2128 | } | |
2129 | ||
1c60fef5 BW |
2130 | static int per_file_ctx(int id, void *ptr, void *data) |
2131 | { | |
e2efd130 | 2132 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2133 | struct seq_file *m = data; |
ae6c4806 DV |
2134 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2135 | ||
2136 | if (!ppgtt) { | |
2137 | seq_printf(m, " no ppgtt for context %d\n", | |
2138 | ctx->user_handle); | |
2139 | return 0; | |
2140 | } | |
1c60fef5 | 2141 | |
f83d6518 OM |
2142 | if (i915_gem_context_is_default(ctx)) |
2143 | seq_puts(m, " default context:\n"); | |
2144 | else | |
821d66dd | 2145 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2146 | ppgtt->debug_dump(ppgtt, m); |
2147 | ||
2148 | return 0; | |
2149 | } | |
2150 | ||
36cdd013 DW |
2151 | static void gen8_ppgtt_info(struct seq_file *m, |
2152 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2153 | { |
77df6772 | 2154 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2155 | struct intel_engine_cs *engine; |
2156 | enum intel_engine_id id; | |
b4ac5afc | 2157 | int i; |
3cf17fc5 | 2158 | |
77df6772 BW |
2159 | if (!ppgtt) |
2160 | return; | |
2161 | ||
3b3f1650 | 2162 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2163 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2164 | for (i = 0; i < 4; i++) { |
e2f80391 | 2165 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2166 | pdp <<= 32; |
e2f80391 | 2167 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2168 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2169 | } |
2170 | } | |
2171 | } | |
2172 | ||
36cdd013 DW |
2173 | static void gen6_ppgtt_info(struct seq_file *m, |
2174 | struct drm_i915_private *dev_priv) | |
77df6772 | 2175 | { |
e2f80391 | 2176 | struct intel_engine_cs *engine; |
3b3f1650 | 2177 | enum intel_engine_id id; |
3cf17fc5 | 2178 | |
7e22dbbb | 2179 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2180 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2181 | ||
3b3f1650 | 2182 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2183 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2184 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2185 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2186 | I915_READ(RING_MODE_GEN7(engine))); | |
2187 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2188 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2189 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2190 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2191 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2192 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2193 | } |
2194 | if (dev_priv->mm.aliasing_ppgtt) { | |
2195 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2196 | ||
267f0c90 | 2197 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2198 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2199 | |
87d60b63 | 2200 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2201 | } |
1c60fef5 | 2202 | |
3cf17fc5 | 2203 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2204 | } |
2205 | ||
2206 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2207 | { | |
36cdd013 DW |
2208 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2209 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2210 | struct drm_file *file; |
637ee29e | 2211 | int ret; |
77df6772 | 2212 | |
637ee29e CW |
2213 | mutex_lock(&dev->filelist_mutex); |
2214 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2215 | if (ret) |
637ee29e CW |
2216 | goto out_unlock; |
2217 | ||
c8c8fb33 | 2218 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2219 | |
36cdd013 DW |
2220 | if (INTEL_GEN(dev_priv) >= 8) |
2221 | gen8_ppgtt_info(m, dev_priv); | |
2222 | else if (INTEL_GEN(dev_priv) >= 6) | |
2223 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2224 | |
ea91e401 MT |
2225 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2226 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2227 | struct task_struct *task; |
ea91e401 | 2228 | |
7cb5dff8 | 2229 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2230 | if (!task) { |
2231 | ret = -ESRCH; | |
637ee29e | 2232 | goto out_rpm; |
06812760 | 2233 | } |
7cb5dff8 GT |
2234 | seq_printf(m, "\nproc: %s\n", task->comm); |
2235 | put_task_struct(task); | |
ea91e401 MT |
2236 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2237 | (void *)(unsigned long)m); | |
2238 | } | |
2239 | ||
637ee29e | 2240 | out_rpm: |
c8c8fb33 | 2241 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2242 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2243 | out_unlock: |
2244 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2245 | return ret; |
3cf17fc5 DV |
2246 | } |
2247 | ||
f5a4c67d CW |
2248 | static int count_irq_waiters(struct drm_i915_private *i915) |
2249 | { | |
e2f80391 | 2250 | struct intel_engine_cs *engine; |
3b3f1650 | 2251 | enum intel_engine_id id; |
f5a4c67d | 2252 | int count = 0; |
f5a4c67d | 2253 | |
3b3f1650 | 2254 | for_each_engine(engine, i915, id) |
688e6c72 | 2255 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2256 | |
2257 | return count; | |
2258 | } | |
2259 | ||
7466c291 CW |
2260 | static const char *rps_power_to_str(unsigned int power) |
2261 | { | |
2262 | static const char * const strings[] = { | |
2263 | [LOW_POWER] = "low power", | |
2264 | [BETWEEN] = "mixed", | |
2265 | [HIGH_POWER] = "high power", | |
2266 | }; | |
2267 | ||
2268 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2269 | return "unknown"; | |
2270 | ||
2271 | return strings[power]; | |
2272 | } | |
2273 | ||
1854d5ca CW |
2274 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2275 | { | |
36cdd013 DW |
2276 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2277 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2278 | struct drm_file *file; |
1854d5ca | 2279 | |
f5a4c67d | 2280 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2281 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2282 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2283 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2284 | seq_printf(m, "Frequency requested %d\n", |
2285 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2286 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2287 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2288 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2289 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2290 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2291 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2292 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2293 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2294 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2295 | |
2296 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2297 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2298 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2299 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2300 | struct task_struct *task; | |
2301 | ||
2302 | rcu_read_lock(); | |
2303 | task = pid_task(file->pid, PIDTYPE_PID); | |
2304 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2305 | task ? task->comm : "<unknown>", | |
2306 | task ? task->pid : -1, | |
2e1b8730 CW |
2307 | file_priv->rps.boosts, |
2308 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2309 | rcu_read_unlock(); |
2310 | } | |
197be2ae | 2311 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2312 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2313 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2314 | |
7466c291 CW |
2315 | if (INTEL_GEN(dev_priv) >= 6 && |
2316 | dev_priv->rps.enabled && | |
28176ef4 | 2317 | dev_priv->gt.active_requests) { |
7466c291 CW |
2318 | u32 rpup, rpupei; |
2319 | u32 rpdown, rpdownei; | |
2320 | ||
2321 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2322 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2323 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2324 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2325 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2326 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2327 | ||
2328 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2329 | rps_power_to_str(dev_priv->rps.power)); | |
2330 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2331 | 100 * rpup / rpupei, | |
2332 | dev_priv->rps.up_threshold); | |
2333 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2334 | 100 * rpdown / rpdownei, | |
2335 | dev_priv->rps.down_threshold); | |
2336 | } else { | |
2337 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2338 | } | |
2339 | ||
8d3afd7d | 2340 | return 0; |
1854d5ca CW |
2341 | } |
2342 | ||
63573eb7 BW |
2343 | static int i915_llc(struct seq_file *m, void *data) |
2344 | { | |
36cdd013 | 2345 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2346 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2347 | |
36cdd013 | 2348 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2349 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2350 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2351 | |
2352 | return 0; | |
2353 | } | |
2354 | ||
fdf5d357 AD |
2355 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2356 | { | |
36cdd013 | 2357 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2358 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2359 | u32 tmp, i; | |
2360 | ||
2d1fe073 | 2361 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2362 | return 0; |
2363 | ||
2364 | seq_printf(m, "GuC firmware status:\n"); | |
2365 | seq_printf(m, "\tpath: %s\n", | |
2366 | guc_fw->guc_fw_path); | |
2367 | seq_printf(m, "\tfetch: %s\n", | |
2368 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2369 | seq_printf(m, "\tload: %s\n", | |
2370 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2371 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2372 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2373 | seq_printf(m, "\tversion found: %d.%d\n", | |
2374 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2375 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2376 | guc_fw->header_offset, guc_fw->header_size); | |
2377 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2378 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2379 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2380 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2381 | |
2382 | tmp = I915_READ(GUC_STATUS); | |
2383 | ||
2384 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2385 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2386 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2387 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2388 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2389 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2390 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2391 | seq_puts(m, "\nScratch registers:\n"); | |
2392 | for (i = 0; i < 16; i++) | |
2393 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2394 | ||
2395 | return 0; | |
2396 | } | |
2397 | ||
5aa1ee4b AG |
2398 | static void i915_guc_log_info(struct seq_file *m, |
2399 | struct drm_i915_private *dev_priv) | |
2400 | { | |
2401 | struct intel_guc *guc = &dev_priv->guc; | |
2402 | ||
2403 | seq_puts(m, "\nGuC logging stats:\n"); | |
2404 | ||
2405 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2406 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2407 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2408 | ||
2409 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2410 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2411 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2412 | ||
2413 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2414 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2415 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2416 | ||
2417 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2418 | guc->log.flush_interrupt_count); | |
2419 | ||
2420 | seq_printf(m, "\tCapture miss count: %u\n", | |
2421 | guc->log.capture_miss_count); | |
2422 | } | |
2423 | ||
8b417c26 DG |
2424 | static void i915_guc_client_info(struct seq_file *m, |
2425 | struct drm_i915_private *dev_priv, | |
2426 | struct i915_guc_client *client) | |
2427 | { | |
e2f80391 | 2428 | struct intel_engine_cs *engine; |
c18468c4 | 2429 | enum intel_engine_id id; |
8b417c26 | 2430 | uint64_t tot = 0; |
8b417c26 DG |
2431 | |
2432 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2433 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2434 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2435 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2436 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2437 | client->wq_size, client->wq_offset, client->wq_tail); | |
2438 | ||
551aaecd | 2439 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2440 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2441 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2442 | ||
3b3f1650 | 2443 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2444 | u64 submissions = client->submissions[id]; |
2445 | tot += submissions; | |
8b417c26 | 2446 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2447 | submissions, engine->name); |
8b417c26 DG |
2448 | } |
2449 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2450 | } | |
2451 | ||
2452 | static int i915_guc_info(struct seq_file *m, void *data) | |
2453 | { | |
36cdd013 | 2454 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2455 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2456 | struct intel_engine_cs *engine; |
c18468c4 | 2457 | enum intel_engine_id id; |
334636c6 | 2458 | u64 total; |
8b417c26 | 2459 | |
334636c6 CW |
2460 | if (!guc->execbuf_client) { |
2461 | seq_printf(m, "GuC submission %s\n", | |
2462 | HAS_GUC_SCHED(dev_priv) ? | |
2463 | "disabled" : | |
2464 | "not supported"); | |
5a843307 | 2465 | return 0; |
334636c6 | 2466 | } |
8b417c26 | 2467 | |
9636f6db | 2468 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2469 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2470 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2471 | |
334636c6 CW |
2472 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2473 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2474 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2475 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2476 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2477 | |
334636c6 | 2478 | total = 0; |
8b417c26 | 2479 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2480 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2481 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2482 | total += submissions; |
397097b0 | 2483 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2484 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2485 | } |
2486 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2487 | ||
334636c6 CW |
2488 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2489 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2490 | |
5aa1ee4b AG |
2491 | i915_guc_log_info(m, dev_priv); |
2492 | ||
8b417c26 DG |
2493 | /* Add more as required ... */ |
2494 | ||
2495 | return 0; | |
2496 | } | |
2497 | ||
4c7e77fc AD |
2498 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2499 | { | |
36cdd013 | 2500 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2501 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2502 | int i = 0, pg; |
2503 | ||
d6b40b4b | 2504 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2505 | return 0; |
2506 | ||
d6b40b4b | 2507 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2508 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2509 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2510 | |
2511 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2512 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2513 | *(log + i), *(log + i + 1), | |
2514 | *(log + i + 2), *(log + i + 3)); | |
2515 | ||
2516 | kunmap_atomic(log); | |
2517 | } | |
2518 | ||
2519 | seq_putc(m, '\n'); | |
2520 | ||
2521 | return 0; | |
2522 | } | |
2523 | ||
685534ef SAK |
2524 | static int i915_guc_log_control_get(void *data, u64 *val) |
2525 | { | |
2526 | struct drm_device *dev = data; | |
2527 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2528 | ||
2529 | if (!dev_priv->guc.log.vma) | |
2530 | return -EINVAL; | |
2531 | ||
2532 | *val = i915.guc_log_level; | |
2533 | ||
2534 | return 0; | |
2535 | } | |
2536 | ||
2537 | static int i915_guc_log_control_set(void *data, u64 val) | |
2538 | { | |
2539 | struct drm_device *dev = data; | |
2540 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2541 | int ret; | |
2542 | ||
2543 | if (!dev_priv->guc.log.vma) | |
2544 | return -EINVAL; | |
2545 | ||
2546 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2547 | if (ret) | |
2548 | return ret; | |
2549 | ||
2550 | intel_runtime_pm_get(dev_priv); | |
2551 | ret = i915_guc_log_control(dev_priv, val); | |
2552 | intel_runtime_pm_put(dev_priv); | |
2553 | ||
2554 | mutex_unlock(&dev->struct_mutex); | |
2555 | return ret; | |
2556 | } | |
2557 | ||
2558 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2559 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2560 | "%lld\n"); | |
2561 | ||
e91fd8c6 RV |
2562 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2563 | { | |
36cdd013 | 2564 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2565 | u32 psrperf = 0; |
a6cbdb8e RV |
2566 | u32 stat[3]; |
2567 | enum pipe pipe; | |
a031d709 | 2568 | bool enabled = false; |
e91fd8c6 | 2569 | |
36cdd013 | 2570 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2571 | seq_puts(m, "PSR not supported\n"); |
2572 | return 0; | |
2573 | } | |
2574 | ||
c8c8fb33 PZ |
2575 | intel_runtime_pm_get(dev_priv); |
2576 | ||
fa128fa6 | 2577 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2578 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2579 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2580 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2581 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2582 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2583 | dev_priv->psr.busy_frontbuffer_bits); | |
2584 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2585 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2586 | |
7e3eb599 NV |
2587 | if (HAS_DDI(dev_priv)) { |
2588 | if (dev_priv->psr.psr2_support) | |
2589 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2590 | else | |
2591 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2592 | } else { | |
3553a8ea | 2593 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2594 | enum transcoder cpu_transcoder = |
2595 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2596 | enum intel_display_power_domain power_domain; | |
2597 | ||
2598 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2599 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2600 | power_domain)) | |
2601 | continue; | |
2602 | ||
3553a8ea DL |
2603 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2604 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2605 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2606 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2607 | enabled = true; | |
9c870d03 CW |
2608 | |
2609 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2610 | } |
2611 | } | |
60e5ffe3 RV |
2612 | |
2613 | seq_printf(m, "Main link in standby mode: %s\n", | |
2614 | yesno(dev_priv->psr.link_standby)); | |
2615 | ||
a6cbdb8e RV |
2616 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2617 | ||
36cdd013 | 2618 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2619 | for_each_pipe(dev_priv, pipe) { |
2620 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2621 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2622 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2623 | } | |
2624 | seq_puts(m, "\n"); | |
e91fd8c6 | 2625 | |
05eec3c2 RV |
2626 | /* |
2627 | * VLV/CHV PSR has no kind of performance counter | |
2628 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2629 | */ | |
36cdd013 | 2630 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2631 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2632 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2633 | |
2634 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2635 | } | |
6ba1f9e1 NV |
2636 | if (dev_priv->psr.psr2_support) { |
2637 | static const char * const live_status[] = { | |
2638 | "IDLE", | |
2639 | "CAPTURE", | |
2640 | "CAPTURE_FS", | |
2641 | "SLEEP", | |
2642 | "BUFON_FW", | |
2643 | "ML_UP", | |
2644 | "SU_STANDBY", | |
2645 | "FAST_SLEEP", | |
2646 | "DEEP_SLEEP", | |
2647 | "BUF_ON", | |
2648 | "TG_ON" }; | |
2649 | u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) & | |
2650 | EDP_PSR2_STATUS_STATE_MASK) >> | |
2651 | EDP_PSR2_STATUS_STATE_SHIFT; | |
2652 | ||
2653 | seq_printf(m, "PSR2_STATUS_EDP: %x\n", | |
2654 | I915_READ(EDP_PSR2_STATUS_CTL)); | |
2655 | ||
2656 | if (pos < ARRAY_SIZE(live_status)) | |
2657 | seq_printf(m, "PSR2 live state %s\n", | |
2658 | live_status[pos]); | |
2659 | } | |
fa128fa6 | 2660 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2661 | |
c8c8fb33 | 2662 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2663 | return 0; |
2664 | } | |
2665 | ||
d2e216d0 RV |
2666 | static int i915_sink_crc(struct seq_file *m, void *data) |
2667 | { | |
36cdd013 DW |
2668 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2669 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2670 | struct intel_connector *connector; |
2671 | struct intel_dp *intel_dp = NULL; | |
2672 | int ret; | |
2673 | u8 crc[6]; | |
2674 | ||
2675 | drm_modeset_lock_all(dev); | |
aca5e361 | 2676 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2677 | struct drm_crtc *crtc; |
d2e216d0 | 2678 | |
26c17cf6 | 2679 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2680 | continue; |
2681 | ||
26c17cf6 ML |
2682 | crtc = connector->base.state->crtc; |
2683 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2684 | continue; |
2685 | ||
26c17cf6 | 2686 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2687 | continue; |
2688 | ||
26c17cf6 | 2689 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2690 | |
2691 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2692 | if (ret) | |
2693 | goto out; | |
2694 | ||
2695 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2696 | crc[0], crc[1], crc[2], | |
2697 | crc[3], crc[4], crc[5]); | |
2698 | goto out; | |
2699 | } | |
2700 | ret = -ENODEV; | |
2701 | out: | |
2702 | drm_modeset_unlock_all(dev); | |
2703 | return ret; | |
2704 | } | |
2705 | ||
ec013e7f JB |
2706 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2707 | { | |
36cdd013 | 2708 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2709 | u64 power; |
2710 | u32 units; | |
2711 | ||
36cdd013 | 2712 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2713 | return -ENODEV; |
2714 | ||
36623ef8 PZ |
2715 | intel_runtime_pm_get(dev_priv); |
2716 | ||
ec013e7f JB |
2717 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2718 | power = (power & 0x1f00) >> 8; | |
2719 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2720 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2721 | power *= units; | |
2722 | ||
36623ef8 PZ |
2723 | intel_runtime_pm_put(dev_priv); |
2724 | ||
ec013e7f | 2725 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2726 | |
2727 | return 0; | |
2728 | } | |
2729 | ||
6455c870 | 2730 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2731 | { |
36cdd013 | 2732 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2733 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2734 | |
a156e64d CW |
2735 | if (!HAS_RUNTIME_PM(dev_priv)) |
2736 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2737 | |
67d97da3 | 2738 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2739 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2740 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2741 | #ifdef CONFIG_PM |
a6aaec8b | 2742 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2743 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2744 | #else |
2745 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2746 | #endif | |
a156e64d | 2747 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2748 | pci_power_name(pdev->current_state), |
2749 | pdev->current_state); | |
371db66a | 2750 | |
ec013e7f JB |
2751 | return 0; |
2752 | } | |
2753 | ||
1da51581 ID |
2754 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2755 | { | |
36cdd013 | 2756 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2757 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2758 | int i; | |
2759 | ||
2760 | mutex_lock(&power_domains->lock); | |
2761 | ||
2762 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2763 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2764 | struct i915_power_well *power_well; | |
2765 | enum intel_display_power_domain power_domain; | |
2766 | ||
2767 | power_well = &power_domains->power_wells[i]; | |
2768 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2769 | power_well->count); | |
2770 | ||
2771 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2772 | power_domain++) { | |
2773 | if (!(BIT(power_domain) & power_well->domains)) | |
2774 | continue; | |
2775 | ||
2776 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2777 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2778 | power_domains->domain_use_count[power_domain]); |
2779 | } | |
2780 | } | |
2781 | ||
2782 | mutex_unlock(&power_domains->lock); | |
2783 | ||
2784 | return 0; | |
2785 | } | |
2786 | ||
b7cec66d DL |
2787 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2788 | { | |
36cdd013 | 2789 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2790 | struct intel_csr *csr; |
2791 | ||
36cdd013 | 2792 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2793 | seq_puts(m, "not supported\n"); |
2794 | return 0; | |
2795 | } | |
2796 | ||
2797 | csr = &dev_priv->csr; | |
2798 | ||
6fb403de MK |
2799 | intel_runtime_pm_get(dev_priv); |
2800 | ||
b7cec66d DL |
2801 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2802 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2803 | ||
2804 | if (!csr->dmc_payload) | |
6fb403de | 2805 | goto out; |
b7cec66d DL |
2806 | |
2807 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2808 | CSR_VERSION_MINOR(csr->version)); | |
2809 | ||
36cdd013 | 2810 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2811 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2812 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2813 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2814 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2815 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2816 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2817 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2818 | } |
2819 | ||
6fb403de MK |
2820 | out: |
2821 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2822 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2823 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2824 | ||
8337206d DL |
2825 | intel_runtime_pm_put(dev_priv); |
2826 | ||
b7cec66d DL |
2827 | return 0; |
2828 | } | |
2829 | ||
53f5e3ca JB |
2830 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2831 | struct drm_display_mode *mode) | |
2832 | { | |
2833 | int i; | |
2834 | ||
2835 | for (i = 0; i < tabs; i++) | |
2836 | seq_putc(m, '\t'); | |
2837 | ||
2838 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2839 | mode->base.id, mode->name, | |
2840 | mode->vrefresh, mode->clock, | |
2841 | mode->hdisplay, mode->hsync_start, | |
2842 | mode->hsync_end, mode->htotal, | |
2843 | mode->vdisplay, mode->vsync_start, | |
2844 | mode->vsync_end, mode->vtotal, | |
2845 | mode->type, mode->flags); | |
2846 | } | |
2847 | ||
2848 | static void intel_encoder_info(struct seq_file *m, | |
2849 | struct intel_crtc *intel_crtc, | |
2850 | struct intel_encoder *intel_encoder) | |
2851 | { | |
36cdd013 DW |
2852 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2853 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2854 | struct drm_crtc *crtc = &intel_crtc->base; |
2855 | struct intel_connector *intel_connector; | |
2856 | struct drm_encoder *encoder; | |
2857 | ||
2858 | encoder = &intel_encoder->base; | |
2859 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2860 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2861 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2862 | struct drm_connector *connector = &intel_connector->base; | |
2863 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2864 | connector->base.id, | |
c23cc417 | 2865 | connector->name, |
53f5e3ca JB |
2866 | drm_get_connector_status_name(connector->status)); |
2867 | if (connector->status == connector_status_connected) { | |
2868 | struct drm_display_mode *mode = &crtc->mode; | |
2869 | seq_printf(m, ", mode:\n"); | |
2870 | intel_seq_print_mode(m, 2, mode); | |
2871 | } else { | |
2872 | seq_putc(m, '\n'); | |
2873 | } | |
2874 | } | |
2875 | } | |
2876 | ||
2877 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2878 | { | |
36cdd013 DW |
2879 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2880 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2881 | struct drm_crtc *crtc = &intel_crtc->base; |
2882 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2883 | struct drm_plane_state *plane_state = crtc->primary->state; |
2884 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2885 | |
23a48d53 | 2886 | if (fb) |
5aa8a937 | 2887 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2888 | fb->base.id, plane_state->src_x >> 16, |
2889 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2890 | else |
2891 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2892 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2893 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2894 | } | |
2895 | ||
2896 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2897 | { | |
2898 | struct drm_display_mode *mode = panel->fixed_mode; | |
2899 | ||
2900 | seq_printf(m, "\tfixed mode:\n"); | |
2901 | intel_seq_print_mode(m, 2, mode); | |
2902 | } | |
2903 | ||
2904 | static void intel_dp_info(struct seq_file *m, | |
2905 | struct intel_connector *intel_connector) | |
2906 | { | |
2907 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2908 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2909 | ||
2910 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2911 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2912 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2913 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2914 | |
2915 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2916 | &intel_dp->aux); | |
53f5e3ca JB |
2917 | } |
2918 | ||
9a148a96 LY |
2919 | static void intel_dp_mst_info(struct seq_file *m, |
2920 | struct intel_connector *intel_connector) | |
2921 | { | |
2922 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2923 | struct intel_dp_mst_encoder *intel_mst = | |
2924 | enc_to_mst(&intel_encoder->base); | |
2925 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2926 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2927 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2928 | intel_connector->port); | |
2929 | ||
2930 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2931 | } | |
2932 | ||
53f5e3ca JB |
2933 | static void intel_hdmi_info(struct seq_file *m, |
2934 | struct intel_connector *intel_connector) | |
2935 | { | |
2936 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2937 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2938 | ||
742f491d | 2939 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2940 | } |
2941 | ||
2942 | static void intel_lvds_info(struct seq_file *m, | |
2943 | struct intel_connector *intel_connector) | |
2944 | { | |
2945 | intel_panel_info(m, &intel_connector->panel); | |
2946 | } | |
2947 | ||
2948 | static void intel_connector_info(struct seq_file *m, | |
2949 | struct drm_connector *connector) | |
2950 | { | |
2951 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2952 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2953 | struct drm_display_mode *mode; |
53f5e3ca JB |
2954 | |
2955 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2956 | connector->base.id, connector->name, |
53f5e3ca JB |
2957 | drm_get_connector_status_name(connector->status)); |
2958 | if (connector->status == connector_status_connected) { | |
2959 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2960 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2961 | connector->display_info.width_mm, | |
2962 | connector->display_info.height_mm); | |
2963 | seq_printf(m, "\tsubpixel order: %s\n", | |
2964 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2965 | seq_printf(m, "\tCEA rev: %d\n", | |
2966 | connector->display_info.cea_rev); | |
2967 | } | |
ee648a74 ML |
2968 | |
2969 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2970 | return; | |
2971 | ||
2972 | switch (connector->connector_type) { | |
2973 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2974 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
2975 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2976 | intel_dp_mst_info(m, intel_connector); | |
2977 | else | |
2978 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
2979 | break; |
2980 | case DRM_MODE_CONNECTOR_LVDS: | |
2981 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2982 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2983 | break; |
2984 | case DRM_MODE_CONNECTOR_HDMIA: | |
2985 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2986 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2987 | intel_hdmi_info(m, intel_connector); | |
2988 | break; | |
2989 | default: | |
2990 | break; | |
36cd7444 | 2991 | } |
53f5e3ca | 2992 | |
f103fc7d JB |
2993 | seq_printf(m, "\tmodes:\n"); |
2994 | list_for_each_entry(mode, &connector->modes, head) | |
2995 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2996 | } |
2997 | ||
36cdd013 | 2998 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2999 | { |
065f2ec2 CW |
3000 | u32 state; |
3001 | ||
2a307c2e | 3002 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3003 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3004 | else |
5efb3e28 | 3005 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3006 | |
3007 | return state; | |
3008 | } | |
3009 | ||
36cdd013 DW |
3010 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3011 | int pipe, int *x, int *y) | |
065f2ec2 | 3012 | { |
065f2ec2 CW |
3013 | u32 pos; |
3014 | ||
5efb3e28 | 3015 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3016 | |
3017 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3018 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3019 | *x = -*x; | |
3020 | ||
3021 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3022 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3023 | *y = -*y; | |
3024 | ||
36cdd013 | 3025 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3026 | } |
3027 | ||
3abc4e09 RF |
3028 | static const char *plane_type(enum drm_plane_type type) |
3029 | { | |
3030 | switch (type) { | |
3031 | case DRM_PLANE_TYPE_OVERLAY: | |
3032 | return "OVL"; | |
3033 | case DRM_PLANE_TYPE_PRIMARY: | |
3034 | return "PRI"; | |
3035 | case DRM_PLANE_TYPE_CURSOR: | |
3036 | return "CUR"; | |
3037 | /* | |
3038 | * Deliberately omitting default: to generate compiler warnings | |
3039 | * when a new drm_plane_type gets added. | |
3040 | */ | |
3041 | } | |
3042 | ||
3043 | return "unknown"; | |
3044 | } | |
3045 | ||
3046 | static const char *plane_rotation(unsigned int rotation) | |
3047 | { | |
3048 | static char buf[48]; | |
3049 | /* | |
3050 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3051 | * will print them all to visualize if the values are misused | |
3052 | */ | |
3053 | snprintf(buf, sizeof(buf), | |
3054 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3055 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3056 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3057 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3058 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3059 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3060 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3061 | rotation); |
3062 | ||
3063 | return buf; | |
3064 | } | |
3065 | ||
3066 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3067 | { | |
36cdd013 DW |
3068 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3069 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3070 | struct intel_plane *intel_plane; |
3071 | ||
3072 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3073 | struct drm_plane_state *state; | |
3074 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3075 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3076 | |
3077 | if (!plane->state) { | |
3078 | seq_puts(m, "plane->state is NULL!\n"); | |
3079 | continue; | |
3080 | } | |
3081 | ||
3082 | state = plane->state; | |
3083 | ||
90844f00 | 3084 | if (state->fb) { |
438b74a5 VS |
3085 | drm_get_format_name(state->fb->format->format, |
3086 | &format_name); | |
90844f00 | 3087 | } else { |
b3c11ac2 | 3088 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3089 | } |
3090 | ||
3abc4e09 RF |
3091 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3092 | plane->base.id, | |
3093 | plane_type(intel_plane->base.type), | |
3094 | state->crtc_x, state->crtc_y, | |
3095 | state->crtc_w, state->crtc_h, | |
3096 | (state->src_x >> 16), | |
3097 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3098 | (state->src_y >> 16), | |
3099 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3100 | (state->src_w >> 16), | |
3101 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3102 | (state->src_h >> 16), | |
3103 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3104 | format_name.str, |
3abc4e09 RF |
3105 | plane_rotation(state->rotation)); |
3106 | } | |
3107 | } | |
3108 | ||
3109 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3110 | { | |
3111 | struct intel_crtc_state *pipe_config; | |
3112 | int num_scalers = intel_crtc->num_scalers; | |
3113 | int i; | |
3114 | ||
3115 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3116 | ||
3117 | /* Not all platformas have a scaler */ | |
3118 | if (num_scalers) { | |
3119 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3120 | num_scalers, | |
3121 | pipe_config->scaler_state.scaler_users, | |
3122 | pipe_config->scaler_state.scaler_id); | |
3123 | ||
58415918 | 3124 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3125 | struct intel_scaler *sc = |
3126 | &pipe_config->scaler_state.scalers[i]; | |
3127 | ||
3128 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3129 | i, yesno(sc->in_use), sc->mode); | |
3130 | } | |
3131 | seq_puts(m, "\n"); | |
3132 | } else { | |
3133 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3134 | } | |
3135 | } | |
3136 | ||
53f5e3ca JB |
3137 | static int i915_display_info(struct seq_file *m, void *unused) |
3138 | { | |
36cdd013 DW |
3139 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3140 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3141 | struct intel_crtc *crtc; |
53f5e3ca JB |
3142 | struct drm_connector *connector; |
3143 | ||
b0e5ddf3 | 3144 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3145 | drm_modeset_lock_all(dev); |
3146 | seq_printf(m, "CRTC info\n"); | |
3147 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3148 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3149 | bool active; |
f77076c9 | 3150 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3151 | int x, y; |
53f5e3ca | 3152 | |
f77076c9 ML |
3153 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3154 | ||
3abc4e09 | 3155 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3156 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3157 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3158 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3159 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3160 | ||
f77076c9 | 3161 | if (pipe_config->base.active) { |
065f2ec2 CW |
3162 | intel_crtc_info(m, crtc); |
3163 | ||
36cdd013 | 3164 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3165 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3166 | yesno(crtc->cursor_base), |
3dd512fb MR |
3167 | x, y, crtc->base.cursor->state->crtc_w, |
3168 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3169 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3170 | intel_scaler_info(m, crtc); |
3171 | intel_plane_info(m, crtc); | |
a23dc658 | 3172 | } |
cace841c DV |
3173 | |
3174 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3175 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3176 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3177 | } |
3178 | ||
3179 | seq_printf(m, "\n"); | |
3180 | seq_printf(m, "Connector info\n"); | |
3181 | seq_printf(m, "--------------\n"); | |
3182 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3183 | intel_connector_info(m, connector); | |
3184 | } | |
3185 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3186 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3187 | |
3188 | return 0; | |
3189 | } | |
3190 | ||
1b36595f CW |
3191 | static int i915_engine_info(struct seq_file *m, void *unused) |
3192 | { | |
3193 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3194 | struct intel_engine_cs *engine; | |
3b3f1650 | 3195 | enum intel_engine_id id; |
1b36595f | 3196 | |
9c870d03 CW |
3197 | intel_runtime_pm_get(dev_priv); |
3198 | ||
3b3f1650 | 3199 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3200 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3201 | struct drm_i915_gem_request *rq; | |
3202 | struct rb_node *rb; | |
3203 | u64 addr; | |
3204 | ||
3205 | seq_printf(m, "%s\n", engine->name); | |
3fe3b030 | 3206 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n", |
1b36595f | 3207 | intel_engine_get_seqno(engine), |
cb399eab | 3208 | intel_engine_last_submit(engine), |
1b36595f | 3209 | engine->hangcheck.seqno, |
3fe3b030 | 3210 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp)); |
1b36595f CW |
3211 | |
3212 | rcu_read_lock(); | |
3213 | ||
3214 | seq_printf(m, "\tRequests:\n"); | |
3215 | ||
73cb9701 CW |
3216 | rq = list_first_entry(&engine->timeline->requests, |
3217 | struct drm_i915_gem_request, link); | |
3218 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3219 | print_request(m, rq, "\t\tfirst "); |
3220 | ||
73cb9701 CW |
3221 | rq = list_last_entry(&engine->timeline->requests, |
3222 | struct drm_i915_gem_request, link); | |
3223 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3224 | print_request(m, rq, "\t\tlast "); |
3225 | ||
3226 | rq = i915_gem_find_active_request(engine); | |
3227 | if (rq) { | |
3228 | print_request(m, rq, "\t\tactive "); | |
3229 | seq_printf(m, | |
3230 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3231 | rq->head, rq->postfix, rq->tail, | |
3232 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3233 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3234 | } | |
3235 | ||
3236 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3237 | I915_READ(RING_START(engine->mmio_base)), | |
3238 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3239 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3240 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3241 | rq ? rq->ring->head : 0); | |
3242 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3243 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3244 | rq ? rq->ring->tail : 0); | |
3245 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3246 | I915_READ(RING_CTL(engine->mmio_base)), | |
3247 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3248 | ||
3249 | rcu_read_unlock(); | |
3250 | ||
3251 | addr = intel_engine_get_active_head(engine); | |
3252 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3253 | upper_32_bits(addr), lower_32_bits(addr)); | |
3254 | addr = intel_engine_get_last_batch_head(engine); | |
3255 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3256 | upper_32_bits(addr), lower_32_bits(addr)); | |
3257 | ||
3258 | if (i915.enable_execlists) { | |
3259 | u32 ptr, read, write; | |
20311bd3 | 3260 | struct rb_node *rb; |
1b36595f CW |
3261 | |
3262 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3263 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3264 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3265 | ||
3266 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3267 | read = GEN8_CSB_READ_PTR(ptr); | |
3268 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3269 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3270 | read, write); | |
3271 | if (read >= GEN8_CSB_ENTRIES) | |
3272 | read = 0; | |
3273 | if (write >= GEN8_CSB_ENTRIES) | |
3274 | write = 0; | |
3275 | if (read > write) | |
3276 | write += GEN8_CSB_ENTRIES; | |
3277 | while (read < write) { | |
3278 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3279 | ||
3280 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3281 | idx, | |
3282 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3283 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3284 | } | |
3285 | ||
3286 | rcu_read_lock(); | |
3287 | rq = READ_ONCE(engine->execlist_port[0].request); | |
3288 | if (rq) | |
3289 | print_request(m, rq, "\t\tELSP[0] "); | |
3290 | else | |
3291 | seq_printf(m, "\t\tELSP[0] idle\n"); | |
3292 | rq = READ_ONCE(engine->execlist_port[1].request); | |
3293 | if (rq) | |
3294 | print_request(m, rq, "\t\tELSP[1] "); | |
3295 | else | |
3296 | seq_printf(m, "\t\tELSP[1] idle\n"); | |
3297 | rcu_read_unlock(); | |
c8247c06 | 3298 | |
663f71e7 | 3299 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3300 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3301 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3302 | print_request(m, rq, "\t\tQ "); |
3303 | } | |
663f71e7 | 3304 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3305 | } else if (INTEL_GEN(dev_priv) > 6) { |
3306 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3307 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3308 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3309 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3310 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3311 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3312 | } | |
3313 | ||
f6168e33 | 3314 | spin_lock_irq(&b->lock); |
1b36595f | 3315 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3316 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3317 | |
3318 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3319 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3320 | } | |
f6168e33 | 3321 | spin_unlock_irq(&b->lock); |
1b36595f CW |
3322 | |
3323 | seq_puts(m, "\n"); | |
3324 | } | |
3325 | ||
9c870d03 CW |
3326 | intel_runtime_pm_put(dev_priv); |
3327 | ||
1b36595f CW |
3328 | return 0; |
3329 | } | |
3330 | ||
e04934cf BW |
3331 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3332 | { | |
36cdd013 DW |
3333 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3334 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3335 | struct intel_engine_cs *engine; |
36cdd013 | 3336 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3337 | enum intel_engine_id id; |
3338 | int j, ret; | |
e04934cf | 3339 | |
39df9190 | 3340 | if (!i915.semaphores) { |
e04934cf BW |
3341 | seq_puts(m, "Semaphores are disabled\n"); |
3342 | return 0; | |
3343 | } | |
3344 | ||
3345 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3346 | if (ret) | |
3347 | return ret; | |
03872064 | 3348 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3349 | |
36cdd013 | 3350 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3351 | struct page *page; |
3352 | uint64_t *seqno; | |
3353 | ||
51d545d0 | 3354 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3355 | |
3356 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3357 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3358 | uint64_t offset; |
3359 | ||
e2f80391 | 3360 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3361 | |
3362 | seq_puts(m, " Last signal:"); | |
3363 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3364 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3365 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3366 | seqno[offset], offset * 8); | |
3367 | } | |
3368 | seq_putc(m, '\n'); | |
3369 | ||
3370 | seq_puts(m, " Last wait: "); | |
3371 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3372 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3373 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3374 | seqno[offset], offset * 8); | |
3375 | } | |
3376 | seq_putc(m, '\n'); | |
3377 | ||
3378 | } | |
3379 | kunmap_atomic(seqno); | |
3380 | } else { | |
3381 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3382 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3383 | for (j = 0; j < num_rings; j++) |
3384 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3385 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3386 | seq_putc(m, '\n'); |
3387 | } | |
3388 | ||
03872064 | 3389 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3390 | mutex_unlock(&dev->struct_mutex); |
3391 | return 0; | |
3392 | } | |
3393 | ||
728e29d7 DV |
3394 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3395 | { | |
36cdd013 DW |
3396 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3397 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3398 | int i; |
3399 | ||
3400 | drm_modeset_lock_all(dev); | |
3401 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3402 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3403 | ||
3404 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3405 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3406 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3407 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3408 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3409 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3410 | pll->state.hw_state.dpll_md); |
3411 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3412 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3413 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3414 | } |
3415 | drm_modeset_unlock_all(dev); | |
3416 | ||
3417 | return 0; | |
3418 | } | |
3419 | ||
1ed1ef9d | 3420 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3421 | { |
3422 | int i; | |
3423 | int ret; | |
e2f80391 | 3424 | struct intel_engine_cs *engine; |
36cdd013 DW |
3425 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3426 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3427 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3428 | enum intel_engine_id id; |
888b5995 | 3429 | |
888b5995 AS |
3430 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3431 | if (ret) | |
3432 | return ret; | |
3433 | ||
3434 | intel_runtime_pm_get(dev_priv); | |
3435 | ||
33136b06 | 3436 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3437 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3438 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3439 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3440 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3441 | i915_reg_t addr; |
3442 | u32 mask, value, read; | |
2fa60f6d | 3443 | bool ok; |
888b5995 | 3444 | |
33136b06 AS |
3445 | addr = workarounds->reg[i].addr; |
3446 | mask = workarounds->reg[i].mask; | |
3447 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3448 | read = I915_READ(addr); |
3449 | ok = (value & mask) == (read & mask); | |
3450 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3451 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3452 | } |
3453 | ||
3454 | intel_runtime_pm_put(dev_priv); | |
3455 | mutex_unlock(&dev->struct_mutex); | |
3456 | ||
3457 | return 0; | |
3458 | } | |
3459 | ||
c5511e44 DL |
3460 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3461 | { | |
36cdd013 DW |
3462 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3463 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3464 | struct skl_ddb_allocation *ddb; |
3465 | struct skl_ddb_entry *entry; | |
3466 | enum pipe pipe; | |
3467 | int plane; | |
3468 | ||
36cdd013 | 3469 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3470 | return 0; |
3471 | ||
c5511e44 DL |
3472 | drm_modeset_lock_all(dev); |
3473 | ||
3474 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3475 | ||
3476 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3477 | ||
3478 | for_each_pipe(dev_priv, pipe) { | |
3479 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3480 | ||
8b364b41 | 3481 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3482 | entry = &ddb->plane[pipe][plane]; |
3483 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3484 | entry->start, entry->end, | |
3485 | skl_ddb_entry_size(entry)); | |
3486 | } | |
3487 | ||
4969d33e | 3488 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3489 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3490 | entry->end, skl_ddb_entry_size(entry)); | |
3491 | } | |
3492 | ||
3493 | drm_modeset_unlock_all(dev); | |
3494 | ||
3495 | return 0; | |
3496 | } | |
3497 | ||
a54746e3 | 3498 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3499 | struct drm_device *dev, |
3500 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3501 | { |
fac5e23e | 3502 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3503 | struct i915_drrs *drrs = &dev_priv->drrs; |
3504 | int vrefresh = 0; | |
26875fe5 | 3505 | struct drm_connector *connector; |
a54746e3 | 3506 | |
26875fe5 ML |
3507 | drm_for_each_connector(connector, dev) { |
3508 | if (connector->state->crtc != &intel_crtc->base) | |
3509 | continue; | |
3510 | ||
3511 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3512 | } |
3513 | ||
3514 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3515 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3516 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3517 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3518 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3519 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3520 | else | |
3521 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3522 | ||
3523 | seq_puts(m, "\n\n"); | |
3524 | ||
f77076c9 | 3525 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3526 | struct intel_panel *panel; |
3527 | ||
3528 | mutex_lock(&drrs->mutex); | |
3529 | /* DRRS Supported */ | |
3530 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3531 | ||
3532 | /* disable_drrs() will make drrs->dp NULL */ | |
3533 | if (!drrs->dp) { | |
3534 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3535 | mutex_unlock(&drrs->mutex); | |
3536 | return; | |
3537 | } | |
3538 | ||
3539 | panel = &drrs->dp->attached_connector->panel; | |
3540 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3541 | drrs->busy_frontbuffer_bits); | |
3542 | ||
3543 | seq_puts(m, "\n\t\t"); | |
3544 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3545 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3546 | vrefresh = panel->fixed_mode->vrefresh; | |
3547 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3548 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3549 | vrefresh = panel->downclock_mode->vrefresh; | |
3550 | } else { | |
3551 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3552 | drrs->refresh_rate_type); | |
3553 | mutex_unlock(&drrs->mutex); | |
3554 | return; | |
3555 | } | |
3556 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3557 | ||
3558 | seq_puts(m, "\n\t\t"); | |
3559 | mutex_unlock(&drrs->mutex); | |
3560 | } else { | |
3561 | /* DRRS not supported. Print the VBT parameter*/ | |
3562 | seq_puts(m, "\tDRRS Supported : No"); | |
3563 | } | |
3564 | seq_puts(m, "\n"); | |
3565 | } | |
3566 | ||
3567 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3568 | { | |
36cdd013 DW |
3569 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3570 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3571 | struct intel_crtc *intel_crtc; |
3572 | int active_crtc_cnt = 0; | |
3573 | ||
26875fe5 | 3574 | drm_modeset_lock_all(dev); |
a54746e3 | 3575 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3576 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3577 | active_crtc_cnt++; |
3578 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3579 | ||
3580 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3581 | } | |
a54746e3 | 3582 | } |
26875fe5 | 3583 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3584 | |
3585 | if (!active_crtc_cnt) | |
3586 | seq_puts(m, "No active crtc found\n"); | |
3587 | ||
3588 | return 0; | |
3589 | } | |
3590 | ||
11bed958 DA |
3591 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3592 | { | |
36cdd013 DW |
3593 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3594 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3595 | struct intel_encoder *intel_encoder; |
3596 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3597 | struct drm_connector *connector; |
3598 | ||
11bed958 | 3599 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3600 | drm_for_each_connector(connector, dev) { |
3601 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3602 | continue; |
b6dabe3b ML |
3603 | |
3604 | intel_encoder = intel_attached_encoder(connector); | |
3605 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3606 | continue; | |
3607 | ||
3608 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3609 | if (!intel_dig_port->dp.can_mst) |
3610 | continue; | |
b6dabe3b | 3611 | |
40ae80cc JB |
3612 | seq_printf(m, "MST Source Port %c\n", |
3613 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3614 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3615 | } | |
3616 | drm_modeset_unlock_all(dev); | |
3617 | return 0; | |
3618 | } | |
3619 | ||
eb3394fa | 3620 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3621 | const char __user *ubuf, |
3622 | size_t len, loff_t *offp) | |
eb3394fa TP |
3623 | { |
3624 | char *input_buffer; | |
3625 | int status = 0; | |
eb3394fa TP |
3626 | struct drm_device *dev; |
3627 | struct drm_connector *connector; | |
3628 | struct list_head *connector_list; | |
3629 | struct intel_dp *intel_dp; | |
3630 | int val = 0; | |
3631 | ||
9aaffa34 | 3632 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3633 | |
eb3394fa TP |
3634 | connector_list = &dev->mode_config.connector_list; |
3635 | ||
3636 | if (len == 0) | |
3637 | return 0; | |
3638 | ||
3639 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3640 | if (!input_buffer) | |
3641 | return -ENOMEM; | |
3642 | ||
3643 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3644 | status = -EFAULT; | |
3645 | goto out; | |
3646 | } | |
3647 | ||
3648 | input_buffer[len] = '\0'; | |
3649 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3650 | ||
3651 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
3652 | if (connector->connector_type != |
3653 | DRM_MODE_CONNECTOR_DisplayPort) | |
3654 | continue; | |
3655 | ||
b8bb08ec | 3656 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3657 | connector->encoder != NULL) { |
3658 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3659 | status = kstrtoint(input_buffer, 10, &val); | |
3660 | if (status < 0) | |
3661 | goto out; | |
3662 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
3663 | /* To prevent erroneous activation of the compliance | |
3664 | * testing code, only accept an actual value of 1 here | |
3665 | */ | |
3666 | if (val == 1) | |
c1617abc | 3667 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3668 | else |
c1617abc | 3669 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3670 | } |
3671 | } | |
3672 | out: | |
3673 | kfree(input_buffer); | |
3674 | if (status < 0) | |
3675 | return status; | |
3676 | ||
3677 | *offp += len; | |
3678 | return len; | |
3679 | } | |
3680 | ||
3681 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3682 | { | |
3683 | struct drm_device *dev = m->private; | |
3684 | struct drm_connector *connector; | |
3685 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3686 | struct intel_dp *intel_dp; | |
3687 | ||
eb3394fa | 3688 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3689 | if (connector->connector_type != |
3690 | DRM_MODE_CONNECTOR_DisplayPort) | |
3691 | continue; | |
3692 | ||
3693 | if (connector->status == connector_status_connected && | |
3694 | connector->encoder != NULL) { | |
3695 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3696 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3697 | seq_puts(m, "1"); |
3698 | else | |
3699 | seq_puts(m, "0"); | |
3700 | } else | |
3701 | seq_puts(m, "0"); | |
3702 | } | |
3703 | ||
3704 | return 0; | |
3705 | } | |
3706 | ||
3707 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3708 | struct file *file) |
eb3394fa | 3709 | { |
36cdd013 | 3710 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3711 | |
36cdd013 DW |
3712 | return single_open(file, i915_displayport_test_active_show, |
3713 | &dev_priv->drm); | |
eb3394fa TP |
3714 | } |
3715 | ||
3716 | static const struct file_operations i915_displayport_test_active_fops = { | |
3717 | .owner = THIS_MODULE, | |
3718 | .open = i915_displayport_test_active_open, | |
3719 | .read = seq_read, | |
3720 | .llseek = seq_lseek, | |
3721 | .release = single_release, | |
3722 | .write = i915_displayport_test_active_write | |
3723 | }; | |
3724 | ||
3725 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3726 | { | |
3727 | struct drm_device *dev = m->private; | |
3728 | struct drm_connector *connector; | |
3729 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3730 | struct intel_dp *intel_dp; | |
3731 | ||
eb3394fa | 3732 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3733 | if (connector->connector_type != |
3734 | DRM_MODE_CONNECTOR_DisplayPort) | |
3735 | continue; | |
3736 | ||
3737 | if (connector->status == connector_status_connected && | |
3738 | connector->encoder != NULL) { | |
3739 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3740 | seq_printf(m, "%lx", intel_dp->compliance.test_data.edid); |
eb3394fa TP |
3741 | } else |
3742 | seq_puts(m, "0"); | |
3743 | } | |
3744 | ||
3745 | return 0; | |
3746 | } | |
3747 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3748 | struct file *file) |
eb3394fa | 3749 | { |
36cdd013 | 3750 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3751 | |
36cdd013 DW |
3752 | return single_open(file, i915_displayport_test_data_show, |
3753 | &dev_priv->drm); | |
eb3394fa TP |
3754 | } |
3755 | ||
3756 | static const struct file_operations i915_displayport_test_data_fops = { | |
3757 | .owner = THIS_MODULE, | |
3758 | .open = i915_displayport_test_data_open, | |
3759 | .read = seq_read, | |
3760 | .llseek = seq_lseek, | |
3761 | .release = single_release | |
3762 | }; | |
3763 | ||
3764 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3765 | { | |
3766 | struct drm_device *dev = m->private; | |
3767 | struct drm_connector *connector; | |
3768 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3769 | struct intel_dp *intel_dp; | |
3770 | ||
eb3394fa | 3771 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3772 | if (connector->connector_type != |
3773 | DRM_MODE_CONNECTOR_DisplayPort) | |
3774 | continue; | |
3775 | ||
3776 | if (connector->status == connector_status_connected && | |
3777 | connector->encoder != NULL) { | |
3778 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3779 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3780 | } else |
3781 | seq_puts(m, "0"); | |
3782 | } | |
3783 | ||
3784 | return 0; | |
3785 | } | |
3786 | ||
3787 | static int i915_displayport_test_type_open(struct inode *inode, | |
3788 | struct file *file) | |
3789 | { | |
36cdd013 | 3790 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3791 | |
36cdd013 DW |
3792 | return single_open(file, i915_displayport_test_type_show, |
3793 | &dev_priv->drm); | |
eb3394fa TP |
3794 | } |
3795 | ||
3796 | static const struct file_operations i915_displayport_test_type_fops = { | |
3797 | .owner = THIS_MODULE, | |
3798 | .open = i915_displayport_test_type_open, | |
3799 | .read = seq_read, | |
3800 | .llseek = seq_lseek, | |
3801 | .release = single_release | |
3802 | }; | |
3803 | ||
97e94b22 | 3804 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3805 | { |
36cdd013 DW |
3806 | struct drm_i915_private *dev_priv = m->private; |
3807 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3808 | int level; |
de38b95c VS |
3809 | int num_levels; |
3810 | ||
36cdd013 | 3811 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3812 | num_levels = 3; |
36cdd013 | 3813 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3814 | num_levels = 1; |
3815 | else | |
5db94019 | 3816 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3817 | |
3818 | drm_modeset_lock_all(dev); | |
3819 | ||
3820 | for (level = 0; level < num_levels; level++) { | |
3821 | unsigned int latency = wm[level]; | |
3822 | ||
97e94b22 DL |
3823 | /* |
3824 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3825 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3826 | */ |
36cdd013 DW |
3827 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3828 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3829 | latency *= 10; |
3830 | else if (level > 0) | |
369a1342 VS |
3831 | latency *= 5; |
3832 | ||
3833 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3834 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3835 | } |
3836 | ||
3837 | drm_modeset_unlock_all(dev); | |
3838 | } | |
3839 | ||
3840 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3841 | { | |
36cdd013 | 3842 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3843 | const uint16_t *latencies; |
3844 | ||
36cdd013 | 3845 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3846 | latencies = dev_priv->wm.skl_latency; |
3847 | else | |
36cdd013 | 3848 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3849 | |
97e94b22 | 3850 | wm_latency_show(m, latencies); |
369a1342 VS |
3851 | |
3852 | return 0; | |
3853 | } | |
3854 | ||
3855 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3856 | { | |
36cdd013 | 3857 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3858 | const uint16_t *latencies; |
3859 | ||
36cdd013 | 3860 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3861 | latencies = dev_priv->wm.skl_latency; |
3862 | else | |
36cdd013 | 3863 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3864 | |
97e94b22 | 3865 | wm_latency_show(m, latencies); |
369a1342 VS |
3866 | |
3867 | return 0; | |
3868 | } | |
3869 | ||
3870 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3871 | { | |
36cdd013 | 3872 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3873 | const uint16_t *latencies; |
3874 | ||
36cdd013 | 3875 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3876 | latencies = dev_priv->wm.skl_latency; |
3877 | else | |
36cdd013 | 3878 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3879 | |
97e94b22 | 3880 | wm_latency_show(m, latencies); |
369a1342 VS |
3881 | |
3882 | return 0; | |
3883 | } | |
3884 | ||
3885 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3886 | { | |
36cdd013 | 3887 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3888 | |
36cdd013 | 3889 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3890 | return -ENODEV; |
3891 | ||
36cdd013 | 3892 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3893 | } |
3894 | ||
3895 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3896 | { | |
36cdd013 | 3897 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3898 | |
36cdd013 | 3899 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3900 | return -ENODEV; |
3901 | ||
36cdd013 | 3902 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3903 | } |
3904 | ||
3905 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3906 | { | |
36cdd013 | 3907 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3908 | |
36cdd013 | 3909 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3910 | return -ENODEV; |
3911 | ||
36cdd013 | 3912 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3913 | } |
3914 | ||
3915 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3916 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3917 | { |
3918 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3919 | struct drm_i915_private *dev_priv = m->private; |
3920 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3921 | uint16_t new[8] = { 0 }; |
de38b95c | 3922 | int num_levels; |
369a1342 VS |
3923 | int level; |
3924 | int ret; | |
3925 | char tmp[32]; | |
3926 | ||
36cdd013 | 3927 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3928 | num_levels = 3; |
36cdd013 | 3929 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3930 | num_levels = 1; |
3931 | else | |
5db94019 | 3932 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 3933 | |
369a1342 VS |
3934 | if (len >= sizeof(tmp)) |
3935 | return -EINVAL; | |
3936 | ||
3937 | if (copy_from_user(tmp, ubuf, len)) | |
3938 | return -EFAULT; | |
3939 | ||
3940 | tmp[len] = '\0'; | |
3941 | ||
97e94b22 DL |
3942 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3943 | &new[0], &new[1], &new[2], &new[3], | |
3944 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3945 | if (ret != num_levels) |
3946 | return -EINVAL; | |
3947 | ||
3948 | drm_modeset_lock_all(dev); | |
3949 | ||
3950 | for (level = 0; level < num_levels; level++) | |
3951 | wm[level] = new[level]; | |
3952 | ||
3953 | drm_modeset_unlock_all(dev); | |
3954 | ||
3955 | return len; | |
3956 | } | |
3957 | ||
3958 | ||
3959 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3960 | size_t len, loff_t *offp) | |
3961 | { | |
3962 | struct seq_file *m = file->private_data; | |
36cdd013 | 3963 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3964 | uint16_t *latencies; |
369a1342 | 3965 | |
36cdd013 | 3966 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3967 | latencies = dev_priv->wm.skl_latency; |
3968 | else | |
36cdd013 | 3969 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
3970 | |
3971 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3972 | } |
3973 | ||
3974 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3975 | size_t len, loff_t *offp) | |
3976 | { | |
3977 | struct seq_file *m = file->private_data; | |
36cdd013 | 3978 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3979 | uint16_t *latencies; |
369a1342 | 3980 | |
36cdd013 | 3981 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3982 | latencies = dev_priv->wm.skl_latency; |
3983 | else | |
36cdd013 | 3984 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
3985 | |
3986 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3987 | } |
3988 | ||
3989 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3990 | size_t len, loff_t *offp) | |
3991 | { | |
3992 | struct seq_file *m = file->private_data; | |
36cdd013 | 3993 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3994 | uint16_t *latencies; |
3995 | ||
36cdd013 | 3996 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3997 | latencies = dev_priv->wm.skl_latency; |
3998 | else | |
36cdd013 | 3999 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4000 | |
97e94b22 | 4001 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4002 | } |
4003 | ||
4004 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4005 | .owner = THIS_MODULE, | |
4006 | .open = pri_wm_latency_open, | |
4007 | .read = seq_read, | |
4008 | .llseek = seq_lseek, | |
4009 | .release = single_release, | |
4010 | .write = pri_wm_latency_write | |
4011 | }; | |
4012 | ||
4013 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4014 | .owner = THIS_MODULE, | |
4015 | .open = spr_wm_latency_open, | |
4016 | .read = seq_read, | |
4017 | .llseek = seq_lseek, | |
4018 | .release = single_release, | |
4019 | .write = spr_wm_latency_write | |
4020 | }; | |
4021 | ||
4022 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4023 | .owner = THIS_MODULE, | |
4024 | .open = cur_wm_latency_open, | |
4025 | .read = seq_read, | |
4026 | .llseek = seq_lseek, | |
4027 | .release = single_release, | |
4028 | .write = cur_wm_latency_write | |
4029 | }; | |
4030 | ||
647416f9 KC |
4031 | static int |
4032 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4033 | { |
36cdd013 | 4034 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4035 | |
d98c52cf | 4036 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4037 | |
647416f9 | 4038 | return 0; |
f3cd474b CW |
4039 | } |
4040 | ||
647416f9 KC |
4041 | static int |
4042 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4043 | { |
36cdd013 | 4044 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4045 | |
b8d24a06 MK |
4046 | /* |
4047 | * There is no safeguard against this debugfs entry colliding | |
4048 | * with the hangcheck calling same i915_handle_error() in | |
4049 | * parallel, causing an explosion. For now we assume that the | |
4050 | * test harness is responsible enough not to inject gpu hangs | |
4051 | * while it is writing to 'i915_wedged' | |
4052 | */ | |
4053 | ||
d98c52cf | 4054 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4055 | return -EAGAIN; |
4056 | ||
c033666a | 4057 | i915_handle_error(dev_priv, val, |
58174462 | 4058 | "Manually setting wedged to %llu", val); |
d46c0517 | 4059 | |
647416f9 | 4060 | return 0; |
f3cd474b CW |
4061 | } |
4062 | ||
647416f9 KC |
4063 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4064 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4065 | "%llu\n"); |
f3cd474b | 4066 | |
094f9a54 CW |
4067 | static int |
4068 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4069 | { | |
36cdd013 | 4070 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4071 | |
4072 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4073 | return 0; | |
4074 | } | |
4075 | ||
4076 | static int | |
4077 | i915_ring_missed_irq_set(void *data, u64 val) | |
4078 | { | |
36cdd013 DW |
4079 | struct drm_i915_private *dev_priv = data; |
4080 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4081 | int ret; |
4082 | ||
4083 | /* Lock against concurrent debugfs callers */ | |
4084 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4085 | if (ret) | |
4086 | return ret; | |
4087 | dev_priv->gpu_error.missed_irq_rings = val; | |
4088 | mutex_unlock(&dev->struct_mutex); | |
4089 | ||
4090 | return 0; | |
4091 | } | |
4092 | ||
4093 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4094 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4095 | "0x%08llx\n"); | |
4096 | ||
4097 | static int | |
4098 | i915_ring_test_irq_get(void *data, u64 *val) | |
4099 | { | |
36cdd013 | 4100 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4101 | |
4102 | *val = dev_priv->gpu_error.test_irq_rings; | |
4103 | ||
4104 | return 0; | |
4105 | } | |
4106 | ||
4107 | static int | |
4108 | i915_ring_test_irq_set(void *data, u64 val) | |
4109 | { | |
36cdd013 | 4110 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4111 | |
3a122c27 | 4112 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4113 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4114 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4115 | |
4116 | return 0; | |
4117 | } | |
4118 | ||
4119 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4120 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4121 | "0x%08llx\n"); | |
4122 | ||
dd624afd CW |
4123 | #define DROP_UNBOUND 0x1 |
4124 | #define DROP_BOUND 0x2 | |
4125 | #define DROP_RETIRE 0x4 | |
4126 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4127 | #define DROP_FREED 0x10 |
4128 | #define DROP_ALL (DROP_UNBOUND | \ | |
4129 | DROP_BOUND | \ | |
4130 | DROP_RETIRE | \ | |
4131 | DROP_ACTIVE | \ | |
4132 | DROP_FREED) | |
647416f9 KC |
4133 | static int |
4134 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4135 | { |
647416f9 | 4136 | *val = DROP_ALL; |
dd624afd | 4137 | |
647416f9 | 4138 | return 0; |
dd624afd CW |
4139 | } |
4140 | ||
647416f9 KC |
4141 | static int |
4142 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4143 | { |
36cdd013 DW |
4144 | struct drm_i915_private *dev_priv = data; |
4145 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4146 | int ret; |
dd624afd | 4147 | |
2f9fe5ff | 4148 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4149 | |
4150 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4151 | * on ioctls on -EAGAIN. */ | |
4152 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4153 | if (ret) | |
4154 | return ret; | |
4155 | ||
4156 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4157 | ret = i915_gem_wait_for_idle(dev_priv, |
4158 | I915_WAIT_INTERRUPTIBLE | | |
4159 | I915_WAIT_LOCKED); | |
dd624afd CW |
4160 | if (ret) |
4161 | goto unlock; | |
4162 | } | |
4163 | ||
4164 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4165 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4166 | |
21ab4e74 CW |
4167 | if (val & DROP_BOUND) |
4168 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4169 | |
21ab4e74 CW |
4170 | if (val & DROP_UNBOUND) |
4171 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4172 | |
4173 | unlock: | |
4174 | mutex_unlock(&dev->struct_mutex); | |
4175 | ||
fbbd37b3 CW |
4176 | if (val & DROP_FREED) { |
4177 | synchronize_rcu(); | |
bdeb9785 | 4178 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4179 | } |
4180 | ||
647416f9 | 4181 | return ret; |
dd624afd CW |
4182 | } |
4183 | ||
647416f9 KC |
4184 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4185 | i915_drop_caches_get, i915_drop_caches_set, | |
4186 | "0x%08llx\n"); | |
dd624afd | 4187 | |
647416f9 KC |
4188 | static int |
4189 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4190 | { |
36cdd013 | 4191 | struct drm_i915_private *dev_priv = data; |
004777cb | 4192 | |
36cdd013 | 4193 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4194 | return -ENODEV; |
4195 | ||
7c59a9c1 | 4196 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4197 | return 0; |
358733e9 JB |
4198 | } |
4199 | ||
647416f9 KC |
4200 | static int |
4201 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4202 | { |
36cdd013 | 4203 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4204 | u32 hw_max, hw_min; |
647416f9 | 4205 | int ret; |
004777cb | 4206 | |
36cdd013 | 4207 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4208 | return -ENODEV; |
358733e9 | 4209 | |
647416f9 | 4210 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4211 | |
4fc688ce | 4212 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4213 | if (ret) |
4214 | return ret; | |
4215 | ||
358733e9 JB |
4216 | /* |
4217 | * Turbo will still be enabled, but won't go above the set value. | |
4218 | */ | |
bc4d91f6 | 4219 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4220 | |
bc4d91f6 AG |
4221 | hw_max = dev_priv->rps.max_freq; |
4222 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4223 | |
b39fb297 | 4224 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4225 | mutex_unlock(&dev_priv->rps.hw_lock); |
4226 | return -EINVAL; | |
0a073b84 JB |
4227 | } |
4228 | ||
b39fb297 | 4229 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4230 | |
dc97997a | 4231 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4232 | |
4fc688ce | 4233 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4234 | |
647416f9 | 4235 | return 0; |
358733e9 JB |
4236 | } |
4237 | ||
647416f9 KC |
4238 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4239 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4240 | "%llu\n"); |
358733e9 | 4241 | |
647416f9 KC |
4242 | static int |
4243 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4244 | { |
36cdd013 | 4245 | struct drm_i915_private *dev_priv = data; |
004777cb | 4246 | |
62e1baa1 | 4247 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4248 | return -ENODEV; |
4249 | ||
7c59a9c1 | 4250 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4251 | return 0; |
1523c310 JB |
4252 | } |
4253 | ||
647416f9 KC |
4254 | static int |
4255 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4256 | { |
36cdd013 | 4257 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4258 | u32 hw_max, hw_min; |
647416f9 | 4259 | int ret; |
004777cb | 4260 | |
62e1baa1 | 4261 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4262 | return -ENODEV; |
1523c310 | 4263 | |
647416f9 | 4264 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4265 | |
4fc688ce | 4266 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4267 | if (ret) |
4268 | return ret; | |
4269 | ||
1523c310 JB |
4270 | /* |
4271 | * Turbo will still be enabled, but won't go below the set value. | |
4272 | */ | |
bc4d91f6 | 4273 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4274 | |
bc4d91f6 AG |
4275 | hw_max = dev_priv->rps.max_freq; |
4276 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4277 | |
36cdd013 DW |
4278 | if (val < hw_min || |
4279 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4280 | mutex_unlock(&dev_priv->rps.hw_lock); |
4281 | return -EINVAL; | |
0a073b84 | 4282 | } |
dd0a1aa1 | 4283 | |
b39fb297 | 4284 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4285 | |
dc97997a | 4286 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4287 | |
4fc688ce | 4288 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4289 | |
647416f9 | 4290 | return 0; |
1523c310 JB |
4291 | } |
4292 | ||
647416f9 KC |
4293 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4294 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4295 | "%llu\n"); |
1523c310 | 4296 | |
647416f9 KC |
4297 | static int |
4298 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4299 | { |
36cdd013 | 4300 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4301 | u32 snpcr; |
07b7ddd9 | 4302 | |
36cdd013 | 4303 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4304 | return -ENODEV; |
4305 | ||
c8c8fb33 | 4306 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4307 | |
07b7ddd9 | 4308 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4309 | |
4310 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4311 | |
647416f9 | 4312 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4313 | |
647416f9 | 4314 | return 0; |
07b7ddd9 JB |
4315 | } |
4316 | ||
647416f9 KC |
4317 | static int |
4318 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4319 | { |
36cdd013 | 4320 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4321 | u32 snpcr; |
07b7ddd9 | 4322 | |
36cdd013 | 4323 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4324 | return -ENODEV; |
4325 | ||
647416f9 | 4326 | if (val > 3) |
07b7ddd9 JB |
4327 | return -EINVAL; |
4328 | ||
c8c8fb33 | 4329 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4330 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4331 | |
4332 | /* Update the cache sharing policy here as well */ | |
4333 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4334 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4335 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4336 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4337 | ||
c8c8fb33 | 4338 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4339 | return 0; |
07b7ddd9 JB |
4340 | } |
4341 | ||
647416f9 KC |
4342 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4343 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4344 | "%llu\n"); | |
07b7ddd9 | 4345 | |
36cdd013 | 4346 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4347 | struct sseu_dev_info *sseu) |
5d39525a | 4348 | { |
0a0b457f | 4349 | int ss_max = 2; |
5d39525a JM |
4350 | int ss; |
4351 | u32 sig1[ss_max], sig2[ss_max]; | |
4352 | ||
4353 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4354 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4355 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4356 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4357 | ||
4358 | for (ss = 0; ss < ss_max; ss++) { | |
4359 | unsigned int eu_cnt; | |
4360 | ||
4361 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4362 | /* skip disabled subslice */ | |
4363 | continue; | |
4364 | ||
f08a0c92 | 4365 | sseu->slice_mask = BIT(0); |
57ec171e | 4366 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4367 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4368 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4369 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4370 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4371 | sseu->eu_total += eu_cnt; |
4372 | sseu->eu_per_subslice = max_t(unsigned int, | |
4373 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4374 | } |
5d39525a JM |
4375 | } |
4376 | ||
36cdd013 | 4377 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4378 | struct sseu_dev_info *sseu) |
5d39525a | 4379 | { |
1c046bc1 | 4380 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4381 | int s, ss; |
4382 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4383 | ||
1c046bc1 | 4384 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4385 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4386 | s_max = 1; |
4387 | ss_max = 3; | |
4388 | } | |
4389 | ||
4390 | for (s = 0; s < s_max; s++) { | |
4391 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4392 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4393 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4394 | } | |
4395 | ||
5d39525a JM |
4396 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4397 | GEN9_PGCTL_SSA_EU19_ACK | | |
4398 | GEN9_PGCTL_SSA_EU210_ACK | | |
4399 | GEN9_PGCTL_SSA_EU311_ACK; | |
4400 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4401 | GEN9_PGCTL_SSB_EU19_ACK | | |
4402 | GEN9_PGCTL_SSB_EU210_ACK | | |
4403 | GEN9_PGCTL_SSB_EU311_ACK; | |
4404 | ||
4405 | for (s = 0; s < s_max; s++) { | |
4406 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4407 | /* skip disabled slice */ | |
4408 | continue; | |
4409 | ||
f08a0c92 | 4410 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4411 | |
36cdd013 | 4412 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
4413 | sseu->subslice_mask = |
4414 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4415 | |
5d39525a JM |
4416 | for (ss = 0; ss < ss_max; ss++) { |
4417 | unsigned int eu_cnt; | |
4418 | ||
cc3f90f0 | 4419 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4420 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4421 | /* skip disabled subslice */ | |
4422 | continue; | |
1c046bc1 | 4423 | |
57ec171e ID |
4424 | sseu->subslice_mask |= BIT(ss); |
4425 | } | |
1c046bc1 | 4426 | |
5d39525a JM |
4427 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4428 | eu_mask[ss%2]); | |
915490d5 ID |
4429 | sseu->eu_total += eu_cnt; |
4430 | sseu->eu_per_subslice = max_t(unsigned int, | |
4431 | sseu->eu_per_subslice, | |
4432 | eu_cnt); | |
5d39525a JM |
4433 | } |
4434 | } | |
4435 | } | |
4436 | ||
36cdd013 | 4437 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4438 | struct sseu_dev_info *sseu) |
91bedd34 | 4439 | { |
91bedd34 | 4440 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4441 | int s; |
91bedd34 | 4442 | |
f08a0c92 | 4443 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4444 | |
f08a0c92 | 4445 | if (sseu->slice_mask) { |
57ec171e | 4446 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4447 | sseu->eu_per_subslice = |
4448 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4449 | sseu->eu_total = sseu->eu_per_subslice * |
4450 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4451 | |
4452 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4453 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4454 | u8 subslice_7eu = |
4455 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4456 | |
915490d5 | 4457 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4458 | } |
4459 | } | |
4460 | } | |
4461 | ||
615d8908 ID |
4462 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4463 | const struct sseu_dev_info *sseu) | |
4464 | { | |
4465 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4466 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4467 | ||
c67ba538 ID |
4468 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4469 | sseu->slice_mask); | |
615d8908 | 4470 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4471 | hweight8(sseu->slice_mask)); |
615d8908 | 4472 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4473 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4474 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4475 | sseu->subslice_mask); | |
615d8908 | 4476 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4477 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4478 | seq_printf(m, " %s EU Total: %u\n", type, |
4479 | sseu->eu_total); | |
4480 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4481 | sseu->eu_per_subslice); | |
4482 | ||
4483 | if (!is_available_info) | |
4484 | return; | |
4485 | ||
4486 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4487 | if (HAS_POOLED_EU(dev_priv)) | |
4488 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4489 | ||
4490 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4491 | yesno(sseu->has_slice_pg)); | |
4492 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4493 | yesno(sseu->has_subslice_pg)); | |
4494 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4495 | yesno(sseu->has_eu_pg)); | |
4496 | } | |
4497 | ||
3873218f JM |
4498 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4499 | { | |
36cdd013 | 4500 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4501 | struct sseu_dev_info sseu; |
3873218f | 4502 | |
36cdd013 | 4503 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4504 | return -ENODEV; |
4505 | ||
4506 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4507 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4508 | |
7f992aba | 4509 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4510 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4511 | |
4512 | intel_runtime_pm_get(dev_priv); | |
4513 | ||
36cdd013 | 4514 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4515 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4516 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4517 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4518 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4519 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4520 | } |
238010ed DW |
4521 | |
4522 | intel_runtime_pm_put(dev_priv); | |
4523 | ||
615d8908 | 4524 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4525 | |
3873218f JM |
4526 | return 0; |
4527 | } | |
4528 | ||
6d794d42 BW |
4529 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4530 | { | |
36cdd013 | 4531 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4532 | |
36cdd013 | 4533 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4534 | return 0; |
4535 | ||
6daccb0b | 4536 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4537 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4538 | |
4539 | return 0; | |
4540 | } | |
4541 | ||
c43b5634 | 4542 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4543 | { |
36cdd013 | 4544 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4545 | |
36cdd013 | 4546 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4547 | return 0; |
4548 | ||
59bad947 | 4549 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4550 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4551 | |
4552 | return 0; | |
4553 | } | |
4554 | ||
4555 | static const struct file_operations i915_forcewake_fops = { | |
4556 | .owner = THIS_MODULE, | |
4557 | .open = i915_forcewake_open, | |
4558 | .release = i915_forcewake_release, | |
4559 | }; | |
4560 | ||
4561 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4562 | { | |
6d794d42 BW |
4563 | struct dentry *ent; |
4564 | ||
4565 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4566 | S_IRUSR, |
36cdd013 | 4567 | root, to_i915(minor->dev), |
6d794d42 | 4568 | &i915_forcewake_fops); |
f3c5fe97 WY |
4569 | if (!ent) |
4570 | return -ENOMEM; | |
6d794d42 | 4571 | |
8eb57294 | 4572 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4573 | } |
4574 | ||
6a9c308d DV |
4575 | static int i915_debugfs_create(struct dentry *root, |
4576 | struct drm_minor *minor, | |
4577 | const char *name, | |
4578 | const struct file_operations *fops) | |
07b7ddd9 | 4579 | { |
07b7ddd9 JB |
4580 | struct dentry *ent; |
4581 | ||
6a9c308d | 4582 | ent = debugfs_create_file(name, |
07b7ddd9 | 4583 | S_IRUGO | S_IWUSR, |
36cdd013 | 4584 | root, to_i915(minor->dev), |
6a9c308d | 4585 | fops); |
f3c5fe97 WY |
4586 | if (!ent) |
4587 | return -ENOMEM; | |
07b7ddd9 | 4588 | |
6a9c308d | 4589 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4590 | } |
4591 | ||
06c5bf8c | 4592 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4593 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4594 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4595 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4596 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4597 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4598 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4599 | {"i915_gem_request", i915_gem_request_info, 0}, |
4600 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4601 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4602 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4603 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4604 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4605 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4606 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 4607 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4608 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4609 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4610 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4611 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4612 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4613 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4614 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4615 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4616 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4617 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4618 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4619 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4620 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4621 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4622 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4623 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4624 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4625 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4626 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4627 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4628 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4629 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4630 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4631 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4632 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4633 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4634 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4635 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4636 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4637 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4638 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4639 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4640 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4641 | }; |
27c202ad | 4642 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4643 | |
06c5bf8c | 4644 | static const struct i915_debugfs_files { |
34b9674c DV |
4645 | const char *name; |
4646 | const struct file_operations *fops; | |
4647 | } i915_debugfs_files[] = { | |
4648 | {"i915_wedged", &i915_wedged_fops}, | |
4649 | {"i915_max_freq", &i915_max_freq_fops}, | |
4650 | {"i915_min_freq", &i915_min_freq_fops}, | |
4651 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4652 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4653 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4654 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4655 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4656 | {"i915_error_state", &i915_error_state_fops}, |
98a2f411 | 4657 | #endif |
34b9674c | 4658 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4659 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4660 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4661 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4662 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4663 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4664 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4665 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef SAK |
4666 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
4667 | {"i915_guc_log_control", &i915_guc_log_control_fops} | |
34b9674c DV |
4668 | }; |
4669 | ||
1dac891c | 4670 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4671 | { |
91c8a326 | 4672 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 4673 | int ret, i; |
f3cd474b | 4674 | |
6d794d42 | 4675 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4676 | if (ret) |
4677 | return ret; | |
6a9c308d | 4678 | |
731035fe TV |
4679 | ret = intel_pipe_crc_create(minor); |
4680 | if (ret) | |
4681 | return ret; | |
07144428 | 4682 | |
34b9674c DV |
4683 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4684 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4685 | i915_debugfs_files[i].name, | |
4686 | i915_debugfs_files[i].fops); | |
4687 | if (ret) | |
4688 | return ret; | |
4689 | } | |
40633219 | 4690 | |
27c202ad BG |
4691 | return drm_debugfs_create_files(i915_debugfs_list, |
4692 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4693 | minor->debugfs_root, minor); |
4694 | } | |
4695 | ||
1dac891c | 4696 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 4697 | { |
91c8a326 | 4698 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
4699 | int i; |
4700 | ||
27c202ad BG |
4701 | drm_debugfs_remove_files(i915_debugfs_list, |
4702 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4703 | |
36cdd013 | 4704 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 4705 | 1, minor); |
07144428 | 4706 | |
731035fe | 4707 | intel_pipe_crc_cleanup(minor); |
07144428 | 4708 | |
34b9674c DV |
4709 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4710 | struct drm_info_list *info_list = | |
36cdd013 | 4711 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
4712 | |
4713 | drm_debugfs_remove_files(info_list, 1, minor); | |
4714 | } | |
2017263e | 4715 | } |
aa7471d2 JN |
4716 | |
4717 | struct dpcd_block { | |
4718 | /* DPCD dump start address. */ | |
4719 | unsigned int offset; | |
4720 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4721 | unsigned int end; | |
4722 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4723 | size_t size; | |
4724 | /* Only valid for eDP. */ | |
4725 | bool edp; | |
4726 | }; | |
4727 | ||
4728 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4729 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4730 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4731 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4732 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4733 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4734 | { .offset = DP_SET_POWER }, | |
4735 | { .offset = DP_EDP_DPCD_REV }, | |
4736 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4737 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4738 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4739 | }; | |
4740 | ||
4741 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4742 | { | |
4743 | struct drm_connector *connector = m->private; | |
4744 | struct intel_dp *intel_dp = | |
4745 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4746 | uint8_t buf[16]; | |
4747 | ssize_t err; | |
4748 | int i; | |
4749 | ||
5c1a8875 MK |
4750 | if (connector->status != connector_status_connected) |
4751 | return -ENODEV; | |
4752 | ||
aa7471d2 JN |
4753 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4754 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4755 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4756 | ||
4757 | if (b->edp && | |
4758 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4759 | continue; | |
4760 | ||
4761 | /* low tech for now */ | |
4762 | if (WARN_ON(size > sizeof(buf))) | |
4763 | continue; | |
4764 | ||
4765 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4766 | if (err <= 0) { | |
4767 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4768 | size, b->offset, err); | |
4769 | continue; | |
4770 | } | |
4771 | ||
4772 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4773 | } |
aa7471d2 JN |
4774 | |
4775 | return 0; | |
4776 | } | |
4777 | ||
4778 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4779 | { | |
4780 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4781 | } | |
4782 | ||
4783 | static const struct file_operations i915_dpcd_fops = { | |
4784 | .owner = THIS_MODULE, | |
4785 | .open = i915_dpcd_open, | |
4786 | .read = seq_read, | |
4787 | .llseek = seq_lseek, | |
4788 | .release = single_release, | |
4789 | }; | |
4790 | ||
ecbd6781 DW |
4791 | static int i915_panel_show(struct seq_file *m, void *data) |
4792 | { | |
4793 | struct drm_connector *connector = m->private; | |
4794 | struct intel_dp *intel_dp = | |
4795 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4796 | ||
4797 | if (connector->status != connector_status_connected) | |
4798 | return -ENODEV; | |
4799 | ||
4800 | seq_printf(m, "Panel power up delay: %d\n", | |
4801 | intel_dp->panel_power_up_delay); | |
4802 | seq_printf(m, "Panel power down delay: %d\n", | |
4803 | intel_dp->panel_power_down_delay); | |
4804 | seq_printf(m, "Backlight on delay: %d\n", | |
4805 | intel_dp->backlight_on_delay); | |
4806 | seq_printf(m, "Backlight off delay: %d\n", | |
4807 | intel_dp->backlight_off_delay); | |
4808 | ||
4809 | return 0; | |
4810 | } | |
4811 | ||
4812 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4813 | { | |
4814 | return single_open(file, i915_panel_show, inode->i_private); | |
4815 | } | |
4816 | ||
4817 | static const struct file_operations i915_panel_fops = { | |
4818 | .owner = THIS_MODULE, | |
4819 | .open = i915_panel_open, | |
4820 | .read = seq_read, | |
4821 | .llseek = seq_lseek, | |
4822 | .release = single_release, | |
4823 | }; | |
4824 | ||
aa7471d2 JN |
4825 | /** |
4826 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4827 | * @connector: pointer to a registered drm_connector | |
4828 | * | |
4829 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4830 | * drm_debugfs_connector_remove(). | |
4831 | * | |
4832 | * Returns 0 on success, negative error codes on error. | |
4833 | */ | |
4834 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4835 | { | |
4836 | struct dentry *root = connector->debugfs_entry; | |
4837 | ||
4838 | /* The connector must have been registered beforehands. */ | |
4839 | if (!root) | |
4840 | return -ENODEV; | |
4841 | ||
4842 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4843 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4844 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4845 | connector, &i915_dpcd_fops); | |
4846 | ||
4847 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4848 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4849 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4850 | |
4851 | return 0; | |
4852 | } |