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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
6d2b8885 | 30 | #include <linux/list_sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
497666d8 DL |
38 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
39 | * allocated we need to hook into the minor for release. */ | |
40 | static int | |
41 | drm_add_fake_info_node(struct drm_minor *minor, | |
42 | struct dentry *ent, | |
43 | const void *key) | |
44 | { | |
45 | struct drm_info_node *node; | |
46 | ||
47 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
48 | if (node == NULL) { | |
49 | debugfs_remove(ent); | |
50 | return -ENOMEM; | |
51 | } | |
52 | ||
53 | node->minor = minor; | |
54 | node->dent = ent; | |
36cdd013 | 55 | node->info_ent = (void *)key; |
497666d8 DL |
56 | |
57 | mutex_lock(&minor->debugfs_lock); | |
58 | list_add(&node->list, &minor->debugfs_list); | |
59 | mutex_unlock(&minor->debugfs_lock); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
70d39fe4 CW |
64 | static int i915_capabilities(struct seq_file *m, void *data) |
65 | { | |
36cdd013 DW |
66 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
67 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 68 | |
36cdd013 | 69 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 70 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 71 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
79fc46df | 72 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 73 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 74 | #undef PRINT_FLAG |
70d39fe4 CW |
75 | |
76 | return 0; | |
77 | } | |
2017263e | 78 | |
a7363de7 | 79 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 80 | { |
573adb39 | 81 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
82 | } |
83 | ||
a7363de7 | 84 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
85 | { |
86 | return obj->pin_display ? 'p' : ' '; | |
87 | } | |
88 | ||
a7363de7 | 89 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 90 | { |
3e510a8e | 91 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 92 | default: |
be12a86b TU |
93 | case I915_TILING_NONE: return ' '; |
94 | case I915_TILING_X: return 'X'; | |
95 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 96 | } |
a6172a80 CW |
97 | } |
98 | ||
a7363de7 | 99 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 100 | { |
275f039d | 101 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
102 | } |
103 | ||
a7363de7 | 104 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 105 | { |
a4f5ea64 | 106 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
107 | } |
108 | ||
ca1543be TU |
109 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
110 | { | |
111 | u64 size = 0; | |
112 | struct i915_vma *vma; | |
113 | ||
1c7f4bca | 114 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 115 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
116 | size += vma->node.size; |
117 | } | |
118 | ||
119 | return size; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
b4716185 | 125 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 126 | struct intel_engine_cs *engine; |
1d693bcc | 127 | struct i915_vma *vma; |
faf5bf0a | 128 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
129 | int pin_count = 0; |
130 | ||
188c1ab7 CW |
131 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
132 | ||
d07f0e59 | 133 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 134 | &obj->base, |
be12a86b | 135 | get_active_flag(obj), |
37811fcc CW |
136 | get_pin_flag(obj), |
137 | get_tiling_flag(obj), | |
1d693bcc | 138 | get_global_flag(obj), |
be12a86b | 139 | get_pin_mapped_flag(obj), |
a05a5862 | 140 | obj->base.size / 1024, |
37811fcc | 141 | obj->base.read_domains, |
d07f0e59 | 142 | obj->base.write_domain, |
36cdd013 | 143 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
144 | obj->mm.dirty ? " dirty" : "", |
145 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
146 | if (obj->base.name) |
147 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 148 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 149 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 150 | pin_count++; |
ba0635ff DC |
151 | } |
152 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
153 | if (obj->pin_display) |
154 | seq_printf(m, " (display)"); | |
1c7f4bca | 155 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
156 | if (!drm_mm_node_allocated(&vma->node)) |
157 | continue; | |
158 | ||
8d2fdc3f | 159 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 160 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 161 | vma->node.start, vma->node.size); |
3272db53 | 162 | if (i915_vma_is_ggtt(vma)) |
596c5923 | 163 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
49ef5294 CW |
164 | if (vma->fence) |
165 | seq_printf(m, " , fence: %d%s", | |
166 | vma->fence->id, | |
167 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 168 | seq_puts(m, ")"); |
1d693bcc | 169 | } |
c1ad11fc | 170 | if (obj->stolen) |
440fd528 | 171 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 172 | |
d07f0e59 | 173 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
174 | if (engine) |
175 | seq_printf(m, " (%s)", engine->name); | |
176 | ||
faf5bf0a CW |
177 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
178 | if (frontbuffer_bits) | |
179 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
180 | } |
181 | ||
6d2b8885 CW |
182 | static int obj_rank_by_stolen(void *priv, |
183 | struct list_head *A, struct list_head *B) | |
184 | { | |
185 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 186 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 187 | struct drm_i915_gem_object *b = |
b25cb2f8 | 188 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 189 | |
2d05fa16 RV |
190 | if (a->stolen->start < b->stolen->start) |
191 | return -1; | |
192 | if (a->stolen->start > b->stolen->start) | |
193 | return 1; | |
194 | return 0; | |
6d2b8885 CW |
195 | } |
196 | ||
197 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
198 | { | |
36cdd013 DW |
199 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
200 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 201 | struct drm_i915_gem_object *obj; |
c44ef60e | 202 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
203 | LIST_HEAD(stolen); |
204 | int count, ret; | |
205 | ||
206 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
207 | if (ret) | |
208 | return ret; | |
209 | ||
210 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 211 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
212 | if (obj->stolen == NULL) |
213 | continue; | |
214 | ||
b25cb2f8 | 215 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
216 | |
217 | total_obj_size += obj->base.size; | |
ca1543be | 218 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
219 | count++; |
220 | } | |
56cea323 | 221 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
222 | if (obj->stolen == NULL) |
223 | continue; | |
224 | ||
b25cb2f8 | 225 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
226 | |
227 | total_obj_size += obj->base.size; | |
228 | count++; | |
229 | } | |
230 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
231 | seq_puts(m, "Stolen:\n"); | |
232 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 233 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
234 | seq_puts(m, " "); |
235 | describe_obj(m, obj); | |
236 | seq_putc(m, '\n'); | |
b25cb2f8 | 237 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
238 | } |
239 | mutex_unlock(&dev->struct_mutex); | |
240 | ||
c44ef60e | 241 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
242 | count, total_obj_size, total_gtt_size); |
243 | return 0; | |
244 | } | |
245 | ||
2db8e9d6 | 246 | struct file_stats { |
6313c204 | 247 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
248 | unsigned long count; |
249 | u64 total, unbound; | |
250 | u64 global, shared; | |
251 | u64 active, inactive; | |
2db8e9d6 CW |
252 | }; |
253 | ||
254 | static int per_file_stats(int id, void *ptr, void *data) | |
255 | { | |
256 | struct drm_i915_gem_object *obj = ptr; | |
257 | struct file_stats *stats = data; | |
6313c204 | 258 | struct i915_vma *vma; |
2db8e9d6 CW |
259 | |
260 | stats->count++; | |
261 | stats->total += obj->base.size; | |
15717de2 CW |
262 | if (!obj->bind_count) |
263 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
264 | if (obj->base.name || obj->base.dma_buf) |
265 | stats->shared += obj->base.size; | |
266 | ||
894eeecc CW |
267 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
268 | if (!drm_mm_node_allocated(&vma->node)) | |
269 | continue; | |
6313c204 | 270 | |
3272db53 | 271 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
272 | stats->global += vma->node.size; |
273 | } else { | |
274 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 275 | |
2bfa996e | 276 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 277 | continue; |
6313c204 | 278 | } |
894eeecc | 279 | |
b0decaf7 | 280 | if (i915_vma_is_active(vma)) |
894eeecc CW |
281 | stats->active += vma->node.size; |
282 | else | |
283 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
284 | } |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
b0da1b79 CW |
289 | #define print_file_stats(m, name, stats) do { \ |
290 | if (stats.count) \ | |
c44ef60e | 291 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
292 | name, \ |
293 | stats.count, \ | |
294 | stats.total, \ | |
295 | stats.active, \ | |
296 | stats.inactive, \ | |
297 | stats.global, \ | |
298 | stats.shared, \ | |
299 | stats.unbound); \ | |
300 | } while (0) | |
493018dc BV |
301 | |
302 | static void print_batch_pool_stats(struct seq_file *m, | |
303 | struct drm_i915_private *dev_priv) | |
304 | { | |
305 | struct drm_i915_gem_object *obj; | |
306 | struct file_stats stats; | |
e2f80391 | 307 | struct intel_engine_cs *engine; |
3b3f1650 | 308 | enum intel_engine_id id; |
b4ac5afc | 309 | int j; |
493018dc BV |
310 | |
311 | memset(&stats, 0, sizeof(stats)); | |
312 | ||
3b3f1650 | 313 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 314 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 315 | list_for_each_entry(obj, |
e2f80391 | 316 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
317 | batch_pool_link) |
318 | per_file_stats(0, obj, &stats); | |
319 | } | |
06fbca71 | 320 | } |
493018dc | 321 | |
b0da1b79 | 322 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
323 | } |
324 | ||
15da9565 CW |
325 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
326 | { | |
327 | struct i915_gem_context *ctx = ptr; | |
328 | int n; | |
329 | ||
330 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
331 | if (ctx->engine[n].state) | |
bf3783e5 | 332 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 333 | if (ctx->engine[n].ring) |
57e88531 | 334 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
335 | } |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static void print_context_stats(struct seq_file *m, | |
341 | struct drm_i915_private *dev_priv) | |
342 | { | |
36cdd013 | 343 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
344 | struct file_stats stats; |
345 | struct drm_file *file; | |
346 | ||
347 | memset(&stats, 0, sizeof(stats)); | |
348 | ||
36cdd013 | 349 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
350 | if (dev_priv->kernel_context) |
351 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
352 | ||
36cdd013 | 353 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
354 | struct drm_i915_file_private *fpriv = file->driver_priv; |
355 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
356 | } | |
36cdd013 | 357 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
358 | |
359 | print_file_stats(m, "[k]contexts", stats); | |
360 | } | |
361 | ||
36cdd013 | 362 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 363 | { |
36cdd013 DW |
364 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
365 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 366 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
367 | u32 count, mapped_count, purgeable_count, dpy_count; |
368 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 369 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 370 | struct drm_file *file; |
73aa808f CW |
371 | int ret; |
372 | ||
373 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
3ef7f228 | 377 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
378 | dev_priv->mm.object_count, |
379 | dev_priv->mm.object_memory); | |
380 | ||
1544c42e CW |
381 | size = count = 0; |
382 | mapped_size = mapped_count = 0; | |
383 | purgeable_size = purgeable_count = 0; | |
56cea323 | 384 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
385 | size += obj->base.size; |
386 | ++count; | |
387 | ||
a4f5ea64 | 388 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
389 | purgeable_size += obj->base.size; |
390 | ++purgeable_count; | |
391 | } | |
392 | ||
a4f5ea64 | 393 | if (obj->mm.mapping) { |
2bd160a1 CW |
394 | mapped_count++; |
395 | mapped_size += obj->base.size; | |
be19b10d | 396 | } |
b7abb714 | 397 | } |
c44ef60e | 398 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 399 | |
2bd160a1 | 400 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 401 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
402 | size += obj->base.size; |
403 | ++count; | |
404 | ||
30154650 | 405 | if (obj->pin_display) { |
2bd160a1 CW |
406 | dpy_size += obj->base.size; |
407 | ++dpy_count; | |
6299f992 | 408 | } |
2bd160a1 | 409 | |
a4f5ea64 | 410 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
411 | purgeable_size += obj->base.size; |
412 | ++purgeable_count; | |
413 | } | |
2bd160a1 | 414 | |
a4f5ea64 | 415 | if (obj->mm.mapping) { |
2bd160a1 CW |
416 | mapped_count++; |
417 | mapped_size += obj->base.size; | |
be19b10d | 418 | } |
6299f992 | 419 | } |
2bd160a1 CW |
420 | seq_printf(m, "%u bound objects, %llu bytes\n", |
421 | count, size); | |
c44ef60e | 422 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 423 | purgeable_count, purgeable_size); |
2bd160a1 CW |
424 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
425 | mapped_count, mapped_size); | |
426 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
427 | dpy_count, dpy_size); | |
6299f992 | 428 | |
c44ef60e | 429 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 430 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 431 | |
493018dc BV |
432 | seq_putc(m, '\n'); |
433 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
434 | mutex_unlock(&dev->struct_mutex); |
435 | ||
436 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 437 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
438 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
439 | struct file_stats stats; | |
c84455b4 CW |
440 | struct drm_i915_file_private *file_priv = file->driver_priv; |
441 | struct drm_i915_gem_request *request; | |
3ec2f427 | 442 | struct task_struct *task; |
2db8e9d6 CW |
443 | |
444 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 445 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 446 | spin_lock(&file->table_lock); |
2db8e9d6 | 447 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 448 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
449 | /* |
450 | * Although we have a valid reference on file->pid, that does | |
451 | * not guarantee that the task_struct who called get_pid() is | |
452 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
453 | * Therefore, we need to protect this ->comm access using RCU. | |
454 | */ | |
c84455b4 CW |
455 | mutex_lock(&dev->struct_mutex); |
456 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
457 | struct drm_i915_gem_request, | |
458 | client_list); | |
3ec2f427 | 459 | rcu_read_lock(); |
c84455b4 CW |
460 | task = pid_task(request && request->ctx->pid ? |
461 | request->ctx->pid : file->pid, | |
462 | PIDTYPE_PID); | |
493018dc | 463 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 464 | rcu_read_unlock(); |
c84455b4 | 465 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 466 | } |
1d2ac403 | 467 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
aee56cff | 472 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 473 | { |
9f25d007 | 474 | struct drm_info_node *node = m->private; |
36cdd013 DW |
475 | struct drm_i915_private *dev_priv = node_to_i915(node); |
476 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 477 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 478 | struct drm_i915_gem_object *obj; |
c44ef60e | 479 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
480 | int count, ret; |
481 | ||
482 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
486 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 487 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 488 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
489 | continue; |
490 | ||
267f0c90 | 491 | seq_puts(m, " "); |
08c18323 | 492 | describe_obj(m, obj); |
267f0c90 | 493 | seq_putc(m, '\n'); |
08c18323 | 494 | total_obj_size += obj->base.size; |
ca1543be | 495 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
496 | count++; |
497 | } | |
498 | ||
499 | mutex_unlock(&dev->struct_mutex); | |
500 | ||
c44ef60e | 501 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
502 | count, total_obj_size, total_gtt_size); |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
4e5359cd SF |
507 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
508 | { | |
36cdd013 DW |
509 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
510 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 511 | struct intel_crtc *crtc; |
8a270ebf DV |
512 | int ret; |
513 | ||
514 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
515 | if (ret) | |
516 | return ret; | |
4e5359cd | 517 | |
d3fcc808 | 518 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
519 | const char pipe = pipe_name(crtc->pipe); |
520 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 521 | struct intel_flip_work *work; |
4e5359cd | 522 | |
5e2d7afc | 523 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
524 | work = crtc->flip_work; |
525 | if (work == NULL) { | |
9db4a9c7 | 526 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
527 | pipe, plane); |
528 | } else { | |
5a21b665 DV |
529 | u32 pending; |
530 | u32 addr; | |
531 | ||
532 | pending = atomic_read(&work->pending); | |
533 | if (pending) { | |
534 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
535 | pipe, plane); | |
536 | } else { | |
537 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
538 | pipe, plane); | |
539 | } | |
540 | if (work->flip_queued_req) { | |
24327f83 | 541 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 542 | |
312c3c47 | 543 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 544 | engine->name, |
24327f83 | 545 | work->flip_queued_req->global_seqno, |
312c3c47 | 546 | intel_engine_last_submit(engine), |
1b7744e7 | 547 | intel_engine_get_seqno(engine), |
f69a02c9 | 548 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
549 | } else |
550 | seq_printf(m, "Flip not associated with any ring\n"); | |
551 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
552 | work->flip_queued_vblank, | |
553 | work->flip_ready_vblank, | |
554 | intel_crtc_get_vblank_counter(crtc)); | |
555 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
556 | ||
36cdd013 | 557 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
558 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
559 | else | |
560 | addr = I915_READ(DSPADDR(crtc->plane)); | |
561 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
562 | ||
563 | if (work->pending_flip_obj) { | |
564 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
565 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
566 | } |
567 | } | |
5e2d7afc | 568 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
569 | } |
570 | ||
8a270ebf DV |
571 | mutex_unlock(&dev->struct_mutex); |
572 | ||
4e5359cd SF |
573 | return 0; |
574 | } | |
575 | ||
493018dc BV |
576 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
577 | { | |
36cdd013 DW |
578 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
579 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 580 | struct drm_i915_gem_object *obj; |
e2f80391 | 581 | struct intel_engine_cs *engine; |
3b3f1650 | 582 | enum intel_engine_id id; |
8d9d5744 | 583 | int total = 0; |
b4ac5afc | 584 | int ret, j; |
493018dc BV |
585 | |
586 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
587 | if (ret) | |
588 | return ret; | |
589 | ||
3b3f1650 | 590 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 591 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
592 | int count; |
593 | ||
594 | count = 0; | |
595 | list_for_each_entry(obj, | |
e2f80391 | 596 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
597 | batch_pool_link) |
598 | count++; | |
599 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 600 | engine->name, j, count); |
8d9d5744 CW |
601 | |
602 | list_for_each_entry(obj, | |
e2f80391 | 603 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
604 | batch_pool_link) { |
605 | seq_puts(m, " "); | |
606 | describe_obj(m, obj); | |
607 | seq_putc(m, '\n'); | |
608 | } | |
609 | ||
610 | total += count; | |
06fbca71 | 611 | } |
493018dc BV |
612 | } |
613 | ||
8d9d5744 | 614 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
615 | |
616 | mutex_unlock(&dev->struct_mutex); | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
1b36595f CW |
621 | static void print_request(struct seq_file *m, |
622 | struct drm_i915_gem_request *rq, | |
623 | const char *prefix) | |
624 | { | |
20311bd3 | 625 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 626 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 627 | rq->priotree.priority, |
1b36595f | 628 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 629 | rq->timeline->common->name); |
1b36595f CW |
630 | } |
631 | ||
2017263e BG |
632 | static int i915_gem_request_info(struct seq_file *m, void *data) |
633 | { | |
36cdd013 DW |
634 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
635 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 636 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
637 | struct intel_engine_cs *engine; |
638 | enum intel_engine_id id; | |
b4ac5afc | 639 | int ret, any; |
de227ef0 CW |
640 | |
641 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
642 | if (ret) | |
643 | return ret; | |
2017263e | 644 | |
2d1070b2 | 645 | any = 0; |
3b3f1650 | 646 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
647 | int count; |
648 | ||
649 | count = 0; | |
73cb9701 | 650 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
651 | count++; |
652 | if (count == 0) | |
a2c7f6fd CW |
653 | continue; |
654 | ||
e2f80391 | 655 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 656 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 657 | print_request(m, req, " "); |
2d1070b2 CW |
658 | |
659 | any++; | |
2017263e | 660 | } |
de227ef0 CW |
661 | mutex_unlock(&dev->struct_mutex); |
662 | ||
2d1070b2 | 663 | if (any == 0) |
267f0c90 | 664 | seq_puts(m, "No requests\n"); |
c2c347a9 | 665 | |
2017263e BG |
666 | return 0; |
667 | } | |
668 | ||
b2223497 | 669 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 670 | struct intel_engine_cs *engine) |
b2223497 | 671 | { |
688e6c72 CW |
672 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
673 | struct rb_node *rb; | |
674 | ||
12471ba8 | 675 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 676 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 677 | |
f6168e33 | 678 | spin_lock_irq(&b->lock); |
688e6c72 | 679 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 680 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
681 | |
682 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
683 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
684 | } | |
f6168e33 | 685 | spin_unlock_irq(&b->lock); |
b2223497 CW |
686 | } |
687 | ||
2017263e BG |
688 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
689 | { | |
36cdd013 | 690 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 691 | struct intel_engine_cs *engine; |
3b3f1650 | 692 | enum intel_engine_id id; |
2017263e | 693 | |
3b3f1650 | 694 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 695 | i915_ring_seqno_info(m, engine); |
de227ef0 | 696 | |
2017263e BG |
697 | return 0; |
698 | } | |
699 | ||
700 | ||
701 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
702 | { | |
36cdd013 | 703 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 704 | struct intel_engine_cs *engine; |
3b3f1650 | 705 | enum intel_engine_id id; |
4bb05040 | 706 | int i, pipe; |
de227ef0 | 707 | |
c8c8fb33 | 708 | intel_runtime_pm_get(dev_priv); |
2017263e | 709 | |
36cdd013 | 710 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
711 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
712 | I915_READ(GEN8_MASTER_IRQ)); | |
713 | ||
714 | seq_printf(m, "Display IER:\t%08x\n", | |
715 | I915_READ(VLV_IER)); | |
716 | seq_printf(m, "Display IIR:\t%08x\n", | |
717 | I915_READ(VLV_IIR)); | |
718 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
719 | I915_READ(VLV_IIR_RW)); | |
720 | seq_printf(m, "Display IMR:\t%08x\n", | |
721 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
722 | for_each_pipe(dev_priv, pipe) { |
723 | enum intel_display_power_domain power_domain; | |
724 | ||
725 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
726 | if (!intel_display_power_get_if_enabled(dev_priv, | |
727 | power_domain)) { | |
728 | seq_printf(m, "Pipe %c power disabled\n", | |
729 | pipe_name(pipe)); | |
730 | continue; | |
731 | } | |
732 | ||
74e1ca8c VS |
733 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
734 | pipe_name(pipe), | |
735 | I915_READ(PIPESTAT(pipe))); | |
736 | ||
9c870d03 CW |
737 | intel_display_power_put(dev_priv, power_domain); |
738 | } | |
739 | ||
740 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
741 | seq_printf(m, "Port hotplug:\t%08x\n", |
742 | I915_READ(PORT_HOTPLUG_EN)); | |
743 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
744 | I915_READ(VLV_DPFLIPSTAT)); | |
745 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
746 | I915_READ(DPINVGTT)); | |
9c870d03 | 747 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
748 | |
749 | for (i = 0; i < 4; i++) { | |
750 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
751 | i, I915_READ(GEN8_GT_IMR(i))); | |
752 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
753 | i, I915_READ(GEN8_GT_IIR(i))); | |
754 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
755 | i, I915_READ(GEN8_GT_IER(i))); | |
756 | } | |
757 | ||
758 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
759 | I915_READ(GEN8_PCU_IMR)); | |
760 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
761 | I915_READ(GEN8_PCU_IIR)); | |
762 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
763 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 764 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
765 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
766 | I915_READ(GEN8_MASTER_IRQ)); | |
767 | ||
768 | for (i = 0; i < 4; i++) { | |
769 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
770 | i, I915_READ(GEN8_GT_IMR(i))); | |
771 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
772 | i, I915_READ(GEN8_GT_IIR(i))); | |
773 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
774 | i, I915_READ(GEN8_GT_IER(i))); | |
775 | } | |
776 | ||
055e393f | 777 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
778 | enum intel_display_power_domain power_domain; |
779 | ||
780 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
781 | if (!intel_display_power_get_if_enabled(dev_priv, | |
782 | power_domain)) { | |
22c59960 PZ |
783 | seq_printf(m, "Pipe %c power disabled\n", |
784 | pipe_name(pipe)); | |
785 | continue; | |
786 | } | |
a123f157 | 787 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
788 | pipe_name(pipe), |
789 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 790 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
791 | pipe_name(pipe), |
792 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 793 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
794 | pipe_name(pipe), |
795 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
796 | |
797 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
798 | } |
799 | ||
800 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
801 | I915_READ(GEN8_DE_PORT_IMR)); | |
802 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
803 | I915_READ(GEN8_DE_PORT_IIR)); | |
804 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
805 | I915_READ(GEN8_DE_PORT_IER)); | |
806 | ||
807 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
808 | I915_READ(GEN8_DE_MISC_IMR)); | |
809 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
810 | I915_READ(GEN8_DE_MISC_IIR)); | |
811 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
812 | I915_READ(GEN8_DE_MISC_IER)); | |
813 | ||
814 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
815 | I915_READ(GEN8_PCU_IMR)); | |
816 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
817 | I915_READ(GEN8_PCU_IIR)); | |
818 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
819 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 820 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
821 | seq_printf(m, "Display IER:\t%08x\n", |
822 | I915_READ(VLV_IER)); | |
823 | seq_printf(m, "Display IIR:\t%08x\n", | |
824 | I915_READ(VLV_IIR)); | |
825 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
826 | I915_READ(VLV_IIR_RW)); | |
827 | seq_printf(m, "Display IMR:\t%08x\n", | |
828 | I915_READ(VLV_IMR)); | |
055e393f | 829 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
830 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
831 | pipe_name(pipe), | |
832 | I915_READ(PIPESTAT(pipe))); | |
833 | ||
834 | seq_printf(m, "Master IER:\t%08x\n", | |
835 | I915_READ(VLV_MASTER_IER)); | |
836 | ||
837 | seq_printf(m, "Render IER:\t%08x\n", | |
838 | I915_READ(GTIER)); | |
839 | seq_printf(m, "Render IIR:\t%08x\n", | |
840 | I915_READ(GTIIR)); | |
841 | seq_printf(m, "Render IMR:\t%08x\n", | |
842 | I915_READ(GTIMR)); | |
843 | ||
844 | seq_printf(m, "PM IER:\t\t%08x\n", | |
845 | I915_READ(GEN6_PMIER)); | |
846 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
847 | I915_READ(GEN6_PMIIR)); | |
848 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
849 | I915_READ(GEN6_PMIMR)); | |
850 | ||
851 | seq_printf(m, "Port hotplug:\t%08x\n", | |
852 | I915_READ(PORT_HOTPLUG_EN)); | |
853 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
854 | I915_READ(VLV_DPFLIPSTAT)); | |
855 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
856 | I915_READ(DPINVGTT)); | |
857 | ||
36cdd013 | 858 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
859 | seq_printf(m, "Interrupt enable: %08x\n", |
860 | I915_READ(IER)); | |
861 | seq_printf(m, "Interrupt identity: %08x\n", | |
862 | I915_READ(IIR)); | |
863 | seq_printf(m, "Interrupt mask: %08x\n", | |
864 | I915_READ(IMR)); | |
055e393f | 865 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
866 | seq_printf(m, "Pipe %c stat: %08x\n", |
867 | pipe_name(pipe), | |
868 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
869 | } else { |
870 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
871 | I915_READ(DEIER)); | |
872 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
873 | I915_READ(DEIIR)); | |
874 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
875 | I915_READ(DEIMR)); | |
876 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
877 | I915_READ(SDEIER)); | |
878 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
879 | I915_READ(SDEIIR)); | |
880 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
881 | I915_READ(SDEIMR)); | |
882 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
883 | I915_READ(GTIER)); | |
884 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
885 | I915_READ(GTIIR)); | |
886 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
887 | I915_READ(GTIMR)); | |
888 | } | |
3b3f1650 | 889 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 890 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
891 | seq_printf(m, |
892 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 893 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 894 | } |
e2f80391 | 895 | i915_ring_seqno_info(m, engine); |
9862e600 | 896 | } |
c8c8fb33 | 897 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 898 | |
2017263e BG |
899 | return 0; |
900 | } | |
901 | ||
a6172a80 CW |
902 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
903 | { | |
36cdd013 DW |
904 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
905 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
906 | int i, ret; |
907 | ||
908 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
909 | if (ret) | |
910 | return ret; | |
a6172a80 | 911 | |
a6172a80 CW |
912 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
913 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 914 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 915 | |
6c085a72 CW |
916 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
917 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 918 | if (!vma) |
267f0c90 | 919 | seq_puts(m, "unused"); |
c2c347a9 | 920 | else |
49ef5294 | 921 | describe_obj(m, vma->obj); |
267f0c90 | 922 | seq_putc(m, '\n'); |
a6172a80 CW |
923 | } |
924 | ||
05394f39 | 925 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
926 | return 0; |
927 | } | |
928 | ||
98a2f411 CW |
929 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
930 | ||
d5442303 DV |
931 | static ssize_t |
932 | i915_error_state_write(struct file *filp, | |
933 | const char __user *ubuf, | |
934 | size_t cnt, | |
935 | loff_t *ppos) | |
936 | { | |
edc3d884 | 937 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 DV |
938 | |
939 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
12ff05e7 | 940 | i915_destroy_error_state(error_priv->i915); |
d5442303 DV |
941 | |
942 | return cnt; | |
943 | } | |
944 | ||
945 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
946 | { | |
36cdd013 | 947 | struct drm_i915_private *dev_priv = inode->i_private; |
d5442303 | 948 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
949 | |
950 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
951 | if (!error_priv) | |
952 | return -ENOMEM; | |
953 | ||
12ff05e7 | 954 | error_priv->i915 = dev_priv; |
d5442303 | 955 | |
36cdd013 | 956 | i915_error_state_get(&dev_priv->drm, error_priv); |
d5442303 | 957 | |
edc3d884 MK |
958 | file->private_data = error_priv; |
959 | ||
960 | return 0; | |
d5442303 DV |
961 | } |
962 | ||
963 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
964 | { | |
edc3d884 | 965 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 966 | |
95d5bfb3 | 967 | i915_error_state_put(error_priv); |
d5442303 DV |
968 | kfree(error_priv); |
969 | ||
edc3d884 MK |
970 | return 0; |
971 | } | |
972 | ||
4dc955f7 MK |
973 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
974 | size_t count, loff_t *pos) | |
975 | { | |
976 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
977 | struct drm_i915_error_state_buf error_str; | |
978 | loff_t tmp_pos = 0; | |
979 | ssize_t ret_count = 0; | |
980 | int ret; | |
981 | ||
12ff05e7 TU |
982 | ret = i915_error_state_buf_init(&error_str, error_priv->i915, |
983 | count, *pos); | |
4dc955f7 MK |
984 | if (ret) |
985 | return ret; | |
edc3d884 | 986 | |
fc16b48b | 987 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
988 | if (ret) |
989 | goto out; | |
990 | ||
edc3d884 MK |
991 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
992 | error_str.buf, | |
993 | error_str.bytes); | |
994 | ||
995 | if (ret_count < 0) | |
996 | ret = ret_count; | |
997 | else | |
998 | *pos = error_str.start + ret_count; | |
999 | out: | |
4dc955f7 | 1000 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1001 | return ret ?: ret_count; |
d5442303 DV |
1002 | } |
1003 | ||
1004 | static const struct file_operations i915_error_state_fops = { | |
1005 | .owner = THIS_MODULE, | |
1006 | .open = i915_error_state_open, | |
edc3d884 | 1007 | .read = i915_error_state_read, |
d5442303 DV |
1008 | .write = i915_error_state_write, |
1009 | .llseek = default_llseek, | |
1010 | .release = i915_error_state_release, | |
1011 | }; | |
1012 | ||
98a2f411 CW |
1013 | #endif |
1014 | ||
647416f9 KC |
1015 | static int |
1016 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1017 | { |
36cdd013 | 1018 | struct drm_i915_private *dev_priv = data; |
40633219 | 1019 | |
4c266edb | 1020 | *val = 1 + atomic_read(&dev_priv->gt.global_timeline.seqno); |
647416f9 | 1021 | return 0; |
40633219 MK |
1022 | } |
1023 | ||
647416f9 KC |
1024 | static int |
1025 | i915_next_seqno_set(void *data, u64 val) | |
1026 | { | |
36cdd013 DW |
1027 | struct drm_i915_private *dev_priv = data; |
1028 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1029 | int ret; |
1030 | ||
40633219 MK |
1031 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1032 | if (ret) | |
1033 | return ret; | |
1034 | ||
73cb9701 | 1035 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1036 | mutex_unlock(&dev->struct_mutex); |
1037 | ||
647416f9 | 1038 | return ret; |
40633219 MK |
1039 | } |
1040 | ||
647416f9 KC |
1041 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1042 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1043 | "0x%llx\n"); |
40633219 | 1044 | |
adb4bd12 | 1045 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1046 | { |
36cdd013 DW |
1047 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1048 | struct drm_device *dev = &dev_priv->drm; | |
c8c8fb33 PZ |
1049 | int ret = 0; |
1050 | ||
1051 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1052 | |
36cdd013 | 1053 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1054 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1055 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1056 | ||
1057 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1058 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1059 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1060 | MEMSTAT_VID_SHIFT); | |
1061 | seq_printf(m, "Current P-state: %d\n", | |
1062 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1063 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1064 | u32 freq_sts; |
1065 | ||
1066 | mutex_lock(&dev_priv->rps.hw_lock); | |
1067 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1068 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1069 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1070 | ||
1071 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1072 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1073 | ||
1074 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1075 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1076 | ||
1077 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1078 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1079 | ||
1080 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1081 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1082 | ||
1083 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1084 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1085 | ||
1086 | seq_printf(m, | |
1087 | "efficient (RPe) frequency: %d MHz\n", | |
1088 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1089 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1090 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1091 | u32 rp_state_limits; |
1092 | u32 gt_perf_status; | |
1093 | u32 rp_state_cap; | |
0d8f9491 | 1094 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1095 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1096 | u32 rpupei, rpcurup, rpprevup; |
1097 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1098 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1099 | int max_freq; |
1100 | ||
35040562 | 1101 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1102 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1103 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1104 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1105 | } else { | |
1106 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1107 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1108 | } | |
1109 | ||
3b8d8d91 | 1110 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1111 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1112 | if (ret) | |
c8c8fb33 | 1113 | goto out; |
d1ebd816 | 1114 | |
59bad947 | 1115 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1116 | |
8e8c06cd | 1117 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1118 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1119 | reqf >>= 23; |
1120 | else { | |
1121 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1122 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1123 | reqf >>= 24; |
1124 | else | |
1125 | reqf >>= 25; | |
1126 | } | |
7c59a9c1 | 1127 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1128 | |
0d8f9491 CW |
1129 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1130 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1131 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1132 | ||
ccab5c82 | 1133 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1134 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1135 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1136 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1137 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1138 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1139 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1140 | if (IS_GEN9(dev_priv)) |
60260a5b | 1141 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1142 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1143 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1144 | else | |
1145 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1146 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1147 | |
59bad947 | 1148 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1149 | mutex_unlock(&dev->struct_mutex); |
1150 | ||
36cdd013 | 1151 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1152 | pm_ier = I915_READ(GEN6_PMIER); |
1153 | pm_imr = I915_READ(GEN6_PMIMR); | |
1154 | pm_isr = I915_READ(GEN6_PMISR); | |
1155 | pm_iir = I915_READ(GEN6_PMIIR); | |
1156 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1157 | } else { | |
1158 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1159 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1160 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1161 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1162 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1163 | } | |
0d8f9491 | 1164 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1165 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1166 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1167 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1168 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1169 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1170 | seq_printf(m, "Render p-state VID: %d\n", |
1171 | gt_perf_status & 0xff); | |
1172 | seq_printf(m, "Render p-state limit: %d\n", | |
1173 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1174 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1175 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1176 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1177 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1178 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1179 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1180 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1181 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1182 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1183 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1184 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1185 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1186 | seq_printf(m, "Up threshold: %d%%\n", |
1187 | dev_priv->rps.up_threshold); | |
1188 | ||
d6cda9c7 AG |
1189 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1190 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1191 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1192 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1193 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1194 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1195 | seq_printf(m, "Down threshold: %d%%\n", |
1196 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1197 | |
cc3f90f0 | 1198 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1199 | rp_state_cap >> 16) & 0xff; |
36cdd013 | 1200 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1201 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1202 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1203 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1204 | |
1205 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
36cdd013 | 1206 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1207 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1208 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1209 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1210 | |
cc3f90f0 | 1211 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1212 | rp_state_cap >> 0) & 0xff; |
36cdd013 | 1213 | max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1214 | GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1215 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1216 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1217 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1218 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1219 | |
d86ed34a CW |
1220 | seq_printf(m, "Current freq: %d MHz\n", |
1221 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1222 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1223 | seq_printf(m, "Idle freq: %d MHz\n", |
1224 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1225 | seq_printf(m, "Min freq: %d MHz\n", |
1226 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1227 | seq_printf(m, "Boost freq: %d MHz\n", |
1228 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1229 | seq_printf(m, "Max freq: %d MHz\n", |
1230 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1231 | seq_printf(m, | |
1232 | "efficient (RPe) frequency: %d MHz\n", | |
1233 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1234 | } else { |
267f0c90 | 1235 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1236 | } |
f97108d1 | 1237 | |
1170f28c MK |
1238 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1239 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1240 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1241 | ||
c8c8fb33 PZ |
1242 | out: |
1243 | intel_runtime_pm_put(dev_priv); | |
1244 | return ret; | |
f97108d1 JB |
1245 | } |
1246 | ||
d636951e BW |
1247 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1248 | struct seq_file *m, | |
1249 | struct intel_instdone *instdone) | |
1250 | { | |
f9e61372 BW |
1251 | int slice; |
1252 | int subslice; | |
1253 | ||
d636951e BW |
1254 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1255 | instdone->instdone); | |
1256 | ||
1257 | if (INTEL_GEN(dev_priv) <= 3) | |
1258 | return; | |
1259 | ||
1260 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1261 | instdone->slice_common); | |
1262 | ||
1263 | if (INTEL_GEN(dev_priv) <= 6) | |
1264 | return; | |
1265 | ||
f9e61372 BW |
1266 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1267 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1268 | slice, subslice, instdone->sampler[slice][subslice]); | |
1269 | ||
1270 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1271 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1272 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1273 | } |
1274 | ||
f654449a CW |
1275 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1276 | { | |
36cdd013 | 1277 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1278 | struct intel_engine_cs *engine; |
666796da TU |
1279 | u64 acthd[I915_NUM_ENGINES]; |
1280 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1281 | struct intel_instdone instdone; |
c3232b18 | 1282 | enum intel_engine_id id; |
f654449a | 1283 | |
8af29b0c CW |
1284 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1285 | seq_printf(m, "Wedged\n"); | |
1286 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1287 | seq_printf(m, "Reset in progress\n"); | |
1288 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1289 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1290 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1291 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1292 | ||
f654449a CW |
1293 | if (!i915.enable_hangcheck) { |
1294 | seq_printf(m, "Hangcheck disabled\n"); | |
1295 | return 0; | |
1296 | } | |
1297 | ||
ebbc7546 MK |
1298 | intel_runtime_pm_get(dev_priv); |
1299 | ||
3b3f1650 | 1300 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1301 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1302 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1303 | } |
1304 | ||
3b3f1650 | 1305 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1306 | |
ebbc7546 MK |
1307 | intel_runtime_pm_put(dev_priv); |
1308 | ||
f654449a CW |
1309 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1310 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1311 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1312 | jiffies)); | |
1313 | } else | |
1314 | seq_printf(m, "Hangcheck inactive\n"); | |
1315 | ||
3b3f1650 | 1316 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1317 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1318 | struct rb_node *rb; | |
1319 | ||
e2f80391 | 1320 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d | 1321 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
cb399eab CW |
1322 | engine->hangcheck.seqno, seqno[id], |
1323 | intel_engine_last_submit(engine)); | |
3fe3b030 | 1324 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1325 | yesno(intel_engine_has_waiter(engine)), |
1326 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1327 | &dev_priv->gpu_error.missed_irq_rings)), |
1328 | yesno(engine->hangcheck.stalled)); | |
1329 | ||
f6168e33 | 1330 | spin_lock_irq(&b->lock); |
33f53719 | 1331 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1332 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1333 | |
1334 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1335 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1336 | } | |
f6168e33 | 1337 | spin_unlock_irq(&b->lock); |
33f53719 | 1338 | |
f654449a | 1339 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1340 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1341 | (long long)acthd[id]); |
3fe3b030 MK |
1342 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1343 | hangcheck_action_to_str(engine->hangcheck.action), | |
1344 | engine->hangcheck.action, | |
1345 | jiffies_to_msecs(jiffies - | |
1346 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1347 | |
e2f80391 | 1348 | if (engine->id == RCS) { |
d636951e | 1349 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1350 | |
d636951e | 1351 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1352 | |
d636951e | 1353 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1354 | |
d636951e BW |
1355 | i915_instdone_info(dev_priv, m, |
1356 | &engine->hangcheck.instdone); | |
61642ff0 | 1357 | } |
f654449a CW |
1358 | } |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
4d85529d | 1363 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1364 | { |
36cdd013 | 1365 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1366 | u32 rgvmodectl, rstdbyctl; |
1367 | u16 crstandvid; | |
616fdb5a | 1368 | |
c8c8fb33 | 1369 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1370 | |
1371 | rgvmodectl = I915_READ(MEMMODECTL); | |
1372 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1373 | crstandvid = I915_READ16(CRSTANDVID); | |
1374 | ||
c8c8fb33 | 1375 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1376 | |
742f491d | 1377 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1378 | seq_printf(m, "Boost freq: %d\n", |
1379 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1380 | MEMMODE_BOOST_FREQ_SHIFT); | |
1381 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1382 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1383 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1384 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1385 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1386 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1387 | seq_printf(m, "Starting frequency: P%d\n", |
1388 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1389 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1390 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1391 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1392 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1393 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1394 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1395 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1396 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1397 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1398 | case RSX_STATUS_ON: | |
267f0c90 | 1399 | seq_puts(m, "on\n"); |
88271da3 JB |
1400 | break; |
1401 | case RSX_STATUS_RC1: | |
267f0c90 | 1402 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1403 | break; |
1404 | case RSX_STATUS_RC1E: | |
267f0c90 | 1405 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1406 | break; |
1407 | case RSX_STATUS_RS1: | |
267f0c90 | 1408 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1409 | break; |
1410 | case RSX_STATUS_RS2: | |
267f0c90 | 1411 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1412 | break; |
1413 | case RSX_STATUS_RS3: | |
267f0c90 | 1414 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1415 | break; |
1416 | default: | |
267f0c90 | 1417 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1418 | break; |
1419 | } | |
f97108d1 JB |
1420 | |
1421 | return 0; | |
1422 | } | |
1423 | ||
f65367b5 | 1424 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1425 | { |
36cdd013 | 1426 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1427 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1428 | |
1429 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1430 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1431 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1432 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1433 | fw_domain->wake_count); |
1434 | } | |
1435 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1436 | |
b2cff0db CW |
1437 | return 0; |
1438 | } | |
1439 | ||
1440 | static int vlv_drpc_info(struct seq_file *m) | |
1441 | { | |
36cdd013 | 1442 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1443 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1444 | |
d46c0517 ID |
1445 | intel_runtime_pm_get(dev_priv); |
1446 | ||
6b312cd3 | 1447 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1448 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1449 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1450 | ||
d46c0517 ID |
1451 | intel_runtime_pm_put(dev_priv); |
1452 | ||
669ab5aa D |
1453 | seq_printf(m, "Video Turbo Mode: %s\n", |
1454 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1455 | seq_printf(m, "Turbo enabled: %s\n", | |
1456 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1457 | seq_printf(m, "HW control enabled: %s\n", | |
1458 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1459 | seq_printf(m, "SW control enabled: %s\n", | |
1460 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1461 | GEN6_RP_MEDIA_SW_MODE)); | |
1462 | seq_printf(m, "RC6 Enabled: %s\n", | |
1463 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1464 | GEN6_RC_CTL_EI_MODE(1)))); | |
1465 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1466 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1467 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1468 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1469 | |
9cc19be5 ID |
1470 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1471 | I915_READ(VLV_GT_RENDER_RC6)); | |
1472 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1473 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1474 | ||
f65367b5 | 1475 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1476 | } |
1477 | ||
4d85529d BW |
1478 | static int gen6_drpc_info(struct seq_file *m) |
1479 | { | |
36cdd013 DW |
1480 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1481 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1482 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1483 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1484 | unsigned forcewake_count; |
aee56cff | 1485 | int count = 0, ret; |
4d85529d BW |
1486 | |
1487 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1488 | if (ret) | |
1489 | return ret; | |
c8c8fb33 | 1490 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1491 | |
907b28c5 | 1492 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1493 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1494 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1495 | |
1496 | if (forcewake_count) { | |
267f0c90 DL |
1497 | seq_puts(m, "RC information inaccurate because somebody " |
1498 | "holds a forcewake reference \n"); | |
4d85529d BW |
1499 | } else { |
1500 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1501 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1502 | udelay(10); | |
1503 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1504 | } | |
1505 | ||
75aa3f63 | 1506 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1507 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1508 | |
1509 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1510 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1511 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1512 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1513 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1514 | } | |
4d85529d | 1515 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1516 | mutex_lock(&dev_priv->rps.hw_lock); |
1517 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1518 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1519 | |
c8c8fb33 PZ |
1520 | intel_runtime_pm_put(dev_priv); |
1521 | ||
4d85529d BW |
1522 | seq_printf(m, "Video Turbo Mode: %s\n", |
1523 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1524 | seq_printf(m, "HW control enabled: %s\n", | |
1525 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1526 | seq_printf(m, "SW control enabled: %s\n", | |
1527 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1528 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1529 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1530 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1531 | seq_printf(m, "RC6 Enabled: %s\n", | |
1532 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1533 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1534 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1535 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1536 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1537 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1538 | } | |
4d85529d BW |
1539 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1540 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1541 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1542 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1543 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1544 | switch (gt_core_status & GEN6_RCn_MASK) { |
1545 | case GEN6_RC0: | |
1546 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1547 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1548 | else |
267f0c90 | 1549 | seq_puts(m, "on\n"); |
4d85529d BW |
1550 | break; |
1551 | case GEN6_RC3: | |
267f0c90 | 1552 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1553 | break; |
1554 | case GEN6_RC6: | |
267f0c90 | 1555 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1556 | break; |
1557 | case GEN6_RC7: | |
267f0c90 | 1558 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1559 | break; |
1560 | default: | |
267f0c90 | 1561 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1562 | break; |
1563 | } | |
1564 | ||
1565 | seq_printf(m, "Core Power Down: %s\n", | |
1566 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1567 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1568 | seq_printf(m, "Render Power Well: %s\n", |
1569 | (gen9_powergate_status & | |
1570 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1571 | seq_printf(m, "Media Power Well: %s\n", | |
1572 | (gen9_powergate_status & | |
1573 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1574 | } | |
cce66a28 BW |
1575 | |
1576 | /* Not exactly sure what this is */ | |
1577 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1578 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1579 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1580 | I915_READ(GEN6_GT_GFX_RC6)); | |
1581 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1582 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1583 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1584 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1585 | ||
ecd8faea BW |
1586 | seq_printf(m, "RC6 voltage: %dmV\n", |
1587 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1588 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1589 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1590 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1591 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1592 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1593 | } |
1594 | ||
1595 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1596 | { | |
36cdd013 | 1597 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1598 | |
36cdd013 | 1599 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1600 | return vlv_drpc_info(m); |
36cdd013 | 1601 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1602 | return gen6_drpc_info(m); |
1603 | else | |
1604 | return ironlake_drpc_info(m); | |
1605 | } | |
1606 | ||
9a851789 DV |
1607 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1608 | { | |
36cdd013 | 1609 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1610 | |
1611 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1612 | dev_priv->fb_tracking.busy_bits); | |
1613 | ||
1614 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1615 | dev_priv->fb_tracking.flip_bits); | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
b5e50c3f JB |
1620 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1621 | { | |
36cdd013 | 1622 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1623 | |
36cdd013 | 1624 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1625 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1626 | return 0; |
1627 | } | |
1628 | ||
36623ef8 | 1629 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1630 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1631 | |
0e631adc | 1632 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1633 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1634 | else |
1635 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1636 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1637 | |
0fc6a9dc PZ |
1638 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1639 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1640 | BDW_FBC_COMPRESSION_MASK : | |
1641 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1642 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1643 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1644 | } | |
31b9df10 | 1645 | |
25ad93fd | 1646 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1647 | intel_runtime_pm_put(dev_priv); |
1648 | ||
b5e50c3f JB |
1649 | return 0; |
1650 | } | |
1651 | ||
da46f936 RV |
1652 | static int i915_fbc_fc_get(void *data, u64 *val) |
1653 | { | |
36cdd013 | 1654 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1655 | |
36cdd013 | 1656 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1657 | return -ENODEV; |
1658 | ||
da46f936 | 1659 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1660 | |
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | static int i915_fbc_fc_set(void *data, u64 val) | |
1665 | { | |
36cdd013 | 1666 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1667 | u32 reg; |
1668 | ||
36cdd013 | 1669 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1670 | return -ENODEV; |
1671 | ||
25ad93fd | 1672 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1673 | |
1674 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1675 | dev_priv->fbc.false_color = val; | |
1676 | ||
1677 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1678 | (reg | FBC_CTL_FALSE_COLOR) : | |
1679 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1680 | ||
25ad93fd | 1681 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1682 | return 0; |
1683 | } | |
1684 | ||
1685 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1686 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1687 | "%llu\n"); | |
1688 | ||
92d44621 PZ |
1689 | static int i915_ips_status(struct seq_file *m, void *unused) |
1690 | { | |
36cdd013 | 1691 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1692 | |
36cdd013 | 1693 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1694 | seq_puts(m, "not supported\n"); |
1695 | return 0; | |
1696 | } | |
1697 | ||
36623ef8 PZ |
1698 | intel_runtime_pm_get(dev_priv); |
1699 | ||
0eaa53f0 RV |
1700 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1701 | yesno(i915.enable_ips)); | |
1702 | ||
36cdd013 | 1703 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1704 | seq_puts(m, "Currently: unknown\n"); |
1705 | } else { | |
1706 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1707 | seq_puts(m, "Currently: enabled\n"); | |
1708 | else | |
1709 | seq_puts(m, "Currently: disabled\n"); | |
1710 | } | |
92d44621 | 1711 | |
36623ef8 PZ |
1712 | intel_runtime_pm_put(dev_priv); |
1713 | ||
92d44621 PZ |
1714 | return 0; |
1715 | } | |
1716 | ||
4a9bef37 JB |
1717 | static int i915_sr_status(struct seq_file *m, void *unused) |
1718 | { | |
36cdd013 | 1719 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1720 | bool sr_enabled = false; |
1721 | ||
36623ef8 | 1722 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1723 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1724 | |
36cdd013 | 1725 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1726 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1727 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1728 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1729 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1730 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1731 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1732 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1733 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1734 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1735 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1736 | |
9c870d03 | 1737 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1738 | intel_runtime_pm_put(dev_priv); |
1739 | ||
08c4d7fc | 1740 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1741 | |
1742 | return 0; | |
1743 | } | |
1744 | ||
7648fa99 JB |
1745 | static int i915_emon_status(struct seq_file *m, void *unused) |
1746 | { | |
36cdd013 DW |
1747 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1748 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1749 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1750 | int ret; |
1751 | ||
36cdd013 | 1752 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1753 | return -ENODEV; |
1754 | ||
de227ef0 CW |
1755 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1756 | if (ret) | |
1757 | return ret; | |
7648fa99 JB |
1758 | |
1759 | temp = i915_mch_val(dev_priv); | |
1760 | chipset = i915_chipset_val(dev_priv); | |
1761 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1762 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1763 | |
1764 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1765 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1766 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1767 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
23b2f8bb JB |
1772 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1773 | { | |
36cdd013 | 1774 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1775 | int ret = 0; |
23b2f8bb | 1776 | int gpu_freq, ia_freq; |
f936ec34 | 1777 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1778 | |
26310346 | 1779 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1780 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1781 | return 0; |
1782 | } | |
1783 | ||
5bfa0199 PZ |
1784 | intel_runtime_pm_get(dev_priv); |
1785 | ||
4fc688ce | 1786 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1787 | if (ret) |
5bfa0199 | 1788 | goto out; |
23b2f8bb | 1789 | |
36cdd013 | 1790 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f936ec34 AG |
1791 | /* Convert GT frequency to 50 HZ units */ |
1792 | min_gpu_freq = | |
1793 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1794 | max_gpu_freq = | |
1795 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1796 | } else { | |
1797 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1798 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1799 | } | |
1800 | ||
267f0c90 | 1801 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1802 | |
f936ec34 | 1803 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1804 | ia_freq = gpu_freq; |
1805 | sandybridge_pcode_read(dev_priv, | |
1806 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1807 | &ia_freq); | |
3ebecd07 | 1808 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1809 | intel_gpu_freq(dev_priv, (gpu_freq * |
36cdd013 | 1810 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? |
ef11bdb3 | 1811 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1812 | ((ia_freq >> 0) & 0xff) * 100, |
1813 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1814 | } |
1815 | ||
4fc688ce | 1816 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1817 | |
5bfa0199 PZ |
1818 | out: |
1819 | intel_runtime_pm_put(dev_priv); | |
1820 | return ret; | |
23b2f8bb JB |
1821 | } |
1822 | ||
44834a67 CW |
1823 | static int i915_opregion(struct seq_file *m, void *unused) |
1824 | { | |
36cdd013 DW |
1825 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1826 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1827 | struct intel_opregion *opregion = &dev_priv->opregion; |
1828 | int ret; | |
1829 | ||
1830 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1831 | if (ret) | |
0d38f009 | 1832 | goto out; |
44834a67 | 1833 | |
2455a8e4 JN |
1834 | if (opregion->header) |
1835 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1836 | |
1837 | mutex_unlock(&dev->struct_mutex); | |
1838 | ||
0d38f009 | 1839 | out: |
44834a67 CW |
1840 | return 0; |
1841 | } | |
1842 | ||
ada8f955 JN |
1843 | static int i915_vbt(struct seq_file *m, void *unused) |
1844 | { | |
36cdd013 | 1845 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1846 | |
1847 | if (opregion->vbt) | |
1848 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1849 | ||
1850 | return 0; | |
1851 | } | |
1852 | ||
37811fcc CW |
1853 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1854 | { | |
36cdd013 DW |
1855 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1856 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1857 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1858 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1859 | int ret; |
1860 | ||
1861 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1862 | if (ret) | |
1863 | return ret; | |
37811fcc | 1864 | |
0695726e | 1865 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1866 | if (dev_priv->fbdev) { |
1867 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1868 | |
1869 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1870 | fbdev_fb->base.width, | |
1871 | fbdev_fb->base.height, | |
1872 | fbdev_fb->base.depth, | |
1873 | fbdev_fb->base.bits_per_pixel, | |
bae781b2 | 1874 | fbdev_fb->base.modifier, |
25bcce94 CW |
1875 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1876 | describe_obj(m, fbdev_fb->obj); | |
1877 | seq_putc(m, '\n'); | |
1878 | } | |
4520f53a | 1879 | #endif |
37811fcc | 1880 | |
4b096ac1 | 1881 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1882 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1883 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1884 | if (fb == fbdev_fb) | |
37811fcc CW |
1885 | continue; |
1886 | ||
c1ca506d | 1887 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1888 | fb->base.width, |
1889 | fb->base.height, | |
1890 | fb->base.depth, | |
623f9783 | 1891 | fb->base.bits_per_pixel, |
bae781b2 | 1892 | fb->base.modifier, |
747a598f | 1893 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1894 | describe_obj(m, fb->obj); |
267f0c90 | 1895 | seq_putc(m, '\n'); |
37811fcc | 1896 | } |
4b096ac1 | 1897 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1898 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1899 | |
1900 | return 0; | |
1901 | } | |
1902 | ||
7e37f889 | 1903 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1904 | { |
1905 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1906 | ring->space, ring->head, ring->tail, |
1907 | ring->last_retired_head); | |
c9fe99bd OM |
1908 | } |
1909 | ||
e76d3630 BW |
1910 | static int i915_context_status(struct seq_file *m, void *unused) |
1911 | { | |
36cdd013 DW |
1912 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1913 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1914 | struct intel_engine_cs *engine; |
e2efd130 | 1915 | struct i915_gem_context *ctx; |
3b3f1650 | 1916 | enum intel_engine_id id; |
c3232b18 | 1917 | int ret; |
e76d3630 | 1918 | |
f3d28878 | 1919 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1920 | if (ret) |
1921 | return ret; | |
1922 | ||
a33afea5 | 1923 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1924 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1925 | if (ctx->pid) { |
d28b99ab CW |
1926 | struct task_struct *task; |
1927 | ||
c84455b4 | 1928 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1929 | if (task) { |
1930 | seq_printf(m, "(%s [%d]) ", | |
1931 | task->comm, task->pid); | |
1932 | put_task_struct(task); | |
1933 | } | |
c84455b4 CW |
1934 | } else if (IS_ERR(ctx->file_priv)) { |
1935 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1936 | } else { |
1937 | seq_puts(m, "(kernel) "); | |
1938 | } | |
1939 | ||
bca44d80 CW |
1940 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1941 | seq_putc(m, '\n'); | |
c9fe99bd | 1942 | |
3b3f1650 | 1943 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1944 | struct intel_context *ce = &ctx->engine[engine->id]; |
1945 | ||
1946 | seq_printf(m, "%s: ", engine->name); | |
1947 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1948 | if (ce->state) | |
bf3783e5 | 1949 | describe_obj(m, ce->state->obj); |
dca33ecc | 1950 | if (ce->ring) |
7e37f889 | 1951 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1952 | seq_putc(m, '\n'); |
c9fe99bd | 1953 | } |
a33afea5 | 1954 | |
a33afea5 | 1955 | seq_putc(m, '\n'); |
a168c293 BW |
1956 | } |
1957 | ||
f3d28878 | 1958 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1959 | |
1960 | return 0; | |
1961 | } | |
1962 | ||
064ca1d2 | 1963 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1964 | struct i915_gem_context *ctx, |
0bc40be8 | 1965 | struct intel_engine_cs *engine) |
064ca1d2 | 1966 | { |
bf3783e5 | 1967 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1968 | struct page *page; |
064ca1d2 | 1969 | int j; |
064ca1d2 | 1970 | |
7069b144 CW |
1971 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1972 | ||
bf3783e5 CW |
1973 | if (!vma) { |
1974 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
1975 | return; |
1976 | } | |
1977 | ||
bf3783e5 CW |
1978 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
1979 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 1980 | i915_ggtt_offset(vma)); |
064ca1d2 | 1981 | |
a4f5ea64 | 1982 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 1983 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
1984 | return; |
1985 | } | |
1986 | ||
bf3783e5 CW |
1987 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
1988 | if (page) { | |
1989 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
1990 | |
1991 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
1992 | seq_printf(m, |
1993 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1994 | j * 4, | |
064ca1d2 TD |
1995 | reg_state[j], reg_state[j + 1], |
1996 | reg_state[j + 2], reg_state[j + 3]); | |
1997 | } | |
1998 | kunmap_atomic(reg_state); | |
1999 | } | |
2000 | ||
a4f5ea64 | 2001 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2002 | seq_putc(m, '\n'); |
2003 | } | |
2004 | ||
c0ab1ae9 BW |
2005 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2006 | { | |
36cdd013 DW |
2007 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2008 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2009 | struct intel_engine_cs *engine; |
e2efd130 | 2010 | struct i915_gem_context *ctx; |
3b3f1650 | 2011 | enum intel_engine_id id; |
b4ac5afc | 2012 | int ret; |
c0ab1ae9 BW |
2013 | |
2014 | if (!i915.enable_execlists) { | |
2015 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2016 | return 0; | |
2017 | } | |
2018 | ||
2019 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2020 | if (ret) | |
2021 | return ret; | |
2022 | ||
e28e404c | 2023 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2024 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2025 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2026 | |
2027 | mutex_unlock(&dev->struct_mutex); | |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
ea16a3cd DV |
2032 | static const char *swizzle_string(unsigned swizzle) |
2033 | { | |
aee56cff | 2034 | switch (swizzle) { |
ea16a3cd DV |
2035 | case I915_BIT_6_SWIZZLE_NONE: |
2036 | return "none"; | |
2037 | case I915_BIT_6_SWIZZLE_9: | |
2038 | return "bit9"; | |
2039 | case I915_BIT_6_SWIZZLE_9_10: | |
2040 | return "bit9/bit10"; | |
2041 | case I915_BIT_6_SWIZZLE_9_11: | |
2042 | return "bit9/bit11"; | |
2043 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2044 | return "bit9/bit10/bit11"; | |
2045 | case I915_BIT_6_SWIZZLE_9_17: | |
2046 | return "bit9/bit17"; | |
2047 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2048 | return "bit9/bit10/bit17"; | |
2049 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2050 | return "unknown"; |
ea16a3cd DV |
2051 | } |
2052 | ||
2053 | return "bug"; | |
2054 | } | |
2055 | ||
2056 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2057 | { | |
36cdd013 | 2058 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2059 | |
c8c8fb33 | 2060 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2061 | |
ea16a3cd DV |
2062 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2063 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2064 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2065 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2066 | ||
36cdd013 | 2067 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2068 | seq_printf(m, "DDC = 0x%08x\n", |
2069 | I915_READ(DCC)); | |
656bfa3a DV |
2070 | seq_printf(m, "DDC2 = 0x%08x\n", |
2071 | I915_READ(DCC2)); | |
ea16a3cd DV |
2072 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2073 | I915_READ16(C0DRB3)); | |
2074 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2075 | I915_READ16(C1DRB3)); | |
36cdd013 | 2076 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2077 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2078 | I915_READ(MAD_DIMM_C0)); | |
2079 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2080 | I915_READ(MAD_DIMM_C1)); | |
2081 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2082 | I915_READ(MAD_DIMM_C2)); | |
2083 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2084 | I915_READ(TILECTL)); | |
36cdd013 | 2085 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2086 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2087 | I915_READ(GAMTARBMODE)); | |
2088 | else | |
2089 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2090 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2091 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2092 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2093 | } |
656bfa3a DV |
2094 | |
2095 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2096 | seq_puts(m, "L-shaped memory detected\n"); | |
2097 | ||
c8c8fb33 | 2098 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2099 | |
2100 | return 0; | |
2101 | } | |
2102 | ||
1c60fef5 BW |
2103 | static int per_file_ctx(int id, void *ptr, void *data) |
2104 | { | |
e2efd130 | 2105 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2106 | struct seq_file *m = data; |
ae6c4806 DV |
2107 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2108 | ||
2109 | if (!ppgtt) { | |
2110 | seq_printf(m, " no ppgtt for context %d\n", | |
2111 | ctx->user_handle); | |
2112 | return 0; | |
2113 | } | |
1c60fef5 | 2114 | |
f83d6518 OM |
2115 | if (i915_gem_context_is_default(ctx)) |
2116 | seq_puts(m, " default context:\n"); | |
2117 | else | |
821d66dd | 2118 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2119 | ppgtt->debug_dump(ppgtt, m); |
2120 | ||
2121 | return 0; | |
2122 | } | |
2123 | ||
36cdd013 DW |
2124 | static void gen8_ppgtt_info(struct seq_file *m, |
2125 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2126 | { |
77df6772 | 2127 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2128 | struct intel_engine_cs *engine; |
2129 | enum intel_engine_id id; | |
b4ac5afc | 2130 | int i; |
3cf17fc5 | 2131 | |
77df6772 BW |
2132 | if (!ppgtt) |
2133 | return; | |
2134 | ||
3b3f1650 | 2135 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2136 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2137 | for (i = 0; i < 4; i++) { |
e2f80391 | 2138 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2139 | pdp <<= 32; |
e2f80391 | 2140 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2141 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2142 | } |
2143 | } | |
2144 | } | |
2145 | ||
36cdd013 DW |
2146 | static void gen6_ppgtt_info(struct seq_file *m, |
2147 | struct drm_i915_private *dev_priv) | |
77df6772 | 2148 | { |
e2f80391 | 2149 | struct intel_engine_cs *engine; |
3b3f1650 | 2150 | enum intel_engine_id id; |
3cf17fc5 | 2151 | |
7e22dbbb | 2152 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2153 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2154 | ||
3b3f1650 | 2155 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2156 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2157 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2158 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2159 | I915_READ(RING_MODE_GEN7(engine))); | |
2160 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2161 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2162 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2163 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2164 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2165 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2166 | } |
2167 | if (dev_priv->mm.aliasing_ppgtt) { | |
2168 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2169 | ||
267f0c90 | 2170 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2171 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2172 | |
87d60b63 | 2173 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2174 | } |
1c60fef5 | 2175 | |
3cf17fc5 | 2176 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2177 | } |
2178 | ||
2179 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2180 | { | |
36cdd013 DW |
2181 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2182 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2183 | struct drm_file *file; |
637ee29e | 2184 | int ret; |
77df6772 | 2185 | |
637ee29e CW |
2186 | mutex_lock(&dev->filelist_mutex); |
2187 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2188 | if (ret) |
637ee29e CW |
2189 | goto out_unlock; |
2190 | ||
c8c8fb33 | 2191 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2192 | |
36cdd013 DW |
2193 | if (INTEL_GEN(dev_priv) >= 8) |
2194 | gen8_ppgtt_info(m, dev_priv); | |
2195 | else if (INTEL_GEN(dev_priv) >= 6) | |
2196 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2197 | |
ea91e401 MT |
2198 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2199 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2200 | struct task_struct *task; |
ea91e401 | 2201 | |
7cb5dff8 | 2202 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2203 | if (!task) { |
2204 | ret = -ESRCH; | |
637ee29e | 2205 | goto out_rpm; |
06812760 | 2206 | } |
7cb5dff8 GT |
2207 | seq_printf(m, "\nproc: %s\n", task->comm); |
2208 | put_task_struct(task); | |
ea91e401 MT |
2209 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2210 | (void *)(unsigned long)m); | |
2211 | } | |
2212 | ||
637ee29e | 2213 | out_rpm: |
c8c8fb33 | 2214 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2215 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2216 | out_unlock: |
2217 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2218 | return ret; |
3cf17fc5 DV |
2219 | } |
2220 | ||
f5a4c67d CW |
2221 | static int count_irq_waiters(struct drm_i915_private *i915) |
2222 | { | |
e2f80391 | 2223 | struct intel_engine_cs *engine; |
3b3f1650 | 2224 | enum intel_engine_id id; |
f5a4c67d | 2225 | int count = 0; |
f5a4c67d | 2226 | |
3b3f1650 | 2227 | for_each_engine(engine, i915, id) |
688e6c72 | 2228 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2229 | |
2230 | return count; | |
2231 | } | |
2232 | ||
7466c291 CW |
2233 | static const char *rps_power_to_str(unsigned int power) |
2234 | { | |
2235 | static const char * const strings[] = { | |
2236 | [LOW_POWER] = "low power", | |
2237 | [BETWEEN] = "mixed", | |
2238 | [HIGH_POWER] = "high power", | |
2239 | }; | |
2240 | ||
2241 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2242 | return "unknown"; | |
2243 | ||
2244 | return strings[power]; | |
2245 | } | |
2246 | ||
1854d5ca CW |
2247 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2248 | { | |
36cdd013 DW |
2249 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2250 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2251 | struct drm_file *file; |
1854d5ca | 2252 | |
f5a4c67d | 2253 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2254 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2255 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2256 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2257 | seq_printf(m, "Frequency requested %d\n", |
2258 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2259 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2260 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2261 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2262 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2263 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2264 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2265 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2266 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2267 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2268 | |
2269 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2270 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2271 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2272 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2273 | struct task_struct *task; | |
2274 | ||
2275 | rcu_read_lock(); | |
2276 | task = pid_task(file->pid, PIDTYPE_PID); | |
2277 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2278 | task ? task->comm : "<unknown>", | |
2279 | task ? task->pid : -1, | |
2e1b8730 CW |
2280 | file_priv->rps.boosts, |
2281 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2282 | rcu_read_unlock(); |
2283 | } | |
197be2ae | 2284 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2285 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2286 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2287 | |
7466c291 CW |
2288 | if (INTEL_GEN(dev_priv) >= 6 && |
2289 | dev_priv->rps.enabled && | |
28176ef4 | 2290 | dev_priv->gt.active_requests) { |
7466c291 CW |
2291 | u32 rpup, rpupei; |
2292 | u32 rpdown, rpdownei; | |
2293 | ||
2294 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2295 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2296 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2297 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2298 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2299 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2300 | ||
2301 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2302 | rps_power_to_str(dev_priv->rps.power)); | |
2303 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2304 | 100 * rpup / rpupei, | |
2305 | dev_priv->rps.up_threshold); | |
2306 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2307 | 100 * rpdown / rpdownei, | |
2308 | dev_priv->rps.down_threshold); | |
2309 | } else { | |
2310 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2311 | } | |
2312 | ||
8d3afd7d | 2313 | return 0; |
1854d5ca CW |
2314 | } |
2315 | ||
63573eb7 BW |
2316 | static int i915_llc(struct seq_file *m, void *data) |
2317 | { | |
36cdd013 | 2318 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2319 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2320 | |
36cdd013 | 2321 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2322 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2323 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2324 | |
2325 | return 0; | |
2326 | } | |
2327 | ||
fdf5d357 AD |
2328 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2329 | { | |
36cdd013 | 2330 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
fdf5d357 AD |
2331 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2332 | u32 tmp, i; | |
2333 | ||
2d1fe073 | 2334 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2335 | return 0; |
2336 | ||
2337 | seq_printf(m, "GuC firmware status:\n"); | |
2338 | seq_printf(m, "\tpath: %s\n", | |
2339 | guc_fw->guc_fw_path); | |
2340 | seq_printf(m, "\tfetch: %s\n", | |
2341 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2342 | seq_printf(m, "\tload: %s\n", | |
2343 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2344 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2345 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2346 | seq_printf(m, "\tversion found: %d.%d\n", | |
2347 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2348 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2349 | guc_fw->header_offset, guc_fw->header_size); | |
2350 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2351 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2352 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2353 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2354 | |
2355 | tmp = I915_READ(GUC_STATUS); | |
2356 | ||
2357 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2358 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2359 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2360 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2361 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2362 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2363 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2364 | seq_puts(m, "\nScratch registers:\n"); | |
2365 | for (i = 0; i < 16; i++) | |
2366 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2367 | ||
2368 | return 0; | |
2369 | } | |
2370 | ||
5aa1ee4b AG |
2371 | static void i915_guc_log_info(struct seq_file *m, |
2372 | struct drm_i915_private *dev_priv) | |
2373 | { | |
2374 | struct intel_guc *guc = &dev_priv->guc; | |
2375 | ||
2376 | seq_puts(m, "\nGuC logging stats:\n"); | |
2377 | ||
2378 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2379 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2380 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2381 | ||
2382 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2383 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2384 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2385 | ||
2386 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2387 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2388 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2389 | ||
2390 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2391 | guc->log.flush_interrupt_count); | |
2392 | ||
2393 | seq_printf(m, "\tCapture miss count: %u\n", | |
2394 | guc->log.capture_miss_count); | |
2395 | } | |
2396 | ||
8b417c26 DG |
2397 | static void i915_guc_client_info(struct seq_file *m, |
2398 | struct drm_i915_private *dev_priv, | |
2399 | struct i915_guc_client *client) | |
2400 | { | |
e2f80391 | 2401 | struct intel_engine_cs *engine; |
c18468c4 | 2402 | enum intel_engine_id id; |
8b417c26 | 2403 | uint64_t tot = 0; |
8b417c26 DG |
2404 | |
2405 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2406 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2407 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2408 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2409 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2410 | client->wq_size, client->wq_offset, client->wq_tail); | |
2411 | ||
551aaecd | 2412 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2413 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2414 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2415 | ||
3b3f1650 | 2416 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2417 | u64 submissions = client->submissions[id]; |
2418 | tot += submissions; | |
8b417c26 | 2419 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2420 | submissions, engine->name); |
8b417c26 DG |
2421 | } |
2422 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2423 | } | |
2424 | ||
2425 | static int i915_guc_info(struct seq_file *m, void *data) | |
2426 | { | |
36cdd013 | 2427 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2428 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2429 | struct intel_engine_cs *engine; |
c18468c4 | 2430 | enum intel_engine_id id; |
334636c6 | 2431 | u64 total; |
8b417c26 | 2432 | |
334636c6 CW |
2433 | if (!guc->execbuf_client) { |
2434 | seq_printf(m, "GuC submission %s\n", | |
2435 | HAS_GUC_SCHED(dev_priv) ? | |
2436 | "disabled" : | |
2437 | "not supported"); | |
5a843307 | 2438 | return 0; |
334636c6 | 2439 | } |
8b417c26 | 2440 | |
9636f6db | 2441 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2442 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2443 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2444 | |
334636c6 CW |
2445 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2446 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2447 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2448 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2449 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2450 | |
334636c6 | 2451 | total = 0; |
8b417c26 | 2452 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2453 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2454 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2455 | total += submissions; |
397097b0 | 2456 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2457 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2458 | } |
2459 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2460 | ||
334636c6 CW |
2461 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2462 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2463 | |
5aa1ee4b AG |
2464 | i915_guc_log_info(m, dev_priv); |
2465 | ||
8b417c26 DG |
2466 | /* Add more as required ... */ |
2467 | ||
2468 | return 0; | |
2469 | } | |
2470 | ||
4c7e77fc AD |
2471 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2472 | { | |
36cdd013 | 2473 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2474 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2475 | int i = 0, pg; |
2476 | ||
d6b40b4b | 2477 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2478 | return 0; |
2479 | ||
d6b40b4b | 2480 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2481 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2482 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2483 | |
2484 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2485 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2486 | *(log + i), *(log + i + 1), | |
2487 | *(log + i + 2), *(log + i + 3)); | |
2488 | ||
2489 | kunmap_atomic(log); | |
2490 | } | |
2491 | ||
2492 | seq_putc(m, '\n'); | |
2493 | ||
2494 | return 0; | |
2495 | } | |
2496 | ||
685534ef SAK |
2497 | static int i915_guc_log_control_get(void *data, u64 *val) |
2498 | { | |
2499 | struct drm_device *dev = data; | |
2500 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2501 | ||
2502 | if (!dev_priv->guc.log.vma) | |
2503 | return -EINVAL; | |
2504 | ||
2505 | *val = i915.guc_log_level; | |
2506 | ||
2507 | return 0; | |
2508 | } | |
2509 | ||
2510 | static int i915_guc_log_control_set(void *data, u64 val) | |
2511 | { | |
2512 | struct drm_device *dev = data; | |
2513 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2514 | int ret; | |
2515 | ||
2516 | if (!dev_priv->guc.log.vma) | |
2517 | return -EINVAL; | |
2518 | ||
2519 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2520 | if (ret) | |
2521 | return ret; | |
2522 | ||
2523 | intel_runtime_pm_get(dev_priv); | |
2524 | ret = i915_guc_log_control(dev_priv, val); | |
2525 | intel_runtime_pm_put(dev_priv); | |
2526 | ||
2527 | mutex_unlock(&dev->struct_mutex); | |
2528 | return ret; | |
2529 | } | |
2530 | ||
2531 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2532 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2533 | "%lld\n"); | |
2534 | ||
e91fd8c6 RV |
2535 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2536 | { | |
36cdd013 | 2537 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2538 | u32 psrperf = 0; |
a6cbdb8e RV |
2539 | u32 stat[3]; |
2540 | enum pipe pipe; | |
a031d709 | 2541 | bool enabled = false; |
e91fd8c6 | 2542 | |
36cdd013 | 2543 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2544 | seq_puts(m, "PSR not supported\n"); |
2545 | return 0; | |
2546 | } | |
2547 | ||
c8c8fb33 PZ |
2548 | intel_runtime_pm_get(dev_priv); |
2549 | ||
fa128fa6 | 2550 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2551 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2552 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2553 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2554 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2555 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2556 | dev_priv->psr.busy_frontbuffer_bits); | |
2557 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2558 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2559 | |
7e3eb599 NV |
2560 | if (HAS_DDI(dev_priv)) { |
2561 | if (dev_priv->psr.psr2_support) | |
2562 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2563 | else | |
2564 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2565 | } else { | |
3553a8ea | 2566 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2567 | enum transcoder cpu_transcoder = |
2568 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2569 | enum intel_display_power_domain power_domain; | |
2570 | ||
2571 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2572 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2573 | power_domain)) | |
2574 | continue; | |
2575 | ||
3553a8ea DL |
2576 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2577 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2578 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2579 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2580 | enabled = true; | |
9c870d03 CW |
2581 | |
2582 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2583 | } |
2584 | } | |
60e5ffe3 RV |
2585 | |
2586 | seq_printf(m, "Main link in standby mode: %s\n", | |
2587 | yesno(dev_priv->psr.link_standby)); | |
2588 | ||
a6cbdb8e RV |
2589 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2590 | ||
36cdd013 | 2591 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2592 | for_each_pipe(dev_priv, pipe) { |
2593 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2594 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2595 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2596 | } | |
2597 | seq_puts(m, "\n"); | |
e91fd8c6 | 2598 | |
05eec3c2 RV |
2599 | /* |
2600 | * VLV/CHV PSR has no kind of performance counter | |
2601 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2602 | */ | |
36cdd013 | 2603 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2604 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2605 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2606 | |
2607 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2608 | } | |
fa128fa6 | 2609 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2610 | |
c8c8fb33 | 2611 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2612 | return 0; |
2613 | } | |
2614 | ||
d2e216d0 RV |
2615 | static int i915_sink_crc(struct seq_file *m, void *data) |
2616 | { | |
36cdd013 DW |
2617 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2618 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2619 | struct intel_connector *connector; |
2620 | struct intel_dp *intel_dp = NULL; | |
2621 | int ret; | |
2622 | u8 crc[6]; | |
2623 | ||
2624 | drm_modeset_lock_all(dev); | |
aca5e361 | 2625 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2626 | struct drm_crtc *crtc; |
d2e216d0 | 2627 | |
26c17cf6 | 2628 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2629 | continue; |
2630 | ||
26c17cf6 ML |
2631 | crtc = connector->base.state->crtc; |
2632 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2633 | continue; |
2634 | ||
26c17cf6 | 2635 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2636 | continue; |
2637 | ||
26c17cf6 | 2638 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2639 | |
2640 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2641 | if (ret) | |
2642 | goto out; | |
2643 | ||
2644 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2645 | crc[0], crc[1], crc[2], | |
2646 | crc[3], crc[4], crc[5]); | |
2647 | goto out; | |
2648 | } | |
2649 | ret = -ENODEV; | |
2650 | out: | |
2651 | drm_modeset_unlock_all(dev); | |
2652 | return ret; | |
2653 | } | |
2654 | ||
ec013e7f JB |
2655 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2656 | { | |
36cdd013 | 2657 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2658 | u64 power; |
2659 | u32 units; | |
2660 | ||
36cdd013 | 2661 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2662 | return -ENODEV; |
2663 | ||
36623ef8 PZ |
2664 | intel_runtime_pm_get(dev_priv); |
2665 | ||
ec013e7f JB |
2666 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2667 | power = (power & 0x1f00) >> 8; | |
2668 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2669 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2670 | power *= units; | |
2671 | ||
36623ef8 PZ |
2672 | intel_runtime_pm_put(dev_priv); |
2673 | ||
ec013e7f | 2674 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2675 | |
2676 | return 0; | |
2677 | } | |
2678 | ||
6455c870 | 2679 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2680 | { |
36cdd013 | 2681 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2682 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2683 | |
a156e64d CW |
2684 | if (!HAS_RUNTIME_PM(dev_priv)) |
2685 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2686 | |
67d97da3 | 2687 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2688 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2689 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2690 | #ifdef CONFIG_PM |
a6aaec8b | 2691 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2692 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2693 | #else |
2694 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2695 | #endif | |
a156e64d | 2696 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2697 | pci_power_name(pdev->current_state), |
2698 | pdev->current_state); | |
371db66a | 2699 | |
ec013e7f JB |
2700 | return 0; |
2701 | } | |
2702 | ||
1da51581 ID |
2703 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2704 | { | |
36cdd013 | 2705 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2706 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2707 | int i; | |
2708 | ||
2709 | mutex_lock(&power_domains->lock); | |
2710 | ||
2711 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2712 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2713 | struct i915_power_well *power_well; | |
2714 | enum intel_display_power_domain power_domain; | |
2715 | ||
2716 | power_well = &power_domains->power_wells[i]; | |
2717 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2718 | power_well->count); | |
2719 | ||
2720 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2721 | power_domain++) { | |
2722 | if (!(BIT(power_domain) & power_well->domains)) | |
2723 | continue; | |
2724 | ||
2725 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2726 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2727 | power_domains->domain_use_count[power_domain]); |
2728 | } | |
2729 | } | |
2730 | ||
2731 | mutex_unlock(&power_domains->lock); | |
2732 | ||
2733 | return 0; | |
2734 | } | |
2735 | ||
b7cec66d DL |
2736 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2737 | { | |
36cdd013 | 2738 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2739 | struct intel_csr *csr; |
2740 | ||
36cdd013 | 2741 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2742 | seq_puts(m, "not supported\n"); |
2743 | return 0; | |
2744 | } | |
2745 | ||
2746 | csr = &dev_priv->csr; | |
2747 | ||
6fb403de MK |
2748 | intel_runtime_pm_get(dev_priv); |
2749 | ||
b7cec66d DL |
2750 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2751 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2752 | ||
2753 | if (!csr->dmc_payload) | |
6fb403de | 2754 | goto out; |
b7cec66d DL |
2755 | |
2756 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2757 | CSR_VERSION_MINOR(csr->version)); | |
2758 | ||
36cdd013 | 2759 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2760 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2761 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2762 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2763 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2764 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2765 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2766 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2767 | } |
2768 | ||
6fb403de MK |
2769 | out: |
2770 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2771 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2772 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2773 | ||
8337206d DL |
2774 | intel_runtime_pm_put(dev_priv); |
2775 | ||
b7cec66d DL |
2776 | return 0; |
2777 | } | |
2778 | ||
53f5e3ca JB |
2779 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2780 | struct drm_display_mode *mode) | |
2781 | { | |
2782 | int i; | |
2783 | ||
2784 | for (i = 0; i < tabs; i++) | |
2785 | seq_putc(m, '\t'); | |
2786 | ||
2787 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2788 | mode->base.id, mode->name, | |
2789 | mode->vrefresh, mode->clock, | |
2790 | mode->hdisplay, mode->hsync_start, | |
2791 | mode->hsync_end, mode->htotal, | |
2792 | mode->vdisplay, mode->vsync_start, | |
2793 | mode->vsync_end, mode->vtotal, | |
2794 | mode->type, mode->flags); | |
2795 | } | |
2796 | ||
2797 | static void intel_encoder_info(struct seq_file *m, | |
2798 | struct intel_crtc *intel_crtc, | |
2799 | struct intel_encoder *intel_encoder) | |
2800 | { | |
36cdd013 DW |
2801 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2802 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2803 | struct drm_crtc *crtc = &intel_crtc->base; |
2804 | struct intel_connector *intel_connector; | |
2805 | struct drm_encoder *encoder; | |
2806 | ||
2807 | encoder = &intel_encoder->base; | |
2808 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2809 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2810 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2811 | struct drm_connector *connector = &intel_connector->base; | |
2812 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2813 | connector->base.id, | |
c23cc417 | 2814 | connector->name, |
53f5e3ca JB |
2815 | drm_get_connector_status_name(connector->status)); |
2816 | if (connector->status == connector_status_connected) { | |
2817 | struct drm_display_mode *mode = &crtc->mode; | |
2818 | seq_printf(m, ", mode:\n"); | |
2819 | intel_seq_print_mode(m, 2, mode); | |
2820 | } else { | |
2821 | seq_putc(m, '\n'); | |
2822 | } | |
2823 | } | |
2824 | } | |
2825 | ||
2826 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2827 | { | |
36cdd013 DW |
2828 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2829 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2830 | struct drm_crtc *crtc = &intel_crtc->base; |
2831 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2832 | struct drm_plane_state *plane_state = crtc->primary->state; |
2833 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2834 | |
23a48d53 | 2835 | if (fb) |
5aa8a937 | 2836 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2837 | fb->base.id, plane_state->src_x >> 16, |
2838 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2839 | else |
2840 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2841 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2842 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2843 | } | |
2844 | ||
2845 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2846 | { | |
2847 | struct drm_display_mode *mode = panel->fixed_mode; | |
2848 | ||
2849 | seq_printf(m, "\tfixed mode:\n"); | |
2850 | intel_seq_print_mode(m, 2, mode); | |
2851 | } | |
2852 | ||
2853 | static void intel_dp_info(struct seq_file *m, | |
2854 | struct intel_connector *intel_connector) | |
2855 | { | |
2856 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2857 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2858 | ||
2859 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2860 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2861 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2862 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2863 | |
2864 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2865 | &intel_dp->aux); | |
53f5e3ca JB |
2866 | } |
2867 | ||
9a148a96 LY |
2868 | static void intel_dp_mst_info(struct seq_file *m, |
2869 | struct intel_connector *intel_connector) | |
2870 | { | |
2871 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2872 | struct intel_dp_mst_encoder *intel_mst = | |
2873 | enc_to_mst(&intel_encoder->base); | |
2874 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2875 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2876 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2877 | intel_connector->port); | |
2878 | ||
2879 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2880 | } | |
2881 | ||
53f5e3ca JB |
2882 | static void intel_hdmi_info(struct seq_file *m, |
2883 | struct intel_connector *intel_connector) | |
2884 | { | |
2885 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2886 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2887 | ||
742f491d | 2888 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2889 | } |
2890 | ||
2891 | static void intel_lvds_info(struct seq_file *m, | |
2892 | struct intel_connector *intel_connector) | |
2893 | { | |
2894 | intel_panel_info(m, &intel_connector->panel); | |
2895 | } | |
2896 | ||
2897 | static void intel_connector_info(struct seq_file *m, | |
2898 | struct drm_connector *connector) | |
2899 | { | |
2900 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2901 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2902 | struct drm_display_mode *mode; |
53f5e3ca JB |
2903 | |
2904 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2905 | connector->base.id, connector->name, |
53f5e3ca JB |
2906 | drm_get_connector_status_name(connector->status)); |
2907 | if (connector->status == connector_status_connected) { | |
2908 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2909 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2910 | connector->display_info.width_mm, | |
2911 | connector->display_info.height_mm); | |
2912 | seq_printf(m, "\tsubpixel order: %s\n", | |
2913 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2914 | seq_printf(m, "\tCEA rev: %d\n", | |
2915 | connector->display_info.cea_rev); | |
2916 | } | |
ee648a74 ML |
2917 | |
2918 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2919 | return; | |
2920 | ||
2921 | switch (connector->connector_type) { | |
2922 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2923 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
2924 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2925 | intel_dp_mst_info(m, intel_connector); | |
2926 | else | |
2927 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
2928 | break; |
2929 | case DRM_MODE_CONNECTOR_LVDS: | |
2930 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2931 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2932 | break; |
2933 | case DRM_MODE_CONNECTOR_HDMIA: | |
2934 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2935 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2936 | intel_hdmi_info(m, intel_connector); | |
2937 | break; | |
2938 | default: | |
2939 | break; | |
36cd7444 | 2940 | } |
53f5e3ca | 2941 | |
f103fc7d JB |
2942 | seq_printf(m, "\tmodes:\n"); |
2943 | list_for_each_entry(mode, &connector->modes, head) | |
2944 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2945 | } |
2946 | ||
36cdd013 | 2947 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 2948 | { |
065f2ec2 CW |
2949 | u32 state; |
2950 | ||
2a307c2e | 2951 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 2952 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2953 | else |
5efb3e28 | 2954 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2955 | |
2956 | return state; | |
2957 | } | |
2958 | ||
36cdd013 DW |
2959 | static bool cursor_position(struct drm_i915_private *dev_priv, |
2960 | int pipe, int *x, int *y) | |
065f2ec2 | 2961 | { |
065f2ec2 CW |
2962 | u32 pos; |
2963 | ||
5efb3e28 | 2964 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2965 | |
2966 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2967 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2968 | *x = -*x; | |
2969 | ||
2970 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2971 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2972 | *y = -*y; | |
2973 | ||
36cdd013 | 2974 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
2975 | } |
2976 | ||
3abc4e09 RF |
2977 | static const char *plane_type(enum drm_plane_type type) |
2978 | { | |
2979 | switch (type) { | |
2980 | case DRM_PLANE_TYPE_OVERLAY: | |
2981 | return "OVL"; | |
2982 | case DRM_PLANE_TYPE_PRIMARY: | |
2983 | return "PRI"; | |
2984 | case DRM_PLANE_TYPE_CURSOR: | |
2985 | return "CUR"; | |
2986 | /* | |
2987 | * Deliberately omitting default: to generate compiler warnings | |
2988 | * when a new drm_plane_type gets added. | |
2989 | */ | |
2990 | } | |
2991 | ||
2992 | return "unknown"; | |
2993 | } | |
2994 | ||
2995 | static const char *plane_rotation(unsigned int rotation) | |
2996 | { | |
2997 | static char buf[48]; | |
2998 | /* | |
2999 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3000 | * will print them all to visualize if the values are misused | |
3001 | */ | |
3002 | snprintf(buf, sizeof(buf), | |
3003 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3004 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3005 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3006 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3007 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3008 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3009 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3010 | rotation); |
3011 | ||
3012 | return buf; | |
3013 | } | |
3014 | ||
3015 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3016 | { | |
36cdd013 DW |
3017 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3018 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3019 | struct intel_plane *intel_plane; |
3020 | ||
3021 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3022 | struct drm_plane_state *state; | |
3023 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3024 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3025 | |
3026 | if (!plane->state) { | |
3027 | seq_puts(m, "plane->state is NULL!\n"); | |
3028 | continue; | |
3029 | } | |
3030 | ||
3031 | state = plane->state; | |
3032 | ||
90844f00 | 3033 | if (state->fb) { |
b3c11ac2 | 3034 | drm_get_format_name(state->fb->pixel_format, &format_name); |
90844f00 | 3035 | } else { |
b3c11ac2 | 3036 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3037 | } |
3038 | ||
3abc4e09 RF |
3039 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3040 | plane->base.id, | |
3041 | plane_type(intel_plane->base.type), | |
3042 | state->crtc_x, state->crtc_y, | |
3043 | state->crtc_w, state->crtc_h, | |
3044 | (state->src_x >> 16), | |
3045 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3046 | (state->src_y >> 16), | |
3047 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3048 | (state->src_w >> 16), | |
3049 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3050 | (state->src_h >> 16), | |
3051 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3052 | format_name.str, |
3abc4e09 RF |
3053 | plane_rotation(state->rotation)); |
3054 | } | |
3055 | } | |
3056 | ||
3057 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3058 | { | |
3059 | struct intel_crtc_state *pipe_config; | |
3060 | int num_scalers = intel_crtc->num_scalers; | |
3061 | int i; | |
3062 | ||
3063 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3064 | ||
3065 | /* Not all platformas have a scaler */ | |
3066 | if (num_scalers) { | |
3067 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3068 | num_scalers, | |
3069 | pipe_config->scaler_state.scaler_users, | |
3070 | pipe_config->scaler_state.scaler_id); | |
3071 | ||
58415918 | 3072 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3073 | struct intel_scaler *sc = |
3074 | &pipe_config->scaler_state.scalers[i]; | |
3075 | ||
3076 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3077 | i, yesno(sc->in_use), sc->mode); | |
3078 | } | |
3079 | seq_puts(m, "\n"); | |
3080 | } else { | |
3081 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3082 | } | |
3083 | } | |
3084 | ||
53f5e3ca JB |
3085 | static int i915_display_info(struct seq_file *m, void *unused) |
3086 | { | |
36cdd013 DW |
3087 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3088 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3089 | struct intel_crtc *crtc; |
53f5e3ca JB |
3090 | struct drm_connector *connector; |
3091 | ||
b0e5ddf3 | 3092 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3093 | drm_modeset_lock_all(dev); |
3094 | seq_printf(m, "CRTC info\n"); | |
3095 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3096 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3097 | bool active; |
f77076c9 | 3098 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3099 | int x, y; |
53f5e3ca | 3100 | |
f77076c9 ML |
3101 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3102 | ||
3abc4e09 | 3103 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3104 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3105 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3106 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3107 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3108 | ||
f77076c9 | 3109 | if (pipe_config->base.active) { |
065f2ec2 CW |
3110 | intel_crtc_info(m, crtc); |
3111 | ||
36cdd013 | 3112 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3113 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3114 | yesno(crtc->cursor_base), |
3dd512fb MR |
3115 | x, y, crtc->base.cursor->state->crtc_w, |
3116 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3117 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3118 | intel_scaler_info(m, crtc); |
3119 | intel_plane_info(m, crtc); | |
a23dc658 | 3120 | } |
cace841c DV |
3121 | |
3122 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3123 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3124 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3125 | } |
3126 | ||
3127 | seq_printf(m, "\n"); | |
3128 | seq_printf(m, "Connector info\n"); | |
3129 | seq_printf(m, "--------------\n"); | |
3130 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3131 | intel_connector_info(m, connector); | |
3132 | } | |
3133 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3134 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3135 | |
3136 | return 0; | |
3137 | } | |
3138 | ||
1b36595f CW |
3139 | static int i915_engine_info(struct seq_file *m, void *unused) |
3140 | { | |
3141 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3142 | struct intel_engine_cs *engine; | |
3b3f1650 | 3143 | enum intel_engine_id id; |
1b36595f | 3144 | |
9c870d03 CW |
3145 | intel_runtime_pm_get(dev_priv); |
3146 | ||
3b3f1650 | 3147 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3148 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3149 | struct drm_i915_gem_request *rq; | |
3150 | struct rb_node *rb; | |
3151 | u64 addr; | |
3152 | ||
3153 | seq_printf(m, "%s\n", engine->name); | |
3fe3b030 | 3154 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n", |
1b36595f | 3155 | intel_engine_get_seqno(engine), |
cb399eab | 3156 | intel_engine_last_submit(engine), |
1b36595f | 3157 | engine->hangcheck.seqno, |
3fe3b030 | 3158 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp)); |
1b36595f CW |
3159 | |
3160 | rcu_read_lock(); | |
3161 | ||
3162 | seq_printf(m, "\tRequests:\n"); | |
3163 | ||
73cb9701 CW |
3164 | rq = list_first_entry(&engine->timeline->requests, |
3165 | struct drm_i915_gem_request, link); | |
3166 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3167 | print_request(m, rq, "\t\tfirst "); |
3168 | ||
73cb9701 CW |
3169 | rq = list_last_entry(&engine->timeline->requests, |
3170 | struct drm_i915_gem_request, link); | |
3171 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3172 | print_request(m, rq, "\t\tlast "); |
3173 | ||
3174 | rq = i915_gem_find_active_request(engine); | |
3175 | if (rq) { | |
3176 | print_request(m, rq, "\t\tactive "); | |
3177 | seq_printf(m, | |
3178 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3179 | rq->head, rq->postfix, rq->tail, | |
3180 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3181 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3182 | } | |
3183 | ||
3184 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3185 | I915_READ(RING_START(engine->mmio_base)), | |
3186 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3187 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3188 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3189 | rq ? rq->ring->head : 0); | |
3190 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3191 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3192 | rq ? rq->ring->tail : 0); | |
3193 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3194 | I915_READ(RING_CTL(engine->mmio_base)), | |
3195 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3196 | ||
3197 | rcu_read_unlock(); | |
3198 | ||
3199 | addr = intel_engine_get_active_head(engine); | |
3200 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3201 | upper_32_bits(addr), lower_32_bits(addr)); | |
3202 | addr = intel_engine_get_last_batch_head(engine); | |
3203 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3204 | upper_32_bits(addr), lower_32_bits(addr)); | |
3205 | ||
3206 | if (i915.enable_execlists) { | |
3207 | u32 ptr, read, write; | |
20311bd3 | 3208 | struct rb_node *rb; |
1b36595f CW |
3209 | |
3210 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3211 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3212 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3213 | ||
3214 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3215 | read = GEN8_CSB_READ_PTR(ptr); | |
3216 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3217 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3218 | read, write); | |
3219 | if (read >= GEN8_CSB_ENTRIES) | |
3220 | read = 0; | |
3221 | if (write >= GEN8_CSB_ENTRIES) | |
3222 | write = 0; | |
3223 | if (read > write) | |
3224 | write += GEN8_CSB_ENTRIES; | |
3225 | while (read < write) { | |
3226 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3227 | ||
3228 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3229 | idx, | |
3230 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3231 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3232 | } | |
3233 | ||
3234 | rcu_read_lock(); | |
3235 | rq = READ_ONCE(engine->execlist_port[0].request); | |
3236 | if (rq) | |
3237 | print_request(m, rq, "\t\tELSP[0] "); | |
3238 | else | |
3239 | seq_printf(m, "\t\tELSP[0] idle\n"); | |
3240 | rq = READ_ONCE(engine->execlist_port[1].request); | |
3241 | if (rq) | |
3242 | print_request(m, rq, "\t\tELSP[1] "); | |
3243 | else | |
3244 | seq_printf(m, "\t\tELSP[1] idle\n"); | |
3245 | rcu_read_unlock(); | |
c8247c06 | 3246 | |
663f71e7 | 3247 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3248 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3249 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3250 | print_request(m, rq, "\t\tQ "); |
3251 | } | |
663f71e7 | 3252 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3253 | } else if (INTEL_GEN(dev_priv) > 6) { |
3254 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3255 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3256 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3257 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3258 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3259 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3260 | } | |
3261 | ||
f6168e33 | 3262 | spin_lock_irq(&b->lock); |
1b36595f | 3263 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3264 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3265 | |
3266 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3267 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3268 | } | |
f6168e33 | 3269 | spin_unlock_irq(&b->lock); |
1b36595f CW |
3270 | |
3271 | seq_puts(m, "\n"); | |
3272 | } | |
3273 | ||
9c870d03 CW |
3274 | intel_runtime_pm_put(dev_priv); |
3275 | ||
1b36595f CW |
3276 | return 0; |
3277 | } | |
3278 | ||
e04934cf BW |
3279 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3280 | { | |
36cdd013 DW |
3281 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3282 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3283 | struct intel_engine_cs *engine; |
36cdd013 | 3284 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3285 | enum intel_engine_id id; |
3286 | int j, ret; | |
e04934cf | 3287 | |
39df9190 | 3288 | if (!i915.semaphores) { |
e04934cf BW |
3289 | seq_puts(m, "Semaphores are disabled\n"); |
3290 | return 0; | |
3291 | } | |
3292 | ||
3293 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3294 | if (ret) | |
3295 | return ret; | |
03872064 | 3296 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3297 | |
36cdd013 | 3298 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3299 | struct page *page; |
3300 | uint64_t *seqno; | |
3301 | ||
51d545d0 | 3302 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3303 | |
3304 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3305 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3306 | uint64_t offset; |
3307 | ||
e2f80391 | 3308 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3309 | |
3310 | seq_puts(m, " Last signal:"); | |
3311 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3312 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3313 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3314 | seqno[offset], offset * 8); | |
3315 | } | |
3316 | seq_putc(m, '\n'); | |
3317 | ||
3318 | seq_puts(m, " Last wait: "); | |
3319 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3320 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3321 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3322 | seqno[offset], offset * 8); | |
3323 | } | |
3324 | seq_putc(m, '\n'); | |
3325 | ||
3326 | } | |
3327 | kunmap_atomic(seqno); | |
3328 | } else { | |
3329 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3330 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3331 | for (j = 0; j < num_rings; j++) |
3332 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3333 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3334 | seq_putc(m, '\n'); |
3335 | } | |
3336 | ||
03872064 | 3337 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3338 | mutex_unlock(&dev->struct_mutex); |
3339 | return 0; | |
3340 | } | |
3341 | ||
728e29d7 DV |
3342 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3343 | { | |
36cdd013 DW |
3344 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3345 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3346 | int i; |
3347 | ||
3348 | drm_modeset_lock_all(dev); | |
3349 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3350 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3351 | ||
3352 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3353 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3354 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3355 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3356 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3357 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3358 | pll->config.hw_state.dpll_md); | |
3359 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3360 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3361 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3362 | } |
3363 | drm_modeset_unlock_all(dev); | |
3364 | ||
3365 | return 0; | |
3366 | } | |
3367 | ||
1ed1ef9d | 3368 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3369 | { |
3370 | int i; | |
3371 | int ret; | |
e2f80391 | 3372 | struct intel_engine_cs *engine; |
36cdd013 DW |
3373 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3374 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3375 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3376 | enum intel_engine_id id; |
888b5995 | 3377 | |
888b5995 AS |
3378 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3379 | if (ret) | |
3380 | return ret; | |
3381 | ||
3382 | intel_runtime_pm_get(dev_priv); | |
3383 | ||
33136b06 | 3384 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3385 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3386 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3387 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3388 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3389 | i915_reg_t addr; |
3390 | u32 mask, value, read; | |
2fa60f6d | 3391 | bool ok; |
888b5995 | 3392 | |
33136b06 AS |
3393 | addr = workarounds->reg[i].addr; |
3394 | mask = workarounds->reg[i].mask; | |
3395 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3396 | read = I915_READ(addr); |
3397 | ok = (value & mask) == (read & mask); | |
3398 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3399 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3400 | } |
3401 | ||
3402 | intel_runtime_pm_put(dev_priv); | |
3403 | mutex_unlock(&dev->struct_mutex); | |
3404 | ||
3405 | return 0; | |
3406 | } | |
3407 | ||
c5511e44 DL |
3408 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3409 | { | |
36cdd013 DW |
3410 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3411 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3412 | struct skl_ddb_allocation *ddb; |
3413 | struct skl_ddb_entry *entry; | |
3414 | enum pipe pipe; | |
3415 | int plane; | |
3416 | ||
36cdd013 | 3417 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3418 | return 0; |
3419 | ||
c5511e44 DL |
3420 | drm_modeset_lock_all(dev); |
3421 | ||
3422 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3423 | ||
3424 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3425 | ||
3426 | for_each_pipe(dev_priv, pipe) { | |
3427 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3428 | ||
8b364b41 | 3429 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3430 | entry = &ddb->plane[pipe][plane]; |
3431 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3432 | entry->start, entry->end, | |
3433 | skl_ddb_entry_size(entry)); | |
3434 | } | |
3435 | ||
4969d33e | 3436 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3437 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3438 | entry->end, skl_ddb_entry_size(entry)); | |
3439 | } | |
3440 | ||
3441 | drm_modeset_unlock_all(dev); | |
3442 | ||
3443 | return 0; | |
3444 | } | |
3445 | ||
a54746e3 | 3446 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3447 | struct drm_device *dev, |
3448 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3449 | { |
fac5e23e | 3450 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3451 | struct i915_drrs *drrs = &dev_priv->drrs; |
3452 | int vrefresh = 0; | |
26875fe5 | 3453 | struct drm_connector *connector; |
a54746e3 | 3454 | |
26875fe5 ML |
3455 | drm_for_each_connector(connector, dev) { |
3456 | if (connector->state->crtc != &intel_crtc->base) | |
3457 | continue; | |
3458 | ||
3459 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3460 | } |
3461 | ||
3462 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3463 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3464 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3465 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3466 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3467 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3468 | else | |
3469 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3470 | ||
3471 | seq_puts(m, "\n\n"); | |
3472 | ||
f77076c9 | 3473 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3474 | struct intel_panel *panel; |
3475 | ||
3476 | mutex_lock(&drrs->mutex); | |
3477 | /* DRRS Supported */ | |
3478 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3479 | ||
3480 | /* disable_drrs() will make drrs->dp NULL */ | |
3481 | if (!drrs->dp) { | |
3482 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3483 | mutex_unlock(&drrs->mutex); | |
3484 | return; | |
3485 | } | |
3486 | ||
3487 | panel = &drrs->dp->attached_connector->panel; | |
3488 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3489 | drrs->busy_frontbuffer_bits); | |
3490 | ||
3491 | seq_puts(m, "\n\t\t"); | |
3492 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3493 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3494 | vrefresh = panel->fixed_mode->vrefresh; | |
3495 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3496 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3497 | vrefresh = panel->downclock_mode->vrefresh; | |
3498 | } else { | |
3499 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3500 | drrs->refresh_rate_type); | |
3501 | mutex_unlock(&drrs->mutex); | |
3502 | return; | |
3503 | } | |
3504 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3505 | ||
3506 | seq_puts(m, "\n\t\t"); | |
3507 | mutex_unlock(&drrs->mutex); | |
3508 | } else { | |
3509 | /* DRRS not supported. Print the VBT parameter*/ | |
3510 | seq_puts(m, "\tDRRS Supported : No"); | |
3511 | } | |
3512 | seq_puts(m, "\n"); | |
3513 | } | |
3514 | ||
3515 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3516 | { | |
36cdd013 DW |
3517 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3518 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3519 | struct intel_crtc *intel_crtc; |
3520 | int active_crtc_cnt = 0; | |
3521 | ||
26875fe5 | 3522 | drm_modeset_lock_all(dev); |
a54746e3 | 3523 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3524 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3525 | active_crtc_cnt++; |
3526 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3527 | ||
3528 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3529 | } | |
a54746e3 | 3530 | } |
26875fe5 | 3531 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3532 | |
3533 | if (!active_crtc_cnt) | |
3534 | seq_puts(m, "No active crtc found\n"); | |
3535 | ||
3536 | return 0; | |
3537 | } | |
3538 | ||
11bed958 DA |
3539 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3540 | { | |
36cdd013 DW |
3541 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3542 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3543 | struct intel_encoder *intel_encoder; |
3544 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3545 | struct drm_connector *connector; |
3546 | ||
11bed958 | 3547 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3548 | drm_for_each_connector(connector, dev) { |
3549 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3550 | continue; |
b6dabe3b ML |
3551 | |
3552 | intel_encoder = intel_attached_encoder(connector); | |
3553 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3554 | continue; | |
3555 | ||
3556 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3557 | if (!intel_dig_port->dp.can_mst) |
3558 | continue; | |
b6dabe3b | 3559 | |
40ae80cc JB |
3560 | seq_printf(m, "MST Source Port %c\n", |
3561 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3562 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3563 | } | |
3564 | drm_modeset_unlock_all(dev); | |
3565 | return 0; | |
3566 | } | |
3567 | ||
eb3394fa | 3568 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3569 | const char __user *ubuf, |
3570 | size_t len, loff_t *offp) | |
eb3394fa TP |
3571 | { |
3572 | char *input_buffer; | |
3573 | int status = 0; | |
eb3394fa TP |
3574 | struct drm_device *dev; |
3575 | struct drm_connector *connector; | |
3576 | struct list_head *connector_list; | |
3577 | struct intel_dp *intel_dp; | |
3578 | int val = 0; | |
3579 | ||
9aaffa34 | 3580 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3581 | |
eb3394fa TP |
3582 | connector_list = &dev->mode_config.connector_list; |
3583 | ||
3584 | if (len == 0) | |
3585 | return 0; | |
3586 | ||
3587 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3588 | if (!input_buffer) | |
3589 | return -ENOMEM; | |
3590 | ||
3591 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3592 | status = -EFAULT; | |
3593 | goto out; | |
3594 | } | |
3595 | ||
3596 | input_buffer[len] = '\0'; | |
3597 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3598 | ||
3599 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
3600 | if (connector->connector_type != |
3601 | DRM_MODE_CONNECTOR_DisplayPort) | |
3602 | continue; | |
3603 | ||
b8bb08ec | 3604 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3605 | connector->encoder != NULL) { |
3606 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3607 | status = kstrtoint(input_buffer, 10, &val); | |
3608 | if (status < 0) | |
3609 | goto out; | |
3610 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
3611 | /* To prevent erroneous activation of the compliance | |
3612 | * testing code, only accept an actual value of 1 here | |
3613 | */ | |
3614 | if (val == 1) | |
c1617abc | 3615 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3616 | else |
c1617abc | 3617 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3618 | } |
3619 | } | |
3620 | out: | |
3621 | kfree(input_buffer); | |
3622 | if (status < 0) | |
3623 | return status; | |
3624 | ||
3625 | *offp += len; | |
3626 | return len; | |
3627 | } | |
3628 | ||
3629 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3630 | { | |
3631 | struct drm_device *dev = m->private; | |
3632 | struct drm_connector *connector; | |
3633 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3634 | struct intel_dp *intel_dp; | |
3635 | ||
eb3394fa | 3636 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3637 | if (connector->connector_type != |
3638 | DRM_MODE_CONNECTOR_DisplayPort) | |
3639 | continue; | |
3640 | ||
3641 | if (connector->status == connector_status_connected && | |
3642 | connector->encoder != NULL) { | |
3643 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3644 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3645 | seq_puts(m, "1"); |
3646 | else | |
3647 | seq_puts(m, "0"); | |
3648 | } else | |
3649 | seq_puts(m, "0"); | |
3650 | } | |
3651 | ||
3652 | return 0; | |
3653 | } | |
3654 | ||
3655 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3656 | struct file *file) |
eb3394fa | 3657 | { |
36cdd013 | 3658 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3659 | |
36cdd013 DW |
3660 | return single_open(file, i915_displayport_test_active_show, |
3661 | &dev_priv->drm); | |
eb3394fa TP |
3662 | } |
3663 | ||
3664 | static const struct file_operations i915_displayport_test_active_fops = { | |
3665 | .owner = THIS_MODULE, | |
3666 | .open = i915_displayport_test_active_open, | |
3667 | .read = seq_read, | |
3668 | .llseek = seq_lseek, | |
3669 | .release = single_release, | |
3670 | .write = i915_displayport_test_active_write | |
3671 | }; | |
3672 | ||
3673 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3674 | { | |
3675 | struct drm_device *dev = m->private; | |
3676 | struct drm_connector *connector; | |
3677 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3678 | struct intel_dp *intel_dp; | |
3679 | ||
eb3394fa | 3680 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3681 | if (connector->connector_type != |
3682 | DRM_MODE_CONNECTOR_DisplayPort) | |
3683 | continue; | |
3684 | ||
3685 | if (connector->status == connector_status_connected && | |
3686 | connector->encoder != NULL) { | |
3687 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3688 | seq_printf(m, "%lx", intel_dp->compliance.test_data.edid); |
eb3394fa TP |
3689 | } else |
3690 | seq_puts(m, "0"); | |
3691 | } | |
3692 | ||
3693 | return 0; | |
3694 | } | |
3695 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3696 | struct file *file) |
eb3394fa | 3697 | { |
36cdd013 | 3698 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3699 | |
36cdd013 DW |
3700 | return single_open(file, i915_displayport_test_data_show, |
3701 | &dev_priv->drm); | |
eb3394fa TP |
3702 | } |
3703 | ||
3704 | static const struct file_operations i915_displayport_test_data_fops = { | |
3705 | .owner = THIS_MODULE, | |
3706 | .open = i915_displayport_test_data_open, | |
3707 | .read = seq_read, | |
3708 | .llseek = seq_lseek, | |
3709 | .release = single_release | |
3710 | }; | |
3711 | ||
3712 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3713 | { | |
3714 | struct drm_device *dev = m->private; | |
3715 | struct drm_connector *connector; | |
3716 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3717 | struct intel_dp *intel_dp; | |
3718 | ||
eb3394fa | 3719 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3720 | if (connector->connector_type != |
3721 | DRM_MODE_CONNECTOR_DisplayPort) | |
3722 | continue; | |
3723 | ||
3724 | if (connector->status == connector_status_connected && | |
3725 | connector->encoder != NULL) { | |
3726 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3727 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3728 | } else |
3729 | seq_puts(m, "0"); | |
3730 | } | |
3731 | ||
3732 | return 0; | |
3733 | } | |
3734 | ||
3735 | static int i915_displayport_test_type_open(struct inode *inode, | |
3736 | struct file *file) | |
3737 | { | |
36cdd013 | 3738 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3739 | |
36cdd013 DW |
3740 | return single_open(file, i915_displayport_test_type_show, |
3741 | &dev_priv->drm); | |
eb3394fa TP |
3742 | } |
3743 | ||
3744 | static const struct file_operations i915_displayport_test_type_fops = { | |
3745 | .owner = THIS_MODULE, | |
3746 | .open = i915_displayport_test_type_open, | |
3747 | .read = seq_read, | |
3748 | .llseek = seq_lseek, | |
3749 | .release = single_release | |
3750 | }; | |
3751 | ||
97e94b22 | 3752 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3753 | { |
36cdd013 DW |
3754 | struct drm_i915_private *dev_priv = m->private; |
3755 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3756 | int level; |
de38b95c VS |
3757 | int num_levels; |
3758 | ||
36cdd013 | 3759 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3760 | num_levels = 3; |
36cdd013 | 3761 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3762 | num_levels = 1; |
3763 | else | |
5db94019 | 3764 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3765 | |
3766 | drm_modeset_lock_all(dev); | |
3767 | ||
3768 | for (level = 0; level < num_levels; level++) { | |
3769 | unsigned int latency = wm[level]; | |
3770 | ||
97e94b22 DL |
3771 | /* |
3772 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3773 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3774 | */ |
36cdd013 DW |
3775 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3776 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3777 | latency *= 10; |
3778 | else if (level > 0) | |
369a1342 VS |
3779 | latency *= 5; |
3780 | ||
3781 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3782 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3783 | } |
3784 | ||
3785 | drm_modeset_unlock_all(dev); | |
3786 | } | |
3787 | ||
3788 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3789 | { | |
36cdd013 | 3790 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3791 | const uint16_t *latencies; |
3792 | ||
36cdd013 | 3793 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3794 | latencies = dev_priv->wm.skl_latency; |
3795 | else | |
36cdd013 | 3796 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3797 | |
97e94b22 | 3798 | wm_latency_show(m, latencies); |
369a1342 VS |
3799 | |
3800 | return 0; | |
3801 | } | |
3802 | ||
3803 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3804 | { | |
36cdd013 | 3805 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3806 | const uint16_t *latencies; |
3807 | ||
36cdd013 | 3808 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3809 | latencies = dev_priv->wm.skl_latency; |
3810 | else | |
36cdd013 | 3811 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3812 | |
97e94b22 | 3813 | wm_latency_show(m, latencies); |
369a1342 VS |
3814 | |
3815 | return 0; | |
3816 | } | |
3817 | ||
3818 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3819 | { | |
36cdd013 | 3820 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3821 | const uint16_t *latencies; |
3822 | ||
36cdd013 | 3823 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3824 | latencies = dev_priv->wm.skl_latency; |
3825 | else | |
36cdd013 | 3826 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3827 | |
97e94b22 | 3828 | wm_latency_show(m, latencies); |
369a1342 VS |
3829 | |
3830 | return 0; | |
3831 | } | |
3832 | ||
3833 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3834 | { | |
36cdd013 | 3835 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3836 | |
36cdd013 | 3837 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3838 | return -ENODEV; |
3839 | ||
36cdd013 | 3840 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3841 | } |
3842 | ||
3843 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3844 | { | |
36cdd013 | 3845 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3846 | |
36cdd013 | 3847 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3848 | return -ENODEV; |
3849 | ||
36cdd013 | 3850 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3851 | } |
3852 | ||
3853 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3854 | { | |
36cdd013 | 3855 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3856 | |
36cdd013 | 3857 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3858 | return -ENODEV; |
3859 | ||
36cdd013 | 3860 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3861 | } |
3862 | ||
3863 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3864 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3865 | { |
3866 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3867 | struct drm_i915_private *dev_priv = m->private; |
3868 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3869 | uint16_t new[8] = { 0 }; |
de38b95c | 3870 | int num_levels; |
369a1342 VS |
3871 | int level; |
3872 | int ret; | |
3873 | char tmp[32]; | |
3874 | ||
36cdd013 | 3875 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3876 | num_levels = 3; |
36cdd013 | 3877 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3878 | num_levels = 1; |
3879 | else | |
5db94019 | 3880 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 3881 | |
369a1342 VS |
3882 | if (len >= sizeof(tmp)) |
3883 | return -EINVAL; | |
3884 | ||
3885 | if (copy_from_user(tmp, ubuf, len)) | |
3886 | return -EFAULT; | |
3887 | ||
3888 | tmp[len] = '\0'; | |
3889 | ||
97e94b22 DL |
3890 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3891 | &new[0], &new[1], &new[2], &new[3], | |
3892 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3893 | if (ret != num_levels) |
3894 | return -EINVAL; | |
3895 | ||
3896 | drm_modeset_lock_all(dev); | |
3897 | ||
3898 | for (level = 0; level < num_levels; level++) | |
3899 | wm[level] = new[level]; | |
3900 | ||
3901 | drm_modeset_unlock_all(dev); | |
3902 | ||
3903 | return len; | |
3904 | } | |
3905 | ||
3906 | ||
3907 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3908 | size_t len, loff_t *offp) | |
3909 | { | |
3910 | struct seq_file *m = file->private_data; | |
36cdd013 | 3911 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3912 | uint16_t *latencies; |
369a1342 | 3913 | |
36cdd013 | 3914 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3915 | latencies = dev_priv->wm.skl_latency; |
3916 | else | |
36cdd013 | 3917 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
3918 | |
3919 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3920 | } |
3921 | ||
3922 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3923 | size_t len, loff_t *offp) | |
3924 | { | |
3925 | struct seq_file *m = file->private_data; | |
36cdd013 | 3926 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3927 | uint16_t *latencies; |
369a1342 | 3928 | |
36cdd013 | 3929 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3930 | latencies = dev_priv->wm.skl_latency; |
3931 | else | |
36cdd013 | 3932 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
3933 | |
3934 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3935 | } |
3936 | ||
3937 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3938 | size_t len, loff_t *offp) | |
3939 | { | |
3940 | struct seq_file *m = file->private_data; | |
36cdd013 | 3941 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3942 | uint16_t *latencies; |
3943 | ||
36cdd013 | 3944 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3945 | latencies = dev_priv->wm.skl_latency; |
3946 | else | |
36cdd013 | 3947 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3948 | |
97e94b22 | 3949 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
3950 | } |
3951 | ||
3952 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3953 | .owner = THIS_MODULE, | |
3954 | .open = pri_wm_latency_open, | |
3955 | .read = seq_read, | |
3956 | .llseek = seq_lseek, | |
3957 | .release = single_release, | |
3958 | .write = pri_wm_latency_write | |
3959 | }; | |
3960 | ||
3961 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3962 | .owner = THIS_MODULE, | |
3963 | .open = spr_wm_latency_open, | |
3964 | .read = seq_read, | |
3965 | .llseek = seq_lseek, | |
3966 | .release = single_release, | |
3967 | .write = spr_wm_latency_write | |
3968 | }; | |
3969 | ||
3970 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3971 | .owner = THIS_MODULE, | |
3972 | .open = cur_wm_latency_open, | |
3973 | .read = seq_read, | |
3974 | .llseek = seq_lseek, | |
3975 | .release = single_release, | |
3976 | .write = cur_wm_latency_write | |
3977 | }; | |
3978 | ||
647416f9 KC |
3979 | static int |
3980 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3981 | { |
36cdd013 | 3982 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 3983 | |
d98c52cf | 3984 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 3985 | |
647416f9 | 3986 | return 0; |
f3cd474b CW |
3987 | } |
3988 | ||
647416f9 KC |
3989 | static int |
3990 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3991 | { |
36cdd013 | 3992 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 3993 | |
b8d24a06 MK |
3994 | /* |
3995 | * There is no safeguard against this debugfs entry colliding | |
3996 | * with the hangcheck calling same i915_handle_error() in | |
3997 | * parallel, causing an explosion. For now we assume that the | |
3998 | * test harness is responsible enough not to inject gpu hangs | |
3999 | * while it is writing to 'i915_wedged' | |
4000 | */ | |
4001 | ||
d98c52cf | 4002 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4003 | return -EAGAIN; |
4004 | ||
c033666a | 4005 | i915_handle_error(dev_priv, val, |
58174462 | 4006 | "Manually setting wedged to %llu", val); |
d46c0517 | 4007 | |
647416f9 | 4008 | return 0; |
f3cd474b CW |
4009 | } |
4010 | ||
647416f9 KC |
4011 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4012 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4013 | "%llu\n"); |
f3cd474b | 4014 | |
094f9a54 CW |
4015 | static int |
4016 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4017 | { | |
36cdd013 | 4018 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4019 | |
4020 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4021 | return 0; | |
4022 | } | |
4023 | ||
4024 | static int | |
4025 | i915_ring_missed_irq_set(void *data, u64 val) | |
4026 | { | |
36cdd013 DW |
4027 | struct drm_i915_private *dev_priv = data; |
4028 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4029 | int ret; |
4030 | ||
4031 | /* Lock against concurrent debugfs callers */ | |
4032 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4033 | if (ret) | |
4034 | return ret; | |
4035 | dev_priv->gpu_error.missed_irq_rings = val; | |
4036 | mutex_unlock(&dev->struct_mutex); | |
4037 | ||
4038 | return 0; | |
4039 | } | |
4040 | ||
4041 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4042 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4043 | "0x%08llx\n"); | |
4044 | ||
4045 | static int | |
4046 | i915_ring_test_irq_get(void *data, u64 *val) | |
4047 | { | |
36cdd013 | 4048 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4049 | |
4050 | *val = dev_priv->gpu_error.test_irq_rings; | |
4051 | ||
4052 | return 0; | |
4053 | } | |
4054 | ||
4055 | static int | |
4056 | i915_ring_test_irq_set(void *data, u64 val) | |
4057 | { | |
36cdd013 | 4058 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4059 | |
3a122c27 | 4060 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4061 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4062 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4063 | |
4064 | return 0; | |
4065 | } | |
4066 | ||
4067 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4068 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4069 | "0x%08llx\n"); | |
4070 | ||
dd624afd CW |
4071 | #define DROP_UNBOUND 0x1 |
4072 | #define DROP_BOUND 0x2 | |
4073 | #define DROP_RETIRE 0x4 | |
4074 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4075 | #define DROP_FREED 0x10 |
4076 | #define DROP_ALL (DROP_UNBOUND | \ | |
4077 | DROP_BOUND | \ | |
4078 | DROP_RETIRE | \ | |
4079 | DROP_ACTIVE | \ | |
4080 | DROP_FREED) | |
647416f9 KC |
4081 | static int |
4082 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4083 | { |
647416f9 | 4084 | *val = DROP_ALL; |
dd624afd | 4085 | |
647416f9 | 4086 | return 0; |
dd624afd CW |
4087 | } |
4088 | ||
647416f9 KC |
4089 | static int |
4090 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4091 | { |
36cdd013 DW |
4092 | struct drm_i915_private *dev_priv = data; |
4093 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4094 | int ret; |
dd624afd | 4095 | |
2f9fe5ff | 4096 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4097 | |
4098 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4099 | * on ioctls on -EAGAIN. */ | |
4100 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4101 | if (ret) | |
4102 | return ret; | |
4103 | ||
4104 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4105 | ret = i915_gem_wait_for_idle(dev_priv, |
4106 | I915_WAIT_INTERRUPTIBLE | | |
4107 | I915_WAIT_LOCKED); | |
dd624afd CW |
4108 | if (ret) |
4109 | goto unlock; | |
4110 | } | |
4111 | ||
4112 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4113 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4114 | |
21ab4e74 CW |
4115 | if (val & DROP_BOUND) |
4116 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4117 | |
21ab4e74 CW |
4118 | if (val & DROP_UNBOUND) |
4119 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4120 | |
4121 | unlock: | |
4122 | mutex_unlock(&dev->struct_mutex); | |
4123 | ||
fbbd37b3 CW |
4124 | if (val & DROP_FREED) { |
4125 | synchronize_rcu(); | |
bdeb9785 | 4126 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4127 | } |
4128 | ||
647416f9 | 4129 | return ret; |
dd624afd CW |
4130 | } |
4131 | ||
647416f9 KC |
4132 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4133 | i915_drop_caches_get, i915_drop_caches_set, | |
4134 | "0x%08llx\n"); | |
dd624afd | 4135 | |
647416f9 KC |
4136 | static int |
4137 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4138 | { |
36cdd013 | 4139 | struct drm_i915_private *dev_priv = data; |
004777cb | 4140 | |
36cdd013 | 4141 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4142 | return -ENODEV; |
4143 | ||
7c59a9c1 | 4144 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4145 | return 0; |
358733e9 JB |
4146 | } |
4147 | ||
647416f9 KC |
4148 | static int |
4149 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4150 | { |
36cdd013 | 4151 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4152 | u32 hw_max, hw_min; |
647416f9 | 4153 | int ret; |
004777cb | 4154 | |
36cdd013 | 4155 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4156 | return -ENODEV; |
358733e9 | 4157 | |
647416f9 | 4158 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4159 | |
4fc688ce | 4160 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4161 | if (ret) |
4162 | return ret; | |
4163 | ||
358733e9 JB |
4164 | /* |
4165 | * Turbo will still be enabled, but won't go above the set value. | |
4166 | */ | |
bc4d91f6 | 4167 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4168 | |
bc4d91f6 AG |
4169 | hw_max = dev_priv->rps.max_freq; |
4170 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4171 | |
b39fb297 | 4172 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4173 | mutex_unlock(&dev_priv->rps.hw_lock); |
4174 | return -EINVAL; | |
0a073b84 JB |
4175 | } |
4176 | ||
b39fb297 | 4177 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4178 | |
dc97997a | 4179 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4180 | |
4fc688ce | 4181 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4182 | |
647416f9 | 4183 | return 0; |
358733e9 JB |
4184 | } |
4185 | ||
647416f9 KC |
4186 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4187 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4188 | "%llu\n"); |
358733e9 | 4189 | |
647416f9 KC |
4190 | static int |
4191 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4192 | { |
36cdd013 | 4193 | struct drm_i915_private *dev_priv = data; |
004777cb | 4194 | |
62e1baa1 | 4195 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4196 | return -ENODEV; |
4197 | ||
7c59a9c1 | 4198 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4199 | return 0; |
1523c310 JB |
4200 | } |
4201 | ||
647416f9 KC |
4202 | static int |
4203 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4204 | { |
36cdd013 | 4205 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4206 | u32 hw_max, hw_min; |
647416f9 | 4207 | int ret; |
004777cb | 4208 | |
62e1baa1 | 4209 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4210 | return -ENODEV; |
1523c310 | 4211 | |
647416f9 | 4212 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4213 | |
4fc688ce | 4214 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4215 | if (ret) |
4216 | return ret; | |
4217 | ||
1523c310 JB |
4218 | /* |
4219 | * Turbo will still be enabled, but won't go below the set value. | |
4220 | */ | |
bc4d91f6 | 4221 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4222 | |
bc4d91f6 AG |
4223 | hw_max = dev_priv->rps.max_freq; |
4224 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4225 | |
36cdd013 DW |
4226 | if (val < hw_min || |
4227 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4228 | mutex_unlock(&dev_priv->rps.hw_lock); |
4229 | return -EINVAL; | |
0a073b84 | 4230 | } |
dd0a1aa1 | 4231 | |
b39fb297 | 4232 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4233 | |
dc97997a | 4234 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4235 | |
4fc688ce | 4236 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4237 | |
647416f9 | 4238 | return 0; |
1523c310 JB |
4239 | } |
4240 | ||
647416f9 KC |
4241 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4242 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4243 | "%llu\n"); |
1523c310 | 4244 | |
647416f9 KC |
4245 | static int |
4246 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4247 | { |
36cdd013 | 4248 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4249 | u32 snpcr; |
07b7ddd9 | 4250 | |
36cdd013 | 4251 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4252 | return -ENODEV; |
4253 | ||
c8c8fb33 | 4254 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4255 | |
07b7ddd9 | 4256 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4257 | |
4258 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4259 | |
647416f9 | 4260 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4261 | |
647416f9 | 4262 | return 0; |
07b7ddd9 JB |
4263 | } |
4264 | ||
647416f9 KC |
4265 | static int |
4266 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4267 | { |
36cdd013 | 4268 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4269 | u32 snpcr; |
07b7ddd9 | 4270 | |
36cdd013 | 4271 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4272 | return -ENODEV; |
4273 | ||
647416f9 | 4274 | if (val > 3) |
07b7ddd9 JB |
4275 | return -EINVAL; |
4276 | ||
c8c8fb33 | 4277 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4278 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4279 | |
4280 | /* Update the cache sharing policy here as well */ | |
4281 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4282 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4283 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4284 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4285 | ||
c8c8fb33 | 4286 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4287 | return 0; |
07b7ddd9 JB |
4288 | } |
4289 | ||
647416f9 KC |
4290 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4291 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4292 | "%llu\n"); | |
07b7ddd9 | 4293 | |
36cdd013 | 4294 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4295 | struct sseu_dev_info *sseu) |
5d39525a | 4296 | { |
0a0b457f | 4297 | int ss_max = 2; |
5d39525a JM |
4298 | int ss; |
4299 | u32 sig1[ss_max], sig2[ss_max]; | |
4300 | ||
4301 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4302 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4303 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4304 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4305 | ||
4306 | for (ss = 0; ss < ss_max; ss++) { | |
4307 | unsigned int eu_cnt; | |
4308 | ||
4309 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4310 | /* skip disabled subslice */ | |
4311 | continue; | |
4312 | ||
f08a0c92 | 4313 | sseu->slice_mask = BIT(0); |
57ec171e | 4314 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4315 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4316 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4317 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4318 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4319 | sseu->eu_total += eu_cnt; |
4320 | sseu->eu_per_subslice = max_t(unsigned int, | |
4321 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4322 | } |
5d39525a JM |
4323 | } |
4324 | ||
36cdd013 | 4325 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4326 | struct sseu_dev_info *sseu) |
5d39525a | 4327 | { |
1c046bc1 | 4328 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4329 | int s, ss; |
4330 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4331 | ||
1c046bc1 | 4332 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4333 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4334 | s_max = 1; |
4335 | ss_max = 3; | |
4336 | } | |
4337 | ||
4338 | for (s = 0; s < s_max; s++) { | |
4339 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4340 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4341 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4342 | } | |
4343 | ||
5d39525a JM |
4344 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4345 | GEN9_PGCTL_SSA_EU19_ACK | | |
4346 | GEN9_PGCTL_SSA_EU210_ACK | | |
4347 | GEN9_PGCTL_SSA_EU311_ACK; | |
4348 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4349 | GEN9_PGCTL_SSB_EU19_ACK | | |
4350 | GEN9_PGCTL_SSB_EU210_ACK | | |
4351 | GEN9_PGCTL_SSB_EU311_ACK; | |
4352 | ||
4353 | for (s = 0; s < s_max; s++) { | |
4354 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4355 | /* skip disabled slice */ | |
4356 | continue; | |
4357 | ||
f08a0c92 | 4358 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4359 | |
36cdd013 | 4360 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
57ec171e ID |
4361 | sseu->subslice_mask = |
4362 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4363 | |
5d39525a JM |
4364 | for (ss = 0; ss < ss_max; ss++) { |
4365 | unsigned int eu_cnt; | |
4366 | ||
cc3f90f0 | 4367 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4368 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4369 | /* skip disabled subslice */ | |
4370 | continue; | |
1c046bc1 | 4371 | |
57ec171e ID |
4372 | sseu->subslice_mask |= BIT(ss); |
4373 | } | |
1c046bc1 | 4374 | |
5d39525a JM |
4375 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4376 | eu_mask[ss%2]); | |
915490d5 ID |
4377 | sseu->eu_total += eu_cnt; |
4378 | sseu->eu_per_subslice = max_t(unsigned int, | |
4379 | sseu->eu_per_subslice, | |
4380 | eu_cnt); | |
5d39525a JM |
4381 | } |
4382 | } | |
4383 | } | |
4384 | ||
36cdd013 | 4385 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4386 | struct sseu_dev_info *sseu) |
91bedd34 | 4387 | { |
91bedd34 | 4388 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4389 | int s; |
91bedd34 | 4390 | |
f08a0c92 | 4391 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4392 | |
f08a0c92 | 4393 | if (sseu->slice_mask) { |
57ec171e | 4394 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4395 | sseu->eu_per_subslice = |
4396 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4397 | sseu->eu_total = sseu->eu_per_subslice * |
4398 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4399 | |
4400 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4401 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4402 | u8 subslice_7eu = |
4403 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4404 | |
915490d5 | 4405 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4406 | } |
4407 | } | |
4408 | } | |
4409 | ||
615d8908 ID |
4410 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4411 | const struct sseu_dev_info *sseu) | |
4412 | { | |
4413 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4414 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4415 | ||
c67ba538 ID |
4416 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4417 | sseu->slice_mask); | |
615d8908 | 4418 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4419 | hweight8(sseu->slice_mask)); |
615d8908 | 4420 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4421 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4422 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4423 | sseu->subslice_mask); | |
615d8908 | 4424 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4425 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4426 | seq_printf(m, " %s EU Total: %u\n", type, |
4427 | sseu->eu_total); | |
4428 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4429 | sseu->eu_per_subslice); | |
4430 | ||
4431 | if (!is_available_info) | |
4432 | return; | |
4433 | ||
4434 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4435 | if (HAS_POOLED_EU(dev_priv)) | |
4436 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4437 | ||
4438 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4439 | yesno(sseu->has_slice_pg)); | |
4440 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4441 | yesno(sseu->has_subslice_pg)); | |
4442 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4443 | yesno(sseu->has_eu_pg)); | |
4444 | } | |
4445 | ||
3873218f JM |
4446 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4447 | { | |
36cdd013 | 4448 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4449 | struct sseu_dev_info sseu; |
3873218f | 4450 | |
36cdd013 | 4451 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4452 | return -ENODEV; |
4453 | ||
4454 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4455 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4456 | |
7f992aba | 4457 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4458 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4459 | |
4460 | intel_runtime_pm_get(dev_priv); | |
4461 | ||
36cdd013 | 4462 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4463 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4464 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4465 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4466 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4467 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4468 | } |
238010ed DW |
4469 | |
4470 | intel_runtime_pm_put(dev_priv); | |
4471 | ||
615d8908 | 4472 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4473 | |
3873218f JM |
4474 | return 0; |
4475 | } | |
4476 | ||
6d794d42 BW |
4477 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4478 | { | |
36cdd013 | 4479 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4480 | |
36cdd013 | 4481 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4482 | return 0; |
4483 | ||
6daccb0b | 4484 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4485 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4486 | |
4487 | return 0; | |
4488 | } | |
4489 | ||
c43b5634 | 4490 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4491 | { |
36cdd013 | 4492 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4493 | |
36cdd013 | 4494 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4495 | return 0; |
4496 | ||
59bad947 | 4497 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4498 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4499 | |
4500 | return 0; | |
4501 | } | |
4502 | ||
4503 | static const struct file_operations i915_forcewake_fops = { | |
4504 | .owner = THIS_MODULE, | |
4505 | .open = i915_forcewake_open, | |
4506 | .release = i915_forcewake_release, | |
4507 | }; | |
4508 | ||
4509 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4510 | { | |
6d794d42 BW |
4511 | struct dentry *ent; |
4512 | ||
4513 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4514 | S_IRUSR, |
36cdd013 | 4515 | root, to_i915(minor->dev), |
6d794d42 | 4516 | &i915_forcewake_fops); |
f3c5fe97 WY |
4517 | if (!ent) |
4518 | return -ENOMEM; | |
6d794d42 | 4519 | |
8eb57294 | 4520 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4521 | } |
4522 | ||
6a9c308d DV |
4523 | static int i915_debugfs_create(struct dentry *root, |
4524 | struct drm_minor *minor, | |
4525 | const char *name, | |
4526 | const struct file_operations *fops) | |
07b7ddd9 | 4527 | { |
07b7ddd9 JB |
4528 | struct dentry *ent; |
4529 | ||
6a9c308d | 4530 | ent = debugfs_create_file(name, |
07b7ddd9 | 4531 | S_IRUGO | S_IWUSR, |
36cdd013 | 4532 | root, to_i915(minor->dev), |
6a9c308d | 4533 | fops); |
f3c5fe97 WY |
4534 | if (!ent) |
4535 | return -ENOMEM; | |
07b7ddd9 | 4536 | |
6a9c308d | 4537 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4538 | } |
4539 | ||
06c5bf8c | 4540 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4541 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4542 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4543 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4544 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4545 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4546 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4547 | {"i915_gem_request", i915_gem_request_info, 0}, |
4548 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4549 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4550 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4551 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4552 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4553 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4554 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 4555 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4556 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4557 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4558 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4559 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4560 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4561 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4562 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4563 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4564 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4565 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4566 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4567 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4568 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4569 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4570 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4571 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4572 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4573 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4574 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4575 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4576 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4577 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4578 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4579 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4580 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4581 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4582 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4583 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4584 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4585 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4586 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4587 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4588 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4589 | }; |
27c202ad | 4590 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4591 | |
06c5bf8c | 4592 | static const struct i915_debugfs_files { |
34b9674c DV |
4593 | const char *name; |
4594 | const struct file_operations *fops; | |
4595 | } i915_debugfs_files[] = { | |
4596 | {"i915_wedged", &i915_wedged_fops}, | |
4597 | {"i915_max_freq", &i915_max_freq_fops}, | |
4598 | {"i915_min_freq", &i915_min_freq_fops}, | |
4599 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4600 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4601 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4602 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4603 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4604 | {"i915_error_state", &i915_error_state_fops}, |
98a2f411 | 4605 | #endif |
34b9674c | 4606 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4607 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4608 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4609 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4610 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4611 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4612 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4613 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef SAK |
4614 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
4615 | {"i915_guc_log_control", &i915_guc_log_control_fops} | |
34b9674c DV |
4616 | }; |
4617 | ||
1dac891c | 4618 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4619 | { |
91c8a326 | 4620 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 4621 | int ret, i; |
f3cd474b | 4622 | |
6d794d42 | 4623 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4624 | if (ret) |
4625 | return ret; | |
6a9c308d | 4626 | |
731035fe TV |
4627 | ret = intel_pipe_crc_create(minor); |
4628 | if (ret) | |
4629 | return ret; | |
07144428 | 4630 | |
34b9674c DV |
4631 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4632 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4633 | i915_debugfs_files[i].name, | |
4634 | i915_debugfs_files[i].fops); | |
4635 | if (ret) | |
4636 | return ret; | |
4637 | } | |
40633219 | 4638 | |
27c202ad BG |
4639 | return drm_debugfs_create_files(i915_debugfs_list, |
4640 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4641 | minor->debugfs_root, minor); |
4642 | } | |
4643 | ||
1dac891c | 4644 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 4645 | { |
91c8a326 | 4646 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
4647 | int i; |
4648 | ||
27c202ad BG |
4649 | drm_debugfs_remove_files(i915_debugfs_list, |
4650 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4651 | |
36cdd013 | 4652 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 4653 | 1, minor); |
07144428 | 4654 | |
731035fe | 4655 | intel_pipe_crc_cleanup(minor); |
07144428 | 4656 | |
34b9674c DV |
4657 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4658 | struct drm_info_list *info_list = | |
36cdd013 | 4659 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
4660 | |
4661 | drm_debugfs_remove_files(info_list, 1, minor); | |
4662 | } | |
2017263e | 4663 | } |
aa7471d2 JN |
4664 | |
4665 | struct dpcd_block { | |
4666 | /* DPCD dump start address. */ | |
4667 | unsigned int offset; | |
4668 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4669 | unsigned int end; | |
4670 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4671 | size_t size; | |
4672 | /* Only valid for eDP. */ | |
4673 | bool edp; | |
4674 | }; | |
4675 | ||
4676 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4677 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4678 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4679 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4680 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4681 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4682 | { .offset = DP_SET_POWER }, | |
4683 | { .offset = DP_EDP_DPCD_REV }, | |
4684 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4685 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4686 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4687 | }; | |
4688 | ||
4689 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4690 | { | |
4691 | struct drm_connector *connector = m->private; | |
4692 | struct intel_dp *intel_dp = | |
4693 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4694 | uint8_t buf[16]; | |
4695 | ssize_t err; | |
4696 | int i; | |
4697 | ||
5c1a8875 MK |
4698 | if (connector->status != connector_status_connected) |
4699 | return -ENODEV; | |
4700 | ||
aa7471d2 JN |
4701 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4702 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4703 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4704 | ||
4705 | if (b->edp && | |
4706 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4707 | continue; | |
4708 | ||
4709 | /* low tech for now */ | |
4710 | if (WARN_ON(size > sizeof(buf))) | |
4711 | continue; | |
4712 | ||
4713 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4714 | if (err <= 0) { | |
4715 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4716 | size, b->offset, err); | |
4717 | continue; | |
4718 | } | |
4719 | ||
4720 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4721 | } |
aa7471d2 JN |
4722 | |
4723 | return 0; | |
4724 | } | |
4725 | ||
4726 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4727 | { | |
4728 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4729 | } | |
4730 | ||
4731 | static const struct file_operations i915_dpcd_fops = { | |
4732 | .owner = THIS_MODULE, | |
4733 | .open = i915_dpcd_open, | |
4734 | .read = seq_read, | |
4735 | .llseek = seq_lseek, | |
4736 | .release = single_release, | |
4737 | }; | |
4738 | ||
ecbd6781 DW |
4739 | static int i915_panel_show(struct seq_file *m, void *data) |
4740 | { | |
4741 | struct drm_connector *connector = m->private; | |
4742 | struct intel_dp *intel_dp = | |
4743 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4744 | ||
4745 | if (connector->status != connector_status_connected) | |
4746 | return -ENODEV; | |
4747 | ||
4748 | seq_printf(m, "Panel power up delay: %d\n", | |
4749 | intel_dp->panel_power_up_delay); | |
4750 | seq_printf(m, "Panel power down delay: %d\n", | |
4751 | intel_dp->panel_power_down_delay); | |
4752 | seq_printf(m, "Backlight on delay: %d\n", | |
4753 | intel_dp->backlight_on_delay); | |
4754 | seq_printf(m, "Backlight off delay: %d\n", | |
4755 | intel_dp->backlight_off_delay); | |
4756 | ||
4757 | return 0; | |
4758 | } | |
4759 | ||
4760 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4761 | { | |
4762 | return single_open(file, i915_panel_show, inode->i_private); | |
4763 | } | |
4764 | ||
4765 | static const struct file_operations i915_panel_fops = { | |
4766 | .owner = THIS_MODULE, | |
4767 | .open = i915_panel_open, | |
4768 | .read = seq_read, | |
4769 | .llseek = seq_lseek, | |
4770 | .release = single_release, | |
4771 | }; | |
4772 | ||
aa7471d2 JN |
4773 | /** |
4774 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4775 | * @connector: pointer to a registered drm_connector | |
4776 | * | |
4777 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4778 | * drm_debugfs_connector_remove(). | |
4779 | * | |
4780 | * Returns 0 on success, negative error codes on error. | |
4781 | */ | |
4782 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4783 | { | |
4784 | struct dentry *root = connector->debugfs_entry; | |
4785 | ||
4786 | /* The connector must have been registered beforehands. */ | |
4787 | if (!root) | |
4788 | return -ENODEV; | |
4789 | ||
4790 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4791 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4792 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4793 | connector, &i915_dpcd_fops); | |
4794 | ||
4795 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4796 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4797 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4798 | |
4799 | return 0; | |
4800 | } |