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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
6d2b8885 | 30 | #include <linux/list_sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
497666d8 DL |
38 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
39 | * allocated we need to hook into the minor for release. */ | |
40 | static int | |
41 | drm_add_fake_info_node(struct drm_minor *minor, | |
42 | struct dentry *ent, | |
43 | const void *key) | |
44 | { | |
45 | struct drm_info_node *node; | |
46 | ||
47 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
48 | if (node == NULL) { | |
49 | debugfs_remove(ent); | |
50 | return -ENOMEM; | |
51 | } | |
52 | ||
53 | node->minor = minor; | |
54 | node->dent = ent; | |
36cdd013 | 55 | node->info_ent = (void *)key; |
497666d8 DL |
56 | |
57 | mutex_lock(&minor->debugfs_lock); | |
58 | list_add(&node->list, &minor->debugfs_list); | |
59 | mutex_unlock(&minor->debugfs_lock); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
418e3cd8 CW |
64 | static __always_inline void seq_print_param(struct seq_file *m, |
65 | const char *name, | |
66 | const char *type, | |
67 | const void *x) | |
68 | { | |
69 | if (!__builtin_strcmp(type, "bool")) | |
70 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
71 | else if (!__builtin_strcmp(type, "int")) | |
72 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
73 | else if (!__builtin_strcmp(type, "unsigned int")) | |
74 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
75 | else | |
76 | BUILD_BUG(); | |
77 | } | |
78 | ||
70d39fe4 CW |
79 | static int i915_capabilities(struct seq_file *m, void *data) |
80 | { | |
36cdd013 DW |
81 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
82 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 83 | |
36cdd013 | 84 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 85 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 86 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 87 | |
79fc46df | 88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 89 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 90 | #undef PRINT_FLAG |
70d39fe4 | 91 | |
418e3cd8 CW |
92 | kernel_param_lock(THIS_MODULE); |
93 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
94 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
95 | #undef PRINT_PARAM | |
96 | kernel_param_unlock(THIS_MODULE); | |
97 | ||
70d39fe4 CW |
98 | return 0; |
99 | } | |
2017263e | 100 | |
a7363de7 | 101 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 102 | { |
573adb39 | 103 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
104 | } |
105 | ||
a7363de7 | 106 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
107 | { |
108 | return obj->pin_display ? 'p' : ' '; | |
109 | } | |
110 | ||
a7363de7 | 111 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 112 | { |
3e510a8e | 113 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 114 | default: |
be12a86b TU |
115 | case I915_TILING_NONE: return ' '; |
116 | case I915_TILING_X: return 'X'; | |
117 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 118 | } |
a6172a80 CW |
119 | } |
120 | ||
a7363de7 | 121 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 122 | { |
275f039d | 123 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
124 | } |
125 | ||
a7363de7 | 126 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 127 | { |
a4f5ea64 | 128 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
129 | } |
130 | ||
ca1543be TU |
131 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
132 | { | |
133 | u64 size = 0; | |
134 | struct i915_vma *vma; | |
135 | ||
1c7f4bca | 136 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 137 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
138 | size += vma->node.size; |
139 | } | |
140 | ||
141 | return size; | |
142 | } | |
143 | ||
37811fcc CW |
144 | static void |
145 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
146 | { | |
b4716185 | 147 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 148 | struct intel_engine_cs *engine; |
1d693bcc | 149 | struct i915_vma *vma; |
faf5bf0a | 150 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
151 | int pin_count = 0; |
152 | ||
188c1ab7 CW |
153 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
154 | ||
d07f0e59 | 155 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 156 | &obj->base, |
be12a86b | 157 | get_active_flag(obj), |
37811fcc CW |
158 | get_pin_flag(obj), |
159 | get_tiling_flag(obj), | |
1d693bcc | 160 | get_global_flag(obj), |
be12a86b | 161 | get_pin_mapped_flag(obj), |
a05a5862 | 162 | obj->base.size / 1024, |
37811fcc | 163 | obj->base.read_domains, |
d07f0e59 | 164 | obj->base.write_domain, |
36cdd013 | 165 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
166 | obj->mm.dirty ? " dirty" : "", |
167 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
168 | if (obj->base.name) |
169 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 170 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 171 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 172 | pin_count++; |
ba0635ff DC |
173 | } |
174 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
175 | if (obj->pin_display) |
176 | seq_printf(m, " (display)"); | |
1c7f4bca | 177 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
178 | if (!drm_mm_node_allocated(&vma->node)) |
179 | continue; | |
180 | ||
8d2fdc3f | 181 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 182 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 183 | vma->node.start, vma->node.size); |
21976853 CW |
184 | if (i915_vma_is_ggtt(vma)) { |
185 | switch (vma->ggtt_view.type) { | |
186 | case I915_GGTT_VIEW_NORMAL: | |
187 | seq_puts(m, ", normal"); | |
188 | break; | |
189 | ||
190 | case I915_GGTT_VIEW_PARTIAL: | |
191 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
192 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
193 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
194 | break; |
195 | ||
196 | case I915_GGTT_VIEW_ROTATED: | |
197 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
198 | vma->ggtt_view.rotated.plane[0].width, |
199 | vma->ggtt_view.rotated.plane[0].height, | |
200 | vma->ggtt_view.rotated.plane[0].stride, | |
201 | vma->ggtt_view.rotated.plane[0].offset, | |
202 | vma->ggtt_view.rotated.plane[1].width, | |
203 | vma->ggtt_view.rotated.plane[1].height, | |
204 | vma->ggtt_view.rotated.plane[1].stride, | |
205 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
206 | break; |
207 | ||
208 | default: | |
209 | MISSING_CASE(vma->ggtt_view.type); | |
210 | break; | |
211 | } | |
212 | } | |
49ef5294 CW |
213 | if (vma->fence) |
214 | seq_printf(m, " , fence: %d%s", | |
215 | vma->fence->id, | |
216 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 217 | seq_puts(m, ")"); |
1d693bcc | 218 | } |
c1ad11fc | 219 | if (obj->stolen) |
440fd528 | 220 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 221 | |
d07f0e59 | 222 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
223 | if (engine) |
224 | seq_printf(m, " (%s)", engine->name); | |
225 | ||
faf5bf0a CW |
226 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
227 | if (frontbuffer_bits) | |
228 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
229 | } |
230 | ||
6d2b8885 CW |
231 | static int obj_rank_by_stolen(void *priv, |
232 | struct list_head *A, struct list_head *B) | |
233 | { | |
234 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 236 | struct drm_i915_gem_object *b = |
b25cb2f8 | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 238 | |
2d05fa16 RV |
239 | if (a->stolen->start < b->stolen->start) |
240 | return -1; | |
241 | if (a->stolen->start > b->stolen->start) | |
242 | return 1; | |
243 | return 0; | |
6d2b8885 CW |
244 | } |
245 | ||
246 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
247 | { | |
36cdd013 DW |
248 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
249 | struct drm_device *dev = &dev_priv->drm; | |
6d2b8885 | 250 | struct drm_i915_gem_object *obj; |
c44ef60e | 251 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
252 | LIST_HEAD(stolen); |
253 | int count, ret; | |
254 | ||
255 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
256 | if (ret) | |
257 | return ret; | |
258 | ||
259 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 260 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6d2b8885 CW |
261 | if (obj->stolen == NULL) |
262 | continue; | |
263 | ||
b25cb2f8 | 264 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
265 | |
266 | total_obj_size += obj->base.size; | |
ca1543be | 267 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
268 | count++; |
269 | } | |
56cea323 | 270 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
6d2b8885 CW |
271 | if (obj->stolen == NULL) |
272 | continue; | |
273 | ||
b25cb2f8 | 274 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
275 | |
276 | total_obj_size += obj->base.size; | |
277 | count++; | |
278 | } | |
279 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
280 | seq_puts(m, "Stolen:\n"); | |
281 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 282 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
283 | seq_puts(m, " "); |
284 | describe_obj(m, obj); | |
285 | seq_putc(m, '\n'); | |
b25cb2f8 | 286 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
287 | } |
288 | mutex_unlock(&dev->struct_mutex); | |
289 | ||
c44ef60e | 290 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
291 | count, total_obj_size, total_gtt_size); |
292 | return 0; | |
293 | } | |
294 | ||
2db8e9d6 | 295 | struct file_stats { |
6313c204 | 296 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
297 | unsigned long count; |
298 | u64 total, unbound; | |
299 | u64 global, shared; | |
300 | u64 active, inactive; | |
2db8e9d6 CW |
301 | }; |
302 | ||
303 | static int per_file_stats(int id, void *ptr, void *data) | |
304 | { | |
305 | struct drm_i915_gem_object *obj = ptr; | |
306 | struct file_stats *stats = data; | |
6313c204 | 307 | struct i915_vma *vma; |
2db8e9d6 CW |
308 | |
309 | stats->count++; | |
310 | stats->total += obj->base.size; | |
15717de2 CW |
311 | if (!obj->bind_count) |
312 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
313 | if (obj->base.name || obj->base.dma_buf) |
314 | stats->shared += obj->base.size; | |
315 | ||
894eeecc CW |
316 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
317 | if (!drm_mm_node_allocated(&vma->node)) | |
318 | continue; | |
6313c204 | 319 | |
3272db53 | 320 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
321 | stats->global += vma->node.size; |
322 | } else { | |
323 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 324 | |
2bfa996e | 325 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 326 | continue; |
6313c204 | 327 | } |
894eeecc | 328 | |
b0decaf7 | 329 | if (i915_vma_is_active(vma)) |
894eeecc CW |
330 | stats->active += vma->node.size; |
331 | else | |
332 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
333 | } |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
b0da1b79 CW |
338 | #define print_file_stats(m, name, stats) do { \ |
339 | if (stats.count) \ | |
c44ef60e | 340 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
341 | name, \ |
342 | stats.count, \ | |
343 | stats.total, \ | |
344 | stats.active, \ | |
345 | stats.inactive, \ | |
346 | stats.global, \ | |
347 | stats.shared, \ | |
348 | stats.unbound); \ | |
349 | } while (0) | |
493018dc BV |
350 | |
351 | static void print_batch_pool_stats(struct seq_file *m, | |
352 | struct drm_i915_private *dev_priv) | |
353 | { | |
354 | struct drm_i915_gem_object *obj; | |
355 | struct file_stats stats; | |
e2f80391 | 356 | struct intel_engine_cs *engine; |
3b3f1650 | 357 | enum intel_engine_id id; |
b4ac5afc | 358 | int j; |
493018dc BV |
359 | |
360 | memset(&stats, 0, sizeof(stats)); | |
361 | ||
3b3f1650 | 362 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 363 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 364 | list_for_each_entry(obj, |
e2f80391 | 365 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
366 | batch_pool_link) |
367 | per_file_stats(0, obj, &stats); | |
368 | } | |
06fbca71 | 369 | } |
493018dc | 370 | |
b0da1b79 | 371 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
372 | } |
373 | ||
15da9565 CW |
374 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
375 | { | |
376 | struct i915_gem_context *ctx = ptr; | |
377 | int n; | |
378 | ||
379 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
380 | if (ctx->engine[n].state) | |
bf3783e5 | 381 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 382 | if (ctx->engine[n].ring) |
57e88531 | 383 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
384 | } |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static void print_context_stats(struct seq_file *m, | |
390 | struct drm_i915_private *dev_priv) | |
391 | { | |
36cdd013 | 392 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
393 | struct file_stats stats; |
394 | struct drm_file *file; | |
395 | ||
396 | memset(&stats, 0, sizeof(stats)); | |
397 | ||
36cdd013 | 398 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
399 | if (dev_priv->kernel_context) |
400 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
401 | ||
36cdd013 | 402 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
403 | struct drm_i915_file_private *fpriv = file->driver_priv; |
404 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
405 | } | |
36cdd013 | 406 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
407 | |
408 | print_file_stats(m, "[k]contexts", stats); | |
409 | } | |
410 | ||
36cdd013 | 411 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 412 | { |
36cdd013 DW |
413 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
414 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 415 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
416 | u32 count, mapped_count, purgeable_count, dpy_count; |
417 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 418 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 419 | struct drm_file *file; |
73aa808f CW |
420 | int ret; |
421 | ||
422 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
423 | if (ret) | |
424 | return ret; | |
425 | ||
3ef7f228 | 426 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
427 | dev_priv->mm.object_count, |
428 | dev_priv->mm.object_memory); | |
429 | ||
1544c42e CW |
430 | size = count = 0; |
431 | mapped_size = mapped_count = 0; | |
432 | purgeable_size = purgeable_count = 0; | |
56cea323 | 433 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
434 | size += obj->base.size; |
435 | ++count; | |
436 | ||
a4f5ea64 | 437 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
438 | purgeable_size += obj->base.size; |
439 | ++purgeable_count; | |
440 | } | |
441 | ||
a4f5ea64 | 442 | if (obj->mm.mapping) { |
2bd160a1 CW |
443 | mapped_count++; |
444 | mapped_size += obj->base.size; | |
be19b10d | 445 | } |
b7abb714 | 446 | } |
c44ef60e | 447 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 448 | |
2bd160a1 | 449 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 450 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
451 | size += obj->base.size; |
452 | ++count; | |
453 | ||
30154650 | 454 | if (obj->pin_display) { |
2bd160a1 CW |
455 | dpy_size += obj->base.size; |
456 | ++dpy_count; | |
6299f992 | 457 | } |
2bd160a1 | 458 | |
a4f5ea64 | 459 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
460 | purgeable_size += obj->base.size; |
461 | ++purgeable_count; | |
462 | } | |
2bd160a1 | 463 | |
a4f5ea64 | 464 | if (obj->mm.mapping) { |
2bd160a1 CW |
465 | mapped_count++; |
466 | mapped_size += obj->base.size; | |
be19b10d | 467 | } |
6299f992 | 468 | } |
2bd160a1 CW |
469 | seq_printf(m, "%u bound objects, %llu bytes\n", |
470 | count, size); | |
c44ef60e | 471 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 472 | purgeable_count, purgeable_size); |
2bd160a1 CW |
473 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
474 | mapped_count, mapped_size); | |
475 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
476 | dpy_count, dpy_size); | |
6299f992 | 477 | |
c44ef60e | 478 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 479 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 480 | |
493018dc BV |
481 | seq_putc(m, '\n'); |
482 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
483 | mutex_unlock(&dev->struct_mutex); |
484 | ||
485 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 486 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
487 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
488 | struct file_stats stats; | |
c84455b4 CW |
489 | struct drm_i915_file_private *file_priv = file->driver_priv; |
490 | struct drm_i915_gem_request *request; | |
3ec2f427 | 491 | struct task_struct *task; |
2db8e9d6 CW |
492 | |
493 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 494 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 495 | spin_lock(&file->table_lock); |
2db8e9d6 | 496 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 497 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
498 | /* |
499 | * Although we have a valid reference on file->pid, that does | |
500 | * not guarantee that the task_struct who called get_pid() is | |
501 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
502 | * Therefore, we need to protect this ->comm access using RCU. | |
503 | */ | |
c84455b4 CW |
504 | mutex_lock(&dev->struct_mutex); |
505 | request = list_first_entry_or_null(&file_priv->mm.request_list, | |
506 | struct drm_i915_gem_request, | |
507 | client_list); | |
3ec2f427 | 508 | rcu_read_lock(); |
c84455b4 CW |
509 | task = pid_task(request && request->ctx->pid ? |
510 | request->ctx->pid : file->pid, | |
511 | PIDTYPE_PID); | |
493018dc | 512 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 513 | rcu_read_unlock(); |
c84455b4 | 514 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 515 | } |
1d2ac403 | 516 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
517 | |
518 | return 0; | |
519 | } | |
520 | ||
aee56cff | 521 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 522 | { |
9f25d007 | 523 | struct drm_info_node *node = m->private; |
36cdd013 DW |
524 | struct drm_i915_private *dev_priv = node_to_i915(node); |
525 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 526 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 527 | struct drm_i915_gem_object *obj; |
c44ef60e | 528 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
529 | int count, ret; |
530 | ||
531 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
532 | if (ret) | |
533 | return ret; | |
534 | ||
535 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 536 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 537 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
538 | continue; |
539 | ||
267f0c90 | 540 | seq_puts(m, " "); |
08c18323 | 541 | describe_obj(m, obj); |
267f0c90 | 542 | seq_putc(m, '\n'); |
08c18323 | 543 | total_obj_size += obj->base.size; |
ca1543be | 544 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
545 | count++; |
546 | } | |
547 | ||
548 | mutex_unlock(&dev->struct_mutex); | |
549 | ||
c44ef60e | 550 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
551 | count, total_obj_size, total_gtt_size); |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
4e5359cd SF |
556 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
557 | { | |
36cdd013 DW |
558 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
559 | struct drm_device *dev = &dev_priv->drm; | |
4e5359cd | 560 | struct intel_crtc *crtc; |
8a270ebf DV |
561 | int ret; |
562 | ||
563 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
564 | if (ret) | |
565 | return ret; | |
4e5359cd | 566 | |
d3fcc808 | 567 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
568 | const char pipe = pipe_name(crtc->pipe); |
569 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 570 | struct intel_flip_work *work; |
4e5359cd | 571 | |
5e2d7afc | 572 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
573 | work = crtc->flip_work; |
574 | if (work == NULL) { | |
9db4a9c7 | 575 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
576 | pipe, plane); |
577 | } else { | |
5a21b665 DV |
578 | u32 pending; |
579 | u32 addr; | |
580 | ||
581 | pending = atomic_read(&work->pending); | |
582 | if (pending) { | |
583 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
584 | pipe, plane); | |
585 | } else { | |
586 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
587 | pipe, plane); | |
588 | } | |
589 | if (work->flip_queued_req) { | |
24327f83 | 590 | struct intel_engine_cs *engine = work->flip_queued_req->engine; |
5a21b665 | 591 | |
312c3c47 | 592 | seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", |
5a21b665 | 593 | engine->name, |
24327f83 | 594 | work->flip_queued_req->global_seqno, |
312c3c47 | 595 | intel_engine_last_submit(engine), |
1b7744e7 | 596 | intel_engine_get_seqno(engine), |
f69a02c9 | 597 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
598 | } else |
599 | seq_printf(m, "Flip not associated with any ring\n"); | |
600 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
601 | work->flip_queued_vblank, | |
602 | work->flip_ready_vblank, | |
603 | intel_crtc_get_vblank_counter(crtc)); | |
604 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
605 | ||
36cdd013 | 606 | if (INTEL_GEN(dev_priv) >= 4) |
5a21b665 DV |
607 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
608 | else | |
609 | addr = I915_READ(DSPADDR(crtc->plane)); | |
610 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
611 | ||
612 | if (work->pending_flip_obj) { | |
613 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
614 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
615 | } |
616 | } | |
5e2d7afc | 617 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
618 | } |
619 | ||
8a270ebf DV |
620 | mutex_unlock(&dev->struct_mutex); |
621 | ||
4e5359cd SF |
622 | return 0; |
623 | } | |
624 | ||
493018dc BV |
625 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
626 | { | |
36cdd013 DW |
627 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
628 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 629 | struct drm_i915_gem_object *obj; |
e2f80391 | 630 | struct intel_engine_cs *engine; |
3b3f1650 | 631 | enum intel_engine_id id; |
8d9d5744 | 632 | int total = 0; |
b4ac5afc | 633 | int ret, j; |
493018dc BV |
634 | |
635 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
636 | if (ret) | |
637 | return ret; | |
638 | ||
3b3f1650 | 639 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 640 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
641 | int count; |
642 | ||
643 | count = 0; | |
644 | list_for_each_entry(obj, | |
e2f80391 | 645 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
646 | batch_pool_link) |
647 | count++; | |
648 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 649 | engine->name, j, count); |
8d9d5744 CW |
650 | |
651 | list_for_each_entry(obj, | |
e2f80391 | 652 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
653 | batch_pool_link) { |
654 | seq_puts(m, " "); | |
655 | describe_obj(m, obj); | |
656 | seq_putc(m, '\n'); | |
657 | } | |
658 | ||
659 | total += count; | |
06fbca71 | 660 | } |
493018dc BV |
661 | } |
662 | ||
8d9d5744 | 663 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
664 | |
665 | mutex_unlock(&dev->struct_mutex); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
1b36595f CW |
670 | static void print_request(struct seq_file *m, |
671 | struct drm_i915_gem_request *rq, | |
672 | const char *prefix) | |
673 | { | |
20311bd3 | 674 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 675 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 676 | rq->priotree.priority, |
1b36595f | 677 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 678 | rq->timeline->common->name); |
1b36595f CW |
679 | } |
680 | ||
2017263e BG |
681 | static int i915_gem_request_info(struct seq_file *m, void *data) |
682 | { | |
36cdd013 DW |
683 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
684 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 685 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
686 | struct intel_engine_cs *engine; |
687 | enum intel_engine_id id; | |
b4ac5afc | 688 | int ret, any; |
de227ef0 CW |
689 | |
690 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
691 | if (ret) | |
692 | return ret; | |
2017263e | 693 | |
2d1070b2 | 694 | any = 0; |
3b3f1650 | 695 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
696 | int count; |
697 | ||
698 | count = 0; | |
73cb9701 | 699 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
700 | count++; |
701 | if (count == 0) | |
a2c7f6fd CW |
702 | continue; |
703 | ||
e2f80391 | 704 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 705 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 706 | print_request(m, req, " "); |
2d1070b2 CW |
707 | |
708 | any++; | |
2017263e | 709 | } |
de227ef0 CW |
710 | mutex_unlock(&dev->struct_mutex); |
711 | ||
2d1070b2 | 712 | if (any == 0) |
267f0c90 | 713 | seq_puts(m, "No requests\n"); |
c2c347a9 | 714 | |
2017263e BG |
715 | return 0; |
716 | } | |
717 | ||
b2223497 | 718 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 719 | struct intel_engine_cs *engine) |
b2223497 | 720 | { |
688e6c72 CW |
721 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
722 | struct rb_node *rb; | |
723 | ||
12471ba8 | 724 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 725 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 726 | |
f6168e33 | 727 | spin_lock_irq(&b->lock); |
688e6c72 | 728 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 729 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
730 | |
731 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
732 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
733 | } | |
f6168e33 | 734 | spin_unlock_irq(&b->lock); |
b2223497 CW |
735 | } |
736 | ||
2017263e BG |
737 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
738 | { | |
36cdd013 | 739 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 740 | struct intel_engine_cs *engine; |
3b3f1650 | 741 | enum intel_engine_id id; |
2017263e | 742 | |
3b3f1650 | 743 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 744 | i915_ring_seqno_info(m, engine); |
de227ef0 | 745 | |
2017263e BG |
746 | return 0; |
747 | } | |
748 | ||
749 | ||
750 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
751 | { | |
36cdd013 | 752 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 753 | struct intel_engine_cs *engine; |
3b3f1650 | 754 | enum intel_engine_id id; |
4bb05040 | 755 | int i, pipe; |
de227ef0 | 756 | |
c8c8fb33 | 757 | intel_runtime_pm_get(dev_priv); |
2017263e | 758 | |
36cdd013 | 759 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
760 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
761 | I915_READ(GEN8_MASTER_IRQ)); | |
762 | ||
763 | seq_printf(m, "Display IER:\t%08x\n", | |
764 | I915_READ(VLV_IER)); | |
765 | seq_printf(m, "Display IIR:\t%08x\n", | |
766 | I915_READ(VLV_IIR)); | |
767 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
768 | I915_READ(VLV_IIR_RW)); | |
769 | seq_printf(m, "Display IMR:\t%08x\n", | |
770 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
771 | for_each_pipe(dev_priv, pipe) { |
772 | enum intel_display_power_domain power_domain; | |
773 | ||
774 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
775 | if (!intel_display_power_get_if_enabled(dev_priv, | |
776 | power_domain)) { | |
777 | seq_printf(m, "Pipe %c power disabled\n", | |
778 | pipe_name(pipe)); | |
779 | continue; | |
780 | } | |
781 | ||
74e1ca8c VS |
782 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
783 | pipe_name(pipe), | |
784 | I915_READ(PIPESTAT(pipe))); | |
785 | ||
9c870d03 CW |
786 | intel_display_power_put(dev_priv, power_domain); |
787 | } | |
788 | ||
789 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
790 | seq_printf(m, "Port hotplug:\t%08x\n", |
791 | I915_READ(PORT_HOTPLUG_EN)); | |
792 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
793 | I915_READ(VLV_DPFLIPSTAT)); | |
794 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
795 | I915_READ(DPINVGTT)); | |
9c870d03 | 796 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
797 | |
798 | for (i = 0; i < 4; i++) { | |
799 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
800 | i, I915_READ(GEN8_GT_IMR(i))); | |
801 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
802 | i, I915_READ(GEN8_GT_IIR(i))); | |
803 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
804 | i, I915_READ(GEN8_GT_IER(i))); | |
805 | } | |
806 | ||
807 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
808 | I915_READ(GEN8_PCU_IMR)); | |
809 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
810 | I915_READ(GEN8_PCU_IIR)); | |
811 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
812 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 813 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
814 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
815 | I915_READ(GEN8_MASTER_IRQ)); | |
816 | ||
817 | for (i = 0; i < 4; i++) { | |
818 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
819 | i, I915_READ(GEN8_GT_IMR(i))); | |
820 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
821 | i, I915_READ(GEN8_GT_IIR(i))); | |
822 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
823 | i, I915_READ(GEN8_GT_IER(i))); | |
824 | } | |
825 | ||
055e393f | 826 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
827 | enum intel_display_power_domain power_domain; |
828 | ||
829 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
830 | if (!intel_display_power_get_if_enabled(dev_priv, | |
831 | power_domain)) { | |
22c59960 PZ |
832 | seq_printf(m, "Pipe %c power disabled\n", |
833 | pipe_name(pipe)); | |
834 | continue; | |
835 | } | |
a123f157 | 836 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
837 | pipe_name(pipe), |
838 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 839 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
840 | pipe_name(pipe), |
841 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 842 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
843 | pipe_name(pipe), |
844 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
845 | |
846 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
847 | } |
848 | ||
849 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
850 | I915_READ(GEN8_DE_PORT_IMR)); | |
851 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
852 | I915_READ(GEN8_DE_PORT_IIR)); | |
853 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
854 | I915_READ(GEN8_DE_PORT_IER)); | |
855 | ||
856 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
857 | I915_READ(GEN8_DE_MISC_IMR)); | |
858 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
859 | I915_READ(GEN8_DE_MISC_IIR)); | |
860 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
861 | I915_READ(GEN8_DE_MISC_IER)); | |
862 | ||
863 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
864 | I915_READ(GEN8_PCU_IMR)); | |
865 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
866 | I915_READ(GEN8_PCU_IIR)); | |
867 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
868 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 869 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
870 | seq_printf(m, "Display IER:\t%08x\n", |
871 | I915_READ(VLV_IER)); | |
872 | seq_printf(m, "Display IIR:\t%08x\n", | |
873 | I915_READ(VLV_IIR)); | |
874 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
875 | I915_READ(VLV_IIR_RW)); | |
876 | seq_printf(m, "Display IMR:\t%08x\n", | |
877 | I915_READ(VLV_IMR)); | |
4f4631af CW |
878 | for_each_pipe(dev_priv, pipe) { |
879 | enum intel_display_power_domain power_domain; | |
880 | ||
881 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
882 | if (!intel_display_power_get_if_enabled(dev_priv, | |
883 | power_domain)) { | |
884 | seq_printf(m, "Pipe %c power disabled\n", | |
885 | pipe_name(pipe)); | |
886 | continue; | |
887 | } | |
888 | ||
7e231dbe JB |
889 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
890 | pipe_name(pipe), | |
891 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
892 | intel_display_power_put(dev_priv, power_domain); |
893 | } | |
7e231dbe JB |
894 | |
895 | seq_printf(m, "Master IER:\t%08x\n", | |
896 | I915_READ(VLV_MASTER_IER)); | |
897 | ||
898 | seq_printf(m, "Render IER:\t%08x\n", | |
899 | I915_READ(GTIER)); | |
900 | seq_printf(m, "Render IIR:\t%08x\n", | |
901 | I915_READ(GTIIR)); | |
902 | seq_printf(m, "Render IMR:\t%08x\n", | |
903 | I915_READ(GTIMR)); | |
904 | ||
905 | seq_printf(m, "PM IER:\t\t%08x\n", | |
906 | I915_READ(GEN6_PMIER)); | |
907 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
908 | I915_READ(GEN6_PMIIR)); | |
909 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
910 | I915_READ(GEN6_PMIMR)); | |
911 | ||
912 | seq_printf(m, "Port hotplug:\t%08x\n", | |
913 | I915_READ(PORT_HOTPLUG_EN)); | |
914 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
915 | I915_READ(VLV_DPFLIPSTAT)); | |
916 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
917 | I915_READ(DPINVGTT)); | |
918 | ||
36cdd013 | 919 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
920 | seq_printf(m, "Interrupt enable: %08x\n", |
921 | I915_READ(IER)); | |
922 | seq_printf(m, "Interrupt identity: %08x\n", | |
923 | I915_READ(IIR)); | |
924 | seq_printf(m, "Interrupt mask: %08x\n", | |
925 | I915_READ(IMR)); | |
055e393f | 926 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
927 | seq_printf(m, "Pipe %c stat: %08x\n", |
928 | pipe_name(pipe), | |
929 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
930 | } else { |
931 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
932 | I915_READ(DEIER)); | |
933 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
934 | I915_READ(DEIIR)); | |
935 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
936 | I915_READ(DEIMR)); | |
937 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
938 | I915_READ(SDEIER)); | |
939 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
940 | I915_READ(SDEIIR)); | |
941 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
942 | I915_READ(SDEIMR)); | |
943 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
944 | I915_READ(GTIER)); | |
945 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
946 | I915_READ(GTIIR)); | |
947 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
948 | I915_READ(GTIMR)); | |
949 | } | |
3b3f1650 | 950 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 951 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
952 | seq_printf(m, |
953 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 954 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 955 | } |
e2f80391 | 956 | i915_ring_seqno_info(m, engine); |
9862e600 | 957 | } |
c8c8fb33 | 958 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 959 | |
2017263e BG |
960 | return 0; |
961 | } | |
962 | ||
a6172a80 CW |
963 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
964 | { | |
36cdd013 DW |
965 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
966 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
967 | int i, ret; |
968 | ||
969 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
970 | if (ret) | |
971 | return ret; | |
a6172a80 | 972 | |
a6172a80 CW |
973 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
974 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 975 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 976 | |
6c085a72 CW |
977 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
978 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 979 | if (!vma) |
267f0c90 | 980 | seq_puts(m, "unused"); |
c2c347a9 | 981 | else |
49ef5294 | 982 | describe_obj(m, vma->obj); |
267f0c90 | 983 | seq_putc(m, '\n'); |
a6172a80 CW |
984 | } |
985 | ||
05394f39 | 986 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
987 | return 0; |
988 | } | |
989 | ||
98a2f411 | 990 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
991 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
992 | size_t count, loff_t *pos) | |
d5442303 | 993 | { |
5a4c6f1b CW |
994 | struct i915_gpu_state *error = file->private_data; |
995 | struct drm_i915_error_state_buf str; | |
996 | ssize_t ret; | |
997 | loff_t tmp; | |
d5442303 | 998 | |
5a4c6f1b CW |
999 | if (!error) |
1000 | return 0; | |
d5442303 | 1001 | |
5a4c6f1b CW |
1002 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
1003 | if (ret) | |
1004 | return ret; | |
d5442303 | 1005 | |
5a4c6f1b CW |
1006 | ret = i915_error_state_to_str(&str, error); |
1007 | if (ret) | |
1008 | goto out; | |
d5442303 | 1009 | |
5a4c6f1b CW |
1010 | tmp = 0; |
1011 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
1012 | if (ret < 0) | |
1013 | goto out; | |
d5442303 | 1014 | |
5a4c6f1b CW |
1015 | *pos = str.start + ret; |
1016 | out: | |
1017 | i915_error_state_buf_release(&str); | |
1018 | return ret; | |
1019 | } | |
edc3d884 | 1020 | |
5a4c6f1b CW |
1021 | static int gpu_state_release(struct inode *inode, struct file *file) |
1022 | { | |
1023 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1024 | return 0; |
d5442303 DV |
1025 | } |
1026 | ||
5a4c6f1b | 1027 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1028 | { |
5a4c6f1b | 1029 | struct i915_gpu_state *gpu; |
d5442303 | 1030 | |
5a4c6f1b CW |
1031 | gpu = i915_capture_gpu_state(inode->i_private); |
1032 | if (!gpu) | |
1033 | return -ENOMEM; | |
d5442303 | 1034 | |
5a4c6f1b | 1035 | file->private_data = gpu; |
edc3d884 MK |
1036 | return 0; |
1037 | } | |
1038 | ||
5a4c6f1b CW |
1039 | static const struct file_operations i915_gpu_info_fops = { |
1040 | .owner = THIS_MODULE, | |
1041 | .open = i915_gpu_info_open, | |
1042 | .read = gpu_state_read, | |
1043 | .llseek = default_llseek, | |
1044 | .release = gpu_state_release, | |
1045 | }; | |
1046 | ||
1047 | static ssize_t | |
1048 | i915_error_state_write(struct file *filp, | |
1049 | const char __user *ubuf, | |
1050 | size_t cnt, | |
1051 | loff_t *ppos) | |
4dc955f7 | 1052 | { |
5a4c6f1b | 1053 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1054 | |
5a4c6f1b CW |
1055 | if (!error) |
1056 | return 0; | |
edc3d884 | 1057 | |
5a4c6f1b CW |
1058 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1059 | i915_reset_error_state(error->i915); | |
edc3d884 | 1060 | |
5a4c6f1b CW |
1061 | return cnt; |
1062 | } | |
edc3d884 | 1063 | |
5a4c6f1b CW |
1064 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1065 | { | |
1066 | file->private_data = i915_first_error_state(inode->i_private); | |
1067 | return 0; | |
d5442303 DV |
1068 | } |
1069 | ||
1070 | static const struct file_operations i915_error_state_fops = { | |
1071 | .owner = THIS_MODULE, | |
1072 | .open = i915_error_state_open, | |
5a4c6f1b | 1073 | .read = gpu_state_read, |
d5442303 DV |
1074 | .write = i915_error_state_write, |
1075 | .llseek = default_llseek, | |
5a4c6f1b | 1076 | .release = gpu_state_release, |
d5442303 | 1077 | }; |
98a2f411 CW |
1078 | #endif |
1079 | ||
647416f9 KC |
1080 | static int |
1081 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1082 | { |
36cdd013 | 1083 | struct drm_i915_private *dev_priv = data; |
40633219 | 1084 | |
4c266edb | 1085 | *val = 1 + atomic_read(&dev_priv->gt.global_timeline.seqno); |
647416f9 | 1086 | return 0; |
40633219 MK |
1087 | } |
1088 | ||
647416f9 KC |
1089 | static int |
1090 | i915_next_seqno_set(void *data, u64 val) | |
1091 | { | |
36cdd013 DW |
1092 | struct drm_i915_private *dev_priv = data; |
1093 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1094 | int ret; |
1095 | ||
40633219 MK |
1096 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1097 | if (ret) | |
1098 | return ret; | |
1099 | ||
73cb9701 | 1100 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1101 | mutex_unlock(&dev->struct_mutex); |
1102 | ||
647416f9 | 1103 | return ret; |
40633219 MK |
1104 | } |
1105 | ||
647416f9 KC |
1106 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1107 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1108 | "0x%llx\n"); |
40633219 | 1109 | |
adb4bd12 | 1110 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1111 | { |
36cdd013 | 1112 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1113 | int ret = 0; |
1114 | ||
1115 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1116 | |
36cdd013 | 1117 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1118 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1119 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1120 | ||
1121 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1122 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1123 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1124 | MEMSTAT_VID_SHIFT); | |
1125 | seq_printf(m, "Current P-state: %d\n", | |
1126 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1127 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1128 | u32 freq_sts; |
1129 | ||
1130 | mutex_lock(&dev_priv->rps.hw_lock); | |
1131 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1132 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1133 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1134 | ||
1135 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1136 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1137 | ||
1138 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1139 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1140 | ||
1141 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1142 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1143 | ||
1144 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1145 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1146 | ||
1147 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1148 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1149 | ||
1150 | seq_printf(m, | |
1151 | "efficient (RPe) frequency: %d MHz\n", | |
1152 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1153 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1154 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1155 | u32 rp_state_limits; |
1156 | u32 gt_perf_status; | |
1157 | u32 rp_state_cap; | |
0d8f9491 | 1158 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1159 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1160 | u32 rpupei, rpcurup, rpprevup; |
1161 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1162 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1163 | int max_freq; |
1164 | ||
35040562 | 1165 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1166 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1167 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1168 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1169 | } else { | |
1170 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1171 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1172 | } | |
1173 | ||
3b8d8d91 | 1174 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1175 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1176 | |
8e8c06cd | 1177 | reqf = I915_READ(GEN6_RPNSWREQ); |
36cdd013 | 1178 | if (IS_GEN9(dev_priv)) |
60260a5b AG |
1179 | reqf >>= 23; |
1180 | else { | |
1181 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1182 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1183 | reqf >>= 24; |
1184 | else | |
1185 | reqf >>= 25; | |
1186 | } | |
7c59a9c1 | 1187 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1188 | |
0d8f9491 CW |
1189 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1190 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1191 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1192 | ||
ccab5c82 | 1193 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1194 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1195 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1196 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1197 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1198 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1199 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
36cdd013 | 1200 | if (IS_GEN9(dev_priv)) |
60260a5b | 1201 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1202 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1203 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1204 | else | |
1205 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1206 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1207 | |
59bad947 | 1208 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1209 | |
36cdd013 | 1210 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1211 | pm_ier = I915_READ(GEN6_PMIER); |
1212 | pm_imr = I915_READ(GEN6_PMIMR); | |
1213 | pm_isr = I915_READ(GEN6_PMISR); | |
1214 | pm_iir = I915_READ(GEN6_PMIIR); | |
1215 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1216 | } else { | |
1217 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1218 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1219 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1220 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1221 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1222 | } | |
0d8f9491 | 1223 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1224 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1225 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1226 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1227 | seq_printf(m, "Render p-state ratio: %d\n", |
36cdd013 | 1228 | (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1229 | seq_printf(m, "Render p-state VID: %d\n", |
1230 | gt_perf_status & 0xff); | |
1231 | seq_printf(m, "Render p-state limit: %d\n", | |
1232 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1233 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1234 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1235 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1236 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1237 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1238 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1239 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1240 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1241 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1242 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1243 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1244 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1245 | seq_printf(m, "Up threshold: %d%%\n", |
1246 | dev_priv->rps.up_threshold); | |
1247 | ||
d6cda9c7 AG |
1248 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1249 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1250 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1251 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1252 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1253 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1254 | seq_printf(m, "Down threshold: %d%%\n", |
1255 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1256 | |
cc3f90f0 | 1257 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1258 | rp_state_cap >> 16) & 0xff; |
b976dc53 | 1259 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1260 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1261 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1262 | |
1263 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
b976dc53 | 1264 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1265 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1266 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1267 | |
cc3f90f0 | 1268 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1269 | rp_state_cap >> 0) & 0xff; |
b976dc53 | 1270 | max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1271 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1272 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1273 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1274 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1275 | |
d86ed34a CW |
1276 | seq_printf(m, "Current freq: %d MHz\n", |
1277 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1278 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1279 | seq_printf(m, "Idle freq: %d MHz\n", |
1280 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1281 | seq_printf(m, "Min freq: %d MHz\n", |
1282 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1283 | seq_printf(m, "Boost freq: %d MHz\n", |
1284 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1285 | seq_printf(m, "Max freq: %d MHz\n", |
1286 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1287 | seq_printf(m, | |
1288 | "efficient (RPe) frequency: %d MHz\n", | |
1289 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1290 | } else { |
267f0c90 | 1291 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1292 | } |
f97108d1 | 1293 | |
49cd97a3 | 1294 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1295 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1296 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1297 | ||
c8c8fb33 PZ |
1298 | intel_runtime_pm_put(dev_priv); |
1299 | return ret; | |
f97108d1 JB |
1300 | } |
1301 | ||
d636951e BW |
1302 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1303 | struct seq_file *m, | |
1304 | struct intel_instdone *instdone) | |
1305 | { | |
f9e61372 BW |
1306 | int slice; |
1307 | int subslice; | |
1308 | ||
d636951e BW |
1309 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1310 | instdone->instdone); | |
1311 | ||
1312 | if (INTEL_GEN(dev_priv) <= 3) | |
1313 | return; | |
1314 | ||
1315 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1316 | instdone->slice_common); | |
1317 | ||
1318 | if (INTEL_GEN(dev_priv) <= 6) | |
1319 | return; | |
1320 | ||
f9e61372 BW |
1321 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1322 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1323 | slice, subslice, instdone->sampler[slice][subslice]); | |
1324 | ||
1325 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1326 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1327 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1328 | } |
1329 | ||
f654449a CW |
1330 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1331 | { | |
36cdd013 | 1332 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1333 | struct intel_engine_cs *engine; |
666796da TU |
1334 | u64 acthd[I915_NUM_ENGINES]; |
1335 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1336 | struct intel_instdone instdone; |
c3232b18 | 1337 | enum intel_engine_id id; |
f654449a | 1338 | |
8af29b0c CW |
1339 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
1340 | seq_printf(m, "Wedged\n"); | |
1341 | if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) | |
1342 | seq_printf(m, "Reset in progress\n"); | |
1343 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) | |
1344 | seq_printf(m, "Waiter holding struct mutex\n"); | |
1345 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) | |
1346 | seq_printf(m, "struct_mutex blocked for reset\n"); | |
1347 | ||
f654449a CW |
1348 | if (!i915.enable_hangcheck) { |
1349 | seq_printf(m, "Hangcheck disabled\n"); | |
1350 | return 0; | |
1351 | } | |
1352 | ||
ebbc7546 MK |
1353 | intel_runtime_pm_get(dev_priv); |
1354 | ||
3b3f1650 | 1355 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1356 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1357 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1358 | } |
1359 | ||
3b3f1650 | 1360 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1361 | |
ebbc7546 MK |
1362 | intel_runtime_pm_put(dev_priv); |
1363 | ||
f654449a CW |
1364 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1365 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1366 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1367 | jiffies)); | |
1368 | } else | |
1369 | seq_printf(m, "Hangcheck inactive\n"); | |
1370 | ||
3b3f1650 | 1371 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1372 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1373 | struct rb_node *rb; | |
1374 | ||
e2f80391 | 1375 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d | 1376 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
cb399eab CW |
1377 | engine->hangcheck.seqno, seqno[id], |
1378 | intel_engine_last_submit(engine)); | |
3fe3b030 | 1379 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1380 | yesno(intel_engine_has_waiter(engine)), |
1381 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1382 | &dev_priv->gpu_error.missed_irq_rings)), |
1383 | yesno(engine->hangcheck.stalled)); | |
1384 | ||
f6168e33 | 1385 | spin_lock_irq(&b->lock); |
33f53719 | 1386 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1387 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1388 | |
1389 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1390 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1391 | } | |
f6168e33 | 1392 | spin_unlock_irq(&b->lock); |
33f53719 | 1393 | |
f654449a | 1394 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1395 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1396 | (long long)acthd[id]); |
3fe3b030 MK |
1397 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1398 | hangcheck_action_to_str(engine->hangcheck.action), | |
1399 | engine->hangcheck.action, | |
1400 | jiffies_to_msecs(jiffies - | |
1401 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1402 | |
e2f80391 | 1403 | if (engine->id == RCS) { |
d636951e | 1404 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1405 | |
d636951e | 1406 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1407 | |
d636951e | 1408 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1409 | |
d636951e BW |
1410 | i915_instdone_info(dev_priv, m, |
1411 | &engine->hangcheck.instdone); | |
61642ff0 | 1412 | } |
f654449a CW |
1413 | } |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
4d85529d | 1418 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1419 | { |
36cdd013 | 1420 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1421 | u32 rgvmodectl, rstdbyctl; |
1422 | u16 crstandvid; | |
616fdb5a | 1423 | |
c8c8fb33 | 1424 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1425 | |
1426 | rgvmodectl = I915_READ(MEMMODECTL); | |
1427 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1428 | crstandvid = I915_READ16(CRSTANDVID); | |
1429 | ||
c8c8fb33 | 1430 | intel_runtime_pm_put(dev_priv); |
f97108d1 | 1431 | |
742f491d | 1432 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1433 | seq_printf(m, "Boost freq: %d\n", |
1434 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1435 | MEMMODE_BOOST_FREQ_SHIFT); | |
1436 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1437 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1438 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1439 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1440 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1441 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1442 | seq_printf(m, "Starting frequency: P%d\n", |
1443 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1444 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1445 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1446 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1447 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1448 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1449 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1450 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1451 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1452 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1453 | case RSX_STATUS_ON: | |
267f0c90 | 1454 | seq_puts(m, "on\n"); |
88271da3 JB |
1455 | break; |
1456 | case RSX_STATUS_RC1: | |
267f0c90 | 1457 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1458 | break; |
1459 | case RSX_STATUS_RC1E: | |
267f0c90 | 1460 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1461 | break; |
1462 | case RSX_STATUS_RS1: | |
267f0c90 | 1463 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1464 | break; |
1465 | case RSX_STATUS_RS2: | |
267f0c90 | 1466 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1467 | break; |
1468 | case RSX_STATUS_RS3: | |
267f0c90 | 1469 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1470 | break; |
1471 | default: | |
267f0c90 | 1472 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1473 | break; |
1474 | } | |
f97108d1 JB |
1475 | |
1476 | return 0; | |
1477 | } | |
1478 | ||
f65367b5 | 1479 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1480 | { |
36cdd013 | 1481 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b2cff0db | 1482 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1483 | |
1484 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1485 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1486 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1487 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1488 | fw_domain->wake_count); |
1489 | } | |
1490 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1491 | |
b2cff0db CW |
1492 | return 0; |
1493 | } | |
1494 | ||
1495 | static int vlv_drpc_info(struct seq_file *m) | |
1496 | { | |
36cdd013 | 1497 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1498 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1499 | |
d46c0517 ID |
1500 | intel_runtime_pm_get(dev_priv); |
1501 | ||
6b312cd3 | 1502 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1503 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1504 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1505 | ||
d46c0517 ID |
1506 | intel_runtime_pm_put(dev_priv); |
1507 | ||
669ab5aa D |
1508 | seq_printf(m, "Video Turbo Mode: %s\n", |
1509 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1510 | seq_printf(m, "Turbo enabled: %s\n", | |
1511 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1512 | seq_printf(m, "HW control enabled: %s\n", | |
1513 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1514 | seq_printf(m, "SW control enabled: %s\n", | |
1515 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1516 | GEN6_RP_MEDIA_SW_MODE)); | |
1517 | seq_printf(m, "RC6 Enabled: %s\n", | |
1518 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1519 | GEN6_RC_CTL_EI_MODE(1)))); | |
1520 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1521 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1522 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1523 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1524 | |
9cc19be5 ID |
1525 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1526 | I915_READ(VLV_GT_RENDER_RC6)); | |
1527 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1528 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1529 | ||
f65367b5 | 1530 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1531 | } |
1532 | ||
4d85529d BW |
1533 | static int gen6_drpc_info(struct seq_file *m) |
1534 | { | |
36cdd013 DW |
1535 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1536 | struct drm_device *dev = &dev_priv->drm; | |
ecd8faea | 1537 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1538 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1539 | unsigned forcewake_count; |
aee56cff | 1540 | int count = 0, ret; |
4d85529d BW |
1541 | |
1542 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1543 | if (ret) | |
1544 | return ret; | |
c8c8fb33 | 1545 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1546 | |
907b28c5 | 1547 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1548 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1549 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1550 | |
1551 | if (forcewake_count) { | |
267f0c90 DL |
1552 | seq_puts(m, "RC information inaccurate because somebody " |
1553 | "holds a forcewake reference \n"); | |
4d85529d BW |
1554 | } else { |
1555 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1556 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1557 | udelay(10); | |
1558 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1559 | } | |
1560 | ||
75aa3f63 | 1561 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1562 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1563 | |
1564 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1565 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1566 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1567 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1568 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1569 | } | |
4d85529d | 1570 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1571 | mutex_lock(&dev_priv->rps.hw_lock); |
1572 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1573 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1574 | |
c8c8fb33 PZ |
1575 | intel_runtime_pm_put(dev_priv); |
1576 | ||
4d85529d BW |
1577 | seq_printf(m, "Video Turbo Mode: %s\n", |
1578 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1579 | seq_printf(m, "HW control enabled: %s\n", | |
1580 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1581 | seq_printf(m, "SW control enabled: %s\n", | |
1582 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1583 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1584 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1585 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1586 | seq_printf(m, "RC6 Enabled: %s\n", | |
1587 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1588 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1589 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1590 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1591 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1592 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1593 | } | |
4d85529d BW |
1594 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1595 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1596 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1597 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1598 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1599 | switch (gt_core_status & GEN6_RCn_MASK) { |
1600 | case GEN6_RC0: | |
1601 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1602 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1603 | else |
267f0c90 | 1604 | seq_puts(m, "on\n"); |
4d85529d BW |
1605 | break; |
1606 | case GEN6_RC3: | |
267f0c90 | 1607 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1608 | break; |
1609 | case GEN6_RC6: | |
267f0c90 | 1610 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1611 | break; |
1612 | case GEN6_RC7: | |
267f0c90 | 1613 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1614 | break; |
1615 | default: | |
267f0c90 | 1616 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1617 | break; |
1618 | } | |
1619 | ||
1620 | seq_printf(m, "Core Power Down: %s\n", | |
1621 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1622 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1623 | seq_printf(m, "Render Power Well: %s\n", |
1624 | (gen9_powergate_status & | |
1625 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1626 | seq_printf(m, "Media Power Well: %s\n", | |
1627 | (gen9_powergate_status & | |
1628 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1629 | } | |
cce66a28 BW |
1630 | |
1631 | /* Not exactly sure what this is */ | |
1632 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1633 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1634 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1635 | I915_READ(GEN6_GT_GFX_RC6)); | |
1636 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1637 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1638 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1639 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1640 | ||
ecd8faea BW |
1641 | seq_printf(m, "RC6 voltage: %dmV\n", |
1642 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1643 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1644 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1645 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1646 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1647 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1648 | } |
1649 | ||
1650 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1651 | { | |
36cdd013 | 1652 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4d85529d | 1653 | |
36cdd013 | 1654 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
669ab5aa | 1655 | return vlv_drpc_info(m); |
36cdd013 | 1656 | else if (INTEL_GEN(dev_priv) >= 6) |
4d85529d BW |
1657 | return gen6_drpc_info(m); |
1658 | else | |
1659 | return ironlake_drpc_info(m); | |
1660 | } | |
1661 | ||
9a851789 DV |
1662 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1663 | { | |
36cdd013 | 1664 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1665 | |
1666 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1667 | dev_priv->fb_tracking.busy_bits); | |
1668 | ||
1669 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1670 | dev_priv->fb_tracking.flip_bits); | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
b5e50c3f JB |
1675 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1676 | { | |
36cdd013 | 1677 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1678 | |
36cdd013 | 1679 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1680 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1681 | return 0; |
1682 | } | |
1683 | ||
36623ef8 | 1684 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1685 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1686 | |
0e631adc | 1687 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1688 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1689 | else |
1690 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1691 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1692 | |
0fc6a9dc PZ |
1693 | if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { |
1694 | uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? | |
1695 | BDW_FBC_COMPRESSION_MASK : | |
1696 | IVB_FBC_COMPRESSION_MASK; | |
31b9df10 | 1697 | seq_printf(m, "Compressing: %s\n", |
0fc6a9dc PZ |
1698 | yesno(I915_READ(FBC_STATUS2) & mask)); |
1699 | } | |
31b9df10 | 1700 | |
25ad93fd | 1701 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1702 | intel_runtime_pm_put(dev_priv); |
1703 | ||
b5e50c3f JB |
1704 | return 0; |
1705 | } | |
1706 | ||
da46f936 RV |
1707 | static int i915_fbc_fc_get(void *data, u64 *val) |
1708 | { | |
36cdd013 | 1709 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1710 | |
36cdd013 | 1711 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1712 | return -ENODEV; |
1713 | ||
da46f936 | 1714 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1715 | |
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | static int i915_fbc_fc_set(void *data, u64 val) | |
1720 | { | |
36cdd013 | 1721 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1722 | u32 reg; |
1723 | ||
36cdd013 | 1724 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1725 | return -ENODEV; |
1726 | ||
25ad93fd | 1727 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1728 | |
1729 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1730 | dev_priv->fbc.false_color = val; | |
1731 | ||
1732 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1733 | (reg | FBC_CTL_FALSE_COLOR) : | |
1734 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1735 | ||
25ad93fd | 1736 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1737 | return 0; |
1738 | } | |
1739 | ||
1740 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1741 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1742 | "%llu\n"); | |
1743 | ||
92d44621 PZ |
1744 | static int i915_ips_status(struct seq_file *m, void *unused) |
1745 | { | |
36cdd013 | 1746 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1747 | |
36cdd013 | 1748 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1749 | seq_puts(m, "not supported\n"); |
1750 | return 0; | |
1751 | } | |
1752 | ||
36623ef8 PZ |
1753 | intel_runtime_pm_get(dev_priv); |
1754 | ||
0eaa53f0 RV |
1755 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1756 | yesno(i915.enable_ips)); | |
1757 | ||
36cdd013 | 1758 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1759 | seq_puts(m, "Currently: unknown\n"); |
1760 | } else { | |
1761 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1762 | seq_puts(m, "Currently: enabled\n"); | |
1763 | else | |
1764 | seq_puts(m, "Currently: disabled\n"); | |
1765 | } | |
92d44621 | 1766 | |
36623ef8 PZ |
1767 | intel_runtime_pm_put(dev_priv); |
1768 | ||
92d44621 PZ |
1769 | return 0; |
1770 | } | |
1771 | ||
4a9bef37 JB |
1772 | static int i915_sr_status(struct seq_file *m, void *unused) |
1773 | { | |
36cdd013 | 1774 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1775 | bool sr_enabled = false; |
1776 | ||
36623ef8 | 1777 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1778 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1779 | |
36cdd013 | 1780 | if (HAS_PCH_SPLIT(dev_priv)) |
5ba2aaaa | 1781 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1782 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1783 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1784 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1785 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1786 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1787 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1788 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1789 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1790 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1791 | |
9c870d03 | 1792 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1793 | intel_runtime_pm_put(dev_priv); |
1794 | ||
08c4d7fc | 1795 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1796 | |
1797 | return 0; | |
1798 | } | |
1799 | ||
7648fa99 JB |
1800 | static int i915_emon_status(struct seq_file *m, void *unused) |
1801 | { | |
36cdd013 DW |
1802 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1803 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1804 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1805 | int ret; |
1806 | ||
36cdd013 | 1807 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1808 | return -ENODEV; |
1809 | ||
de227ef0 CW |
1810 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1811 | if (ret) | |
1812 | return ret; | |
7648fa99 JB |
1813 | |
1814 | temp = i915_mch_val(dev_priv); | |
1815 | chipset = i915_chipset_val(dev_priv); | |
1816 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1817 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1818 | |
1819 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1820 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1821 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1822 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
23b2f8bb JB |
1827 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1828 | { | |
36cdd013 | 1829 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1830 | int ret = 0; |
23b2f8bb | 1831 | int gpu_freq, ia_freq; |
f936ec34 | 1832 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1833 | |
26310346 | 1834 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1835 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1836 | return 0; |
1837 | } | |
1838 | ||
5bfa0199 PZ |
1839 | intel_runtime_pm_get(dev_priv); |
1840 | ||
4fc688ce | 1841 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1842 | if (ret) |
5bfa0199 | 1843 | goto out; |
23b2f8bb | 1844 | |
b976dc53 | 1845 | if (IS_GEN9_BC(dev_priv)) { |
f936ec34 AG |
1846 | /* Convert GT frequency to 50 HZ units */ |
1847 | min_gpu_freq = | |
1848 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1849 | max_gpu_freq = | |
1850 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1851 | } else { | |
1852 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1853 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1854 | } | |
1855 | ||
267f0c90 | 1856 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1857 | |
f936ec34 | 1858 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1859 | ia_freq = gpu_freq; |
1860 | sandybridge_pcode_read(dev_priv, | |
1861 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1862 | &ia_freq); | |
3ebecd07 | 1863 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1864 | intel_gpu_freq(dev_priv, (gpu_freq * |
b976dc53 RV |
1865 | (IS_GEN9_BC(dev_priv) ? |
1866 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1867 | ((ia_freq >> 0) & 0xff) * 100, |
1868 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1869 | } |
1870 | ||
4fc688ce | 1871 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1872 | |
5bfa0199 PZ |
1873 | out: |
1874 | intel_runtime_pm_put(dev_priv); | |
1875 | return ret; | |
23b2f8bb JB |
1876 | } |
1877 | ||
44834a67 CW |
1878 | static int i915_opregion(struct seq_file *m, void *unused) |
1879 | { | |
36cdd013 DW |
1880 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1881 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1882 | struct intel_opregion *opregion = &dev_priv->opregion; |
1883 | int ret; | |
1884 | ||
1885 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1886 | if (ret) | |
0d38f009 | 1887 | goto out; |
44834a67 | 1888 | |
2455a8e4 JN |
1889 | if (opregion->header) |
1890 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1891 | |
1892 | mutex_unlock(&dev->struct_mutex); | |
1893 | ||
0d38f009 | 1894 | out: |
44834a67 CW |
1895 | return 0; |
1896 | } | |
1897 | ||
ada8f955 JN |
1898 | static int i915_vbt(struct seq_file *m, void *unused) |
1899 | { | |
36cdd013 | 1900 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1901 | |
1902 | if (opregion->vbt) | |
1903 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
37811fcc CW |
1908 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1909 | { | |
36cdd013 DW |
1910 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1911 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1912 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1913 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1914 | int ret; |
1915 | ||
1916 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1917 | if (ret) | |
1918 | return ret; | |
37811fcc | 1919 | |
0695726e | 1920 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
36cdd013 DW |
1921 | if (dev_priv->fbdev) { |
1922 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); | |
25bcce94 CW |
1923 | |
1924 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1925 | fbdev_fb->base.width, | |
1926 | fbdev_fb->base.height, | |
b00c600e | 1927 | fbdev_fb->base.format->depth, |
272725c7 | 1928 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1929 | fbdev_fb->base.modifier, |
25bcce94 CW |
1930 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1931 | describe_obj(m, fbdev_fb->obj); | |
1932 | seq_putc(m, '\n'); | |
1933 | } | |
4520f53a | 1934 | #endif |
37811fcc | 1935 | |
4b096ac1 | 1936 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1937 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1938 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1939 | if (fb == fbdev_fb) | |
37811fcc CW |
1940 | continue; |
1941 | ||
c1ca506d | 1942 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1943 | fb->base.width, |
1944 | fb->base.height, | |
b00c600e | 1945 | fb->base.format->depth, |
272725c7 | 1946 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1947 | fb->base.modifier, |
747a598f | 1948 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1949 | describe_obj(m, fb->obj); |
267f0c90 | 1950 | seq_putc(m, '\n'); |
37811fcc | 1951 | } |
4b096ac1 | 1952 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1953 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1954 | |
1955 | return 0; | |
1956 | } | |
1957 | ||
7e37f889 | 1958 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1959 | { |
1960 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1961 | ring->space, ring->head, ring->tail, |
1962 | ring->last_retired_head); | |
c9fe99bd OM |
1963 | } |
1964 | ||
e76d3630 BW |
1965 | static int i915_context_status(struct seq_file *m, void *unused) |
1966 | { | |
36cdd013 DW |
1967 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1968 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1969 | struct intel_engine_cs *engine; |
e2efd130 | 1970 | struct i915_gem_context *ctx; |
3b3f1650 | 1971 | enum intel_engine_id id; |
c3232b18 | 1972 | int ret; |
e76d3630 | 1973 | |
f3d28878 | 1974 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1975 | if (ret) |
1976 | return ret; | |
1977 | ||
a33afea5 | 1978 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1979 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1980 | if (ctx->pid) { |
d28b99ab CW |
1981 | struct task_struct *task; |
1982 | ||
c84455b4 | 1983 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1984 | if (task) { |
1985 | seq_printf(m, "(%s [%d]) ", | |
1986 | task->comm, task->pid); | |
1987 | put_task_struct(task); | |
1988 | } | |
c84455b4 CW |
1989 | } else if (IS_ERR(ctx->file_priv)) { |
1990 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1991 | } else { |
1992 | seq_puts(m, "(kernel) "); | |
1993 | } | |
1994 | ||
bca44d80 CW |
1995 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1996 | seq_putc(m, '\n'); | |
c9fe99bd | 1997 | |
3b3f1650 | 1998 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1999 | struct intel_context *ce = &ctx->engine[engine->id]; |
2000 | ||
2001 | seq_printf(m, "%s: ", engine->name); | |
2002 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
2003 | if (ce->state) | |
bf3783e5 | 2004 | describe_obj(m, ce->state->obj); |
dca33ecc | 2005 | if (ce->ring) |
7e37f889 | 2006 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 2007 | seq_putc(m, '\n'); |
c9fe99bd | 2008 | } |
a33afea5 | 2009 | |
a33afea5 | 2010 | seq_putc(m, '\n'); |
a168c293 BW |
2011 | } |
2012 | ||
f3d28878 | 2013 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2014 | |
2015 | return 0; | |
2016 | } | |
2017 | ||
064ca1d2 | 2018 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2019 | struct i915_gem_context *ctx, |
0bc40be8 | 2020 | struct intel_engine_cs *engine) |
064ca1d2 | 2021 | { |
bf3783e5 | 2022 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2023 | struct page *page; |
064ca1d2 | 2024 | int j; |
064ca1d2 | 2025 | |
7069b144 CW |
2026 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2027 | ||
bf3783e5 CW |
2028 | if (!vma) { |
2029 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2030 | return; |
2031 | } | |
2032 | ||
bf3783e5 CW |
2033 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2034 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2035 | i915_ggtt_offset(vma)); |
064ca1d2 | 2036 | |
a4f5ea64 | 2037 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2038 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2039 | return; |
2040 | } | |
2041 | ||
bf3783e5 CW |
2042 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2043 | if (page) { | |
2044 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2045 | |
2046 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2047 | seq_printf(m, |
2048 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2049 | j * 4, | |
064ca1d2 TD |
2050 | reg_state[j], reg_state[j + 1], |
2051 | reg_state[j + 2], reg_state[j + 3]); | |
2052 | } | |
2053 | kunmap_atomic(reg_state); | |
2054 | } | |
2055 | ||
a4f5ea64 | 2056 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2057 | seq_putc(m, '\n'); |
2058 | } | |
2059 | ||
c0ab1ae9 BW |
2060 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2061 | { | |
36cdd013 DW |
2062 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2063 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2064 | struct intel_engine_cs *engine; |
e2efd130 | 2065 | struct i915_gem_context *ctx; |
3b3f1650 | 2066 | enum intel_engine_id id; |
b4ac5afc | 2067 | int ret; |
c0ab1ae9 BW |
2068 | |
2069 | if (!i915.enable_execlists) { | |
2070 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2071 | return 0; | |
2072 | } | |
2073 | ||
2074 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2075 | if (ret) | |
2076 | return ret; | |
2077 | ||
e28e404c | 2078 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3b3f1650 | 2079 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2080 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2081 | |
2082 | mutex_unlock(&dev->struct_mutex); | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
ea16a3cd DV |
2087 | static const char *swizzle_string(unsigned swizzle) |
2088 | { | |
aee56cff | 2089 | switch (swizzle) { |
ea16a3cd DV |
2090 | case I915_BIT_6_SWIZZLE_NONE: |
2091 | return "none"; | |
2092 | case I915_BIT_6_SWIZZLE_9: | |
2093 | return "bit9"; | |
2094 | case I915_BIT_6_SWIZZLE_9_10: | |
2095 | return "bit9/bit10"; | |
2096 | case I915_BIT_6_SWIZZLE_9_11: | |
2097 | return "bit9/bit11"; | |
2098 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2099 | return "bit9/bit10/bit11"; | |
2100 | case I915_BIT_6_SWIZZLE_9_17: | |
2101 | return "bit9/bit17"; | |
2102 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2103 | return "bit9/bit10/bit17"; | |
2104 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2105 | return "unknown"; |
ea16a3cd DV |
2106 | } |
2107 | ||
2108 | return "bug"; | |
2109 | } | |
2110 | ||
2111 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2112 | { | |
36cdd013 | 2113 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2114 | |
c8c8fb33 | 2115 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2116 | |
ea16a3cd DV |
2117 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2118 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2119 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2120 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2121 | ||
36cdd013 | 2122 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2123 | seq_printf(m, "DDC = 0x%08x\n", |
2124 | I915_READ(DCC)); | |
656bfa3a DV |
2125 | seq_printf(m, "DDC2 = 0x%08x\n", |
2126 | I915_READ(DCC2)); | |
ea16a3cd DV |
2127 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2128 | I915_READ16(C0DRB3)); | |
2129 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2130 | I915_READ16(C1DRB3)); | |
36cdd013 | 2131 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2132 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2133 | I915_READ(MAD_DIMM_C0)); | |
2134 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2135 | I915_READ(MAD_DIMM_C1)); | |
2136 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2137 | I915_READ(MAD_DIMM_C2)); | |
2138 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2139 | I915_READ(TILECTL)); | |
36cdd013 | 2140 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2141 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2142 | I915_READ(GAMTARBMODE)); | |
2143 | else | |
2144 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2145 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2146 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2147 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2148 | } |
656bfa3a DV |
2149 | |
2150 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2151 | seq_puts(m, "L-shaped memory detected\n"); | |
2152 | ||
c8c8fb33 | 2153 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2154 | |
2155 | return 0; | |
2156 | } | |
2157 | ||
1c60fef5 BW |
2158 | static int per_file_ctx(int id, void *ptr, void *data) |
2159 | { | |
e2efd130 | 2160 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2161 | struct seq_file *m = data; |
ae6c4806 DV |
2162 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2163 | ||
2164 | if (!ppgtt) { | |
2165 | seq_printf(m, " no ppgtt for context %d\n", | |
2166 | ctx->user_handle); | |
2167 | return 0; | |
2168 | } | |
1c60fef5 | 2169 | |
f83d6518 OM |
2170 | if (i915_gem_context_is_default(ctx)) |
2171 | seq_puts(m, " default context:\n"); | |
2172 | else | |
821d66dd | 2173 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2174 | ppgtt->debug_dump(ppgtt, m); |
2175 | ||
2176 | return 0; | |
2177 | } | |
2178 | ||
36cdd013 DW |
2179 | static void gen8_ppgtt_info(struct seq_file *m, |
2180 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2181 | { |
77df6772 | 2182 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2183 | struct intel_engine_cs *engine; |
2184 | enum intel_engine_id id; | |
b4ac5afc | 2185 | int i; |
3cf17fc5 | 2186 | |
77df6772 BW |
2187 | if (!ppgtt) |
2188 | return; | |
2189 | ||
3b3f1650 | 2190 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2191 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2192 | for (i = 0; i < 4; i++) { |
e2f80391 | 2193 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2194 | pdp <<= 32; |
e2f80391 | 2195 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2196 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2197 | } |
2198 | } | |
2199 | } | |
2200 | ||
36cdd013 DW |
2201 | static void gen6_ppgtt_info(struct seq_file *m, |
2202 | struct drm_i915_private *dev_priv) | |
77df6772 | 2203 | { |
e2f80391 | 2204 | struct intel_engine_cs *engine; |
3b3f1650 | 2205 | enum intel_engine_id id; |
3cf17fc5 | 2206 | |
7e22dbbb | 2207 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2208 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2209 | ||
3b3f1650 | 2210 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2211 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2212 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2213 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2214 | I915_READ(RING_MODE_GEN7(engine))); | |
2215 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2216 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2217 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2218 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2219 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2220 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2221 | } |
2222 | if (dev_priv->mm.aliasing_ppgtt) { | |
2223 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2224 | ||
267f0c90 | 2225 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2226 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2227 | |
87d60b63 | 2228 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2229 | } |
1c60fef5 | 2230 | |
3cf17fc5 | 2231 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2232 | } |
2233 | ||
2234 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2235 | { | |
36cdd013 DW |
2236 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2237 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2238 | struct drm_file *file; |
637ee29e | 2239 | int ret; |
77df6772 | 2240 | |
637ee29e CW |
2241 | mutex_lock(&dev->filelist_mutex); |
2242 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2243 | if (ret) |
637ee29e CW |
2244 | goto out_unlock; |
2245 | ||
c8c8fb33 | 2246 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2247 | |
36cdd013 DW |
2248 | if (INTEL_GEN(dev_priv) >= 8) |
2249 | gen8_ppgtt_info(m, dev_priv); | |
2250 | else if (INTEL_GEN(dev_priv) >= 6) | |
2251 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2252 | |
ea91e401 MT |
2253 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2254 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2255 | struct task_struct *task; |
ea91e401 | 2256 | |
7cb5dff8 | 2257 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2258 | if (!task) { |
2259 | ret = -ESRCH; | |
637ee29e | 2260 | goto out_rpm; |
06812760 | 2261 | } |
7cb5dff8 GT |
2262 | seq_printf(m, "\nproc: %s\n", task->comm); |
2263 | put_task_struct(task); | |
ea91e401 MT |
2264 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2265 | (void *)(unsigned long)m); | |
2266 | } | |
2267 | ||
637ee29e | 2268 | out_rpm: |
c8c8fb33 | 2269 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2270 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2271 | out_unlock: |
2272 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2273 | return ret; |
3cf17fc5 DV |
2274 | } |
2275 | ||
f5a4c67d CW |
2276 | static int count_irq_waiters(struct drm_i915_private *i915) |
2277 | { | |
e2f80391 | 2278 | struct intel_engine_cs *engine; |
3b3f1650 | 2279 | enum intel_engine_id id; |
f5a4c67d | 2280 | int count = 0; |
f5a4c67d | 2281 | |
3b3f1650 | 2282 | for_each_engine(engine, i915, id) |
688e6c72 | 2283 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2284 | |
2285 | return count; | |
2286 | } | |
2287 | ||
7466c291 CW |
2288 | static const char *rps_power_to_str(unsigned int power) |
2289 | { | |
2290 | static const char * const strings[] = { | |
2291 | [LOW_POWER] = "low power", | |
2292 | [BETWEEN] = "mixed", | |
2293 | [HIGH_POWER] = "high power", | |
2294 | }; | |
2295 | ||
2296 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2297 | return "unknown"; | |
2298 | ||
2299 | return strings[power]; | |
2300 | } | |
2301 | ||
1854d5ca CW |
2302 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2303 | { | |
36cdd013 DW |
2304 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2305 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2306 | struct drm_file *file; |
1854d5ca | 2307 | |
f5a4c67d | 2308 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2309 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2310 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2311 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2312 | seq_printf(m, "Frequency requested %d\n", |
2313 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2314 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2315 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2316 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2317 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2318 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2319 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2320 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2321 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2322 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2323 | |
2324 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2325 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2326 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2327 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2328 | struct task_struct *task; | |
2329 | ||
2330 | rcu_read_lock(); | |
2331 | task = pid_task(file->pid, PIDTYPE_PID); | |
2332 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2333 | task ? task->comm : "<unknown>", | |
2334 | task ? task->pid : -1, | |
2e1b8730 CW |
2335 | file_priv->rps.boosts, |
2336 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2337 | rcu_read_unlock(); |
2338 | } | |
197be2ae | 2339 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2340 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2341 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2342 | |
7466c291 CW |
2343 | if (INTEL_GEN(dev_priv) >= 6 && |
2344 | dev_priv->rps.enabled && | |
28176ef4 | 2345 | dev_priv->gt.active_requests) { |
7466c291 CW |
2346 | u32 rpup, rpupei; |
2347 | u32 rpdown, rpdownei; | |
2348 | ||
2349 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2350 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2351 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2352 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2353 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2354 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2355 | ||
2356 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2357 | rps_power_to_str(dev_priv->rps.power)); | |
2358 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2359 | 100 * rpup / rpupei, | |
2360 | dev_priv->rps.up_threshold); | |
2361 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2362 | 100 * rpdown / rpdownei, | |
2363 | dev_priv->rps.down_threshold); | |
2364 | } else { | |
2365 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2366 | } | |
2367 | ||
8d3afd7d | 2368 | return 0; |
1854d5ca CW |
2369 | } |
2370 | ||
63573eb7 BW |
2371 | static int i915_llc(struct seq_file *m, void *data) |
2372 | { | |
36cdd013 | 2373 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2374 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2375 | |
36cdd013 | 2376 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2377 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2378 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2379 | |
2380 | return 0; | |
2381 | } | |
2382 | ||
0509ead1 AS |
2383 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2384 | { | |
2385 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2386 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2387 | ||
2388 | if (!HAS_HUC_UCODE(dev_priv)) | |
2389 | return 0; | |
2390 | ||
2391 | seq_puts(m, "HuC firmware status:\n"); | |
2392 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2393 | seq_printf(m, "\tfetch: %s\n", | |
2394 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2395 | seq_printf(m, "\tload: %s\n", | |
2396 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2397 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2398 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2399 | seq_printf(m, "\tversion found: %d.%d\n", | |
2400 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2401 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2402 | huc_fw->header_offset, huc_fw->header_size); | |
2403 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2404 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2405 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2406 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2407 | ||
3582ad13 | 2408 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2409 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2410 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2411 | |
2412 | return 0; | |
2413 | } | |
2414 | ||
fdf5d357 AD |
2415 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2416 | { | |
36cdd013 | 2417 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2418 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2419 | u32 tmp, i; |
2420 | ||
2d1fe073 | 2421 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2422 | return 0; |
2423 | ||
2424 | seq_printf(m, "GuC firmware status:\n"); | |
2425 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2426 | guc_fw->path); |
fdf5d357 | 2427 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2428 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2429 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2430 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2431 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2432 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2433 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2434 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2435 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2436 | guc_fw->header_offset, guc_fw->header_size); | |
2437 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2438 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2439 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2440 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2441 | |
3582ad13 | 2442 | intel_runtime_pm_get(dev_priv); |
2443 | ||
fdf5d357 AD |
2444 | tmp = I915_READ(GUC_STATUS); |
2445 | ||
2446 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2447 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2448 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2449 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2450 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2451 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2452 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2453 | seq_puts(m, "\nScratch registers:\n"); | |
2454 | for (i = 0; i < 16; i++) | |
2455 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2456 | ||
3582ad13 | 2457 | intel_runtime_pm_put(dev_priv); |
2458 | ||
fdf5d357 AD |
2459 | return 0; |
2460 | } | |
2461 | ||
5aa1ee4b AG |
2462 | static void i915_guc_log_info(struct seq_file *m, |
2463 | struct drm_i915_private *dev_priv) | |
2464 | { | |
2465 | struct intel_guc *guc = &dev_priv->guc; | |
2466 | ||
2467 | seq_puts(m, "\nGuC logging stats:\n"); | |
2468 | ||
2469 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2470 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2471 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2472 | ||
2473 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2474 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2475 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2476 | ||
2477 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2478 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2479 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2480 | ||
2481 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2482 | guc->log.flush_interrupt_count); | |
2483 | ||
2484 | seq_printf(m, "\tCapture miss count: %u\n", | |
2485 | guc->log.capture_miss_count); | |
2486 | } | |
2487 | ||
8b417c26 DG |
2488 | static void i915_guc_client_info(struct seq_file *m, |
2489 | struct drm_i915_private *dev_priv, | |
2490 | struct i915_guc_client *client) | |
2491 | { | |
e2f80391 | 2492 | struct intel_engine_cs *engine; |
c18468c4 | 2493 | enum intel_engine_id id; |
8b417c26 | 2494 | uint64_t tot = 0; |
8b417c26 DG |
2495 | |
2496 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2497 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2498 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
357248bf | 2499 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2500 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2501 | client->wq_size, client->wq_offset, client->wq_tail); | |
2502 | ||
551aaecd | 2503 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2504 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2505 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2506 | ||
3b3f1650 | 2507 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2508 | u64 submissions = client->submissions[id]; |
2509 | tot += submissions; | |
8b417c26 | 2510 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2511 | submissions, engine->name); |
8b417c26 DG |
2512 | } |
2513 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2514 | } | |
2515 | ||
2516 | static int i915_guc_info(struct seq_file *m, void *data) | |
2517 | { | |
36cdd013 | 2518 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2519 | const struct intel_guc *guc = &dev_priv->guc; |
e2f80391 | 2520 | struct intel_engine_cs *engine; |
c18468c4 | 2521 | enum intel_engine_id id; |
334636c6 | 2522 | u64 total; |
8b417c26 | 2523 | |
334636c6 CW |
2524 | if (!guc->execbuf_client) { |
2525 | seq_printf(m, "GuC submission %s\n", | |
2526 | HAS_GUC_SCHED(dev_priv) ? | |
2527 | "disabled" : | |
2528 | "not supported"); | |
5a843307 | 2529 | return 0; |
334636c6 | 2530 | } |
8b417c26 | 2531 | |
9636f6db | 2532 | seq_printf(m, "Doorbell map:\n"); |
334636c6 CW |
2533 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc->doorbell_bitmap); |
2534 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); | |
9636f6db | 2535 | |
334636c6 CW |
2536 | seq_printf(m, "GuC total action count: %llu\n", guc->action_count); |
2537 | seq_printf(m, "GuC action failure count: %u\n", guc->action_fail); | |
2538 | seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd); | |
2539 | seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status); | |
2540 | seq_printf(m, "GuC last action error code: %d\n", guc->action_err); | |
8b417c26 | 2541 | |
334636c6 | 2542 | total = 0; |
8b417c26 | 2543 | seq_printf(m, "\nGuC submissions:\n"); |
3b3f1650 | 2544 | for_each_engine(engine, dev_priv, id) { |
334636c6 | 2545 | u64 submissions = guc->submissions[id]; |
c18468c4 | 2546 | total += submissions; |
397097b0 | 2547 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
334636c6 | 2548 | engine->name, submissions, guc->last_seqno[id]); |
8b417c26 DG |
2549 | } |
2550 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2551 | ||
334636c6 CW |
2552 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2553 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2554 | |
5aa1ee4b AG |
2555 | i915_guc_log_info(m, dev_priv); |
2556 | ||
8b417c26 DG |
2557 | /* Add more as required ... */ |
2558 | ||
2559 | return 0; | |
2560 | } | |
2561 | ||
4c7e77fc AD |
2562 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2563 | { | |
36cdd013 | 2564 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
8b797af1 | 2565 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2566 | int i = 0, pg; |
2567 | ||
d6b40b4b | 2568 | if (!dev_priv->guc.log.vma) |
4c7e77fc AD |
2569 | return 0; |
2570 | ||
d6b40b4b | 2571 | obj = dev_priv->guc.log.vma->obj; |
8b797af1 CW |
2572 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { |
2573 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2574 | |
2575 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2576 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2577 | *(log + i), *(log + i + 1), | |
2578 | *(log + i + 2), *(log + i + 3)); | |
2579 | ||
2580 | kunmap_atomic(log); | |
2581 | } | |
2582 | ||
2583 | seq_putc(m, '\n'); | |
2584 | ||
2585 | return 0; | |
2586 | } | |
2587 | ||
685534ef SAK |
2588 | static int i915_guc_log_control_get(void *data, u64 *val) |
2589 | { | |
2590 | struct drm_device *dev = data; | |
2591 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2592 | ||
2593 | if (!dev_priv->guc.log.vma) | |
2594 | return -EINVAL; | |
2595 | ||
2596 | *val = i915.guc_log_level; | |
2597 | ||
2598 | return 0; | |
2599 | } | |
2600 | ||
2601 | static int i915_guc_log_control_set(void *data, u64 val) | |
2602 | { | |
2603 | struct drm_device *dev = data; | |
2604 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2605 | int ret; | |
2606 | ||
2607 | if (!dev_priv->guc.log.vma) | |
2608 | return -EINVAL; | |
2609 | ||
2610 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2611 | if (ret) | |
2612 | return ret; | |
2613 | ||
2614 | intel_runtime_pm_get(dev_priv); | |
2615 | ret = i915_guc_log_control(dev_priv, val); | |
2616 | intel_runtime_pm_put(dev_priv); | |
2617 | ||
2618 | mutex_unlock(&dev->struct_mutex); | |
2619 | return ret; | |
2620 | } | |
2621 | ||
2622 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2623 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2624 | "%lld\n"); | |
2625 | ||
b86bef20 CW |
2626 | static const char *psr2_live_status(u32 val) |
2627 | { | |
2628 | static const char * const live_status[] = { | |
2629 | "IDLE", | |
2630 | "CAPTURE", | |
2631 | "CAPTURE_FS", | |
2632 | "SLEEP", | |
2633 | "BUFON_FW", | |
2634 | "ML_UP", | |
2635 | "SU_STANDBY", | |
2636 | "FAST_SLEEP", | |
2637 | "DEEP_SLEEP", | |
2638 | "BUF_ON", | |
2639 | "TG_ON" | |
2640 | }; | |
2641 | ||
2642 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2643 | if (val < ARRAY_SIZE(live_status)) | |
2644 | return live_status[val]; | |
2645 | ||
2646 | return "unknown"; | |
2647 | } | |
2648 | ||
e91fd8c6 RV |
2649 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2650 | { | |
36cdd013 | 2651 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2652 | u32 psrperf = 0; |
a6cbdb8e RV |
2653 | u32 stat[3]; |
2654 | enum pipe pipe; | |
a031d709 | 2655 | bool enabled = false; |
e91fd8c6 | 2656 | |
36cdd013 | 2657 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2658 | seq_puts(m, "PSR not supported\n"); |
2659 | return 0; | |
2660 | } | |
2661 | ||
c8c8fb33 PZ |
2662 | intel_runtime_pm_get(dev_priv); |
2663 | ||
fa128fa6 | 2664 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2665 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2666 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2667 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2668 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2669 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2670 | dev_priv->psr.busy_frontbuffer_bits); | |
2671 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2672 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2673 | |
7e3eb599 NV |
2674 | if (HAS_DDI(dev_priv)) { |
2675 | if (dev_priv->psr.psr2_support) | |
2676 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2677 | else | |
2678 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2679 | } else { | |
3553a8ea | 2680 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2681 | enum transcoder cpu_transcoder = |
2682 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2683 | enum intel_display_power_domain power_domain; | |
2684 | ||
2685 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2686 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2687 | power_domain)) | |
2688 | continue; | |
2689 | ||
3553a8ea DL |
2690 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2691 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2692 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2693 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2694 | enabled = true; | |
9c870d03 CW |
2695 | |
2696 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2697 | } |
2698 | } | |
60e5ffe3 RV |
2699 | |
2700 | seq_printf(m, "Main link in standby mode: %s\n", | |
2701 | yesno(dev_priv->psr.link_standby)); | |
2702 | ||
a6cbdb8e RV |
2703 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2704 | ||
36cdd013 | 2705 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2706 | for_each_pipe(dev_priv, pipe) { |
2707 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2708 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2709 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2710 | } | |
2711 | seq_puts(m, "\n"); | |
e91fd8c6 | 2712 | |
05eec3c2 RV |
2713 | /* |
2714 | * VLV/CHV PSR has no kind of performance counter | |
2715 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2716 | */ | |
36cdd013 | 2717 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2718 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2719 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2720 | |
2721 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2722 | } | |
6ba1f9e1 | 2723 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2724 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2725 | ||
2726 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2727 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2728 | } |
fa128fa6 | 2729 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2730 | |
c8c8fb33 | 2731 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2732 | return 0; |
2733 | } | |
2734 | ||
d2e216d0 RV |
2735 | static int i915_sink_crc(struct seq_file *m, void *data) |
2736 | { | |
36cdd013 DW |
2737 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2738 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 RV |
2739 | struct intel_connector *connector; |
2740 | struct intel_dp *intel_dp = NULL; | |
2741 | int ret; | |
2742 | u8 crc[6]; | |
2743 | ||
2744 | drm_modeset_lock_all(dev); | |
aca5e361 | 2745 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2746 | struct drm_crtc *crtc; |
d2e216d0 | 2747 | |
26c17cf6 | 2748 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2749 | continue; |
2750 | ||
26c17cf6 ML |
2751 | crtc = connector->base.state->crtc; |
2752 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2753 | continue; |
2754 | ||
26c17cf6 | 2755 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2756 | continue; |
2757 | ||
26c17cf6 | 2758 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2759 | |
2760 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2761 | if (ret) | |
2762 | goto out; | |
2763 | ||
2764 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2765 | crc[0], crc[1], crc[2], | |
2766 | crc[3], crc[4], crc[5]); | |
2767 | goto out; | |
2768 | } | |
2769 | ret = -ENODEV; | |
2770 | out: | |
2771 | drm_modeset_unlock_all(dev); | |
2772 | return ret; | |
2773 | } | |
2774 | ||
ec013e7f JB |
2775 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2776 | { | |
36cdd013 | 2777 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ec013e7f JB |
2778 | u64 power; |
2779 | u32 units; | |
2780 | ||
36cdd013 | 2781 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2782 | return -ENODEV; |
2783 | ||
36623ef8 PZ |
2784 | intel_runtime_pm_get(dev_priv); |
2785 | ||
ec013e7f JB |
2786 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2787 | power = (power & 0x1f00) >> 8; | |
2788 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2789 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2790 | power *= units; | |
2791 | ||
36623ef8 PZ |
2792 | intel_runtime_pm_put(dev_priv); |
2793 | ||
ec013e7f | 2794 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2795 | |
2796 | return 0; | |
2797 | } | |
2798 | ||
6455c870 | 2799 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2800 | { |
36cdd013 | 2801 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2802 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2803 | |
a156e64d CW |
2804 | if (!HAS_RUNTIME_PM(dev_priv)) |
2805 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2806 | |
67d97da3 | 2807 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2808 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2809 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2810 | #ifdef CONFIG_PM |
a6aaec8b | 2811 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2812 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2813 | #else |
2814 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2815 | #endif | |
a156e64d | 2816 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2817 | pci_power_name(pdev->current_state), |
2818 | pdev->current_state); | |
371db66a | 2819 | |
ec013e7f JB |
2820 | return 0; |
2821 | } | |
2822 | ||
1da51581 ID |
2823 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2824 | { | |
36cdd013 | 2825 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2826 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2827 | int i; | |
2828 | ||
2829 | mutex_lock(&power_domains->lock); | |
2830 | ||
2831 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2832 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2833 | struct i915_power_well *power_well; | |
2834 | enum intel_display_power_domain power_domain; | |
2835 | ||
2836 | power_well = &power_domains->power_wells[i]; | |
2837 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2838 | power_well->count); | |
2839 | ||
8385c2ec | 2840 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2841 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2842 | intel_display_power_domain_str(power_domain), |
1da51581 | 2843 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2844 | } |
2845 | ||
2846 | mutex_unlock(&power_domains->lock); | |
2847 | ||
2848 | return 0; | |
2849 | } | |
2850 | ||
b7cec66d DL |
2851 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2852 | { | |
36cdd013 | 2853 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2854 | struct intel_csr *csr; |
2855 | ||
36cdd013 | 2856 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2857 | seq_puts(m, "not supported\n"); |
2858 | return 0; | |
2859 | } | |
2860 | ||
2861 | csr = &dev_priv->csr; | |
2862 | ||
6fb403de MK |
2863 | intel_runtime_pm_get(dev_priv); |
2864 | ||
b7cec66d DL |
2865 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2866 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2867 | ||
2868 | if (!csr->dmc_payload) | |
6fb403de | 2869 | goto out; |
b7cec66d DL |
2870 | |
2871 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2872 | CSR_VERSION_MINOR(csr->version)); | |
2873 | ||
36cdd013 | 2874 | if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { |
8337206d DL |
2875 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2876 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2877 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2878 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2879 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2880 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2881 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2882 | } |
2883 | ||
6fb403de MK |
2884 | out: |
2885 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2886 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2887 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2888 | ||
8337206d DL |
2889 | intel_runtime_pm_put(dev_priv); |
2890 | ||
b7cec66d DL |
2891 | return 0; |
2892 | } | |
2893 | ||
53f5e3ca JB |
2894 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2895 | struct drm_display_mode *mode) | |
2896 | { | |
2897 | int i; | |
2898 | ||
2899 | for (i = 0; i < tabs; i++) | |
2900 | seq_putc(m, '\t'); | |
2901 | ||
2902 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2903 | mode->base.id, mode->name, | |
2904 | mode->vrefresh, mode->clock, | |
2905 | mode->hdisplay, mode->hsync_start, | |
2906 | mode->hsync_end, mode->htotal, | |
2907 | mode->vdisplay, mode->vsync_start, | |
2908 | mode->vsync_end, mode->vtotal, | |
2909 | mode->type, mode->flags); | |
2910 | } | |
2911 | ||
2912 | static void intel_encoder_info(struct seq_file *m, | |
2913 | struct intel_crtc *intel_crtc, | |
2914 | struct intel_encoder *intel_encoder) | |
2915 | { | |
36cdd013 DW |
2916 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2917 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2918 | struct drm_crtc *crtc = &intel_crtc->base; |
2919 | struct intel_connector *intel_connector; | |
2920 | struct drm_encoder *encoder; | |
2921 | ||
2922 | encoder = &intel_encoder->base; | |
2923 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2924 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2925 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2926 | struct drm_connector *connector = &intel_connector->base; | |
2927 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2928 | connector->base.id, | |
c23cc417 | 2929 | connector->name, |
53f5e3ca JB |
2930 | drm_get_connector_status_name(connector->status)); |
2931 | if (connector->status == connector_status_connected) { | |
2932 | struct drm_display_mode *mode = &crtc->mode; | |
2933 | seq_printf(m, ", mode:\n"); | |
2934 | intel_seq_print_mode(m, 2, mode); | |
2935 | } else { | |
2936 | seq_putc(m, '\n'); | |
2937 | } | |
2938 | } | |
2939 | } | |
2940 | ||
2941 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2942 | { | |
36cdd013 DW |
2943 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2944 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2945 | struct drm_crtc *crtc = &intel_crtc->base; |
2946 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2947 | struct drm_plane_state *plane_state = crtc->primary->state; |
2948 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2949 | |
23a48d53 | 2950 | if (fb) |
5aa8a937 | 2951 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2952 | fb->base.id, plane_state->src_x >> 16, |
2953 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2954 | else |
2955 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2956 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2957 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2958 | } | |
2959 | ||
2960 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2961 | { | |
2962 | struct drm_display_mode *mode = panel->fixed_mode; | |
2963 | ||
2964 | seq_printf(m, "\tfixed mode:\n"); | |
2965 | intel_seq_print_mode(m, 2, mode); | |
2966 | } | |
2967 | ||
2968 | static void intel_dp_info(struct seq_file *m, | |
2969 | struct intel_connector *intel_connector) | |
2970 | { | |
2971 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2972 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2973 | ||
2974 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2975 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2976 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2977 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2978 | |
2979 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2980 | &intel_dp->aux); | |
53f5e3ca JB |
2981 | } |
2982 | ||
9a148a96 LY |
2983 | static void intel_dp_mst_info(struct seq_file *m, |
2984 | struct intel_connector *intel_connector) | |
2985 | { | |
2986 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2987 | struct intel_dp_mst_encoder *intel_mst = | |
2988 | enc_to_mst(&intel_encoder->base); | |
2989 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2990 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2991 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2992 | intel_connector->port); | |
2993 | ||
2994 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2995 | } | |
2996 | ||
53f5e3ca JB |
2997 | static void intel_hdmi_info(struct seq_file *m, |
2998 | struct intel_connector *intel_connector) | |
2999 | { | |
3000 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
3001 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
3002 | ||
742f491d | 3003 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
3004 | } |
3005 | ||
3006 | static void intel_lvds_info(struct seq_file *m, | |
3007 | struct intel_connector *intel_connector) | |
3008 | { | |
3009 | intel_panel_info(m, &intel_connector->panel); | |
3010 | } | |
3011 | ||
3012 | static void intel_connector_info(struct seq_file *m, | |
3013 | struct drm_connector *connector) | |
3014 | { | |
3015 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3016 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3017 | struct drm_display_mode *mode; |
53f5e3ca JB |
3018 | |
3019 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3020 | connector->base.id, connector->name, |
53f5e3ca JB |
3021 | drm_get_connector_status_name(connector->status)); |
3022 | if (connector->status == connector_status_connected) { | |
3023 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3024 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3025 | connector->display_info.width_mm, | |
3026 | connector->display_info.height_mm); | |
3027 | seq_printf(m, "\tsubpixel order: %s\n", | |
3028 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3029 | seq_printf(m, "\tCEA rev: %d\n", | |
3030 | connector->display_info.cea_rev); | |
3031 | } | |
ee648a74 ML |
3032 | |
3033 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3034 | return; | |
3035 | ||
3036 | switch (connector->connector_type) { | |
3037 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3038 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3039 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3040 | intel_dp_mst_info(m, intel_connector); | |
3041 | else | |
3042 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3043 | break; |
3044 | case DRM_MODE_CONNECTOR_LVDS: | |
3045 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3046 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3047 | break; |
3048 | case DRM_MODE_CONNECTOR_HDMIA: | |
3049 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3050 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3051 | intel_hdmi_info(m, intel_connector); | |
3052 | break; | |
3053 | default: | |
3054 | break; | |
36cd7444 | 3055 | } |
53f5e3ca | 3056 | |
f103fc7d JB |
3057 | seq_printf(m, "\tmodes:\n"); |
3058 | list_for_each_entry(mode, &connector->modes, head) | |
3059 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3060 | } |
3061 | ||
36cdd013 | 3062 | static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) |
065f2ec2 | 3063 | { |
065f2ec2 CW |
3064 | u32 state; |
3065 | ||
2a307c2e | 3066 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 3067 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3068 | else |
5efb3e28 | 3069 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3070 | |
3071 | return state; | |
3072 | } | |
3073 | ||
36cdd013 DW |
3074 | static bool cursor_position(struct drm_i915_private *dev_priv, |
3075 | int pipe, int *x, int *y) | |
065f2ec2 | 3076 | { |
065f2ec2 CW |
3077 | u32 pos; |
3078 | ||
5efb3e28 | 3079 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3080 | |
3081 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3082 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3083 | *x = -*x; | |
3084 | ||
3085 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3086 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3087 | *y = -*y; | |
3088 | ||
36cdd013 | 3089 | return cursor_active(dev_priv, pipe); |
065f2ec2 CW |
3090 | } |
3091 | ||
3abc4e09 RF |
3092 | static const char *plane_type(enum drm_plane_type type) |
3093 | { | |
3094 | switch (type) { | |
3095 | case DRM_PLANE_TYPE_OVERLAY: | |
3096 | return "OVL"; | |
3097 | case DRM_PLANE_TYPE_PRIMARY: | |
3098 | return "PRI"; | |
3099 | case DRM_PLANE_TYPE_CURSOR: | |
3100 | return "CUR"; | |
3101 | /* | |
3102 | * Deliberately omitting default: to generate compiler warnings | |
3103 | * when a new drm_plane_type gets added. | |
3104 | */ | |
3105 | } | |
3106 | ||
3107 | return "unknown"; | |
3108 | } | |
3109 | ||
3110 | static const char *plane_rotation(unsigned int rotation) | |
3111 | { | |
3112 | static char buf[48]; | |
3113 | /* | |
3114 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3115 | * will print them all to visualize if the values are misused | |
3116 | */ | |
3117 | snprintf(buf, sizeof(buf), | |
3118 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3119 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3120 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3121 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3122 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3123 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3124 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3125 | rotation); |
3126 | ||
3127 | return buf; | |
3128 | } | |
3129 | ||
3130 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3131 | { | |
36cdd013 DW |
3132 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3133 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3134 | struct intel_plane *intel_plane; |
3135 | ||
3136 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3137 | struct drm_plane_state *state; | |
3138 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3139 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3140 | |
3141 | if (!plane->state) { | |
3142 | seq_puts(m, "plane->state is NULL!\n"); | |
3143 | continue; | |
3144 | } | |
3145 | ||
3146 | state = plane->state; | |
3147 | ||
90844f00 | 3148 | if (state->fb) { |
438b74a5 VS |
3149 | drm_get_format_name(state->fb->format->format, |
3150 | &format_name); | |
90844f00 | 3151 | } else { |
b3c11ac2 | 3152 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3153 | } |
3154 | ||
3abc4e09 RF |
3155 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3156 | plane->base.id, | |
3157 | plane_type(intel_plane->base.type), | |
3158 | state->crtc_x, state->crtc_y, | |
3159 | state->crtc_w, state->crtc_h, | |
3160 | (state->src_x >> 16), | |
3161 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3162 | (state->src_y >> 16), | |
3163 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3164 | (state->src_w >> 16), | |
3165 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3166 | (state->src_h >> 16), | |
3167 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3168 | format_name.str, |
3abc4e09 RF |
3169 | plane_rotation(state->rotation)); |
3170 | } | |
3171 | } | |
3172 | ||
3173 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3174 | { | |
3175 | struct intel_crtc_state *pipe_config; | |
3176 | int num_scalers = intel_crtc->num_scalers; | |
3177 | int i; | |
3178 | ||
3179 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3180 | ||
3181 | /* Not all platformas have a scaler */ | |
3182 | if (num_scalers) { | |
3183 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3184 | num_scalers, | |
3185 | pipe_config->scaler_state.scaler_users, | |
3186 | pipe_config->scaler_state.scaler_id); | |
3187 | ||
58415918 | 3188 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3189 | struct intel_scaler *sc = |
3190 | &pipe_config->scaler_state.scalers[i]; | |
3191 | ||
3192 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3193 | i, yesno(sc->in_use), sc->mode); | |
3194 | } | |
3195 | seq_puts(m, "\n"); | |
3196 | } else { | |
3197 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3198 | } | |
3199 | } | |
3200 | ||
53f5e3ca JB |
3201 | static int i915_display_info(struct seq_file *m, void *unused) |
3202 | { | |
36cdd013 DW |
3203 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3204 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3205 | struct intel_crtc *crtc; |
53f5e3ca JB |
3206 | struct drm_connector *connector; |
3207 | ||
b0e5ddf3 | 3208 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3209 | drm_modeset_lock_all(dev); |
3210 | seq_printf(m, "CRTC info\n"); | |
3211 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3212 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3213 | bool active; |
f77076c9 | 3214 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3215 | int x, y; |
53f5e3ca | 3216 | |
f77076c9 ML |
3217 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3218 | ||
3abc4e09 | 3219 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3220 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3221 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3222 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3223 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3224 | ||
f77076c9 | 3225 | if (pipe_config->base.active) { |
065f2ec2 CW |
3226 | intel_crtc_info(m, crtc); |
3227 | ||
36cdd013 | 3228 | active = cursor_position(dev_priv, crtc->pipe, &x, &y); |
57127efa | 3229 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3230 | yesno(crtc->cursor_base), |
3dd512fb MR |
3231 | x, y, crtc->base.cursor->state->crtc_w, |
3232 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3233 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3234 | intel_scaler_info(m, crtc); |
3235 | intel_plane_info(m, crtc); | |
a23dc658 | 3236 | } |
cace841c DV |
3237 | |
3238 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3239 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3240 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3241 | } |
3242 | ||
3243 | seq_printf(m, "\n"); | |
3244 | seq_printf(m, "Connector info\n"); | |
3245 | seq_printf(m, "--------------\n"); | |
3246 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3247 | intel_connector_info(m, connector); | |
3248 | } | |
3249 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3250 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3251 | |
3252 | return 0; | |
3253 | } | |
3254 | ||
1b36595f CW |
3255 | static int i915_engine_info(struct seq_file *m, void *unused) |
3256 | { | |
3257 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3258 | struct intel_engine_cs *engine; | |
3b3f1650 | 3259 | enum intel_engine_id id; |
1b36595f | 3260 | |
9c870d03 CW |
3261 | intel_runtime_pm_get(dev_priv); |
3262 | ||
3b3f1650 | 3263 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3264 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3265 | struct drm_i915_gem_request *rq; | |
3266 | struct rb_node *rb; | |
3267 | u64 addr; | |
3268 | ||
3269 | seq_printf(m, "%s\n", engine->name); | |
3fe3b030 | 3270 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n", |
1b36595f | 3271 | intel_engine_get_seqno(engine), |
cb399eab | 3272 | intel_engine_last_submit(engine), |
1b36595f | 3273 | engine->hangcheck.seqno, |
3fe3b030 | 3274 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp)); |
1b36595f CW |
3275 | |
3276 | rcu_read_lock(); | |
3277 | ||
3278 | seq_printf(m, "\tRequests:\n"); | |
3279 | ||
73cb9701 CW |
3280 | rq = list_first_entry(&engine->timeline->requests, |
3281 | struct drm_i915_gem_request, link); | |
3282 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3283 | print_request(m, rq, "\t\tfirst "); |
3284 | ||
73cb9701 CW |
3285 | rq = list_last_entry(&engine->timeline->requests, |
3286 | struct drm_i915_gem_request, link); | |
3287 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3288 | print_request(m, rq, "\t\tlast "); |
3289 | ||
3290 | rq = i915_gem_find_active_request(engine); | |
3291 | if (rq) { | |
3292 | print_request(m, rq, "\t\tactive "); | |
3293 | seq_printf(m, | |
3294 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3295 | rq->head, rq->postfix, rq->tail, | |
3296 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3297 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3298 | } | |
3299 | ||
3300 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3301 | I915_READ(RING_START(engine->mmio_base)), | |
3302 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3303 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3304 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3305 | rq ? rq->ring->head : 0); | |
3306 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3307 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3308 | rq ? rq->ring->tail : 0); | |
3309 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3310 | I915_READ(RING_CTL(engine->mmio_base)), | |
3311 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3312 | ||
3313 | rcu_read_unlock(); | |
3314 | ||
3315 | addr = intel_engine_get_active_head(engine); | |
3316 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3317 | upper_32_bits(addr), lower_32_bits(addr)); | |
3318 | addr = intel_engine_get_last_batch_head(engine); | |
3319 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3320 | upper_32_bits(addr), lower_32_bits(addr)); | |
3321 | ||
3322 | if (i915.enable_execlists) { | |
3323 | u32 ptr, read, write; | |
20311bd3 | 3324 | struct rb_node *rb; |
1b36595f CW |
3325 | |
3326 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3327 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3328 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3329 | ||
3330 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3331 | read = GEN8_CSB_READ_PTR(ptr); | |
3332 | write = GEN8_CSB_WRITE_PTR(ptr); | |
3333 | seq_printf(m, "\tExeclist CSB read %d, write %d\n", | |
3334 | read, write); | |
3335 | if (read >= GEN8_CSB_ENTRIES) | |
3336 | read = 0; | |
3337 | if (write >= GEN8_CSB_ENTRIES) | |
3338 | write = 0; | |
3339 | if (read > write) | |
3340 | write += GEN8_CSB_ENTRIES; | |
3341 | while (read < write) { | |
3342 | unsigned int idx = ++read % GEN8_CSB_ENTRIES; | |
3343 | ||
3344 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", | |
3345 | idx, | |
3346 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3347 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3348 | } | |
3349 | ||
3350 | rcu_read_lock(); | |
3351 | rq = READ_ONCE(engine->execlist_port[0].request); | |
816ee798 CW |
3352 | if (rq) { |
3353 | seq_printf(m, "\t\tELSP[0] count=%d, ", | |
3354 | engine->execlist_port[0].count); | |
3355 | print_request(m, rq, "rq: "); | |
3356 | } else { | |
1b36595f | 3357 | seq_printf(m, "\t\tELSP[0] idle\n"); |
816ee798 | 3358 | } |
1b36595f | 3359 | rq = READ_ONCE(engine->execlist_port[1].request); |
816ee798 CW |
3360 | if (rq) { |
3361 | seq_printf(m, "\t\tELSP[1] count=%d, ", | |
3362 | engine->execlist_port[1].count); | |
3363 | print_request(m, rq, "rq: "); | |
3364 | } else { | |
1b36595f | 3365 | seq_printf(m, "\t\tELSP[1] idle\n"); |
816ee798 | 3366 | } |
1b36595f | 3367 | rcu_read_unlock(); |
c8247c06 | 3368 | |
663f71e7 | 3369 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
3370 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { |
3371 | rq = rb_entry(rb, typeof(*rq), priotree.node); | |
c8247c06 CW |
3372 | print_request(m, rq, "\t\tQ "); |
3373 | } | |
663f71e7 | 3374 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3375 | } else if (INTEL_GEN(dev_priv) > 6) { |
3376 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3377 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3378 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3379 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3380 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3381 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3382 | } | |
3383 | ||
f6168e33 | 3384 | spin_lock_irq(&b->lock); |
1b36595f | 3385 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3386 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3387 | |
3388 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3389 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3390 | } | |
f6168e33 | 3391 | spin_unlock_irq(&b->lock); |
1b36595f CW |
3392 | |
3393 | seq_puts(m, "\n"); | |
3394 | } | |
3395 | ||
9c870d03 CW |
3396 | intel_runtime_pm_put(dev_priv); |
3397 | ||
1b36595f CW |
3398 | return 0; |
3399 | } | |
3400 | ||
e04934cf BW |
3401 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3402 | { | |
36cdd013 DW |
3403 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3404 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3405 | struct intel_engine_cs *engine; |
36cdd013 | 3406 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3407 | enum intel_engine_id id; |
3408 | int j, ret; | |
e04934cf | 3409 | |
39df9190 | 3410 | if (!i915.semaphores) { |
e04934cf BW |
3411 | seq_puts(m, "Semaphores are disabled\n"); |
3412 | return 0; | |
3413 | } | |
3414 | ||
3415 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3416 | if (ret) | |
3417 | return ret; | |
03872064 | 3418 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3419 | |
36cdd013 | 3420 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3421 | struct page *page; |
3422 | uint64_t *seqno; | |
3423 | ||
51d545d0 | 3424 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3425 | |
3426 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3427 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3428 | uint64_t offset; |
3429 | ||
e2f80391 | 3430 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3431 | |
3432 | seq_puts(m, " Last signal:"); | |
3433 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3434 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3435 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3436 | seqno[offset], offset * 8); | |
3437 | } | |
3438 | seq_putc(m, '\n'); | |
3439 | ||
3440 | seq_puts(m, " Last wait: "); | |
3441 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3442 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3443 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3444 | seqno[offset], offset * 8); | |
3445 | } | |
3446 | seq_putc(m, '\n'); | |
3447 | ||
3448 | } | |
3449 | kunmap_atomic(seqno); | |
3450 | } else { | |
3451 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3452 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3453 | for (j = 0; j < num_rings; j++) |
3454 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3455 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3456 | seq_putc(m, '\n'); |
3457 | } | |
3458 | ||
03872064 | 3459 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3460 | mutex_unlock(&dev->struct_mutex); |
3461 | return 0; | |
3462 | } | |
3463 | ||
728e29d7 DV |
3464 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3465 | { | |
36cdd013 DW |
3466 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3467 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3468 | int i; |
3469 | ||
3470 | drm_modeset_lock_all(dev); | |
3471 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3472 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3473 | ||
3474 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3475 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3476 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3477 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3478 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3479 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3480 | pll->state.hw_state.dpll_md); |
3481 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3482 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3483 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3484 | } |
3485 | drm_modeset_unlock_all(dev); | |
3486 | ||
3487 | return 0; | |
3488 | } | |
3489 | ||
1ed1ef9d | 3490 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3491 | { |
3492 | int i; | |
3493 | int ret; | |
e2f80391 | 3494 | struct intel_engine_cs *engine; |
36cdd013 DW |
3495 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3496 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3497 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3498 | enum intel_engine_id id; |
888b5995 | 3499 | |
888b5995 AS |
3500 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3501 | if (ret) | |
3502 | return ret; | |
3503 | ||
3504 | intel_runtime_pm_get(dev_priv); | |
3505 | ||
33136b06 | 3506 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3507 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3508 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3509 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3510 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3511 | i915_reg_t addr; |
3512 | u32 mask, value, read; | |
2fa60f6d | 3513 | bool ok; |
888b5995 | 3514 | |
33136b06 AS |
3515 | addr = workarounds->reg[i].addr; |
3516 | mask = workarounds->reg[i].mask; | |
3517 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3518 | read = I915_READ(addr); |
3519 | ok = (value & mask) == (read & mask); | |
3520 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3521 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3522 | } |
3523 | ||
3524 | intel_runtime_pm_put(dev_priv); | |
3525 | mutex_unlock(&dev->struct_mutex); | |
3526 | ||
3527 | return 0; | |
3528 | } | |
3529 | ||
c5511e44 DL |
3530 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3531 | { | |
36cdd013 DW |
3532 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3533 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3534 | struct skl_ddb_allocation *ddb; |
3535 | struct skl_ddb_entry *entry; | |
3536 | enum pipe pipe; | |
3537 | int plane; | |
3538 | ||
36cdd013 | 3539 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3540 | return 0; |
3541 | ||
c5511e44 DL |
3542 | drm_modeset_lock_all(dev); |
3543 | ||
3544 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3545 | ||
3546 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3547 | ||
3548 | for_each_pipe(dev_priv, pipe) { | |
3549 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3550 | ||
8b364b41 | 3551 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3552 | entry = &ddb->plane[pipe][plane]; |
3553 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3554 | entry->start, entry->end, | |
3555 | skl_ddb_entry_size(entry)); | |
3556 | } | |
3557 | ||
4969d33e | 3558 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3559 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3560 | entry->end, skl_ddb_entry_size(entry)); | |
3561 | } | |
3562 | ||
3563 | drm_modeset_unlock_all(dev); | |
3564 | ||
3565 | return 0; | |
3566 | } | |
3567 | ||
a54746e3 | 3568 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3569 | struct drm_device *dev, |
3570 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3571 | { |
fac5e23e | 3572 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3573 | struct i915_drrs *drrs = &dev_priv->drrs; |
3574 | int vrefresh = 0; | |
26875fe5 | 3575 | struct drm_connector *connector; |
a54746e3 | 3576 | |
26875fe5 ML |
3577 | drm_for_each_connector(connector, dev) { |
3578 | if (connector->state->crtc != &intel_crtc->base) | |
3579 | continue; | |
3580 | ||
3581 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3582 | } |
3583 | ||
3584 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3585 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3586 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3587 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3588 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3589 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3590 | else | |
3591 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3592 | ||
3593 | seq_puts(m, "\n\n"); | |
3594 | ||
f77076c9 | 3595 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3596 | struct intel_panel *panel; |
3597 | ||
3598 | mutex_lock(&drrs->mutex); | |
3599 | /* DRRS Supported */ | |
3600 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3601 | ||
3602 | /* disable_drrs() will make drrs->dp NULL */ | |
3603 | if (!drrs->dp) { | |
3604 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3605 | mutex_unlock(&drrs->mutex); | |
3606 | return; | |
3607 | } | |
3608 | ||
3609 | panel = &drrs->dp->attached_connector->panel; | |
3610 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3611 | drrs->busy_frontbuffer_bits); | |
3612 | ||
3613 | seq_puts(m, "\n\t\t"); | |
3614 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3615 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3616 | vrefresh = panel->fixed_mode->vrefresh; | |
3617 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3618 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3619 | vrefresh = panel->downclock_mode->vrefresh; | |
3620 | } else { | |
3621 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3622 | drrs->refresh_rate_type); | |
3623 | mutex_unlock(&drrs->mutex); | |
3624 | return; | |
3625 | } | |
3626 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3627 | ||
3628 | seq_puts(m, "\n\t\t"); | |
3629 | mutex_unlock(&drrs->mutex); | |
3630 | } else { | |
3631 | /* DRRS not supported. Print the VBT parameter*/ | |
3632 | seq_puts(m, "\tDRRS Supported : No"); | |
3633 | } | |
3634 | seq_puts(m, "\n"); | |
3635 | } | |
3636 | ||
3637 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3638 | { | |
36cdd013 DW |
3639 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3640 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3641 | struct intel_crtc *intel_crtc; |
3642 | int active_crtc_cnt = 0; | |
3643 | ||
26875fe5 | 3644 | drm_modeset_lock_all(dev); |
a54746e3 | 3645 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3646 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3647 | active_crtc_cnt++; |
3648 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3649 | ||
3650 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3651 | } | |
a54746e3 | 3652 | } |
26875fe5 | 3653 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3654 | |
3655 | if (!active_crtc_cnt) | |
3656 | seq_puts(m, "No active crtc found\n"); | |
3657 | ||
3658 | return 0; | |
3659 | } | |
3660 | ||
11bed958 DA |
3661 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3662 | { | |
36cdd013 DW |
3663 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3664 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3665 | struct intel_encoder *intel_encoder; |
3666 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3667 | struct drm_connector *connector; |
3668 | ||
11bed958 | 3669 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3670 | drm_for_each_connector(connector, dev) { |
3671 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3672 | continue; |
b6dabe3b ML |
3673 | |
3674 | intel_encoder = intel_attached_encoder(connector); | |
3675 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3676 | continue; | |
3677 | ||
3678 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3679 | if (!intel_dig_port->dp.can_mst) |
3680 | continue; | |
b6dabe3b | 3681 | |
40ae80cc JB |
3682 | seq_printf(m, "MST Source Port %c\n", |
3683 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3684 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3685 | } | |
3686 | drm_modeset_unlock_all(dev); | |
3687 | return 0; | |
3688 | } | |
3689 | ||
eb3394fa | 3690 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3691 | const char __user *ubuf, |
3692 | size_t len, loff_t *offp) | |
eb3394fa TP |
3693 | { |
3694 | char *input_buffer; | |
3695 | int status = 0; | |
eb3394fa TP |
3696 | struct drm_device *dev; |
3697 | struct drm_connector *connector; | |
3698 | struct list_head *connector_list; | |
3699 | struct intel_dp *intel_dp; | |
3700 | int val = 0; | |
3701 | ||
9aaffa34 | 3702 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3703 | |
eb3394fa TP |
3704 | connector_list = &dev->mode_config.connector_list; |
3705 | ||
3706 | if (len == 0) | |
3707 | return 0; | |
3708 | ||
3709 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
3710 | if (!input_buffer) | |
3711 | return -ENOMEM; | |
3712 | ||
3713 | if (copy_from_user(input_buffer, ubuf, len)) { | |
3714 | status = -EFAULT; | |
3715 | goto out; | |
3716 | } | |
3717 | ||
3718 | input_buffer[len] = '\0'; | |
3719 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
3720 | ||
3721 | list_for_each_entry(connector, connector_list, head) { | |
eb3394fa TP |
3722 | if (connector->connector_type != |
3723 | DRM_MODE_CONNECTOR_DisplayPort) | |
3724 | continue; | |
3725 | ||
b8bb08ec | 3726 | if (connector->status == connector_status_connected && |
eb3394fa TP |
3727 | connector->encoder != NULL) { |
3728 | intel_dp = enc_to_intel_dp(connector->encoder); | |
3729 | status = kstrtoint(input_buffer, 10, &val); | |
3730 | if (status < 0) | |
3731 | goto out; | |
3732 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
3733 | /* To prevent erroneous activation of the compliance | |
3734 | * testing code, only accept an actual value of 1 here | |
3735 | */ | |
3736 | if (val == 1) | |
c1617abc | 3737 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3738 | else |
c1617abc | 3739 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3740 | } |
3741 | } | |
3742 | out: | |
3743 | kfree(input_buffer); | |
3744 | if (status < 0) | |
3745 | return status; | |
3746 | ||
3747 | *offp += len; | |
3748 | return len; | |
3749 | } | |
3750 | ||
3751 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3752 | { | |
3753 | struct drm_device *dev = m->private; | |
3754 | struct drm_connector *connector; | |
3755 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3756 | struct intel_dp *intel_dp; | |
3757 | ||
eb3394fa | 3758 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3759 | if (connector->connector_type != |
3760 | DRM_MODE_CONNECTOR_DisplayPort) | |
3761 | continue; | |
3762 | ||
3763 | if (connector->status == connector_status_connected && | |
3764 | connector->encoder != NULL) { | |
3765 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3766 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3767 | seq_puts(m, "1"); |
3768 | else | |
3769 | seq_puts(m, "0"); | |
3770 | } else | |
3771 | seq_puts(m, "0"); | |
3772 | } | |
3773 | ||
3774 | return 0; | |
3775 | } | |
3776 | ||
3777 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3778 | struct file *file) |
eb3394fa | 3779 | { |
36cdd013 | 3780 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3781 | |
36cdd013 DW |
3782 | return single_open(file, i915_displayport_test_active_show, |
3783 | &dev_priv->drm); | |
eb3394fa TP |
3784 | } |
3785 | ||
3786 | static const struct file_operations i915_displayport_test_active_fops = { | |
3787 | .owner = THIS_MODULE, | |
3788 | .open = i915_displayport_test_active_open, | |
3789 | .read = seq_read, | |
3790 | .llseek = seq_lseek, | |
3791 | .release = single_release, | |
3792 | .write = i915_displayport_test_active_write | |
3793 | }; | |
3794 | ||
3795 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3796 | { | |
3797 | struct drm_device *dev = m->private; | |
3798 | struct drm_connector *connector; | |
3799 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3800 | struct intel_dp *intel_dp; | |
3801 | ||
eb3394fa | 3802 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3803 | if (connector->connector_type != |
3804 | DRM_MODE_CONNECTOR_DisplayPort) | |
3805 | continue; | |
3806 | ||
3807 | if (connector->status == connector_status_connected && | |
3808 | connector->encoder != NULL) { | |
3809 | intel_dp = enc_to_intel_dp(connector->encoder); | |
b48a5ba9 MN |
3810 | if (intel_dp->compliance.test_type == |
3811 | DP_TEST_LINK_EDID_READ) | |
3812 | seq_printf(m, "%lx", | |
3813 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3814 | else if (intel_dp->compliance.test_type == |
3815 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3816 | seq_printf(m, "hdisplay: %d\n", | |
3817 | intel_dp->compliance.test_data.hdisplay); | |
3818 | seq_printf(m, "vdisplay: %d\n", | |
3819 | intel_dp->compliance.test_data.vdisplay); | |
3820 | seq_printf(m, "bpc: %u\n", | |
3821 | intel_dp->compliance.test_data.bpc); | |
3822 | } | |
eb3394fa TP |
3823 | } else |
3824 | seq_puts(m, "0"); | |
3825 | } | |
3826 | ||
3827 | return 0; | |
3828 | } | |
3829 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3830 | struct file *file) |
eb3394fa | 3831 | { |
36cdd013 | 3832 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3833 | |
36cdd013 DW |
3834 | return single_open(file, i915_displayport_test_data_show, |
3835 | &dev_priv->drm); | |
eb3394fa TP |
3836 | } |
3837 | ||
3838 | static const struct file_operations i915_displayport_test_data_fops = { | |
3839 | .owner = THIS_MODULE, | |
3840 | .open = i915_displayport_test_data_open, | |
3841 | .read = seq_read, | |
3842 | .llseek = seq_lseek, | |
3843 | .release = single_release | |
3844 | }; | |
3845 | ||
3846 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3847 | { | |
3848 | struct drm_device *dev = m->private; | |
3849 | struct drm_connector *connector; | |
3850 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
3851 | struct intel_dp *intel_dp; | |
3852 | ||
eb3394fa | 3853 | list_for_each_entry(connector, connector_list, head) { |
eb3394fa TP |
3854 | if (connector->connector_type != |
3855 | DRM_MODE_CONNECTOR_DisplayPort) | |
3856 | continue; | |
3857 | ||
3858 | if (connector->status == connector_status_connected && | |
3859 | connector->encoder != NULL) { | |
3860 | intel_dp = enc_to_intel_dp(connector->encoder); | |
c1617abc | 3861 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3862 | } else |
3863 | seq_puts(m, "0"); | |
3864 | } | |
3865 | ||
3866 | return 0; | |
3867 | } | |
3868 | ||
3869 | static int i915_displayport_test_type_open(struct inode *inode, | |
3870 | struct file *file) | |
3871 | { | |
36cdd013 | 3872 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3873 | |
36cdd013 DW |
3874 | return single_open(file, i915_displayport_test_type_show, |
3875 | &dev_priv->drm); | |
eb3394fa TP |
3876 | } |
3877 | ||
3878 | static const struct file_operations i915_displayport_test_type_fops = { | |
3879 | .owner = THIS_MODULE, | |
3880 | .open = i915_displayport_test_type_open, | |
3881 | .read = seq_read, | |
3882 | .llseek = seq_lseek, | |
3883 | .release = single_release | |
3884 | }; | |
3885 | ||
97e94b22 | 3886 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3887 | { |
36cdd013 DW |
3888 | struct drm_i915_private *dev_priv = m->private; |
3889 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3890 | int level; |
de38b95c VS |
3891 | int num_levels; |
3892 | ||
36cdd013 | 3893 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3894 | num_levels = 3; |
36cdd013 | 3895 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
3896 | num_levels = 1; |
3897 | else | |
5db94019 | 3898 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3899 | |
3900 | drm_modeset_lock_all(dev); | |
3901 | ||
3902 | for (level = 0; level < num_levels; level++) { | |
3903 | unsigned int latency = wm[level]; | |
3904 | ||
97e94b22 DL |
3905 | /* |
3906 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3907 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3908 | */ |
36cdd013 DW |
3909 | if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || |
3910 | IS_CHERRYVIEW(dev_priv)) | |
97e94b22 DL |
3911 | latency *= 10; |
3912 | else if (level > 0) | |
369a1342 VS |
3913 | latency *= 5; |
3914 | ||
3915 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3916 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3917 | } |
3918 | ||
3919 | drm_modeset_unlock_all(dev); | |
3920 | } | |
3921 | ||
3922 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3923 | { | |
36cdd013 | 3924 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3925 | const uint16_t *latencies; |
3926 | ||
36cdd013 | 3927 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3928 | latencies = dev_priv->wm.skl_latency; |
3929 | else | |
36cdd013 | 3930 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3931 | |
97e94b22 | 3932 | wm_latency_show(m, latencies); |
369a1342 VS |
3933 | |
3934 | return 0; | |
3935 | } | |
3936 | ||
3937 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3938 | { | |
36cdd013 | 3939 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3940 | const uint16_t *latencies; |
3941 | ||
36cdd013 | 3942 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3943 | latencies = dev_priv->wm.skl_latency; |
3944 | else | |
36cdd013 | 3945 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3946 | |
97e94b22 | 3947 | wm_latency_show(m, latencies); |
369a1342 VS |
3948 | |
3949 | return 0; | |
3950 | } | |
3951 | ||
3952 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3953 | { | |
36cdd013 | 3954 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3955 | const uint16_t *latencies; |
3956 | ||
36cdd013 | 3957 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3958 | latencies = dev_priv->wm.skl_latency; |
3959 | else | |
36cdd013 | 3960 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3961 | |
97e94b22 | 3962 | wm_latency_show(m, latencies); |
369a1342 VS |
3963 | |
3964 | return 0; | |
3965 | } | |
3966 | ||
3967 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3968 | { | |
36cdd013 | 3969 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3970 | |
36cdd013 | 3971 | if (INTEL_GEN(dev_priv) < 5) |
369a1342 VS |
3972 | return -ENODEV; |
3973 | ||
36cdd013 | 3974 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3975 | } |
3976 | ||
3977 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3978 | { | |
36cdd013 | 3979 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3980 | |
36cdd013 | 3981 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3982 | return -ENODEV; |
3983 | ||
36cdd013 | 3984 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3985 | } |
3986 | ||
3987 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3988 | { | |
36cdd013 | 3989 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3990 | |
36cdd013 | 3991 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3992 | return -ENODEV; |
3993 | ||
36cdd013 | 3994 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3995 | } |
3996 | ||
3997 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3998 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3999 | { |
4000 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4001 | struct drm_i915_private *dev_priv = m->private; |
4002 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4003 | uint16_t new[8] = { 0 }; |
de38b95c | 4004 | int num_levels; |
369a1342 VS |
4005 | int level; |
4006 | int ret; | |
4007 | char tmp[32]; | |
4008 | ||
36cdd013 | 4009 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4010 | num_levels = 3; |
36cdd013 | 4011 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c VS |
4012 | num_levels = 1; |
4013 | else | |
5db94019 | 4014 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4015 | |
369a1342 VS |
4016 | if (len >= sizeof(tmp)) |
4017 | return -EINVAL; | |
4018 | ||
4019 | if (copy_from_user(tmp, ubuf, len)) | |
4020 | return -EFAULT; | |
4021 | ||
4022 | tmp[len] = '\0'; | |
4023 | ||
97e94b22 DL |
4024 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4025 | &new[0], &new[1], &new[2], &new[3], | |
4026 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4027 | if (ret != num_levels) |
4028 | return -EINVAL; | |
4029 | ||
4030 | drm_modeset_lock_all(dev); | |
4031 | ||
4032 | for (level = 0; level < num_levels; level++) | |
4033 | wm[level] = new[level]; | |
4034 | ||
4035 | drm_modeset_unlock_all(dev); | |
4036 | ||
4037 | return len; | |
4038 | } | |
4039 | ||
4040 | ||
4041 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4042 | size_t len, loff_t *offp) | |
4043 | { | |
4044 | struct seq_file *m = file->private_data; | |
36cdd013 | 4045 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4046 | uint16_t *latencies; |
369a1342 | 4047 | |
36cdd013 | 4048 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4049 | latencies = dev_priv->wm.skl_latency; |
4050 | else | |
36cdd013 | 4051 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4052 | |
4053 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4054 | } |
4055 | ||
4056 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4057 | size_t len, loff_t *offp) | |
4058 | { | |
4059 | struct seq_file *m = file->private_data; | |
36cdd013 | 4060 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4061 | uint16_t *latencies; |
369a1342 | 4062 | |
36cdd013 | 4063 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4064 | latencies = dev_priv->wm.skl_latency; |
4065 | else | |
36cdd013 | 4066 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4067 | |
4068 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4069 | } |
4070 | ||
4071 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4072 | size_t len, loff_t *offp) | |
4073 | { | |
4074 | struct seq_file *m = file->private_data; | |
36cdd013 | 4075 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4076 | uint16_t *latencies; |
4077 | ||
36cdd013 | 4078 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4079 | latencies = dev_priv->wm.skl_latency; |
4080 | else | |
36cdd013 | 4081 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4082 | |
97e94b22 | 4083 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4084 | } |
4085 | ||
4086 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4087 | .owner = THIS_MODULE, | |
4088 | .open = pri_wm_latency_open, | |
4089 | .read = seq_read, | |
4090 | .llseek = seq_lseek, | |
4091 | .release = single_release, | |
4092 | .write = pri_wm_latency_write | |
4093 | }; | |
4094 | ||
4095 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4096 | .owner = THIS_MODULE, | |
4097 | .open = spr_wm_latency_open, | |
4098 | .read = seq_read, | |
4099 | .llseek = seq_lseek, | |
4100 | .release = single_release, | |
4101 | .write = spr_wm_latency_write | |
4102 | }; | |
4103 | ||
4104 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4105 | .owner = THIS_MODULE, | |
4106 | .open = cur_wm_latency_open, | |
4107 | .read = seq_read, | |
4108 | .llseek = seq_lseek, | |
4109 | .release = single_release, | |
4110 | .write = cur_wm_latency_write | |
4111 | }; | |
4112 | ||
647416f9 KC |
4113 | static int |
4114 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4115 | { |
36cdd013 | 4116 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4117 | |
d98c52cf | 4118 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4119 | |
647416f9 | 4120 | return 0; |
f3cd474b CW |
4121 | } |
4122 | ||
647416f9 KC |
4123 | static int |
4124 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4125 | { |
36cdd013 | 4126 | struct drm_i915_private *dev_priv = data; |
d46c0517 | 4127 | |
b8d24a06 MK |
4128 | /* |
4129 | * There is no safeguard against this debugfs entry colliding | |
4130 | * with the hangcheck calling same i915_handle_error() in | |
4131 | * parallel, causing an explosion. For now we assume that the | |
4132 | * test harness is responsible enough not to inject gpu hangs | |
4133 | * while it is writing to 'i915_wedged' | |
4134 | */ | |
4135 | ||
d98c52cf | 4136 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4137 | return -EAGAIN; |
4138 | ||
c033666a | 4139 | i915_handle_error(dev_priv, val, |
58174462 | 4140 | "Manually setting wedged to %llu", val); |
d46c0517 | 4141 | |
647416f9 | 4142 | return 0; |
f3cd474b CW |
4143 | } |
4144 | ||
647416f9 KC |
4145 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4146 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4147 | "%llu\n"); |
f3cd474b | 4148 | |
094f9a54 CW |
4149 | static int |
4150 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4151 | { | |
36cdd013 | 4152 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4153 | |
4154 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4155 | return 0; | |
4156 | } | |
4157 | ||
4158 | static int | |
4159 | i915_ring_missed_irq_set(void *data, u64 val) | |
4160 | { | |
36cdd013 DW |
4161 | struct drm_i915_private *dev_priv = data; |
4162 | struct drm_device *dev = &dev_priv->drm; | |
094f9a54 CW |
4163 | int ret; |
4164 | ||
4165 | /* Lock against concurrent debugfs callers */ | |
4166 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4167 | if (ret) | |
4168 | return ret; | |
4169 | dev_priv->gpu_error.missed_irq_rings = val; | |
4170 | mutex_unlock(&dev->struct_mutex); | |
4171 | ||
4172 | return 0; | |
4173 | } | |
4174 | ||
4175 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4176 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4177 | "0x%08llx\n"); | |
4178 | ||
4179 | static int | |
4180 | i915_ring_test_irq_get(void *data, u64 *val) | |
4181 | { | |
36cdd013 | 4182 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4183 | |
4184 | *val = dev_priv->gpu_error.test_irq_rings; | |
4185 | ||
4186 | return 0; | |
4187 | } | |
4188 | ||
4189 | static int | |
4190 | i915_ring_test_irq_set(void *data, u64 val) | |
4191 | { | |
36cdd013 | 4192 | struct drm_i915_private *dev_priv = data; |
094f9a54 | 4193 | |
3a122c27 | 4194 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4195 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4196 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4197 | |
4198 | return 0; | |
4199 | } | |
4200 | ||
4201 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4202 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4203 | "0x%08llx\n"); | |
4204 | ||
dd624afd CW |
4205 | #define DROP_UNBOUND 0x1 |
4206 | #define DROP_BOUND 0x2 | |
4207 | #define DROP_RETIRE 0x4 | |
4208 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 CW |
4209 | #define DROP_FREED 0x10 |
4210 | #define DROP_ALL (DROP_UNBOUND | \ | |
4211 | DROP_BOUND | \ | |
4212 | DROP_RETIRE | \ | |
4213 | DROP_ACTIVE | \ | |
4214 | DROP_FREED) | |
647416f9 KC |
4215 | static int |
4216 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4217 | { |
647416f9 | 4218 | *val = DROP_ALL; |
dd624afd | 4219 | |
647416f9 | 4220 | return 0; |
dd624afd CW |
4221 | } |
4222 | ||
647416f9 KC |
4223 | static int |
4224 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4225 | { |
36cdd013 DW |
4226 | struct drm_i915_private *dev_priv = data; |
4227 | struct drm_device *dev = &dev_priv->drm; | |
647416f9 | 4228 | int ret; |
dd624afd | 4229 | |
2f9fe5ff | 4230 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4231 | |
4232 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4233 | * on ioctls on -EAGAIN. */ | |
4234 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4235 | if (ret) | |
4236 | return ret; | |
4237 | ||
4238 | if (val & DROP_ACTIVE) { | |
22dd3bb9 CW |
4239 | ret = i915_gem_wait_for_idle(dev_priv, |
4240 | I915_WAIT_INTERRUPTIBLE | | |
4241 | I915_WAIT_LOCKED); | |
dd624afd CW |
4242 | if (ret) |
4243 | goto unlock; | |
4244 | } | |
4245 | ||
4246 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4247 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4248 | |
21ab4e74 CW |
4249 | if (val & DROP_BOUND) |
4250 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4251 | |
21ab4e74 CW |
4252 | if (val & DROP_UNBOUND) |
4253 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4254 | |
4255 | unlock: | |
4256 | mutex_unlock(&dev->struct_mutex); | |
4257 | ||
fbbd37b3 CW |
4258 | if (val & DROP_FREED) { |
4259 | synchronize_rcu(); | |
bdeb9785 | 4260 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4261 | } |
4262 | ||
647416f9 | 4263 | return ret; |
dd624afd CW |
4264 | } |
4265 | ||
647416f9 KC |
4266 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4267 | i915_drop_caches_get, i915_drop_caches_set, | |
4268 | "0x%08llx\n"); | |
dd624afd | 4269 | |
647416f9 KC |
4270 | static int |
4271 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4272 | { |
36cdd013 | 4273 | struct drm_i915_private *dev_priv = data; |
004777cb | 4274 | |
36cdd013 | 4275 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4276 | return -ENODEV; |
4277 | ||
7c59a9c1 | 4278 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4279 | return 0; |
358733e9 JB |
4280 | } |
4281 | ||
647416f9 KC |
4282 | static int |
4283 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4284 | { |
36cdd013 | 4285 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4286 | u32 hw_max, hw_min; |
647416f9 | 4287 | int ret; |
004777cb | 4288 | |
36cdd013 | 4289 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4290 | return -ENODEV; |
358733e9 | 4291 | |
647416f9 | 4292 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4293 | |
4fc688ce | 4294 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4295 | if (ret) |
4296 | return ret; | |
4297 | ||
358733e9 JB |
4298 | /* |
4299 | * Turbo will still be enabled, but won't go above the set value. | |
4300 | */ | |
bc4d91f6 | 4301 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4302 | |
bc4d91f6 AG |
4303 | hw_max = dev_priv->rps.max_freq; |
4304 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4305 | |
b39fb297 | 4306 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4307 | mutex_unlock(&dev_priv->rps.hw_lock); |
4308 | return -EINVAL; | |
0a073b84 JB |
4309 | } |
4310 | ||
b39fb297 | 4311 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4312 | |
9fcee2f7 CW |
4313 | if (intel_set_rps(dev_priv, val)) |
4314 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4315 | |
4fc688ce | 4316 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4317 | |
647416f9 | 4318 | return 0; |
358733e9 JB |
4319 | } |
4320 | ||
647416f9 KC |
4321 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4322 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4323 | "%llu\n"); |
358733e9 | 4324 | |
647416f9 KC |
4325 | static int |
4326 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4327 | { |
36cdd013 | 4328 | struct drm_i915_private *dev_priv = data; |
004777cb | 4329 | |
62e1baa1 | 4330 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4331 | return -ENODEV; |
4332 | ||
7c59a9c1 | 4333 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4334 | return 0; |
1523c310 JB |
4335 | } |
4336 | ||
647416f9 KC |
4337 | static int |
4338 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4339 | { |
36cdd013 | 4340 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4341 | u32 hw_max, hw_min; |
647416f9 | 4342 | int ret; |
004777cb | 4343 | |
62e1baa1 | 4344 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4345 | return -ENODEV; |
1523c310 | 4346 | |
647416f9 | 4347 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4348 | |
4fc688ce | 4349 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4350 | if (ret) |
4351 | return ret; | |
4352 | ||
1523c310 JB |
4353 | /* |
4354 | * Turbo will still be enabled, but won't go below the set value. | |
4355 | */ | |
bc4d91f6 | 4356 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4357 | |
bc4d91f6 AG |
4358 | hw_max = dev_priv->rps.max_freq; |
4359 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4360 | |
36cdd013 DW |
4361 | if (val < hw_min || |
4362 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4363 | mutex_unlock(&dev_priv->rps.hw_lock); |
4364 | return -EINVAL; | |
0a073b84 | 4365 | } |
dd0a1aa1 | 4366 | |
b39fb297 | 4367 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4368 | |
9fcee2f7 CW |
4369 | if (intel_set_rps(dev_priv, val)) |
4370 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4371 | |
4fc688ce | 4372 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4373 | |
647416f9 | 4374 | return 0; |
1523c310 JB |
4375 | } |
4376 | ||
647416f9 KC |
4377 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4378 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4379 | "%llu\n"); |
1523c310 | 4380 | |
647416f9 KC |
4381 | static int |
4382 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4383 | { |
36cdd013 | 4384 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4385 | u32 snpcr; |
07b7ddd9 | 4386 | |
36cdd013 | 4387 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4388 | return -ENODEV; |
4389 | ||
c8c8fb33 | 4390 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4391 | |
07b7ddd9 | 4392 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4393 | |
4394 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4395 | |
647416f9 | 4396 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4397 | |
647416f9 | 4398 | return 0; |
07b7ddd9 JB |
4399 | } |
4400 | ||
647416f9 KC |
4401 | static int |
4402 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4403 | { |
36cdd013 | 4404 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4405 | u32 snpcr; |
07b7ddd9 | 4406 | |
36cdd013 | 4407 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4408 | return -ENODEV; |
4409 | ||
647416f9 | 4410 | if (val > 3) |
07b7ddd9 JB |
4411 | return -EINVAL; |
4412 | ||
c8c8fb33 | 4413 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4414 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4415 | |
4416 | /* Update the cache sharing policy here as well */ | |
4417 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4418 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4419 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4420 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4421 | ||
c8c8fb33 | 4422 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4423 | return 0; |
07b7ddd9 JB |
4424 | } |
4425 | ||
647416f9 KC |
4426 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4427 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4428 | "%llu\n"); | |
07b7ddd9 | 4429 | |
36cdd013 | 4430 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4431 | struct sseu_dev_info *sseu) |
5d39525a | 4432 | { |
0a0b457f | 4433 | int ss_max = 2; |
5d39525a JM |
4434 | int ss; |
4435 | u32 sig1[ss_max], sig2[ss_max]; | |
4436 | ||
4437 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4438 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4439 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4440 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4441 | ||
4442 | for (ss = 0; ss < ss_max; ss++) { | |
4443 | unsigned int eu_cnt; | |
4444 | ||
4445 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4446 | /* skip disabled subslice */ | |
4447 | continue; | |
4448 | ||
f08a0c92 | 4449 | sseu->slice_mask = BIT(0); |
57ec171e | 4450 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4451 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4452 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4453 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4454 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4455 | sseu->eu_total += eu_cnt; |
4456 | sseu->eu_per_subslice = max_t(unsigned int, | |
4457 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4458 | } |
5d39525a JM |
4459 | } |
4460 | ||
36cdd013 | 4461 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4462 | struct sseu_dev_info *sseu) |
5d39525a | 4463 | { |
1c046bc1 | 4464 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4465 | int s, ss; |
4466 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4467 | ||
1c046bc1 | 4468 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4469 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4470 | s_max = 1; |
4471 | ss_max = 3; | |
4472 | } | |
4473 | ||
4474 | for (s = 0; s < s_max; s++) { | |
4475 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4476 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4477 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4478 | } | |
4479 | ||
5d39525a JM |
4480 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4481 | GEN9_PGCTL_SSA_EU19_ACK | | |
4482 | GEN9_PGCTL_SSA_EU210_ACK | | |
4483 | GEN9_PGCTL_SSA_EU311_ACK; | |
4484 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4485 | GEN9_PGCTL_SSB_EU19_ACK | | |
4486 | GEN9_PGCTL_SSB_EU210_ACK | | |
4487 | GEN9_PGCTL_SSB_EU311_ACK; | |
4488 | ||
4489 | for (s = 0; s < s_max; s++) { | |
4490 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4491 | /* skip disabled slice */ | |
4492 | continue; | |
4493 | ||
f08a0c92 | 4494 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4495 | |
b976dc53 | 4496 | if (IS_GEN9_BC(dev_priv)) |
57ec171e ID |
4497 | sseu->subslice_mask = |
4498 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4499 | |
5d39525a JM |
4500 | for (ss = 0; ss < ss_max; ss++) { |
4501 | unsigned int eu_cnt; | |
4502 | ||
cc3f90f0 | 4503 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4504 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4505 | /* skip disabled subslice */ | |
4506 | continue; | |
1c046bc1 | 4507 | |
57ec171e ID |
4508 | sseu->subslice_mask |= BIT(ss); |
4509 | } | |
1c046bc1 | 4510 | |
5d39525a JM |
4511 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4512 | eu_mask[ss%2]); | |
915490d5 ID |
4513 | sseu->eu_total += eu_cnt; |
4514 | sseu->eu_per_subslice = max_t(unsigned int, | |
4515 | sseu->eu_per_subslice, | |
4516 | eu_cnt); | |
5d39525a JM |
4517 | } |
4518 | } | |
4519 | } | |
4520 | ||
36cdd013 | 4521 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4522 | struct sseu_dev_info *sseu) |
91bedd34 | 4523 | { |
91bedd34 | 4524 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4525 | int s; |
91bedd34 | 4526 | |
f08a0c92 | 4527 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4528 | |
f08a0c92 | 4529 | if (sseu->slice_mask) { |
57ec171e | 4530 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4531 | sseu->eu_per_subslice = |
4532 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4533 | sseu->eu_total = sseu->eu_per_subslice * |
4534 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4535 | |
4536 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4537 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4538 | u8 subslice_7eu = |
4539 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4540 | |
915490d5 | 4541 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4542 | } |
4543 | } | |
4544 | } | |
4545 | ||
615d8908 ID |
4546 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4547 | const struct sseu_dev_info *sseu) | |
4548 | { | |
4549 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4550 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4551 | ||
c67ba538 ID |
4552 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4553 | sseu->slice_mask); | |
615d8908 | 4554 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4555 | hweight8(sseu->slice_mask)); |
615d8908 | 4556 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4557 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4558 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4559 | sseu->subslice_mask); | |
615d8908 | 4560 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4561 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4562 | seq_printf(m, " %s EU Total: %u\n", type, |
4563 | sseu->eu_total); | |
4564 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4565 | sseu->eu_per_subslice); | |
4566 | ||
4567 | if (!is_available_info) | |
4568 | return; | |
4569 | ||
4570 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4571 | if (HAS_POOLED_EU(dev_priv)) | |
4572 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4573 | ||
4574 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4575 | yesno(sseu->has_slice_pg)); | |
4576 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4577 | yesno(sseu->has_subslice_pg)); | |
4578 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4579 | yesno(sseu->has_eu_pg)); | |
4580 | } | |
4581 | ||
3873218f JM |
4582 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4583 | { | |
36cdd013 | 4584 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4585 | struct sseu_dev_info sseu; |
3873218f | 4586 | |
36cdd013 | 4587 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4588 | return -ENODEV; |
4589 | ||
4590 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4591 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4592 | |
7f992aba | 4593 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4594 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4595 | |
4596 | intel_runtime_pm_get(dev_priv); | |
4597 | ||
36cdd013 | 4598 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4599 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4600 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4601 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4602 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4603 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4604 | } |
238010ed DW |
4605 | |
4606 | intel_runtime_pm_put(dev_priv); | |
4607 | ||
615d8908 | 4608 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4609 | |
3873218f JM |
4610 | return 0; |
4611 | } | |
4612 | ||
6d794d42 BW |
4613 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4614 | { | |
36cdd013 | 4615 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4616 | |
36cdd013 | 4617 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4618 | return 0; |
4619 | ||
6daccb0b | 4620 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4621 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4622 | |
4623 | return 0; | |
4624 | } | |
4625 | ||
c43b5634 | 4626 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4627 | { |
36cdd013 | 4628 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4629 | |
36cdd013 | 4630 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4631 | return 0; |
4632 | ||
59bad947 | 4633 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4634 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4635 | |
4636 | return 0; | |
4637 | } | |
4638 | ||
4639 | static const struct file_operations i915_forcewake_fops = { | |
4640 | .owner = THIS_MODULE, | |
4641 | .open = i915_forcewake_open, | |
4642 | .release = i915_forcewake_release, | |
4643 | }; | |
4644 | ||
4645 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4646 | { | |
6d794d42 BW |
4647 | struct dentry *ent; |
4648 | ||
4649 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4650 | S_IRUSR, |
36cdd013 | 4651 | root, to_i915(minor->dev), |
6d794d42 | 4652 | &i915_forcewake_fops); |
f3c5fe97 WY |
4653 | if (!ent) |
4654 | return -ENOMEM; | |
6d794d42 | 4655 | |
8eb57294 | 4656 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4657 | } |
4658 | ||
317eaa95 L |
4659 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4660 | { | |
4661 | struct drm_i915_private *dev_priv = m->private; | |
4662 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4663 | ||
4664 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4665 | seq_printf(m, "Detected: %s\n", | |
4666 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4667 | ||
4668 | return 0; | |
4669 | } | |
4670 | ||
4671 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4672 | const char __user *ubuf, size_t len, | |
4673 | loff_t *offp) | |
4674 | { | |
4675 | struct seq_file *m = file->private_data; | |
4676 | struct drm_i915_private *dev_priv = m->private; | |
4677 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4678 | unsigned int new_threshold; | |
4679 | int i; | |
4680 | char *newline; | |
4681 | char tmp[16]; | |
4682 | ||
4683 | if (len >= sizeof(tmp)) | |
4684 | return -EINVAL; | |
4685 | ||
4686 | if (copy_from_user(tmp, ubuf, len)) | |
4687 | return -EFAULT; | |
4688 | ||
4689 | tmp[len] = '\0'; | |
4690 | ||
4691 | /* Strip newline, if any */ | |
4692 | newline = strchr(tmp, '\n'); | |
4693 | if (newline) | |
4694 | *newline = '\0'; | |
4695 | ||
4696 | if (strcmp(tmp, "reset") == 0) | |
4697 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4698 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4699 | return -EINVAL; | |
4700 | ||
4701 | if (new_threshold > 0) | |
4702 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4703 | new_threshold); | |
4704 | else | |
4705 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4706 | ||
4707 | spin_lock_irq(&dev_priv->irq_lock); | |
4708 | hotplug->hpd_storm_threshold = new_threshold; | |
4709 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4710 | for_each_hpd_pin(i) | |
4711 | hotplug->stats[i].count = 0; | |
4712 | spin_unlock_irq(&dev_priv->irq_lock); | |
4713 | ||
4714 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4715 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4716 | ||
4717 | return len; | |
4718 | } | |
4719 | ||
4720 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4721 | { | |
4722 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4723 | } | |
4724 | ||
4725 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4726 | .owner = THIS_MODULE, | |
4727 | .open = i915_hpd_storm_ctl_open, | |
4728 | .read = seq_read, | |
4729 | .llseek = seq_lseek, | |
4730 | .release = single_release, | |
4731 | .write = i915_hpd_storm_ctl_write | |
4732 | }; | |
4733 | ||
6a9c308d DV |
4734 | static int i915_debugfs_create(struct dentry *root, |
4735 | struct drm_minor *minor, | |
4736 | const char *name, | |
4737 | const struct file_operations *fops) | |
07b7ddd9 | 4738 | { |
07b7ddd9 JB |
4739 | struct dentry *ent; |
4740 | ||
6a9c308d | 4741 | ent = debugfs_create_file(name, |
07b7ddd9 | 4742 | S_IRUGO | S_IWUSR, |
36cdd013 | 4743 | root, to_i915(minor->dev), |
6a9c308d | 4744 | fops); |
f3c5fe97 WY |
4745 | if (!ent) |
4746 | return -ENOMEM; | |
07b7ddd9 | 4747 | |
6a9c308d | 4748 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4749 | } |
4750 | ||
06c5bf8c | 4751 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4752 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4753 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4754 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4755 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4756 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4757 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4758 | {"i915_gem_request", i915_gem_request_info, 0}, |
4759 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4760 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4761 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4762 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4763 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4764 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4765 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
0509ead1 | 4766 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4767 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4768 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4769 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4770 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4771 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4772 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4773 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4774 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4775 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4776 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4777 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4778 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4779 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4780 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4781 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4782 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4783 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4784 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4785 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4786 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4787 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4788 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4789 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4790 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4791 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4792 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4793 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4794 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4795 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4796 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4797 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4798 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4799 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4800 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4801 | }; |
27c202ad | 4802 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4803 | |
06c5bf8c | 4804 | static const struct i915_debugfs_files { |
34b9674c DV |
4805 | const char *name; |
4806 | const struct file_operations *fops; | |
4807 | } i915_debugfs_files[] = { | |
4808 | {"i915_wedged", &i915_wedged_fops}, | |
4809 | {"i915_max_freq", &i915_max_freq_fops}, | |
4810 | {"i915_min_freq", &i915_min_freq_fops}, | |
4811 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4812 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4813 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4814 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4815 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4816 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4817 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4818 | #endif |
34b9674c | 4819 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4820 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4821 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4822 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4823 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4824 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
4825 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4826 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4827 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4828 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4829 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4830 | }; |
4831 | ||
1dac891c | 4832 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4833 | { |
91c8a326 | 4834 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 4835 | int ret, i; |
f3cd474b | 4836 | |
6d794d42 | 4837 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4838 | if (ret) |
4839 | return ret; | |
6a9c308d | 4840 | |
731035fe TV |
4841 | ret = intel_pipe_crc_create(minor); |
4842 | if (ret) | |
4843 | return ret; | |
07144428 | 4844 | |
34b9674c DV |
4845 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4846 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4847 | i915_debugfs_files[i].name, | |
4848 | i915_debugfs_files[i].fops); | |
4849 | if (ret) | |
4850 | return ret; | |
4851 | } | |
40633219 | 4852 | |
27c202ad BG |
4853 | return drm_debugfs_create_files(i915_debugfs_list, |
4854 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4855 | minor->debugfs_root, minor); |
4856 | } | |
4857 | ||
1dac891c | 4858 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 4859 | { |
91c8a326 | 4860 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
4861 | int i; |
4862 | ||
27c202ad BG |
4863 | drm_debugfs_remove_files(i915_debugfs_list, |
4864 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4865 | |
36cdd013 | 4866 | drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, |
6d794d42 | 4867 | 1, minor); |
07144428 | 4868 | |
731035fe | 4869 | intel_pipe_crc_cleanup(minor); |
07144428 | 4870 | |
34b9674c DV |
4871 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4872 | struct drm_info_list *info_list = | |
36cdd013 | 4873 | (struct drm_info_list *)i915_debugfs_files[i].fops; |
34b9674c DV |
4874 | |
4875 | drm_debugfs_remove_files(info_list, 1, minor); | |
4876 | } | |
2017263e | 4877 | } |
aa7471d2 JN |
4878 | |
4879 | struct dpcd_block { | |
4880 | /* DPCD dump start address. */ | |
4881 | unsigned int offset; | |
4882 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4883 | unsigned int end; | |
4884 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4885 | size_t size; | |
4886 | /* Only valid for eDP. */ | |
4887 | bool edp; | |
4888 | }; | |
4889 | ||
4890 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4891 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4892 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4893 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4894 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4895 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4896 | { .offset = DP_SET_POWER }, | |
4897 | { .offset = DP_EDP_DPCD_REV }, | |
4898 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4899 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4900 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4901 | }; | |
4902 | ||
4903 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4904 | { | |
4905 | struct drm_connector *connector = m->private; | |
4906 | struct intel_dp *intel_dp = | |
4907 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4908 | uint8_t buf[16]; | |
4909 | ssize_t err; | |
4910 | int i; | |
4911 | ||
5c1a8875 MK |
4912 | if (connector->status != connector_status_connected) |
4913 | return -ENODEV; | |
4914 | ||
aa7471d2 JN |
4915 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4916 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4917 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4918 | ||
4919 | if (b->edp && | |
4920 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4921 | continue; | |
4922 | ||
4923 | /* low tech for now */ | |
4924 | if (WARN_ON(size > sizeof(buf))) | |
4925 | continue; | |
4926 | ||
4927 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4928 | if (err <= 0) { | |
4929 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4930 | size, b->offset, err); | |
4931 | continue; | |
4932 | } | |
4933 | ||
4934 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4935 | } |
aa7471d2 JN |
4936 | |
4937 | return 0; | |
4938 | } | |
4939 | ||
4940 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4941 | { | |
4942 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4943 | } | |
4944 | ||
4945 | static const struct file_operations i915_dpcd_fops = { | |
4946 | .owner = THIS_MODULE, | |
4947 | .open = i915_dpcd_open, | |
4948 | .read = seq_read, | |
4949 | .llseek = seq_lseek, | |
4950 | .release = single_release, | |
4951 | }; | |
4952 | ||
ecbd6781 DW |
4953 | static int i915_panel_show(struct seq_file *m, void *data) |
4954 | { | |
4955 | struct drm_connector *connector = m->private; | |
4956 | struct intel_dp *intel_dp = | |
4957 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4958 | ||
4959 | if (connector->status != connector_status_connected) | |
4960 | return -ENODEV; | |
4961 | ||
4962 | seq_printf(m, "Panel power up delay: %d\n", | |
4963 | intel_dp->panel_power_up_delay); | |
4964 | seq_printf(m, "Panel power down delay: %d\n", | |
4965 | intel_dp->panel_power_down_delay); | |
4966 | seq_printf(m, "Backlight on delay: %d\n", | |
4967 | intel_dp->backlight_on_delay); | |
4968 | seq_printf(m, "Backlight off delay: %d\n", | |
4969 | intel_dp->backlight_off_delay); | |
4970 | ||
4971 | return 0; | |
4972 | } | |
4973 | ||
4974 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4975 | { | |
4976 | return single_open(file, i915_panel_show, inode->i_private); | |
4977 | } | |
4978 | ||
4979 | static const struct file_operations i915_panel_fops = { | |
4980 | .owner = THIS_MODULE, | |
4981 | .open = i915_panel_open, | |
4982 | .read = seq_read, | |
4983 | .llseek = seq_lseek, | |
4984 | .release = single_release, | |
4985 | }; | |
4986 | ||
aa7471d2 JN |
4987 | /** |
4988 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4989 | * @connector: pointer to a registered drm_connector | |
4990 | * | |
4991 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4992 | * drm_debugfs_connector_remove(). | |
4993 | * | |
4994 | * Returns 0 on success, negative error codes on error. | |
4995 | */ | |
4996 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4997 | { | |
4998 | struct dentry *root = connector->debugfs_entry; | |
4999 | ||
5000 | /* The connector must have been registered beforehands. */ | |
5001 | if (!root) | |
5002 | return -ENODEV; | |
5003 | ||
5004 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5005 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5006 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5007 | connector, &i915_dpcd_fops); | |
5008 | ||
5009 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5010 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5011 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5012 | |
5013 | return 0; | |
5014 | } |