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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
760285e7 | 33 | #include <drm/drmP.h> |
4e5359cd | 34 | #include "intel_drv.h" |
e5c65260 | 35 | #include "intel_ringbuffer.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
2017263e BG |
37 | #include "i915_drv.h" |
38 | ||
39 | #define DRM_I915_RING_DEBUG 1 | |
40 | ||
41 | ||
42 | #if defined(CONFIG_DEBUG_FS) | |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 | 46 | INACTIVE_LIST, |
d21d5975 | 47 | PINNED_LIST, |
f13d3f73 | 48 | }; |
2017263e | 49 | |
70d39fe4 CW |
50 | static const char *yesno(int v) |
51 | { | |
52 | return v ? "yes" : "no"; | |
53 | } | |
54 | ||
55 | static int i915_capabilities(struct seq_file *m, void *data) | |
56 | { | |
57 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
58 | struct drm_device *dev = node->minor->dev; | |
59 | const struct intel_device_info *info = INTEL_INFO(dev); | |
60 | ||
61 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
63 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
64 | #define SEP_SEMICOLON ; | |
65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
66 | #undef PRINT_FLAG | |
67 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
68 | |
69 | return 0; | |
70 | } | |
2017263e | 71 | |
05394f39 | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 73 | { |
05394f39 | 74 | if (obj->user_pin_count > 0) |
a6172a80 | 75 | return "P"; |
05394f39 | 76 | else if (obj->pin_count > 0) |
a6172a80 CW |
77 | return "p"; |
78 | else | |
79 | return " "; | |
80 | } | |
81 | ||
05394f39 | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 83 | { |
0206e353 AJ |
84 | switch (obj->tiling_mode) { |
85 | default: | |
86 | case I915_TILING_NONE: return " "; | |
87 | case I915_TILING_X: return "X"; | |
88 | case I915_TILING_Y: return "Y"; | |
89 | } | |
a6172a80 CW |
90 | } |
91 | ||
37811fcc CW |
92 | static void |
93 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
94 | { | |
2563a452 | 95 | seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
37811fcc CW |
96 | &obj->base, |
97 | get_pin_flag(obj), | |
98 | get_tiling_flag(obj), | |
a05a5862 | 99 | obj->base.size / 1024, |
37811fcc CW |
100 | obj->base.read_domains, |
101 | obj->base.write_domain, | |
0201f1ec CW |
102 | obj->last_read_seqno, |
103 | obj->last_write_seqno, | |
caea7476 | 104 | obj->last_fenced_seqno, |
84734a04 | 105 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
106 | obj->dirty ? " dirty" : "", |
107 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
108 | if (obj->base.name) | |
109 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
110 | if (obj->pin_count) |
111 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
112 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
113 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
f343c5f6 BW |
114 | if (i915_gem_obj_ggtt_bound(obj)) |
115 | seq_printf(m, " (gtt offset: %08lx, size: %08x)", | |
116 | i915_gem_obj_ggtt_offset(obj), (unsigned int)i915_gem_obj_ggtt_size(obj)); | |
c1ad11fc CW |
117 | if (obj->stolen) |
118 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
119 | if (obj->pin_mappable || obj->fault_mappable) { |
120 | char s[3], *t = s; | |
121 | if (obj->pin_mappable) | |
122 | *t++ = 'p'; | |
123 | if (obj->fault_mappable) | |
124 | *t++ = 'f'; | |
125 | *t = '\0'; | |
126 | seq_printf(m, " (%s mappable)", s); | |
127 | } | |
69dc4987 CW |
128 | if (obj->ring != NULL) |
129 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
130 | } |
131 | ||
433e12f7 | 132 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
133 | { |
134 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
135 | uintptr_t list = (uintptr_t) node->info_ent->data; |
136 | struct list_head *head; | |
2017263e BG |
137 | struct drm_device *dev = node->minor->dev; |
138 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 139 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
140 | size_t total_obj_size, total_gtt_size; |
141 | int count, ret; | |
de227ef0 CW |
142 | |
143 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
144 | if (ret) | |
145 | return ret; | |
2017263e | 146 | |
433e12f7 BG |
147 | switch (list) { |
148 | case ACTIVE_LIST: | |
267f0c90 | 149 | seq_puts(m, "Active:\n"); |
69dc4987 | 150 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
151 | break; |
152 | case INACTIVE_LIST: | |
267f0c90 | 153 | seq_puts(m, "Inactive:\n"); |
433e12f7 BG |
154 | head = &dev_priv->mm.inactive_list; |
155 | break; | |
433e12f7 | 156 | default: |
de227ef0 CW |
157 | mutex_unlock(&dev->struct_mutex); |
158 | return -EINVAL; | |
2017263e | 159 | } |
2017263e | 160 | |
8f2480fb | 161 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 162 | list_for_each_entry(obj, head, mm_list) { |
267f0c90 | 163 | seq_puts(m, " "); |
05394f39 | 164 | describe_obj(m, obj); |
267f0c90 | 165 | seq_putc(m, '\n'); |
05394f39 | 166 | total_obj_size += obj->base.size; |
f343c5f6 | 167 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
8f2480fb | 168 | count++; |
2017263e | 169 | } |
de227ef0 | 170 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 171 | |
8f2480fb CW |
172 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
173 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
174 | return 0; |
175 | } | |
176 | ||
6299f992 CW |
177 | #define count_objects(list, member) do { \ |
178 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 179 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
180 | ++count; \ |
181 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 182 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
183 | ++mappable_count; \ |
184 | } \ | |
185 | } \ | |
0206e353 | 186 | } while (0) |
6299f992 | 187 | |
2db8e9d6 CW |
188 | struct file_stats { |
189 | int count; | |
190 | size_t total, active, inactive, unbound; | |
191 | }; | |
192 | ||
193 | static int per_file_stats(int id, void *ptr, void *data) | |
194 | { | |
195 | struct drm_i915_gem_object *obj = ptr; | |
196 | struct file_stats *stats = data; | |
197 | ||
198 | stats->count++; | |
199 | stats->total += obj->base.size; | |
200 | ||
f343c5f6 | 201 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
202 | if (!list_empty(&obj->ring_list)) |
203 | stats->active += obj->base.size; | |
204 | else | |
205 | stats->inactive += obj->base.size; | |
206 | } else { | |
207 | if (!list_empty(&obj->global_list)) | |
208 | stats->unbound += obj->base.size; | |
209 | } | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
aee56cff | 214 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f CW |
215 | { |
216 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
217 | struct drm_device *dev = node->minor->dev; | |
218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
219 | u32 count, mappable_count, purgeable_count; |
220 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 221 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 222 | struct drm_file *file; |
73aa808f CW |
223 | int ret; |
224 | ||
225 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
226 | if (ret) | |
227 | return ret; | |
228 | ||
6299f992 CW |
229 | seq_printf(m, "%u objects, %zu bytes\n", |
230 | dev_priv->mm.object_count, | |
231 | dev_priv->mm.object_memory); | |
232 | ||
233 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 234 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
235 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
236 | count, mappable_count, size, mappable_size); | |
237 | ||
238 | size = count = mappable_size = mappable_count = 0; | |
239 | count_objects(&dev_priv->mm.active_list, mm_list); | |
6299f992 CW |
240 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
241 | count, mappable_count, size, mappable_size); | |
242 | ||
6299f992 CW |
243 | size = count = mappable_size = mappable_count = 0; |
244 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
245 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
246 | count, mappable_count, size, mappable_size); | |
247 | ||
b7abb714 | 248 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 249 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 250 | size += obj->base.size, ++count; |
b7abb714 CW |
251 | if (obj->madv == I915_MADV_DONTNEED) |
252 | purgeable_size += obj->base.size, ++purgeable_count; | |
253 | } | |
6c085a72 CW |
254 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
255 | ||
6299f992 | 256 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 258 | if (obj->fault_mappable) { |
f343c5f6 | 259 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
260 | ++count; |
261 | } | |
262 | if (obj->pin_mappable) { | |
f343c5f6 | 263 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
264 | ++mappable_count; |
265 | } | |
b7abb714 CW |
266 | if (obj->madv == I915_MADV_DONTNEED) { |
267 | purgeable_size += obj->base.size; | |
268 | ++purgeable_count; | |
269 | } | |
6299f992 | 270 | } |
b7abb714 CW |
271 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
272 | purgeable_count, purgeable_size); | |
6299f992 CW |
273 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
274 | mappable_count, mappable_size); | |
275 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
276 | count, size); | |
277 | ||
93d18799 | 278 | seq_printf(m, "%zu [%lu] gtt total\n", |
5d4545ae BW |
279 | dev_priv->gtt.total, |
280 | dev_priv->gtt.mappable_end - dev_priv->gtt.start); | |
73aa808f | 281 | |
267f0c90 | 282 | seq_putc(m, '\n'); |
2db8e9d6 CW |
283 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
284 | struct file_stats stats; | |
285 | ||
286 | memset(&stats, 0, sizeof(stats)); | |
287 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
288 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
289 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
290 | stats.count, | |
291 | stats.total, | |
292 | stats.active, | |
293 | stats.inactive, | |
294 | stats.unbound); | |
295 | } | |
296 | ||
73aa808f CW |
297 | mutex_unlock(&dev->struct_mutex); |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
aee56cff | 302 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
303 | { |
304 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
305 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 306 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
307 | struct drm_i915_private *dev_priv = dev->dev_private; |
308 | struct drm_i915_gem_object *obj; | |
309 | size_t total_obj_size, total_gtt_size; | |
310 | int count, ret; | |
311 | ||
312 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
313 | if (ret) | |
314 | return ret; | |
315 | ||
316 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 317 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
318 | if (list == PINNED_LIST && obj->pin_count == 0) |
319 | continue; | |
320 | ||
267f0c90 | 321 | seq_puts(m, " "); |
08c18323 | 322 | describe_obj(m, obj); |
267f0c90 | 323 | seq_putc(m, '\n'); |
08c18323 | 324 | total_obj_size += obj->base.size; |
f343c5f6 | 325 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
326 | count++; |
327 | } | |
328 | ||
329 | mutex_unlock(&dev->struct_mutex); | |
330 | ||
331 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
332 | count, total_obj_size, total_gtt_size); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
4e5359cd SF |
337 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
338 | { | |
339 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
340 | struct drm_device *dev = node->minor->dev; | |
341 | unsigned long flags; | |
342 | struct intel_crtc *crtc; | |
343 | ||
344 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
345 | const char pipe = pipe_name(crtc->pipe); |
346 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
347 | struct intel_unpin_work *work; |
348 | ||
349 | spin_lock_irqsave(&dev->event_lock, flags); | |
350 | work = crtc->unpin_work; | |
351 | if (work == NULL) { | |
9db4a9c7 | 352 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
353 | pipe, plane); |
354 | } else { | |
e7d841ca | 355 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 356 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
357 | pipe, plane); |
358 | } else { | |
9db4a9c7 | 359 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
360 | pipe, plane); |
361 | } | |
362 | if (work->enable_stall_check) | |
267f0c90 | 363 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 364 | else |
267f0c90 | 365 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 366 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
367 | |
368 | if (work->old_fb_obj) { | |
05394f39 CW |
369 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
370 | if (obj) | |
f343c5f6 BW |
371 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
372 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
373 | } |
374 | if (work->pending_flip_obj) { | |
05394f39 CW |
375 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
376 | if (obj) | |
f343c5f6 BW |
377 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
378 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
379 | } |
380 | } | |
381 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
2017263e BG |
387 | static int i915_gem_request_info(struct seq_file *m, void *data) |
388 | { | |
389 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
390 | struct drm_device *dev = node->minor->dev; | |
391 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 392 | struct intel_ring_buffer *ring; |
2017263e | 393 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 394 | int ret, count, i; |
de227ef0 CW |
395 | |
396 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
397 | if (ret) | |
398 | return ret; | |
2017263e | 399 | |
c2c347a9 | 400 | count = 0; |
a2c7f6fd CW |
401 | for_each_ring(ring, dev_priv, i) { |
402 | if (list_empty(&ring->request_list)) | |
403 | continue; | |
404 | ||
405 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 406 | list_for_each_entry(gem_request, |
a2c7f6fd | 407 | &ring->request_list, |
c2c347a9 CW |
408 | list) { |
409 | seq_printf(m, " %d @ %d\n", | |
410 | gem_request->seqno, | |
411 | (int) (jiffies - gem_request->emitted_jiffies)); | |
412 | } | |
413 | count++; | |
2017263e | 414 | } |
de227ef0 CW |
415 | mutex_unlock(&dev->struct_mutex); |
416 | ||
c2c347a9 | 417 | if (count == 0) |
267f0c90 | 418 | seq_puts(m, "No requests\n"); |
c2c347a9 | 419 | |
2017263e BG |
420 | return 0; |
421 | } | |
422 | ||
b2223497 CW |
423 | static void i915_ring_seqno_info(struct seq_file *m, |
424 | struct intel_ring_buffer *ring) | |
425 | { | |
426 | if (ring->get_seqno) { | |
43a7b924 | 427 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 428 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
429 | } |
430 | } | |
431 | ||
2017263e BG |
432 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
433 | { | |
434 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
435 | struct drm_device *dev = node->minor->dev; | |
436 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 437 | struct intel_ring_buffer *ring; |
1ec14ad3 | 438 | int ret, i; |
de227ef0 CW |
439 | |
440 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
441 | if (ret) | |
442 | return ret; | |
2017263e | 443 | |
a2c7f6fd CW |
444 | for_each_ring(ring, dev_priv, i) |
445 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
446 | |
447 | mutex_unlock(&dev->struct_mutex); | |
448 | ||
2017263e BG |
449 | return 0; |
450 | } | |
451 | ||
452 | ||
453 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
454 | { | |
455 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
456 | struct drm_device *dev = node->minor->dev; | |
457 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 458 | struct intel_ring_buffer *ring; |
9db4a9c7 | 459 | int ret, i, pipe; |
de227ef0 CW |
460 | |
461 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
462 | if (ret) | |
463 | return ret; | |
2017263e | 464 | |
7e231dbe JB |
465 | if (IS_VALLEYVIEW(dev)) { |
466 | seq_printf(m, "Display IER:\t%08x\n", | |
467 | I915_READ(VLV_IER)); | |
468 | seq_printf(m, "Display IIR:\t%08x\n", | |
469 | I915_READ(VLV_IIR)); | |
470 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
471 | I915_READ(VLV_IIR_RW)); | |
472 | seq_printf(m, "Display IMR:\t%08x\n", | |
473 | I915_READ(VLV_IMR)); | |
474 | for_each_pipe(pipe) | |
475 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
476 | pipe_name(pipe), | |
477 | I915_READ(PIPESTAT(pipe))); | |
478 | ||
479 | seq_printf(m, "Master IER:\t%08x\n", | |
480 | I915_READ(VLV_MASTER_IER)); | |
481 | ||
482 | seq_printf(m, "Render IER:\t%08x\n", | |
483 | I915_READ(GTIER)); | |
484 | seq_printf(m, "Render IIR:\t%08x\n", | |
485 | I915_READ(GTIIR)); | |
486 | seq_printf(m, "Render IMR:\t%08x\n", | |
487 | I915_READ(GTIMR)); | |
488 | ||
489 | seq_printf(m, "PM IER:\t\t%08x\n", | |
490 | I915_READ(GEN6_PMIER)); | |
491 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
492 | I915_READ(GEN6_PMIIR)); | |
493 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
494 | I915_READ(GEN6_PMIMR)); | |
495 | ||
496 | seq_printf(m, "Port hotplug:\t%08x\n", | |
497 | I915_READ(PORT_HOTPLUG_EN)); | |
498 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
499 | I915_READ(VLV_DPFLIPSTAT)); | |
500 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
501 | I915_READ(DPINVGTT)); | |
502 | ||
503 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
504 | seq_printf(m, "Interrupt enable: %08x\n", |
505 | I915_READ(IER)); | |
506 | seq_printf(m, "Interrupt identity: %08x\n", | |
507 | I915_READ(IIR)); | |
508 | seq_printf(m, "Interrupt mask: %08x\n", | |
509 | I915_READ(IMR)); | |
9db4a9c7 JB |
510 | for_each_pipe(pipe) |
511 | seq_printf(m, "Pipe %c stat: %08x\n", | |
512 | pipe_name(pipe), | |
513 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
514 | } else { |
515 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
516 | I915_READ(DEIER)); | |
517 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
518 | I915_READ(DEIIR)); | |
519 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
520 | I915_READ(DEIMR)); | |
521 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
522 | I915_READ(SDEIER)); | |
523 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
524 | I915_READ(SDEIIR)); | |
525 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
526 | I915_READ(SDEIMR)); | |
527 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
528 | I915_READ(GTIER)); | |
529 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
530 | I915_READ(GTIIR)); | |
531 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
532 | I915_READ(GTIMR)); | |
533 | } | |
2017263e BG |
534 | seq_printf(m, "Interrupts received: %d\n", |
535 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 536 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 537 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
538 | seq_printf(m, |
539 | "Graphics Interrupt mask (%s): %08x\n", | |
540 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 541 | } |
a2c7f6fd | 542 | i915_ring_seqno_info(m, ring); |
9862e600 | 543 | } |
de227ef0 CW |
544 | mutex_unlock(&dev->struct_mutex); |
545 | ||
2017263e BG |
546 | return 0; |
547 | } | |
548 | ||
a6172a80 CW |
549 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
550 | { | |
551 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
552 | struct drm_device *dev = node->minor->dev; | |
553 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
554 | int i, ret; |
555 | ||
556 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
557 | if (ret) | |
558 | return ret; | |
a6172a80 CW |
559 | |
560 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
561 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
562 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 563 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 564 | |
6c085a72 CW |
565 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
566 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 567 | if (obj == NULL) |
267f0c90 | 568 | seq_puts(m, "unused"); |
c2c347a9 | 569 | else |
05394f39 | 570 | describe_obj(m, obj); |
267f0c90 | 571 | seq_putc(m, '\n'); |
a6172a80 CW |
572 | } |
573 | ||
05394f39 | 574 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
575 | return 0; |
576 | } | |
577 | ||
2017263e BG |
578 | static int i915_hws_info(struct seq_file *m, void *data) |
579 | { | |
580 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
581 | struct drm_device *dev = node->minor->dev; | |
582 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 583 | struct intel_ring_buffer *ring; |
1a240d4d | 584 | const u32 *hws; |
4066c0ae CW |
585 | int i; |
586 | ||
1ec14ad3 | 587 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 588 | hws = ring->status_page.page_addr; |
2017263e BG |
589 | if (hws == NULL) |
590 | return 0; | |
591 | ||
592 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
593 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
594 | i * 4, | |
595 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
596 | } | |
597 | return 0; | |
598 | } | |
599 | ||
d5442303 DV |
600 | static ssize_t |
601 | i915_error_state_write(struct file *filp, | |
602 | const char __user *ubuf, | |
603 | size_t cnt, | |
604 | loff_t *ppos) | |
605 | { | |
edc3d884 | 606 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 607 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 608 | int ret; |
d5442303 DV |
609 | |
610 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
611 | ||
22bcfc6a DV |
612 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
613 | if (ret) | |
614 | return ret; | |
615 | ||
d5442303 DV |
616 | i915_destroy_error_state(dev); |
617 | mutex_unlock(&dev->struct_mutex); | |
618 | ||
619 | return cnt; | |
620 | } | |
621 | ||
622 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
623 | { | |
624 | struct drm_device *dev = inode->i_private; | |
d5442303 | 625 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
626 | |
627 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
628 | if (!error_priv) | |
629 | return -ENOMEM; | |
630 | ||
631 | error_priv->dev = dev; | |
632 | ||
95d5bfb3 | 633 | i915_error_state_get(dev, error_priv); |
d5442303 | 634 | |
edc3d884 MK |
635 | file->private_data = error_priv; |
636 | ||
637 | return 0; | |
d5442303 DV |
638 | } |
639 | ||
640 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
641 | { | |
edc3d884 | 642 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 643 | |
95d5bfb3 | 644 | i915_error_state_put(error_priv); |
d5442303 DV |
645 | kfree(error_priv); |
646 | ||
edc3d884 MK |
647 | return 0; |
648 | } | |
649 | ||
4dc955f7 MK |
650 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
651 | size_t count, loff_t *pos) | |
652 | { | |
653 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
654 | struct drm_i915_error_state_buf error_str; | |
655 | loff_t tmp_pos = 0; | |
656 | ssize_t ret_count = 0; | |
657 | int ret; | |
658 | ||
659 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
660 | if (ret) | |
661 | return ret; | |
edc3d884 | 662 | |
fc16b48b | 663 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
664 | if (ret) |
665 | goto out; | |
666 | ||
edc3d884 MK |
667 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
668 | error_str.buf, | |
669 | error_str.bytes); | |
670 | ||
671 | if (ret_count < 0) | |
672 | ret = ret_count; | |
673 | else | |
674 | *pos = error_str.start + ret_count; | |
675 | out: | |
4dc955f7 | 676 | i915_error_state_buf_release(&error_str); |
edc3d884 | 677 | return ret ?: ret_count; |
d5442303 DV |
678 | } |
679 | ||
680 | static const struct file_operations i915_error_state_fops = { | |
681 | .owner = THIS_MODULE, | |
682 | .open = i915_error_state_open, | |
edc3d884 | 683 | .read = i915_error_state_read, |
d5442303 DV |
684 | .write = i915_error_state_write, |
685 | .llseek = default_llseek, | |
686 | .release = i915_error_state_release, | |
687 | }; | |
688 | ||
647416f9 KC |
689 | static int |
690 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 691 | { |
647416f9 | 692 | struct drm_device *dev = data; |
40633219 | 693 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
694 | int ret; |
695 | ||
696 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
697 | if (ret) | |
698 | return ret; | |
699 | ||
647416f9 | 700 | *val = dev_priv->next_seqno; |
40633219 MK |
701 | mutex_unlock(&dev->struct_mutex); |
702 | ||
647416f9 | 703 | return 0; |
40633219 MK |
704 | } |
705 | ||
647416f9 KC |
706 | static int |
707 | i915_next_seqno_set(void *data, u64 val) | |
708 | { | |
709 | struct drm_device *dev = data; | |
40633219 MK |
710 | int ret; |
711 | ||
40633219 MK |
712 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
713 | if (ret) | |
714 | return ret; | |
715 | ||
e94fbaa8 | 716 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
717 | mutex_unlock(&dev->struct_mutex); |
718 | ||
647416f9 | 719 | return ret; |
40633219 MK |
720 | } |
721 | ||
647416f9 KC |
722 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
723 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 724 | "0x%llx\n"); |
40633219 | 725 | |
f97108d1 JB |
726 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
727 | { | |
728 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
729 | struct drm_device *dev = node->minor->dev; | |
730 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
731 | u16 crstanddelay; |
732 | int ret; | |
733 | ||
734 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
735 | if (ret) | |
736 | return ret; | |
737 | ||
738 | crstanddelay = I915_READ16(CRSTANDVID); | |
739 | ||
740 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
741 | |
742 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
748 | { | |
749 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
750 | struct drm_device *dev = node->minor->dev; | |
751 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 752 | int ret; |
3b8d8d91 JB |
753 | |
754 | if (IS_GEN5(dev)) { | |
755 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
756 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
757 | ||
758 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
759 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
760 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
761 | MEMSTAT_VID_SHIFT); | |
762 | seq_printf(m, "Current P-state: %d\n", | |
763 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 764 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
765 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
766 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
767 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 768 | u32 rpstat, cagf; |
ccab5c82 JB |
769 | u32 rpupei, rpcurup, rpprevup; |
770 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
771 | int max_freq; |
772 | ||
773 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
774 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
775 | if (ret) | |
776 | return ret; | |
777 | ||
fcca7926 | 778 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 779 | |
ccab5c82 JB |
780 | rpstat = I915_READ(GEN6_RPSTAT1); |
781 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
782 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
783 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
784 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
785 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
786 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
787 | if (IS_HASWELL(dev)) |
788 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
789 | else | |
790 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
791 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 792 | |
d1ebd816 BW |
793 | gen6_gt_force_wake_put(dev_priv); |
794 | mutex_unlock(&dev->struct_mutex); | |
795 | ||
3b8d8d91 | 796 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 797 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
798 | seq_printf(m, "Render p-state ratio: %d\n", |
799 | (gt_perf_status & 0xff00) >> 8); | |
800 | seq_printf(m, "Render p-state VID: %d\n", | |
801 | gt_perf_status & 0xff); | |
802 | seq_printf(m, "Render p-state limit: %d\n", | |
803 | rp_state_limits & 0xff); | |
f82855d3 | 804 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
805 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
806 | GEN6_CURICONT_MASK); | |
807 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
808 | GEN6_CURBSYTAVG_MASK); | |
809 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
810 | GEN6_CURBSYTAVG_MASK); | |
811 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
812 | GEN6_CURIAVG_MASK); | |
813 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
814 | GEN6_CURBSYTAVG_MASK); | |
815 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
816 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
817 | |
818 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
819 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 820 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
821 | |
822 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
823 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 824 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
825 | |
826 | max_freq = rp_state_cap & 0xff; | |
827 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 828 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
829 | |
830 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
831 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
832 | } else if (IS_VALLEYVIEW(dev)) { |
833 | u32 freq_sts, val; | |
834 | ||
259bd5d4 | 835 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 836 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
837 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
838 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
839 | ||
64936258 | 840 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
841 | seq_printf(m, "max GPU freq: %d MHz\n", |
842 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
843 | ||
64936258 | 844 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
845 | seq_printf(m, "min GPU freq: %d MHz\n", |
846 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
847 | ||
848 | seq_printf(m, "current GPU freq: %d MHz\n", | |
849 | vlv_gpu_freq(dev_priv->mem_freq, | |
850 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 851 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 852 | } else { |
267f0c90 | 853 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 854 | } |
f97108d1 JB |
855 | |
856 | return 0; | |
857 | } | |
858 | ||
859 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
860 | { | |
861 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
862 | struct drm_device *dev = node->minor->dev; | |
863 | drm_i915_private_t *dev_priv = dev->dev_private; | |
864 | u32 delayfreq; | |
616fdb5a BW |
865 | int ret, i; |
866 | ||
867 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
868 | if (ret) | |
869 | return ret; | |
f97108d1 JB |
870 | |
871 | for (i = 0; i < 16; i++) { | |
872 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
873 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
874 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
875 | } |
876 | ||
616fdb5a BW |
877 | mutex_unlock(&dev->struct_mutex); |
878 | ||
f97108d1 JB |
879 | return 0; |
880 | } | |
881 | ||
882 | static inline int MAP_TO_MV(int map) | |
883 | { | |
884 | return 1250 - (map * 25); | |
885 | } | |
886 | ||
887 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
888 | { | |
889 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
890 | struct drm_device *dev = node->minor->dev; | |
891 | drm_i915_private_t *dev_priv = dev->dev_private; | |
892 | u32 inttoext; | |
616fdb5a BW |
893 | int ret, i; |
894 | ||
895 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
896 | if (ret) | |
897 | return ret; | |
f97108d1 JB |
898 | |
899 | for (i = 1; i <= 32; i++) { | |
900 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
901 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
902 | } | |
903 | ||
616fdb5a BW |
904 | mutex_unlock(&dev->struct_mutex); |
905 | ||
f97108d1 JB |
906 | return 0; |
907 | } | |
908 | ||
4d85529d | 909 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
910 | { |
911 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
912 | struct drm_device *dev = node->minor->dev; | |
913 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
914 | u32 rgvmodectl, rstdbyctl; |
915 | u16 crstandvid; | |
916 | int ret; | |
917 | ||
918 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
919 | if (ret) | |
920 | return ret; | |
921 | ||
922 | rgvmodectl = I915_READ(MEMMODECTL); | |
923 | rstdbyctl = I915_READ(RSTDBYCTL); | |
924 | crstandvid = I915_READ16(CRSTANDVID); | |
925 | ||
926 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
927 | |
928 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
929 | "yes" : "no"); | |
930 | seq_printf(m, "Boost freq: %d\n", | |
931 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
932 | MEMMODE_BOOST_FREQ_SHIFT); | |
933 | seq_printf(m, "HW control enabled: %s\n", | |
934 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
935 | seq_printf(m, "SW control enabled: %s\n", | |
936 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
937 | seq_printf(m, "Gated voltage change: %s\n", | |
938 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
939 | seq_printf(m, "Starting frequency: P%d\n", | |
940 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 941 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 942 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
943 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
944 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
945 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
946 | seq_printf(m, "Render standby enabled: %s\n", | |
947 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 948 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
949 | switch (rstdbyctl & RSX_STATUS_MASK) { |
950 | case RSX_STATUS_ON: | |
267f0c90 | 951 | seq_puts(m, "on\n"); |
88271da3 JB |
952 | break; |
953 | case RSX_STATUS_RC1: | |
267f0c90 | 954 | seq_puts(m, "RC1\n"); |
88271da3 JB |
955 | break; |
956 | case RSX_STATUS_RC1E: | |
267f0c90 | 957 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
958 | break; |
959 | case RSX_STATUS_RS1: | |
267f0c90 | 960 | seq_puts(m, "RS1\n"); |
88271da3 JB |
961 | break; |
962 | case RSX_STATUS_RS2: | |
267f0c90 | 963 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
964 | break; |
965 | case RSX_STATUS_RS3: | |
267f0c90 | 966 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
967 | break; |
968 | default: | |
267f0c90 | 969 | seq_puts(m, "unknown\n"); |
88271da3 JB |
970 | break; |
971 | } | |
f97108d1 JB |
972 | |
973 | return 0; | |
974 | } | |
975 | ||
4d85529d BW |
976 | static int gen6_drpc_info(struct seq_file *m) |
977 | { | |
978 | ||
979 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
980 | struct drm_device *dev = node->minor->dev; | |
981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 982 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 983 | unsigned forcewake_count; |
aee56cff | 984 | int count = 0, ret; |
4d85529d BW |
985 | |
986 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
987 | if (ret) | |
988 | return ret; | |
989 | ||
93b525dc DV |
990 | spin_lock_irq(&dev_priv->gt_lock); |
991 | forcewake_count = dev_priv->forcewake_count; | |
992 | spin_unlock_irq(&dev_priv->gt_lock); | |
993 | ||
994 | if (forcewake_count) { | |
267f0c90 DL |
995 | seq_puts(m, "RC information inaccurate because somebody " |
996 | "holds a forcewake reference \n"); | |
4d85529d BW |
997 | } else { |
998 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
999 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1000 | udelay(10); | |
1001 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1002 | } | |
1003 | ||
1004 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1005 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1006 | ||
1007 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1008 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1009 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1010 | mutex_lock(&dev_priv->rps.hw_lock); |
1011 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1012 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1013 | |
1014 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1015 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1016 | seq_printf(m, "HW control enabled: %s\n", | |
1017 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1018 | seq_printf(m, "SW control enabled: %s\n", | |
1019 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1020 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1021 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1022 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1023 | seq_printf(m, "RC6 Enabled: %s\n", | |
1024 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1025 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1026 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1027 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1028 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1029 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1030 | switch (gt_core_status & GEN6_RCn_MASK) { |
1031 | case GEN6_RC0: | |
1032 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1033 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1034 | else |
267f0c90 | 1035 | seq_puts(m, "on\n"); |
4d85529d BW |
1036 | break; |
1037 | case GEN6_RC3: | |
267f0c90 | 1038 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1039 | break; |
1040 | case GEN6_RC6: | |
267f0c90 | 1041 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1042 | break; |
1043 | case GEN6_RC7: | |
267f0c90 | 1044 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1045 | break; |
1046 | default: | |
267f0c90 | 1047 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1048 | break; |
1049 | } | |
1050 | ||
1051 | seq_printf(m, "Core Power Down: %s\n", | |
1052 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1053 | |
1054 | /* Not exactly sure what this is */ | |
1055 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1056 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1057 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1058 | I915_READ(GEN6_GT_GFX_RC6)); | |
1059 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1060 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1061 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1062 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1063 | ||
ecd8faea BW |
1064 | seq_printf(m, "RC6 voltage: %dmV\n", |
1065 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1066 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1067 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1068 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1069 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1070 | return 0; |
1071 | } | |
1072 | ||
1073 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1074 | { | |
1075 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1076 | struct drm_device *dev = node->minor->dev; | |
1077 | ||
1078 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1079 | return gen6_drpc_info(m); | |
1080 | else | |
1081 | return ironlake_drpc_info(m); | |
1082 | } | |
1083 | ||
b5e50c3f JB |
1084 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1085 | { | |
1086 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1087 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1088 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1089 | |
ee5382ae | 1090 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1091 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1092 | return 0; |
1093 | } | |
1094 | ||
ee5382ae | 1095 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1096 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1097 | } else { |
267f0c90 | 1098 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1099 | switch (dev_priv->fbc.no_fbc_reason) { |
bed4a673 | 1100 | case FBC_NO_OUTPUT: |
267f0c90 | 1101 | seq_puts(m, "no outputs"); |
bed4a673 | 1102 | break; |
b5e50c3f | 1103 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1104 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1105 | break; |
1106 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1107 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1108 | break; |
1109 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1110 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1111 | break; |
1112 | case FBC_BAD_PLANE: | |
267f0c90 | 1113 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1114 | break; |
1115 | case FBC_NOT_TILED: | |
267f0c90 | 1116 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1117 | break; |
9c928d16 | 1118 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1119 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1120 | break; |
c1a9f047 | 1121 | case FBC_MODULE_PARAM: |
267f0c90 | 1122 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1123 | break; |
8a5729a3 | 1124 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1125 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1126 | break; |
b5e50c3f | 1127 | default: |
267f0c90 | 1128 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1129 | } |
267f0c90 | 1130 | seq_putc(m, '\n'); |
b5e50c3f JB |
1131 | } |
1132 | return 0; | |
1133 | } | |
1134 | ||
92d44621 PZ |
1135 | static int i915_ips_status(struct seq_file *m, void *unused) |
1136 | { | |
1137 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1138 | struct drm_device *dev = node->minor->dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | ||
f5adf94e | 1141 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1142 | seq_puts(m, "not supported\n"); |
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1147 | seq_puts(m, "enabled\n"); | |
1148 | else | |
1149 | seq_puts(m, "disabled\n"); | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
4a9bef37 JB |
1154 | static int i915_sr_status(struct seq_file *m, void *unused) |
1155 | { | |
1156 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1157 | struct drm_device *dev = node->minor->dev; | |
1158 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1159 | bool sr_enabled = false; | |
1160 | ||
1398261a | 1161 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1162 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1163 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1164 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1165 | else if (IS_I915GM(dev)) | |
1166 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1167 | else if (IS_PINEVIEW(dev)) | |
1168 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1169 | ||
5ba2aaaa CW |
1170 | seq_printf(m, "self-refresh: %s\n", |
1171 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1172 | |
1173 | return 0; | |
1174 | } | |
1175 | ||
7648fa99 JB |
1176 | static int i915_emon_status(struct seq_file *m, void *unused) |
1177 | { | |
1178 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1179 | struct drm_device *dev = node->minor->dev; | |
1180 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1181 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1182 | int ret; |
1183 | ||
582be6b4 CW |
1184 | if (!IS_GEN5(dev)) |
1185 | return -ENODEV; | |
1186 | ||
de227ef0 CW |
1187 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1188 | if (ret) | |
1189 | return ret; | |
7648fa99 JB |
1190 | |
1191 | temp = i915_mch_val(dev_priv); | |
1192 | chipset = i915_chipset_val(dev_priv); | |
1193 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1194 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1195 | |
1196 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1197 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1198 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1199 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
23b2f8bb JB |
1204 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1205 | { | |
1206 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1207 | struct drm_device *dev = node->minor->dev; | |
1208 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1209 | int ret; | |
1210 | int gpu_freq, ia_freq; | |
1211 | ||
1c70c0ce | 1212 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1213 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1214 | return 0; |
1215 | } | |
1216 | ||
4fc688ce | 1217 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1218 | if (ret) |
1219 | return ret; | |
1220 | ||
267f0c90 | 1221 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1222 | |
c6a828d3 DV |
1223 | for (gpu_freq = dev_priv->rps.min_delay; |
1224 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1225 | gpu_freq++) { |
42c0526c BW |
1226 | ia_freq = gpu_freq; |
1227 | sandybridge_pcode_read(dev_priv, | |
1228 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1229 | &ia_freq); | |
3ebecd07 CW |
1230 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1231 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1232 | ((ia_freq >> 0) & 0xff) * 100, | |
1233 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1234 | } |
1235 | ||
4fc688ce | 1236 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1237 | |
1238 | return 0; | |
1239 | } | |
1240 | ||
7648fa99 JB |
1241 | static int i915_gfxec(struct seq_file *m, void *unused) |
1242 | { | |
1243 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1244 | struct drm_device *dev = node->minor->dev; | |
1245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1246 | int ret; |
1247 | ||
1248 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1249 | if (ret) | |
1250 | return ret; | |
7648fa99 JB |
1251 | |
1252 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1253 | ||
616fdb5a BW |
1254 | mutex_unlock(&dev->struct_mutex); |
1255 | ||
7648fa99 JB |
1256 | return 0; |
1257 | } | |
1258 | ||
44834a67 CW |
1259 | static int i915_opregion(struct seq_file *m, void *unused) |
1260 | { | |
1261 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1262 | struct drm_device *dev = node->minor->dev; | |
1263 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1264 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1265 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1266 | int ret; |
1267 | ||
0d38f009 DV |
1268 | if (data == NULL) |
1269 | return -ENOMEM; | |
1270 | ||
44834a67 CW |
1271 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1272 | if (ret) | |
0d38f009 | 1273 | goto out; |
44834a67 | 1274 | |
0d38f009 DV |
1275 | if (opregion->header) { |
1276 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1277 | seq_write(m, data, OPREGION_SIZE); | |
1278 | } | |
44834a67 CW |
1279 | |
1280 | mutex_unlock(&dev->struct_mutex); | |
1281 | ||
0d38f009 DV |
1282 | out: |
1283 | kfree(data); | |
44834a67 CW |
1284 | return 0; |
1285 | } | |
1286 | ||
37811fcc CW |
1287 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1288 | { | |
1289 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1290 | struct drm_device *dev = node->minor->dev; | |
1291 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1292 | struct intel_fbdev *ifbdev; | |
1293 | struct intel_framebuffer *fb; | |
1294 | int ret; | |
1295 | ||
1296 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1297 | if (ret) | |
1298 | return ret; | |
1299 | ||
1300 | ifbdev = dev_priv->fbdev; | |
1301 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1302 | ||
623f9783 | 1303 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1304 | fb->base.width, |
1305 | fb->base.height, | |
1306 | fb->base.depth, | |
623f9783 DV |
1307 | fb->base.bits_per_pixel, |
1308 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1309 | describe_obj(m, fb->obj); |
267f0c90 | 1310 | seq_putc(m, '\n'); |
4b096ac1 | 1311 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1312 | |
4b096ac1 | 1313 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1314 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1315 | if (&fb->base == ifbdev->helper.fb) | |
1316 | continue; | |
1317 | ||
623f9783 | 1318 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1319 | fb->base.width, |
1320 | fb->base.height, | |
1321 | fb->base.depth, | |
623f9783 DV |
1322 | fb->base.bits_per_pixel, |
1323 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1324 | describe_obj(m, fb->obj); |
267f0c90 | 1325 | seq_putc(m, '\n'); |
37811fcc | 1326 | } |
4b096ac1 | 1327 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1328 | |
1329 | return 0; | |
1330 | } | |
1331 | ||
e76d3630 BW |
1332 | static int i915_context_status(struct seq_file *m, void *unused) |
1333 | { | |
1334 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1335 | struct drm_device *dev = node->minor->dev; | |
1336 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1337 | struct intel_ring_buffer *ring; |
1338 | int ret, i; | |
e76d3630 BW |
1339 | |
1340 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1341 | if (ret) | |
1342 | return ret; | |
1343 | ||
3e373948 | 1344 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1345 | seq_puts(m, "power context "); |
3e373948 | 1346 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1347 | seq_putc(m, '\n'); |
dc501fbc | 1348 | } |
e76d3630 | 1349 | |
3e373948 | 1350 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1351 | seq_puts(m, "render context "); |
3e373948 | 1352 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1353 | seq_putc(m, '\n'); |
dc501fbc | 1354 | } |
e76d3630 | 1355 | |
a168c293 BW |
1356 | for_each_ring(ring, dev_priv, i) { |
1357 | if (ring->default_context) { | |
1358 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1359 | describe_obj(m, ring->default_context->obj); | |
267f0c90 | 1360 | seq_putc(m, '\n'); |
a168c293 BW |
1361 | } |
1362 | } | |
1363 | ||
e76d3630 BW |
1364 | mutex_unlock(&dev->mode_config.mutex); |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
6d794d42 BW |
1369 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1370 | { | |
1371 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1372 | struct drm_device *dev = node->minor->dev; | |
1373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1374 | unsigned forcewake_count; |
6d794d42 | 1375 | |
9f1f46a4 DV |
1376 | spin_lock_irq(&dev_priv->gt_lock); |
1377 | forcewake_count = dev_priv->forcewake_count; | |
1378 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1379 | |
9f1f46a4 | 1380 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1381 | |
1382 | return 0; | |
1383 | } | |
1384 | ||
ea16a3cd DV |
1385 | static const char *swizzle_string(unsigned swizzle) |
1386 | { | |
aee56cff | 1387 | switch (swizzle) { |
ea16a3cd DV |
1388 | case I915_BIT_6_SWIZZLE_NONE: |
1389 | return "none"; | |
1390 | case I915_BIT_6_SWIZZLE_9: | |
1391 | return "bit9"; | |
1392 | case I915_BIT_6_SWIZZLE_9_10: | |
1393 | return "bit9/bit10"; | |
1394 | case I915_BIT_6_SWIZZLE_9_11: | |
1395 | return "bit9/bit11"; | |
1396 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1397 | return "bit9/bit10/bit11"; | |
1398 | case I915_BIT_6_SWIZZLE_9_17: | |
1399 | return "bit9/bit17"; | |
1400 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1401 | return "bit9/bit10/bit17"; | |
1402 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1403 | return "unknown"; |
ea16a3cd DV |
1404 | } |
1405 | ||
1406 | return "bug"; | |
1407 | } | |
1408 | ||
1409 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1410 | { | |
1411 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1412 | struct drm_device *dev = node->minor->dev; | |
1413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1414 | int ret; |
1415 | ||
1416 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1417 | if (ret) | |
1418 | return ret; | |
ea16a3cd | 1419 | |
ea16a3cd DV |
1420 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1421 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1422 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1423 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1424 | ||
1425 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1426 | seq_printf(m, "DDC = 0x%08x\n", | |
1427 | I915_READ(DCC)); | |
1428 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1429 | I915_READ16(C0DRB3)); | |
1430 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1431 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1432 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1433 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1434 | I915_READ(MAD_DIMM_C0)); | |
1435 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1436 | I915_READ(MAD_DIMM_C1)); | |
1437 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1438 | I915_READ(MAD_DIMM_C2)); | |
1439 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1440 | I915_READ(TILECTL)); | |
1441 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1442 | I915_READ(ARB_MODE)); | |
1443 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1444 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1445 | } |
1446 | mutex_unlock(&dev->struct_mutex); | |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
3cf17fc5 DV |
1451 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1452 | { | |
1453 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1454 | struct drm_device *dev = node->minor->dev; | |
1455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1456 | struct intel_ring_buffer *ring; | |
1457 | int i, ret; | |
1458 | ||
1459 | ||
1460 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1461 | if (ret) | |
1462 | return ret; | |
1463 | if (INTEL_INFO(dev)->gen == 6) | |
1464 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1465 | ||
a2c7f6fd | 1466 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1467 | seq_printf(m, "%s\n", ring->name); |
1468 | if (INTEL_INFO(dev)->gen == 7) | |
1469 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1470 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1471 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1472 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1473 | } | |
1474 | if (dev_priv->mm.aliasing_ppgtt) { | |
1475 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1476 | ||
267f0c90 | 1477 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1478 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1479 | } | |
1480 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1481 | mutex_unlock(&dev->struct_mutex); | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
57f350b6 JB |
1486 | static int i915_dpio_info(struct seq_file *m, void *data) |
1487 | { | |
1488 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1489 | struct drm_device *dev = node->minor->dev; | |
1490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1491 | int ret; | |
1492 | ||
1493 | ||
1494 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1495 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1496 | return 0; |
1497 | } | |
1498 | ||
09153000 | 1499 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1500 | if (ret) |
1501 | return ret; | |
1502 | ||
1503 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1504 | ||
1505 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
ae99258f | 1506 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
57f350b6 | 1507 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
ae99258f | 1508 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
57f350b6 JB |
1509 | |
1510 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
ae99258f | 1511 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
57f350b6 | 1512 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
ae99258f | 1513 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
57f350b6 JB |
1514 | |
1515 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
ae99258f | 1516 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
57f350b6 | 1517 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
ae99258f | 1518 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
57f350b6 | 1519 | |
4abb2c39 VS |
1520 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
1521 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); | |
1522 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", | |
1523 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); | |
57f350b6 JB |
1524 | |
1525 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ae99258f | 1526 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1527 | |
09153000 | 1528 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1529 | |
1530 | return 0; | |
1531 | } | |
1532 | ||
647416f9 KC |
1533 | static int |
1534 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1535 | { |
647416f9 | 1536 | struct drm_device *dev = data; |
f3cd474b | 1537 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1538 | |
647416f9 | 1539 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1540 | |
647416f9 | 1541 | return 0; |
f3cd474b CW |
1542 | } |
1543 | ||
647416f9 KC |
1544 | static int |
1545 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1546 | { |
647416f9 | 1547 | struct drm_device *dev = data; |
f3cd474b | 1548 | |
647416f9 | 1549 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1550 | i915_handle_error(dev, val); |
f3cd474b | 1551 | |
647416f9 | 1552 | return 0; |
f3cd474b CW |
1553 | } |
1554 | ||
647416f9 KC |
1555 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1556 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1557 | "%llu\n"); |
f3cd474b | 1558 | |
647416f9 KC |
1559 | static int |
1560 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1561 | { |
647416f9 | 1562 | struct drm_device *dev = data; |
e5eb3d63 | 1563 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1564 | |
647416f9 | 1565 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1566 | |
647416f9 | 1567 | return 0; |
e5eb3d63 DV |
1568 | } |
1569 | ||
647416f9 KC |
1570 | static int |
1571 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1572 | { |
647416f9 | 1573 | struct drm_device *dev = data; |
e5eb3d63 | 1574 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1575 | int ret; |
e5eb3d63 | 1576 | |
647416f9 | 1577 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1578 | |
22bcfc6a DV |
1579 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1580 | if (ret) | |
1581 | return ret; | |
1582 | ||
99584db3 | 1583 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1584 | mutex_unlock(&dev->struct_mutex); |
1585 | ||
647416f9 | 1586 | return 0; |
e5eb3d63 DV |
1587 | } |
1588 | ||
647416f9 KC |
1589 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1590 | i915_ring_stop_get, i915_ring_stop_set, | |
1591 | "0x%08llx\n"); | |
d5442303 | 1592 | |
dd624afd CW |
1593 | #define DROP_UNBOUND 0x1 |
1594 | #define DROP_BOUND 0x2 | |
1595 | #define DROP_RETIRE 0x4 | |
1596 | #define DROP_ACTIVE 0x8 | |
1597 | #define DROP_ALL (DROP_UNBOUND | \ | |
1598 | DROP_BOUND | \ | |
1599 | DROP_RETIRE | \ | |
1600 | DROP_ACTIVE) | |
647416f9 KC |
1601 | static int |
1602 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1603 | { |
647416f9 | 1604 | *val = DROP_ALL; |
dd624afd | 1605 | |
647416f9 | 1606 | return 0; |
dd624afd CW |
1607 | } |
1608 | ||
647416f9 KC |
1609 | static int |
1610 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1611 | { |
647416f9 | 1612 | struct drm_device *dev = data; |
dd624afd CW |
1613 | struct drm_i915_private *dev_priv = dev->dev_private; |
1614 | struct drm_i915_gem_object *obj, *next; | |
647416f9 | 1615 | int ret; |
dd624afd | 1616 | |
647416f9 | 1617 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1618 | |
1619 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1620 | * on ioctls on -EAGAIN. */ | |
1621 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1622 | if (ret) | |
1623 | return ret; | |
1624 | ||
1625 | if (val & DROP_ACTIVE) { | |
1626 | ret = i915_gpu_idle(dev); | |
1627 | if (ret) | |
1628 | goto unlock; | |
1629 | } | |
1630 | ||
1631 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1632 | i915_gem_retire_requests(dev); | |
1633 | ||
1634 | if (val & DROP_BOUND) { | |
1635 | list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list) | |
1636 | if (obj->pin_count == 0) { | |
1637 | ret = i915_gem_object_unbind(obj); | |
1638 | if (ret) | |
1639 | goto unlock; | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1644 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1645 | global_list) | |
dd624afd CW |
1646 | if (obj->pages_pin_count == 0) { |
1647 | ret = i915_gem_object_put_pages(obj); | |
1648 | if (ret) | |
1649 | goto unlock; | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | unlock: | |
1654 | mutex_unlock(&dev->struct_mutex); | |
1655 | ||
647416f9 | 1656 | return ret; |
dd624afd CW |
1657 | } |
1658 | ||
647416f9 KC |
1659 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1660 | i915_drop_caches_get, i915_drop_caches_set, | |
1661 | "0x%08llx\n"); | |
dd624afd | 1662 | |
647416f9 KC |
1663 | static int |
1664 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1665 | { |
647416f9 | 1666 | struct drm_device *dev = data; |
358733e9 | 1667 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1668 | int ret; |
004777cb DV |
1669 | |
1670 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1671 | return -ENODEV; | |
1672 | ||
4fc688ce | 1673 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1674 | if (ret) |
1675 | return ret; | |
358733e9 | 1676 | |
0a073b84 JB |
1677 | if (IS_VALLEYVIEW(dev)) |
1678 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1679 | dev_priv->rps.max_delay); | |
1680 | else | |
1681 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1682 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1683 | |
647416f9 | 1684 | return 0; |
358733e9 JB |
1685 | } |
1686 | ||
647416f9 KC |
1687 | static int |
1688 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1689 | { |
647416f9 | 1690 | struct drm_device *dev = data; |
358733e9 | 1691 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1692 | int ret; |
004777cb DV |
1693 | |
1694 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1695 | return -ENODEV; | |
358733e9 | 1696 | |
647416f9 | 1697 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 1698 | |
4fc688ce | 1699 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1700 | if (ret) |
1701 | return ret; | |
1702 | ||
358733e9 JB |
1703 | /* |
1704 | * Turbo will still be enabled, but won't go above the set value. | |
1705 | */ | |
0a073b84 JB |
1706 | if (IS_VALLEYVIEW(dev)) { |
1707 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1708 | dev_priv->rps.max_delay = val; | |
1709 | gen6_set_rps(dev, val); | |
1710 | } else { | |
1711 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1712 | dev_priv->rps.max_delay = val; | |
1713 | gen6_set_rps(dev, val); | |
1714 | } | |
1715 | ||
4fc688ce | 1716 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1717 | |
647416f9 | 1718 | return 0; |
358733e9 JB |
1719 | } |
1720 | ||
647416f9 KC |
1721 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
1722 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 1723 | "%llu\n"); |
358733e9 | 1724 | |
647416f9 KC |
1725 | static int |
1726 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 1727 | { |
647416f9 | 1728 | struct drm_device *dev = data; |
1523c310 | 1729 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1730 | int ret; |
004777cb DV |
1731 | |
1732 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1733 | return -ENODEV; | |
1734 | ||
4fc688ce | 1735 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1736 | if (ret) |
1737 | return ret; | |
1523c310 | 1738 | |
0a073b84 JB |
1739 | if (IS_VALLEYVIEW(dev)) |
1740 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1741 | dev_priv->rps.min_delay); | |
1742 | else | |
1743 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1744 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1745 | |
647416f9 | 1746 | return 0; |
1523c310 JB |
1747 | } |
1748 | ||
647416f9 KC |
1749 | static int |
1750 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 1751 | { |
647416f9 | 1752 | struct drm_device *dev = data; |
1523c310 | 1753 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1754 | int ret; |
004777cb DV |
1755 | |
1756 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1757 | return -ENODEV; | |
1523c310 | 1758 | |
647416f9 | 1759 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 1760 | |
4fc688ce | 1761 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1762 | if (ret) |
1763 | return ret; | |
1764 | ||
1523c310 JB |
1765 | /* |
1766 | * Turbo will still be enabled, but won't go below the set value. | |
1767 | */ | |
0a073b84 JB |
1768 | if (IS_VALLEYVIEW(dev)) { |
1769 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1770 | dev_priv->rps.min_delay = val; | |
1771 | valleyview_set_rps(dev, val); | |
1772 | } else { | |
1773 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1774 | dev_priv->rps.min_delay = val; | |
1775 | gen6_set_rps(dev, val); | |
1776 | } | |
4fc688ce | 1777 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1778 | |
647416f9 | 1779 | return 0; |
1523c310 JB |
1780 | } |
1781 | ||
647416f9 KC |
1782 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
1783 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 1784 | "%llu\n"); |
1523c310 | 1785 | |
647416f9 KC |
1786 | static int |
1787 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 1788 | { |
647416f9 | 1789 | struct drm_device *dev = data; |
07b7ddd9 | 1790 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 1791 | u32 snpcr; |
647416f9 | 1792 | int ret; |
07b7ddd9 | 1793 | |
004777cb DV |
1794 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1795 | return -ENODEV; | |
1796 | ||
22bcfc6a DV |
1797 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1798 | if (ret) | |
1799 | return ret; | |
1800 | ||
07b7ddd9 JB |
1801 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
1802 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1803 | ||
647416f9 | 1804 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 1805 | |
647416f9 | 1806 | return 0; |
07b7ddd9 JB |
1807 | } |
1808 | ||
647416f9 KC |
1809 | static int |
1810 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 1811 | { |
647416f9 | 1812 | struct drm_device *dev = data; |
07b7ddd9 | 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 1814 | u32 snpcr; |
07b7ddd9 | 1815 | |
004777cb DV |
1816 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1817 | return -ENODEV; | |
1818 | ||
647416f9 | 1819 | if (val > 3) |
07b7ddd9 JB |
1820 | return -EINVAL; |
1821 | ||
647416f9 | 1822 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
1823 | |
1824 | /* Update the cache sharing policy here as well */ | |
1825 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1826 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1827 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1828 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1829 | ||
647416f9 | 1830 | return 0; |
07b7ddd9 JB |
1831 | } |
1832 | ||
647416f9 KC |
1833 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
1834 | i915_cache_sharing_get, i915_cache_sharing_set, | |
1835 | "%llu\n"); | |
07b7ddd9 | 1836 | |
f3cd474b CW |
1837 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1838 | * allocated we need to hook into the minor for release. */ | |
1839 | static int | |
1840 | drm_add_fake_info_node(struct drm_minor *minor, | |
1841 | struct dentry *ent, | |
1842 | const void *key) | |
1843 | { | |
1844 | struct drm_info_node *node; | |
1845 | ||
1846 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1847 | if (node == NULL) { | |
1848 | debugfs_remove(ent); | |
1849 | return -ENOMEM; | |
1850 | } | |
1851 | ||
1852 | node->minor = minor; | |
1853 | node->dent = ent; | |
1854 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1855 | |
1856 | mutex_lock(&minor->debugfs_lock); | |
1857 | list_add(&node->list, &minor->debugfs_list); | |
1858 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1859 | |
1860 | return 0; | |
1861 | } | |
1862 | ||
6d794d42 BW |
1863 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1864 | { | |
1865 | struct drm_device *dev = inode->i_private; | |
1866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 1867 | |
075edca4 | 1868 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1869 | return 0; |
1870 | ||
6d794d42 | 1871 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
1872 | |
1873 | return 0; | |
1874 | } | |
1875 | ||
c43b5634 | 1876 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
1877 | { |
1878 | struct drm_device *dev = inode->i_private; | |
1879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1880 | ||
075edca4 | 1881 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1882 | return 0; |
1883 | ||
6d794d42 | 1884 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
1885 | |
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | static const struct file_operations i915_forcewake_fops = { | |
1890 | .owner = THIS_MODULE, | |
1891 | .open = i915_forcewake_open, | |
1892 | .release = i915_forcewake_release, | |
1893 | }; | |
1894 | ||
1895 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1896 | { | |
1897 | struct drm_device *dev = minor->dev; | |
1898 | struct dentry *ent; | |
1899 | ||
1900 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1901 | S_IRUSR, |
6d794d42 BW |
1902 | root, dev, |
1903 | &i915_forcewake_fops); | |
1904 | if (IS_ERR(ent)) | |
1905 | return PTR_ERR(ent); | |
1906 | ||
8eb57294 | 1907 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1908 | } |
1909 | ||
6a9c308d DV |
1910 | static int i915_debugfs_create(struct dentry *root, |
1911 | struct drm_minor *minor, | |
1912 | const char *name, | |
1913 | const struct file_operations *fops) | |
07b7ddd9 JB |
1914 | { |
1915 | struct drm_device *dev = minor->dev; | |
1916 | struct dentry *ent; | |
1917 | ||
6a9c308d | 1918 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
1919 | S_IRUGO | S_IWUSR, |
1920 | root, dev, | |
6a9c308d | 1921 | fops); |
07b7ddd9 JB |
1922 | if (IS_ERR(ent)) |
1923 | return PTR_ERR(ent); | |
1924 | ||
6a9c308d | 1925 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
1926 | } |
1927 | ||
27c202ad | 1928 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1929 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1930 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1931 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 1932 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 1933 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 1934 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 1935 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1936 | {"i915_gem_request", i915_gem_request_info, 0}, |
1937 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1938 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1939 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1940 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1941 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1942 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 1943 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
1944 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1945 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1946 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1947 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1948 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1949 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1950 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1951 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1952 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 1953 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 1954 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1955 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1956 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1957 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1958 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 1959 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 1960 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 1961 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 1962 | }; |
27c202ad | 1963 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1964 | |
34b9674c DV |
1965 | struct i915_debugfs_files { |
1966 | const char *name; | |
1967 | const struct file_operations *fops; | |
1968 | } i915_debugfs_files[] = { | |
1969 | {"i915_wedged", &i915_wedged_fops}, | |
1970 | {"i915_max_freq", &i915_max_freq_fops}, | |
1971 | {"i915_min_freq", &i915_min_freq_fops}, | |
1972 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
1973 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
1974 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, | |
1975 | {"i915_error_state", &i915_error_state_fops}, | |
1976 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
1977 | }; | |
1978 | ||
27c202ad | 1979 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1980 | { |
34b9674c | 1981 | int ret, i; |
f3cd474b | 1982 | |
6d794d42 | 1983 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1984 | if (ret) |
1985 | return ret; | |
6a9c308d | 1986 | |
34b9674c DV |
1987 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
1988 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1989 | i915_debugfs_files[i].name, | |
1990 | i915_debugfs_files[i].fops); | |
1991 | if (ret) | |
1992 | return ret; | |
1993 | } | |
40633219 | 1994 | |
27c202ad BG |
1995 | return drm_debugfs_create_files(i915_debugfs_list, |
1996 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1997 | minor->debugfs_root, minor); |
1998 | } | |
1999 | ||
27c202ad | 2000 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2001 | { |
34b9674c DV |
2002 | int i; |
2003 | ||
27c202ad BG |
2004 | drm_debugfs_remove_files(i915_debugfs_list, |
2005 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2006 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2007 | 1, minor); | |
34b9674c DV |
2008 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2009 | struct drm_info_list *info_list = | |
2010 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2011 | ||
2012 | drm_debugfs_remove_files(info_list, 1, minor); | |
2013 | } | |
2017263e BG |
2014 | } |
2015 | ||
2016 | #endif /* CONFIG_DEBUG_FS */ |