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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
d92a8cfc | 31 | #include <linux/sched/mm.h> |
4e5359cd | 32 | #include "intel_drv.h" |
a2695744 | 33 | #include "intel_guc_submission.h" |
2017263e | 34 | |
36cdd013 DW |
35 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
36 | { | |
37 | return to_i915(node->minor->dev); | |
38 | } | |
39 | ||
70d39fe4 CW |
40 | static int i915_capabilities(struct seq_file *m, void *data) |
41 | { | |
36cdd013 DW |
42 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
43 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
a8c9b849 | 44 | struct drm_printer p = drm_seq_file_printer(m); |
70d39fe4 | 45 | |
36cdd013 | 46 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 47 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 48 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 49 | |
a8c9b849 | 50 | intel_device_info_dump_flags(info, &p); |
5fbbe8d4 | 51 | intel_device_info_dump_runtime(info, &p); |
3fed1808 | 52 | intel_driver_caps_print(&dev_priv->caps, &p); |
70d39fe4 | 53 | |
418e3cd8 | 54 | kernel_param_lock(THIS_MODULE); |
acfb9973 | 55 | i915_params_dump(&i915_modparams, &p); |
418e3cd8 CW |
56 | kernel_param_unlock(THIS_MODULE); |
57 | ||
70d39fe4 CW |
58 | return 0; |
59 | } | |
2017263e | 60 | |
a7363de7 | 61 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 62 | { |
573adb39 | 63 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
64 | } |
65 | ||
a7363de7 | 66 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b | 67 | { |
bd3d2252 | 68 | return obj->pin_global ? 'p' : ' '; |
be12a86b TU |
69 | } |
70 | ||
a7363de7 | 71 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 72 | { |
3e510a8e | 73 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 74 | default: |
be12a86b TU |
75 | case I915_TILING_NONE: return ' '; |
76 | case I915_TILING_X: return 'X'; | |
77 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 78 | } |
a6172a80 CW |
79 | } |
80 | ||
a7363de7 | 81 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 82 | { |
a65adaf8 | 83 | return obj->userfault_count ? 'g' : ' '; |
be12a86b TU |
84 | } |
85 | ||
a7363de7 | 86 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 87 | { |
a4f5ea64 | 88 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
89 | } |
90 | ||
ca1543be TU |
91 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
92 | { | |
93 | u64 size = 0; | |
94 | struct i915_vma *vma; | |
95 | ||
e2189dd0 CW |
96 | for_each_ggtt_vma(vma, obj) { |
97 | if (drm_mm_node_allocated(&vma->node)) | |
ca1543be TU |
98 | size += vma->node.size; |
99 | } | |
100 | ||
101 | return size; | |
102 | } | |
103 | ||
7393b7ee MA |
104 | static const char * |
105 | stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) | |
106 | { | |
107 | size_t x = 0; | |
108 | ||
109 | switch (page_sizes) { | |
110 | case 0: | |
111 | return ""; | |
112 | case I915_GTT_PAGE_SIZE_4K: | |
113 | return "4K"; | |
114 | case I915_GTT_PAGE_SIZE_64K: | |
115 | return "64K"; | |
116 | case I915_GTT_PAGE_SIZE_2M: | |
117 | return "2M"; | |
118 | default: | |
119 | if (!buf) | |
120 | return "M"; | |
121 | ||
122 | if (page_sizes & I915_GTT_PAGE_SIZE_2M) | |
123 | x += snprintf(buf + x, len - x, "2M, "); | |
124 | if (page_sizes & I915_GTT_PAGE_SIZE_64K) | |
125 | x += snprintf(buf + x, len - x, "64K, "); | |
126 | if (page_sizes & I915_GTT_PAGE_SIZE_4K) | |
127 | x += snprintf(buf + x, len - x, "4K, "); | |
128 | buf[x-2] = '\0'; | |
129 | ||
130 | return buf; | |
131 | } | |
132 | } | |
133 | ||
37811fcc CW |
134 | static void |
135 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
136 | { | |
b4716185 | 137 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 138 | struct intel_engine_cs *engine; |
1d693bcc | 139 | struct i915_vma *vma; |
faf5bf0a | 140 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
141 | int pin_count = 0; |
142 | ||
188c1ab7 CW |
143 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
144 | ||
d07f0e59 | 145 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 146 | &obj->base, |
be12a86b | 147 | get_active_flag(obj), |
37811fcc CW |
148 | get_pin_flag(obj), |
149 | get_tiling_flag(obj), | |
1d693bcc | 150 | get_global_flag(obj), |
be12a86b | 151 | get_pin_mapped_flag(obj), |
a05a5862 | 152 | obj->base.size / 1024, |
c0a51fd0 CK |
153 | obj->read_domains, |
154 | obj->write_domain, | |
36cdd013 | 155 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
156 | obj->mm.dirty ? " dirty" : "", |
157 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
158 | if (obj->base.name) |
159 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 160 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 161 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 162 | pin_count++; |
ba0635ff DC |
163 | } |
164 | seq_printf(m, " (pinned x %d)", pin_count); | |
bd3d2252 CW |
165 | if (obj->pin_global) |
166 | seq_printf(m, " (global)"); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
168 | if (!drm_mm_node_allocated(&vma->node)) |
169 | continue; | |
170 | ||
7393b7ee | 171 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", |
3272db53 | 172 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
7393b7ee MA |
173 | vma->node.start, vma->node.size, |
174 | stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); | |
21976853 CW |
175 | if (i915_vma_is_ggtt(vma)) { |
176 | switch (vma->ggtt_view.type) { | |
177 | case I915_GGTT_VIEW_NORMAL: | |
178 | seq_puts(m, ", normal"); | |
179 | break; | |
180 | ||
181 | case I915_GGTT_VIEW_PARTIAL: | |
182 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
183 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
184 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
185 | break; |
186 | ||
187 | case I915_GGTT_VIEW_ROTATED: | |
188 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
189 | vma->ggtt_view.rotated.plane[0].width, |
190 | vma->ggtt_view.rotated.plane[0].height, | |
191 | vma->ggtt_view.rotated.plane[0].stride, | |
192 | vma->ggtt_view.rotated.plane[0].offset, | |
193 | vma->ggtt_view.rotated.plane[1].width, | |
194 | vma->ggtt_view.rotated.plane[1].height, | |
195 | vma->ggtt_view.rotated.plane[1].stride, | |
196 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
197 | break; |
198 | ||
199 | default: | |
200 | MISSING_CASE(vma->ggtt_view.type); | |
201 | break; | |
202 | } | |
203 | } | |
49ef5294 CW |
204 | if (vma->fence) |
205 | seq_printf(m, " , fence: %d%s", | |
206 | vma->fence->id, | |
207 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 208 | seq_puts(m, ")"); |
1d693bcc | 209 | } |
c1ad11fc | 210 | if (obj->stolen) |
440fd528 | 211 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 212 | |
d07f0e59 | 213 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
214 | if (engine) |
215 | seq_printf(m, " (%s)", engine->name); | |
216 | ||
faf5bf0a CW |
217 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
218 | if (frontbuffer_bits) | |
219 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
220 | } |
221 | ||
e637d2cb | 222 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 223 | { |
e637d2cb CW |
224 | const struct drm_i915_gem_object *a = |
225 | *(const struct drm_i915_gem_object **)A; | |
226 | const struct drm_i915_gem_object *b = | |
227 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 228 | |
2d05fa16 RV |
229 | if (a->stolen->start < b->stolen->start) |
230 | return -1; | |
231 | if (a->stolen->start > b->stolen->start) | |
232 | return 1; | |
233 | return 0; | |
6d2b8885 CW |
234 | } |
235 | ||
236 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
237 | { | |
36cdd013 DW |
238 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
239 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 240 | struct drm_i915_gem_object **objects; |
6d2b8885 | 241 | struct drm_i915_gem_object *obj; |
c44ef60e | 242 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
243 | unsigned long total, count, n; |
244 | int ret; | |
245 | ||
246 | total = READ_ONCE(dev_priv->mm.object_count); | |
2098105e | 247 | objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL); |
e637d2cb CW |
248 | if (!objects) |
249 | return -ENOMEM; | |
6d2b8885 CW |
250 | |
251 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
252 | if (ret) | |
e637d2cb | 253 | goto out; |
6d2b8885 CW |
254 | |
255 | total_obj_size = total_gtt_size = count = 0; | |
f2123818 CW |
256 | |
257 | spin_lock(&dev_priv->mm.obj_lock); | |
258 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
e637d2cb CW |
259 | if (count == total) |
260 | break; | |
261 | ||
6d2b8885 CW |
262 | if (obj->stolen == NULL) |
263 | continue; | |
264 | ||
e637d2cb | 265 | objects[count++] = obj; |
6d2b8885 | 266 | total_obj_size += obj->base.size; |
ca1543be | 267 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 268 | |
6d2b8885 | 269 | } |
f2123818 | 270 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { |
e637d2cb CW |
271 | if (count == total) |
272 | break; | |
273 | ||
6d2b8885 CW |
274 | if (obj->stolen == NULL) |
275 | continue; | |
276 | ||
e637d2cb | 277 | objects[count++] = obj; |
6d2b8885 | 278 | total_obj_size += obj->base.size; |
6d2b8885 | 279 | } |
f2123818 | 280 | spin_unlock(&dev_priv->mm.obj_lock); |
e637d2cb CW |
281 | |
282 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
283 | ||
6d2b8885 | 284 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 285 | for (n = 0; n < count; n++) { |
6d2b8885 | 286 | seq_puts(m, " "); |
e637d2cb | 287 | describe_obj(m, objects[n]); |
6d2b8885 | 288 | seq_putc(m, '\n'); |
6d2b8885 | 289 | } |
e637d2cb | 290 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 291 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
292 | |
293 | mutex_unlock(&dev->struct_mutex); | |
294 | out: | |
2098105e | 295 | kvfree(objects); |
e637d2cb | 296 | return ret; |
6d2b8885 CW |
297 | } |
298 | ||
2db8e9d6 | 299 | struct file_stats { |
6313c204 | 300 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
301 | unsigned long count; |
302 | u64 total, unbound; | |
303 | u64 global, shared; | |
304 | u64 active, inactive; | |
2db8e9d6 CW |
305 | }; |
306 | ||
307 | static int per_file_stats(int id, void *ptr, void *data) | |
308 | { | |
309 | struct drm_i915_gem_object *obj = ptr; | |
310 | struct file_stats *stats = data; | |
6313c204 | 311 | struct i915_vma *vma; |
2db8e9d6 | 312 | |
0caf81b5 CW |
313 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
314 | ||
2db8e9d6 CW |
315 | stats->count++; |
316 | stats->total += obj->base.size; | |
15717de2 CW |
317 | if (!obj->bind_count) |
318 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
319 | if (obj->base.name || obj->base.dma_buf) |
320 | stats->shared += obj->base.size; | |
321 | ||
894eeecc CW |
322 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
323 | if (!drm_mm_node_allocated(&vma->node)) | |
324 | continue; | |
6313c204 | 325 | |
3272db53 | 326 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
327 | stats->global += vma->node.size; |
328 | } else { | |
329 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 330 | |
2bfa996e | 331 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 332 | continue; |
6313c204 | 333 | } |
894eeecc | 334 | |
b0decaf7 | 335 | if (i915_vma_is_active(vma)) |
894eeecc CW |
336 | stats->active += vma->node.size; |
337 | else | |
338 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
339 | } |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
b0da1b79 CW |
344 | #define print_file_stats(m, name, stats) do { \ |
345 | if (stats.count) \ | |
c44ef60e | 346 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
347 | name, \ |
348 | stats.count, \ | |
349 | stats.total, \ | |
350 | stats.active, \ | |
351 | stats.inactive, \ | |
352 | stats.global, \ | |
353 | stats.shared, \ | |
354 | stats.unbound); \ | |
355 | } while (0) | |
493018dc BV |
356 | |
357 | static void print_batch_pool_stats(struct seq_file *m, | |
358 | struct drm_i915_private *dev_priv) | |
359 | { | |
360 | struct drm_i915_gem_object *obj; | |
361 | struct file_stats stats; | |
e2f80391 | 362 | struct intel_engine_cs *engine; |
3b3f1650 | 363 | enum intel_engine_id id; |
b4ac5afc | 364 | int j; |
493018dc BV |
365 | |
366 | memset(&stats, 0, sizeof(stats)); | |
367 | ||
3b3f1650 | 368 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 369 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 370 | list_for_each_entry(obj, |
e2f80391 | 371 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
372 | batch_pool_link) |
373 | per_file_stats(0, obj, &stats); | |
374 | } | |
06fbca71 | 375 | } |
493018dc | 376 | |
b0da1b79 | 377 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
378 | } |
379 | ||
15da9565 CW |
380 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
381 | { | |
382 | struct i915_gem_context *ctx = ptr; | |
383 | int n; | |
384 | ||
385 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
386 | if (ctx->engine[n].state) | |
bf3783e5 | 387 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 388 | if (ctx->engine[n].ring) |
57e88531 | 389 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
390 | } |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static void print_context_stats(struct seq_file *m, | |
396 | struct drm_i915_private *dev_priv) | |
397 | { | |
36cdd013 | 398 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
399 | struct file_stats stats; |
400 | struct drm_file *file; | |
401 | ||
402 | memset(&stats, 0, sizeof(stats)); | |
403 | ||
36cdd013 | 404 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
405 | if (dev_priv->kernel_context) |
406 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
407 | ||
36cdd013 | 408 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
409 | struct drm_i915_file_private *fpriv = file->driver_priv; |
410 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
411 | } | |
36cdd013 | 412 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
413 | |
414 | print_file_stats(m, "[k]contexts", stats); | |
415 | } | |
416 | ||
36cdd013 | 417 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 418 | { |
36cdd013 DW |
419 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
420 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 421 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7393b7ee MA |
422 | u32 count, mapped_count, purgeable_count, dpy_count, huge_count; |
423 | u64 size, mapped_size, purgeable_size, dpy_size, huge_size; | |
6299f992 | 424 | struct drm_i915_gem_object *obj; |
7393b7ee | 425 | unsigned int page_sizes = 0; |
2db8e9d6 | 426 | struct drm_file *file; |
7393b7ee | 427 | char buf[80]; |
73aa808f CW |
428 | int ret; |
429 | ||
430 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
431 | if (ret) | |
432 | return ret; | |
433 | ||
3ef7f228 | 434 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
435 | dev_priv->mm.object_count, |
436 | dev_priv->mm.object_memory); | |
437 | ||
1544c42e CW |
438 | size = count = 0; |
439 | mapped_size = mapped_count = 0; | |
440 | purgeable_size = purgeable_count = 0; | |
7393b7ee | 441 | huge_size = huge_count = 0; |
f2123818 CW |
442 | |
443 | spin_lock(&dev_priv->mm.obj_lock); | |
444 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) { | |
2bd160a1 CW |
445 | size += obj->base.size; |
446 | ++count; | |
447 | ||
a4f5ea64 | 448 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
449 | purgeable_size += obj->base.size; |
450 | ++purgeable_count; | |
451 | } | |
452 | ||
a4f5ea64 | 453 | if (obj->mm.mapping) { |
2bd160a1 CW |
454 | mapped_count++; |
455 | mapped_size += obj->base.size; | |
be19b10d | 456 | } |
7393b7ee MA |
457 | |
458 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
459 | huge_count++; | |
460 | huge_size += obj->base.size; | |
461 | page_sizes |= obj->mm.page_sizes.sg; | |
462 | } | |
b7abb714 | 463 | } |
c44ef60e | 464 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 465 | |
2bd160a1 | 466 | size = count = dpy_size = dpy_count = 0; |
f2123818 | 467 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { |
2bd160a1 CW |
468 | size += obj->base.size; |
469 | ++count; | |
470 | ||
bd3d2252 | 471 | if (obj->pin_global) { |
2bd160a1 CW |
472 | dpy_size += obj->base.size; |
473 | ++dpy_count; | |
6299f992 | 474 | } |
2bd160a1 | 475 | |
a4f5ea64 | 476 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
477 | purgeable_size += obj->base.size; |
478 | ++purgeable_count; | |
479 | } | |
2bd160a1 | 480 | |
a4f5ea64 | 481 | if (obj->mm.mapping) { |
2bd160a1 CW |
482 | mapped_count++; |
483 | mapped_size += obj->base.size; | |
be19b10d | 484 | } |
7393b7ee MA |
485 | |
486 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
487 | huge_count++; | |
488 | huge_size += obj->base.size; | |
489 | page_sizes |= obj->mm.page_sizes.sg; | |
490 | } | |
6299f992 | 491 | } |
f2123818 CW |
492 | spin_unlock(&dev_priv->mm.obj_lock); |
493 | ||
2bd160a1 CW |
494 | seq_printf(m, "%u bound objects, %llu bytes\n", |
495 | count, size); | |
c44ef60e | 496 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 497 | purgeable_count, purgeable_size); |
2bd160a1 CW |
498 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
499 | mapped_count, mapped_size); | |
7393b7ee MA |
500 | seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n", |
501 | huge_count, | |
502 | stringify_page_sizes(page_sizes, buf, sizeof(buf)), | |
503 | huge_size); | |
bd3d2252 | 504 | seq_printf(m, "%u display objects (globally pinned), %llu bytes\n", |
2bd160a1 | 505 | dpy_count, dpy_size); |
6299f992 | 506 | |
b7128ef1 MA |
507 | seq_printf(m, "%llu [%pa] gtt total\n", |
508 | ggtt->base.total, &ggtt->mappable_end); | |
7393b7ee MA |
509 | seq_printf(m, "Supported page sizes: %s\n", |
510 | stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, | |
511 | buf, sizeof(buf))); | |
73aa808f | 512 | |
493018dc BV |
513 | seq_putc(m, '\n'); |
514 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
515 | mutex_unlock(&dev->struct_mutex); |
516 | ||
517 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 518 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
519 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
520 | struct file_stats stats; | |
c84455b4 | 521 | struct drm_i915_file_private *file_priv = file->driver_priv; |
e61e0f51 | 522 | struct i915_request *request; |
3ec2f427 | 523 | struct task_struct *task; |
2db8e9d6 | 524 | |
0caf81b5 CW |
525 | mutex_lock(&dev->struct_mutex); |
526 | ||
2db8e9d6 | 527 | memset(&stats, 0, sizeof(stats)); |
6313c204 | 528 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 529 | spin_lock(&file->table_lock); |
2db8e9d6 | 530 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 531 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
532 | /* |
533 | * Although we have a valid reference on file->pid, that does | |
534 | * not guarantee that the task_struct who called get_pid() is | |
535 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
536 | * Therefore, we need to protect this ->comm access using RCU. | |
537 | */ | |
c84455b4 | 538 | request = list_first_entry_or_null(&file_priv->mm.request_list, |
e61e0f51 | 539 | struct i915_request, |
c8659efa | 540 | client_link); |
3ec2f427 | 541 | rcu_read_lock(); |
c84455b4 CW |
542 | task = pid_task(request && request->ctx->pid ? |
543 | request->ctx->pid : file->pid, | |
544 | PIDTYPE_PID); | |
493018dc | 545 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 546 | rcu_read_unlock(); |
0caf81b5 | 547 | |
c84455b4 | 548 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 549 | } |
1d2ac403 | 550 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
aee56cff | 555 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 556 | { |
9f25d007 | 557 | struct drm_info_node *node = m->private; |
36cdd013 DW |
558 | struct drm_i915_private *dev_priv = node_to_i915(node); |
559 | struct drm_device *dev = &dev_priv->drm; | |
f2123818 | 560 | struct drm_i915_gem_object **objects; |
08c18323 | 561 | struct drm_i915_gem_object *obj; |
c44ef60e | 562 | u64 total_obj_size, total_gtt_size; |
f2123818 | 563 | unsigned long nobject, n; |
08c18323 CW |
564 | int count, ret; |
565 | ||
f2123818 CW |
566 | nobject = READ_ONCE(dev_priv->mm.object_count); |
567 | objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL); | |
568 | if (!objects) | |
569 | return -ENOMEM; | |
570 | ||
08c18323 CW |
571 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
572 | if (ret) | |
573 | return ret; | |
574 | ||
f2123818 CW |
575 | count = 0; |
576 | spin_lock(&dev_priv->mm.obj_lock); | |
577 | list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) { | |
578 | objects[count++] = obj; | |
579 | if (count == nobject) | |
580 | break; | |
581 | } | |
582 | spin_unlock(&dev_priv->mm.obj_lock); | |
583 | ||
584 | total_obj_size = total_gtt_size = 0; | |
585 | for (n = 0; n < count; n++) { | |
586 | obj = objects[n]; | |
587 | ||
267f0c90 | 588 | seq_puts(m, " "); |
08c18323 | 589 | describe_obj(m, obj); |
267f0c90 | 590 | seq_putc(m, '\n'); |
08c18323 | 591 | total_obj_size += obj->base.size; |
ca1543be | 592 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
593 | } |
594 | ||
595 | mutex_unlock(&dev->struct_mutex); | |
596 | ||
c44ef60e | 597 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 | 598 | count, total_obj_size, total_gtt_size); |
f2123818 | 599 | kvfree(objects); |
08c18323 CW |
600 | |
601 | return 0; | |
602 | } | |
603 | ||
493018dc BV |
604 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
605 | { | |
36cdd013 DW |
606 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
607 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 608 | struct drm_i915_gem_object *obj; |
e2f80391 | 609 | struct intel_engine_cs *engine; |
3b3f1650 | 610 | enum intel_engine_id id; |
8d9d5744 | 611 | int total = 0; |
b4ac5afc | 612 | int ret, j; |
493018dc BV |
613 | |
614 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
615 | if (ret) | |
616 | return ret; | |
617 | ||
3b3f1650 | 618 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 619 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
620 | int count; |
621 | ||
622 | count = 0; | |
623 | list_for_each_entry(obj, | |
e2f80391 | 624 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
625 | batch_pool_link) |
626 | count++; | |
627 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 628 | engine->name, j, count); |
8d9d5744 CW |
629 | |
630 | list_for_each_entry(obj, | |
e2f80391 | 631 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
632 | batch_pool_link) { |
633 | seq_puts(m, " "); | |
634 | describe_obj(m, obj); | |
635 | seq_putc(m, '\n'); | |
636 | } | |
637 | ||
638 | total += count; | |
06fbca71 | 639 | } |
493018dc BV |
640 | } |
641 | ||
8d9d5744 | 642 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
643 | |
644 | mutex_unlock(&dev->struct_mutex); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
80d89350 TU |
649 | static void gen8_display_interrupt_info(struct seq_file *m) |
650 | { | |
651 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
652 | int pipe; | |
653 | ||
654 | for_each_pipe(dev_priv, pipe) { | |
655 | enum intel_display_power_domain power_domain; | |
656 | ||
657 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
658 | if (!intel_display_power_get_if_enabled(dev_priv, | |
659 | power_domain)) { | |
660 | seq_printf(m, "Pipe %c power disabled\n", | |
661 | pipe_name(pipe)); | |
662 | continue; | |
663 | } | |
664 | seq_printf(m, "Pipe %c IMR:\t%08x\n", | |
665 | pipe_name(pipe), | |
666 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
667 | seq_printf(m, "Pipe %c IIR:\t%08x\n", | |
668 | pipe_name(pipe), | |
669 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
670 | seq_printf(m, "Pipe %c IER:\t%08x\n", | |
671 | pipe_name(pipe), | |
672 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
673 | ||
674 | intel_display_power_put(dev_priv, power_domain); | |
675 | } | |
676 | ||
677 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
678 | I915_READ(GEN8_DE_PORT_IMR)); | |
679 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
680 | I915_READ(GEN8_DE_PORT_IIR)); | |
681 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
682 | I915_READ(GEN8_DE_PORT_IER)); | |
683 | ||
684 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
685 | I915_READ(GEN8_DE_MISC_IMR)); | |
686 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
687 | I915_READ(GEN8_DE_MISC_IIR)); | |
688 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
689 | I915_READ(GEN8_DE_MISC_IER)); | |
690 | ||
691 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
692 | I915_READ(GEN8_PCU_IMR)); | |
693 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
694 | I915_READ(GEN8_PCU_IIR)); | |
695 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
696 | I915_READ(GEN8_PCU_IER)); | |
697 | } | |
698 | ||
2017263e BG |
699 | static int i915_interrupt_info(struct seq_file *m, void *data) |
700 | { | |
36cdd013 | 701 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 702 | struct intel_engine_cs *engine; |
3b3f1650 | 703 | enum intel_engine_id id; |
4bb05040 | 704 | int i, pipe; |
de227ef0 | 705 | |
c8c8fb33 | 706 | intel_runtime_pm_get(dev_priv); |
2017263e | 707 | |
36cdd013 | 708 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
709 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
710 | I915_READ(GEN8_MASTER_IRQ)); | |
711 | ||
712 | seq_printf(m, "Display IER:\t%08x\n", | |
713 | I915_READ(VLV_IER)); | |
714 | seq_printf(m, "Display IIR:\t%08x\n", | |
715 | I915_READ(VLV_IIR)); | |
716 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
717 | I915_READ(VLV_IIR_RW)); | |
718 | seq_printf(m, "Display IMR:\t%08x\n", | |
719 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
720 | for_each_pipe(dev_priv, pipe) { |
721 | enum intel_display_power_domain power_domain; | |
722 | ||
723 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
724 | if (!intel_display_power_get_if_enabled(dev_priv, | |
725 | power_domain)) { | |
726 | seq_printf(m, "Pipe %c power disabled\n", | |
727 | pipe_name(pipe)); | |
728 | continue; | |
729 | } | |
730 | ||
74e1ca8c VS |
731 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
732 | pipe_name(pipe), | |
733 | I915_READ(PIPESTAT(pipe))); | |
734 | ||
9c870d03 CW |
735 | intel_display_power_put(dev_priv, power_domain); |
736 | } | |
737 | ||
738 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
739 | seq_printf(m, "Port hotplug:\t%08x\n", |
740 | I915_READ(PORT_HOTPLUG_EN)); | |
741 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
742 | I915_READ(VLV_DPFLIPSTAT)); | |
743 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
744 | I915_READ(DPINVGTT)); | |
9c870d03 | 745 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
746 | |
747 | for (i = 0; i < 4; i++) { | |
748 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
749 | i, I915_READ(GEN8_GT_IMR(i))); | |
750 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
751 | i, I915_READ(GEN8_GT_IIR(i))); | |
752 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
753 | i, I915_READ(GEN8_GT_IER(i))); | |
754 | } | |
755 | ||
756 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
757 | I915_READ(GEN8_PCU_IMR)); | |
758 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
759 | I915_READ(GEN8_PCU_IIR)); | |
760 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
761 | I915_READ(GEN8_PCU_IER)); | |
80d89350 TU |
762 | } else if (INTEL_GEN(dev_priv) >= 11) { |
763 | seq_printf(m, "Master Interrupt Control: %08x\n", | |
764 | I915_READ(GEN11_GFX_MSTR_IRQ)); | |
765 | ||
766 | seq_printf(m, "Render/Copy Intr Enable: %08x\n", | |
767 | I915_READ(GEN11_RENDER_COPY_INTR_ENABLE)); | |
768 | seq_printf(m, "VCS/VECS Intr Enable: %08x\n", | |
769 | I915_READ(GEN11_VCS_VECS_INTR_ENABLE)); | |
770 | seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", | |
771 | I915_READ(GEN11_GUC_SG_INTR_ENABLE)); | |
772 | seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", | |
773 | I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE)); | |
774 | seq_printf(m, "Crypto Intr Enable:\t %08x\n", | |
775 | I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE)); | |
776 | seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", | |
777 | I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)); | |
778 | ||
779 | seq_printf(m, "Display Interrupt Control:\t%08x\n", | |
780 | I915_READ(GEN11_DISPLAY_INT_CTL)); | |
781 | ||
782 | gen8_display_interrupt_info(m); | |
36cdd013 | 783 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
784 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
785 | I915_READ(GEN8_MASTER_IRQ)); | |
786 | ||
787 | for (i = 0; i < 4; i++) { | |
788 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
789 | i, I915_READ(GEN8_GT_IMR(i))); | |
790 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
791 | i, I915_READ(GEN8_GT_IIR(i))); | |
792 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
793 | i, I915_READ(GEN8_GT_IER(i))); | |
794 | } | |
795 | ||
80d89350 | 796 | gen8_display_interrupt_info(m); |
36cdd013 | 797 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
798 | seq_printf(m, "Display IER:\t%08x\n", |
799 | I915_READ(VLV_IER)); | |
800 | seq_printf(m, "Display IIR:\t%08x\n", | |
801 | I915_READ(VLV_IIR)); | |
802 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
803 | I915_READ(VLV_IIR_RW)); | |
804 | seq_printf(m, "Display IMR:\t%08x\n", | |
805 | I915_READ(VLV_IMR)); | |
4f4631af CW |
806 | for_each_pipe(dev_priv, pipe) { |
807 | enum intel_display_power_domain power_domain; | |
808 | ||
809 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
810 | if (!intel_display_power_get_if_enabled(dev_priv, | |
811 | power_domain)) { | |
812 | seq_printf(m, "Pipe %c power disabled\n", | |
813 | pipe_name(pipe)); | |
814 | continue; | |
815 | } | |
816 | ||
7e231dbe JB |
817 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
818 | pipe_name(pipe), | |
819 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
820 | intel_display_power_put(dev_priv, power_domain); |
821 | } | |
7e231dbe JB |
822 | |
823 | seq_printf(m, "Master IER:\t%08x\n", | |
824 | I915_READ(VLV_MASTER_IER)); | |
825 | ||
826 | seq_printf(m, "Render IER:\t%08x\n", | |
827 | I915_READ(GTIER)); | |
828 | seq_printf(m, "Render IIR:\t%08x\n", | |
829 | I915_READ(GTIIR)); | |
830 | seq_printf(m, "Render IMR:\t%08x\n", | |
831 | I915_READ(GTIMR)); | |
832 | ||
833 | seq_printf(m, "PM IER:\t\t%08x\n", | |
834 | I915_READ(GEN6_PMIER)); | |
835 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
836 | I915_READ(GEN6_PMIIR)); | |
837 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
838 | I915_READ(GEN6_PMIMR)); | |
839 | ||
840 | seq_printf(m, "Port hotplug:\t%08x\n", | |
841 | I915_READ(PORT_HOTPLUG_EN)); | |
842 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
843 | I915_READ(VLV_DPFLIPSTAT)); | |
844 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
845 | I915_READ(DPINVGTT)); | |
846 | ||
36cdd013 | 847 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
848 | seq_printf(m, "Interrupt enable: %08x\n", |
849 | I915_READ(IER)); | |
850 | seq_printf(m, "Interrupt identity: %08x\n", | |
851 | I915_READ(IIR)); | |
852 | seq_printf(m, "Interrupt mask: %08x\n", | |
853 | I915_READ(IMR)); | |
055e393f | 854 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
855 | seq_printf(m, "Pipe %c stat: %08x\n", |
856 | pipe_name(pipe), | |
857 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
858 | } else { |
859 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
860 | I915_READ(DEIER)); | |
861 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
862 | I915_READ(DEIIR)); | |
863 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
864 | I915_READ(DEIMR)); | |
865 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
866 | I915_READ(SDEIER)); | |
867 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
868 | I915_READ(SDEIIR)); | |
869 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
870 | I915_READ(SDEIMR)); | |
871 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
872 | I915_READ(GTIER)); | |
873 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
874 | I915_READ(GTIIR)); | |
875 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
876 | I915_READ(GTIMR)); | |
877 | } | |
80d89350 TU |
878 | |
879 | if (INTEL_GEN(dev_priv) >= 11) { | |
880 | seq_printf(m, "RCS Intr Mask:\t %08x\n", | |
881 | I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); | |
882 | seq_printf(m, "BCS Intr Mask:\t %08x\n", | |
883 | I915_READ(GEN11_BCS_RSVD_INTR_MASK)); | |
884 | seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", | |
885 | I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); | |
886 | seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", | |
887 | I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); | |
888 | seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", | |
889 | I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); | |
890 | seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", | |
891 | I915_READ(GEN11_GUC_SG_INTR_MASK)); | |
892 | seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", | |
893 | I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK)); | |
894 | seq_printf(m, "Crypto Intr Mask:\t %08x\n", | |
895 | I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK)); | |
896 | seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", | |
897 | I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); | |
898 | ||
899 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
d5acadfe | 900 | for_each_engine(engine, dev_priv, id) { |
a2c7f6fd CW |
901 | seq_printf(m, |
902 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 903 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 904 | } |
9862e600 | 905 | } |
80d89350 | 906 | |
c8c8fb33 | 907 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 908 | |
2017263e BG |
909 | return 0; |
910 | } | |
911 | ||
a6172a80 CW |
912 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
913 | { | |
36cdd013 DW |
914 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
916 | int i, ret; |
917 | ||
918 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
919 | if (ret) | |
920 | return ret; | |
a6172a80 | 921 | |
a6172a80 CW |
922 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
923 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 924 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 925 | |
6c085a72 CW |
926 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
927 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 928 | if (!vma) |
267f0c90 | 929 | seq_puts(m, "unused"); |
c2c347a9 | 930 | else |
49ef5294 | 931 | describe_obj(m, vma->obj); |
267f0c90 | 932 | seq_putc(m, '\n'); |
a6172a80 CW |
933 | } |
934 | ||
05394f39 | 935 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
936 | return 0; |
937 | } | |
938 | ||
98a2f411 | 939 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
940 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
941 | size_t count, loff_t *pos) | |
d5442303 | 942 | { |
5a4c6f1b CW |
943 | struct i915_gpu_state *error = file->private_data; |
944 | struct drm_i915_error_state_buf str; | |
945 | ssize_t ret; | |
946 | loff_t tmp; | |
d5442303 | 947 | |
5a4c6f1b CW |
948 | if (!error) |
949 | return 0; | |
d5442303 | 950 | |
5a4c6f1b CW |
951 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
952 | if (ret) | |
953 | return ret; | |
d5442303 | 954 | |
5a4c6f1b CW |
955 | ret = i915_error_state_to_str(&str, error); |
956 | if (ret) | |
957 | goto out; | |
d5442303 | 958 | |
5a4c6f1b CW |
959 | tmp = 0; |
960 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
961 | if (ret < 0) | |
962 | goto out; | |
d5442303 | 963 | |
5a4c6f1b CW |
964 | *pos = str.start + ret; |
965 | out: | |
966 | i915_error_state_buf_release(&str); | |
967 | return ret; | |
968 | } | |
edc3d884 | 969 | |
5a4c6f1b CW |
970 | static int gpu_state_release(struct inode *inode, struct file *file) |
971 | { | |
972 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 973 | return 0; |
d5442303 DV |
974 | } |
975 | ||
5a4c6f1b | 976 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 977 | { |
090e5fe3 | 978 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 979 | struct i915_gpu_state *gpu; |
d5442303 | 980 | |
090e5fe3 CW |
981 | intel_runtime_pm_get(i915); |
982 | gpu = i915_capture_gpu_state(i915); | |
983 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
984 | if (!gpu) |
985 | return -ENOMEM; | |
d5442303 | 986 | |
5a4c6f1b | 987 | file->private_data = gpu; |
edc3d884 MK |
988 | return 0; |
989 | } | |
990 | ||
5a4c6f1b CW |
991 | static const struct file_operations i915_gpu_info_fops = { |
992 | .owner = THIS_MODULE, | |
993 | .open = i915_gpu_info_open, | |
994 | .read = gpu_state_read, | |
995 | .llseek = default_llseek, | |
996 | .release = gpu_state_release, | |
997 | }; | |
998 | ||
999 | static ssize_t | |
1000 | i915_error_state_write(struct file *filp, | |
1001 | const char __user *ubuf, | |
1002 | size_t cnt, | |
1003 | loff_t *ppos) | |
4dc955f7 | 1004 | { |
5a4c6f1b | 1005 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1006 | |
5a4c6f1b CW |
1007 | if (!error) |
1008 | return 0; | |
edc3d884 | 1009 | |
5a4c6f1b CW |
1010 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1011 | i915_reset_error_state(error->i915); | |
edc3d884 | 1012 | |
5a4c6f1b CW |
1013 | return cnt; |
1014 | } | |
edc3d884 | 1015 | |
5a4c6f1b CW |
1016 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1017 | { | |
1018 | file->private_data = i915_first_error_state(inode->i_private); | |
1019 | return 0; | |
d5442303 DV |
1020 | } |
1021 | ||
1022 | static const struct file_operations i915_error_state_fops = { | |
1023 | .owner = THIS_MODULE, | |
1024 | .open = i915_error_state_open, | |
5a4c6f1b | 1025 | .read = gpu_state_read, |
d5442303 DV |
1026 | .write = i915_error_state_write, |
1027 | .llseek = default_llseek, | |
5a4c6f1b | 1028 | .release = gpu_state_release, |
d5442303 | 1029 | }; |
98a2f411 CW |
1030 | #endif |
1031 | ||
647416f9 KC |
1032 | static int |
1033 | i915_next_seqno_set(void *data, u64 val) | |
1034 | { | |
36cdd013 DW |
1035 | struct drm_i915_private *dev_priv = data; |
1036 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1037 | int ret; |
1038 | ||
40633219 MK |
1039 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1040 | if (ret) | |
1041 | return ret; | |
1042 | ||
65c475c6 | 1043 | intel_runtime_pm_get(dev_priv); |
73cb9701 | 1044 | ret = i915_gem_set_global_seqno(dev, val); |
65c475c6 CW |
1045 | intel_runtime_pm_put(dev_priv); |
1046 | ||
40633219 MK |
1047 | mutex_unlock(&dev->struct_mutex); |
1048 | ||
647416f9 | 1049 | return ret; |
40633219 MK |
1050 | } |
1051 | ||
647416f9 | 1052 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1053 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1054 | "0x%llx\n"); |
40633219 | 1055 | |
adb4bd12 | 1056 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1057 | { |
36cdd013 | 1058 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1059 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
c8c8fb33 PZ |
1060 | int ret = 0; |
1061 | ||
1062 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1063 | |
36cdd013 | 1064 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1065 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1066 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1067 | ||
1068 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1069 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1070 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1071 | MEMSTAT_VID_SHIFT); | |
1072 | seq_printf(m, "Current P-state: %d\n", | |
1073 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1074 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
0d6fc92a | 1075 | u32 rpmodectl, freq_sts; |
666a4537 | 1076 | |
9f817501 | 1077 | mutex_lock(&dev_priv->pcu_lock); |
0d6fc92a SAK |
1078 | |
1079 | rpmodectl = I915_READ(GEN6_RP_CONTROL); | |
1080 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1081 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1082 | seq_printf(m, "HW control enabled: %s\n", | |
1083 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1084 | seq_printf(m, "SW control enabled: %s\n", | |
1085 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1086 | GEN6_RP_MEDIA_SW_MODE)); | |
1087 | ||
666a4537 WB |
1088 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
1089 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1090 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1091 | ||
1092 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1093 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1094 | ||
1095 | seq_printf(m, "current GPU freq: %d MHz\n", | |
562d9bae | 1096 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
666a4537 WB |
1097 | |
1098 | seq_printf(m, "max GPU freq: %d MHz\n", | |
562d9bae | 1099 | intel_gpu_freq(dev_priv, rps->max_freq)); |
666a4537 WB |
1100 | |
1101 | seq_printf(m, "min GPU freq: %d MHz\n", | |
562d9bae | 1102 | intel_gpu_freq(dev_priv, rps->min_freq)); |
666a4537 WB |
1103 | |
1104 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
562d9bae | 1105 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
666a4537 WB |
1106 | |
1107 | seq_printf(m, | |
1108 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1109 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
9f817501 | 1110 | mutex_unlock(&dev_priv->pcu_lock); |
36cdd013 | 1111 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1112 | u32 rp_state_limits; |
1113 | u32 gt_perf_status; | |
1114 | u32 rp_state_cap; | |
0d8f9491 | 1115 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1116 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1117 | u32 rpupei, rpcurup, rpprevup; |
1118 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1119 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1120 | int max_freq; |
1121 | ||
35040562 | 1122 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1123 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1124 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1125 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1126 | } else { | |
1127 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1128 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1129 | } | |
1130 | ||
3b8d8d91 | 1131 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1132 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1133 | |
8e8c06cd | 1134 | reqf = I915_READ(GEN6_RPNSWREQ); |
35ceabf3 | 1135 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b AG |
1136 | reqf >>= 23; |
1137 | else { | |
1138 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1139 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1140 | reqf >>= 24; |
1141 | else | |
1142 | reqf >>= 25; | |
1143 | } | |
7c59a9c1 | 1144 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1145 | |
0d8f9491 CW |
1146 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1147 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1148 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1149 | ||
ccab5c82 | 1150 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1151 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1152 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1153 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1154 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1155 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1156 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
c84b2705 TU |
1157 | cagf = intel_gpu_freq(dev_priv, |
1158 | intel_get_cagf(dev_priv, rpstat)); | |
ccab5c82 | 1159 | |
59bad947 | 1160 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1161 | |
36cdd013 | 1162 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1163 | pm_ier = I915_READ(GEN6_PMIER); |
1164 | pm_imr = I915_READ(GEN6_PMIMR); | |
1165 | pm_isr = I915_READ(GEN6_PMISR); | |
1166 | pm_iir = I915_READ(GEN6_PMIIR); | |
1167 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1168 | } else { | |
1169 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1170 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1171 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1172 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1173 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1174 | } | |
960e5465 SAK |
1175 | seq_printf(m, "Video Turbo Mode: %s\n", |
1176 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1177 | seq_printf(m, "HW control enabled: %s\n", | |
1178 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1179 | seq_printf(m, "SW control enabled: %s\n", | |
1180 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1181 | GEN6_RP_MEDIA_SW_MODE)); | |
0d8f9491 | 1182 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1183 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 | 1184 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
562d9bae | 1185 | rps->pm_intrmsk_mbz); |
3b8d8d91 | 1186 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1187 | seq_printf(m, "Render p-state ratio: %d\n", |
35ceabf3 | 1188 | (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1189 | seq_printf(m, "Render p-state VID: %d\n", |
1190 | gt_perf_status & 0xff); | |
1191 | seq_printf(m, "Render p-state limit: %d\n", | |
1192 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1193 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1194 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1195 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1196 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1197 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1198 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1199 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1200 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1201 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1202 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1203 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1204 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
562d9bae | 1205 | seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold); |
d86ed34a | 1206 | |
d6cda9c7 AG |
1207 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1208 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1209 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1210 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1211 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1212 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
562d9bae | 1213 | seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold); |
3b8d8d91 | 1214 | |
cc3f90f0 | 1215 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1216 | rp_state_cap >> 16) & 0xff; |
35ceabf3 RV |
1217 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1218 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1219 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1220 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1221 | |
1222 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
35ceabf3 RV |
1223 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1224 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1225 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1226 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1227 | |
cc3f90f0 | 1228 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1229 | rp_state_cap >> 0) & 0xff; |
35ceabf3 RV |
1230 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1231 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1232 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1233 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1234 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
562d9bae | 1235 | intel_gpu_freq(dev_priv, rps->max_freq)); |
aed242ff | 1236 | |
d86ed34a | 1237 | seq_printf(m, "Current freq: %d MHz\n", |
562d9bae | 1238 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
d86ed34a | 1239 | seq_printf(m, "Actual freq: %d MHz\n", cagf); |
aed242ff | 1240 | seq_printf(m, "Idle freq: %d MHz\n", |
562d9bae | 1241 | intel_gpu_freq(dev_priv, rps->idle_freq)); |
d86ed34a | 1242 | seq_printf(m, "Min freq: %d MHz\n", |
562d9bae | 1243 | intel_gpu_freq(dev_priv, rps->min_freq)); |
29ecd78d | 1244 | seq_printf(m, "Boost freq: %d MHz\n", |
562d9bae | 1245 | intel_gpu_freq(dev_priv, rps->boost_freq)); |
d86ed34a | 1246 | seq_printf(m, "Max freq: %d MHz\n", |
562d9bae | 1247 | intel_gpu_freq(dev_priv, rps->max_freq)); |
d86ed34a CW |
1248 | seq_printf(m, |
1249 | "efficient (RPe) frequency: %d MHz\n", | |
562d9bae | 1250 | intel_gpu_freq(dev_priv, rps->efficient_freq)); |
3b8d8d91 | 1251 | } else { |
267f0c90 | 1252 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1253 | } |
f97108d1 | 1254 | |
49cd97a3 | 1255 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1256 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1257 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1258 | ||
c8c8fb33 PZ |
1259 | intel_runtime_pm_put(dev_priv); |
1260 | return ret; | |
f97108d1 JB |
1261 | } |
1262 | ||
d636951e BW |
1263 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1264 | struct seq_file *m, | |
1265 | struct intel_instdone *instdone) | |
1266 | { | |
f9e61372 BW |
1267 | int slice; |
1268 | int subslice; | |
1269 | ||
d636951e BW |
1270 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1271 | instdone->instdone); | |
1272 | ||
1273 | if (INTEL_GEN(dev_priv) <= 3) | |
1274 | return; | |
1275 | ||
1276 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1277 | instdone->slice_common); | |
1278 | ||
1279 | if (INTEL_GEN(dev_priv) <= 6) | |
1280 | return; | |
1281 | ||
f9e61372 BW |
1282 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1283 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1284 | slice, subslice, instdone->sampler[slice][subslice]); | |
1285 | ||
1286 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1287 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1288 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1289 | } |
1290 | ||
f654449a CW |
1291 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1292 | { | |
36cdd013 | 1293 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1294 | struct intel_engine_cs *engine; |
666796da TU |
1295 | u64 acthd[I915_NUM_ENGINES]; |
1296 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1297 | struct intel_instdone instdone; |
c3232b18 | 1298 | enum intel_engine_id id; |
f654449a | 1299 | |
8af29b0c | 1300 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1301 | seq_puts(m, "Wedged\n"); |
1302 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1303 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1304 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1305 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1306 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1307 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1308 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1309 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1310 | |
4f044a88 | 1311 | if (!i915_modparams.enable_hangcheck) { |
8c185eca | 1312 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1313 | return 0; |
1314 | } | |
1315 | ||
ebbc7546 MK |
1316 | intel_runtime_pm_get(dev_priv); |
1317 | ||
3b3f1650 | 1318 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1319 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1320 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1321 | } |
1322 | ||
3b3f1650 | 1323 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1324 | |
ebbc7546 MK |
1325 | intel_runtime_pm_put(dev_priv); |
1326 | ||
8352aea3 CW |
1327 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1328 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1329 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1330 | jiffies)); | |
8352aea3 CW |
1331 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1332 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1333 | else | |
1334 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1335 | |
f73b5674 CW |
1336 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1337 | ||
3b3f1650 | 1338 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1339 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1340 | struct rb_node *rb; | |
1341 | ||
e2f80391 | 1342 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1343 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1344 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1345 | intel_engine_last_submit(engine), |
1346 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1347 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1348 | yesno(intel_engine_has_waiter(engine)), |
1349 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1350 | &dev_priv->gpu_error.missed_irq_rings)), |
1351 | yesno(engine->hangcheck.stalled)); | |
1352 | ||
61d3dc70 | 1353 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1354 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1355 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1356 | |
1357 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1358 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1359 | } | |
61d3dc70 | 1360 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1361 | |
f654449a | 1362 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1363 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1364 | (long long)acthd[id]); |
3fe3b030 MK |
1365 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1366 | hangcheck_action_to_str(engine->hangcheck.action), | |
1367 | engine->hangcheck.action, | |
1368 | jiffies_to_msecs(jiffies - | |
1369 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1370 | |
e2f80391 | 1371 | if (engine->id == RCS) { |
d636951e | 1372 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1373 | |
d636951e | 1374 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1375 | |
d636951e | 1376 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1377 | |
d636951e BW |
1378 | i915_instdone_info(dev_priv, m, |
1379 | &engine->hangcheck.instdone); | |
61642ff0 | 1380 | } |
f654449a CW |
1381 | } |
1382 | ||
1383 | return 0; | |
1384 | } | |
1385 | ||
061d06a2 MT |
1386 | static int i915_reset_info(struct seq_file *m, void *unused) |
1387 | { | |
1388 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1389 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
1390 | struct intel_engine_cs *engine; | |
1391 | enum intel_engine_id id; | |
1392 | ||
1393 | seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); | |
1394 | ||
1395 | for_each_engine(engine, dev_priv, id) { | |
1396 | seq_printf(m, "%s = %u\n", engine->name, | |
1397 | i915_reset_engine_count(error, engine)); | |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
4d85529d | 1403 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1404 | { |
36cdd013 | 1405 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1406 | u32 rgvmodectl, rstdbyctl; |
1407 | u16 crstandvid; | |
616fdb5a | 1408 | |
616fdb5a BW |
1409 | rgvmodectl = I915_READ(MEMMODECTL); |
1410 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1411 | crstandvid = I915_READ16(CRSTANDVID); | |
1412 | ||
742f491d | 1413 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1414 | seq_printf(m, "Boost freq: %d\n", |
1415 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1416 | MEMMODE_BOOST_FREQ_SHIFT); | |
1417 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1418 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1419 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1420 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1421 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1422 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1423 | seq_printf(m, "Starting frequency: P%d\n", |
1424 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1425 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1426 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1427 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1428 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1429 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1430 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1431 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1432 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1433 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1434 | case RSX_STATUS_ON: | |
267f0c90 | 1435 | seq_puts(m, "on\n"); |
88271da3 JB |
1436 | break; |
1437 | case RSX_STATUS_RC1: | |
267f0c90 | 1438 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1439 | break; |
1440 | case RSX_STATUS_RC1E: | |
267f0c90 | 1441 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1442 | break; |
1443 | case RSX_STATUS_RS1: | |
267f0c90 | 1444 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1445 | break; |
1446 | case RSX_STATUS_RS2: | |
267f0c90 | 1447 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1448 | break; |
1449 | case RSX_STATUS_RS3: | |
267f0c90 | 1450 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1451 | break; |
1452 | default: | |
267f0c90 | 1453 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1454 | break; |
1455 | } | |
f97108d1 JB |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | ||
f65367b5 | 1460 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1461 | { |
233ebf57 | 1462 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1463 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1464 | unsigned int tmp; |
b2cff0db | 1465 | |
d7a133d8 CW |
1466 | seq_printf(m, "user.bypass_count = %u\n", |
1467 | i915->uncore.user_forcewake.count); | |
1468 | ||
233ebf57 | 1469 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1470 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1471 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1472 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1473 | |
b2cff0db CW |
1474 | return 0; |
1475 | } | |
1476 | ||
1362877e MK |
1477 | static void print_rc6_res(struct seq_file *m, |
1478 | const char *title, | |
1479 | const i915_reg_t reg) | |
1480 | { | |
1481 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1482 | ||
1483 | seq_printf(m, "%s %u (%llu us)\n", | |
1484 | title, I915_READ(reg), | |
1485 | intel_rc6_residency_us(dev_priv, reg)); | |
1486 | } | |
1487 | ||
b2cff0db CW |
1488 | static int vlv_drpc_info(struct seq_file *m) |
1489 | { | |
36cdd013 | 1490 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
0d6fc92a | 1491 | u32 rcctl1, pw_status; |
669ab5aa | 1492 | |
6b312cd3 | 1493 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1494 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
1495 | ||
669ab5aa D |
1496 | seq_printf(m, "RC6 Enabled: %s\n", |
1497 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1498 | GEN6_RC_CTL_EI_MODE(1)))); | |
1499 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1500 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1501 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1502 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1503 | |
1362877e MK |
1504 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1505 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1506 | |
f65367b5 | 1507 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1508 | } |
1509 | ||
4d85529d BW |
1510 | static int gen6_drpc_info(struct seq_file *m) |
1511 | { | |
36cdd013 | 1512 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
960e5465 | 1513 | u32 gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1514 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
4d85529d | 1515 | |
75aa3f63 | 1516 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1517 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d | 1518 | |
4d85529d | 1519 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
36cdd013 | 1520 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1521 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1522 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1523 | } | |
cf632bd6 | 1524 | |
51cc9ade ID |
1525 | if (INTEL_GEN(dev_priv) <= 7) { |
1526 | mutex_lock(&dev_priv->pcu_lock); | |
1527 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, | |
1528 | &rc6vids); | |
1529 | mutex_unlock(&dev_priv->pcu_lock); | |
1530 | } | |
4d85529d | 1531 | |
fff24e21 | 1532 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1533 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1534 | seq_printf(m, "RC6 Enabled: %s\n", | |
1535 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1536 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1537 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1538 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1539 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1540 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1541 | } | |
4d85529d BW |
1542 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1543 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1544 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1545 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1546 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1547 | switch (gt_core_status & GEN6_RCn_MASK) { |
1548 | case GEN6_RC0: | |
1549 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1550 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1551 | else |
267f0c90 | 1552 | seq_puts(m, "on\n"); |
4d85529d BW |
1553 | break; |
1554 | case GEN6_RC3: | |
267f0c90 | 1555 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1556 | break; |
1557 | case GEN6_RC6: | |
267f0c90 | 1558 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1559 | break; |
1560 | case GEN6_RC7: | |
267f0c90 | 1561 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1562 | break; |
1563 | default: | |
267f0c90 | 1564 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1565 | break; |
1566 | } | |
1567 | ||
1568 | seq_printf(m, "Core Power Down: %s\n", | |
1569 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1570 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1571 | seq_printf(m, "Render Power Well: %s\n", |
1572 | (gen9_powergate_status & | |
1573 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1574 | seq_printf(m, "Media Power Well: %s\n", | |
1575 | (gen9_powergate_status & | |
1576 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1577 | } | |
cce66a28 BW |
1578 | |
1579 | /* Not exactly sure what this is */ | |
1362877e MK |
1580 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1581 | GEN6_GT_GFX_RC6_LOCKED); | |
1582 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1583 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1584 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1585 | |
51cc9ade ID |
1586 | if (INTEL_GEN(dev_priv) <= 7) { |
1587 | seq_printf(m, "RC6 voltage: %dmV\n", | |
1588 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1589 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1590 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1591 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1592 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
1593 | } | |
1594 | ||
f2dd7578 | 1595 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1596 | } |
1597 | ||
1598 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1599 | { | |
36cdd013 | 1600 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1601 | int err; |
1602 | ||
1603 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1604 | |
36cdd013 | 1605 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1606 | err = vlv_drpc_info(m); |
36cdd013 | 1607 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1608 | err = gen6_drpc_info(m); |
4d85529d | 1609 | else |
cf632bd6 CW |
1610 | err = ironlake_drpc_info(m); |
1611 | ||
1612 | intel_runtime_pm_put(dev_priv); | |
1613 | ||
1614 | return err; | |
4d85529d BW |
1615 | } |
1616 | ||
9a851789 DV |
1617 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1618 | { | |
36cdd013 | 1619 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1620 | |
1621 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1622 | dev_priv->fb_tracking.busy_bits); | |
1623 | ||
1624 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1625 | dev_priv->fb_tracking.flip_bits); | |
1626 | ||
1627 | return 0; | |
1628 | } | |
1629 | ||
b5e50c3f JB |
1630 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1631 | { | |
36cdd013 | 1632 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3138872c | 1633 | struct intel_fbc *fbc = &dev_priv->fbc; |
b5e50c3f | 1634 | |
ab309a6a MW |
1635 | if (!HAS_FBC(dev_priv)) |
1636 | return -ENODEV; | |
b5e50c3f | 1637 | |
36623ef8 | 1638 | intel_runtime_pm_get(dev_priv); |
3138872c | 1639 | mutex_lock(&fbc->lock); |
36623ef8 | 1640 | |
0e631adc | 1641 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1642 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 | 1643 | else |
3138872c CW |
1644 | seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); |
1645 | ||
1646 | if (fbc->work.scheduled) | |
1b29b7ca | 1647 | seq_printf(m, "FBC worker scheduled on vblank %llu, now %llu\n", |
3138872c CW |
1648 | fbc->work.scheduled_vblank, |
1649 | drm_crtc_vblank_count(&fbc->crtc->base)); | |
36623ef8 | 1650 | |
3fd5d1ec VS |
1651 | if (intel_fbc_is_active(dev_priv)) { |
1652 | u32 mask; | |
1653 | ||
1654 | if (INTEL_GEN(dev_priv) >= 8) | |
1655 | mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; | |
1656 | else if (INTEL_GEN(dev_priv) >= 7) | |
1657 | mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; | |
1658 | else if (INTEL_GEN(dev_priv) >= 5) | |
1659 | mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; | |
1660 | else if (IS_G4X(dev_priv)) | |
1661 | mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; | |
1662 | else | |
1663 | mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | | |
1664 | FBC_STAT_COMPRESSED); | |
1665 | ||
1666 | seq_printf(m, "Compressing: %s\n", yesno(mask)); | |
0fc6a9dc | 1667 | } |
31b9df10 | 1668 | |
3138872c | 1669 | mutex_unlock(&fbc->lock); |
36623ef8 PZ |
1670 | intel_runtime_pm_put(dev_priv); |
1671 | ||
b5e50c3f JB |
1672 | return 0; |
1673 | } | |
1674 | ||
4127dc43 | 1675 | static int i915_fbc_false_color_get(void *data, u64 *val) |
da46f936 | 1676 | { |
36cdd013 | 1677 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1678 | |
36cdd013 | 1679 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1680 | return -ENODEV; |
1681 | ||
da46f936 | 1682 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1683 | |
1684 | return 0; | |
1685 | } | |
1686 | ||
4127dc43 | 1687 | static int i915_fbc_false_color_set(void *data, u64 val) |
da46f936 | 1688 | { |
36cdd013 | 1689 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1690 | u32 reg; |
1691 | ||
36cdd013 | 1692 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1693 | return -ENODEV; |
1694 | ||
25ad93fd | 1695 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1696 | |
1697 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1698 | dev_priv->fbc.false_color = val; | |
1699 | ||
1700 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1701 | (reg | FBC_CTL_FALSE_COLOR) : | |
1702 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1703 | ||
25ad93fd | 1704 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1705 | return 0; |
1706 | } | |
1707 | ||
4127dc43 VS |
1708 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, |
1709 | i915_fbc_false_color_get, i915_fbc_false_color_set, | |
da46f936 RV |
1710 | "%llu\n"); |
1711 | ||
92d44621 PZ |
1712 | static int i915_ips_status(struct seq_file *m, void *unused) |
1713 | { | |
36cdd013 | 1714 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1715 | |
ab309a6a MW |
1716 | if (!HAS_IPS(dev_priv)) |
1717 | return -ENODEV; | |
92d44621 | 1718 | |
36623ef8 PZ |
1719 | intel_runtime_pm_get(dev_priv); |
1720 | ||
0eaa53f0 | 1721 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
4f044a88 | 1722 | yesno(i915_modparams.enable_ips)); |
0eaa53f0 | 1723 | |
36cdd013 | 1724 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1725 | seq_puts(m, "Currently: unknown\n"); |
1726 | } else { | |
1727 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1728 | seq_puts(m, "Currently: enabled\n"); | |
1729 | else | |
1730 | seq_puts(m, "Currently: disabled\n"); | |
1731 | } | |
92d44621 | 1732 | |
36623ef8 PZ |
1733 | intel_runtime_pm_put(dev_priv); |
1734 | ||
92d44621 PZ |
1735 | return 0; |
1736 | } | |
1737 | ||
4a9bef37 JB |
1738 | static int i915_sr_status(struct seq_file *m, void *unused) |
1739 | { | |
36cdd013 | 1740 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1741 | bool sr_enabled = false; |
1742 | ||
36623ef8 | 1743 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1744 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1745 | |
7342a72c CW |
1746 | if (INTEL_GEN(dev_priv) >= 9) |
1747 | /* no global SR status; inspect per-plane WM */; | |
1748 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1749 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1750 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1751 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1752 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1753 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1754 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1755 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1756 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1757 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1758 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1759 | |
9c870d03 | 1760 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1761 | intel_runtime_pm_put(dev_priv); |
1762 | ||
08c4d7fc | 1763 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1764 | |
1765 | return 0; | |
1766 | } | |
1767 | ||
7648fa99 JB |
1768 | static int i915_emon_status(struct seq_file *m, void *unused) |
1769 | { | |
36cdd013 DW |
1770 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1771 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1772 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1773 | int ret; |
1774 | ||
36cdd013 | 1775 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1776 | return -ENODEV; |
1777 | ||
de227ef0 CW |
1778 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1779 | if (ret) | |
1780 | return ret; | |
7648fa99 JB |
1781 | |
1782 | temp = i915_mch_val(dev_priv); | |
1783 | chipset = i915_chipset_val(dev_priv); | |
1784 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1785 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1786 | |
1787 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1788 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1789 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1790 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
23b2f8bb JB |
1795 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1796 | { | |
36cdd013 | 1797 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
562d9bae | 1798 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
f936ec34 | 1799 | unsigned int max_gpu_freq, min_gpu_freq; |
d586b5f4 CW |
1800 | int gpu_freq, ia_freq; |
1801 | int ret; | |
23b2f8bb | 1802 | |
ab309a6a MW |
1803 | if (!HAS_LLC(dev_priv)) |
1804 | return -ENODEV; | |
23b2f8bb | 1805 | |
5bfa0199 PZ |
1806 | intel_runtime_pm_get(dev_priv); |
1807 | ||
9f817501 | 1808 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
23b2f8bb | 1809 | if (ret) |
5bfa0199 | 1810 | goto out; |
23b2f8bb | 1811 | |
d586b5f4 CW |
1812 | min_gpu_freq = rps->min_freq; |
1813 | max_gpu_freq = rps->max_freq; | |
35ceabf3 | 1814 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
f936ec34 | 1815 | /* Convert GT frequency to 50 HZ units */ |
d586b5f4 CW |
1816 | min_gpu_freq /= GEN9_FREQ_SCALER; |
1817 | max_gpu_freq /= GEN9_FREQ_SCALER; | |
f936ec34 AG |
1818 | } |
1819 | ||
267f0c90 | 1820 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1821 | |
f936ec34 | 1822 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1823 | ia_freq = gpu_freq; |
1824 | sandybridge_pcode_read(dev_priv, | |
1825 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1826 | &ia_freq); | |
3ebecd07 | 1827 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1828 | intel_gpu_freq(dev_priv, (gpu_freq * |
35ceabf3 RV |
1829 | (IS_GEN9_BC(dev_priv) || |
1830 | IS_CANNONLAKE(dev_priv) ? | |
b976dc53 | 1831 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1832 | ((ia_freq >> 0) & 0xff) * 100, |
1833 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1834 | } |
1835 | ||
9f817501 | 1836 | mutex_unlock(&dev_priv->pcu_lock); |
23b2f8bb | 1837 | |
5bfa0199 PZ |
1838 | out: |
1839 | intel_runtime_pm_put(dev_priv); | |
1840 | return ret; | |
23b2f8bb JB |
1841 | } |
1842 | ||
44834a67 CW |
1843 | static int i915_opregion(struct seq_file *m, void *unused) |
1844 | { | |
36cdd013 DW |
1845 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1846 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1847 | struct intel_opregion *opregion = &dev_priv->opregion; |
1848 | int ret; | |
1849 | ||
1850 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1851 | if (ret) | |
0d38f009 | 1852 | goto out; |
44834a67 | 1853 | |
2455a8e4 JN |
1854 | if (opregion->header) |
1855 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1856 | |
1857 | mutex_unlock(&dev->struct_mutex); | |
1858 | ||
0d38f009 | 1859 | out: |
44834a67 CW |
1860 | return 0; |
1861 | } | |
1862 | ||
ada8f955 JN |
1863 | static int i915_vbt(struct seq_file *m, void *unused) |
1864 | { | |
36cdd013 | 1865 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1866 | |
1867 | if (opregion->vbt) | |
1868 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
37811fcc CW |
1873 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1874 | { | |
36cdd013 DW |
1875 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1876 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1877 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1878 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1879 | int ret; |
1880 | ||
1881 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1882 | if (ret) | |
1883 | return ret; | |
37811fcc | 1884 | |
0695726e | 1885 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
346fb4e0 | 1886 | if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { |
36cdd013 | 1887 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); |
25bcce94 CW |
1888 | |
1889 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1890 | fbdev_fb->base.width, | |
1891 | fbdev_fb->base.height, | |
b00c600e | 1892 | fbdev_fb->base.format->depth, |
272725c7 | 1893 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1894 | fbdev_fb->base.modifier, |
25bcce94 CW |
1895 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1896 | describe_obj(m, fbdev_fb->obj); | |
1897 | seq_putc(m, '\n'); | |
1898 | } | |
4520f53a | 1899 | #endif |
37811fcc | 1900 | |
4b096ac1 | 1901 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1902 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1903 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1904 | if (fb == fbdev_fb) | |
37811fcc CW |
1905 | continue; |
1906 | ||
c1ca506d | 1907 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1908 | fb->base.width, |
1909 | fb->base.height, | |
b00c600e | 1910 | fb->base.format->depth, |
272725c7 | 1911 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1912 | fb->base.modifier, |
747a598f | 1913 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1914 | describe_obj(m, fb->obj); |
267f0c90 | 1915 | seq_putc(m, '\n'); |
37811fcc | 1916 | } |
4b096ac1 | 1917 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1918 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1919 | |
1920 | return 0; | |
1921 | } | |
1922 | ||
7e37f889 | 1923 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1924 | { |
ef5032a0 CW |
1925 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)", |
1926 | ring->space, ring->head, ring->tail, ring->emit); | |
c9fe99bd OM |
1927 | } |
1928 | ||
e76d3630 BW |
1929 | static int i915_context_status(struct seq_file *m, void *unused) |
1930 | { | |
36cdd013 DW |
1931 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1932 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1933 | struct intel_engine_cs *engine; |
e2efd130 | 1934 | struct i915_gem_context *ctx; |
3b3f1650 | 1935 | enum intel_engine_id id; |
c3232b18 | 1936 | int ret; |
e76d3630 | 1937 | |
f3d28878 | 1938 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1939 | if (ret) |
1940 | return ret; | |
1941 | ||
829a0af2 | 1942 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
5d1808ec | 1943 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1944 | if (ctx->pid) { |
d28b99ab CW |
1945 | struct task_struct *task; |
1946 | ||
c84455b4 | 1947 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1948 | if (task) { |
1949 | seq_printf(m, "(%s [%d]) ", | |
1950 | task->comm, task->pid); | |
1951 | put_task_struct(task); | |
1952 | } | |
c84455b4 CW |
1953 | } else if (IS_ERR(ctx->file_priv)) { |
1954 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1955 | } else { |
1956 | seq_puts(m, "(kernel) "); | |
1957 | } | |
1958 | ||
bca44d80 CW |
1959 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1960 | seq_putc(m, '\n'); | |
c9fe99bd | 1961 | |
3b3f1650 | 1962 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1963 | struct intel_context *ce = &ctx->engine[engine->id]; |
1964 | ||
1965 | seq_printf(m, "%s: ", engine->name); | |
bca44d80 | 1966 | if (ce->state) |
bf3783e5 | 1967 | describe_obj(m, ce->state->obj); |
dca33ecc | 1968 | if (ce->ring) |
7e37f889 | 1969 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1970 | seq_putc(m, '\n'); |
c9fe99bd | 1971 | } |
a33afea5 | 1972 | |
a33afea5 | 1973 | seq_putc(m, '\n'); |
a168c293 BW |
1974 | } |
1975 | ||
f3d28878 | 1976 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1977 | |
1978 | return 0; | |
1979 | } | |
1980 | ||
ea16a3cd DV |
1981 | static const char *swizzle_string(unsigned swizzle) |
1982 | { | |
aee56cff | 1983 | switch (swizzle) { |
ea16a3cd DV |
1984 | case I915_BIT_6_SWIZZLE_NONE: |
1985 | return "none"; | |
1986 | case I915_BIT_6_SWIZZLE_9: | |
1987 | return "bit9"; | |
1988 | case I915_BIT_6_SWIZZLE_9_10: | |
1989 | return "bit9/bit10"; | |
1990 | case I915_BIT_6_SWIZZLE_9_11: | |
1991 | return "bit9/bit11"; | |
1992 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1993 | return "bit9/bit10/bit11"; | |
1994 | case I915_BIT_6_SWIZZLE_9_17: | |
1995 | return "bit9/bit17"; | |
1996 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1997 | return "bit9/bit10/bit17"; | |
1998 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1999 | return "unknown"; |
ea16a3cd DV |
2000 | } |
2001 | ||
2002 | return "bug"; | |
2003 | } | |
2004 | ||
2005 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2006 | { | |
36cdd013 | 2007 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2008 | |
c8c8fb33 | 2009 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2010 | |
ea16a3cd DV |
2011 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2012 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2013 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2014 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2015 | ||
36cdd013 | 2016 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2017 | seq_printf(m, "DDC = 0x%08x\n", |
2018 | I915_READ(DCC)); | |
656bfa3a DV |
2019 | seq_printf(m, "DDC2 = 0x%08x\n", |
2020 | I915_READ(DCC2)); | |
ea16a3cd DV |
2021 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2022 | I915_READ16(C0DRB3)); | |
2023 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2024 | I915_READ16(C1DRB3)); | |
36cdd013 | 2025 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2026 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2027 | I915_READ(MAD_DIMM_C0)); | |
2028 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2029 | I915_READ(MAD_DIMM_C1)); | |
2030 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2031 | I915_READ(MAD_DIMM_C2)); | |
2032 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2033 | I915_READ(TILECTL)); | |
36cdd013 | 2034 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2035 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2036 | I915_READ(GAMTARBMODE)); | |
2037 | else | |
2038 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2039 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2040 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2041 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2042 | } |
656bfa3a DV |
2043 | |
2044 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2045 | seq_puts(m, "L-shaped memory detected\n"); | |
2046 | ||
c8c8fb33 | 2047 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2048 | |
2049 | return 0; | |
2050 | } | |
2051 | ||
1c60fef5 BW |
2052 | static int per_file_ctx(int id, void *ptr, void *data) |
2053 | { | |
e2efd130 | 2054 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2055 | struct seq_file *m = data; |
ae6c4806 DV |
2056 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2057 | ||
2058 | if (!ppgtt) { | |
2059 | seq_printf(m, " no ppgtt for context %d\n", | |
2060 | ctx->user_handle); | |
2061 | return 0; | |
2062 | } | |
1c60fef5 | 2063 | |
f83d6518 OM |
2064 | if (i915_gem_context_is_default(ctx)) |
2065 | seq_puts(m, " default context:\n"); | |
2066 | else | |
821d66dd | 2067 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2068 | ppgtt->debug_dump(ppgtt, m); |
2069 | ||
2070 | return 0; | |
2071 | } | |
2072 | ||
36cdd013 DW |
2073 | static void gen8_ppgtt_info(struct seq_file *m, |
2074 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2075 | { |
77df6772 | 2076 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2077 | struct intel_engine_cs *engine; |
2078 | enum intel_engine_id id; | |
b4ac5afc | 2079 | int i; |
3cf17fc5 | 2080 | |
77df6772 BW |
2081 | if (!ppgtt) |
2082 | return; | |
2083 | ||
3b3f1650 | 2084 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2085 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2086 | for (i = 0; i < 4; i++) { |
e2f80391 | 2087 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2088 | pdp <<= 32; |
e2f80391 | 2089 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2090 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2091 | } |
2092 | } | |
2093 | } | |
2094 | ||
36cdd013 DW |
2095 | static void gen6_ppgtt_info(struct seq_file *m, |
2096 | struct drm_i915_private *dev_priv) | |
77df6772 | 2097 | { |
e2f80391 | 2098 | struct intel_engine_cs *engine; |
3b3f1650 | 2099 | enum intel_engine_id id; |
3cf17fc5 | 2100 | |
7e22dbbb | 2101 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2102 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2103 | ||
3b3f1650 | 2104 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2105 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2106 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2107 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2108 | I915_READ(RING_MODE_GEN7(engine))); | |
2109 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2110 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2111 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2112 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2113 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2114 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2115 | } |
2116 | if (dev_priv->mm.aliasing_ppgtt) { | |
2117 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2118 | ||
267f0c90 | 2119 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2120 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2121 | |
87d60b63 | 2122 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2123 | } |
1c60fef5 | 2124 | |
3cf17fc5 | 2125 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2126 | } |
2127 | ||
2128 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2129 | { | |
36cdd013 DW |
2130 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2131 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2132 | struct drm_file *file; |
637ee29e | 2133 | int ret; |
77df6772 | 2134 | |
637ee29e CW |
2135 | mutex_lock(&dev->filelist_mutex); |
2136 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2137 | if (ret) |
637ee29e CW |
2138 | goto out_unlock; |
2139 | ||
c8c8fb33 | 2140 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2141 | |
36cdd013 DW |
2142 | if (INTEL_GEN(dev_priv) >= 8) |
2143 | gen8_ppgtt_info(m, dev_priv); | |
2144 | else if (INTEL_GEN(dev_priv) >= 6) | |
2145 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2146 | |
ea91e401 MT |
2147 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2148 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2149 | struct task_struct *task; |
ea91e401 | 2150 | |
7cb5dff8 | 2151 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2152 | if (!task) { |
2153 | ret = -ESRCH; | |
637ee29e | 2154 | goto out_rpm; |
06812760 | 2155 | } |
7cb5dff8 GT |
2156 | seq_printf(m, "\nproc: %s\n", task->comm); |
2157 | put_task_struct(task); | |
ea91e401 MT |
2158 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2159 | (void *)(unsigned long)m); | |
2160 | } | |
2161 | ||
637ee29e | 2162 | out_rpm: |
c8c8fb33 | 2163 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2164 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2165 | out_unlock: |
2166 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2167 | return ret; |
3cf17fc5 DV |
2168 | } |
2169 | ||
f5a4c67d CW |
2170 | static int count_irq_waiters(struct drm_i915_private *i915) |
2171 | { | |
e2f80391 | 2172 | struct intel_engine_cs *engine; |
3b3f1650 | 2173 | enum intel_engine_id id; |
f5a4c67d | 2174 | int count = 0; |
f5a4c67d | 2175 | |
3b3f1650 | 2176 | for_each_engine(engine, i915, id) |
688e6c72 | 2177 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2178 | |
2179 | return count; | |
2180 | } | |
2181 | ||
7466c291 CW |
2182 | static const char *rps_power_to_str(unsigned int power) |
2183 | { | |
2184 | static const char * const strings[] = { | |
2185 | [LOW_POWER] = "low power", | |
2186 | [BETWEEN] = "mixed", | |
2187 | [HIGH_POWER] = "high power", | |
2188 | }; | |
2189 | ||
2190 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2191 | return "unknown"; | |
2192 | ||
2193 | return strings[power]; | |
2194 | } | |
2195 | ||
1854d5ca CW |
2196 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2197 | { | |
36cdd013 DW |
2198 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2199 | struct drm_device *dev = &dev_priv->drm; | |
562d9bae | 2200 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
1854d5ca | 2201 | struct drm_file *file; |
1854d5ca | 2202 | |
562d9bae | 2203 | seq_printf(m, "RPS enabled? %d\n", rps->enabled); |
28176ef4 CW |
2204 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2205 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2206 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7b92c1bd | 2207 | seq_printf(m, "Boosts outstanding? %d\n", |
562d9bae | 2208 | atomic_read(&rps->num_waiters)); |
7466c291 | 2209 | seq_printf(m, "Frequency requested %d\n", |
562d9bae | 2210 | intel_gpu_freq(dev_priv, rps->cur_freq)); |
7466c291 | 2211 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", |
562d9bae SAK |
2212 | intel_gpu_freq(dev_priv, rps->min_freq), |
2213 | intel_gpu_freq(dev_priv, rps->min_freq_softlimit), | |
2214 | intel_gpu_freq(dev_priv, rps->max_freq_softlimit), | |
2215 | intel_gpu_freq(dev_priv, rps->max_freq)); | |
7466c291 | 2216 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
562d9bae SAK |
2217 | intel_gpu_freq(dev_priv, rps->idle_freq), |
2218 | intel_gpu_freq(dev_priv, rps->efficient_freq), | |
2219 | intel_gpu_freq(dev_priv, rps->boost_freq)); | |
1d2ac403 DV |
2220 | |
2221 | mutex_lock(&dev->filelist_mutex); | |
1854d5ca CW |
2222 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2223 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2224 | struct task_struct *task; | |
2225 | ||
2226 | rcu_read_lock(); | |
2227 | task = pid_task(file->pid, PIDTYPE_PID); | |
7b92c1bd | 2228 | seq_printf(m, "%s [%d]: %d boosts\n", |
1854d5ca CW |
2229 | task ? task->comm : "<unknown>", |
2230 | task ? task->pid : -1, | |
562d9bae | 2231 | atomic_read(&file_priv->rps_client.boosts)); |
1854d5ca CW |
2232 | rcu_read_unlock(); |
2233 | } | |
7b92c1bd | 2234 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", |
562d9bae | 2235 | atomic_read(&rps->boosts)); |
1d2ac403 | 2236 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2237 | |
7466c291 | 2238 | if (INTEL_GEN(dev_priv) >= 6 && |
562d9bae | 2239 | rps->enabled && |
28176ef4 | 2240 | dev_priv->gt.active_requests) { |
7466c291 CW |
2241 | u32 rpup, rpupei; |
2242 | u32 rpdown, rpdownei; | |
2243 | ||
2244 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2245 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2246 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2247 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2248 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2249 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2250 | ||
2251 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
562d9bae | 2252 | rps_power_to_str(rps->power)); |
7466c291 | 2253 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", |
23f4a287 | 2254 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
562d9bae | 2255 | rps->up_threshold); |
7466c291 | 2256 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", |
23f4a287 | 2257 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
562d9bae | 2258 | rps->down_threshold); |
7466c291 CW |
2259 | } else { |
2260 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2261 | } | |
2262 | ||
8d3afd7d | 2263 | return 0; |
1854d5ca CW |
2264 | } |
2265 | ||
63573eb7 BW |
2266 | static int i915_llc(struct seq_file *m, void *data) |
2267 | { | |
36cdd013 | 2268 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2269 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2270 | |
36cdd013 | 2271 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2272 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2273 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2274 | |
2275 | return 0; | |
2276 | } | |
2277 | ||
0509ead1 AS |
2278 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2279 | { | |
2280 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
56ffc742 | 2281 | struct drm_printer p; |
0509ead1 | 2282 | |
ab309a6a MW |
2283 | if (!HAS_HUC(dev_priv)) |
2284 | return -ENODEV; | |
0509ead1 | 2285 | |
56ffc742 MW |
2286 | p = drm_seq_file_printer(m); |
2287 | intel_uc_fw_dump(&dev_priv->huc.fw, &p); | |
0509ead1 | 2288 | |
3582ad13 | 2289 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2290 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2291 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2292 | |
2293 | return 0; | |
2294 | } | |
2295 | ||
fdf5d357 AD |
2296 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2297 | { | |
36cdd013 | 2298 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
56ffc742 | 2299 | struct drm_printer p; |
fdf5d357 AD |
2300 | u32 tmp, i; |
2301 | ||
ab309a6a MW |
2302 | if (!HAS_GUC(dev_priv)) |
2303 | return -ENODEV; | |
fdf5d357 | 2304 | |
56ffc742 MW |
2305 | p = drm_seq_file_printer(m); |
2306 | intel_uc_fw_dump(&dev_priv->guc.fw, &p); | |
fdf5d357 | 2307 | |
3582ad13 | 2308 | intel_runtime_pm_get(dev_priv); |
2309 | ||
fdf5d357 AD |
2310 | tmp = I915_READ(GUC_STATUS); |
2311 | ||
2312 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2313 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2314 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2315 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2316 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2317 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2318 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2319 | seq_puts(m, "\nScratch registers:\n"); | |
2320 | for (i = 0; i < 16; i++) | |
2321 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2322 | ||
3582ad13 | 2323 | intel_runtime_pm_put(dev_priv); |
2324 | ||
fdf5d357 AD |
2325 | return 0; |
2326 | } | |
2327 | ||
5aa1ee4b AG |
2328 | static void i915_guc_log_info(struct seq_file *m, |
2329 | struct drm_i915_private *dev_priv) | |
2330 | { | |
2331 | struct intel_guc *guc = &dev_priv->guc; | |
2332 | ||
2333 | seq_puts(m, "\nGuC logging stats:\n"); | |
2334 | ||
2335 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2336 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2337 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2338 | ||
2339 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2340 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2341 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2342 | ||
2343 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2344 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2345 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2346 | ||
2347 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2348 | guc->log.flush_interrupt_count); | |
2349 | ||
6a96be24 MW |
2350 | seq_printf(m, "\tRelay full count: %u\n", |
2351 | guc->log.relay.full_count); | |
5aa1ee4b AG |
2352 | } |
2353 | ||
8b417c26 DG |
2354 | static void i915_guc_client_info(struct seq_file *m, |
2355 | struct drm_i915_private *dev_priv, | |
5afc8b49 | 2356 | struct intel_guc_client *client) |
8b417c26 | 2357 | { |
e2f80391 | 2358 | struct intel_engine_cs *engine; |
c18468c4 | 2359 | enum intel_engine_id id; |
8b417c26 | 2360 | uint64_t tot = 0; |
8b417c26 | 2361 | |
b09935a6 OM |
2362 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2363 | client->priority, client->stage_id, client->proc_desc_offset); | |
59db36cf MW |
2364 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", |
2365 | client->doorbell_id, client->doorbell_offset); | |
8b417c26 | 2366 | |
3b3f1650 | 2367 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2368 | u64 submissions = client->submissions[id]; |
2369 | tot += submissions; | |
8b417c26 | 2370 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2371 | submissions, engine->name); |
8b417c26 DG |
2372 | } |
2373 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2374 | } | |
2375 | ||
a8b9370f OM |
2376 | static int i915_guc_info(struct seq_file *m, void *data) |
2377 | { | |
2378 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2379 | const struct intel_guc *guc = &dev_priv->guc; | |
a8b9370f | 2380 | |
ab309a6a MW |
2381 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2382 | return -ENODEV; | |
2383 | ||
2384 | GEM_BUG_ON(!guc->execbuf_client); | |
a8b9370f | 2385 | |
9636f6db | 2386 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2387 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2388 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2389 | |
334636c6 CW |
2390 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2391 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
e78c9175 CW |
2392 | if (guc->preempt_client) { |
2393 | seq_printf(m, "\nGuC preempt client @ %p:\n", | |
2394 | guc->preempt_client); | |
2395 | i915_guc_client_info(m, dev_priv, guc->preempt_client); | |
2396 | } | |
8b417c26 | 2397 | |
5aa1ee4b AG |
2398 | i915_guc_log_info(m, dev_priv); |
2399 | ||
8b417c26 DG |
2400 | /* Add more as required ... */ |
2401 | ||
2402 | return 0; | |
2403 | } | |
2404 | ||
a8b9370f | 2405 | static int i915_guc_stage_pool(struct seq_file *m, void *data) |
4c7e77fc | 2406 | { |
36cdd013 | 2407 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a8b9370f OM |
2408 | const struct intel_guc *guc = &dev_priv->guc; |
2409 | struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; | |
5afc8b49 | 2410 | struct intel_guc_client *client = guc->execbuf_client; |
a8b9370f OM |
2411 | unsigned int tmp; |
2412 | int index; | |
4c7e77fc | 2413 | |
ab309a6a MW |
2414 | if (!USES_GUC_SUBMISSION(dev_priv)) |
2415 | return -ENODEV; | |
4c7e77fc | 2416 | |
a8b9370f OM |
2417 | for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { |
2418 | struct intel_engine_cs *engine; | |
2419 | ||
2420 | if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)) | |
2421 | continue; | |
2422 | ||
2423 | seq_printf(m, "GuC stage descriptor %u:\n", index); | |
2424 | seq_printf(m, "\tIndex: %u\n", desc->stage_id); | |
2425 | seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); | |
2426 | seq_printf(m, "\tPriority: %d\n", desc->priority); | |
2427 | seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); | |
2428 | seq_printf(m, "\tEngines used: 0x%x\n", | |
2429 | desc->engines_used); | |
2430 | seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", | |
2431 | desc->db_trigger_phy, | |
2432 | desc->db_trigger_cpu, | |
2433 | desc->db_trigger_uk); | |
2434 | seq_printf(m, "\tProcess descriptor: 0x%x\n", | |
2435 | desc->process_desc); | |
9a09485d | 2436 | seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", |
a8b9370f OM |
2437 | desc->wq_addr, desc->wq_size); |
2438 | seq_putc(m, '\n'); | |
2439 | ||
2440 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { | |
2441 | u32 guc_engine_id = engine->guc_id; | |
2442 | struct guc_execlist_context *lrc = | |
2443 | &desc->lrc[guc_engine_id]; | |
2444 | ||
2445 | seq_printf(m, "\t%s LRC:\n", engine->name); | |
2446 | seq_printf(m, "\t\tContext desc: 0x%x\n", | |
2447 | lrc->context_desc); | |
2448 | seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); | |
2449 | seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); | |
2450 | seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); | |
2451 | seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); | |
2452 | seq_putc(m, '\n'); | |
2453 | } | |
2454 | } | |
2455 | ||
2456 | return 0; | |
2457 | } | |
2458 | ||
4c7e77fc AD |
2459 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2460 | { | |
ac58d2ab DCS |
2461 | struct drm_info_node *node = m->private; |
2462 | struct drm_i915_private *dev_priv = node_to_i915(node); | |
2463 | bool dump_load_err = !!node->info_ent->data; | |
2464 | struct drm_i915_gem_object *obj = NULL; | |
2465 | u32 *log; | |
2466 | int i = 0; | |
4c7e77fc | 2467 | |
ab309a6a MW |
2468 | if (!HAS_GUC(dev_priv)) |
2469 | return -ENODEV; | |
2470 | ||
ac58d2ab DCS |
2471 | if (dump_load_err) |
2472 | obj = dev_priv->guc.load_err_log; | |
2473 | else if (dev_priv->guc.log.vma) | |
2474 | obj = dev_priv->guc.log.vma->obj; | |
4c7e77fc | 2475 | |
ac58d2ab DCS |
2476 | if (!obj) |
2477 | return 0; | |
4c7e77fc | 2478 | |
ac58d2ab DCS |
2479 | log = i915_gem_object_pin_map(obj, I915_MAP_WC); |
2480 | if (IS_ERR(log)) { | |
2481 | DRM_DEBUG("Failed to pin object\n"); | |
2482 | seq_puts(m, "(log data unaccessible)\n"); | |
2483 | return PTR_ERR(log); | |
4c7e77fc AD |
2484 | } |
2485 | ||
ac58d2ab DCS |
2486 | for (i = 0; i < obj->base.size / sizeof(u32); i += 4) |
2487 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2488 | *(log + i), *(log + i + 1), | |
2489 | *(log + i + 2), *(log + i + 3)); | |
2490 | ||
4c7e77fc AD |
2491 | seq_putc(m, '\n'); |
2492 | ||
ac58d2ab DCS |
2493 | i915_gem_object_unpin_map(obj); |
2494 | ||
4c7e77fc AD |
2495 | return 0; |
2496 | } | |
2497 | ||
4977a287 | 2498 | static int i915_guc_log_level_get(void *data, u64 *val) |
685534ef | 2499 | { |
bcc36d8a | 2500 | struct drm_i915_private *dev_priv = data; |
685534ef | 2501 | |
86aa8247 | 2502 | if (!USES_GUC(dev_priv)) |
ab309a6a MW |
2503 | return -ENODEV; |
2504 | ||
4977a287 | 2505 | *val = intel_guc_log_level_get(&dev_priv->guc.log); |
685534ef SAK |
2506 | |
2507 | return 0; | |
2508 | } | |
2509 | ||
4977a287 | 2510 | static int i915_guc_log_level_set(void *data, u64 val) |
685534ef | 2511 | { |
bcc36d8a | 2512 | struct drm_i915_private *dev_priv = data; |
685534ef | 2513 | |
86aa8247 | 2514 | if (!USES_GUC(dev_priv)) |
ab309a6a MW |
2515 | return -ENODEV; |
2516 | ||
4977a287 | 2517 | return intel_guc_log_level_set(&dev_priv->guc.log, val); |
685534ef SAK |
2518 | } |
2519 | ||
4977a287 MW |
2520 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops, |
2521 | i915_guc_log_level_get, i915_guc_log_level_set, | |
685534ef SAK |
2522 | "%lld\n"); |
2523 | ||
4977a287 MW |
2524 | static int i915_guc_log_relay_open(struct inode *inode, struct file *file) |
2525 | { | |
2526 | struct drm_i915_private *dev_priv = inode->i_private; | |
2527 | ||
2528 | if (!USES_GUC(dev_priv)) | |
2529 | return -ENODEV; | |
2530 | ||
2531 | file->private_data = &dev_priv->guc.log; | |
2532 | ||
2533 | return intel_guc_log_relay_open(&dev_priv->guc.log); | |
2534 | } | |
2535 | ||
2536 | static ssize_t | |
2537 | i915_guc_log_relay_write(struct file *filp, | |
2538 | const char __user *ubuf, | |
2539 | size_t cnt, | |
2540 | loff_t *ppos) | |
2541 | { | |
2542 | struct intel_guc_log *log = filp->private_data; | |
2543 | ||
2544 | intel_guc_log_relay_flush(log); | |
2545 | ||
2546 | return cnt; | |
2547 | } | |
2548 | ||
2549 | static int i915_guc_log_relay_release(struct inode *inode, struct file *file) | |
2550 | { | |
2551 | struct drm_i915_private *dev_priv = inode->i_private; | |
2552 | ||
2553 | intel_guc_log_relay_close(&dev_priv->guc.log); | |
2554 | ||
2555 | return 0; | |
2556 | } | |
2557 | ||
2558 | static const struct file_operations i915_guc_log_relay_fops = { | |
2559 | .owner = THIS_MODULE, | |
2560 | .open = i915_guc_log_relay_open, | |
2561 | .write = i915_guc_log_relay_write, | |
2562 | .release = i915_guc_log_relay_release, | |
2563 | }; | |
2564 | ||
b86bef20 CW |
2565 | static const char *psr2_live_status(u32 val) |
2566 | { | |
2567 | static const char * const live_status[] = { | |
2568 | "IDLE", | |
2569 | "CAPTURE", | |
2570 | "CAPTURE_FS", | |
2571 | "SLEEP", | |
2572 | "BUFON_FW", | |
2573 | "ML_UP", | |
2574 | "SU_STANDBY", | |
2575 | "FAST_SLEEP", | |
2576 | "DEEP_SLEEP", | |
2577 | "BUF_ON", | |
2578 | "TG_ON" | |
2579 | }; | |
2580 | ||
2581 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2582 | if (val < ARRAY_SIZE(live_status)) | |
2583 | return live_status[val]; | |
2584 | ||
2585 | return "unknown"; | |
2586 | } | |
2587 | ||
e91fd8c6 RV |
2588 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2589 | { | |
36cdd013 | 2590 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2591 | u32 psrperf = 0; |
a6cbdb8e RV |
2592 | u32 stat[3]; |
2593 | enum pipe pipe; | |
a031d709 | 2594 | bool enabled = false; |
c9ef291a | 2595 | bool sink_support; |
e91fd8c6 | 2596 | |
ab309a6a MW |
2597 | if (!HAS_PSR(dev_priv)) |
2598 | return -ENODEV; | |
3553a8ea | 2599 | |
c9ef291a DP |
2600 | sink_support = dev_priv->psr.sink_support; |
2601 | seq_printf(m, "Sink_Support: %s\n", yesno(sink_support)); | |
2602 | if (!sink_support) | |
2603 | return 0; | |
2604 | ||
c8c8fb33 PZ |
2605 | intel_runtime_pm_get(dev_priv); |
2606 | ||
fa128fa6 | 2607 | mutex_lock(&dev_priv->psr.lock); |
2807cf69 | 2608 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
fa128fa6 DV |
2609 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2610 | dev_priv->psr.busy_frontbuffer_bits); | |
2611 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2612 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2613 | |
7e3eb599 NV |
2614 | if (HAS_DDI(dev_priv)) { |
2615 | if (dev_priv->psr.psr2_support) | |
2616 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2617 | else | |
2618 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2619 | } else { | |
3553a8ea | 2620 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2621 | enum transcoder cpu_transcoder = |
2622 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2623 | enum intel_display_power_domain power_domain; | |
2624 | ||
2625 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2626 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2627 | power_domain)) | |
2628 | continue; | |
2629 | ||
3553a8ea DL |
2630 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2631 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2632 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2633 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2634 | enabled = true; | |
9c870d03 CW |
2635 | |
2636 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2637 | } |
2638 | } | |
60e5ffe3 RV |
2639 | |
2640 | seq_printf(m, "Main link in standby mode: %s\n", | |
2641 | yesno(dev_priv->psr.link_standby)); | |
2642 | ||
a6cbdb8e RV |
2643 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2644 | ||
36cdd013 | 2645 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2646 | for_each_pipe(dev_priv, pipe) { |
2647 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2648 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2649 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2650 | } | |
2651 | seq_puts(m, "\n"); | |
e91fd8c6 | 2652 | |
05eec3c2 RV |
2653 | /* |
2654 | * VLV/CHV PSR has no kind of performance counter | |
2655 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2656 | */ | |
36cdd013 | 2657 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2658 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2659 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2660 | |
2661 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2662 | } | |
6ba1f9e1 | 2663 | if (dev_priv->psr.psr2_support) { |
861023e0 | 2664 | u32 psr2 = I915_READ(EDP_PSR2_STATUS); |
b86bef20 | 2665 | |
861023e0 | 2666 | seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n", |
b86bef20 | 2667 | psr2, psr2_live_status(psr2)); |
6ba1f9e1 | 2668 | } |
fa128fa6 | 2669 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2670 | |
c8c8fb33 | 2671 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2672 | return 0; |
2673 | } | |
2674 | ||
d2e216d0 RV |
2675 | static int i915_sink_crc(struct seq_file *m, void *data) |
2676 | { | |
36cdd013 DW |
2677 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2678 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2679 | struct intel_connector *connector; |
3f6a5e1e | 2680 | struct drm_connector_list_iter conn_iter; |
d2e216d0 | 2681 | struct intel_dp *intel_dp = NULL; |
10bf0a38 | 2682 | struct drm_modeset_acquire_ctx ctx; |
d2e216d0 RV |
2683 | int ret; |
2684 | u8 crc[6]; | |
2685 | ||
10bf0a38 ML |
2686 | drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); |
2687 | ||
3f6a5e1e | 2688 | drm_connector_list_iter_begin(dev, &conn_iter); |
10bf0a38 | 2689 | |
3f6a5e1e | 2690 | for_each_intel_connector_iter(connector, &conn_iter) { |
26c17cf6 | 2691 | struct drm_crtc *crtc; |
10bf0a38 | 2692 | struct drm_connector_state *state; |
93313538 | 2693 | struct intel_crtc_state *crtc_state; |
d2e216d0 | 2694 | |
10bf0a38 | 2695 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2696 | continue; |
2697 | ||
10bf0a38 ML |
2698 | retry: |
2699 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); | |
2700 | if (ret) | |
2701 | goto err; | |
2702 | ||
2703 | state = connector->base.state; | |
2704 | if (!state->best_encoder) | |
b6ae3c7c PZ |
2705 | continue; |
2706 | ||
10bf0a38 ML |
2707 | crtc = state->crtc; |
2708 | ret = drm_modeset_lock(&crtc->mutex, &ctx); | |
2709 | if (ret) | |
2710 | goto err; | |
2711 | ||
93313538 ML |
2712 | crtc_state = to_intel_crtc_state(crtc->state); |
2713 | if (!crtc_state->base.active) | |
d2e216d0 RV |
2714 | continue; |
2715 | ||
93313538 ML |
2716 | /* |
2717 | * We need to wait for all crtc updates to complete, to make | |
2718 | * sure any pending modesets and plane updates are completed. | |
2719 | */ | |
2720 | if (crtc_state->base.commit) { | |
2721 | ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done); | |
2722 | ||
2723 | if (ret) | |
2724 | goto err; | |
2725 | } | |
2726 | ||
10bf0a38 | 2727 | intel_dp = enc_to_intel_dp(state->best_encoder); |
d2e216d0 | 2728 | |
93313538 | 2729 | ret = intel_dp_sink_crc(intel_dp, crtc_state, crc); |
d2e216d0 | 2730 | if (ret) |
10bf0a38 | 2731 | goto err; |
d2e216d0 RV |
2732 | |
2733 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2734 | crc[0], crc[1], crc[2], | |
2735 | crc[3], crc[4], crc[5]); | |
2736 | goto out; | |
10bf0a38 ML |
2737 | |
2738 | err: | |
2739 | if (ret == -EDEADLK) { | |
2740 | ret = drm_modeset_backoff(&ctx); | |
2741 | if (!ret) | |
2742 | goto retry; | |
2743 | } | |
2744 | goto out; | |
d2e216d0 RV |
2745 | } |
2746 | ret = -ENODEV; | |
2747 | out: | |
3f6a5e1e | 2748 | drm_connector_list_iter_end(&conn_iter); |
10bf0a38 ML |
2749 | drm_modeset_drop_locks(&ctx); |
2750 | drm_modeset_acquire_fini(&ctx); | |
2751 | ||
d2e216d0 RV |
2752 | return ret; |
2753 | } | |
2754 | ||
ec013e7f JB |
2755 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2756 | { | |
36cdd013 | 2757 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
d38014ea | 2758 | unsigned long long power; |
ec013e7f JB |
2759 | u32 units; |
2760 | ||
36cdd013 | 2761 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2762 | return -ENODEV; |
2763 | ||
36623ef8 PZ |
2764 | intel_runtime_pm_get(dev_priv); |
2765 | ||
d38014ea GKB |
2766 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { |
2767 | intel_runtime_pm_put(dev_priv); | |
2768 | return -ENODEV; | |
2769 | } | |
2770 | ||
2771 | units = (power & 0x1f00) >> 8; | |
ec013e7f | 2772 | power = I915_READ(MCH_SECP_NRG_STTS); |
d38014ea | 2773 | power = (1000000 * power) >> units; /* convert to uJ */ |
ec013e7f | 2774 | |
36623ef8 PZ |
2775 | intel_runtime_pm_put(dev_priv); |
2776 | ||
d38014ea | 2777 | seq_printf(m, "%llu", power); |
371db66a PZ |
2778 | |
2779 | return 0; | |
2780 | } | |
2781 | ||
6455c870 | 2782 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2783 | { |
36cdd013 | 2784 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2785 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2786 | |
a156e64d CW |
2787 | if (!HAS_RUNTIME_PM(dev_priv)) |
2788 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2789 | |
6f56103d CW |
2790 | seq_printf(m, "GPU idle: %s (epoch %u)\n", |
2791 | yesno(!dev_priv->gt.awake), dev_priv->gt.epoch); | |
371db66a | 2792 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2793 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2794 | #ifdef CONFIG_PM |
a6aaec8b | 2795 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2796 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2797 | #else |
2798 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2799 | #endif | |
a156e64d | 2800 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2801 | pci_power_name(pdev->current_state), |
2802 | pdev->current_state); | |
371db66a | 2803 | |
ec013e7f JB |
2804 | return 0; |
2805 | } | |
2806 | ||
1da51581 ID |
2807 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2808 | { | |
36cdd013 | 2809 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2810 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2811 | int i; | |
2812 | ||
2813 | mutex_lock(&power_domains->lock); | |
2814 | ||
2815 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2816 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2817 | struct i915_power_well *power_well; | |
2818 | enum intel_display_power_domain power_domain; | |
2819 | ||
2820 | power_well = &power_domains->power_wells[i]; | |
2821 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2822 | power_well->count); | |
2823 | ||
8385c2ec | 2824 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2825 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2826 | intel_display_power_domain_str(power_domain), |
1da51581 | 2827 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2828 | } |
2829 | ||
2830 | mutex_unlock(&power_domains->lock); | |
2831 | ||
2832 | return 0; | |
2833 | } | |
2834 | ||
b7cec66d DL |
2835 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2836 | { | |
36cdd013 | 2837 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2838 | struct intel_csr *csr; |
2839 | ||
ab309a6a MW |
2840 | if (!HAS_CSR(dev_priv)) |
2841 | return -ENODEV; | |
b7cec66d DL |
2842 | |
2843 | csr = &dev_priv->csr; | |
2844 | ||
6fb403de MK |
2845 | intel_runtime_pm_get(dev_priv); |
2846 | ||
b7cec66d DL |
2847 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2848 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2849 | ||
2850 | if (!csr->dmc_payload) | |
6fb403de | 2851 | goto out; |
b7cec66d DL |
2852 | |
2853 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2854 | CSR_VERSION_MINOR(csr->version)); | |
2855 | ||
48de568c MK |
2856 | if (IS_KABYLAKE(dev_priv) || |
2857 | (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) { | |
8337206d DL |
2858 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2859 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2860 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2861 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2862 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2863 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2864 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2865 | } |
2866 | ||
6fb403de MK |
2867 | out: |
2868 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2869 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2870 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2871 | ||
8337206d DL |
2872 | intel_runtime_pm_put(dev_priv); |
2873 | ||
b7cec66d DL |
2874 | return 0; |
2875 | } | |
2876 | ||
53f5e3ca JB |
2877 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2878 | struct drm_display_mode *mode) | |
2879 | { | |
2880 | int i; | |
2881 | ||
2882 | for (i = 0; i < tabs; i++) | |
2883 | seq_putc(m, '\t'); | |
2884 | ||
2885 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2886 | mode->base.id, mode->name, | |
2887 | mode->vrefresh, mode->clock, | |
2888 | mode->hdisplay, mode->hsync_start, | |
2889 | mode->hsync_end, mode->htotal, | |
2890 | mode->vdisplay, mode->vsync_start, | |
2891 | mode->vsync_end, mode->vtotal, | |
2892 | mode->type, mode->flags); | |
2893 | } | |
2894 | ||
2895 | static void intel_encoder_info(struct seq_file *m, | |
2896 | struct intel_crtc *intel_crtc, | |
2897 | struct intel_encoder *intel_encoder) | |
2898 | { | |
36cdd013 DW |
2899 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2900 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2901 | struct drm_crtc *crtc = &intel_crtc->base; |
2902 | struct intel_connector *intel_connector; | |
2903 | struct drm_encoder *encoder; | |
2904 | ||
2905 | encoder = &intel_encoder->base; | |
2906 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2907 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2908 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2909 | struct drm_connector *connector = &intel_connector->base; | |
2910 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2911 | connector->base.id, | |
c23cc417 | 2912 | connector->name, |
53f5e3ca JB |
2913 | drm_get_connector_status_name(connector->status)); |
2914 | if (connector->status == connector_status_connected) { | |
2915 | struct drm_display_mode *mode = &crtc->mode; | |
2916 | seq_printf(m, ", mode:\n"); | |
2917 | intel_seq_print_mode(m, 2, mode); | |
2918 | } else { | |
2919 | seq_putc(m, '\n'); | |
2920 | } | |
2921 | } | |
2922 | } | |
2923 | ||
2924 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2925 | { | |
36cdd013 DW |
2926 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2927 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2928 | struct drm_crtc *crtc = &intel_crtc->base; |
2929 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2930 | struct drm_plane_state *plane_state = crtc->primary->state; |
2931 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2932 | |
23a48d53 | 2933 | if (fb) |
5aa8a937 | 2934 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2935 | fb->base.id, plane_state->src_x >> 16, |
2936 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2937 | else |
2938 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2939 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2940 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2941 | } | |
2942 | ||
2943 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2944 | { | |
2945 | struct drm_display_mode *mode = panel->fixed_mode; | |
2946 | ||
2947 | seq_printf(m, "\tfixed mode:\n"); | |
2948 | intel_seq_print_mode(m, 2, mode); | |
2949 | } | |
2950 | ||
2951 | static void intel_dp_info(struct seq_file *m, | |
2952 | struct intel_connector *intel_connector) | |
2953 | { | |
2954 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2955 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2956 | ||
2957 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2958 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2959 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2960 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2961 | |
2962 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2963 | &intel_dp->aux); | |
53f5e3ca JB |
2964 | } |
2965 | ||
9a148a96 LY |
2966 | static void intel_dp_mst_info(struct seq_file *m, |
2967 | struct intel_connector *intel_connector) | |
2968 | { | |
2969 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2970 | struct intel_dp_mst_encoder *intel_mst = | |
2971 | enc_to_mst(&intel_encoder->base); | |
2972 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2973 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2974 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2975 | intel_connector->port); | |
2976 | ||
2977 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2978 | } | |
2979 | ||
53f5e3ca JB |
2980 | static void intel_hdmi_info(struct seq_file *m, |
2981 | struct intel_connector *intel_connector) | |
2982 | { | |
2983 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2984 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2985 | ||
742f491d | 2986 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2987 | } |
2988 | ||
2989 | static void intel_lvds_info(struct seq_file *m, | |
2990 | struct intel_connector *intel_connector) | |
2991 | { | |
2992 | intel_panel_info(m, &intel_connector->panel); | |
2993 | } | |
2994 | ||
2995 | static void intel_connector_info(struct seq_file *m, | |
2996 | struct drm_connector *connector) | |
2997 | { | |
2998 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2999 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3000 | struct drm_display_mode *mode; |
53f5e3ca JB |
3001 | |
3002 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3003 | connector->base.id, connector->name, |
53f5e3ca JB |
3004 | drm_get_connector_status_name(connector->status)); |
3005 | if (connector->status == connector_status_connected) { | |
3006 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3007 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3008 | connector->display_info.width_mm, | |
3009 | connector->display_info.height_mm); | |
3010 | seq_printf(m, "\tsubpixel order: %s\n", | |
3011 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3012 | seq_printf(m, "\tCEA rev: %d\n", | |
3013 | connector->display_info.cea_rev); | |
3014 | } | |
ee648a74 | 3015 | |
77d1f615 | 3016 | if (!intel_encoder) |
ee648a74 ML |
3017 | return; |
3018 | ||
3019 | switch (connector->connector_type) { | |
3020 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3021 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3022 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3023 | intel_dp_mst_info(m, intel_connector); | |
3024 | else | |
3025 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3026 | break; |
3027 | case DRM_MODE_CONNECTOR_LVDS: | |
3028 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3029 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3030 | break; |
3031 | case DRM_MODE_CONNECTOR_HDMIA: | |
3032 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
7e732cac | 3033 | intel_encoder->type == INTEL_OUTPUT_DDI) |
ee648a74 ML |
3034 | intel_hdmi_info(m, intel_connector); |
3035 | break; | |
3036 | default: | |
3037 | break; | |
36cd7444 | 3038 | } |
53f5e3ca | 3039 | |
f103fc7d JB |
3040 | seq_printf(m, "\tmodes:\n"); |
3041 | list_for_each_entry(mode, &connector->modes, head) | |
3042 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3043 | } |
3044 | ||
3abc4e09 RF |
3045 | static const char *plane_type(enum drm_plane_type type) |
3046 | { | |
3047 | switch (type) { | |
3048 | case DRM_PLANE_TYPE_OVERLAY: | |
3049 | return "OVL"; | |
3050 | case DRM_PLANE_TYPE_PRIMARY: | |
3051 | return "PRI"; | |
3052 | case DRM_PLANE_TYPE_CURSOR: | |
3053 | return "CUR"; | |
3054 | /* | |
3055 | * Deliberately omitting default: to generate compiler warnings | |
3056 | * when a new drm_plane_type gets added. | |
3057 | */ | |
3058 | } | |
3059 | ||
3060 | return "unknown"; | |
3061 | } | |
3062 | ||
3063 | static const char *plane_rotation(unsigned int rotation) | |
3064 | { | |
3065 | static char buf[48]; | |
3066 | /* | |
c2c446ad | 3067 | * According to doc only one DRM_MODE_ROTATE_ is allowed but this |
3abc4e09 RF |
3068 | * will print them all to visualize if the values are misused |
3069 | */ | |
3070 | snprintf(buf, sizeof(buf), | |
3071 | "%s%s%s%s%s%s(0x%08x)", | |
c2c446ad RF |
3072 | (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", |
3073 | (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", | |
3074 | (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", | |
3075 | (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", | |
3076 | (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", | |
3077 | (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3078 | rotation); |
3079 | ||
3080 | return buf; | |
3081 | } | |
3082 | ||
3083 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3084 | { | |
36cdd013 DW |
3085 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3086 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3087 | struct intel_plane *intel_plane; |
3088 | ||
3089 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3090 | struct drm_plane_state *state; | |
3091 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3092 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3093 | |
3094 | if (!plane->state) { | |
3095 | seq_puts(m, "plane->state is NULL!\n"); | |
3096 | continue; | |
3097 | } | |
3098 | ||
3099 | state = plane->state; | |
3100 | ||
90844f00 | 3101 | if (state->fb) { |
438b74a5 VS |
3102 | drm_get_format_name(state->fb->format->format, |
3103 | &format_name); | |
90844f00 | 3104 | } else { |
b3c11ac2 | 3105 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3106 | } |
3107 | ||
3abc4e09 RF |
3108 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3109 | plane->base.id, | |
3110 | plane_type(intel_plane->base.type), | |
3111 | state->crtc_x, state->crtc_y, | |
3112 | state->crtc_w, state->crtc_h, | |
3113 | (state->src_x >> 16), | |
3114 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3115 | (state->src_y >> 16), | |
3116 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3117 | (state->src_w >> 16), | |
3118 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3119 | (state->src_h >> 16), | |
3120 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3121 | format_name.str, |
3abc4e09 RF |
3122 | plane_rotation(state->rotation)); |
3123 | } | |
3124 | } | |
3125 | ||
3126 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3127 | { | |
3128 | struct intel_crtc_state *pipe_config; | |
3129 | int num_scalers = intel_crtc->num_scalers; | |
3130 | int i; | |
3131 | ||
3132 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3133 | ||
3134 | /* Not all platformas have a scaler */ | |
3135 | if (num_scalers) { | |
3136 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3137 | num_scalers, | |
3138 | pipe_config->scaler_state.scaler_users, | |
3139 | pipe_config->scaler_state.scaler_id); | |
3140 | ||
58415918 | 3141 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3142 | struct intel_scaler *sc = |
3143 | &pipe_config->scaler_state.scalers[i]; | |
3144 | ||
3145 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3146 | i, yesno(sc->in_use), sc->mode); | |
3147 | } | |
3148 | seq_puts(m, "\n"); | |
3149 | } else { | |
3150 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3151 | } | |
3152 | } | |
3153 | ||
53f5e3ca JB |
3154 | static int i915_display_info(struct seq_file *m, void *unused) |
3155 | { | |
36cdd013 DW |
3156 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3157 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3158 | struct intel_crtc *crtc; |
53f5e3ca | 3159 | struct drm_connector *connector; |
3f6a5e1e | 3160 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3161 | |
b0e5ddf3 | 3162 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3163 | seq_printf(m, "CRTC info\n"); |
3164 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3165 | for_each_intel_crtc(dev, crtc) { |
f77076c9 | 3166 | struct intel_crtc_state *pipe_config; |
53f5e3ca | 3167 | |
3f6a5e1e | 3168 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3169 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3170 | ||
3abc4e09 | 3171 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3172 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3173 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3174 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3175 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3176 | ||
f77076c9 | 3177 | if (pipe_config->base.active) { |
cd5dcbf1 VS |
3178 | struct intel_plane *cursor = |
3179 | to_intel_plane(crtc->base.cursor); | |
3180 | ||
065f2ec2 CW |
3181 | intel_crtc_info(m, crtc); |
3182 | ||
cd5dcbf1 VS |
3183 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", |
3184 | yesno(cursor->base.state->visible), | |
3185 | cursor->base.state->crtc_x, | |
3186 | cursor->base.state->crtc_y, | |
3187 | cursor->base.state->crtc_w, | |
3188 | cursor->base.state->crtc_h, | |
3189 | cursor->cursor.base); | |
3abc4e09 RF |
3190 | intel_scaler_info(m, crtc); |
3191 | intel_plane_info(m, crtc); | |
a23dc658 | 3192 | } |
cace841c DV |
3193 | |
3194 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3195 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3196 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3197 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3198 | } |
3199 | ||
3200 | seq_printf(m, "\n"); | |
3201 | seq_printf(m, "Connector info\n"); | |
3202 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3203 | mutex_lock(&dev->mode_config.mutex); |
3204 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3205 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3206 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3207 | drm_connector_list_iter_end(&conn_iter); |
3208 | mutex_unlock(&dev->mode_config.mutex); | |
3209 | ||
b0e5ddf3 | 3210 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3211 | |
3212 | return 0; | |
3213 | } | |
3214 | ||
1b36595f CW |
3215 | static int i915_engine_info(struct seq_file *m, void *unused) |
3216 | { | |
3217 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3218 | struct intel_engine_cs *engine; | |
3b3f1650 | 3219 | enum intel_engine_id id; |
f636edb2 | 3220 | struct drm_printer p; |
1b36595f | 3221 | |
9c870d03 CW |
3222 | intel_runtime_pm_get(dev_priv); |
3223 | ||
6f56103d CW |
3224 | seq_printf(m, "GT awake? %s (epoch %u)\n", |
3225 | yesno(dev_priv->gt.awake), dev_priv->gt.epoch); | |
f73b5674 CW |
3226 | seq_printf(m, "Global active requests: %d\n", |
3227 | dev_priv->gt.active_requests); | |
f577a03b LL |
3228 | seq_printf(m, "CS timestamp frequency: %u kHz\n", |
3229 | dev_priv->info.cs_timestamp_frequency_khz); | |
f73b5674 | 3230 | |
f636edb2 CW |
3231 | p = drm_seq_file_printer(m); |
3232 | for_each_engine(engine, dev_priv, id) | |
0db18b17 | 3233 | intel_engine_dump(engine, &p, "%s\n", engine->name); |
1b36595f | 3234 | |
9c870d03 CW |
3235 | intel_runtime_pm_put(dev_priv); |
3236 | ||
1b36595f CW |
3237 | return 0; |
3238 | } | |
3239 | ||
79e9cd5f LL |
3240 | static int i915_rcs_topology(struct seq_file *m, void *unused) |
3241 | { | |
3242 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3243 | struct drm_printer p = drm_seq_file_printer(m); | |
3244 | ||
3245 | intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p); | |
3246 | ||
3247 | return 0; | |
3248 | } | |
3249 | ||
c5418a8b CW |
3250 | static int i915_shrinker_info(struct seq_file *m, void *unused) |
3251 | { | |
3252 | struct drm_i915_private *i915 = node_to_i915(m->private); | |
3253 | ||
3254 | seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks); | |
3255 | seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch); | |
3256 | ||
3257 | return 0; | |
3258 | } | |
3259 | ||
728e29d7 DV |
3260 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3261 | { | |
36cdd013 DW |
3262 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3263 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3264 | int i; |
3265 | ||
3266 | drm_modeset_lock_all(dev); | |
3267 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3268 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3269 | ||
3270 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3271 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3272 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3273 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3274 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3275 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3276 | pll->state.hw_state.dpll_md); |
3277 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3278 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3279 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3280 | } |
3281 | drm_modeset_unlock_all(dev); | |
3282 | ||
3283 | return 0; | |
3284 | } | |
3285 | ||
1ed1ef9d | 3286 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3287 | { |
3288 | int i; | |
3289 | int ret; | |
e2f80391 | 3290 | struct intel_engine_cs *engine; |
36cdd013 DW |
3291 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3292 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3293 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3294 | enum intel_engine_id id; |
888b5995 | 3295 | |
888b5995 AS |
3296 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3297 | if (ret) | |
3298 | return ret; | |
3299 | ||
3300 | intel_runtime_pm_get(dev_priv); | |
3301 | ||
33136b06 | 3302 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3303 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3304 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3305 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3306 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3307 | i915_reg_t addr; |
3308 | u32 mask, value, read; | |
2fa60f6d | 3309 | bool ok; |
888b5995 | 3310 | |
33136b06 AS |
3311 | addr = workarounds->reg[i].addr; |
3312 | mask = workarounds->reg[i].mask; | |
3313 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3314 | read = I915_READ(addr); |
3315 | ok = (value & mask) == (read & mask); | |
3316 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3317 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3318 | } |
3319 | ||
3320 | intel_runtime_pm_put(dev_priv); | |
3321 | mutex_unlock(&dev->struct_mutex); | |
3322 | ||
3323 | return 0; | |
3324 | } | |
3325 | ||
d2d4f39b KM |
3326 | static int i915_ipc_status_show(struct seq_file *m, void *data) |
3327 | { | |
3328 | struct drm_i915_private *dev_priv = m->private; | |
3329 | ||
3330 | seq_printf(m, "Isochronous Priority Control: %s\n", | |
3331 | yesno(dev_priv->ipc_enabled)); | |
3332 | return 0; | |
3333 | } | |
3334 | ||
3335 | static int i915_ipc_status_open(struct inode *inode, struct file *file) | |
3336 | { | |
3337 | struct drm_i915_private *dev_priv = inode->i_private; | |
3338 | ||
3339 | if (!HAS_IPC(dev_priv)) | |
3340 | return -ENODEV; | |
3341 | ||
3342 | return single_open(file, i915_ipc_status_show, dev_priv); | |
3343 | } | |
3344 | ||
3345 | static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, | |
3346 | size_t len, loff_t *offp) | |
3347 | { | |
3348 | struct seq_file *m = file->private_data; | |
3349 | struct drm_i915_private *dev_priv = m->private; | |
3350 | int ret; | |
3351 | bool enable; | |
3352 | ||
3353 | ret = kstrtobool_from_user(ubuf, len, &enable); | |
3354 | if (ret < 0) | |
3355 | return ret; | |
3356 | ||
3357 | intel_runtime_pm_get(dev_priv); | |
3358 | if (!dev_priv->ipc_enabled && enable) | |
3359 | DRM_INFO("Enabling IPC: WM will be proper only after next commit\n"); | |
3360 | dev_priv->wm.distrust_bios_wm = true; | |
3361 | dev_priv->ipc_enabled = enable; | |
3362 | intel_enable_ipc(dev_priv); | |
3363 | intel_runtime_pm_put(dev_priv); | |
3364 | ||
3365 | return len; | |
3366 | } | |
3367 | ||
3368 | static const struct file_operations i915_ipc_status_fops = { | |
3369 | .owner = THIS_MODULE, | |
3370 | .open = i915_ipc_status_open, | |
3371 | .read = seq_read, | |
3372 | .llseek = seq_lseek, | |
3373 | .release = single_release, | |
3374 | .write = i915_ipc_status_write | |
3375 | }; | |
3376 | ||
c5511e44 DL |
3377 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3378 | { | |
36cdd013 DW |
3379 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3380 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3381 | struct skl_ddb_allocation *ddb; |
3382 | struct skl_ddb_entry *entry; | |
3383 | enum pipe pipe; | |
3384 | int plane; | |
3385 | ||
36cdd013 | 3386 | if (INTEL_GEN(dev_priv) < 9) |
ab309a6a | 3387 | return -ENODEV; |
2fcffe19 | 3388 | |
c5511e44 DL |
3389 | drm_modeset_lock_all(dev); |
3390 | ||
3391 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3392 | ||
3393 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3394 | ||
3395 | for_each_pipe(dev_priv, pipe) { | |
3396 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3397 | ||
8b364b41 | 3398 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3399 | entry = &ddb->plane[pipe][plane]; |
3400 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3401 | entry->start, entry->end, | |
3402 | skl_ddb_entry_size(entry)); | |
3403 | } | |
3404 | ||
4969d33e | 3405 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3406 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3407 | entry->end, skl_ddb_entry_size(entry)); | |
3408 | } | |
3409 | ||
3410 | drm_modeset_unlock_all(dev); | |
3411 | ||
3412 | return 0; | |
3413 | } | |
3414 | ||
a54746e3 | 3415 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3416 | struct drm_device *dev, |
3417 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3418 | { |
fac5e23e | 3419 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3420 | struct i915_drrs *drrs = &dev_priv->drrs; |
3421 | int vrefresh = 0; | |
26875fe5 | 3422 | struct drm_connector *connector; |
3f6a5e1e | 3423 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3424 | |
3f6a5e1e DV |
3425 | drm_connector_list_iter_begin(dev, &conn_iter); |
3426 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3427 | if (connector->state->crtc != &intel_crtc->base) |
3428 | continue; | |
3429 | ||
3430 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3431 | } |
3f6a5e1e | 3432 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3433 | |
3434 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3435 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3436 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3437 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3438 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3439 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3440 | else | |
3441 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3442 | ||
3443 | seq_puts(m, "\n\n"); | |
3444 | ||
f77076c9 | 3445 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3446 | struct intel_panel *panel; |
3447 | ||
3448 | mutex_lock(&drrs->mutex); | |
3449 | /* DRRS Supported */ | |
3450 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3451 | ||
3452 | /* disable_drrs() will make drrs->dp NULL */ | |
3453 | if (!drrs->dp) { | |
ce6e2137 R |
3454 | seq_puts(m, "Idleness DRRS: Disabled\n"); |
3455 | if (dev_priv->psr.enabled) | |
3456 | seq_puts(m, | |
3457 | "\tAs PSR is enabled, DRRS is not enabled\n"); | |
a54746e3 VK |
3458 | mutex_unlock(&drrs->mutex); |
3459 | return; | |
3460 | } | |
3461 | ||
3462 | panel = &drrs->dp->attached_connector->panel; | |
3463 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3464 | drrs->busy_frontbuffer_bits); | |
3465 | ||
3466 | seq_puts(m, "\n\t\t"); | |
3467 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3468 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3469 | vrefresh = panel->fixed_mode->vrefresh; | |
3470 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3471 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3472 | vrefresh = panel->downclock_mode->vrefresh; | |
3473 | } else { | |
3474 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3475 | drrs->refresh_rate_type); | |
3476 | mutex_unlock(&drrs->mutex); | |
3477 | return; | |
3478 | } | |
3479 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3480 | ||
3481 | seq_puts(m, "\n\t\t"); | |
3482 | mutex_unlock(&drrs->mutex); | |
3483 | } else { | |
3484 | /* DRRS not supported. Print the VBT parameter*/ | |
3485 | seq_puts(m, "\tDRRS Supported : No"); | |
3486 | } | |
3487 | seq_puts(m, "\n"); | |
3488 | } | |
3489 | ||
3490 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3491 | { | |
36cdd013 DW |
3492 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3493 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3494 | struct intel_crtc *intel_crtc; |
3495 | int active_crtc_cnt = 0; | |
3496 | ||
26875fe5 | 3497 | drm_modeset_lock_all(dev); |
a54746e3 | 3498 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3499 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3500 | active_crtc_cnt++; |
3501 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3502 | ||
3503 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3504 | } | |
a54746e3 | 3505 | } |
26875fe5 | 3506 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3507 | |
3508 | if (!active_crtc_cnt) | |
3509 | seq_puts(m, "No active crtc found\n"); | |
3510 | ||
3511 | return 0; | |
3512 | } | |
3513 | ||
11bed958 DA |
3514 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3515 | { | |
36cdd013 DW |
3516 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3517 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3518 | struct intel_encoder *intel_encoder; |
3519 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3520 | struct drm_connector *connector; |
3f6a5e1e | 3521 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3522 | |
3f6a5e1e DV |
3523 | drm_connector_list_iter_begin(dev, &conn_iter); |
3524 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3525 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3526 | continue; |
b6dabe3b ML |
3527 | |
3528 | intel_encoder = intel_attached_encoder(connector); | |
3529 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3530 | continue; | |
3531 | ||
3532 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3533 | if (!intel_dig_port->dp.can_mst) |
3534 | continue; | |
b6dabe3b | 3535 | |
40ae80cc | 3536 | seq_printf(m, "MST Source Port %c\n", |
8f4f2797 | 3537 | port_name(intel_dig_port->base.port)); |
11bed958 DA |
3538 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3539 | } | |
3f6a5e1e DV |
3540 | drm_connector_list_iter_end(&conn_iter); |
3541 | ||
11bed958 DA |
3542 | return 0; |
3543 | } | |
3544 | ||
eb3394fa | 3545 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3546 | const char __user *ubuf, |
3547 | size_t len, loff_t *offp) | |
eb3394fa TP |
3548 | { |
3549 | char *input_buffer; | |
3550 | int status = 0; | |
eb3394fa TP |
3551 | struct drm_device *dev; |
3552 | struct drm_connector *connector; | |
3f6a5e1e | 3553 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3554 | struct intel_dp *intel_dp; |
3555 | int val = 0; | |
3556 | ||
9aaffa34 | 3557 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3558 | |
eb3394fa TP |
3559 | if (len == 0) |
3560 | return 0; | |
3561 | ||
261aeba8 GT |
3562 | input_buffer = memdup_user_nul(ubuf, len); |
3563 | if (IS_ERR(input_buffer)) | |
3564 | return PTR_ERR(input_buffer); | |
eb3394fa | 3565 | |
eb3394fa TP |
3566 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3567 | ||
3f6a5e1e DV |
3568 | drm_connector_list_iter_begin(dev, &conn_iter); |
3569 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3570 | struct intel_encoder *encoder; |
3571 | ||
eb3394fa TP |
3572 | if (connector->connector_type != |
3573 | DRM_MODE_CONNECTOR_DisplayPort) | |
3574 | continue; | |
3575 | ||
a874b6a3 ML |
3576 | encoder = to_intel_encoder(connector->encoder); |
3577 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3578 | continue; | |
3579 | ||
3580 | if (encoder && connector->status == connector_status_connected) { | |
3581 | intel_dp = enc_to_intel_dp(&encoder->base); | |
eb3394fa TP |
3582 | status = kstrtoint(input_buffer, 10, &val); |
3583 | if (status < 0) | |
3f6a5e1e | 3584 | break; |
eb3394fa TP |
3585 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3586 | /* To prevent erroneous activation of the compliance | |
3587 | * testing code, only accept an actual value of 1 here | |
3588 | */ | |
3589 | if (val == 1) | |
c1617abc | 3590 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3591 | else |
c1617abc | 3592 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3593 | } |
3594 | } | |
3f6a5e1e | 3595 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3596 | kfree(input_buffer); |
3597 | if (status < 0) | |
3598 | return status; | |
3599 | ||
3600 | *offp += len; | |
3601 | return len; | |
3602 | } | |
3603 | ||
3604 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3605 | { | |
e4006713 AS |
3606 | struct drm_i915_private *dev_priv = m->private; |
3607 | struct drm_device *dev = &dev_priv->drm; | |
eb3394fa | 3608 | struct drm_connector *connector; |
3f6a5e1e | 3609 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3610 | struct intel_dp *intel_dp; |
3611 | ||
3f6a5e1e DV |
3612 | drm_connector_list_iter_begin(dev, &conn_iter); |
3613 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3614 | struct intel_encoder *encoder; |
3615 | ||
eb3394fa TP |
3616 | if (connector->connector_type != |
3617 | DRM_MODE_CONNECTOR_DisplayPort) | |
3618 | continue; | |
3619 | ||
a874b6a3 ML |
3620 | encoder = to_intel_encoder(connector->encoder); |
3621 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3622 | continue; | |
3623 | ||
3624 | if (encoder && connector->status == connector_status_connected) { | |
3625 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3626 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3627 | seq_puts(m, "1"); |
3628 | else | |
3629 | seq_puts(m, "0"); | |
3630 | } else | |
3631 | seq_puts(m, "0"); | |
3632 | } | |
3f6a5e1e | 3633 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3634 | |
3635 | return 0; | |
3636 | } | |
3637 | ||
3638 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3639 | struct file *file) |
eb3394fa | 3640 | { |
36cdd013 | 3641 | return single_open(file, i915_displayport_test_active_show, |
e4006713 | 3642 | inode->i_private); |
eb3394fa TP |
3643 | } |
3644 | ||
3645 | static const struct file_operations i915_displayport_test_active_fops = { | |
3646 | .owner = THIS_MODULE, | |
3647 | .open = i915_displayport_test_active_open, | |
3648 | .read = seq_read, | |
3649 | .llseek = seq_lseek, | |
3650 | .release = single_release, | |
3651 | .write = i915_displayport_test_active_write | |
3652 | }; | |
3653 | ||
3654 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3655 | { | |
e4006713 AS |
3656 | struct drm_i915_private *dev_priv = m->private; |
3657 | struct drm_device *dev = &dev_priv->drm; | |
eb3394fa | 3658 | struct drm_connector *connector; |
3f6a5e1e | 3659 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3660 | struct intel_dp *intel_dp; |
3661 | ||
3f6a5e1e DV |
3662 | drm_connector_list_iter_begin(dev, &conn_iter); |
3663 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3664 | struct intel_encoder *encoder; |
3665 | ||
eb3394fa TP |
3666 | if (connector->connector_type != |
3667 | DRM_MODE_CONNECTOR_DisplayPort) | |
3668 | continue; | |
3669 | ||
a874b6a3 ML |
3670 | encoder = to_intel_encoder(connector->encoder); |
3671 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3672 | continue; | |
3673 | ||
3674 | if (encoder && connector->status == connector_status_connected) { | |
3675 | intel_dp = enc_to_intel_dp(&encoder->base); | |
b48a5ba9 MN |
3676 | if (intel_dp->compliance.test_type == |
3677 | DP_TEST_LINK_EDID_READ) | |
3678 | seq_printf(m, "%lx", | |
3679 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3680 | else if (intel_dp->compliance.test_type == |
3681 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3682 | seq_printf(m, "hdisplay: %d\n", | |
3683 | intel_dp->compliance.test_data.hdisplay); | |
3684 | seq_printf(m, "vdisplay: %d\n", | |
3685 | intel_dp->compliance.test_data.vdisplay); | |
3686 | seq_printf(m, "bpc: %u\n", | |
3687 | intel_dp->compliance.test_data.bpc); | |
3688 | } | |
eb3394fa TP |
3689 | } else |
3690 | seq_puts(m, "0"); | |
3691 | } | |
3f6a5e1e | 3692 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3693 | |
3694 | return 0; | |
3695 | } | |
e4006713 | 3696 | DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); |
eb3394fa TP |
3697 | |
3698 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3699 | { | |
e4006713 AS |
3700 | struct drm_i915_private *dev_priv = m->private; |
3701 | struct drm_device *dev = &dev_priv->drm; | |
eb3394fa | 3702 | struct drm_connector *connector; |
3f6a5e1e | 3703 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3704 | struct intel_dp *intel_dp; |
3705 | ||
3f6a5e1e DV |
3706 | drm_connector_list_iter_begin(dev, &conn_iter); |
3707 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3708 | struct intel_encoder *encoder; |
3709 | ||
eb3394fa TP |
3710 | if (connector->connector_type != |
3711 | DRM_MODE_CONNECTOR_DisplayPort) | |
3712 | continue; | |
3713 | ||
a874b6a3 ML |
3714 | encoder = to_intel_encoder(connector->encoder); |
3715 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3716 | continue; | |
3717 | ||
3718 | if (encoder && connector->status == connector_status_connected) { | |
3719 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3720 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3721 | } else |
3722 | seq_puts(m, "0"); | |
3723 | } | |
3f6a5e1e | 3724 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3725 | |
3726 | return 0; | |
3727 | } | |
e4006713 | 3728 | DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); |
eb3394fa | 3729 | |
97e94b22 | 3730 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3731 | { |
36cdd013 DW |
3732 | struct drm_i915_private *dev_priv = m->private; |
3733 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3734 | int level; |
de38b95c VS |
3735 | int num_levels; |
3736 | ||
36cdd013 | 3737 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3738 | num_levels = 3; |
36cdd013 | 3739 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3740 | num_levels = 1; |
04548cba VS |
3741 | else if (IS_G4X(dev_priv)) |
3742 | num_levels = 3; | |
de38b95c | 3743 | else |
5db94019 | 3744 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3745 | |
3746 | drm_modeset_lock_all(dev); | |
3747 | ||
3748 | for (level = 0; level < num_levels; level++) { | |
3749 | unsigned int latency = wm[level]; | |
3750 | ||
97e94b22 DL |
3751 | /* |
3752 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3753 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3754 | */ |
04548cba VS |
3755 | if (INTEL_GEN(dev_priv) >= 9 || |
3756 | IS_VALLEYVIEW(dev_priv) || | |
3757 | IS_CHERRYVIEW(dev_priv) || | |
3758 | IS_G4X(dev_priv)) | |
97e94b22 DL |
3759 | latency *= 10; |
3760 | else if (level > 0) | |
369a1342 VS |
3761 | latency *= 5; |
3762 | ||
3763 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3764 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3765 | } |
3766 | ||
3767 | drm_modeset_unlock_all(dev); | |
3768 | } | |
3769 | ||
3770 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3771 | { | |
36cdd013 | 3772 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3773 | const uint16_t *latencies; |
3774 | ||
36cdd013 | 3775 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3776 | latencies = dev_priv->wm.skl_latency; |
3777 | else | |
36cdd013 | 3778 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3779 | |
97e94b22 | 3780 | wm_latency_show(m, latencies); |
369a1342 VS |
3781 | |
3782 | return 0; | |
3783 | } | |
3784 | ||
3785 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3786 | { | |
36cdd013 | 3787 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3788 | const uint16_t *latencies; |
3789 | ||
36cdd013 | 3790 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3791 | latencies = dev_priv->wm.skl_latency; |
3792 | else | |
36cdd013 | 3793 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3794 | |
97e94b22 | 3795 | wm_latency_show(m, latencies); |
369a1342 VS |
3796 | |
3797 | return 0; | |
3798 | } | |
3799 | ||
3800 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3801 | { | |
36cdd013 | 3802 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3803 | const uint16_t *latencies; |
3804 | ||
36cdd013 | 3805 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3806 | latencies = dev_priv->wm.skl_latency; |
3807 | else | |
36cdd013 | 3808 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3809 | |
97e94b22 | 3810 | wm_latency_show(m, latencies); |
369a1342 VS |
3811 | |
3812 | return 0; | |
3813 | } | |
3814 | ||
3815 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3816 | { | |
36cdd013 | 3817 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3818 | |
04548cba | 3819 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
369a1342 VS |
3820 | return -ENODEV; |
3821 | ||
36cdd013 | 3822 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3823 | } |
3824 | ||
3825 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3826 | { | |
36cdd013 | 3827 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3828 | |
36cdd013 | 3829 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3830 | return -ENODEV; |
3831 | ||
36cdd013 | 3832 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3833 | } |
3834 | ||
3835 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3836 | { | |
36cdd013 | 3837 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3838 | |
36cdd013 | 3839 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3840 | return -ENODEV; |
3841 | ||
36cdd013 | 3842 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3843 | } |
3844 | ||
3845 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3846 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3847 | { |
3848 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3849 | struct drm_i915_private *dev_priv = m->private; |
3850 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3851 | uint16_t new[8] = { 0 }; |
de38b95c | 3852 | int num_levels; |
369a1342 VS |
3853 | int level; |
3854 | int ret; | |
3855 | char tmp[32]; | |
3856 | ||
36cdd013 | 3857 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3858 | num_levels = 3; |
36cdd013 | 3859 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3860 | num_levels = 1; |
04548cba VS |
3861 | else if (IS_G4X(dev_priv)) |
3862 | num_levels = 3; | |
de38b95c | 3863 | else |
5db94019 | 3864 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 3865 | |
369a1342 VS |
3866 | if (len >= sizeof(tmp)) |
3867 | return -EINVAL; | |
3868 | ||
3869 | if (copy_from_user(tmp, ubuf, len)) | |
3870 | return -EFAULT; | |
3871 | ||
3872 | tmp[len] = '\0'; | |
3873 | ||
97e94b22 DL |
3874 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3875 | &new[0], &new[1], &new[2], &new[3], | |
3876 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3877 | if (ret != num_levels) |
3878 | return -EINVAL; | |
3879 | ||
3880 | drm_modeset_lock_all(dev); | |
3881 | ||
3882 | for (level = 0; level < num_levels; level++) | |
3883 | wm[level] = new[level]; | |
3884 | ||
3885 | drm_modeset_unlock_all(dev); | |
3886 | ||
3887 | return len; | |
3888 | } | |
3889 | ||
3890 | ||
3891 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3892 | size_t len, loff_t *offp) | |
3893 | { | |
3894 | struct seq_file *m = file->private_data; | |
36cdd013 | 3895 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3896 | uint16_t *latencies; |
369a1342 | 3897 | |
36cdd013 | 3898 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3899 | latencies = dev_priv->wm.skl_latency; |
3900 | else | |
36cdd013 | 3901 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
3902 | |
3903 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3904 | } |
3905 | ||
3906 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3907 | size_t len, loff_t *offp) | |
3908 | { | |
3909 | struct seq_file *m = file->private_data; | |
36cdd013 | 3910 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 3911 | uint16_t *latencies; |
369a1342 | 3912 | |
36cdd013 | 3913 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3914 | latencies = dev_priv->wm.skl_latency; |
3915 | else | |
36cdd013 | 3916 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
3917 | |
3918 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
3919 | } |
3920 | ||
3921 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3922 | size_t len, loff_t *offp) | |
3923 | { | |
3924 | struct seq_file *m = file->private_data; | |
36cdd013 | 3925 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3926 | uint16_t *latencies; |
3927 | ||
36cdd013 | 3928 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3929 | latencies = dev_priv->wm.skl_latency; |
3930 | else | |
36cdd013 | 3931 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3932 | |
97e94b22 | 3933 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
3934 | } |
3935 | ||
3936 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3937 | .owner = THIS_MODULE, | |
3938 | .open = pri_wm_latency_open, | |
3939 | .read = seq_read, | |
3940 | .llseek = seq_lseek, | |
3941 | .release = single_release, | |
3942 | .write = pri_wm_latency_write | |
3943 | }; | |
3944 | ||
3945 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3946 | .owner = THIS_MODULE, | |
3947 | .open = spr_wm_latency_open, | |
3948 | .read = seq_read, | |
3949 | .llseek = seq_lseek, | |
3950 | .release = single_release, | |
3951 | .write = spr_wm_latency_write | |
3952 | }; | |
3953 | ||
3954 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3955 | .owner = THIS_MODULE, | |
3956 | .open = cur_wm_latency_open, | |
3957 | .read = seq_read, | |
3958 | .llseek = seq_lseek, | |
3959 | .release = single_release, | |
3960 | .write = cur_wm_latency_write | |
3961 | }; | |
3962 | ||
647416f9 KC |
3963 | static int |
3964 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3965 | { |
36cdd013 | 3966 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 3967 | |
d98c52cf | 3968 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 3969 | |
647416f9 | 3970 | return 0; |
f3cd474b CW |
3971 | } |
3972 | ||
647416f9 KC |
3973 | static int |
3974 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3975 | { |
598b6b5a CW |
3976 | struct drm_i915_private *i915 = data; |
3977 | struct intel_engine_cs *engine; | |
3978 | unsigned int tmp; | |
d46c0517 | 3979 | |
b8d24a06 MK |
3980 | /* |
3981 | * There is no safeguard against this debugfs entry colliding | |
3982 | * with the hangcheck calling same i915_handle_error() in | |
3983 | * parallel, causing an explosion. For now we assume that the | |
3984 | * test harness is responsible enough not to inject gpu hangs | |
3985 | * while it is writing to 'i915_wedged' | |
3986 | */ | |
3987 | ||
598b6b5a | 3988 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
3989 | return -EAGAIN; |
3990 | ||
598b6b5a CW |
3991 | for_each_engine_masked(engine, i915, val, tmp) { |
3992 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
3993 | engine->hangcheck.stalled = true; | |
3994 | } | |
3995 | ||
c27557ab TU |
3996 | i915_handle_error(i915, val, "Manually set wedged engine mask = %llx", |
3997 | val); | |
d46c0517 | 3998 | |
598b6b5a | 3999 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
4000 | I915_RESET_HANDOFF, |
4001 | TASK_UNINTERRUPTIBLE); | |
4002 | ||
647416f9 | 4003 | return 0; |
f3cd474b CW |
4004 | } |
4005 | ||
647416f9 KC |
4006 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4007 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4008 | "%llu\n"); |
f3cd474b | 4009 | |
64486ae7 CW |
4010 | static int |
4011 | fault_irq_set(struct drm_i915_private *i915, | |
4012 | unsigned long *irq, | |
4013 | unsigned long val) | |
4014 | { | |
4015 | int err; | |
4016 | ||
4017 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4018 | if (err) | |
4019 | return err; | |
4020 | ||
4021 | err = i915_gem_wait_for_idle(i915, | |
4022 | I915_WAIT_LOCKED | | |
4023 | I915_WAIT_INTERRUPTIBLE); | |
4024 | if (err) | |
4025 | goto err_unlock; | |
4026 | ||
64486ae7 CW |
4027 | *irq = val; |
4028 | mutex_unlock(&i915->drm.struct_mutex); | |
4029 | ||
4030 | /* Flush idle worker to disarm irq */ | |
7c26240e | 4031 | drain_delayed_work(&i915->gt.idle_work); |
64486ae7 CW |
4032 | |
4033 | return 0; | |
4034 | ||
4035 | err_unlock: | |
4036 | mutex_unlock(&i915->drm.struct_mutex); | |
4037 | return err; | |
4038 | } | |
4039 | ||
094f9a54 CW |
4040 | static int |
4041 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4042 | { | |
36cdd013 | 4043 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4044 | |
4045 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4046 | return 0; | |
4047 | } | |
4048 | ||
4049 | static int | |
4050 | i915_ring_missed_irq_set(void *data, u64 val) | |
4051 | { | |
64486ae7 | 4052 | struct drm_i915_private *i915 = data; |
094f9a54 | 4053 | |
64486ae7 | 4054 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4055 | } |
4056 | ||
4057 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4058 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4059 | "0x%08llx\n"); | |
4060 | ||
4061 | static int | |
4062 | i915_ring_test_irq_get(void *data, u64 *val) | |
4063 | { | |
36cdd013 | 4064 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4065 | |
4066 | *val = dev_priv->gpu_error.test_irq_rings; | |
4067 | ||
4068 | return 0; | |
4069 | } | |
4070 | ||
4071 | static int | |
4072 | i915_ring_test_irq_set(void *data, u64 val) | |
4073 | { | |
64486ae7 | 4074 | struct drm_i915_private *i915 = data; |
094f9a54 | 4075 | |
64486ae7 | 4076 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4077 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4078 | |
64486ae7 | 4079 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4080 | } |
4081 | ||
4082 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4083 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4084 | "0x%08llx\n"); | |
4085 | ||
b4a0b32d CW |
4086 | #define DROP_UNBOUND BIT(0) |
4087 | #define DROP_BOUND BIT(1) | |
4088 | #define DROP_RETIRE BIT(2) | |
4089 | #define DROP_ACTIVE BIT(3) | |
4090 | #define DROP_FREED BIT(4) | |
4091 | #define DROP_SHRINK_ALL BIT(5) | |
4092 | #define DROP_IDLE BIT(6) | |
fbbd37b3 CW |
4093 | #define DROP_ALL (DROP_UNBOUND | \ |
4094 | DROP_BOUND | \ | |
4095 | DROP_RETIRE | \ | |
4096 | DROP_ACTIVE | \ | |
8eadc19b | 4097 | DROP_FREED | \ |
b4a0b32d CW |
4098 | DROP_SHRINK_ALL |\ |
4099 | DROP_IDLE) | |
647416f9 KC |
4100 | static int |
4101 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4102 | { |
647416f9 | 4103 | *val = DROP_ALL; |
dd624afd | 4104 | |
647416f9 | 4105 | return 0; |
dd624afd CW |
4106 | } |
4107 | ||
647416f9 KC |
4108 | static int |
4109 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4110 | { |
36cdd013 DW |
4111 | struct drm_i915_private *dev_priv = data; |
4112 | struct drm_device *dev = &dev_priv->drm; | |
00c26cf9 | 4113 | int ret = 0; |
dd624afd | 4114 | |
b4a0b32d CW |
4115 | DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", |
4116 | val, val & DROP_ALL); | |
dd624afd CW |
4117 | |
4118 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4119 | * on ioctls on -EAGAIN. */ | |
00c26cf9 CW |
4120 | if (val & (DROP_ACTIVE | DROP_RETIRE)) { |
4121 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
dd624afd | 4122 | if (ret) |
00c26cf9 | 4123 | return ret; |
dd624afd | 4124 | |
00c26cf9 CW |
4125 | if (val & DROP_ACTIVE) |
4126 | ret = i915_gem_wait_for_idle(dev_priv, | |
4127 | I915_WAIT_INTERRUPTIBLE | | |
4128 | I915_WAIT_LOCKED); | |
4129 | ||
4130 | if (val & DROP_RETIRE) | |
e61e0f51 | 4131 | i915_retire_requests(dev_priv); |
00c26cf9 CW |
4132 | |
4133 | mutex_unlock(&dev->struct_mutex); | |
4134 | } | |
dd624afd | 4135 | |
d92a8cfc | 4136 | fs_reclaim_acquire(GFP_KERNEL); |
21ab4e74 | 4137 | if (val & DROP_BOUND) |
912d572d | 4138 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND); |
4ad72b7f | 4139 | |
21ab4e74 | 4140 | if (val & DROP_UNBOUND) |
912d572d | 4141 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND); |
dd624afd | 4142 | |
8eadc19b CW |
4143 | if (val & DROP_SHRINK_ALL) |
4144 | i915_gem_shrink_all(dev_priv); | |
d92a8cfc | 4145 | fs_reclaim_release(GFP_KERNEL); |
8eadc19b | 4146 | |
b4a0b32d CW |
4147 | if (val & DROP_IDLE) |
4148 | drain_delayed_work(&dev_priv->gt.idle_work); | |
4149 | ||
c9c70471 | 4150 | if (val & DROP_FREED) |
bdeb9785 | 4151 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 | 4152 | |
647416f9 | 4153 | return ret; |
dd624afd CW |
4154 | } |
4155 | ||
647416f9 KC |
4156 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4157 | i915_drop_caches_get, i915_drop_caches_set, | |
4158 | "0x%08llx\n"); | |
dd624afd | 4159 | |
647416f9 KC |
4160 | static int |
4161 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4162 | { |
36cdd013 | 4163 | struct drm_i915_private *dev_priv = data; |
004777cb | 4164 | |
36cdd013 | 4165 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4166 | return -ENODEV; |
4167 | ||
562d9bae | 4168 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit); |
647416f9 | 4169 | return 0; |
358733e9 JB |
4170 | } |
4171 | ||
647416f9 KC |
4172 | static int |
4173 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4174 | { |
36cdd013 | 4175 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4176 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4177 | u32 hw_max, hw_min; |
647416f9 | 4178 | int ret; |
004777cb | 4179 | |
36cdd013 | 4180 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4181 | return -ENODEV; |
358733e9 | 4182 | |
647416f9 | 4183 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4184 | |
9f817501 | 4185 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4186 | if (ret) |
4187 | return ret; | |
4188 | ||
358733e9 JB |
4189 | /* |
4190 | * Turbo will still be enabled, but won't go above the set value. | |
4191 | */ | |
bc4d91f6 | 4192 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4193 | |
562d9bae SAK |
4194 | hw_max = rps->max_freq; |
4195 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4196 | |
562d9bae | 4197 | if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) { |
9f817501 | 4198 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4199 | return -EINVAL; |
0a073b84 JB |
4200 | } |
4201 | ||
562d9bae | 4202 | rps->max_freq_softlimit = val; |
dd0a1aa1 | 4203 | |
9fcee2f7 CW |
4204 | if (intel_set_rps(dev_priv, val)) |
4205 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4206 | |
9f817501 | 4207 | mutex_unlock(&dev_priv->pcu_lock); |
358733e9 | 4208 | |
647416f9 | 4209 | return 0; |
358733e9 JB |
4210 | } |
4211 | ||
647416f9 KC |
4212 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4213 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4214 | "%llu\n"); |
358733e9 | 4215 | |
647416f9 KC |
4216 | static int |
4217 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4218 | { |
36cdd013 | 4219 | struct drm_i915_private *dev_priv = data; |
004777cb | 4220 | |
62e1baa1 | 4221 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4222 | return -ENODEV; |
4223 | ||
562d9bae | 4224 | *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit); |
647416f9 | 4225 | return 0; |
1523c310 JB |
4226 | } |
4227 | ||
647416f9 KC |
4228 | static int |
4229 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4230 | { |
36cdd013 | 4231 | struct drm_i915_private *dev_priv = data; |
562d9bae | 4232 | struct intel_rps *rps = &dev_priv->gt_pm.rps; |
bc4d91f6 | 4233 | u32 hw_max, hw_min; |
647416f9 | 4234 | int ret; |
004777cb | 4235 | |
62e1baa1 | 4236 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4237 | return -ENODEV; |
1523c310 | 4238 | |
647416f9 | 4239 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4240 | |
9f817501 | 4241 | ret = mutex_lock_interruptible(&dev_priv->pcu_lock); |
004777cb DV |
4242 | if (ret) |
4243 | return ret; | |
4244 | ||
1523c310 JB |
4245 | /* |
4246 | * Turbo will still be enabled, but won't go below the set value. | |
4247 | */ | |
bc4d91f6 | 4248 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4249 | |
562d9bae SAK |
4250 | hw_max = rps->max_freq; |
4251 | hw_min = rps->min_freq; | |
dd0a1aa1 | 4252 | |
36cdd013 | 4253 | if (val < hw_min || |
562d9bae | 4254 | val > hw_max || val > rps->max_freq_softlimit) { |
9f817501 | 4255 | mutex_unlock(&dev_priv->pcu_lock); |
dd0a1aa1 | 4256 | return -EINVAL; |
0a073b84 | 4257 | } |
dd0a1aa1 | 4258 | |
562d9bae | 4259 | rps->min_freq_softlimit = val; |
dd0a1aa1 | 4260 | |
9fcee2f7 CW |
4261 | if (intel_set_rps(dev_priv, val)) |
4262 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4263 | |
9f817501 | 4264 | mutex_unlock(&dev_priv->pcu_lock); |
1523c310 | 4265 | |
647416f9 | 4266 | return 0; |
1523c310 JB |
4267 | } |
4268 | ||
647416f9 KC |
4269 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4270 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4271 | "%llu\n"); |
1523c310 | 4272 | |
647416f9 KC |
4273 | static int |
4274 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4275 | { |
36cdd013 | 4276 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4277 | u32 snpcr; |
07b7ddd9 | 4278 | |
36cdd013 | 4279 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4280 | return -ENODEV; |
4281 | ||
c8c8fb33 | 4282 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4283 | |
07b7ddd9 | 4284 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4285 | |
4286 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4287 | |
647416f9 | 4288 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4289 | |
647416f9 | 4290 | return 0; |
07b7ddd9 JB |
4291 | } |
4292 | ||
647416f9 KC |
4293 | static int |
4294 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4295 | { |
36cdd013 | 4296 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4297 | u32 snpcr; |
07b7ddd9 | 4298 | |
36cdd013 | 4299 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4300 | return -ENODEV; |
4301 | ||
647416f9 | 4302 | if (val > 3) |
07b7ddd9 JB |
4303 | return -EINVAL; |
4304 | ||
c8c8fb33 | 4305 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4306 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4307 | |
4308 | /* Update the cache sharing policy here as well */ | |
4309 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4310 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4311 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4312 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4313 | ||
c8c8fb33 | 4314 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4315 | return 0; |
07b7ddd9 JB |
4316 | } |
4317 | ||
647416f9 KC |
4318 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4319 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4320 | "%llu\n"); | |
07b7ddd9 | 4321 | |
36cdd013 | 4322 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4323 | struct sseu_dev_info *sseu) |
5d39525a | 4324 | { |
7aa0b14e CW |
4325 | #define SS_MAX 2 |
4326 | const int ss_max = SS_MAX; | |
4327 | u32 sig1[SS_MAX], sig2[SS_MAX]; | |
5d39525a | 4328 | int ss; |
5d39525a JM |
4329 | |
4330 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4331 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4332 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4333 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4334 | ||
4335 | for (ss = 0; ss < ss_max; ss++) { | |
4336 | unsigned int eu_cnt; | |
4337 | ||
4338 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4339 | /* skip disabled subslice */ | |
4340 | continue; | |
4341 | ||
f08a0c92 | 4342 | sseu->slice_mask = BIT(0); |
8cc76693 | 4343 | sseu->subslice_mask[0] |= BIT(ss); |
5d39525a JM |
4344 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4345 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4346 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4347 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4348 | sseu->eu_total += eu_cnt; |
4349 | sseu->eu_per_subslice = max_t(unsigned int, | |
4350 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4351 | } |
7aa0b14e | 4352 | #undef SS_MAX |
5d39525a JM |
4353 | } |
4354 | ||
f8c3dcf9 RV |
4355 | static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, |
4356 | struct sseu_dev_info *sseu) | |
4357 | { | |
c7fb3c6c | 4358 | #define SS_MAX 6 |
f8c3dcf9 | 4359 | const struct intel_device_info *info = INTEL_INFO(dev_priv); |
c7fb3c6c | 4360 | u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; |
f8c3dcf9 | 4361 | int s, ss; |
f8c3dcf9 | 4362 | |
b3e7f866 | 4363 | for (s = 0; s < info->sseu.max_slices; s++) { |
f8c3dcf9 RV |
4364 | /* |
4365 | * FIXME: Valid SS Mask respects the spec and read | |
4366 | * only valid bits for those registers, excluding reserverd | |
4367 | * although this seems wrong because it would leave many | |
4368 | * subslices without ACK. | |
4369 | */ | |
4370 | s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) & | |
4371 | GEN10_PGCTL_VALID_SS_MASK(s); | |
4372 | eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s)); | |
4373 | eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s)); | |
4374 | } | |
4375 | ||
4376 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | | |
4377 | GEN9_PGCTL_SSA_EU19_ACK | | |
4378 | GEN9_PGCTL_SSA_EU210_ACK | | |
4379 | GEN9_PGCTL_SSA_EU311_ACK; | |
4380 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4381 | GEN9_PGCTL_SSB_EU19_ACK | | |
4382 | GEN9_PGCTL_SSB_EU210_ACK | | |
4383 | GEN9_PGCTL_SSB_EU311_ACK; | |
4384 | ||
b3e7f866 | 4385 | for (s = 0; s < info->sseu.max_slices; s++) { |
f8c3dcf9 RV |
4386 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
4387 | /* skip disabled slice */ | |
4388 | continue; | |
4389 | ||
4390 | sseu->slice_mask |= BIT(s); | |
8cc76693 | 4391 | sseu->subslice_mask[s] = info->sseu.subslice_mask[s]; |
f8c3dcf9 | 4392 | |
b3e7f866 | 4393 | for (ss = 0; ss < info->sseu.max_subslices; ss++) { |
f8c3dcf9 RV |
4394 | unsigned int eu_cnt; |
4395 | ||
4396 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
4397 | /* skip disabled subslice */ | |
4398 | continue; | |
4399 | ||
4400 | eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] & | |
4401 | eu_mask[ss % 2]); | |
4402 | sseu->eu_total += eu_cnt; | |
4403 | sseu->eu_per_subslice = max_t(unsigned int, | |
4404 | sseu->eu_per_subslice, | |
4405 | eu_cnt); | |
4406 | } | |
4407 | } | |
c7fb3c6c | 4408 | #undef SS_MAX |
f8c3dcf9 RV |
4409 | } |
4410 | ||
36cdd013 | 4411 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4412 | struct sseu_dev_info *sseu) |
5d39525a | 4413 | { |
c7fb3c6c | 4414 | #define SS_MAX 3 |
b3e7f866 | 4415 | const struct intel_device_info *info = INTEL_INFO(dev_priv); |
c7fb3c6c | 4416 | u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; |
5d39525a | 4417 | int s, ss; |
1c046bc1 | 4418 | |
b3e7f866 | 4419 | for (s = 0; s < info->sseu.max_slices; s++) { |
1c046bc1 JM |
4420 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); |
4421 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4422 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4423 | } | |
4424 | ||
5d39525a JM |
4425 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4426 | GEN9_PGCTL_SSA_EU19_ACK | | |
4427 | GEN9_PGCTL_SSA_EU210_ACK | | |
4428 | GEN9_PGCTL_SSA_EU311_ACK; | |
4429 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4430 | GEN9_PGCTL_SSB_EU19_ACK | | |
4431 | GEN9_PGCTL_SSB_EU210_ACK | | |
4432 | GEN9_PGCTL_SSB_EU311_ACK; | |
4433 | ||
b3e7f866 | 4434 | for (s = 0; s < info->sseu.max_slices; s++) { |
5d39525a JM |
4435 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
4436 | /* skip disabled slice */ | |
4437 | continue; | |
4438 | ||
f08a0c92 | 4439 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4440 | |
f8c3dcf9 | 4441 | if (IS_GEN9_BC(dev_priv)) |
8cc76693 LL |
4442 | sseu->subslice_mask[s] = |
4443 | INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; | |
1c046bc1 | 4444 | |
b3e7f866 | 4445 | for (ss = 0; ss < info->sseu.max_subslices; ss++) { |
5d39525a JM |
4446 | unsigned int eu_cnt; |
4447 | ||
cc3f90f0 | 4448 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4449 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4450 | /* skip disabled subslice */ | |
4451 | continue; | |
1c046bc1 | 4452 | |
8cc76693 | 4453 | sseu->subslice_mask[s] |= BIT(ss); |
57ec171e | 4454 | } |
1c046bc1 | 4455 | |
5d39525a JM |
4456 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4457 | eu_mask[ss%2]); | |
915490d5 ID |
4458 | sseu->eu_total += eu_cnt; |
4459 | sseu->eu_per_subslice = max_t(unsigned int, | |
4460 | sseu->eu_per_subslice, | |
4461 | eu_cnt); | |
5d39525a JM |
4462 | } |
4463 | } | |
c7fb3c6c | 4464 | #undef SS_MAX |
5d39525a JM |
4465 | } |
4466 | ||
36cdd013 | 4467 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4468 | struct sseu_dev_info *sseu) |
91bedd34 | 4469 | { |
91bedd34 | 4470 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4471 | int s; |
91bedd34 | 4472 | |
f08a0c92 | 4473 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4474 | |
f08a0c92 | 4475 | if (sseu->slice_mask) { |
43b67998 ID |
4476 | sseu->eu_per_subslice = |
4477 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
8cc76693 LL |
4478 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
4479 | sseu->subslice_mask[s] = | |
4480 | INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; | |
4481 | } | |
57ec171e ID |
4482 | sseu->eu_total = sseu->eu_per_subslice * |
4483 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4484 | |
4485 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4486 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4487 | u8 subslice_7eu = |
4488 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4489 | |
915490d5 | 4490 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4491 | } |
4492 | } | |
4493 | } | |
4494 | ||
615d8908 ID |
4495 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4496 | const struct sseu_dev_info *sseu) | |
4497 | { | |
4498 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4499 | const char *type = is_available_info ? "Available" : "Enabled"; | |
8cc76693 | 4500 | int s; |
615d8908 | 4501 | |
c67ba538 ID |
4502 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4503 | sseu->slice_mask); | |
615d8908 | 4504 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4505 | hweight8(sseu->slice_mask)); |
615d8908 | 4506 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4507 | sseu_subslice_total(sseu)); |
8cc76693 LL |
4508 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
4509 | seq_printf(m, " %s Slice%i subslices: %u\n", type, | |
4510 | s, hweight8(sseu->subslice_mask[s])); | |
4511 | } | |
615d8908 ID |
4512 | seq_printf(m, " %s EU Total: %u\n", type, |
4513 | sseu->eu_total); | |
4514 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4515 | sseu->eu_per_subslice); | |
4516 | ||
4517 | if (!is_available_info) | |
4518 | return; | |
4519 | ||
4520 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4521 | if (HAS_POOLED_EU(dev_priv)) | |
4522 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4523 | ||
4524 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4525 | yesno(sseu->has_slice_pg)); | |
4526 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4527 | yesno(sseu->has_subslice_pg)); | |
4528 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4529 | yesno(sseu->has_eu_pg)); | |
4530 | } | |
4531 | ||
3873218f JM |
4532 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4533 | { | |
36cdd013 | 4534 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4535 | struct sseu_dev_info sseu; |
3873218f | 4536 | |
36cdd013 | 4537 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4538 | return -ENODEV; |
4539 | ||
4540 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4541 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4542 | |
7f992aba | 4543 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4544 | memset(&sseu, 0, sizeof(sseu)); |
8cc76693 LL |
4545 | sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices; |
4546 | sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices; | |
4547 | sseu.max_eus_per_subslice = | |
4548 | INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice; | |
238010ed DW |
4549 | |
4550 | intel_runtime_pm_get(dev_priv); | |
4551 | ||
36cdd013 | 4552 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4553 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4554 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4555 | broadwell_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 | 4556 | } else if (IS_GEN9(dev_priv)) { |
915490d5 | 4557 | gen9_sseu_device_status(dev_priv, &sseu); |
f8c3dcf9 RV |
4558 | } else if (INTEL_GEN(dev_priv) >= 10) { |
4559 | gen10_sseu_device_status(dev_priv, &sseu); | |
7f992aba | 4560 | } |
238010ed DW |
4561 | |
4562 | intel_runtime_pm_put(dev_priv); | |
4563 | ||
615d8908 | 4564 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4565 | |
3873218f JM |
4566 | return 0; |
4567 | } | |
4568 | ||
6d794d42 BW |
4569 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4570 | { | |
d7a133d8 | 4571 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4572 | |
d7a133d8 | 4573 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4574 | return 0; |
4575 | ||
d7a133d8 CW |
4576 | intel_runtime_pm_get(i915); |
4577 | intel_uncore_forcewake_user_get(i915); | |
6d794d42 BW |
4578 | |
4579 | return 0; | |
4580 | } | |
4581 | ||
c43b5634 | 4582 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4583 | { |
d7a133d8 | 4584 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4585 | |
d7a133d8 | 4586 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4587 | return 0; |
4588 | ||
d7a133d8 CW |
4589 | intel_uncore_forcewake_user_put(i915); |
4590 | intel_runtime_pm_put(i915); | |
6d794d42 BW |
4591 | |
4592 | return 0; | |
4593 | } | |
4594 | ||
4595 | static const struct file_operations i915_forcewake_fops = { | |
4596 | .owner = THIS_MODULE, | |
4597 | .open = i915_forcewake_open, | |
4598 | .release = i915_forcewake_release, | |
4599 | }; | |
4600 | ||
317eaa95 L |
4601 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4602 | { | |
4603 | struct drm_i915_private *dev_priv = m->private; | |
4604 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4605 | ||
4606 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4607 | seq_printf(m, "Detected: %s\n", | |
4608 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4609 | ||
4610 | return 0; | |
4611 | } | |
4612 | ||
4613 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4614 | const char __user *ubuf, size_t len, | |
4615 | loff_t *offp) | |
4616 | { | |
4617 | struct seq_file *m = file->private_data; | |
4618 | struct drm_i915_private *dev_priv = m->private; | |
4619 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4620 | unsigned int new_threshold; | |
4621 | int i; | |
4622 | char *newline; | |
4623 | char tmp[16]; | |
4624 | ||
4625 | if (len >= sizeof(tmp)) | |
4626 | return -EINVAL; | |
4627 | ||
4628 | if (copy_from_user(tmp, ubuf, len)) | |
4629 | return -EFAULT; | |
4630 | ||
4631 | tmp[len] = '\0'; | |
4632 | ||
4633 | /* Strip newline, if any */ | |
4634 | newline = strchr(tmp, '\n'); | |
4635 | if (newline) | |
4636 | *newline = '\0'; | |
4637 | ||
4638 | if (strcmp(tmp, "reset") == 0) | |
4639 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4640 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4641 | return -EINVAL; | |
4642 | ||
4643 | if (new_threshold > 0) | |
4644 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4645 | new_threshold); | |
4646 | else | |
4647 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4648 | ||
4649 | spin_lock_irq(&dev_priv->irq_lock); | |
4650 | hotplug->hpd_storm_threshold = new_threshold; | |
4651 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4652 | for_each_hpd_pin(i) | |
4653 | hotplug->stats[i].count = 0; | |
4654 | spin_unlock_irq(&dev_priv->irq_lock); | |
4655 | ||
4656 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4657 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4658 | ||
4659 | return len; | |
4660 | } | |
4661 | ||
4662 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4663 | { | |
4664 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4665 | } | |
4666 | ||
4667 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4668 | .owner = THIS_MODULE, | |
4669 | .open = i915_hpd_storm_ctl_open, | |
4670 | .read = seq_read, | |
4671 | .llseek = seq_lseek, | |
4672 | .release = single_release, | |
4673 | .write = i915_hpd_storm_ctl_write | |
4674 | }; | |
4675 | ||
35954e88 R |
4676 | static int i915_drrs_ctl_set(void *data, u64 val) |
4677 | { | |
4678 | struct drm_i915_private *dev_priv = data; | |
4679 | struct drm_device *dev = &dev_priv->drm; | |
4680 | struct intel_crtc *intel_crtc; | |
4681 | struct intel_encoder *encoder; | |
4682 | struct intel_dp *intel_dp; | |
4683 | ||
4684 | if (INTEL_GEN(dev_priv) < 7) | |
4685 | return -ENODEV; | |
4686 | ||
4687 | drm_modeset_lock_all(dev); | |
4688 | for_each_intel_crtc(dev, intel_crtc) { | |
4689 | if (!intel_crtc->base.state->active || | |
4690 | !intel_crtc->config->has_drrs) | |
4691 | continue; | |
4692 | ||
4693 | for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) { | |
4694 | if (encoder->type != INTEL_OUTPUT_EDP) | |
4695 | continue; | |
4696 | ||
4697 | DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n", | |
4698 | val ? "en" : "dis", val); | |
4699 | ||
4700 | intel_dp = enc_to_intel_dp(&encoder->base); | |
4701 | if (val) | |
4702 | intel_edp_drrs_enable(intel_dp, | |
4703 | intel_crtc->config); | |
4704 | else | |
4705 | intel_edp_drrs_disable(intel_dp, | |
4706 | intel_crtc->config); | |
4707 | } | |
4708 | } | |
4709 | drm_modeset_unlock_all(dev); | |
4710 | ||
4711 | return 0; | |
4712 | } | |
4713 | ||
4714 | DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n"); | |
4715 | ||
06c5bf8c | 4716 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4717 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4718 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4719 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6d2b8885 | 4720 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
a6172a80 | 4721 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4722 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4723 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4724 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4725 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4726 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
ac58d2ab | 4727 | {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, |
a8b9370f | 4728 | {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, |
0509ead1 | 4729 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4730 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4731 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
061d06a2 | 4732 | {"i915_reset_info", i915_reset_info, 0}, |
f97108d1 | 4733 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4734 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4735 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4736 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4737 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4738 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4739 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4740 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4741 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4742 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4743 | {"i915_context_status", i915_context_status, 0}, |
f65367b5 | 4744 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4745 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4746 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4747 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4748 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4749 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4750 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4751 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4752 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4753 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4754 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4755 | {"i915_engine_info", i915_engine_info, 0}, |
79e9cd5f | 4756 | {"i915_rcs_topology", i915_rcs_topology, 0}, |
c5418a8b | 4757 | {"i915_shrinker_info", i915_shrinker_info, 0}, |
728e29d7 | 4758 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4759 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4760 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4761 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4762 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4763 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4764 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4765 | }; |
27c202ad | 4766 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4767 | |
06c5bf8c | 4768 | static const struct i915_debugfs_files { |
34b9674c DV |
4769 | const char *name; |
4770 | const struct file_operations *fops; | |
4771 | } i915_debugfs_files[] = { | |
4772 | {"i915_wedged", &i915_wedged_fops}, | |
4773 | {"i915_max_freq", &i915_max_freq_fops}, | |
4774 | {"i915_min_freq", &i915_min_freq_fops}, | |
4775 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4776 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4777 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4778 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4779 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4780 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4781 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4782 | #endif |
34b9674c | 4783 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4784 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4785 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4786 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4787 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
4127dc43 | 4788 | {"i915_fbc_false_color", &i915_fbc_false_color_fops}, |
eb3394fa TP |
4789 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4790 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4791 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
4977a287 MW |
4792 | {"i915_guc_log_level", &i915_guc_log_level_fops}, |
4793 | {"i915_guc_log_relay", &i915_guc_log_relay_fops}, | |
d2d4f39b | 4794 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, |
35954e88 R |
4795 | {"i915_ipc_status", &i915_ipc_status_fops}, |
4796 | {"i915_drrs_ctl", &i915_drrs_ctl_fops} | |
34b9674c DV |
4797 | }; |
4798 | ||
1dac891c | 4799 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4800 | { |
91c8a326 | 4801 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4802 | struct dentry *ent; |
34b9674c | 4803 | int ret, i; |
f3cd474b | 4804 | |
b05eeb0f NT |
4805 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4806 | minor->debugfs_root, to_i915(minor->dev), | |
4807 | &i915_forcewake_fops); | |
4808 | if (!ent) | |
4809 | return -ENOMEM; | |
6a9c308d | 4810 | |
731035fe TV |
4811 | ret = intel_pipe_crc_create(minor); |
4812 | if (ret) | |
4813 | return ret; | |
07144428 | 4814 | |
34b9674c | 4815 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4816 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4817 | S_IRUGO | S_IWUSR, | |
4818 | minor->debugfs_root, | |
4819 | to_i915(minor->dev), | |
34b9674c | 4820 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4821 | if (!ent) |
4822 | return -ENOMEM; | |
34b9674c | 4823 | } |
40633219 | 4824 | |
27c202ad BG |
4825 | return drm_debugfs_create_files(i915_debugfs_list, |
4826 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4827 | minor->debugfs_root, minor); |
4828 | } | |
4829 | ||
aa7471d2 JN |
4830 | struct dpcd_block { |
4831 | /* DPCD dump start address. */ | |
4832 | unsigned int offset; | |
4833 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4834 | unsigned int end; | |
4835 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4836 | size_t size; | |
4837 | /* Only valid for eDP. */ | |
4838 | bool edp; | |
4839 | }; | |
4840 | ||
4841 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4842 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4843 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4844 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4845 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4846 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4847 | { .offset = DP_SET_POWER }, | |
4848 | { .offset = DP_EDP_DPCD_REV }, | |
4849 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4850 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4851 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4852 | }; | |
4853 | ||
4854 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4855 | { | |
4856 | struct drm_connector *connector = m->private; | |
4857 | struct intel_dp *intel_dp = | |
4858 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4859 | uint8_t buf[16]; | |
4860 | ssize_t err; | |
4861 | int i; | |
4862 | ||
5c1a8875 MK |
4863 | if (connector->status != connector_status_connected) |
4864 | return -ENODEV; | |
4865 | ||
aa7471d2 JN |
4866 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4867 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4868 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4869 | ||
4870 | if (b->edp && | |
4871 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4872 | continue; | |
4873 | ||
4874 | /* low tech for now */ | |
4875 | if (WARN_ON(size > sizeof(buf))) | |
4876 | continue; | |
4877 | ||
4878 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4879 | if (err <= 0) { | |
4880 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4881 | size, b->offset, err); | |
4882 | continue; | |
4883 | } | |
4884 | ||
4885 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4886 | } |
aa7471d2 JN |
4887 | |
4888 | return 0; | |
4889 | } | |
e4006713 | 4890 | DEFINE_SHOW_ATTRIBUTE(i915_dpcd); |
aa7471d2 | 4891 | |
ecbd6781 DW |
4892 | static int i915_panel_show(struct seq_file *m, void *data) |
4893 | { | |
4894 | struct drm_connector *connector = m->private; | |
4895 | struct intel_dp *intel_dp = | |
4896 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4897 | ||
4898 | if (connector->status != connector_status_connected) | |
4899 | return -ENODEV; | |
4900 | ||
4901 | seq_printf(m, "Panel power up delay: %d\n", | |
4902 | intel_dp->panel_power_up_delay); | |
4903 | seq_printf(m, "Panel power down delay: %d\n", | |
4904 | intel_dp->panel_power_down_delay); | |
4905 | seq_printf(m, "Backlight on delay: %d\n", | |
4906 | intel_dp->backlight_on_delay); | |
4907 | seq_printf(m, "Backlight off delay: %d\n", | |
4908 | intel_dp->backlight_off_delay); | |
4909 | ||
4910 | return 0; | |
4911 | } | |
e4006713 | 4912 | DEFINE_SHOW_ATTRIBUTE(i915_panel); |
ecbd6781 | 4913 | |
aa7471d2 JN |
4914 | /** |
4915 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4916 | * @connector: pointer to a registered drm_connector | |
4917 | * | |
4918 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4919 | * drm_debugfs_connector_remove(). | |
4920 | * | |
4921 | * Returns 0 on success, negative error codes on error. | |
4922 | */ | |
4923 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4924 | { | |
4925 | struct dentry *root = connector->debugfs_entry; | |
4926 | ||
4927 | /* The connector must have been registered beforehands. */ | |
4928 | if (!root) | |
4929 | return -ENODEV; | |
4930 | ||
4931 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4932 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4933 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4934 | connector, &i915_dpcd_fops); | |
4935 | ||
4936 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4937 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4938 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4939 | |
4940 | return 0; | |
4941 | } |