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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
4e5359cd | 31 | #include "intel_drv.h" |
2017263e | 32 | |
36cdd013 DW |
33 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
34 | { | |
35 | return to_i915(node->minor->dev); | |
36 | } | |
37 | ||
418e3cd8 CW |
38 | static __always_inline void seq_print_param(struct seq_file *m, |
39 | const char *name, | |
40 | const char *type, | |
41 | const void *x) | |
42 | { | |
43 | if (!__builtin_strcmp(type, "bool")) | |
44 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
45 | else if (!__builtin_strcmp(type, "int")) | |
46 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
47 | else if (!__builtin_strcmp(type, "unsigned int")) | |
48 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
49 | else if (!__builtin_strcmp(type, "char *")) |
50 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
51 | else |
52 | BUILD_BUG(); | |
53 | } | |
54 | ||
70d39fe4 CW |
55 | static int i915_capabilities(struct seq_file *m, void *data) |
56 | { | |
36cdd013 DW |
57 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
58 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 59 | |
36cdd013 | 60 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 61 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 63 | |
79fc46df | 64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 66 | #undef PRINT_FLAG |
70d39fe4 | 67 | |
418e3cd8 CW |
68 | kernel_param_lock(THIS_MODULE); |
69 | #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x); | |
70 | I915_PARAMS_FOR_EACH(PRINT_PARAM); | |
71 | #undef PRINT_PARAM | |
72 | kernel_param_unlock(THIS_MODULE); | |
73 | ||
70d39fe4 CW |
74 | return 0; |
75 | } | |
2017263e | 76 | |
a7363de7 | 77 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 78 | { |
573adb39 | 79 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
80 | } |
81 | ||
a7363de7 | 82 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
83 | { |
84 | return obj->pin_display ? 'p' : ' '; | |
85 | } | |
86 | ||
a7363de7 | 87 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 88 | { |
3e510a8e | 89 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 90 | default: |
be12a86b TU |
91 | case I915_TILING_NONE: return ' '; |
92 | case I915_TILING_X: return 'X'; | |
93 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 94 | } |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 98 | { |
275f039d | 99 | return !list_empty(&obj->userfault_link) ? 'g' : ' '; |
be12a86b TU |
100 | } |
101 | ||
a7363de7 | 102 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 103 | { |
a4f5ea64 | 104 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
105 | } |
106 | ||
ca1543be TU |
107 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
108 | { | |
109 | u64 size = 0; | |
110 | struct i915_vma *vma; | |
111 | ||
1c7f4bca | 112 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 113 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
114 | size += vma->node.size; |
115 | } | |
116 | ||
117 | return size; | |
118 | } | |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
b4716185 | 123 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 124 | struct intel_engine_cs *engine; |
1d693bcc | 125 | struct i915_vma *vma; |
faf5bf0a | 126 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
127 | int pin_count = 0; |
128 | ||
188c1ab7 CW |
129 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
130 | ||
d07f0e59 | 131 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 132 | &obj->base, |
be12a86b | 133 | get_active_flag(obj), |
37811fcc CW |
134 | get_pin_flag(obj), |
135 | get_tiling_flag(obj), | |
1d693bcc | 136 | get_global_flag(obj), |
be12a86b | 137 | get_pin_mapped_flag(obj), |
a05a5862 | 138 | obj->base.size / 1024, |
37811fcc | 139 | obj->base.read_domains, |
d07f0e59 | 140 | obj->base.write_domain, |
36cdd013 | 141 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
142 | obj->mm.dirty ? " dirty" : "", |
143 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
144 | if (obj->base.name) |
145 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 146 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 147 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 148 | pin_count++; |
ba0635ff DC |
149 | } |
150 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
151 | if (obj->pin_display) |
152 | seq_printf(m, " (display)"); | |
1c7f4bca | 153 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
154 | if (!drm_mm_node_allocated(&vma->node)) |
155 | continue; | |
156 | ||
8d2fdc3f | 157 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 158 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 159 | vma->node.start, vma->node.size); |
21976853 CW |
160 | if (i915_vma_is_ggtt(vma)) { |
161 | switch (vma->ggtt_view.type) { | |
162 | case I915_GGTT_VIEW_NORMAL: | |
163 | seq_puts(m, ", normal"); | |
164 | break; | |
165 | ||
166 | case I915_GGTT_VIEW_PARTIAL: | |
167 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
168 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
169 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
170 | break; |
171 | ||
172 | case I915_GGTT_VIEW_ROTATED: | |
173 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
174 | vma->ggtt_view.rotated.plane[0].width, |
175 | vma->ggtt_view.rotated.plane[0].height, | |
176 | vma->ggtt_view.rotated.plane[0].stride, | |
177 | vma->ggtt_view.rotated.plane[0].offset, | |
178 | vma->ggtt_view.rotated.plane[1].width, | |
179 | vma->ggtt_view.rotated.plane[1].height, | |
180 | vma->ggtt_view.rotated.plane[1].stride, | |
181 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
182 | break; |
183 | ||
184 | default: | |
185 | MISSING_CASE(vma->ggtt_view.type); | |
186 | break; | |
187 | } | |
188 | } | |
49ef5294 CW |
189 | if (vma->fence) |
190 | seq_printf(m, " , fence: %d%s", | |
191 | vma->fence->id, | |
192 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 193 | seq_puts(m, ")"); |
1d693bcc | 194 | } |
c1ad11fc | 195 | if (obj->stolen) |
440fd528 | 196 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 197 | |
d07f0e59 | 198 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
199 | if (engine) |
200 | seq_printf(m, " (%s)", engine->name); | |
201 | ||
faf5bf0a CW |
202 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
203 | if (frontbuffer_bits) | |
204 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
205 | } |
206 | ||
e637d2cb | 207 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 208 | { |
e637d2cb CW |
209 | const struct drm_i915_gem_object *a = |
210 | *(const struct drm_i915_gem_object **)A; | |
211 | const struct drm_i915_gem_object *b = | |
212 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 213 | |
2d05fa16 RV |
214 | if (a->stolen->start < b->stolen->start) |
215 | return -1; | |
216 | if (a->stolen->start > b->stolen->start) | |
217 | return 1; | |
218 | return 0; | |
6d2b8885 CW |
219 | } |
220 | ||
221 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
222 | { | |
36cdd013 DW |
223 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
224 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 225 | struct drm_i915_gem_object **objects; |
6d2b8885 | 226 | struct drm_i915_gem_object *obj; |
c44ef60e | 227 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
228 | unsigned long total, count, n; |
229 | int ret; | |
230 | ||
231 | total = READ_ONCE(dev_priv->mm.object_count); | |
2098105e | 232 | objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL); |
e637d2cb CW |
233 | if (!objects) |
234 | return -ENOMEM; | |
6d2b8885 CW |
235 | |
236 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
237 | if (ret) | |
e637d2cb | 238 | goto out; |
6d2b8885 CW |
239 | |
240 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 241 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
e637d2cb CW |
242 | if (count == total) |
243 | break; | |
244 | ||
6d2b8885 CW |
245 | if (obj->stolen == NULL) |
246 | continue; | |
247 | ||
e637d2cb | 248 | objects[count++] = obj; |
6d2b8885 | 249 | total_obj_size += obj->base.size; |
ca1543be | 250 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 251 | |
6d2b8885 | 252 | } |
56cea323 | 253 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
e637d2cb CW |
254 | if (count == total) |
255 | break; | |
256 | ||
6d2b8885 CW |
257 | if (obj->stolen == NULL) |
258 | continue; | |
259 | ||
e637d2cb | 260 | objects[count++] = obj; |
6d2b8885 | 261 | total_obj_size += obj->base.size; |
6d2b8885 | 262 | } |
e637d2cb CW |
263 | |
264 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
265 | ||
6d2b8885 | 266 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 267 | for (n = 0; n < count; n++) { |
6d2b8885 | 268 | seq_puts(m, " "); |
e637d2cb | 269 | describe_obj(m, objects[n]); |
6d2b8885 | 270 | seq_putc(m, '\n'); |
6d2b8885 | 271 | } |
e637d2cb | 272 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 273 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
274 | |
275 | mutex_unlock(&dev->struct_mutex); | |
276 | out: | |
2098105e | 277 | kvfree(objects); |
e637d2cb | 278 | return ret; |
6d2b8885 CW |
279 | } |
280 | ||
2db8e9d6 | 281 | struct file_stats { |
6313c204 | 282 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
283 | unsigned long count; |
284 | u64 total, unbound; | |
285 | u64 global, shared; | |
286 | u64 active, inactive; | |
2db8e9d6 CW |
287 | }; |
288 | ||
289 | static int per_file_stats(int id, void *ptr, void *data) | |
290 | { | |
291 | struct drm_i915_gem_object *obj = ptr; | |
292 | struct file_stats *stats = data; | |
6313c204 | 293 | struct i915_vma *vma; |
2db8e9d6 | 294 | |
0caf81b5 CW |
295 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
296 | ||
2db8e9d6 CW |
297 | stats->count++; |
298 | stats->total += obj->base.size; | |
15717de2 CW |
299 | if (!obj->bind_count) |
300 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
301 | if (obj->base.name || obj->base.dma_buf) |
302 | stats->shared += obj->base.size; | |
303 | ||
894eeecc CW |
304 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
305 | if (!drm_mm_node_allocated(&vma->node)) | |
306 | continue; | |
6313c204 | 307 | |
3272db53 | 308 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
309 | stats->global += vma->node.size; |
310 | } else { | |
311 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 312 | |
2bfa996e | 313 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 314 | continue; |
6313c204 | 315 | } |
894eeecc | 316 | |
b0decaf7 | 317 | if (i915_vma_is_active(vma)) |
894eeecc CW |
318 | stats->active += vma->node.size; |
319 | else | |
320 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
321 | } |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
b0da1b79 CW |
326 | #define print_file_stats(m, name, stats) do { \ |
327 | if (stats.count) \ | |
c44ef60e | 328 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
329 | name, \ |
330 | stats.count, \ | |
331 | stats.total, \ | |
332 | stats.active, \ | |
333 | stats.inactive, \ | |
334 | stats.global, \ | |
335 | stats.shared, \ | |
336 | stats.unbound); \ | |
337 | } while (0) | |
493018dc BV |
338 | |
339 | static void print_batch_pool_stats(struct seq_file *m, | |
340 | struct drm_i915_private *dev_priv) | |
341 | { | |
342 | struct drm_i915_gem_object *obj; | |
343 | struct file_stats stats; | |
e2f80391 | 344 | struct intel_engine_cs *engine; |
3b3f1650 | 345 | enum intel_engine_id id; |
b4ac5afc | 346 | int j; |
493018dc BV |
347 | |
348 | memset(&stats, 0, sizeof(stats)); | |
349 | ||
3b3f1650 | 350 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 351 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 352 | list_for_each_entry(obj, |
e2f80391 | 353 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
354 | batch_pool_link) |
355 | per_file_stats(0, obj, &stats); | |
356 | } | |
06fbca71 | 357 | } |
493018dc | 358 | |
b0da1b79 | 359 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
360 | } |
361 | ||
15da9565 CW |
362 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
363 | { | |
364 | struct i915_gem_context *ctx = ptr; | |
365 | int n; | |
366 | ||
367 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
368 | if (ctx->engine[n].state) | |
bf3783e5 | 369 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 370 | if (ctx->engine[n].ring) |
57e88531 | 371 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
372 | } |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static void print_context_stats(struct seq_file *m, | |
378 | struct drm_i915_private *dev_priv) | |
379 | { | |
36cdd013 | 380 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
381 | struct file_stats stats; |
382 | struct drm_file *file; | |
383 | ||
384 | memset(&stats, 0, sizeof(stats)); | |
385 | ||
36cdd013 | 386 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
387 | if (dev_priv->kernel_context) |
388 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
389 | ||
36cdd013 | 390 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
391 | struct drm_i915_file_private *fpriv = file->driver_priv; |
392 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
393 | } | |
36cdd013 | 394 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
395 | |
396 | print_file_stats(m, "[k]contexts", stats); | |
397 | } | |
398 | ||
36cdd013 | 399 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 400 | { |
36cdd013 DW |
401 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
402 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 403 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2bd160a1 CW |
404 | u32 count, mapped_count, purgeable_count, dpy_count; |
405 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 406 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 407 | struct drm_file *file; |
73aa808f CW |
408 | int ret; |
409 | ||
410 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
3ef7f228 | 414 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
415 | dev_priv->mm.object_count, |
416 | dev_priv->mm.object_memory); | |
417 | ||
1544c42e CW |
418 | size = count = 0; |
419 | mapped_size = mapped_count = 0; | |
420 | purgeable_size = purgeable_count = 0; | |
56cea323 | 421 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
422 | size += obj->base.size; |
423 | ++count; | |
424 | ||
a4f5ea64 | 425 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
426 | purgeable_size += obj->base.size; |
427 | ++purgeable_count; | |
428 | } | |
429 | ||
a4f5ea64 | 430 | if (obj->mm.mapping) { |
2bd160a1 CW |
431 | mapped_count++; |
432 | mapped_size += obj->base.size; | |
be19b10d | 433 | } |
b7abb714 | 434 | } |
c44ef60e | 435 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 436 | |
2bd160a1 | 437 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 438 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
439 | size += obj->base.size; |
440 | ++count; | |
441 | ||
30154650 | 442 | if (obj->pin_display) { |
2bd160a1 CW |
443 | dpy_size += obj->base.size; |
444 | ++dpy_count; | |
6299f992 | 445 | } |
2bd160a1 | 446 | |
a4f5ea64 | 447 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
448 | purgeable_size += obj->base.size; |
449 | ++purgeable_count; | |
450 | } | |
2bd160a1 | 451 | |
a4f5ea64 | 452 | if (obj->mm.mapping) { |
2bd160a1 CW |
453 | mapped_count++; |
454 | mapped_size += obj->base.size; | |
be19b10d | 455 | } |
6299f992 | 456 | } |
2bd160a1 CW |
457 | seq_printf(m, "%u bound objects, %llu bytes\n", |
458 | count, size); | |
c44ef60e | 459 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 460 | purgeable_count, purgeable_size); |
2bd160a1 CW |
461 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
462 | mapped_count, mapped_size); | |
463 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
464 | dpy_count, dpy_size); | |
6299f992 | 465 | |
c44ef60e | 466 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 467 | ggtt->base.total, ggtt->mappable_end); |
73aa808f | 468 | |
493018dc BV |
469 | seq_putc(m, '\n'); |
470 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
471 | mutex_unlock(&dev->struct_mutex); |
472 | ||
473 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 474 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
475 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
476 | struct file_stats stats; | |
c84455b4 CW |
477 | struct drm_i915_file_private *file_priv = file->driver_priv; |
478 | struct drm_i915_gem_request *request; | |
3ec2f427 | 479 | struct task_struct *task; |
2db8e9d6 | 480 | |
0caf81b5 CW |
481 | mutex_lock(&dev->struct_mutex); |
482 | ||
2db8e9d6 | 483 | memset(&stats, 0, sizeof(stats)); |
6313c204 | 484 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 485 | spin_lock(&file->table_lock); |
2db8e9d6 | 486 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 487 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
488 | /* |
489 | * Although we have a valid reference on file->pid, that does | |
490 | * not guarantee that the task_struct who called get_pid() is | |
491 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
492 | * Therefore, we need to protect this ->comm access using RCU. | |
493 | */ | |
c84455b4 CW |
494 | request = list_first_entry_or_null(&file_priv->mm.request_list, |
495 | struct drm_i915_gem_request, | |
c8659efa | 496 | client_link); |
3ec2f427 | 497 | rcu_read_lock(); |
c84455b4 CW |
498 | task = pid_task(request && request->ctx->pid ? |
499 | request->ctx->pid : file->pid, | |
500 | PIDTYPE_PID); | |
493018dc | 501 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 502 | rcu_read_unlock(); |
0caf81b5 | 503 | |
c84455b4 | 504 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 505 | } |
1d2ac403 | 506 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
507 | |
508 | return 0; | |
509 | } | |
510 | ||
aee56cff | 511 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 512 | { |
9f25d007 | 513 | struct drm_info_node *node = m->private; |
36cdd013 DW |
514 | struct drm_i915_private *dev_priv = node_to_i915(node); |
515 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 516 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 517 | struct drm_i915_gem_object *obj; |
c44ef60e | 518 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
519 | int count, ret; |
520 | ||
521 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
522 | if (ret) | |
523 | return ret; | |
524 | ||
525 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 526 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 527 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
528 | continue; |
529 | ||
267f0c90 | 530 | seq_puts(m, " "); |
08c18323 | 531 | describe_obj(m, obj); |
267f0c90 | 532 | seq_putc(m, '\n'); |
08c18323 | 533 | total_obj_size += obj->base.size; |
ca1543be | 534 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
535 | count++; |
536 | } | |
537 | ||
538 | mutex_unlock(&dev->struct_mutex); | |
539 | ||
c44ef60e | 540 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
541 | count, total_obj_size, total_gtt_size); |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
493018dc BV |
546 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
547 | { | |
36cdd013 DW |
548 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
549 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 550 | struct drm_i915_gem_object *obj; |
e2f80391 | 551 | struct intel_engine_cs *engine; |
3b3f1650 | 552 | enum intel_engine_id id; |
8d9d5744 | 553 | int total = 0; |
b4ac5afc | 554 | int ret, j; |
493018dc BV |
555 | |
556 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
557 | if (ret) | |
558 | return ret; | |
559 | ||
3b3f1650 | 560 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 561 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
562 | int count; |
563 | ||
564 | count = 0; | |
565 | list_for_each_entry(obj, | |
e2f80391 | 566 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
567 | batch_pool_link) |
568 | count++; | |
569 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 570 | engine->name, j, count); |
8d9d5744 CW |
571 | |
572 | list_for_each_entry(obj, | |
e2f80391 | 573 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
574 | batch_pool_link) { |
575 | seq_puts(m, " "); | |
576 | describe_obj(m, obj); | |
577 | seq_putc(m, '\n'); | |
578 | } | |
579 | ||
580 | total += count; | |
06fbca71 | 581 | } |
493018dc BV |
582 | } |
583 | ||
8d9d5744 | 584 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
585 | |
586 | mutex_unlock(&dev->struct_mutex); | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
1b36595f CW |
591 | static void print_request(struct seq_file *m, |
592 | struct drm_i915_gem_request *rq, | |
593 | const char *prefix) | |
594 | { | |
20311bd3 | 595 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 596 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 597 | rq->priotree.priority, |
1b36595f | 598 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 599 | rq->timeline->common->name); |
1b36595f CW |
600 | } |
601 | ||
2017263e BG |
602 | static int i915_gem_request_info(struct seq_file *m, void *data) |
603 | { | |
36cdd013 DW |
604 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
605 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 606 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
607 | struct intel_engine_cs *engine; |
608 | enum intel_engine_id id; | |
b4ac5afc | 609 | int ret, any; |
de227ef0 CW |
610 | |
611 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
612 | if (ret) | |
613 | return ret; | |
2017263e | 614 | |
2d1070b2 | 615 | any = 0; |
3b3f1650 | 616 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
617 | int count; |
618 | ||
619 | count = 0; | |
73cb9701 | 620 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
621 | count++; |
622 | if (count == 0) | |
a2c7f6fd CW |
623 | continue; |
624 | ||
e2f80391 | 625 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 626 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 627 | print_request(m, req, " "); |
2d1070b2 CW |
628 | |
629 | any++; | |
2017263e | 630 | } |
de227ef0 CW |
631 | mutex_unlock(&dev->struct_mutex); |
632 | ||
2d1070b2 | 633 | if (any == 0) |
267f0c90 | 634 | seq_puts(m, "No requests\n"); |
c2c347a9 | 635 | |
2017263e BG |
636 | return 0; |
637 | } | |
638 | ||
b2223497 | 639 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 640 | struct intel_engine_cs *engine) |
b2223497 | 641 | { |
688e6c72 CW |
642 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
643 | struct rb_node *rb; | |
644 | ||
12471ba8 | 645 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 646 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 647 | |
61d3dc70 | 648 | spin_lock_irq(&b->rb_lock); |
688e6c72 | 649 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 650 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
651 | |
652 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
653 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
654 | } | |
61d3dc70 | 655 | spin_unlock_irq(&b->rb_lock); |
b2223497 CW |
656 | } |
657 | ||
2017263e BG |
658 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
659 | { | |
36cdd013 | 660 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 661 | struct intel_engine_cs *engine; |
3b3f1650 | 662 | enum intel_engine_id id; |
2017263e | 663 | |
3b3f1650 | 664 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 665 | i915_ring_seqno_info(m, engine); |
de227ef0 | 666 | |
2017263e BG |
667 | return 0; |
668 | } | |
669 | ||
670 | ||
671 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
672 | { | |
36cdd013 | 673 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 674 | struct intel_engine_cs *engine; |
3b3f1650 | 675 | enum intel_engine_id id; |
4bb05040 | 676 | int i, pipe; |
de227ef0 | 677 | |
c8c8fb33 | 678 | intel_runtime_pm_get(dev_priv); |
2017263e | 679 | |
36cdd013 | 680 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
681 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
682 | I915_READ(GEN8_MASTER_IRQ)); | |
683 | ||
684 | seq_printf(m, "Display IER:\t%08x\n", | |
685 | I915_READ(VLV_IER)); | |
686 | seq_printf(m, "Display IIR:\t%08x\n", | |
687 | I915_READ(VLV_IIR)); | |
688 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
689 | I915_READ(VLV_IIR_RW)); | |
690 | seq_printf(m, "Display IMR:\t%08x\n", | |
691 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
692 | for_each_pipe(dev_priv, pipe) { |
693 | enum intel_display_power_domain power_domain; | |
694 | ||
695 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
696 | if (!intel_display_power_get_if_enabled(dev_priv, | |
697 | power_domain)) { | |
698 | seq_printf(m, "Pipe %c power disabled\n", | |
699 | pipe_name(pipe)); | |
700 | continue; | |
701 | } | |
702 | ||
74e1ca8c VS |
703 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
704 | pipe_name(pipe), | |
705 | I915_READ(PIPESTAT(pipe))); | |
706 | ||
9c870d03 CW |
707 | intel_display_power_put(dev_priv, power_domain); |
708 | } | |
709 | ||
710 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
711 | seq_printf(m, "Port hotplug:\t%08x\n", |
712 | I915_READ(PORT_HOTPLUG_EN)); | |
713 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
714 | I915_READ(VLV_DPFLIPSTAT)); | |
715 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
716 | I915_READ(DPINVGTT)); | |
9c870d03 | 717 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
718 | |
719 | for (i = 0; i < 4; i++) { | |
720 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
721 | i, I915_READ(GEN8_GT_IMR(i))); | |
722 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
723 | i, I915_READ(GEN8_GT_IIR(i))); | |
724 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
725 | i, I915_READ(GEN8_GT_IER(i))); | |
726 | } | |
727 | ||
728 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
729 | I915_READ(GEN8_PCU_IMR)); | |
730 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
731 | I915_READ(GEN8_PCU_IIR)); | |
732 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
733 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 734 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
735 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
736 | I915_READ(GEN8_MASTER_IRQ)); | |
737 | ||
738 | for (i = 0; i < 4; i++) { | |
739 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
740 | i, I915_READ(GEN8_GT_IMR(i))); | |
741 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
742 | i, I915_READ(GEN8_GT_IIR(i))); | |
743 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
744 | i, I915_READ(GEN8_GT_IER(i))); | |
745 | } | |
746 | ||
055e393f | 747 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
748 | enum intel_display_power_domain power_domain; |
749 | ||
750 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
751 | if (!intel_display_power_get_if_enabled(dev_priv, | |
752 | power_domain)) { | |
22c59960 PZ |
753 | seq_printf(m, "Pipe %c power disabled\n", |
754 | pipe_name(pipe)); | |
755 | continue; | |
756 | } | |
a123f157 | 757 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
758 | pipe_name(pipe), |
759 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 760 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
761 | pipe_name(pipe), |
762 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 763 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
764 | pipe_name(pipe), |
765 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
766 | |
767 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
768 | } |
769 | ||
770 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
771 | I915_READ(GEN8_DE_PORT_IMR)); | |
772 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
773 | I915_READ(GEN8_DE_PORT_IIR)); | |
774 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
775 | I915_READ(GEN8_DE_PORT_IER)); | |
776 | ||
777 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
778 | I915_READ(GEN8_DE_MISC_IMR)); | |
779 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
780 | I915_READ(GEN8_DE_MISC_IIR)); | |
781 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
782 | I915_READ(GEN8_DE_MISC_IER)); | |
783 | ||
784 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
785 | I915_READ(GEN8_PCU_IMR)); | |
786 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
787 | I915_READ(GEN8_PCU_IIR)); | |
788 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
789 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 790 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
791 | seq_printf(m, "Display IER:\t%08x\n", |
792 | I915_READ(VLV_IER)); | |
793 | seq_printf(m, "Display IIR:\t%08x\n", | |
794 | I915_READ(VLV_IIR)); | |
795 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
796 | I915_READ(VLV_IIR_RW)); | |
797 | seq_printf(m, "Display IMR:\t%08x\n", | |
798 | I915_READ(VLV_IMR)); | |
4f4631af CW |
799 | for_each_pipe(dev_priv, pipe) { |
800 | enum intel_display_power_domain power_domain; | |
801 | ||
802 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
803 | if (!intel_display_power_get_if_enabled(dev_priv, | |
804 | power_domain)) { | |
805 | seq_printf(m, "Pipe %c power disabled\n", | |
806 | pipe_name(pipe)); | |
807 | continue; | |
808 | } | |
809 | ||
7e231dbe JB |
810 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
811 | pipe_name(pipe), | |
812 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
813 | intel_display_power_put(dev_priv, power_domain); |
814 | } | |
7e231dbe JB |
815 | |
816 | seq_printf(m, "Master IER:\t%08x\n", | |
817 | I915_READ(VLV_MASTER_IER)); | |
818 | ||
819 | seq_printf(m, "Render IER:\t%08x\n", | |
820 | I915_READ(GTIER)); | |
821 | seq_printf(m, "Render IIR:\t%08x\n", | |
822 | I915_READ(GTIIR)); | |
823 | seq_printf(m, "Render IMR:\t%08x\n", | |
824 | I915_READ(GTIMR)); | |
825 | ||
826 | seq_printf(m, "PM IER:\t\t%08x\n", | |
827 | I915_READ(GEN6_PMIER)); | |
828 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
829 | I915_READ(GEN6_PMIIR)); | |
830 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
831 | I915_READ(GEN6_PMIMR)); | |
832 | ||
833 | seq_printf(m, "Port hotplug:\t%08x\n", | |
834 | I915_READ(PORT_HOTPLUG_EN)); | |
835 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
836 | I915_READ(VLV_DPFLIPSTAT)); | |
837 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
838 | I915_READ(DPINVGTT)); | |
839 | ||
36cdd013 | 840 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
841 | seq_printf(m, "Interrupt enable: %08x\n", |
842 | I915_READ(IER)); | |
843 | seq_printf(m, "Interrupt identity: %08x\n", | |
844 | I915_READ(IIR)); | |
845 | seq_printf(m, "Interrupt mask: %08x\n", | |
846 | I915_READ(IMR)); | |
055e393f | 847 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
848 | seq_printf(m, "Pipe %c stat: %08x\n", |
849 | pipe_name(pipe), | |
850 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
851 | } else { |
852 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
853 | I915_READ(DEIER)); | |
854 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
855 | I915_READ(DEIIR)); | |
856 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
857 | I915_READ(DEIMR)); | |
858 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
859 | I915_READ(SDEIER)); | |
860 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
861 | I915_READ(SDEIIR)); | |
862 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
863 | I915_READ(SDEIMR)); | |
864 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
865 | I915_READ(GTIER)); | |
866 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
867 | I915_READ(GTIIR)); | |
868 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
869 | I915_READ(GTIMR)); | |
870 | } | |
3b3f1650 | 871 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 872 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
873 | seq_printf(m, |
874 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 875 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 876 | } |
e2f80391 | 877 | i915_ring_seqno_info(m, engine); |
9862e600 | 878 | } |
c8c8fb33 | 879 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 880 | |
2017263e BG |
881 | return 0; |
882 | } | |
883 | ||
a6172a80 CW |
884 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
885 | { | |
36cdd013 DW |
886 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
887 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
888 | int i, ret; |
889 | ||
890 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
891 | if (ret) | |
892 | return ret; | |
a6172a80 | 893 | |
a6172a80 CW |
894 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
895 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 896 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 897 | |
6c085a72 CW |
898 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
899 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 900 | if (!vma) |
267f0c90 | 901 | seq_puts(m, "unused"); |
c2c347a9 | 902 | else |
49ef5294 | 903 | describe_obj(m, vma->obj); |
267f0c90 | 904 | seq_putc(m, '\n'); |
a6172a80 CW |
905 | } |
906 | ||
05394f39 | 907 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
908 | return 0; |
909 | } | |
910 | ||
98a2f411 | 911 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
912 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
913 | size_t count, loff_t *pos) | |
d5442303 | 914 | { |
5a4c6f1b CW |
915 | struct i915_gpu_state *error = file->private_data; |
916 | struct drm_i915_error_state_buf str; | |
917 | ssize_t ret; | |
918 | loff_t tmp; | |
d5442303 | 919 | |
5a4c6f1b CW |
920 | if (!error) |
921 | return 0; | |
d5442303 | 922 | |
5a4c6f1b CW |
923 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
924 | if (ret) | |
925 | return ret; | |
d5442303 | 926 | |
5a4c6f1b CW |
927 | ret = i915_error_state_to_str(&str, error); |
928 | if (ret) | |
929 | goto out; | |
d5442303 | 930 | |
5a4c6f1b CW |
931 | tmp = 0; |
932 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
933 | if (ret < 0) | |
934 | goto out; | |
d5442303 | 935 | |
5a4c6f1b CW |
936 | *pos = str.start + ret; |
937 | out: | |
938 | i915_error_state_buf_release(&str); | |
939 | return ret; | |
940 | } | |
edc3d884 | 941 | |
5a4c6f1b CW |
942 | static int gpu_state_release(struct inode *inode, struct file *file) |
943 | { | |
944 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 945 | return 0; |
d5442303 DV |
946 | } |
947 | ||
5a4c6f1b | 948 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 949 | { |
090e5fe3 | 950 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 951 | struct i915_gpu_state *gpu; |
d5442303 | 952 | |
090e5fe3 CW |
953 | intel_runtime_pm_get(i915); |
954 | gpu = i915_capture_gpu_state(i915); | |
955 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
956 | if (!gpu) |
957 | return -ENOMEM; | |
d5442303 | 958 | |
5a4c6f1b | 959 | file->private_data = gpu; |
edc3d884 MK |
960 | return 0; |
961 | } | |
962 | ||
5a4c6f1b CW |
963 | static const struct file_operations i915_gpu_info_fops = { |
964 | .owner = THIS_MODULE, | |
965 | .open = i915_gpu_info_open, | |
966 | .read = gpu_state_read, | |
967 | .llseek = default_llseek, | |
968 | .release = gpu_state_release, | |
969 | }; | |
970 | ||
971 | static ssize_t | |
972 | i915_error_state_write(struct file *filp, | |
973 | const char __user *ubuf, | |
974 | size_t cnt, | |
975 | loff_t *ppos) | |
4dc955f7 | 976 | { |
5a4c6f1b | 977 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 978 | |
5a4c6f1b CW |
979 | if (!error) |
980 | return 0; | |
edc3d884 | 981 | |
5a4c6f1b CW |
982 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
983 | i915_reset_error_state(error->i915); | |
edc3d884 | 984 | |
5a4c6f1b CW |
985 | return cnt; |
986 | } | |
edc3d884 | 987 | |
5a4c6f1b CW |
988 | static int i915_error_state_open(struct inode *inode, struct file *file) |
989 | { | |
990 | file->private_data = i915_first_error_state(inode->i_private); | |
991 | return 0; | |
d5442303 DV |
992 | } |
993 | ||
994 | static const struct file_operations i915_error_state_fops = { | |
995 | .owner = THIS_MODULE, | |
996 | .open = i915_error_state_open, | |
5a4c6f1b | 997 | .read = gpu_state_read, |
d5442303 DV |
998 | .write = i915_error_state_write, |
999 | .llseek = default_llseek, | |
5a4c6f1b | 1000 | .release = gpu_state_release, |
d5442303 | 1001 | }; |
98a2f411 CW |
1002 | #endif |
1003 | ||
647416f9 KC |
1004 | static int |
1005 | i915_next_seqno_set(void *data, u64 val) | |
1006 | { | |
36cdd013 DW |
1007 | struct drm_i915_private *dev_priv = data; |
1008 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1009 | int ret; |
1010 | ||
40633219 MK |
1011 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
73cb9701 | 1015 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1016 | mutex_unlock(&dev->struct_mutex); |
1017 | ||
647416f9 | 1018 | return ret; |
40633219 MK |
1019 | } |
1020 | ||
647416f9 | 1021 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1022 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1023 | "0x%llx\n"); |
40633219 | 1024 | |
adb4bd12 | 1025 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1026 | { |
36cdd013 | 1027 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1028 | int ret = 0; |
1029 | ||
1030 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1031 | |
36cdd013 | 1032 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1033 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1034 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1035 | ||
1036 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1037 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1038 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1039 | MEMSTAT_VID_SHIFT); | |
1040 | seq_printf(m, "Current P-state: %d\n", | |
1041 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1042 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
666a4537 WB |
1043 | u32 freq_sts; |
1044 | ||
1045 | mutex_lock(&dev_priv->rps.hw_lock); | |
1046 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1047 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1048 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1049 | ||
1050 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1051 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1052 | ||
1053 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1054 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1055 | ||
1056 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1057 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1058 | ||
1059 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1060 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1061 | ||
1062 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1063 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1064 | ||
1065 | seq_printf(m, | |
1066 | "efficient (RPe) frequency: %d MHz\n", | |
1067 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1068 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1069 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1070 | u32 rp_state_limits; |
1071 | u32 gt_perf_status; | |
1072 | u32 rp_state_cap; | |
0d8f9491 | 1073 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1074 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1075 | u32 rpupei, rpcurup, rpprevup; |
1076 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1077 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1078 | int max_freq; |
1079 | ||
35040562 | 1080 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1081 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1082 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1083 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1084 | } else { | |
1085 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1086 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1087 | } | |
1088 | ||
3b8d8d91 | 1089 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1090 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1091 | |
8e8c06cd | 1092 | reqf = I915_READ(GEN6_RPNSWREQ); |
35ceabf3 | 1093 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b AG |
1094 | reqf >>= 23; |
1095 | else { | |
1096 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1097 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1098 | reqf >>= 24; |
1099 | else | |
1100 | reqf >>= 25; | |
1101 | } | |
7c59a9c1 | 1102 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1103 | |
0d8f9491 CW |
1104 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1105 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1106 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1107 | ||
ccab5c82 | 1108 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1109 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1110 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1111 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1112 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1113 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1114 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
35ceabf3 | 1115 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b | 1116 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1117 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1118 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1119 | else | |
1120 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1121 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1122 | |
59bad947 | 1123 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1124 | |
36cdd013 | 1125 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1126 | pm_ier = I915_READ(GEN6_PMIER); |
1127 | pm_imr = I915_READ(GEN6_PMIMR); | |
1128 | pm_isr = I915_READ(GEN6_PMISR); | |
1129 | pm_iir = I915_READ(GEN6_PMIIR); | |
1130 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1131 | } else { | |
1132 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1133 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1134 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1135 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1136 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1137 | } | |
0d8f9491 | 1138 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1139 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 SAK |
1140 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
1141 | dev_priv->rps.pm_intrmsk_mbz); | |
3b8d8d91 | 1142 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1143 | seq_printf(m, "Render p-state ratio: %d\n", |
35ceabf3 | 1144 | (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1145 | seq_printf(m, "Render p-state VID: %d\n", |
1146 | gt_perf_status & 0xff); | |
1147 | seq_printf(m, "Render p-state limit: %d\n", | |
1148 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1149 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1150 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1151 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1152 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1153 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1154 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1155 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1156 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1157 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1158 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1159 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1160 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1161 | seq_printf(m, "Up threshold: %d%%\n", |
1162 | dev_priv->rps.up_threshold); | |
1163 | ||
d6cda9c7 AG |
1164 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1165 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1166 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1167 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1168 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1169 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1170 | seq_printf(m, "Down threshold: %d%%\n", |
1171 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1172 | |
cc3f90f0 | 1173 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1174 | rp_state_cap >> 16) & 0xff; |
35ceabf3 RV |
1175 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1176 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1177 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1178 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1179 | |
1180 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
35ceabf3 RV |
1181 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1182 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1183 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1184 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1185 | |
cc3f90f0 | 1186 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1187 | rp_state_cap >> 0) & 0xff; |
35ceabf3 RV |
1188 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1189 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1190 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1191 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1192 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1193 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1194 | |
d86ed34a CW |
1195 | seq_printf(m, "Current freq: %d MHz\n", |
1196 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1197 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1198 | seq_printf(m, "Idle freq: %d MHz\n", |
1199 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1200 | seq_printf(m, "Min freq: %d MHz\n", |
1201 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1202 | seq_printf(m, "Boost freq: %d MHz\n", |
1203 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1204 | seq_printf(m, "Max freq: %d MHz\n", |
1205 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1206 | seq_printf(m, | |
1207 | "efficient (RPe) frequency: %d MHz\n", | |
1208 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1209 | } else { |
267f0c90 | 1210 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1211 | } |
f97108d1 | 1212 | |
49cd97a3 | 1213 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1214 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1215 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1216 | ||
c8c8fb33 PZ |
1217 | intel_runtime_pm_put(dev_priv); |
1218 | return ret; | |
f97108d1 JB |
1219 | } |
1220 | ||
d636951e BW |
1221 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1222 | struct seq_file *m, | |
1223 | struct intel_instdone *instdone) | |
1224 | { | |
f9e61372 BW |
1225 | int slice; |
1226 | int subslice; | |
1227 | ||
d636951e BW |
1228 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1229 | instdone->instdone); | |
1230 | ||
1231 | if (INTEL_GEN(dev_priv) <= 3) | |
1232 | return; | |
1233 | ||
1234 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1235 | instdone->slice_common); | |
1236 | ||
1237 | if (INTEL_GEN(dev_priv) <= 6) | |
1238 | return; | |
1239 | ||
f9e61372 BW |
1240 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1241 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1242 | slice, subslice, instdone->sampler[slice][subslice]); | |
1243 | ||
1244 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1245 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1246 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1247 | } |
1248 | ||
f654449a CW |
1249 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1250 | { | |
36cdd013 | 1251 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1252 | struct intel_engine_cs *engine; |
666796da TU |
1253 | u64 acthd[I915_NUM_ENGINES]; |
1254 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1255 | struct intel_instdone instdone; |
c3232b18 | 1256 | enum intel_engine_id id; |
f654449a | 1257 | |
8af29b0c | 1258 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1259 | seq_puts(m, "Wedged\n"); |
1260 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1261 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1262 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1263 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1264 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1265 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1266 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1267 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1268 | |
f654449a | 1269 | if (!i915.enable_hangcheck) { |
8c185eca | 1270 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1271 | return 0; |
1272 | } | |
1273 | ||
ebbc7546 MK |
1274 | intel_runtime_pm_get(dev_priv); |
1275 | ||
3b3f1650 | 1276 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1277 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1278 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1279 | } |
1280 | ||
3b3f1650 | 1281 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1282 | |
ebbc7546 MK |
1283 | intel_runtime_pm_put(dev_priv); |
1284 | ||
8352aea3 CW |
1285 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1286 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1287 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1288 | jiffies)); | |
8352aea3 CW |
1289 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1290 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1291 | else | |
1292 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1293 | |
f73b5674 CW |
1294 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1295 | ||
3b3f1650 | 1296 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1297 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1298 | struct rb_node *rb; | |
1299 | ||
e2f80391 | 1300 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1301 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1302 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1303 | intel_engine_last_submit(engine), |
1304 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1305 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1306 | yesno(intel_engine_has_waiter(engine)), |
1307 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1308 | &dev_priv->gpu_error.missed_irq_rings)), |
1309 | yesno(engine->hangcheck.stalled)); | |
1310 | ||
61d3dc70 | 1311 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1312 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1313 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1314 | |
1315 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1316 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1317 | } | |
61d3dc70 | 1318 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1319 | |
f654449a | 1320 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1321 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1322 | (long long)acthd[id]); |
3fe3b030 MK |
1323 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1324 | hangcheck_action_to_str(engine->hangcheck.action), | |
1325 | engine->hangcheck.action, | |
1326 | jiffies_to_msecs(jiffies - | |
1327 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1328 | |
e2f80391 | 1329 | if (engine->id == RCS) { |
d636951e | 1330 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1331 | |
d636951e | 1332 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1333 | |
d636951e | 1334 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1335 | |
d636951e BW |
1336 | i915_instdone_info(dev_priv, m, |
1337 | &engine->hangcheck.instdone); | |
61642ff0 | 1338 | } |
f654449a CW |
1339 | } |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
061d06a2 MT |
1344 | static int i915_reset_info(struct seq_file *m, void *unused) |
1345 | { | |
1346 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1347 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
1348 | struct intel_engine_cs *engine; | |
1349 | enum intel_engine_id id; | |
1350 | ||
1351 | seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); | |
1352 | ||
1353 | for_each_engine(engine, dev_priv, id) { | |
1354 | seq_printf(m, "%s = %u\n", engine->name, | |
1355 | i915_reset_engine_count(error, engine)); | |
1356 | } | |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | ||
4d85529d | 1361 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1362 | { |
36cdd013 | 1363 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1364 | u32 rgvmodectl, rstdbyctl; |
1365 | u16 crstandvid; | |
616fdb5a | 1366 | |
616fdb5a BW |
1367 | rgvmodectl = I915_READ(MEMMODECTL); |
1368 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1369 | crstandvid = I915_READ16(CRSTANDVID); | |
1370 | ||
742f491d | 1371 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1372 | seq_printf(m, "Boost freq: %d\n", |
1373 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1374 | MEMMODE_BOOST_FREQ_SHIFT); | |
1375 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1376 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1377 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1378 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1379 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1380 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1381 | seq_printf(m, "Starting frequency: P%d\n", |
1382 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1383 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1384 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1385 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1386 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1387 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1388 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1389 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1390 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1391 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1392 | case RSX_STATUS_ON: | |
267f0c90 | 1393 | seq_puts(m, "on\n"); |
88271da3 JB |
1394 | break; |
1395 | case RSX_STATUS_RC1: | |
267f0c90 | 1396 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1397 | break; |
1398 | case RSX_STATUS_RC1E: | |
267f0c90 | 1399 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1400 | break; |
1401 | case RSX_STATUS_RS1: | |
267f0c90 | 1402 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1403 | break; |
1404 | case RSX_STATUS_RS2: | |
267f0c90 | 1405 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1406 | break; |
1407 | case RSX_STATUS_RS3: | |
267f0c90 | 1408 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1409 | break; |
1410 | default: | |
267f0c90 | 1411 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1412 | break; |
1413 | } | |
f97108d1 JB |
1414 | |
1415 | return 0; | |
1416 | } | |
1417 | ||
f65367b5 | 1418 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1419 | { |
233ebf57 | 1420 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1421 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1422 | unsigned int tmp; |
b2cff0db | 1423 | |
233ebf57 | 1424 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1425 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1426 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1427 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1428 | |
b2cff0db CW |
1429 | return 0; |
1430 | } | |
1431 | ||
1362877e MK |
1432 | static void print_rc6_res(struct seq_file *m, |
1433 | const char *title, | |
1434 | const i915_reg_t reg) | |
1435 | { | |
1436 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1437 | ||
1438 | seq_printf(m, "%s %u (%llu us)\n", | |
1439 | title, I915_READ(reg), | |
1440 | intel_rc6_residency_us(dev_priv, reg)); | |
1441 | } | |
1442 | ||
b2cff0db CW |
1443 | static int vlv_drpc_info(struct seq_file *m) |
1444 | { | |
36cdd013 | 1445 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
6b312cd3 | 1446 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1447 | |
6b312cd3 | 1448 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1449 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1450 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1451 | ||
1452 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1453 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1454 | seq_printf(m, "Turbo enabled: %s\n", | |
1455 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1456 | seq_printf(m, "HW control enabled: %s\n", | |
1457 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1458 | seq_printf(m, "SW control enabled: %s\n", | |
1459 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1460 | GEN6_RP_MEDIA_SW_MODE)); | |
1461 | seq_printf(m, "RC6 Enabled: %s\n", | |
1462 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1463 | GEN6_RC_CTL_EI_MODE(1)))); | |
1464 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1465 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1466 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1467 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1468 | |
1362877e MK |
1469 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1470 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1471 | |
f65367b5 | 1472 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1473 | } |
1474 | ||
4d85529d BW |
1475 | static int gen6_drpc_info(struct seq_file *m) |
1476 | { | |
36cdd013 | 1477 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
ecd8faea | 1478 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1479 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1480 | unsigned forcewake_count; |
cf632bd6 | 1481 | int count = 0; |
93b525dc | 1482 | |
cf632bd6 | 1483 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1484 | if (forcewake_count) { |
267f0c90 DL |
1485 | seq_puts(m, "RC information inaccurate because somebody " |
1486 | "holds a forcewake reference \n"); | |
4d85529d BW |
1487 | } else { |
1488 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1489 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1490 | udelay(10); | |
1491 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1492 | } | |
1493 | ||
75aa3f63 | 1494 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1495 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1496 | |
1497 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1498 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
36cdd013 | 1499 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1500 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1501 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1502 | } | |
cf632bd6 | 1503 | |
44cbd338 BW |
1504 | mutex_lock(&dev_priv->rps.hw_lock); |
1505 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1506 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1507 | |
1508 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1509 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1510 | seq_printf(m, "HW control enabled: %s\n", | |
1511 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1512 | seq_printf(m, "SW control enabled: %s\n", | |
1513 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1514 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1515 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1516 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1517 | seq_printf(m, "RC6 Enabled: %s\n", | |
1518 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1519 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1520 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1521 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1522 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1523 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1524 | } | |
4d85529d BW |
1525 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1526 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1527 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1528 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1529 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1530 | switch (gt_core_status & GEN6_RCn_MASK) { |
1531 | case GEN6_RC0: | |
1532 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1533 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1534 | else |
267f0c90 | 1535 | seq_puts(m, "on\n"); |
4d85529d BW |
1536 | break; |
1537 | case GEN6_RC3: | |
267f0c90 | 1538 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1539 | break; |
1540 | case GEN6_RC6: | |
267f0c90 | 1541 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1542 | break; |
1543 | case GEN6_RC7: | |
267f0c90 | 1544 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1545 | break; |
1546 | default: | |
267f0c90 | 1547 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1548 | break; |
1549 | } | |
1550 | ||
1551 | seq_printf(m, "Core Power Down: %s\n", | |
1552 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1553 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1554 | seq_printf(m, "Render Power Well: %s\n", |
1555 | (gen9_powergate_status & | |
1556 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1557 | seq_printf(m, "Media Power Well: %s\n", | |
1558 | (gen9_powergate_status & | |
1559 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1560 | } | |
cce66a28 BW |
1561 | |
1562 | /* Not exactly sure what this is */ | |
1362877e MK |
1563 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1564 | GEN6_GT_GFX_RC6_LOCKED); | |
1565 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1566 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1567 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1568 | |
ecd8faea BW |
1569 | seq_printf(m, "RC6 voltage: %dmV\n", |
1570 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1571 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1572 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1573 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1574 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1575 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1576 | } |
1577 | ||
1578 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1579 | { | |
36cdd013 | 1580 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1581 | int err; |
1582 | ||
1583 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1584 | |
36cdd013 | 1585 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1586 | err = vlv_drpc_info(m); |
36cdd013 | 1587 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1588 | err = gen6_drpc_info(m); |
4d85529d | 1589 | else |
cf632bd6 CW |
1590 | err = ironlake_drpc_info(m); |
1591 | ||
1592 | intel_runtime_pm_put(dev_priv); | |
1593 | ||
1594 | return err; | |
4d85529d BW |
1595 | } |
1596 | ||
9a851789 DV |
1597 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1598 | { | |
36cdd013 | 1599 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1600 | |
1601 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1602 | dev_priv->fb_tracking.busy_bits); | |
1603 | ||
1604 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1605 | dev_priv->fb_tracking.flip_bits); | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
b5e50c3f JB |
1610 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1611 | { | |
36cdd013 | 1612 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1613 | |
36cdd013 | 1614 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1615 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1616 | return 0; |
1617 | } | |
1618 | ||
36623ef8 | 1619 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1620 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1621 | |
0e631adc | 1622 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1623 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1624 | else |
1625 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1626 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1627 | |
3fd5d1ec VS |
1628 | if (intel_fbc_is_active(dev_priv)) { |
1629 | u32 mask; | |
1630 | ||
1631 | if (INTEL_GEN(dev_priv) >= 8) | |
1632 | mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; | |
1633 | else if (INTEL_GEN(dev_priv) >= 7) | |
1634 | mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; | |
1635 | else if (INTEL_GEN(dev_priv) >= 5) | |
1636 | mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; | |
1637 | else if (IS_G4X(dev_priv)) | |
1638 | mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; | |
1639 | else | |
1640 | mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | | |
1641 | FBC_STAT_COMPRESSED); | |
1642 | ||
1643 | seq_printf(m, "Compressing: %s\n", yesno(mask)); | |
0fc6a9dc | 1644 | } |
31b9df10 | 1645 | |
25ad93fd | 1646 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1647 | intel_runtime_pm_put(dev_priv); |
1648 | ||
b5e50c3f JB |
1649 | return 0; |
1650 | } | |
1651 | ||
4127dc43 | 1652 | static int i915_fbc_false_color_get(void *data, u64 *val) |
da46f936 | 1653 | { |
36cdd013 | 1654 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1655 | |
36cdd013 | 1656 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1657 | return -ENODEV; |
1658 | ||
da46f936 | 1659 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1660 | |
1661 | return 0; | |
1662 | } | |
1663 | ||
4127dc43 | 1664 | static int i915_fbc_false_color_set(void *data, u64 val) |
da46f936 | 1665 | { |
36cdd013 | 1666 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1667 | u32 reg; |
1668 | ||
36cdd013 | 1669 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1670 | return -ENODEV; |
1671 | ||
25ad93fd | 1672 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1673 | |
1674 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1675 | dev_priv->fbc.false_color = val; | |
1676 | ||
1677 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1678 | (reg | FBC_CTL_FALSE_COLOR) : | |
1679 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1680 | ||
25ad93fd | 1681 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1682 | return 0; |
1683 | } | |
1684 | ||
4127dc43 VS |
1685 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, |
1686 | i915_fbc_false_color_get, i915_fbc_false_color_set, | |
da46f936 RV |
1687 | "%llu\n"); |
1688 | ||
92d44621 PZ |
1689 | static int i915_ips_status(struct seq_file *m, void *unused) |
1690 | { | |
36cdd013 | 1691 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1692 | |
36cdd013 | 1693 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1694 | seq_puts(m, "not supported\n"); |
1695 | return 0; | |
1696 | } | |
1697 | ||
36623ef8 PZ |
1698 | intel_runtime_pm_get(dev_priv); |
1699 | ||
0eaa53f0 RV |
1700 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1701 | yesno(i915.enable_ips)); | |
1702 | ||
36cdd013 | 1703 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1704 | seq_puts(m, "Currently: unknown\n"); |
1705 | } else { | |
1706 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1707 | seq_puts(m, "Currently: enabled\n"); | |
1708 | else | |
1709 | seq_puts(m, "Currently: disabled\n"); | |
1710 | } | |
92d44621 | 1711 | |
36623ef8 PZ |
1712 | intel_runtime_pm_put(dev_priv); |
1713 | ||
92d44621 PZ |
1714 | return 0; |
1715 | } | |
1716 | ||
4a9bef37 JB |
1717 | static int i915_sr_status(struct seq_file *m, void *unused) |
1718 | { | |
36cdd013 | 1719 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1720 | bool sr_enabled = false; |
1721 | ||
36623ef8 | 1722 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1723 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1724 | |
7342a72c CW |
1725 | if (INTEL_GEN(dev_priv) >= 9) |
1726 | /* no global SR status; inspect per-plane WM */; | |
1727 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1728 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1729 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1730 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1731 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1732 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1733 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1734 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1735 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1736 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1737 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1738 | |
9c870d03 | 1739 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1740 | intel_runtime_pm_put(dev_priv); |
1741 | ||
08c4d7fc | 1742 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1743 | |
1744 | return 0; | |
1745 | } | |
1746 | ||
7648fa99 JB |
1747 | static int i915_emon_status(struct seq_file *m, void *unused) |
1748 | { | |
36cdd013 DW |
1749 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1750 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1751 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1752 | int ret; |
1753 | ||
36cdd013 | 1754 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1755 | return -ENODEV; |
1756 | ||
de227ef0 CW |
1757 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1758 | if (ret) | |
1759 | return ret; | |
7648fa99 JB |
1760 | |
1761 | temp = i915_mch_val(dev_priv); | |
1762 | chipset = i915_chipset_val(dev_priv); | |
1763 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1764 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1765 | |
1766 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1767 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1768 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1769 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1770 | ||
1771 | return 0; | |
1772 | } | |
1773 | ||
23b2f8bb JB |
1774 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1775 | { | |
36cdd013 | 1776 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1777 | int ret = 0; |
23b2f8bb | 1778 | int gpu_freq, ia_freq; |
f936ec34 | 1779 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1780 | |
26310346 | 1781 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1782 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1783 | return 0; |
1784 | } | |
1785 | ||
5bfa0199 PZ |
1786 | intel_runtime_pm_get(dev_priv); |
1787 | ||
4fc688ce | 1788 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1789 | if (ret) |
5bfa0199 | 1790 | goto out; |
23b2f8bb | 1791 | |
35ceabf3 | 1792 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
f936ec34 AG |
1793 | /* Convert GT frequency to 50 HZ units */ |
1794 | min_gpu_freq = | |
1795 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1796 | max_gpu_freq = | |
1797 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1798 | } else { | |
1799 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1800 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1801 | } | |
1802 | ||
267f0c90 | 1803 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1804 | |
f936ec34 | 1805 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1806 | ia_freq = gpu_freq; |
1807 | sandybridge_pcode_read(dev_priv, | |
1808 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1809 | &ia_freq); | |
3ebecd07 | 1810 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1811 | intel_gpu_freq(dev_priv, (gpu_freq * |
35ceabf3 RV |
1812 | (IS_GEN9_BC(dev_priv) || |
1813 | IS_CANNONLAKE(dev_priv) ? | |
b976dc53 | 1814 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1815 | ((ia_freq >> 0) & 0xff) * 100, |
1816 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1817 | } |
1818 | ||
4fc688ce | 1819 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1820 | |
5bfa0199 PZ |
1821 | out: |
1822 | intel_runtime_pm_put(dev_priv); | |
1823 | return ret; | |
23b2f8bb JB |
1824 | } |
1825 | ||
44834a67 CW |
1826 | static int i915_opregion(struct seq_file *m, void *unused) |
1827 | { | |
36cdd013 DW |
1828 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1829 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1830 | struct intel_opregion *opregion = &dev_priv->opregion; |
1831 | int ret; | |
1832 | ||
1833 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1834 | if (ret) | |
0d38f009 | 1835 | goto out; |
44834a67 | 1836 | |
2455a8e4 JN |
1837 | if (opregion->header) |
1838 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1839 | |
1840 | mutex_unlock(&dev->struct_mutex); | |
1841 | ||
0d38f009 | 1842 | out: |
44834a67 CW |
1843 | return 0; |
1844 | } | |
1845 | ||
ada8f955 JN |
1846 | static int i915_vbt(struct seq_file *m, void *unused) |
1847 | { | |
36cdd013 | 1848 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1849 | |
1850 | if (opregion->vbt) | |
1851 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1852 | ||
1853 | return 0; | |
1854 | } | |
1855 | ||
37811fcc CW |
1856 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1857 | { | |
36cdd013 DW |
1858 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1859 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1860 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1861 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1862 | int ret; |
1863 | ||
1864 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1865 | if (ret) | |
1866 | return ret; | |
37811fcc | 1867 | |
0695726e | 1868 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
346fb4e0 | 1869 | if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { |
36cdd013 | 1870 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); |
25bcce94 CW |
1871 | |
1872 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1873 | fbdev_fb->base.width, | |
1874 | fbdev_fb->base.height, | |
b00c600e | 1875 | fbdev_fb->base.format->depth, |
272725c7 | 1876 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1877 | fbdev_fb->base.modifier, |
25bcce94 CW |
1878 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1879 | describe_obj(m, fbdev_fb->obj); | |
1880 | seq_putc(m, '\n'); | |
1881 | } | |
4520f53a | 1882 | #endif |
37811fcc | 1883 | |
4b096ac1 | 1884 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1885 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1886 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1887 | if (fb == fbdev_fb) | |
37811fcc CW |
1888 | continue; |
1889 | ||
c1ca506d | 1890 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1891 | fb->base.width, |
1892 | fb->base.height, | |
b00c600e | 1893 | fb->base.format->depth, |
272725c7 | 1894 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1895 | fb->base.modifier, |
747a598f | 1896 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1897 | describe_obj(m, fb->obj); |
267f0c90 | 1898 | seq_putc(m, '\n'); |
37811fcc | 1899 | } |
4b096ac1 | 1900 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1901 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1902 | |
1903 | return 0; | |
1904 | } | |
1905 | ||
7e37f889 | 1906 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1907 | { |
fe085f13 CW |
1908 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1909 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1910 | } |
1911 | ||
e76d3630 BW |
1912 | static int i915_context_status(struct seq_file *m, void *unused) |
1913 | { | |
36cdd013 DW |
1914 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1915 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1916 | struct intel_engine_cs *engine; |
e2efd130 | 1917 | struct i915_gem_context *ctx; |
3b3f1650 | 1918 | enum intel_engine_id id; |
c3232b18 | 1919 | int ret; |
e76d3630 | 1920 | |
f3d28878 | 1921 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1922 | if (ret) |
1923 | return ret; | |
1924 | ||
829a0af2 | 1925 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
5d1808ec | 1926 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1927 | if (ctx->pid) { |
d28b99ab CW |
1928 | struct task_struct *task; |
1929 | ||
c84455b4 | 1930 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1931 | if (task) { |
1932 | seq_printf(m, "(%s [%d]) ", | |
1933 | task->comm, task->pid); | |
1934 | put_task_struct(task); | |
1935 | } | |
c84455b4 CW |
1936 | } else if (IS_ERR(ctx->file_priv)) { |
1937 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1938 | } else { |
1939 | seq_puts(m, "(kernel) "); | |
1940 | } | |
1941 | ||
bca44d80 CW |
1942 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1943 | seq_putc(m, '\n'); | |
c9fe99bd | 1944 | |
3b3f1650 | 1945 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
1946 | struct intel_context *ce = &ctx->engine[engine->id]; |
1947 | ||
1948 | seq_printf(m, "%s: ", engine->name); | |
1949 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1950 | if (ce->state) | |
bf3783e5 | 1951 | describe_obj(m, ce->state->obj); |
dca33ecc | 1952 | if (ce->ring) |
7e37f889 | 1953 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1954 | seq_putc(m, '\n'); |
c9fe99bd | 1955 | } |
a33afea5 | 1956 | |
4ff4b44c CW |
1957 | seq_printf(m, |
1958 | "\tvma hashtable size=%u (actual %lu), count=%u\n", | |
1959 | ctx->vma_lut.ht_size, | |
1960 | BIT(ctx->vma_lut.ht_bits), | |
1961 | ctx->vma_lut.ht_count); | |
1962 | ||
a33afea5 | 1963 | seq_putc(m, '\n'); |
a168c293 BW |
1964 | } |
1965 | ||
f3d28878 | 1966 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1967 | |
1968 | return 0; | |
1969 | } | |
1970 | ||
064ca1d2 | 1971 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1972 | struct i915_gem_context *ctx, |
0bc40be8 | 1973 | struct intel_engine_cs *engine) |
064ca1d2 | 1974 | { |
bf3783e5 | 1975 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1976 | struct page *page; |
064ca1d2 | 1977 | int j; |
064ca1d2 | 1978 | |
7069b144 CW |
1979 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
1980 | ||
bf3783e5 CW |
1981 | if (!vma) { |
1982 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
1983 | return; |
1984 | } | |
1985 | ||
bf3783e5 CW |
1986 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
1987 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 1988 | i915_ggtt_offset(vma)); |
064ca1d2 | 1989 | |
a4f5ea64 | 1990 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 1991 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
1992 | return; |
1993 | } | |
1994 | ||
bf3783e5 CW |
1995 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
1996 | if (page) { | |
1997 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
1998 | |
1999 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2000 | seq_printf(m, |
2001 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2002 | j * 4, | |
064ca1d2 TD |
2003 | reg_state[j], reg_state[j + 1], |
2004 | reg_state[j + 2], reg_state[j + 3]); | |
2005 | } | |
2006 | kunmap_atomic(reg_state); | |
2007 | } | |
2008 | ||
a4f5ea64 | 2009 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2010 | seq_putc(m, '\n'); |
2011 | } | |
2012 | ||
c0ab1ae9 BW |
2013 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2014 | { | |
36cdd013 DW |
2015 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2016 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2017 | struct intel_engine_cs *engine; |
e2efd130 | 2018 | struct i915_gem_context *ctx; |
3b3f1650 | 2019 | enum intel_engine_id id; |
b4ac5afc | 2020 | int ret; |
c0ab1ae9 BW |
2021 | |
2022 | if (!i915.enable_execlists) { | |
2023 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2024 | return 0; | |
2025 | } | |
2026 | ||
2027 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2028 | if (ret) | |
2029 | return ret; | |
2030 | ||
829a0af2 | 2031 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) |
3b3f1650 | 2032 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2033 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2034 | |
2035 | mutex_unlock(&dev->struct_mutex); | |
2036 | ||
2037 | return 0; | |
2038 | } | |
2039 | ||
ea16a3cd DV |
2040 | static const char *swizzle_string(unsigned swizzle) |
2041 | { | |
aee56cff | 2042 | switch (swizzle) { |
ea16a3cd DV |
2043 | case I915_BIT_6_SWIZZLE_NONE: |
2044 | return "none"; | |
2045 | case I915_BIT_6_SWIZZLE_9: | |
2046 | return "bit9"; | |
2047 | case I915_BIT_6_SWIZZLE_9_10: | |
2048 | return "bit9/bit10"; | |
2049 | case I915_BIT_6_SWIZZLE_9_11: | |
2050 | return "bit9/bit11"; | |
2051 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2052 | return "bit9/bit10/bit11"; | |
2053 | case I915_BIT_6_SWIZZLE_9_17: | |
2054 | return "bit9/bit17"; | |
2055 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2056 | return "bit9/bit10/bit17"; | |
2057 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2058 | return "unknown"; |
ea16a3cd DV |
2059 | } |
2060 | ||
2061 | return "bug"; | |
2062 | } | |
2063 | ||
2064 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2065 | { | |
36cdd013 | 2066 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2067 | |
c8c8fb33 | 2068 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2069 | |
ea16a3cd DV |
2070 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2071 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2072 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2073 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2074 | ||
36cdd013 | 2075 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2076 | seq_printf(m, "DDC = 0x%08x\n", |
2077 | I915_READ(DCC)); | |
656bfa3a DV |
2078 | seq_printf(m, "DDC2 = 0x%08x\n", |
2079 | I915_READ(DCC2)); | |
ea16a3cd DV |
2080 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2081 | I915_READ16(C0DRB3)); | |
2082 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2083 | I915_READ16(C1DRB3)); | |
36cdd013 | 2084 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2085 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2086 | I915_READ(MAD_DIMM_C0)); | |
2087 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2088 | I915_READ(MAD_DIMM_C1)); | |
2089 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2090 | I915_READ(MAD_DIMM_C2)); | |
2091 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2092 | I915_READ(TILECTL)); | |
36cdd013 | 2093 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2094 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2095 | I915_READ(GAMTARBMODE)); | |
2096 | else | |
2097 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2098 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2099 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2100 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2101 | } |
656bfa3a DV |
2102 | |
2103 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2104 | seq_puts(m, "L-shaped memory detected\n"); | |
2105 | ||
c8c8fb33 | 2106 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2107 | |
2108 | return 0; | |
2109 | } | |
2110 | ||
1c60fef5 BW |
2111 | static int per_file_ctx(int id, void *ptr, void *data) |
2112 | { | |
e2efd130 | 2113 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2114 | struct seq_file *m = data; |
ae6c4806 DV |
2115 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2116 | ||
2117 | if (!ppgtt) { | |
2118 | seq_printf(m, " no ppgtt for context %d\n", | |
2119 | ctx->user_handle); | |
2120 | return 0; | |
2121 | } | |
1c60fef5 | 2122 | |
f83d6518 OM |
2123 | if (i915_gem_context_is_default(ctx)) |
2124 | seq_puts(m, " default context:\n"); | |
2125 | else | |
821d66dd | 2126 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2127 | ppgtt->debug_dump(ppgtt, m); |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
36cdd013 DW |
2132 | static void gen8_ppgtt_info(struct seq_file *m, |
2133 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2134 | { |
77df6772 | 2135 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2136 | struct intel_engine_cs *engine; |
2137 | enum intel_engine_id id; | |
b4ac5afc | 2138 | int i; |
3cf17fc5 | 2139 | |
77df6772 BW |
2140 | if (!ppgtt) |
2141 | return; | |
2142 | ||
3b3f1650 | 2143 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2144 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2145 | for (i = 0; i < 4; i++) { |
e2f80391 | 2146 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2147 | pdp <<= 32; |
e2f80391 | 2148 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2149 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2150 | } |
2151 | } | |
2152 | } | |
2153 | ||
36cdd013 DW |
2154 | static void gen6_ppgtt_info(struct seq_file *m, |
2155 | struct drm_i915_private *dev_priv) | |
77df6772 | 2156 | { |
e2f80391 | 2157 | struct intel_engine_cs *engine; |
3b3f1650 | 2158 | enum intel_engine_id id; |
3cf17fc5 | 2159 | |
7e22dbbb | 2160 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2161 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2162 | ||
3b3f1650 | 2163 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2164 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2165 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2166 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2167 | I915_READ(RING_MODE_GEN7(engine))); | |
2168 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2169 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2170 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2171 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2172 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2173 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2174 | } |
2175 | if (dev_priv->mm.aliasing_ppgtt) { | |
2176 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2177 | ||
267f0c90 | 2178 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2179 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2180 | |
87d60b63 | 2181 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2182 | } |
1c60fef5 | 2183 | |
3cf17fc5 | 2184 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2185 | } |
2186 | ||
2187 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2188 | { | |
36cdd013 DW |
2189 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2190 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2191 | struct drm_file *file; |
637ee29e | 2192 | int ret; |
77df6772 | 2193 | |
637ee29e CW |
2194 | mutex_lock(&dev->filelist_mutex); |
2195 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2196 | if (ret) |
637ee29e CW |
2197 | goto out_unlock; |
2198 | ||
c8c8fb33 | 2199 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2200 | |
36cdd013 DW |
2201 | if (INTEL_GEN(dev_priv) >= 8) |
2202 | gen8_ppgtt_info(m, dev_priv); | |
2203 | else if (INTEL_GEN(dev_priv) >= 6) | |
2204 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2205 | |
ea91e401 MT |
2206 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2207 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2208 | struct task_struct *task; |
ea91e401 | 2209 | |
7cb5dff8 | 2210 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2211 | if (!task) { |
2212 | ret = -ESRCH; | |
637ee29e | 2213 | goto out_rpm; |
06812760 | 2214 | } |
7cb5dff8 GT |
2215 | seq_printf(m, "\nproc: %s\n", task->comm); |
2216 | put_task_struct(task); | |
ea91e401 MT |
2217 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2218 | (void *)(unsigned long)m); | |
2219 | } | |
2220 | ||
637ee29e | 2221 | out_rpm: |
c8c8fb33 | 2222 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2223 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2224 | out_unlock: |
2225 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2226 | return ret; |
3cf17fc5 DV |
2227 | } |
2228 | ||
f5a4c67d CW |
2229 | static int count_irq_waiters(struct drm_i915_private *i915) |
2230 | { | |
e2f80391 | 2231 | struct intel_engine_cs *engine; |
3b3f1650 | 2232 | enum intel_engine_id id; |
f5a4c67d | 2233 | int count = 0; |
f5a4c67d | 2234 | |
3b3f1650 | 2235 | for_each_engine(engine, i915, id) |
688e6c72 | 2236 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2237 | |
2238 | return count; | |
2239 | } | |
2240 | ||
7466c291 CW |
2241 | static const char *rps_power_to_str(unsigned int power) |
2242 | { | |
2243 | static const char * const strings[] = { | |
2244 | [LOW_POWER] = "low power", | |
2245 | [BETWEEN] = "mixed", | |
2246 | [HIGH_POWER] = "high power", | |
2247 | }; | |
2248 | ||
2249 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2250 | return "unknown"; | |
2251 | ||
2252 | return strings[power]; | |
2253 | } | |
2254 | ||
1854d5ca CW |
2255 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2256 | { | |
36cdd013 DW |
2257 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2258 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2259 | struct drm_file *file; |
1854d5ca | 2260 | |
f5a4c67d | 2261 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2262 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2263 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2264 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7b92c1bd CW |
2265 | seq_printf(m, "Boosts outstanding? %d\n", |
2266 | atomic_read(&dev_priv->rps.num_waiters)); | |
7466c291 CW |
2267 | seq_printf(m, "Frequency requested %d\n", |
2268 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2269 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2270 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2271 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2272 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2273 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2274 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2275 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2276 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2277 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2278 | |
2279 | mutex_lock(&dev->filelist_mutex); | |
1854d5ca CW |
2280 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2281 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2282 | struct task_struct *task; | |
2283 | ||
2284 | rcu_read_lock(); | |
2285 | task = pid_task(file->pid, PIDTYPE_PID); | |
7b92c1bd | 2286 | seq_printf(m, "%s [%d]: %d boosts\n", |
1854d5ca CW |
2287 | task ? task->comm : "<unknown>", |
2288 | task ? task->pid : -1, | |
7b92c1bd | 2289 | atomic_read(&file_priv->rps.boosts)); |
1854d5ca CW |
2290 | rcu_read_unlock(); |
2291 | } | |
7b92c1bd CW |
2292 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", |
2293 | atomic_read(&dev_priv->rps.boosts)); | |
1d2ac403 | 2294 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2295 | |
7466c291 CW |
2296 | if (INTEL_GEN(dev_priv) >= 6 && |
2297 | dev_priv->rps.enabled && | |
28176ef4 | 2298 | dev_priv->gt.active_requests) { |
7466c291 CW |
2299 | u32 rpup, rpupei; |
2300 | u32 rpdown, rpdownei; | |
2301 | ||
2302 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2303 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2304 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2305 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2306 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2307 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2308 | ||
2309 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2310 | rps_power_to_str(dev_priv->rps.power)); | |
2311 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2312 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2313 | dev_priv->rps.up_threshold); |
2314 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2315 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2316 | dev_priv->rps.down_threshold); |
2317 | } else { | |
2318 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2319 | } | |
2320 | ||
8d3afd7d | 2321 | return 0; |
1854d5ca CW |
2322 | } |
2323 | ||
63573eb7 BW |
2324 | static int i915_llc(struct seq_file *m, void *data) |
2325 | { | |
36cdd013 | 2326 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2327 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2328 | |
36cdd013 | 2329 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2330 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2331 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2332 | |
2333 | return 0; | |
2334 | } | |
2335 | ||
0509ead1 AS |
2336 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2337 | { | |
2338 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2339 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2340 | ||
2341 | if (!HAS_HUC_UCODE(dev_priv)) | |
2342 | return 0; | |
2343 | ||
2344 | seq_puts(m, "HuC firmware status:\n"); | |
2345 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2346 | seq_printf(m, "\tfetch: %s\n", | |
2347 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2348 | seq_printf(m, "\tload: %s\n", | |
2349 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2350 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2351 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2352 | seq_printf(m, "\tversion found: %d.%d\n", | |
2353 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2354 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2355 | huc_fw->header_offset, huc_fw->header_size); | |
2356 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2357 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2358 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2359 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2360 | ||
3582ad13 | 2361 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2362 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2363 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2364 | |
2365 | return 0; | |
2366 | } | |
2367 | ||
fdf5d357 AD |
2368 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2369 | { | |
36cdd013 | 2370 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2371 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2372 | u32 tmp, i; |
2373 | ||
2d1fe073 | 2374 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2375 | return 0; |
2376 | ||
2377 | seq_printf(m, "GuC firmware status:\n"); | |
2378 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2379 | guc_fw->path); |
fdf5d357 | 2380 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2381 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2382 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2383 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2384 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2385 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2386 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2387 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2388 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2389 | guc_fw->header_offset, guc_fw->header_size); | |
2390 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2391 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2392 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2393 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2394 | |
3582ad13 | 2395 | intel_runtime_pm_get(dev_priv); |
2396 | ||
fdf5d357 AD |
2397 | tmp = I915_READ(GUC_STATUS); |
2398 | ||
2399 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2400 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2401 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2402 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2403 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2404 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2405 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2406 | seq_puts(m, "\nScratch registers:\n"); | |
2407 | for (i = 0; i < 16; i++) | |
2408 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2409 | ||
3582ad13 | 2410 | intel_runtime_pm_put(dev_priv); |
2411 | ||
fdf5d357 AD |
2412 | return 0; |
2413 | } | |
2414 | ||
5aa1ee4b AG |
2415 | static void i915_guc_log_info(struct seq_file *m, |
2416 | struct drm_i915_private *dev_priv) | |
2417 | { | |
2418 | struct intel_guc *guc = &dev_priv->guc; | |
2419 | ||
2420 | seq_puts(m, "\nGuC logging stats:\n"); | |
2421 | ||
2422 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2423 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2424 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2425 | ||
2426 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2427 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2428 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2429 | ||
2430 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2431 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2432 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2433 | ||
2434 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2435 | guc->log.flush_interrupt_count); | |
2436 | ||
2437 | seq_printf(m, "\tCapture miss count: %u\n", | |
2438 | guc->log.capture_miss_count); | |
2439 | } | |
2440 | ||
8b417c26 DG |
2441 | static void i915_guc_client_info(struct seq_file *m, |
2442 | struct drm_i915_private *dev_priv, | |
2443 | struct i915_guc_client *client) | |
2444 | { | |
e2f80391 | 2445 | struct intel_engine_cs *engine; |
c18468c4 | 2446 | enum intel_engine_id id; |
8b417c26 | 2447 | uint64_t tot = 0; |
8b417c26 | 2448 | |
b09935a6 OM |
2449 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2450 | client->priority, client->stage_id, client->proc_desc_offset); | |
abddffdf | 2451 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n", |
357248bf | 2452 | client->doorbell_id, client->doorbell_offset, client->doorbell_cookie); |
8b417c26 DG |
2453 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
2454 | client->wq_size, client->wq_offset, client->wq_tail); | |
2455 | ||
551aaecd | 2456 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 | 2457 | |
3b3f1650 | 2458 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2459 | u64 submissions = client->submissions[id]; |
2460 | tot += submissions; | |
8b417c26 | 2461 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2462 | submissions, engine->name); |
8b417c26 DG |
2463 | } |
2464 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2465 | } | |
2466 | ||
a8b9370f | 2467 | static bool check_guc_submission(struct seq_file *m) |
8b417c26 | 2468 | { |
36cdd013 | 2469 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2470 | const struct intel_guc *guc = &dev_priv->guc; |
8b417c26 | 2471 | |
334636c6 CW |
2472 | if (!guc->execbuf_client) { |
2473 | seq_printf(m, "GuC submission %s\n", | |
2474 | HAS_GUC_SCHED(dev_priv) ? | |
2475 | "disabled" : | |
2476 | "not supported"); | |
a8b9370f | 2477 | return false; |
334636c6 | 2478 | } |
8b417c26 | 2479 | |
a8b9370f OM |
2480 | return true; |
2481 | } | |
2482 | ||
2483 | static int i915_guc_info(struct seq_file *m, void *data) | |
2484 | { | |
2485 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2486 | const struct intel_guc *guc = &dev_priv->guc; | |
a8b9370f OM |
2487 | |
2488 | if (!check_guc_submission(m)) | |
2489 | return 0; | |
2490 | ||
9636f6db | 2491 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2492 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2493 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2494 | |
334636c6 CW |
2495 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2496 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2497 | |
5aa1ee4b AG |
2498 | i915_guc_log_info(m, dev_priv); |
2499 | ||
8b417c26 DG |
2500 | /* Add more as required ... */ |
2501 | ||
2502 | return 0; | |
2503 | } | |
2504 | ||
a8b9370f | 2505 | static int i915_guc_stage_pool(struct seq_file *m, void *data) |
4c7e77fc | 2506 | { |
36cdd013 | 2507 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a8b9370f OM |
2508 | const struct intel_guc *guc = &dev_priv->guc; |
2509 | struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; | |
2510 | struct i915_guc_client *client = guc->execbuf_client; | |
2511 | unsigned int tmp; | |
2512 | int index; | |
4c7e77fc | 2513 | |
a8b9370f | 2514 | if (!check_guc_submission(m)) |
4c7e77fc AD |
2515 | return 0; |
2516 | ||
a8b9370f OM |
2517 | for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { |
2518 | struct intel_engine_cs *engine; | |
2519 | ||
2520 | if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)) | |
2521 | continue; | |
2522 | ||
2523 | seq_printf(m, "GuC stage descriptor %u:\n", index); | |
2524 | seq_printf(m, "\tIndex: %u\n", desc->stage_id); | |
2525 | seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); | |
2526 | seq_printf(m, "\tPriority: %d\n", desc->priority); | |
2527 | seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); | |
2528 | seq_printf(m, "\tEngines used: 0x%x\n", | |
2529 | desc->engines_used); | |
2530 | seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", | |
2531 | desc->db_trigger_phy, | |
2532 | desc->db_trigger_cpu, | |
2533 | desc->db_trigger_uk); | |
2534 | seq_printf(m, "\tProcess descriptor: 0x%x\n", | |
2535 | desc->process_desc); | |
9a09485d | 2536 | seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", |
a8b9370f OM |
2537 | desc->wq_addr, desc->wq_size); |
2538 | seq_putc(m, '\n'); | |
2539 | ||
2540 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { | |
2541 | u32 guc_engine_id = engine->guc_id; | |
2542 | struct guc_execlist_context *lrc = | |
2543 | &desc->lrc[guc_engine_id]; | |
2544 | ||
2545 | seq_printf(m, "\t%s LRC:\n", engine->name); | |
2546 | seq_printf(m, "\t\tContext desc: 0x%x\n", | |
2547 | lrc->context_desc); | |
2548 | seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); | |
2549 | seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); | |
2550 | seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); | |
2551 | seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); | |
2552 | seq_putc(m, '\n'); | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | return 0; | |
2557 | } | |
2558 | ||
4c7e77fc AD |
2559 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2560 | { | |
ac58d2ab DCS |
2561 | struct drm_info_node *node = m->private; |
2562 | struct drm_i915_private *dev_priv = node_to_i915(node); | |
2563 | bool dump_load_err = !!node->info_ent->data; | |
2564 | struct drm_i915_gem_object *obj = NULL; | |
2565 | u32 *log; | |
2566 | int i = 0; | |
4c7e77fc | 2567 | |
ac58d2ab DCS |
2568 | if (dump_load_err) |
2569 | obj = dev_priv->guc.load_err_log; | |
2570 | else if (dev_priv->guc.log.vma) | |
2571 | obj = dev_priv->guc.log.vma->obj; | |
4c7e77fc | 2572 | |
ac58d2ab DCS |
2573 | if (!obj) |
2574 | return 0; | |
4c7e77fc | 2575 | |
ac58d2ab DCS |
2576 | log = i915_gem_object_pin_map(obj, I915_MAP_WC); |
2577 | if (IS_ERR(log)) { | |
2578 | DRM_DEBUG("Failed to pin object\n"); | |
2579 | seq_puts(m, "(log data unaccessible)\n"); | |
2580 | return PTR_ERR(log); | |
4c7e77fc AD |
2581 | } |
2582 | ||
ac58d2ab DCS |
2583 | for (i = 0; i < obj->base.size / sizeof(u32); i += 4) |
2584 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2585 | *(log + i), *(log + i + 1), | |
2586 | *(log + i + 2), *(log + i + 3)); | |
2587 | ||
4c7e77fc AD |
2588 | seq_putc(m, '\n'); |
2589 | ||
ac58d2ab DCS |
2590 | i915_gem_object_unpin_map(obj); |
2591 | ||
4c7e77fc AD |
2592 | return 0; |
2593 | } | |
2594 | ||
685534ef SAK |
2595 | static int i915_guc_log_control_get(void *data, u64 *val) |
2596 | { | |
bcc36d8a | 2597 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2598 | |
2599 | if (!dev_priv->guc.log.vma) | |
2600 | return -EINVAL; | |
2601 | ||
2602 | *val = i915.guc_log_level; | |
2603 | ||
2604 | return 0; | |
2605 | } | |
2606 | ||
2607 | static int i915_guc_log_control_set(void *data, u64 val) | |
2608 | { | |
bcc36d8a | 2609 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2610 | int ret; |
2611 | ||
2612 | if (!dev_priv->guc.log.vma) | |
2613 | return -EINVAL; | |
2614 | ||
bcc36d8a | 2615 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2616 | if (ret) |
2617 | return ret; | |
2618 | ||
2619 | intel_runtime_pm_get(dev_priv); | |
2620 | ret = i915_guc_log_control(dev_priv, val); | |
2621 | intel_runtime_pm_put(dev_priv); | |
2622 | ||
bcc36d8a | 2623 | mutex_unlock(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2624 | return ret; |
2625 | } | |
2626 | ||
2627 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2628 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2629 | "%lld\n"); | |
2630 | ||
b86bef20 CW |
2631 | static const char *psr2_live_status(u32 val) |
2632 | { | |
2633 | static const char * const live_status[] = { | |
2634 | "IDLE", | |
2635 | "CAPTURE", | |
2636 | "CAPTURE_FS", | |
2637 | "SLEEP", | |
2638 | "BUFON_FW", | |
2639 | "ML_UP", | |
2640 | "SU_STANDBY", | |
2641 | "FAST_SLEEP", | |
2642 | "DEEP_SLEEP", | |
2643 | "BUF_ON", | |
2644 | "TG_ON" | |
2645 | }; | |
2646 | ||
2647 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2648 | if (val < ARRAY_SIZE(live_status)) | |
2649 | return live_status[val]; | |
2650 | ||
2651 | return "unknown"; | |
2652 | } | |
2653 | ||
e91fd8c6 RV |
2654 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2655 | { | |
36cdd013 | 2656 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2657 | u32 psrperf = 0; |
a6cbdb8e RV |
2658 | u32 stat[3]; |
2659 | enum pipe pipe; | |
a031d709 | 2660 | bool enabled = false; |
e91fd8c6 | 2661 | |
36cdd013 | 2662 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2663 | seq_puts(m, "PSR not supported\n"); |
2664 | return 0; | |
2665 | } | |
2666 | ||
c8c8fb33 PZ |
2667 | intel_runtime_pm_get(dev_priv); |
2668 | ||
fa128fa6 | 2669 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2670 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2671 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2672 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2673 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2674 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2675 | dev_priv->psr.busy_frontbuffer_bits); | |
2676 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2677 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2678 | |
7e3eb599 NV |
2679 | if (HAS_DDI(dev_priv)) { |
2680 | if (dev_priv->psr.psr2_support) | |
2681 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2682 | else | |
2683 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2684 | } else { | |
3553a8ea | 2685 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2686 | enum transcoder cpu_transcoder = |
2687 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2688 | enum intel_display_power_domain power_domain; | |
2689 | ||
2690 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2691 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2692 | power_domain)) | |
2693 | continue; | |
2694 | ||
3553a8ea DL |
2695 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2696 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2697 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2698 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2699 | enabled = true; | |
9c870d03 CW |
2700 | |
2701 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2702 | } |
2703 | } | |
60e5ffe3 RV |
2704 | |
2705 | seq_printf(m, "Main link in standby mode: %s\n", | |
2706 | yesno(dev_priv->psr.link_standby)); | |
2707 | ||
a6cbdb8e RV |
2708 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2709 | ||
36cdd013 | 2710 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2711 | for_each_pipe(dev_priv, pipe) { |
2712 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2713 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2714 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2715 | } | |
2716 | seq_puts(m, "\n"); | |
e91fd8c6 | 2717 | |
05eec3c2 RV |
2718 | /* |
2719 | * VLV/CHV PSR has no kind of performance counter | |
2720 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2721 | */ | |
36cdd013 | 2722 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2723 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2724 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2725 | |
2726 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2727 | } | |
6ba1f9e1 | 2728 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2729 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2730 | ||
2731 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2732 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2733 | } |
fa128fa6 | 2734 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2735 | |
c8c8fb33 | 2736 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2737 | return 0; |
2738 | } | |
2739 | ||
d2e216d0 RV |
2740 | static int i915_sink_crc(struct seq_file *m, void *data) |
2741 | { | |
36cdd013 DW |
2742 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2743 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2744 | struct intel_connector *connector; |
3f6a5e1e | 2745 | struct drm_connector_list_iter conn_iter; |
d2e216d0 RV |
2746 | struct intel_dp *intel_dp = NULL; |
2747 | int ret; | |
2748 | u8 crc[6]; | |
2749 | ||
2750 | drm_modeset_lock_all(dev); | |
3f6a5e1e DV |
2751 | drm_connector_list_iter_begin(dev, &conn_iter); |
2752 | for_each_intel_connector_iter(connector, &conn_iter) { | |
26c17cf6 | 2753 | struct drm_crtc *crtc; |
d2e216d0 | 2754 | |
26c17cf6 | 2755 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2756 | continue; |
2757 | ||
26c17cf6 ML |
2758 | crtc = connector->base.state->crtc; |
2759 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2760 | continue; |
2761 | ||
26c17cf6 | 2762 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2763 | continue; |
2764 | ||
26c17cf6 | 2765 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2766 | |
2767 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2768 | if (ret) | |
2769 | goto out; | |
2770 | ||
2771 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2772 | crc[0], crc[1], crc[2], | |
2773 | crc[3], crc[4], crc[5]); | |
2774 | goto out; | |
2775 | } | |
2776 | ret = -ENODEV; | |
2777 | out: | |
3f6a5e1e | 2778 | drm_connector_list_iter_end(&conn_iter); |
d2e216d0 RV |
2779 | drm_modeset_unlock_all(dev); |
2780 | return ret; | |
2781 | } | |
2782 | ||
ec013e7f JB |
2783 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2784 | { | |
36cdd013 | 2785 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
d38014ea | 2786 | unsigned long long power; |
ec013e7f JB |
2787 | u32 units; |
2788 | ||
36cdd013 | 2789 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2790 | return -ENODEV; |
2791 | ||
36623ef8 PZ |
2792 | intel_runtime_pm_get(dev_priv); |
2793 | ||
d38014ea GKB |
2794 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { |
2795 | intel_runtime_pm_put(dev_priv); | |
2796 | return -ENODEV; | |
2797 | } | |
2798 | ||
2799 | units = (power & 0x1f00) >> 8; | |
ec013e7f | 2800 | power = I915_READ(MCH_SECP_NRG_STTS); |
d38014ea | 2801 | power = (1000000 * power) >> units; /* convert to uJ */ |
ec013e7f | 2802 | |
36623ef8 PZ |
2803 | intel_runtime_pm_put(dev_priv); |
2804 | ||
d38014ea | 2805 | seq_printf(m, "%llu", power); |
371db66a PZ |
2806 | |
2807 | return 0; | |
2808 | } | |
2809 | ||
6455c870 | 2810 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2811 | { |
36cdd013 | 2812 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2813 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2814 | |
a156e64d CW |
2815 | if (!HAS_RUNTIME_PM(dev_priv)) |
2816 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2817 | |
67d97da3 | 2818 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2819 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2820 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2821 | #ifdef CONFIG_PM |
a6aaec8b | 2822 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2823 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2824 | #else |
2825 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2826 | #endif | |
a156e64d | 2827 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2828 | pci_power_name(pdev->current_state), |
2829 | pdev->current_state); | |
371db66a | 2830 | |
ec013e7f JB |
2831 | return 0; |
2832 | } | |
2833 | ||
1da51581 ID |
2834 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2835 | { | |
36cdd013 | 2836 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2837 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2838 | int i; | |
2839 | ||
2840 | mutex_lock(&power_domains->lock); | |
2841 | ||
2842 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2843 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2844 | struct i915_power_well *power_well; | |
2845 | enum intel_display_power_domain power_domain; | |
2846 | ||
2847 | power_well = &power_domains->power_wells[i]; | |
2848 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2849 | power_well->count); | |
2850 | ||
8385c2ec | 2851 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2852 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2853 | intel_display_power_domain_str(power_domain), |
1da51581 | 2854 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2855 | } |
2856 | ||
2857 | mutex_unlock(&power_domains->lock); | |
2858 | ||
2859 | return 0; | |
2860 | } | |
2861 | ||
b7cec66d DL |
2862 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2863 | { | |
36cdd013 | 2864 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2865 | struct intel_csr *csr; |
2866 | ||
36cdd013 | 2867 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2868 | seq_puts(m, "not supported\n"); |
2869 | return 0; | |
2870 | } | |
2871 | ||
2872 | csr = &dev_priv->csr; | |
2873 | ||
6fb403de MK |
2874 | intel_runtime_pm_get(dev_priv); |
2875 | ||
b7cec66d DL |
2876 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2877 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2878 | ||
2879 | if (!csr->dmc_payload) | |
6fb403de | 2880 | goto out; |
b7cec66d DL |
2881 | |
2882 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2883 | CSR_VERSION_MINOR(csr->version)); | |
2884 | ||
48de568c MK |
2885 | if (IS_KABYLAKE(dev_priv) || |
2886 | (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) { | |
8337206d DL |
2887 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2888 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2889 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2890 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2891 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2892 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2893 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2894 | } |
2895 | ||
6fb403de MK |
2896 | out: |
2897 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2898 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2899 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2900 | ||
8337206d DL |
2901 | intel_runtime_pm_put(dev_priv); |
2902 | ||
b7cec66d DL |
2903 | return 0; |
2904 | } | |
2905 | ||
53f5e3ca JB |
2906 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2907 | struct drm_display_mode *mode) | |
2908 | { | |
2909 | int i; | |
2910 | ||
2911 | for (i = 0; i < tabs; i++) | |
2912 | seq_putc(m, '\t'); | |
2913 | ||
2914 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2915 | mode->base.id, mode->name, | |
2916 | mode->vrefresh, mode->clock, | |
2917 | mode->hdisplay, mode->hsync_start, | |
2918 | mode->hsync_end, mode->htotal, | |
2919 | mode->vdisplay, mode->vsync_start, | |
2920 | mode->vsync_end, mode->vtotal, | |
2921 | mode->type, mode->flags); | |
2922 | } | |
2923 | ||
2924 | static void intel_encoder_info(struct seq_file *m, | |
2925 | struct intel_crtc *intel_crtc, | |
2926 | struct intel_encoder *intel_encoder) | |
2927 | { | |
36cdd013 DW |
2928 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2929 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2930 | struct drm_crtc *crtc = &intel_crtc->base; |
2931 | struct intel_connector *intel_connector; | |
2932 | struct drm_encoder *encoder; | |
2933 | ||
2934 | encoder = &intel_encoder->base; | |
2935 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2936 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2937 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2938 | struct drm_connector *connector = &intel_connector->base; | |
2939 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2940 | connector->base.id, | |
c23cc417 | 2941 | connector->name, |
53f5e3ca JB |
2942 | drm_get_connector_status_name(connector->status)); |
2943 | if (connector->status == connector_status_connected) { | |
2944 | struct drm_display_mode *mode = &crtc->mode; | |
2945 | seq_printf(m, ", mode:\n"); | |
2946 | intel_seq_print_mode(m, 2, mode); | |
2947 | } else { | |
2948 | seq_putc(m, '\n'); | |
2949 | } | |
2950 | } | |
2951 | } | |
2952 | ||
2953 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2954 | { | |
36cdd013 DW |
2955 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2956 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2957 | struct drm_crtc *crtc = &intel_crtc->base; |
2958 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2959 | struct drm_plane_state *plane_state = crtc->primary->state; |
2960 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2961 | |
23a48d53 | 2962 | if (fb) |
5aa8a937 | 2963 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2964 | fb->base.id, plane_state->src_x >> 16, |
2965 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2966 | else |
2967 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2968 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2969 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2970 | } | |
2971 | ||
2972 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2973 | { | |
2974 | struct drm_display_mode *mode = panel->fixed_mode; | |
2975 | ||
2976 | seq_printf(m, "\tfixed mode:\n"); | |
2977 | intel_seq_print_mode(m, 2, mode); | |
2978 | } | |
2979 | ||
2980 | static void intel_dp_info(struct seq_file *m, | |
2981 | struct intel_connector *intel_connector) | |
2982 | { | |
2983 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2984 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2985 | ||
2986 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2987 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2988 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 2989 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
2990 | |
2991 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
2992 | &intel_dp->aux); | |
53f5e3ca JB |
2993 | } |
2994 | ||
9a148a96 LY |
2995 | static void intel_dp_mst_info(struct seq_file *m, |
2996 | struct intel_connector *intel_connector) | |
2997 | { | |
2998 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2999 | struct intel_dp_mst_encoder *intel_mst = | |
3000 | enc_to_mst(&intel_encoder->base); | |
3001 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
3002 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3003 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
3004 | intel_connector->port); | |
3005 | ||
3006 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
3007 | } | |
3008 | ||
53f5e3ca JB |
3009 | static void intel_hdmi_info(struct seq_file *m, |
3010 | struct intel_connector *intel_connector) | |
3011 | { | |
3012 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
3013 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
3014 | ||
742f491d | 3015 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
3016 | } |
3017 | ||
3018 | static void intel_lvds_info(struct seq_file *m, | |
3019 | struct intel_connector *intel_connector) | |
3020 | { | |
3021 | intel_panel_info(m, &intel_connector->panel); | |
3022 | } | |
3023 | ||
3024 | static void intel_connector_info(struct seq_file *m, | |
3025 | struct drm_connector *connector) | |
3026 | { | |
3027 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3028 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3029 | struct drm_display_mode *mode; |
53f5e3ca JB |
3030 | |
3031 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3032 | connector->base.id, connector->name, |
53f5e3ca JB |
3033 | drm_get_connector_status_name(connector->status)); |
3034 | if (connector->status == connector_status_connected) { | |
3035 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3036 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3037 | connector->display_info.width_mm, | |
3038 | connector->display_info.height_mm); | |
3039 | seq_printf(m, "\tsubpixel order: %s\n", | |
3040 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3041 | seq_printf(m, "\tCEA rev: %d\n", | |
3042 | connector->display_info.cea_rev); | |
3043 | } | |
ee648a74 | 3044 | |
77d1f615 | 3045 | if (!intel_encoder) |
ee648a74 ML |
3046 | return; |
3047 | ||
3048 | switch (connector->connector_type) { | |
3049 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3050 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3051 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3052 | intel_dp_mst_info(m, intel_connector); | |
3053 | else | |
3054 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3055 | break; |
3056 | case DRM_MODE_CONNECTOR_LVDS: | |
3057 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3058 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3059 | break; |
3060 | case DRM_MODE_CONNECTOR_HDMIA: | |
3061 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3062 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3063 | intel_hdmi_info(m, intel_connector); | |
3064 | break; | |
3065 | default: | |
3066 | break; | |
36cd7444 | 3067 | } |
53f5e3ca | 3068 | |
f103fc7d JB |
3069 | seq_printf(m, "\tmodes:\n"); |
3070 | list_for_each_entry(mode, &connector->modes, head) | |
3071 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3072 | } |
3073 | ||
3abc4e09 RF |
3074 | static const char *plane_type(enum drm_plane_type type) |
3075 | { | |
3076 | switch (type) { | |
3077 | case DRM_PLANE_TYPE_OVERLAY: | |
3078 | return "OVL"; | |
3079 | case DRM_PLANE_TYPE_PRIMARY: | |
3080 | return "PRI"; | |
3081 | case DRM_PLANE_TYPE_CURSOR: | |
3082 | return "CUR"; | |
3083 | /* | |
3084 | * Deliberately omitting default: to generate compiler warnings | |
3085 | * when a new drm_plane_type gets added. | |
3086 | */ | |
3087 | } | |
3088 | ||
3089 | return "unknown"; | |
3090 | } | |
3091 | ||
3092 | static const char *plane_rotation(unsigned int rotation) | |
3093 | { | |
3094 | static char buf[48]; | |
3095 | /* | |
c2c446ad | 3096 | * According to doc only one DRM_MODE_ROTATE_ is allowed but this |
3abc4e09 RF |
3097 | * will print them all to visualize if the values are misused |
3098 | */ | |
3099 | snprintf(buf, sizeof(buf), | |
3100 | "%s%s%s%s%s%s(0x%08x)", | |
c2c446ad RF |
3101 | (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", |
3102 | (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", | |
3103 | (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", | |
3104 | (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", | |
3105 | (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", | |
3106 | (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3107 | rotation); |
3108 | ||
3109 | return buf; | |
3110 | } | |
3111 | ||
3112 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3113 | { | |
36cdd013 DW |
3114 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3115 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3116 | struct intel_plane *intel_plane; |
3117 | ||
3118 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3119 | struct drm_plane_state *state; | |
3120 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3121 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3122 | |
3123 | if (!plane->state) { | |
3124 | seq_puts(m, "plane->state is NULL!\n"); | |
3125 | continue; | |
3126 | } | |
3127 | ||
3128 | state = plane->state; | |
3129 | ||
90844f00 | 3130 | if (state->fb) { |
438b74a5 VS |
3131 | drm_get_format_name(state->fb->format->format, |
3132 | &format_name); | |
90844f00 | 3133 | } else { |
b3c11ac2 | 3134 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3135 | } |
3136 | ||
3abc4e09 RF |
3137 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3138 | plane->base.id, | |
3139 | plane_type(intel_plane->base.type), | |
3140 | state->crtc_x, state->crtc_y, | |
3141 | state->crtc_w, state->crtc_h, | |
3142 | (state->src_x >> 16), | |
3143 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3144 | (state->src_y >> 16), | |
3145 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3146 | (state->src_w >> 16), | |
3147 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3148 | (state->src_h >> 16), | |
3149 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3150 | format_name.str, |
3abc4e09 RF |
3151 | plane_rotation(state->rotation)); |
3152 | } | |
3153 | } | |
3154 | ||
3155 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3156 | { | |
3157 | struct intel_crtc_state *pipe_config; | |
3158 | int num_scalers = intel_crtc->num_scalers; | |
3159 | int i; | |
3160 | ||
3161 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3162 | ||
3163 | /* Not all platformas have a scaler */ | |
3164 | if (num_scalers) { | |
3165 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3166 | num_scalers, | |
3167 | pipe_config->scaler_state.scaler_users, | |
3168 | pipe_config->scaler_state.scaler_id); | |
3169 | ||
58415918 | 3170 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3171 | struct intel_scaler *sc = |
3172 | &pipe_config->scaler_state.scalers[i]; | |
3173 | ||
3174 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3175 | i, yesno(sc->in_use), sc->mode); | |
3176 | } | |
3177 | seq_puts(m, "\n"); | |
3178 | } else { | |
3179 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3180 | } | |
3181 | } | |
3182 | ||
53f5e3ca JB |
3183 | static int i915_display_info(struct seq_file *m, void *unused) |
3184 | { | |
36cdd013 DW |
3185 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3186 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3187 | struct intel_crtc *crtc; |
53f5e3ca | 3188 | struct drm_connector *connector; |
3f6a5e1e | 3189 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3190 | |
b0e5ddf3 | 3191 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3192 | seq_printf(m, "CRTC info\n"); |
3193 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3194 | for_each_intel_crtc(dev, crtc) { |
f77076c9 | 3195 | struct intel_crtc_state *pipe_config; |
53f5e3ca | 3196 | |
3f6a5e1e | 3197 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3198 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3199 | ||
3abc4e09 | 3200 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3201 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3202 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3203 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3204 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3205 | ||
f77076c9 | 3206 | if (pipe_config->base.active) { |
cd5dcbf1 VS |
3207 | struct intel_plane *cursor = |
3208 | to_intel_plane(crtc->base.cursor); | |
3209 | ||
065f2ec2 CW |
3210 | intel_crtc_info(m, crtc); |
3211 | ||
cd5dcbf1 VS |
3212 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", |
3213 | yesno(cursor->base.state->visible), | |
3214 | cursor->base.state->crtc_x, | |
3215 | cursor->base.state->crtc_y, | |
3216 | cursor->base.state->crtc_w, | |
3217 | cursor->base.state->crtc_h, | |
3218 | cursor->cursor.base); | |
3abc4e09 RF |
3219 | intel_scaler_info(m, crtc); |
3220 | intel_plane_info(m, crtc); | |
a23dc658 | 3221 | } |
cace841c DV |
3222 | |
3223 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3224 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3225 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3226 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3227 | } |
3228 | ||
3229 | seq_printf(m, "\n"); | |
3230 | seq_printf(m, "Connector info\n"); | |
3231 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3232 | mutex_lock(&dev->mode_config.mutex); |
3233 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3234 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3235 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3236 | drm_connector_list_iter_end(&conn_iter); |
3237 | mutex_unlock(&dev->mode_config.mutex); | |
3238 | ||
b0e5ddf3 | 3239 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3240 | |
3241 | return 0; | |
3242 | } | |
3243 | ||
1b36595f CW |
3244 | static int i915_engine_info(struct seq_file *m, void *unused) |
3245 | { | |
3246 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
061d06a2 | 3247 | struct i915_gpu_error *error = &dev_priv->gpu_error; |
1b36595f | 3248 | struct intel_engine_cs *engine; |
3b3f1650 | 3249 | enum intel_engine_id id; |
1b36595f | 3250 | |
9c870d03 CW |
3251 | intel_runtime_pm_get(dev_priv); |
3252 | ||
f73b5674 CW |
3253 | seq_printf(m, "GT awake? %s\n", |
3254 | yesno(dev_priv->gt.awake)); | |
3255 | seq_printf(m, "Global active requests: %d\n", | |
3256 | dev_priv->gt.active_requests); | |
3257 | ||
3b3f1650 | 3258 | for_each_engine(engine, dev_priv, id) { |
1b36595f CW |
3259 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
3260 | struct drm_i915_gem_request *rq; | |
3261 | struct rb_node *rb; | |
3262 | u64 addr; | |
3263 | ||
3264 | seq_printf(m, "%s\n", engine->name); | |
f73b5674 | 3265 | seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n", |
1b36595f | 3266 | intel_engine_get_seqno(engine), |
cb399eab | 3267 | intel_engine_last_submit(engine), |
1b36595f | 3268 | engine->hangcheck.seqno, |
f73b5674 CW |
3269 | jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), |
3270 | engine->timeline->inflight_seqnos); | |
061d06a2 MT |
3271 | seq_printf(m, "\tReset count: %d\n", |
3272 | i915_reset_engine_count(error, engine)); | |
1b36595f CW |
3273 | |
3274 | rcu_read_lock(); | |
3275 | ||
3276 | seq_printf(m, "\tRequests:\n"); | |
3277 | ||
73cb9701 CW |
3278 | rq = list_first_entry(&engine->timeline->requests, |
3279 | struct drm_i915_gem_request, link); | |
3280 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3281 | print_request(m, rq, "\t\tfirst "); |
3282 | ||
73cb9701 CW |
3283 | rq = list_last_entry(&engine->timeline->requests, |
3284 | struct drm_i915_gem_request, link); | |
3285 | if (&rq->link != &engine->timeline->requests) | |
1b36595f CW |
3286 | print_request(m, rq, "\t\tlast "); |
3287 | ||
3288 | rq = i915_gem_find_active_request(engine); | |
3289 | if (rq) { | |
3290 | print_request(m, rq, "\t\tactive "); | |
3291 | seq_printf(m, | |
3292 | "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", | |
3293 | rq->head, rq->postfix, rq->tail, | |
3294 | rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, | |
3295 | rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); | |
3296 | } | |
3297 | ||
3298 | seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", | |
3299 | I915_READ(RING_START(engine->mmio_base)), | |
3300 | rq ? i915_ggtt_offset(rq->ring->vma) : 0); | |
3301 | seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", | |
3302 | I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, | |
3303 | rq ? rq->ring->head : 0); | |
3304 | seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", | |
3305 | I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, | |
3306 | rq ? rq->ring->tail : 0); | |
3307 | seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", | |
3308 | I915_READ(RING_CTL(engine->mmio_base)), | |
3309 | I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); | |
3310 | ||
3311 | rcu_read_unlock(); | |
3312 | ||
3313 | addr = intel_engine_get_active_head(engine); | |
3314 | seq_printf(m, "\tACTHD: 0x%08x_%08x\n", | |
3315 | upper_32_bits(addr), lower_32_bits(addr)); | |
3316 | addr = intel_engine_get_last_batch_head(engine); | |
3317 | seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", | |
3318 | upper_32_bits(addr), lower_32_bits(addr)); | |
3319 | ||
3320 | if (i915.enable_execlists) { | |
3321 | u32 ptr, read, write; | |
77f0d0e9 | 3322 | unsigned int idx; |
1b36595f CW |
3323 | |
3324 | seq_printf(m, "\tExeclist status: 0x%08x %08x\n", | |
3325 | I915_READ(RING_EXECLIST_STATUS_LO(engine)), | |
3326 | I915_READ(RING_EXECLIST_STATUS_HI(engine))); | |
3327 | ||
3328 | ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); | |
3329 | read = GEN8_CSB_READ_PTR(ptr); | |
3330 | write = GEN8_CSB_WRITE_PTR(ptr); | |
4d73da93 CW |
3331 | seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n", |
3332 | read, write, | |
3333 | yesno(test_bit(ENGINE_IRQ_EXECLIST, | |
3334 | &engine->irq_posted))); | |
1b36595f CW |
3335 | if (read >= GEN8_CSB_ENTRIES) |
3336 | read = 0; | |
3337 | if (write >= GEN8_CSB_ENTRIES) | |
3338 | write = 0; | |
3339 | if (read > write) | |
3340 | write += GEN8_CSB_ENTRIES; | |
3341 | while (read < write) { | |
77f0d0e9 | 3342 | idx = ++read % GEN8_CSB_ENTRIES; |
1b36595f CW |
3343 | seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", |
3344 | idx, | |
3345 | I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), | |
3346 | I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); | |
3347 | } | |
3348 | ||
3349 | rcu_read_lock(); | |
77f0d0e9 CW |
3350 | for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); idx++) { |
3351 | unsigned int count; | |
3352 | ||
3353 | rq = port_unpack(&engine->execlist_port[idx], | |
3354 | &count); | |
3355 | if (rq) { | |
3356 | seq_printf(m, "\t\tELSP[%d] count=%d, ", | |
3357 | idx, count); | |
3358 | print_request(m, rq, "rq: "); | |
3359 | } else { | |
3360 | seq_printf(m, "\t\tELSP[%d] idle\n", | |
3361 | idx); | |
3362 | } | |
816ee798 | 3363 | } |
1b36595f | 3364 | rcu_read_unlock(); |
c8247c06 | 3365 | |
663f71e7 | 3366 | spin_lock_irq(&engine->timeline->lock); |
6c067579 CW |
3367 | for (rb = engine->execlist_first; rb; rb = rb_next(rb)){ |
3368 | struct i915_priolist *p = | |
3369 | rb_entry(rb, typeof(*p), node); | |
3370 | ||
3371 | list_for_each_entry(rq, &p->requests, | |
3372 | priotree.link) | |
3373 | print_request(m, rq, "\t\tQ "); | |
c8247c06 | 3374 | } |
663f71e7 | 3375 | spin_unlock_irq(&engine->timeline->lock); |
1b36595f CW |
3376 | } else if (INTEL_GEN(dev_priv) > 6) { |
3377 | seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", | |
3378 | I915_READ(RING_PP_DIR_BASE(engine))); | |
3379 | seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", | |
3380 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
3381 | seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", | |
3382 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3383 | } | |
3384 | ||
61d3dc70 | 3385 | spin_lock_irq(&b->rb_lock); |
1b36595f | 3386 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 3387 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
1b36595f CW |
3388 | |
3389 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
3390 | w->tsk->comm, w->tsk->pid, w->seqno); | |
3391 | } | |
61d3dc70 | 3392 | spin_unlock_irq(&b->rb_lock); |
1b36595f CW |
3393 | |
3394 | seq_puts(m, "\n"); | |
3395 | } | |
3396 | ||
9c870d03 CW |
3397 | intel_runtime_pm_put(dev_priv); |
3398 | ||
1b36595f CW |
3399 | return 0; |
3400 | } | |
3401 | ||
e04934cf BW |
3402 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3403 | { | |
36cdd013 DW |
3404 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3405 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3406 | struct intel_engine_cs *engine; |
36cdd013 | 3407 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3408 | enum intel_engine_id id; |
3409 | int j, ret; | |
e04934cf | 3410 | |
39df9190 | 3411 | if (!i915.semaphores) { |
e04934cf BW |
3412 | seq_puts(m, "Semaphores are disabled\n"); |
3413 | return 0; | |
3414 | } | |
3415 | ||
3416 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3417 | if (ret) | |
3418 | return ret; | |
03872064 | 3419 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3420 | |
36cdd013 | 3421 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3422 | struct page *page; |
3423 | uint64_t *seqno; | |
3424 | ||
51d545d0 | 3425 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3426 | |
3427 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3428 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3429 | uint64_t offset; |
3430 | ||
e2f80391 | 3431 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3432 | |
3433 | seq_puts(m, " Last signal:"); | |
3434 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3435 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3436 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3437 | seqno[offset], offset * 8); | |
3438 | } | |
3439 | seq_putc(m, '\n'); | |
3440 | ||
3441 | seq_puts(m, " Last wait: "); | |
3442 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3443 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3444 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3445 | seqno[offset], offset * 8); | |
3446 | } | |
3447 | seq_putc(m, '\n'); | |
3448 | ||
3449 | } | |
3450 | kunmap_atomic(seqno); | |
3451 | } else { | |
3452 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3453 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3454 | for (j = 0; j < num_rings; j++) |
3455 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3456 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3457 | seq_putc(m, '\n'); |
3458 | } | |
3459 | ||
03872064 | 3460 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3461 | mutex_unlock(&dev->struct_mutex); |
3462 | return 0; | |
3463 | } | |
3464 | ||
728e29d7 DV |
3465 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3466 | { | |
36cdd013 DW |
3467 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3468 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3469 | int i; |
3470 | ||
3471 | drm_modeset_lock_all(dev); | |
3472 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3473 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3474 | ||
3475 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3476 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3477 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3478 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3479 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3480 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3481 | pll->state.hw_state.dpll_md); |
3482 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3483 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3484 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3485 | } |
3486 | drm_modeset_unlock_all(dev); | |
3487 | ||
3488 | return 0; | |
3489 | } | |
3490 | ||
1ed1ef9d | 3491 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3492 | { |
3493 | int i; | |
3494 | int ret; | |
e2f80391 | 3495 | struct intel_engine_cs *engine; |
36cdd013 DW |
3496 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3497 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3498 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3499 | enum intel_engine_id id; |
888b5995 | 3500 | |
888b5995 AS |
3501 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3502 | if (ret) | |
3503 | return ret; | |
3504 | ||
3505 | intel_runtime_pm_get(dev_priv); | |
3506 | ||
33136b06 | 3507 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3508 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3509 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3510 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3511 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3512 | i915_reg_t addr; |
3513 | u32 mask, value, read; | |
2fa60f6d | 3514 | bool ok; |
888b5995 | 3515 | |
33136b06 AS |
3516 | addr = workarounds->reg[i].addr; |
3517 | mask = workarounds->reg[i].mask; | |
3518 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3519 | read = I915_READ(addr); |
3520 | ok = (value & mask) == (read & mask); | |
3521 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3522 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3523 | } |
3524 | ||
3525 | intel_runtime_pm_put(dev_priv); | |
3526 | mutex_unlock(&dev->struct_mutex); | |
3527 | ||
3528 | return 0; | |
3529 | } | |
3530 | ||
c5511e44 DL |
3531 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3532 | { | |
36cdd013 DW |
3533 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3534 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3535 | struct skl_ddb_allocation *ddb; |
3536 | struct skl_ddb_entry *entry; | |
3537 | enum pipe pipe; | |
3538 | int plane; | |
3539 | ||
36cdd013 | 3540 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3541 | return 0; |
3542 | ||
c5511e44 DL |
3543 | drm_modeset_lock_all(dev); |
3544 | ||
3545 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3546 | ||
3547 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3548 | ||
3549 | for_each_pipe(dev_priv, pipe) { | |
3550 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3551 | ||
8b364b41 | 3552 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3553 | entry = &ddb->plane[pipe][plane]; |
3554 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3555 | entry->start, entry->end, | |
3556 | skl_ddb_entry_size(entry)); | |
3557 | } | |
3558 | ||
4969d33e | 3559 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3560 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3561 | entry->end, skl_ddb_entry_size(entry)); | |
3562 | } | |
3563 | ||
3564 | drm_modeset_unlock_all(dev); | |
3565 | ||
3566 | return 0; | |
3567 | } | |
3568 | ||
a54746e3 | 3569 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3570 | struct drm_device *dev, |
3571 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3572 | { |
fac5e23e | 3573 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3574 | struct i915_drrs *drrs = &dev_priv->drrs; |
3575 | int vrefresh = 0; | |
26875fe5 | 3576 | struct drm_connector *connector; |
3f6a5e1e | 3577 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3578 | |
3f6a5e1e DV |
3579 | drm_connector_list_iter_begin(dev, &conn_iter); |
3580 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3581 | if (connector->state->crtc != &intel_crtc->base) |
3582 | continue; | |
3583 | ||
3584 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3585 | } |
3f6a5e1e | 3586 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3587 | |
3588 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3589 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3590 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3591 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3592 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3593 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3594 | else | |
3595 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3596 | ||
3597 | seq_puts(m, "\n\n"); | |
3598 | ||
f77076c9 | 3599 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3600 | struct intel_panel *panel; |
3601 | ||
3602 | mutex_lock(&drrs->mutex); | |
3603 | /* DRRS Supported */ | |
3604 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3605 | ||
3606 | /* disable_drrs() will make drrs->dp NULL */ | |
3607 | if (!drrs->dp) { | |
3608 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3609 | mutex_unlock(&drrs->mutex); | |
3610 | return; | |
3611 | } | |
3612 | ||
3613 | panel = &drrs->dp->attached_connector->panel; | |
3614 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3615 | drrs->busy_frontbuffer_bits); | |
3616 | ||
3617 | seq_puts(m, "\n\t\t"); | |
3618 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3619 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3620 | vrefresh = panel->fixed_mode->vrefresh; | |
3621 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3622 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3623 | vrefresh = panel->downclock_mode->vrefresh; | |
3624 | } else { | |
3625 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3626 | drrs->refresh_rate_type); | |
3627 | mutex_unlock(&drrs->mutex); | |
3628 | return; | |
3629 | } | |
3630 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3631 | ||
3632 | seq_puts(m, "\n\t\t"); | |
3633 | mutex_unlock(&drrs->mutex); | |
3634 | } else { | |
3635 | /* DRRS not supported. Print the VBT parameter*/ | |
3636 | seq_puts(m, "\tDRRS Supported : No"); | |
3637 | } | |
3638 | seq_puts(m, "\n"); | |
3639 | } | |
3640 | ||
3641 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3642 | { | |
36cdd013 DW |
3643 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3644 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3645 | struct intel_crtc *intel_crtc; |
3646 | int active_crtc_cnt = 0; | |
3647 | ||
26875fe5 | 3648 | drm_modeset_lock_all(dev); |
a54746e3 | 3649 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3650 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3651 | active_crtc_cnt++; |
3652 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3653 | ||
3654 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3655 | } | |
a54746e3 | 3656 | } |
26875fe5 | 3657 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3658 | |
3659 | if (!active_crtc_cnt) | |
3660 | seq_puts(m, "No active crtc found\n"); | |
3661 | ||
3662 | return 0; | |
3663 | } | |
3664 | ||
11bed958 DA |
3665 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3666 | { | |
36cdd013 DW |
3667 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3668 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3669 | struct intel_encoder *intel_encoder; |
3670 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3671 | struct drm_connector *connector; |
3f6a5e1e | 3672 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3673 | |
3f6a5e1e DV |
3674 | drm_connector_list_iter_begin(dev, &conn_iter); |
3675 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3676 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3677 | continue; |
b6dabe3b ML |
3678 | |
3679 | intel_encoder = intel_attached_encoder(connector); | |
3680 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3681 | continue; | |
3682 | ||
3683 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3684 | if (!intel_dig_port->dp.can_mst) |
3685 | continue; | |
b6dabe3b | 3686 | |
40ae80cc JB |
3687 | seq_printf(m, "MST Source Port %c\n", |
3688 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3689 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3690 | } | |
3f6a5e1e DV |
3691 | drm_connector_list_iter_end(&conn_iter); |
3692 | ||
11bed958 DA |
3693 | return 0; |
3694 | } | |
3695 | ||
eb3394fa | 3696 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3697 | const char __user *ubuf, |
3698 | size_t len, loff_t *offp) | |
eb3394fa TP |
3699 | { |
3700 | char *input_buffer; | |
3701 | int status = 0; | |
eb3394fa TP |
3702 | struct drm_device *dev; |
3703 | struct drm_connector *connector; | |
3f6a5e1e | 3704 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3705 | struct intel_dp *intel_dp; |
3706 | int val = 0; | |
3707 | ||
9aaffa34 | 3708 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3709 | |
eb3394fa TP |
3710 | if (len == 0) |
3711 | return 0; | |
3712 | ||
261aeba8 GT |
3713 | input_buffer = memdup_user_nul(ubuf, len); |
3714 | if (IS_ERR(input_buffer)) | |
3715 | return PTR_ERR(input_buffer); | |
eb3394fa | 3716 | |
eb3394fa TP |
3717 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3718 | ||
3f6a5e1e DV |
3719 | drm_connector_list_iter_begin(dev, &conn_iter); |
3720 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3721 | struct intel_encoder *encoder; |
3722 | ||
eb3394fa TP |
3723 | if (connector->connector_type != |
3724 | DRM_MODE_CONNECTOR_DisplayPort) | |
3725 | continue; | |
3726 | ||
a874b6a3 ML |
3727 | encoder = to_intel_encoder(connector->encoder); |
3728 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3729 | continue; | |
3730 | ||
3731 | if (encoder && connector->status == connector_status_connected) { | |
3732 | intel_dp = enc_to_intel_dp(&encoder->base); | |
eb3394fa TP |
3733 | status = kstrtoint(input_buffer, 10, &val); |
3734 | if (status < 0) | |
3f6a5e1e | 3735 | break; |
eb3394fa TP |
3736 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3737 | /* To prevent erroneous activation of the compliance | |
3738 | * testing code, only accept an actual value of 1 here | |
3739 | */ | |
3740 | if (val == 1) | |
c1617abc | 3741 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3742 | else |
c1617abc | 3743 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3744 | } |
3745 | } | |
3f6a5e1e | 3746 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3747 | kfree(input_buffer); |
3748 | if (status < 0) | |
3749 | return status; | |
3750 | ||
3751 | *offp += len; | |
3752 | return len; | |
3753 | } | |
3754 | ||
3755 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3756 | { | |
3757 | struct drm_device *dev = m->private; | |
3758 | struct drm_connector *connector; | |
3f6a5e1e | 3759 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3760 | struct intel_dp *intel_dp; |
3761 | ||
3f6a5e1e DV |
3762 | drm_connector_list_iter_begin(dev, &conn_iter); |
3763 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3764 | struct intel_encoder *encoder; |
3765 | ||
eb3394fa TP |
3766 | if (connector->connector_type != |
3767 | DRM_MODE_CONNECTOR_DisplayPort) | |
3768 | continue; | |
3769 | ||
a874b6a3 ML |
3770 | encoder = to_intel_encoder(connector->encoder); |
3771 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3772 | continue; | |
3773 | ||
3774 | if (encoder && connector->status == connector_status_connected) { | |
3775 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3776 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3777 | seq_puts(m, "1"); |
3778 | else | |
3779 | seq_puts(m, "0"); | |
3780 | } else | |
3781 | seq_puts(m, "0"); | |
3782 | } | |
3f6a5e1e | 3783 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3784 | |
3785 | return 0; | |
3786 | } | |
3787 | ||
3788 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3789 | struct file *file) |
eb3394fa | 3790 | { |
36cdd013 | 3791 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3792 | |
36cdd013 DW |
3793 | return single_open(file, i915_displayport_test_active_show, |
3794 | &dev_priv->drm); | |
eb3394fa TP |
3795 | } |
3796 | ||
3797 | static const struct file_operations i915_displayport_test_active_fops = { | |
3798 | .owner = THIS_MODULE, | |
3799 | .open = i915_displayport_test_active_open, | |
3800 | .read = seq_read, | |
3801 | .llseek = seq_lseek, | |
3802 | .release = single_release, | |
3803 | .write = i915_displayport_test_active_write | |
3804 | }; | |
3805 | ||
3806 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3807 | { | |
3808 | struct drm_device *dev = m->private; | |
3809 | struct drm_connector *connector; | |
3f6a5e1e | 3810 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3811 | struct intel_dp *intel_dp; |
3812 | ||
3f6a5e1e DV |
3813 | drm_connector_list_iter_begin(dev, &conn_iter); |
3814 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3815 | struct intel_encoder *encoder; |
3816 | ||
eb3394fa TP |
3817 | if (connector->connector_type != |
3818 | DRM_MODE_CONNECTOR_DisplayPort) | |
3819 | continue; | |
3820 | ||
a874b6a3 ML |
3821 | encoder = to_intel_encoder(connector->encoder); |
3822 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3823 | continue; | |
3824 | ||
3825 | if (encoder && connector->status == connector_status_connected) { | |
3826 | intel_dp = enc_to_intel_dp(&encoder->base); | |
b48a5ba9 MN |
3827 | if (intel_dp->compliance.test_type == |
3828 | DP_TEST_LINK_EDID_READ) | |
3829 | seq_printf(m, "%lx", | |
3830 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3831 | else if (intel_dp->compliance.test_type == |
3832 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3833 | seq_printf(m, "hdisplay: %d\n", | |
3834 | intel_dp->compliance.test_data.hdisplay); | |
3835 | seq_printf(m, "vdisplay: %d\n", | |
3836 | intel_dp->compliance.test_data.vdisplay); | |
3837 | seq_printf(m, "bpc: %u\n", | |
3838 | intel_dp->compliance.test_data.bpc); | |
3839 | } | |
eb3394fa TP |
3840 | } else |
3841 | seq_puts(m, "0"); | |
3842 | } | |
3f6a5e1e | 3843 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3844 | |
3845 | return 0; | |
3846 | } | |
3847 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3848 | struct file *file) |
eb3394fa | 3849 | { |
36cdd013 | 3850 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3851 | |
36cdd013 DW |
3852 | return single_open(file, i915_displayport_test_data_show, |
3853 | &dev_priv->drm); | |
eb3394fa TP |
3854 | } |
3855 | ||
3856 | static const struct file_operations i915_displayport_test_data_fops = { | |
3857 | .owner = THIS_MODULE, | |
3858 | .open = i915_displayport_test_data_open, | |
3859 | .read = seq_read, | |
3860 | .llseek = seq_lseek, | |
3861 | .release = single_release | |
3862 | }; | |
3863 | ||
3864 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3865 | { | |
3866 | struct drm_device *dev = m->private; | |
3867 | struct drm_connector *connector; | |
3f6a5e1e | 3868 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3869 | struct intel_dp *intel_dp; |
3870 | ||
3f6a5e1e DV |
3871 | drm_connector_list_iter_begin(dev, &conn_iter); |
3872 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3873 | struct intel_encoder *encoder; |
3874 | ||
eb3394fa TP |
3875 | if (connector->connector_type != |
3876 | DRM_MODE_CONNECTOR_DisplayPort) | |
3877 | continue; | |
3878 | ||
a874b6a3 ML |
3879 | encoder = to_intel_encoder(connector->encoder); |
3880 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3881 | continue; | |
3882 | ||
3883 | if (encoder && connector->status == connector_status_connected) { | |
3884 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3885 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3886 | } else |
3887 | seq_puts(m, "0"); | |
3888 | } | |
3f6a5e1e | 3889 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3890 | |
3891 | return 0; | |
3892 | } | |
3893 | ||
3894 | static int i915_displayport_test_type_open(struct inode *inode, | |
3895 | struct file *file) | |
3896 | { | |
36cdd013 | 3897 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3898 | |
36cdd013 DW |
3899 | return single_open(file, i915_displayport_test_type_show, |
3900 | &dev_priv->drm); | |
eb3394fa TP |
3901 | } |
3902 | ||
3903 | static const struct file_operations i915_displayport_test_type_fops = { | |
3904 | .owner = THIS_MODULE, | |
3905 | .open = i915_displayport_test_type_open, | |
3906 | .read = seq_read, | |
3907 | .llseek = seq_lseek, | |
3908 | .release = single_release | |
3909 | }; | |
3910 | ||
97e94b22 | 3911 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3912 | { |
36cdd013 DW |
3913 | struct drm_i915_private *dev_priv = m->private; |
3914 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3915 | int level; |
de38b95c VS |
3916 | int num_levels; |
3917 | ||
36cdd013 | 3918 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3919 | num_levels = 3; |
36cdd013 | 3920 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3921 | num_levels = 1; |
04548cba VS |
3922 | else if (IS_G4X(dev_priv)) |
3923 | num_levels = 3; | |
de38b95c | 3924 | else |
5db94019 | 3925 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3926 | |
3927 | drm_modeset_lock_all(dev); | |
3928 | ||
3929 | for (level = 0; level < num_levels; level++) { | |
3930 | unsigned int latency = wm[level]; | |
3931 | ||
97e94b22 DL |
3932 | /* |
3933 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3934 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3935 | */ |
04548cba VS |
3936 | if (INTEL_GEN(dev_priv) >= 9 || |
3937 | IS_VALLEYVIEW(dev_priv) || | |
3938 | IS_CHERRYVIEW(dev_priv) || | |
3939 | IS_G4X(dev_priv)) | |
97e94b22 DL |
3940 | latency *= 10; |
3941 | else if (level > 0) | |
369a1342 VS |
3942 | latency *= 5; |
3943 | ||
3944 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3945 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3946 | } |
3947 | ||
3948 | drm_modeset_unlock_all(dev); | |
3949 | } | |
3950 | ||
3951 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3952 | { | |
36cdd013 | 3953 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3954 | const uint16_t *latencies; |
3955 | ||
36cdd013 | 3956 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3957 | latencies = dev_priv->wm.skl_latency; |
3958 | else | |
36cdd013 | 3959 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3960 | |
97e94b22 | 3961 | wm_latency_show(m, latencies); |
369a1342 VS |
3962 | |
3963 | return 0; | |
3964 | } | |
3965 | ||
3966 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3967 | { | |
36cdd013 | 3968 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3969 | const uint16_t *latencies; |
3970 | ||
36cdd013 | 3971 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3972 | latencies = dev_priv->wm.skl_latency; |
3973 | else | |
36cdd013 | 3974 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3975 | |
97e94b22 | 3976 | wm_latency_show(m, latencies); |
369a1342 VS |
3977 | |
3978 | return 0; | |
3979 | } | |
3980 | ||
3981 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3982 | { | |
36cdd013 | 3983 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3984 | const uint16_t *latencies; |
3985 | ||
36cdd013 | 3986 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3987 | latencies = dev_priv->wm.skl_latency; |
3988 | else | |
36cdd013 | 3989 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3990 | |
97e94b22 | 3991 | wm_latency_show(m, latencies); |
369a1342 VS |
3992 | |
3993 | return 0; | |
3994 | } | |
3995 | ||
3996 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3997 | { | |
36cdd013 | 3998 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3999 | |
04548cba | 4000 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
369a1342 VS |
4001 | return -ENODEV; |
4002 | ||
36cdd013 | 4003 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
4004 | } |
4005 | ||
4006 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4007 | { | |
36cdd013 | 4008 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4009 | |
36cdd013 | 4010 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4011 | return -ENODEV; |
4012 | ||
36cdd013 | 4013 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
4014 | } |
4015 | ||
4016 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4017 | { | |
36cdd013 | 4018 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 4019 | |
36cdd013 | 4020 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
4021 | return -ENODEV; |
4022 | ||
36cdd013 | 4023 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
4024 | } |
4025 | ||
4026 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4027 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4028 | { |
4029 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
4030 | struct drm_i915_private *dev_priv = m->private; |
4031 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 4032 | uint16_t new[8] = { 0 }; |
de38b95c | 4033 | int num_levels; |
369a1342 VS |
4034 | int level; |
4035 | int ret; | |
4036 | char tmp[32]; | |
4037 | ||
36cdd013 | 4038 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4039 | num_levels = 3; |
36cdd013 | 4040 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 4041 | num_levels = 1; |
04548cba VS |
4042 | else if (IS_G4X(dev_priv)) |
4043 | num_levels = 3; | |
de38b95c | 4044 | else |
5db94019 | 4045 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4046 | |
369a1342 VS |
4047 | if (len >= sizeof(tmp)) |
4048 | return -EINVAL; | |
4049 | ||
4050 | if (copy_from_user(tmp, ubuf, len)) | |
4051 | return -EFAULT; | |
4052 | ||
4053 | tmp[len] = '\0'; | |
4054 | ||
97e94b22 DL |
4055 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4056 | &new[0], &new[1], &new[2], &new[3], | |
4057 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4058 | if (ret != num_levels) |
4059 | return -EINVAL; | |
4060 | ||
4061 | drm_modeset_lock_all(dev); | |
4062 | ||
4063 | for (level = 0; level < num_levels; level++) | |
4064 | wm[level] = new[level]; | |
4065 | ||
4066 | drm_modeset_unlock_all(dev); | |
4067 | ||
4068 | return len; | |
4069 | } | |
4070 | ||
4071 | ||
4072 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4073 | size_t len, loff_t *offp) | |
4074 | { | |
4075 | struct seq_file *m = file->private_data; | |
36cdd013 | 4076 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4077 | uint16_t *latencies; |
369a1342 | 4078 | |
36cdd013 | 4079 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4080 | latencies = dev_priv->wm.skl_latency; |
4081 | else | |
36cdd013 | 4082 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4083 | |
4084 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4085 | } |
4086 | ||
4087 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4088 | size_t len, loff_t *offp) | |
4089 | { | |
4090 | struct seq_file *m = file->private_data; | |
36cdd013 | 4091 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4092 | uint16_t *latencies; |
369a1342 | 4093 | |
36cdd013 | 4094 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4095 | latencies = dev_priv->wm.skl_latency; |
4096 | else | |
36cdd013 | 4097 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4098 | |
4099 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4100 | } |
4101 | ||
4102 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4103 | size_t len, loff_t *offp) | |
4104 | { | |
4105 | struct seq_file *m = file->private_data; | |
36cdd013 | 4106 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4107 | uint16_t *latencies; |
4108 | ||
36cdd013 | 4109 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4110 | latencies = dev_priv->wm.skl_latency; |
4111 | else | |
36cdd013 | 4112 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4113 | |
97e94b22 | 4114 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4115 | } |
4116 | ||
4117 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4118 | .owner = THIS_MODULE, | |
4119 | .open = pri_wm_latency_open, | |
4120 | .read = seq_read, | |
4121 | .llseek = seq_lseek, | |
4122 | .release = single_release, | |
4123 | .write = pri_wm_latency_write | |
4124 | }; | |
4125 | ||
4126 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4127 | .owner = THIS_MODULE, | |
4128 | .open = spr_wm_latency_open, | |
4129 | .read = seq_read, | |
4130 | .llseek = seq_lseek, | |
4131 | .release = single_release, | |
4132 | .write = spr_wm_latency_write | |
4133 | }; | |
4134 | ||
4135 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4136 | .owner = THIS_MODULE, | |
4137 | .open = cur_wm_latency_open, | |
4138 | .read = seq_read, | |
4139 | .llseek = seq_lseek, | |
4140 | .release = single_release, | |
4141 | .write = cur_wm_latency_write | |
4142 | }; | |
4143 | ||
647416f9 KC |
4144 | static int |
4145 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4146 | { |
36cdd013 | 4147 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4148 | |
d98c52cf | 4149 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4150 | |
647416f9 | 4151 | return 0; |
f3cd474b CW |
4152 | } |
4153 | ||
647416f9 KC |
4154 | static int |
4155 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4156 | { |
598b6b5a CW |
4157 | struct drm_i915_private *i915 = data; |
4158 | struct intel_engine_cs *engine; | |
4159 | unsigned int tmp; | |
d46c0517 | 4160 | |
b8d24a06 MK |
4161 | /* |
4162 | * There is no safeguard against this debugfs entry colliding | |
4163 | * with the hangcheck calling same i915_handle_error() in | |
4164 | * parallel, causing an explosion. For now we assume that the | |
4165 | * test harness is responsible enough not to inject gpu hangs | |
4166 | * while it is writing to 'i915_wedged' | |
4167 | */ | |
4168 | ||
598b6b5a | 4169 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
4170 | return -EAGAIN; |
4171 | ||
598b6b5a CW |
4172 | for_each_engine_masked(engine, i915, val, tmp) { |
4173 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
4174 | engine->hangcheck.stalled = true; | |
4175 | } | |
4176 | ||
4177 | i915_handle_error(i915, val, "Manually setting wedged to %llu", val); | |
d46c0517 | 4178 | |
598b6b5a | 4179 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
4180 | I915_RESET_HANDOFF, |
4181 | TASK_UNINTERRUPTIBLE); | |
4182 | ||
647416f9 | 4183 | return 0; |
f3cd474b CW |
4184 | } |
4185 | ||
647416f9 KC |
4186 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4187 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4188 | "%llu\n"); |
f3cd474b | 4189 | |
64486ae7 CW |
4190 | static int |
4191 | fault_irq_set(struct drm_i915_private *i915, | |
4192 | unsigned long *irq, | |
4193 | unsigned long val) | |
4194 | { | |
4195 | int err; | |
4196 | ||
4197 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4198 | if (err) | |
4199 | return err; | |
4200 | ||
4201 | err = i915_gem_wait_for_idle(i915, | |
4202 | I915_WAIT_LOCKED | | |
4203 | I915_WAIT_INTERRUPTIBLE); | |
4204 | if (err) | |
4205 | goto err_unlock; | |
4206 | ||
64486ae7 CW |
4207 | *irq = val; |
4208 | mutex_unlock(&i915->drm.struct_mutex); | |
4209 | ||
4210 | /* Flush idle worker to disarm irq */ | |
4211 | while (flush_delayed_work(&i915->gt.idle_work)) | |
4212 | ; | |
4213 | ||
4214 | return 0; | |
4215 | ||
4216 | err_unlock: | |
4217 | mutex_unlock(&i915->drm.struct_mutex); | |
4218 | return err; | |
4219 | } | |
4220 | ||
094f9a54 CW |
4221 | static int |
4222 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4223 | { | |
36cdd013 | 4224 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4225 | |
4226 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4227 | return 0; | |
4228 | } | |
4229 | ||
4230 | static int | |
4231 | i915_ring_missed_irq_set(void *data, u64 val) | |
4232 | { | |
64486ae7 | 4233 | struct drm_i915_private *i915 = data; |
094f9a54 | 4234 | |
64486ae7 | 4235 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4236 | } |
4237 | ||
4238 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4239 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4240 | "0x%08llx\n"); | |
4241 | ||
4242 | static int | |
4243 | i915_ring_test_irq_get(void *data, u64 *val) | |
4244 | { | |
36cdd013 | 4245 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4246 | |
4247 | *val = dev_priv->gpu_error.test_irq_rings; | |
4248 | ||
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | static int | |
4253 | i915_ring_test_irq_set(void *data, u64 val) | |
4254 | { | |
64486ae7 | 4255 | struct drm_i915_private *i915 = data; |
094f9a54 | 4256 | |
64486ae7 | 4257 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4258 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4259 | |
64486ae7 | 4260 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4261 | } |
4262 | ||
4263 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4264 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4265 | "0x%08llx\n"); | |
4266 | ||
dd624afd CW |
4267 | #define DROP_UNBOUND 0x1 |
4268 | #define DROP_BOUND 0x2 | |
4269 | #define DROP_RETIRE 0x4 | |
4270 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 | 4271 | #define DROP_FREED 0x10 |
8eadc19b | 4272 | #define DROP_SHRINK_ALL 0x20 |
fbbd37b3 CW |
4273 | #define DROP_ALL (DROP_UNBOUND | \ |
4274 | DROP_BOUND | \ | |
4275 | DROP_RETIRE | \ | |
4276 | DROP_ACTIVE | \ | |
8eadc19b CW |
4277 | DROP_FREED | \ |
4278 | DROP_SHRINK_ALL) | |
647416f9 KC |
4279 | static int |
4280 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4281 | { |
647416f9 | 4282 | *val = DROP_ALL; |
dd624afd | 4283 | |
647416f9 | 4284 | return 0; |
dd624afd CW |
4285 | } |
4286 | ||
647416f9 KC |
4287 | static int |
4288 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4289 | { |
36cdd013 DW |
4290 | struct drm_i915_private *dev_priv = data; |
4291 | struct drm_device *dev = &dev_priv->drm; | |
00c26cf9 | 4292 | int ret = 0; |
dd624afd | 4293 | |
2f9fe5ff | 4294 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4295 | |
4296 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4297 | * on ioctls on -EAGAIN. */ | |
00c26cf9 CW |
4298 | if (val & (DROP_ACTIVE | DROP_RETIRE)) { |
4299 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
dd624afd | 4300 | if (ret) |
00c26cf9 | 4301 | return ret; |
dd624afd | 4302 | |
00c26cf9 CW |
4303 | if (val & DROP_ACTIVE) |
4304 | ret = i915_gem_wait_for_idle(dev_priv, | |
4305 | I915_WAIT_INTERRUPTIBLE | | |
4306 | I915_WAIT_LOCKED); | |
4307 | ||
4308 | if (val & DROP_RETIRE) | |
4309 | i915_gem_retire_requests(dev_priv); | |
4310 | ||
4311 | mutex_unlock(&dev->struct_mutex); | |
4312 | } | |
dd624afd | 4313 | |
05df49e7 | 4314 | lockdep_set_current_reclaim_state(GFP_KERNEL); |
21ab4e74 CW |
4315 | if (val & DROP_BOUND) |
4316 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4317 | |
21ab4e74 CW |
4318 | if (val & DROP_UNBOUND) |
4319 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd | 4320 | |
8eadc19b CW |
4321 | if (val & DROP_SHRINK_ALL) |
4322 | i915_gem_shrink_all(dev_priv); | |
05df49e7 | 4323 | lockdep_clear_current_reclaim_state(); |
8eadc19b | 4324 | |
fbbd37b3 CW |
4325 | if (val & DROP_FREED) { |
4326 | synchronize_rcu(); | |
bdeb9785 | 4327 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4328 | } |
4329 | ||
647416f9 | 4330 | return ret; |
dd624afd CW |
4331 | } |
4332 | ||
647416f9 KC |
4333 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4334 | i915_drop_caches_get, i915_drop_caches_set, | |
4335 | "0x%08llx\n"); | |
dd624afd | 4336 | |
647416f9 KC |
4337 | static int |
4338 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4339 | { |
36cdd013 | 4340 | struct drm_i915_private *dev_priv = data; |
004777cb | 4341 | |
36cdd013 | 4342 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4343 | return -ENODEV; |
4344 | ||
7c59a9c1 | 4345 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4346 | return 0; |
358733e9 JB |
4347 | } |
4348 | ||
647416f9 KC |
4349 | static int |
4350 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4351 | { |
36cdd013 | 4352 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4353 | u32 hw_max, hw_min; |
647416f9 | 4354 | int ret; |
004777cb | 4355 | |
36cdd013 | 4356 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4357 | return -ENODEV; |
358733e9 | 4358 | |
647416f9 | 4359 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4360 | |
4fc688ce | 4361 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4362 | if (ret) |
4363 | return ret; | |
4364 | ||
358733e9 JB |
4365 | /* |
4366 | * Turbo will still be enabled, but won't go above the set value. | |
4367 | */ | |
bc4d91f6 | 4368 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4369 | |
bc4d91f6 AG |
4370 | hw_max = dev_priv->rps.max_freq; |
4371 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4372 | |
b39fb297 | 4373 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4374 | mutex_unlock(&dev_priv->rps.hw_lock); |
4375 | return -EINVAL; | |
0a073b84 JB |
4376 | } |
4377 | ||
b39fb297 | 4378 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4379 | |
9fcee2f7 CW |
4380 | if (intel_set_rps(dev_priv, val)) |
4381 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4382 | |
4fc688ce | 4383 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4384 | |
647416f9 | 4385 | return 0; |
358733e9 JB |
4386 | } |
4387 | ||
647416f9 KC |
4388 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4389 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4390 | "%llu\n"); |
358733e9 | 4391 | |
647416f9 KC |
4392 | static int |
4393 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4394 | { |
36cdd013 | 4395 | struct drm_i915_private *dev_priv = data; |
004777cb | 4396 | |
62e1baa1 | 4397 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4398 | return -ENODEV; |
4399 | ||
7c59a9c1 | 4400 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4401 | return 0; |
1523c310 JB |
4402 | } |
4403 | ||
647416f9 KC |
4404 | static int |
4405 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4406 | { |
36cdd013 | 4407 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4408 | u32 hw_max, hw_min; |
647416f9 | 4409 | int ret; |
004777cb | 4410 | |
62e1baa1 | 4411 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4412 | return -ENODEV; |
1523c310 | 4413 | |
647416f9 | 4414 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4415 | |
4fc688ce | 4416 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4417 | if (ret) |
4418 | return ret; | |
4419 | ||
1523c310 JB |
4420 | /* |
4421 | * Turbo will still be enabled, but won't go below the set value. | |
4422 | */ | |
bc4d91f6 | 4423 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4424 | |
bc4d91f6 AG |
4425 | hw_max = dev_priv->rps.max_freq; |
4426 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4427 | |
36cdd013 DW |
4428 | if (val < hw_min || |
4429 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4430 | mutex_unlock(&dev_priv->rps.hw_lock); |
4431 | return -EINVAL; | |
0a073b84 | 4432 | } |
dd0a1aa1 | 4433 | |
b39fb297 | 4434 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4435 | |
9fcee2f7 CW |
4436 | if (intel_set_rps(dev_priv, val)) |
4437 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4438 | |
4fc688ce | 4439 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4440 | |
647416f9 | 4441 | return 0; |
1523c310 JB |
4442 | } |
4443 | ||
647416f9 KC |
4444 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4445 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4446 | "%llu\n"); |
1523c310 | 4447 | |
647416f9 KC |
4448 | static int |
4449 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4450 | { |
36cdd013 | 4451 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4452 | u32 snpcr; |
07b7ddd9 | 4453 | |
36cdd013 | 4454 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4455 | return -ENODEV; |
4456 | ||
c8c8fb33 | 4457 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4458 | |
07b7ddd9 | 4459 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4460 | |
4461 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4462 | |
647416f9 | 4463 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4464 | |
647416f9 | 4465 | return 0; |
07b7ddd9 JB |
4466 | } |
4467 | ||
647416f9 KC |
4468 | static int |
4469 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4470 | { |
36cdd013 | 4471 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4472 | u32 snpcr; |
07b7ddd9 | 4473 | |
36cdd013 | 4474 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4475 | return -ENODEV; |
4476 | ||
647416f9 | 4477 | if (val > 3) |
07b7ddd9 JB |
4478 | return -EINVAL; |
4479 | ||
c8c8fb33 | 4480 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4481 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4482 | |
4483 | /* Update the cache sharing policy here as well */ | |
4484 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4485 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4486 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4487 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4488 | ||
c8c8fb33 | 4489 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4490 | return 0; |
07b7ddd9 JB |
4491 | } |
4492 | ||
647416f9 KC |
4493 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4494 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4495 | "%llu\n"); | |
07b7ddd9 | 4496 | |
36cdd013 | 4497 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4498 | struct sseu_dev_info *sseu) |
5d39525a | 4499 | { |
0a0b457f | 4500 | int ss_max = 2; |
5d39525a JM |
4501 | int ss; |
4502 | u32 sig1[ss_max], sig2[ss_max]; | |
4503 | ||
4504 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4505 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4506 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4507 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4508 | ||
4509 | for (ss = 0; ss < ss_max; ss++) { | |
4510 | unsigned int eu_cnt; | |
4511 | ||
4512 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4513 | /* skip disabled subslice */ | |
4514 | continue; | |
4515 | ||
f08a0c92 | 4516 | sseu->slice_mask = BIT(0); |
57ec171e | 4517 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4518 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4519 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4520 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4521 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4522 | sseu->eu_total += eu_cnt; |
4523 | sseu->eu_per_subslice = max_t(unsigned int, | |
4524 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4525 | } |
5d39525a JM |
4526 | } |
4527 | ||
36cdd013 | 4528 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4529 | struct sseu_dev_info *sseu) |
5d39525a | 4530 | { |
1c046bc1 | 4531 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4532 | int s, ss; |
4533 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4534 | ||
1c046bc1 | 4535 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4536 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4537 | s_max = 1; |
4538 | ss_max = 3; | |
4539 | } | |
4540 | ||
4541 | for (s = 0; s < s_max; s++) { | |
4542 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4543 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4544 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4545 | } | |
4546 | ||
5d39525a JM |
4547 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4548 | GEN9_PGCTL_SSA_EU19_ACK | | |
4549 | GEN9_PGCTL_SSA_EU210_ACK | | |
4550 | GEN9_PGCTL_SSA_EU311_ACK; | |
4551 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4552 | GEN9_PGCTL_SSB_EU19_ACK | | |
4553 | GEN9_PGCTL_SSB_EU210_ACK | | |
4554 | GEN9_PGCTL_SSB_EU311_ACK; | |
4555 | ||
4556 | for (s = 0; s < s_max; s++) { | |
4557 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4558 | /* skip disabled slice */ | |
4559 | continue; | |
4560 | ||
f08a0c92 | 4561 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4562 | |
7ea1adf3 | 4563 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) |
57ec171e ID |
4564 | sseu->subslice_mask = |
4565 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4566 | |
5d39525a JM |
4567 | for (ss = 0; ss < ss_max; ss++) { |
4568 | unsigned int eu_cnt; | |
4569 | ||
cc3f90f0 | 4570 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4571 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4572 | /* skip disabled subslice */ | |
4573 | continue; | |
1c046bc1 | 4574 | |
57ec171e ID |
4575 | sseu->subslice_mask |= BIT(ss); |
4576 | } | |
1c046bc1 | 4577 | |
5d39525a JM |
4578 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4579 | eu_mask[ss%2]); | |
915490d5 ID |
4580 | sseu->eu_total += eu_cnt; |
4581 | sseu->eu_per_subslice = max_t(unsigned int, | |
4582 | sseu->eu_per_subslice, | |
4583 | eu_cnt); | |
5d39525a JM |
4584 | } |
4585 | } | |
4586 | } | |
4587 | ||
36cdd013 | 4588 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4589 | struct sseu_dev_info *sseu) |
91bedd34 | 4590 | { |
91bedd34 | 4591 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4592 | int s; |
91bedd34 | 4593 | |
f08a0c92 | 4594 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4595 | |
f08a0c92 | 4596 | if (sseu->slice_mask) { |
57ec171e | 4597 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4598 | sseu->eu_per_subslice = |
4599 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4600 | sseu->eu_total = sseu->eu_per_subslice * |
4601 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4602 | |
4603 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4604 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4605 | u8 subslice_7eu = |
4606 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4607 | |
915490d5 | 4608 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4609 | } |
4610 | } | |
4611 | } | |
4612 | ||
615d8908 ID |
4613 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4614 | const struct sseu_dev_info *sseu) | |
4615 | { | |
4616 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4617 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4618 | ||
c67ba538 ID |
4619 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4620 | sseu->slice_mask); | |
615d8908 | 4621 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4622 | hweight8(sseu->slice_mask)); |
615d8908 | 4623 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4624 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4625 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4626 | sseu->subslice_mask); | |
615d8908 | 4627 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4628 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4629 | seq_printf(m, " %s EU Total: %u\n", type, |
4630 | sseu->eu_total); | |
4631 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4632 | sseu->eu_per_subslice); | |
4633 | ||
4634 | if (!is_available_info) | |
4635 | return; | |
4636 | ||
4637 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4638 | if (HAS_POOLED_EU(dev_priv)) | |
4639 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4640 | ||
4641 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4642 | yesno(sseu->has_slice_pg)); | |
4643 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4644 | yesno(sseu->has_subslice_pg)); | |
4645 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4646 | yesno(sseu->has_eu_pg)); | |
4647 | } | |
4648 | ||
3873218f JM |
4649 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4650 | { | |
36cdd013 | 4651 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4652 | struct sseu_dev_info sseu; |
3873218f | 4653 | |
36cdd013 | 4654 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4655 | return -ENODEV; |
4656 | ||
4657 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4658 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4659 | |
7f992aba | 4660 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4661 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4662 | |
4663 | intel_runtime_pm_get(dev_priv); | |
4664 | ||
36cdd013 | 4665 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4666 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4667 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4668 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4669 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4670 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4671 | } |
238010ed DW |
4672 | |
4673 | intel_runtime_pm_put(dev_priv); | |
4674 | ||
615d8908 | 4675 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4676 | |
3873218f JM |
4677 | return 0; |
4678 | } | |
4679 | ||
6d794d42 BW |
4680 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4681 | { | |
36cdd013 | 4682 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4683 | |
36cdd013 | 4684 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4685 | return 0; |
4686 | ||
6daccb0b | 4687 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4688 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4689 | |
4690 | return 0; | |
4691 | } | |
4692 | ||
c43b5634 | 4693 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4694 | { |
36cdd013 | 4695 | struct drm_i915_private *dev_priv = inode->i_private; |
6d794d42 | 4696 | |
36cdd013 | 4697 | if (INTEL_GEN(dev_priv) < 6) |
6d794d42 BW |
4698 | return 0; |
4699 | ||
59bad947 | 4700 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4701 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4702 | |
4703 | return 0; | |
4704 | } | |
4705 | ||
4706 | static const struct file_operations i915_forcewake_fops = { | |
4707 | .owner = THIS_MODULE, | |
4708 | .open = i915_forcewake_open, | |
4709 | .release = i915_forcewake_release, | |
4710 | }; | |
4711 | ||
317eaa95 L |
4712 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4713 | { | |
4714 | struct drm_i915_private *dev_priv = m->private; | |
4715 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4716 | ||
4717 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4718 | seq_printf(m, "Detected: %s\n", | |
4719 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4720 | ||
4721 | return 0; | |
4722 | } | |
4723 | ||
4724 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4725 | const char __user *ubuf, size_t len, | |
4726 | loff_t *offp) | |
4727 | { | |
4728 | struct seq_file *m = file->private_data; | |
4729 | struct drm_i915_private *dev_priv = m->private; | |
4730 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4731 | unsigned int new_threshold; | |
4732 | int i; | |
4733 | char *newline; | |
4734 | char tmp[16]; | |
4735 | ||
4736 | if (len >= sizeof(tmp)) | |
4737 | return -EINVAL; | |
4738 | ||
4739 | if (copy_from_user(tmp, ubuf, len)) | |
4740 | return -EFAULT; | |
4741 | ||
4742 | tmp[len] = '\0'; | |
4743 | ||
4744 | /* Strip newline, if any */ | |
4745 | newline = strchr(tmp, '\n'); | |
4746 | if (newline) | |
4747 | *newline = '\0'; | |
4748 | ||
4749 | if (strcmp(tmp, "reset") == 0) | |
4750 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4751 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4752 | return -EINVAL; | |
4753 | ||
4754 | if (new_threshold > 0) | |
4755 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4756 | new_threshold); | |
4757 | else | |
4758 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4759 | ||
4760 | spin_lock_irq(&dev_priv->irq_lock); | |
4761 | hotplug->hpd_storm_threshold = new_threshold; | |
4762 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4763 | for_each_hpd_pin(i) | |
4764 | hotplug->stats[i].count = 0; | |
4765 | spin_unlock_irq(&dev_priv->irq_lock); | |
4766 | ||
4767 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4768 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4769 | ||
4770 | return len; | |
4771 | } | |
4772 | ||
4773 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4774 | { | |
4775 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4776 | } | |
4777 | ||
4778 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4779 | .owner = THIS_MODULE, | |
4780 | .open = i915_hpd_storm_ctl_open, | |
4781 | .read = seq_read, | |
4782 | .llseek = seq_lseek, | |
4783 | .release = single_release, | |
4784 | .write = i915_hpd_storm_ctl_write | |
4785 | }; | |
4786 | ||
06c5bf8c | 4787 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4788 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4789 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4790 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4791 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4792 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
2017263e BG |
4793 | {"i915_gem_request", i915_gem_request_info, 0}, |
4794 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4795 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4796 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4797 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4798 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4799 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4800 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
ac58d2ab | 4801 | {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, |
a8b9370f | 4802 | {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, |
0509ead1 | 4803 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4804 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4805 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
061d06a2 | 4806 | {"i915_reset_info", i915_reset_info, 0}, |
f97108d1 | 4807 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4808 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4809 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4810 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4811 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4812 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4813 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4814 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4815 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4816 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4817 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4818 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4819 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4820 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4821 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4822 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4823 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4824 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4825 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4826 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4827 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4828 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4829 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4830 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4831 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4832 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4833 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4834 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4835 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4836 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4837 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4838 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4839 | }; |
27c202ad | 4840 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4841 | |
06c5bf8c | 4842 | static const struct i915_debugfs_files { |
34b9674c DV |
4843 | const char *name; |
4844 | const struct file_operations *fops; | |
4845 | } i915_debugfs_files[] = { | |
4846 | {"i915_wedged", &i915_wedged_fops}, | |
4847 | {"i915_max_freq", &i915_max_freq_fops}, | |
4848 | {"i915_min_freq", &i915_min_freq_fops}, | |
4849 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4850 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4851 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4852 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4853 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4854 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4855 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4856 | #endif |
34b9674c | 4857 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4858 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4859 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4860 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4861 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
4127dc43 | 4862 | {"i915_fbc_false_color", &i915_fbc_false_color_fops}, |
eb3394fa TP |
4863 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4864 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4865 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 L |
4866 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
4867 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops} | |
34b9674c DV |
4868 | }; |
4869 | ||
1dac891c | 4870 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4871 | { |
91c8a326 | 4872 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4873 | struct dentry *ent; |
34b9674c | 4874 | int ret, i; |
f3cd474b | 4875 | |
b05eeb0f NT |
4876 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4877 | minor->debugfs_root, to_i915(minor->dev), | |
4878 | &i915_forcewake_fops); | |
4879 | if (!ent) | |
4880 | return -ENOMEM; | |
6a9c308d | 4881 | |
731035fe TV |
4882 | ret = intel_pipe_crc_create(minor); |
4883 | if (ret) | |
4884 | return ret; | |
07144428 | 4885 | |
34b9674c | 4886 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4887 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4888 | S_IRUGO | S_IWUSR, | |
4889 | minor->debugfs_root, | |
4890 | to_i915(minor->dev), | |
34b9674c | 4891 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4892 | if (!ent) |
4893 | return -ENOMEM; | |
34b9674c | 4894 | } |
40633219 | 4895 | |
27c202ad BG |
4896 | return drm_debugfs_create_files(i915_debugfs_list, |
4897 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4898 | minor->debugfs_root, minor); |
4899 | } | |
4900 | ||
aa7471d2 JN |
4901 | struct dpcd_block { |
4902 | /* DPCD dump start address. */ | |
4903 | unsigned int offset; | |
4904 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4905 | unsigned int end; | |
4906 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4907 | size_t size; | |
4908 | /* Only valid for eDP. */ | |
4909 | bool edp; | |
4910 | }; | |
4911 | ||
4912 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4913 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4914 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4915 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4916 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4917 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4918 | { .offset = DP_SET_POWER }, | |
4919 | { .offset = DP_EDP_DPCD_REV }, | |
4920 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4921 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4922 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4923 | }; | |
4924 | ||
4925 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4926 | { | |
4927 | struct drm_connector *connector = m->private; | |
4928 | struct intel_dp *intel_dp = | |
4929 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4930 | uint8_t buf[16]; | |
4931 | ssize_t err; | |
4932 | int i; | |
4933 | ||
5c1a8875 MK |
4934 | if (connector->status != connector_status_connected) |
4935 | return -ENODEV; | |
4936 | ||
aa7471d2 JN |
4937 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4938 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4939 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4940 | ||
4941 | if (b->edp && | |
4942 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4943 | continue; | |
4944 | ||
4945 | /* low tech for now */ | |
4946 | if (WARN_ON(size > sizeof(buf))) | |
4947 | continue; | |
4948 | ||
4949 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4950 | if (err <= 0) { | |
4951 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4952 | size, b->offset, err); | |
4953 | continue; | |
4954 | } | |
4955 | ||
4956 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4957 | } |
aa7471d2 JN |
4958 | |
4959 | return 0; | |
4960 | } | |
4961 | ||
4962 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4963 | { | |
4964 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4965 | } | |
4966 | ||
4967 | static const struct file_operations i915_dpcd_fops = { | |
4968 | .owner = THIS_MODULE, | |
4969 | .open = i915_dpcd_open, | |
4970 | .read = seq_read, | |
4971 | .llseek = seq_lseek, | |
4972 | .release = single_release, | |
4973 | }; | |
4974 | ||
ecbd6781 DW |
4975 | static int i915_panel_show(struct seq_file *m, void *data) |
4976 | { | |
4977 | struct drm_connector *connector = m->private; | |
4978 | struct intel_dp *intel_dp = | |
4979 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4980 | ||
4981 | if (connector->status != connector_status_connected) | |
4982 | return -ENODEV; | |
4983 | ||
4984 | seq_printf(m, "Panel power up delay: %d\n", | |
4985 | intel_dp->panel_power_up_delay); | |
4986 | seq_printf(m, "Panel power down delay: %d\n", | |
4987 | intel_dp->panel_power_down_delay); | |
4988 | seq_printf(m, "Backlight on delay: %d\n", | |
4989 | intel_dp->backlight_on_delay); | |
4990 | seq_printf(m, "Backlight off delay: %d\n", | |
4991 | intel_dp->backlight_off_delay); | |
4992 | ||
4993 | return 0; | |
4994 | } | |
4995 | ||
4996 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4997 | { | |
4998 | return single_open(file, i915_panel_show, inode->i_private); | |
4999 | } | |
5000 | ||
5001 | static const struct file_operations i915_panel_fops = { | |
5002 | .owner = THIS_MODULE, | |
5003 | .open = i915_panel_open, | |
5004 | .read = seq_read, | |
5005 | .llseek = seq_lseek, | |
5006 | .release = single_release, | |
5007 | }; | |
5008 | ||
aa7471d2 JN |
5009 | /** |
5010 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5011 | * @connector: pointer to a registered drm_connector | |
5012 | * | |
5013 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5014 | * drm_debugfs_connector_remove(). | |
5015 | * | |
5016 | * Returns 0 on success, negative error codes on error. | |
5017 | */ | |
5018 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5019 | { | |
5020 | struct dentry *root = connector->debugfs_entry; | |
5021 | ||
5022 | /* The connector must have been registered beforehands. */ | |
5023 | if (!root) | |
5024 | return -ENODEV; | |
5025 | ||
5026 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5027 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
5028 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
5029 | connector, &i915_dpcd_fops); | |
5030 | ||
5031 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5032 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
5033 | connector, &i915_panel_fops); | |
aa7471d2 JN |
5034 | |
5035 | return 0; | |
5036 | } |