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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
6d2b8885 | 33 | #include <linux/list_sort.h> |
ec013e7f | 34 | #include <asm/msr-index.h> |
760285e7 | 35 | #include <drm/drmP.h> |
4e5359cd | 36 | #include "intel_drv.h" |
e5c65260 | 37 | #include "intel_ringbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
2017263e BG |
39 | #include "i915_drv.h" |
40 | ||
2017263e BG |
41 | #if defined(CONFIG_DEBUG_FS) |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
54 | static int i915_capabilities(struct seq_file *m, void *data) | |
55 | { | |
56 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
57 | struct drm_device *dev = node->minor->dev; | |
58 | const struct intel_device_info *info = INTEL_INFO(dev); | |
59 | ||
60 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 61 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
62 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
63 | #define SEP_SEMICOLON ; | |
64 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
65 | #undef PRINT_FLAG | |
66 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
67 | |
68 | return 0; | |
69 | } | |
2017263e | 70 | |
05394f39 | 71 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 72 | { |
05394f39 | 73 | if (obj->user_pin_count > 0) |
a6172a80 | 74 | return "P"; |
05394f39 | 75 | else if (obj->pin_count > 0) |
a6172a80 CW |
76 | return "p"; |
77 | else | |
78 | return " "; | |
79 | } | |
80 | ||
05394f39 | 81 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 82 | { |
0206e353 AJ |
83 | switch (obj->tiling_mode) { |
84 | default: | |
85 | case I915_TILING_NONE: return " "; | |
86 | case I915_TILING_X: return "X"; | |
87 | case I915_TILING_Y: return "Y"; | |
88 | } | |
a6172a80 CW |
89 | } |
90 | ||
1d693bcc BW |
91 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
92 | { | |
93 | return obj->has_global_gtt_mapping ? "g" : " "; | |
94 | } | |
95 | ||
37811fcc CW |
96 | static void |
97 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
98 | { | |
1d693bcc | 99 | struct i915_vma *vma; |
fb1ae911 | 100 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
101 | &obj->base, |
102 | get_pin_flag(obj), | |
103 | get_tiling_flag(obj), | |
1d693bcc | 104 | get_global_flag(obj), |
a05a5862 | 105 | obj->base.size / 1024, |
37811fcc CW |
106 | obj->base.read_domains, |
107 | obj->base.write_domain, | |
0201f1ec CW |
108 | obj->last_read_seqno, |
109 | obj->last_write_seqno, | |
caea7476 | 110 | obj->last_fenced_seqno, |
84734a04 | 111 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
112 | obj->dirty ? " dirty" : "", |
113 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
114 | if (obj->base.name) | |
115 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
116 | if (obj->pin_count) |
117 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
118 | if (obj->pin_display) |
119 | seq_printf(m, " (display)"); | |
37811fcc CW |
120 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
121 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
122 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
123 | if (!i915_is_ggtt(vma->vm)) | |
124 | seq_puts(m, " (pp"); | |
125 | else | |
126 | seq_puts(m, " (g"); | |
127 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
128 | vma->node.start, vma->node.size); | |
129 | } | |
c1ad11fc CW |
130 | if (obj->stolen) |
131 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
132 | if (obj->pin_mappable || obj->fault_mappable) { |
133 | char s[3], *t = s; | |
134 | if (obj->pin_mappable) | |
135 | *t++ = 'p'; | |
136 | if (obj->fault_mappable) | |
137 | *t++ = 'f'; | |
138 | *t = '\0'; | |
139 | seq_printf(m, " (%s mappable)", s); | |
140 | } | |
69dc4987 CW |
141 | if (obj->ring != NULL) |
142 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
143 | } |
144 | ||
3ccfd19d BW |
145 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
146 | { | |
147 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
148 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
149 | seq_putc(m, ' '); | |
150 | } | |
151 | ||
433e12f7 | 152 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
153 | { |
154 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
155 | uintptr_t list = (uintptr_t) node->info_ent->data; |
156 | struct list_head *head; | |
2017263e | 157 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
158 | struct drm_i915_private *dev_priv = dev->dev_private; |
159 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 160 | struct i915_vma *vma; |
8f2480fb CW |
161 | size_t total_obj_size, total_gtt_size; |
162 | int count, ret; | |
de227ef0 CW |
163 | |
164 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
165 | if (ret) | |
166 | return ret; | |
2017263e | 167 | |
ca191b13 | 168 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
169 | switch (list) { |
170 | case ACTIVE_LIST: | |
267f0c90 | 171 | seq_puts(m, "Active:\n"); |
5cef07e1 | 172 | head = &vm->active_list; |
433e12f7 BG |
173 | break; |
174 | case INACTIVE_LIST: | |
267f0c90 | 175 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 176 | head = &vm->inactive_list; |
433e12f7 | 177 | break; |
433e12f7 | 178 | default: |
de227ef0 CW |
179 | mutex_unlock(&dev->struct_mutex); |
180 | return -EINVAL; | |
2017263e | 181 | } |
2017263e | 182 | |
8f2480fb | 183 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
184 | list_for_each_entry(vma, head, mm_list) { |
185 | seq_printf(m, " "); | |
186 | describe_obj(m, vma->obj); | |
187 | seq_printf(m, "\n"); | |
188 | total_obj_size += vma->obj->base.size; | |
189 | total_gtt_size += vma->node.size; | |
8f2480fb | 190 | count++; |
2017263e | 191 | } |
de227ef0 | 192 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 193 | |
8f2480fb CW |
194 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
195 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
196 | return 0; |
197 | } | |
198 | ||
6d2b8885 CW |
199 | static int obj_rank_by_stolen(void *priv, |
200 | struct list_head *A, struct list_head *B) | |
201 | { | |
202 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 203 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 204 | struct drm_i915_gem_object *b = |
b25cb2f8 | 205 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
206 | |
207 | return a->stolen->start - b->stolen->start; | |
208 | } | |
209 | ||
210 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
211 | { | |
212 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
213 | struct drm_device *dev = node->minor->dev; | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | struct drm_i915_gem_object *obj; | |
216 | size_t total_obj_size, total_gtt_size; | |
217 | LIST_HEAD(stolen); | |
218 | int count, ret; | |
219 | ||
220 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
221 | if (ret) | |
222 | return ret; | |
223 | ||
224 | total_obj_size = total_gtt_size = count = 0; | |
225 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
226 | if (obj->stolen == NULL) | |
227 | continue; | |
228 | ||
b25cb2f8 | 229 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
230 | |
231 | total_obj_size += obj->base.size; | |
232 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
233 | count++; | |
234 | } | |
235 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
236 | if (obj->stolen == NULL) | |
237 | continue; | |
238 | ||
b25cb2f8 | 239 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
240 | |
241 | total_obj_size += obj->base.size; | |
242 | count++; | |
243 | } | |
244 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
245 | seq_puts(m, "Stolen:\n"); | |
246 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 247 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
248 | seq_puts(m, " "); |
249 | describe_obj(m, obj); | |
250 | seq_putc(m, '\n'); | |
b25cb2f8 | 251 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
252 | } |
253 | mutex_unlock(&dev->struct_mutex); | |
254 | ||
255 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
256 | count, total_obj_size, total_gtt_size); | |
257 | return 0; | |
258 | } | |
259 | ||
6299f992 CW |
260 | #define count_objects(list, member) do { \ |
261 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 262 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
263 | ++count; \ |
264 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 265 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
266 | ++mappable_count; \ |
267 | } \ | |
268 | } \ | |
0206e353 | 269 | } while (0) |
6299f992 | 270 | |
2db8e9d6 CW |
271 | struct file_stats { |
272 | int count; | |
273 | size_t total, active, inactive, unbound; | |
274 | }; | |
275 | ||
276 | static int per_file_stats(int id, void *ptr, void *data) | |
277 | { | |
278 | struct drm_i915_gem_object *obj = ptr; | |
279 | struct file_stats *stats = data; | |
280 | ||
281 | stats->count++; | |
282 | stats->total += obj->base.size; | |
283 | ||
f343c5f6 | 284 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
285 | if (!list_empty(&obj->ring_list)) |
286 | stats->active += obj->base.size; | |
287 | else | |
288 | stats->inactive += obj->base.size; | |
289 | } else { | |
290 | if (!list_empty(&obj->global_list)) | |
291 | stats->unbound += obj->base.size; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
ca191b13 BW |
297 | #define count_vmas(list, member) do { \ |
298 | list_for_each_entry(vma, list, member) { \ | |
299 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
300 | ++count; \ | |
301 | if (vma->obj->map_and_fenceable) { \ | |
302 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
303 | ++mappable_count; \ | |
304 | } \ | |
305 | } \ | |
306 | } while (0) | |
307 | ||
308 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
309 | { |
310 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
311 | struct drm_device *dev = node->minor->dev; | |
312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
313 | u32 count, mappable_count, purgeable_count; |
314 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 315 | struct drm_i915_gem_object *obj; |
5cef07e1 | 316 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 317 | struct drm_file *file; |
ca191b13 | 318 | struct i915_vma *vma; |
73aa808f CW |
319 | int ret; |
320 | ||
321 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
322 | if (ret) | |
323 | return ret; | |
324 | ||
6299f992 CW |
325 | seq_printf(m, "%u objects, %zu bytes\n", |
326 | dev_priv->mm.object_count, | |
327 | dev_priv->mm.object_memory); | |
328 | ||
329 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 330 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
331 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
332 | count, mappable_count, size, mappable_size); | |
333 | ||
334 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 335 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
336 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
337 | count, mappable_count, size, mappable_size); | |
338 | ||
6299f992 | 339 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 340 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
341 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
342 | count, mappable_count, size, mappable_size); | |
343 | ||
b7abb714 | 344 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 345 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 346 | size += obj->base.size, ++count; |
b7abb714 CW |
347 | if (obj->madv == I915_MADV_DONTNEED) |
348 | purgeable_size += obj->base.size, ++purgeable_count; | |
349 | } | |
6c085a72 CW |
350 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
351 | ||
6299f992 | 352 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 353 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 354 | if (obj->fault_mappable) { |
f343c5f6 | 355 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
356 | ++count; |
357 | } | |
358 | if (obj->pin_mappable) { | |
f343c5f6 | 359 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
360 | ++mappable_count; |
361 | } | |
b7abb714 CW |
362 | if (obj->madv == I915_MADV_DONTNEED) { |
363 | purgeable_size += obj->base.size; | |
364 | ++purgeable_count; | |
365 | } | |
6299f992 | 366 | } |
b7abb714 CW |
367 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
368 | purgeable_count, purgeable_size); | |
6299f992 CW |
369 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
370 | mappable_count, mappable_size); | |
371 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
372 | count, size); | |
373 | ||
93d18799 | 374 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
375 | dev_priv->gtt.base.total, |
376 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 377 | |
267f0c90 | 378 | seq_putc(m, '\n'); |
2db8e9d6 CW |
379 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
380 | struct file_stats stats; | |
381 | ||
382 | memset(&stats, 0, sizeof(stats)); | |
383 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
384 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
385 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
386 | stats.count, | |
387 | stats.total, | |
388 | stats.active, | |
389 | stats.inactive, | |
390 | stats.unbound); | |
391 | } | |
392 | ||
73aa808f CW |
393 | mutex_unlock(&dev->struct_mutex); |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
aee56cff | 398 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
399 | { |
400 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
401 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 402 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | struct drm_i915_gem_object *obj; | |
405 | size_t total_obj_size, total_gtt_size; | |
406 | int count, ret; | |
407 | ||
408 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
412 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 413 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
414 | if (list == PINNED_LIST && obj->pin_count == 0) |
415 | continue; | |
416 | ||
267f0c90 | 417 | seq_puts(m, " "); |
08c18323 | 418 | describe_obj(m, obj); |
267f0c90 | 419 | seq_putc(m, '\n'); |
08c18323 | 420 | total_obj_size += obj->base.size; |
f343c5f6 | 421 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
422 | count++; |
423 | } | |
424 | ||
425 | mutex_unlock(&dev->struct_mutex); | |
426 | ||
427 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
428 | count, total_obj_size, total_gtt_size); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
4e5359cd SF |
433 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
434 | { | |
435 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
436 | struct drm_device *dev = node->minor->dev; | |
437 | unsigned long flags; | |
438 | struct intel_crtc *crtc; | |
439 | ||
440 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
441 | const char pipe = pipe_name(crtc->pipe); |
442 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
443 | struct intel_unpin_work *work; |
444 | ||
445 | spin_lock_irqsave(&dev->event_lock, flags); | |
446 | work = crtc->unpin_work; | |
447 | if (work == NULL) { | |
9db4a9c7 | 448 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
449 | pipe, plane); |
450 | } else { | |
e7d841ca | 451 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 452 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
453 | pipe, plane); |
454 | } else { | |
9db4a9c7 | 455 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
456 | pipe, plane); |
457 | } | |
458 | if (work->enable_stall_check) | |
267f0c90 | 459 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 460 | else |
267f0c90 | 461 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 462 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
463 | |
464 | if (work->old_fb_obj) { | |
05394f39 CW |
465 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
466 | if (obj) | |
f343c5f6 BW |
467 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
468 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
469 | } |
470 | if (work->pending_flip_obj) { | |
05394f39 CW |
471 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
472 | if (obj) | |
f343c5f6 BW |
473 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
474 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
475 | } |
476 | } | |
477 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
2017263e BG |
483 | static int i915_gem_request_info(struct seq_file *m, void *data) |
484 | { | |
485 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
486 | struct drm_device *dev = node->minor->dev; | |
487 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 488 | struct intel_ring_buffer *ring; |
2017263e | 489 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 490 | int ret, count, i; |
de227ef0 CW |
491 | |
492 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
493 | if (ret) | |
494 | return ret; | |
2017263e | 495 | |
c2c347a9 | 496 | count = 0; |
a2c7f6fd CW |
497 | for_each_ring(ring, dev_priv, i) { |
498 | if (list_empty(&ring->request_list)) | |
499 | continue; | |
500 | ||
501 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 502 | list_for_each_entry(gem_request, |
a2c7f6fd | 503 | &ring->request_list, |
c2c347a9 CW |
504 | list) { |
505 | seq_printf(m, " %d @ %d\n", | |
506 | gem_request->seqno, | |
507 | (int) (jiffies - gem_request->emitted_jiffies)); | |
508 | } | |
509 | count++; | |
2017263e | 510 | } |
de227ef0 CW |
511 | mutex_unlock(&dev->struct_mutex); |
512 | ||
c2c347a9 | 513 | if (count == 0) |
267f0c90 | 514 | seq_puts(m, "No requests\n"); |
c2c347a9 | 515 | |
2017263e BG |
516 | return 0; |
517 | } | |
518 | ||
b2223497 CW |
519 | static void i915_ring_seqno_info(struct seq_file *m, |
520 | struct intel_ring_buffer *ring) | |
521 | { | |
522 | if (ring->get_seqno) { | |
43a7b924 | 523 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 524 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
525 | } |
526 | } | |
527 | ||
2017263e BG |
528 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
529 | { | |
530 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
531 | struct drm_device *dev = node->minor->dev; | |
532 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 533 | struct intel_ring_buffer *ring; |
1ec14ad3 | 534 | int ret, i; |
de227ef0 CW |
535 | |
536 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
537 | if (ret) | |
538 | return ret; | |
2017263e | 539 | |
a2c7f6fd CW |
540 | for_each_ring(ring, dev_priv, i) |
541 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
542 | |
543 | mutex_unlock(&dev->struct_mutex); | |
544 | ||
2017263e BG |
545 | return 0; |
546 | } | |
547 | ||
548 | ||
549 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
550 | { | |
551 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
552 | struct drm_device *dev = node->minor->dev; | |
553 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 554 | struct intel_ring_buffer *ring; |
9db4a9c7 | 555 | int ret, i, pipe; |
de227ef0 CW |
556 | |
557 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
558 | if (ret) | |
559 | return ret; | |
2017263e | 560 | |
7e231dbe JB |
561 | if (IS_VALLEYVIEW(dev)) { |
562 | seq_printf(m, "Display IER:\t%08x\n", | |
563 | I915_READ(VLV_IER)); | |
564 | seq_printf(m, "Display IIR:\t%08x\n", | |
565 | I915_READ(VLV_IIR)); | |
566 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
567 | I915_READ(VLV_IIR_RW)); | |
568 | seq_printf(m, "Display IMR:\t%08x\n", | |
569 | I915_READ(VLV_IMR)); | |
570 | for_each_pipe(pipe) | |
571 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
572 | pipe_name(pipe), | |
573 | I915_READ(PIPESTAT(pipe))); | |
574 | ||
575 | seq_printf(m, "Master IER:\t%08x\n", | |
576 | I915_READ(VLV_MASTER_IER)); | |
577 | ||
578 | seq_printf(m, "Render IER:\t%08x\n", | |
579 | I915_READ(GTIER)); | |
580 | seq_printf(m, "Render IIR:\t%08x\n", | |
581 | I915_READ(GTIIR)); | |
582 | seq_printf(m, "Render IMR:\t%08x\n", | |
583 | I915_READ(GTIMR)); | |
584 | ||
585 | seq_printf(m, "PM IER:\t\t%08x\n", | |
586 | I915_READ(GEN6_PMIER)); | |
587 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
588 | I915_READ(GEN6_PMIIR)); | |
589 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
590 | I915_READ(GEN6_PMIMR)); | |
591 | ||
592 | seq_printf(m, "Port hotplug:\t%08x\n", | |
593 | I915_READ(PORT_HOTPLUG_EN)); | |
594 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
595 | I915_READ(VLV_DPFLIPSTAT)); | |
596 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
597 | I915_READ(DPINVGTT)); | |
598 | ||
599 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
600 | seq_printf(m, "Interrupt enable: %08x\n", |
601 | I915_READ(IER)); | |
602 | seq_printf(m, "Interrupt identity: %08x\n", | |
603 | I915_READ(IIR)); | |
604 | seq_printf(m, "Interrupt mask: %08x\n", | |
605 | I915_READ(IMR)); | |
9db4a9c7 JB |
606 | for_each_pipe(pipe) |
607 | seq_printf(m, "Pipe %c stat: %08x\n", | |
608 | pipe_name(pipe), | |
609 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
610 | } else { |
611 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
612 | I915_READ(DEIER)); | |
613 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
614 | I915_READ(DEIIR)); | |
615 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
616 | I915_READ(DEIMR)); | |
617 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
618 | I915_READ(SDEIER)); | |
619 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
620 | I915_READ(SDEIIR)); | |
621 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
622 | I915_READ(SDEIMR)); | |
623 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
624 | I915_READ(GTIER)); | |
625 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
626 | I915_READ(GTIIR)); | |
627 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
628 | I915_READ(GTIMR)); | |
629 | } | |
2017263e BG |
630 | seq_printf(m, "Interrupts received: %d\n", |
631 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 632 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 633 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
634 | seq_printf(m, |
635 | "Graphics Interrupt mask (%s): %08x\n", | |
636 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 637 | } |
a2c7f6fd | 638 | i915_ring_seqno_info(m, ring); |
9862e600 | 639 | } |
de227ef0 CW |
640 | mutex_unlock(&dev->struct_mutex); |
641 | ||
2017263e BG |
642 | return 0; |
643 | } | |
644 | ||
a6172a80 CW |
645 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
646 | { | |
647 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
648 | struct drm_device *dev = node->minor->dev; | |
649 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
650 | int i, ret; |
651 | ||
652 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
653 | if (ret) | |
654 | return ret; | |
a6172a80 CW |
655 | |
656 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
657 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
658 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 659 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 660 | |
6c085a72 CW |
661 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
662 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 663 | if (obj == NULL) |
267f0c90 | 664 | seq_puts(m, "unused"); |
c2c347a9 | 665 | else |
05394f39 | 666 | describe_obj(m, obj); |
267f0c90 | 667 | seq_putc(m, '\n'); |
a6172a80 CW |
668 | } |
669 | ||
05394f39 | 670 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
671 | return 0; |
672 | } | |
673 | ||
2017263e BG |
674 | static int i915_hws_info(struct seq_file *m, void *data) |
675 | { | |
676 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
677 | struct drm_device *dev = node->minor->dev; | |
678 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 679 | struct intel_ring_buffer *ring; |
1a240d4d | 680 | const u32 *hws; |
4066c0ae CW |
681 | int i; |
682 | ||
1ec14ad3 | 683 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 684 | hws = ring->status_page.page_addr; |
2017263e BG |
685 | if (hws == NULL) |
686 | return 0; | |
687 | ||
688 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
689 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
690 | i * 4, | |
691 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
692 | } | |
693 | return 0; | |
694 | } | |
695 | ||
d5442303 DV |
696 | static ssize_t |
697 | i915_error_state_write(struct file *filp, | |
698 | const char __user *ubuf, | |
699 | size_t cnt, | |
700 | loff_t *ppos) | |
701 | { | |
edc3d884 | 702 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 703 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 704 | int ret; |
d5442303 DV |
705 | |
706 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
707 | ||
22bcfc6a DV |
708 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
709 | if (ret) | |
710 | return ret; | |
711 | ||
d5442303 DV |
712 | i915_destroy_error_state(dev); |
713 | mutex_unlock(&dev->struct_mutex); | |
714 | ||
715 | return cnt; | |
716 | } | |
717 | ||
718 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
719 | { | |
720 | struct drm_device *dev = inode->i_private; | |
d5442303 | 721 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
722 | |
723 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
724 | if (!error_priv) | |
725 | return -ENOMEM; | |
726 | ||
727 | error_priv->dev = dev; | |
728 | ||
95d5bfb3 | 729 | i915_error_state_get(dev, error_priv); |
d5442303 | 730 | |
edc3d884 MK |
731 | file->private_data = error_priv; |
732 | ||
733 | return 0; | |
d5442303 DV |
734 | } |
735 | ||
736 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
737 | { | |
edc3d884 | 738 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 739 | |
95d5bfb3 | 740 | i915_error_state_put(error_priv); |
d5442303 DV |
741 | kfree(error_priv); |
742 | ||
edc3d884 MK |
743 | return 0; |
744 | } | |
745 | ||
4dc955f7 MK |
746 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
747 | size_t count, loff_t *pos) | |
748 | { | |
749 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
750 | struct drm_i915_error_state_buf error_str; | |
751 | loff_t tmp_pos = 0; | |
752 | ssize_t ret_count = 0; | |
753 | int ret; | |
754 | ||
755 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
756 | if (ret) | |
757 | return ret; | |
edc3d884 | 758 | |
fc16b48b | 759 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
760 | if (ret) |
761 | goto out; | |
762 | ||
edc3d884 MK |
763 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
764 | error_str.buf, | |
765 | error_str.bytes); | |
766 | ||
767 | if (ret_count < 0) | |
768 | ret = ret_count; | |
769 | else | |
770 | *pos = error_str.start + ret_count; | |
771 | out: | |
4dc955f7 | 772 | i915_error_state_buf_release(&error_str); |
edc3d884 | 773 | return ret ?: ret_count; |
d5442303 DV |
774 | } |
775 | ||
776 | static const struct file_operations i915_error_state_fops = { | |
777 | .owner = THIS_MODULE, | |
778 | .open = i915_error_state_open, | |
edc3d884 | 779 | .read = i915_error_state_read, |
d5442303 DV |
780 | .write = i915_error_state_write, |
781 | .llseek = default_llseek, | |
782 | .release = i915_error_state_release, | |
783 | }; | |
784 | ||
647416f9 KC |
785 | static int |
786 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 787 | { |
647416f9 | 788 | struct drm_device *dev = data; |
40633219 | 789 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
790 | int ret; |
791 | ||
792 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
793 | if (ret) | |
794 | return ret; | |
795 | ||
647416f9 | 796 | *val = dev_priv->next_seqno; |
40633219 MK |
797 | mutex_unlock(&dev->struct_mutex); |
798 | ||
647416f9 | 799 | return 0; |
40633219 MK |
800 | } |
801 | ||
647416f9 KC |
802 | static int |
803 | i915_next_seqno_set(void *data, u64 val) | |
804 | { | |
805 | struct drm_device *dev = data; | |
40633219 MK |
806 | int ret; |
807 | ||
40633219 MK |
808 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
809 | if (ret) | |
810 | return ret; | |
811 | ||
e94fbaa8 | 812 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
813 | mutex_unlock(&dev->struct_mutex); |
814 | ||
647416f9 | 815 | return ret; |
40633219 MK |
816 | } |
817 | ||
647416f9 KC |
818 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
819 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 820 | "0x%llx\n"); |
40633219 | 821 | |
f97108d1 JB |
822 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
823 | { | |
824 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
825 | struct drm_device *dev = node->minor->dev; | |
826 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
827 | u16 crstanddelay; |
828 | int ret; | |
829 | ||
830 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
831 | if (ret) | |
832 | return ret; | |
833 | ||
834 | crstanddelay = I915_READ16(CRSTANDVID); | |
835 | ||
836 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
837 | |
838 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
844 | { | |
845 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
846 | struct drm_device *dev = node->minor->dev; | |
847 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 848 | int ret; |
3b8d8d91 | 849 | |
5c9669ce TR |
850 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
851 | ||
3b8d8d91 JB |
852 | if (IS_GEN5(dev)) { |
853 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
854 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
855 | ||
856 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
857 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
858 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
859 | MEMSTAT_VID_SHIFT); | |
860 | seq_printf(m, "Current P-state: %d\n", | |
861 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 862 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
863 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
864 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
865 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 866 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
867 | u32 rpupei, rpcurup, rpprevup; |
868 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
869 | int max_freq; |
870 | ||
871 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
872 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
873 | if (ret) | |
874 | return ret; | |
875 | ||
fcca7926 | 876 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 877 | |
8e8c06cd CW |
878 | reqf = I915_READ(GEN6_RPNSWREQ); |
879 | reqf &= ~GEN6_TURBO_DISABLE; | |
880 | if (IS_HASWELL(dev)) | |
881 | reqf >>= 24; | |
882 | else | |
883 | reqf >>= 25; | |
884 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
885 | ||
ccab5c82 JB |
886 | rpstat = I915_READ(GEN6_RPSTAT1); |
887 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
888 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
889 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
890 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
891 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
892 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
893 | if (IS_HASWELL(dev)) |
894 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
895 | else | |
896 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
897 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 898 | |
d1ebd816 BW |
899 | gen6_gt_force_wake_put(dev_priv); |
900 | mutex_unlock(&dev->struct_mutex); | |
901 | ||
3b8d8d91 | 902 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 903 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
904 | seq_printf(m, "Render p-state ratio: %d\n", |
905 | (gt_perf_status & 0xff00) >> 8); | |
906 | seq_printf(m, "Render p-state VID: %d\n", | |
907 | gt_perf_status & 0xff); | |
908 | seq_printf(m, "Render p-state limit: %d\n", | |
909 | rp_state_limits & 0xff); | |
8e8c06cd | 910 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 911 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
912 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
913 | GEN6_CURICONT_MASK); | |
914 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
915 | GEN6_CURBSYTAVG_MASK); | |
916 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
917 | GEN6_CURBSYTAVG_MASK); | |
918 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
919 | GEN6_CURIAVG_MASK); | |
920 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
921 | GEN6_CURBSYTAVG_MASK); | |
922 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
923 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
924 | |
925 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
926 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 927 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
928 | |
929 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
930 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 931 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
932 | |
933 | max_freq = rp_state_cap & 0xff; | |
934 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 935 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
936 | |
937 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
938 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
939 | } else if (IS_VALLEYVIEW(dev)) { |
940 | u32 freq_sts, val; | |
941 | ||
259bd5d4 | 942 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 943 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
944 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
945 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
946 | ||
64936258 | 947 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
948 | seq_printf(m, "max GPU freq: %d MHz\n", |
949 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
950 | ||
64936258 | 951 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
952 | seq_printf(m, "min GPU freq: %d MHz\n", |
953 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
954 | ||
955 | seq_printf(m, "current GPU freq: %d MHz\n", | |
956 | vlv_gpu_freq(dev_priv->mem_freq, | |
957 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 958 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 959 | } else { |
267f0c90 | 960 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 961 | } |
f97108d1 JB |
962 | |
963 | return 0; | |
964 | } | |
965 | ||
966 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
967 | { | |
968 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
969 | struct drm_device *dev = node->minor->dev; | |
970 | drm_i915_private_t *dev_priv = dev->dev_private; | |
971 | u32 delayfreq; | |
616fdb5a BW |
972 | int ret, i; |
973 | ||
974 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
975 | if (ret) | |
976 | return ret; | |
f97108d1 JB |
977 | |
978 | for (i = 0; i < 16; i++) { | |
979 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
980 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
981 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
982 | } |
983 | ||
616fdb5a BW |
984 | mutex_unlock(&dev->struct_mutex); |
985 | ||
f97108d1 JB |
986 | return 0; |
987 | } | |
988 | ||
989 | static inline int MAP_TO_MV(int map) | |
990 | { | |
991 | return 1250 - (map * 25); | |
992 | } | |
993 | ||
994 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
995 | { | |
996 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
997 | struct drm_device *dev = node->minor->dev; | |
998 | drm_i915_private_t *dev_priv = dev->dev_private; | |
999 | u32 inttoext; | |
616fdb5a BW |
1000 | int ret, i; |
1001 | ||
1002 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1003 | if (ret) | |
1004 | return ret; | |
f97108d1 JB |
1005 | |
1006 | for (i = 1; i <= 32; i++) { | |
1007 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1008 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1009 | } | |
1010 | ||
616fdb5a BW |
1011 | mutex_unlock(&dev->struct_mutex); |
1012 | ||
f97108d1 JB |
1013 | return 0; |
1014 | } | |
1015 | ||
4d85529d | 1016 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1017 | { |
1018 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1019 | struct drm_device *dev = node->minor->dev; | |
1020 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1021 | u32 rgvmodectl, rstdbyctl; |
1022 | u16 crstandvid; | |
1023 | int ret; | |
1024 | ||
1025 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1026 | if (ret) | |
1027 | return ret; | |
1028 | ||
1029 | rgvmodectl = I915_READ(MEMMODECTL); | |
1030 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1031 | crstandvid = I915_READ16(CRSTANDVID); | |
1032 | ||
1033 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1034 | |
1035 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1036 | "yes" : "no"); | |
1037 | seq_printf(m, "Boost freq: %d\n", | |
1038 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1039 | MEMMODE_BOOST_FREQ_SHIFT); | |
1040 | seq_printf(m, "HW control enabled: %s\n", | |
1041 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1042 | seq_printf(m, "SW control enabled: %s\n", | |
1043 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1044 | seq_printf(m, "Gated voltage change: %s\n", | |
1045 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1046 | seq_printf(m, "Starting frequency: P%d\n", | |
1047 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1048 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1049 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1050 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1051 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1052 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1053 | seq_printf(m, "Render standby enabled: %s\n", | |
1054 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1055 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1056 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1057 | case RSX_STATUS_ON: | |
267f0c90 | 1058 | seq_puts(m, "on\n"); |
88271da3 JB |
1059 | break; |
1060 | case RSX_STATUS_RC1: | |
267f0c90 | 1061 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1062 | break; |
1063 | case RSX_STATUS_RC1E: | |
267f0c90 | 1064 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1065 | break; |
1066 | case RSX_STATUS_RS1: | |
267f0c90 | 1067 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1068 | break; |
1069 | case RSX_STATUS_RS2: | |
267f0c90 | 1070 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1071 | break; |
1072 | case RSX_STATUS_RS3: | |
267f0c90 | 1073 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1074 | break; |
1075 | default: | |
267f0c90 | 1076 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1077 | break; |
1078 | } | |
f97108d1 JB |
1079 | |
1080 | return 0; | |
1081 | } | |
1082 | ||
4d85529d BW |
1083 | static int gen6_drpc_info(struct seq_file *m) |
1084 | { | |
1085 | ||
1086 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1087 | struct drm_device *dev = node->minor->dev; | |
1088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1089 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1090 | unsigned forcewake_count; |
aee56cff | 1091 | int count = 0, ret; |
4d85529d BW |
1092 | |
1093 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1094 | if (ret) | |
1095 | return ret; | |
1096 | ||
907b28c5 CW |
1097 | spin_lock_irq(&dev_priv->uncore.lock); |
1098 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1099 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1100 | |
1101 | if (forcewake_count) { | |
267f0c90 DL |
1102 | seq_puts(m, "RC information inaccurate because somebody " |
1103 | "holds a forcewake reference \n"); | |
4d85529d BW |
1104 | } else { |
1105 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1106 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1107 | udelay(10); | |
1108 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1109 | } | |
1110 | ||
1111 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1112 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1113 | |
1114 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1115 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1116 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1117 | mutex_lock(&dev_priv->rps.hw_lock); |
1118 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1119 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1120 | |
1121 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1122 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1123 | seq_printf(m, "HW control enabled: %s\n", | |
1124 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1125 | seq_printf(m, "SW control enabled: %s\n", | |
1126 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1127 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1128 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1129 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1130 | seq_printf(m, "RC6 Enabled: %s\n", | |
1131 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1132 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1133 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1134 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1135 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1136 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1137 | switch (gt_core_status & GEN6_RCn_MASK) { |
1138 | case GEN6_RC0: | |
1139 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1140 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1141 | else |
267f0c90 | 1142 | seq_puts(m, "on\n"); |
4d85529d BW |
1143 | break; |
1144 | case GEN6_RC3: | |
267f0c90 | 1145 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1146 | break; |
1147 | case GEN6_RC6: | |
267f0c90 | 1148 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1149 | break; |
1150 | case GEN6_RC7: | |
267f0c90 | 1151 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1152 | break; |
1153 | default: | |
267f0c90 | 1154 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1155 | break; |
1156 | } | |
1157 | ||
1158 | seq_printf(m, "Core Power Down: %s\n", | |
1159 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1160 | |
1161 | /* Not exactly sure what this is */ | |
1162 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1163 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1164 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1165 | I915_READ(GEN6_GT_GFX_RC6)); | |
1166 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1167 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1168 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1169 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1170 | ||
ecd8faea BW |
1171 | seq_printf(m, "RC6 voltage: %dmV\n", |
1172 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1173 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1174 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1175 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1176 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1177 | return 0; |
1178 | } | |
1179 | ||
1180 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1181 | { | |
1182 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1183 | struct drm_device *dev = node->minor->dev; | |
1184 | ||
1185 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1186 | return gen6_drpc_info(m); | |
1187 | else | |
1188 | return ironlake_drpc_info(m); | |
1189 | } | |
1190 | ||
b5e50c3f JB |
1191 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1192 | { | |
1193 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1194 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1195 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1196 | |
ee5382ae | 1197 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1198 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1199 | return 0; |
1200 | } | |
1201 | ||
ee5382ae | 1202 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1203 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1204 | } else { |
267f0c90 | 1205 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1206 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1207 | case FBC_OK: |
1208 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1209 | break; | |
1210 | case FBC_UNSUPPORTED: | |
1211 | seq_puts(m, "unsupported by this chipset"); | |
1212 | break; | |
bed4a673 | 1213 | case FBC_NO_OUTPUT: |
267f0c90 | 1214 | seq_puts(m, "no outputs"); |
bed4a673 | 1215 | break; |
b5e50c3f | 1216 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1217 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1218 | break; |
1219 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1220 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1221 | break; |
1222 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1223 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1224 | break; |
1225 | case FBC_BAD_PLANE: | |
267f0c90 | 1226 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1227 | break; |
1228 | case FBC_NOT_TILED: | |
267f0c90 | 1229 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1230 | break; |
9c928d16 | 1231 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1232 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1233 | break; |
c1a9f047 | 1234 | case FBC_MODULE_PARAM: |
267f0c90 | 1235 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1236 | break; |
8a5729a3 | 1237 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1238 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1239 | break; |
b5e50c3f | 1240 | default: |
267f0c90 | 1241 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1242 | } |
267f0c90 | 1243 | seq_putc(m, '\n'); |
b5e50c3f JB |
1244 | } |
1245 | return 0; | |
1246 | } | |
1247 | ||
92d44621 PZ |
1248 | static int i915_ips_status(struct seq_file *m, void *unused) |
1249 | { | |
1250 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1251 | struct drm_device *dev = node->minor->dev; | |
1252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1253 | ||
f5adf94e | 1254 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1255 | seq_puts(m, "not supported\n"); |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1260 | seq_puts(m, "enabled\n"); | |
1261 | else | |
1262 | seq_puts(m, "disabled\n"); | |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
4a9bef37 JB |
1267 | static int i915_sr_status(struct seq_file *m, void *unused) |
1268 | { | |
1269 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1270 | struct drm_device *dev = node->minor->dev; | |
1271 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1272 | bool sr_enabled = false; | |
1273 | ||
1398261a | 1274 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1275 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1276 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1277 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1278 | else if (IS_I915GM(dev)) | |
1279 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1280 | else if (IS_PINEVIEW(dev)) | |
1281 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1282 | ||
5ba2aaaa CW |
1283 | seq_printf(m, "self-refresh: %s\n", |
1284 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1285 | |
1286 | return 0; | |
1287 | } | |
1288 | ||
7648fa99 JB |
1289 | static int i915_emon_status(struct seq_file *m, void *unused) |
1290 | { | |
1291 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1292 | struct drm_device *dev = node->minor->dev; | |
1293 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1294 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1295 | int ret; |
1296 | ||
582be6b4 CW |
1297 | if (!IS_GEN5(dev)) |
1298 | return -ENODEV; | |
1299 | ||
de227ef0 CW |
1300 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1301 | if (ret) | |
1302 | return ret; | |
7648fa99 JB |
1303 | |
1304 | temp = i915_mch_val(dev_priv); | |
1305 | chipset = i915_chipset_val(dev_priv); | |
1306 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1307 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1308 | |
1309 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1310 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1311 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1312 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
23b2f8bb JB |
1317 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1318 | { | |
1319 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1320 | struct drm_device *dev = node->minor->dev; | |
1321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1322 | int ret; | |
1323 | int gpu_freq, ia_freq; | |
1324 | ||
1c70c0ce | 1325 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1326 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1327 | return 0; |
1328 | } | |
1329 | ||
5c9669ce TR |
1330 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1331 | ||
4fc688ce | 1332 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1333 | if (ret) |
1334 | return ret; | |
1335 | ||
267f0c90 | 1336 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1337 | |
c6a828d3 DV |
1338 | for (gpu_freq = dev_priv->rps.min_delay; |
1339 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1340 | gpu_freq++) { |
42c0526c BW |
1341 | ia_freq = gpu_freq; |
1342 | sandybridge_pcode_read(dev_priv, | |
1343 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1344 | &ia_freq); | |
3ebecd07 CW |
1345 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1346 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1347 | ((ia_freq >> 0) & 0xff) * 100, | |
1348 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1349 | } |
1350 | ||
4fc688ce | 1351 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
7648fa99 JB |
1356 | static int i915_gfxec(struct seq_file *m, void *unused) |
1357 | { | |
1358 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1359 | struct drm_device *dev = node->minor->dev; | |
1360 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1361 | int ret; |
1362 | ||
1363 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1364 | if (ret) | |
1365 | return ret; | |
7648fa99 JB |
1366 | |
1367 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1368 | ||
616fdb5a BW |
1369 | mutex_unlock(&dev->struct_mutex); |
1370 | ||
7648fa99 JB |
1371 | return 0; |
1372 | } | |
1373 | ||
44834a67 CW |
1374 | static int i915_opregion(struct seq_file *m, void *unused) |
1375 | { | |
1376 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1377 | struct drm_device *dev = node->minor->dev; | |
1378 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1379 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1380 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1381 | int ret; |
1382 | ||
0d38f009 DV |
1383 | if (data == NULL) |
1384 | return -ENOMEM; | |
1385 | ||
44834a67 CW |
1386 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1387 | if (ret) | |
0d38f009 | 1388 | goto out; |
44834a67 | 1389 | |
0d38f009 DV |
1390 | if (opregion->header) { |
1391 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1392 | seq_write(m, data, OPREGION_SIZE); | |
1393 | } | |
44834a67 CW |
1394 | |
1395 | mutex_unlock(&dev->struct_mutex); | |
1396 | ||
0d38f009 DV |
1397 | out: |
1398 | kfree(data); | |
44834a67 CW |
1399 | return 0; |
1400 | } | |
1401 | ||
37811fcc CW |
1402 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1403 | { | |
1404 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1405 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1406 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1407 | struct intel_framebuffer *fb; |
37811fcc | 1408 | |
4520f53a DV |
1409 | #ifdef CONFIG_DRM_I915_FBDEV |
1410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1411 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1412 | if (ret) |
1413 | return ret; | |
1414 | ||
1415 | ifbdev = dev_priv->fbdev; | |
1416 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1417 | ||
623f9783 | 1418 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1419 | fb->base.width, |
1420 | fb->base.height, | |
1421 | fb->base.depth, | |
623f9783 DV |
1422 | fb->base.bits_per_pixel, |
1423 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1424 | describe_obj(m, fb->obj); |
267f0c90 | 1425 | seq_putc(m, '\n'); |
4b096ac1 | 1426 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1427 | #endif |
37811fcc | 1428 | |
4b096ac1 | 1429 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1430 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1431 | if (&fb->base == ifbdev->helper.fb) | |
1432 | continue; | |
1433 | ||
623f9783 | 1434 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1435 | fb->base.width, |
1436 | fb->base.height, | |
1437 | fb->base.depth, | |
623f9783 DV |
1438 | fb->base.bits_per_pixel, |
1439 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1440 | describe_obj(m, fb->obj); |
267f0c90 | 1441 | seq_putc(m, '\n'); |
37811fcc | 1442 | } |
4b096ac1 | 1443 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1444 | |
1445 | return 0; | |
1446 | } | |
1447 | ||
e76d3630 BW |
1448 | static int i915_context_status(struct seq_file *m, void *unused) |
1449 | { | |
1450 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1451 | struct drm_device *dev = node->minor->dev; | |
1452 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1453 | struct intel_ring_buffer *ring; |
a33afea5 | 1454 | struct i915_hw_context *ctx; |
a168c293 | 1455 | int ret, i; |
e76d3630 BW |
1456 | |
1457 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1458 | if (ret) | |
1459 | return ret; | |
1460 | ||
3e373948 | 1461 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1462 | seq_puts(m, "power context "); |
3e373948 | 1463 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1464 | seq_putc(m, '\n'); |
dc501fbc | 1465 | } |
e76d3630 | 1466 | |
3e373948 | 1467 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1468 | seq_puts(m, "render context "); |
3e373948 | 1469 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1470 | seq_putc(m, '\n'); |
dc501fbc | 1471 | } |
e76d3630 | 1472 | |
a33afea5 BW |
1473 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1474 | seq_puts(m, "HW context "); | |
3ccfd19d | 1475 | describe_ctx(m, ctx); |
a33afea5 BW |
1476 | for_each_ring(ring, dev_priv, i) |
1477 | if (ring->default_context == ctx) | |
1478 | seq_printf(m, "(default context %s) ", ring->name); | |
1479 | ||
1480 | describe_obj(m, ctx->obj); | |
1481 | seq_putc(m, '\n'); | |
a168c293 BW |
1482 | } |
1483 | ||
e76d3630 BW |
1484 | mutex_unlock(&dev->mode_config.mutex); |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
6d794d42 BW |
1489 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1490 | { | |
1491 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1492 | struct drm_device *dev = node->minor->dev; | |
1493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1494 | unsigned forcewake_count; |
6d794d42 | 1495 | |
907b28c5 CW |
1496 | spin_lock_irq(&dev_priv->uncore.lock); |
1497 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1498 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1499 | |
9f1f46a4 | 1500 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1501 | |
1502 | return 0; | |
1503 | } | |
1504 | ||
ea16a3cd DV |
1505 | static const char *swizzle_string(unsigned swizzle) |
1506 | { | |
aee56cff | 1507 | switch (swizzle) { |
ea16a3cd DV |
1508 | case I915_BIT_6_SWIZZLE_NONE: |
1509 | return "none"; | |
1510 | case I915_BIT_6_SWIZZLE_9: | |
1511 | return "bit9"; | |
1512 | case I915_BIT_6_SWIZZLE_9_10: | |
1513 | return "bit9/bit10"; | |
1514 | case I915_BIT_6_SWIZZLE_9_11: | |
1515 | return "bit9/bit11"; | |
1516 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1517 | return "bit9/bit10/bit11"; | |
1518 | case I915_BIT_6_SWIZZLE_9_17: | |
1519 | return "bit9/bit17"; | |
1520 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1521 | return "bit9/bit10/bit17"; | |
1522 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1523 | return "unknown"; |
ea16a3cd DV |
1524 | } |
1525 | ||
1526 | return "bug"; | |
1527 | } | |
1528 | ||
1529 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1530 | { | |
1531 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1532 | struct drm_device *dev = node->minor->dev; | |
1533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1534 | int ret; |
1535 | ||
1536 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1537 | if (ret) | |
1538 | return ret; | |
ea16a3cd | 1539 | |
ea16a3cd DV |
1540 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1541 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1542 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1543 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1544 | ||
1545 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1546 | seq_printf(m, "DDC = 0x%08x\n", | |
1547 | I915_READ(DCC)); | |
1548 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1549 | I915_READ16(C0DRB3)); | |
1550 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1551 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1552 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1553 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1554 | I915_READ(MAD_DIMM_C0)); | |
1555 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1556 | I915_READ(MAD_DIMM_C1)); | |
1557 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1558 | I915_READ(MAD_DIMM_C2)); | |
1559 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1560 | I915_READ(TILECTL)); | |
1561 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1562 | I915_READ(ARB_MODE)); | |
1563 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1564 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1565 | } |
1566 | mutex_unlock(&dev->struct_mutex); | |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
3cf17fc5 DV |
1571 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1572 | { | |
1573 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1574 | struct drm_device *dev = node->minor->dev; | |
1575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1576 | struct intel_ring_buffer *ring; | |
1577 | int i, ret; | |
1578 | ||
1579 | ||
1580 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1581 | if (ret) | |
1582 | return ret; | |
1583 | if (INTEL_INFO(dev)->gen == 6) | |
1584 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1585 | ||
a2c7f6fd | 1586 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1587 | seq_printf(m, "%s\n", ring->name); |
1588 | if (INTEL_INFO(dev)->gen == 7) | |
1589 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1590 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1591 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1592 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1593 | } | |
1594 | if (dev_priv->mm.aliasing_ppgtt) { | |
1595 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1596 | ||
267f0c90 | 1597 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1598 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1599 | } | |
1600 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1601 | mutex_unlock(&dev->struct_mutex); | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
57f350b6 JB |
1606 | static int i915_dpio_info(struct seq_file *m, void *data) |
1607 | { | |
1608 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1609 | struct drm_device *dev = node->minor->dev; | |
1610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1611 | int ret; | |
1612 | ||
1613 | ||
1614 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1615 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1616 | return 0; |
1617 | } | |
1618 | ||
09153000 | 1619 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1620 | if (ret) |
1621 | return ret; | |
1622 | ||
1623 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1624 | ||
1625 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1626 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1627 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1628 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1629 | |
1630 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1631 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1632 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1633 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1634 | |
1635 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1636 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1637 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1638 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1639 | |
4abb2c39 | 1640 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1641 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1642 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1643 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1644 | |
1645 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1646 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1647 | |
09153000 | 1648 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1649 | |
1650 | return 0; | |
1651 | } | |
1652 | ||
63573eb7 BW |
1653 | static int i915_llc(struct seq_file *m, void *data) |
1654 | { | |
1655 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1656 | struct drm_device *dev = node->minor->dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | ||
1659 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1660 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1661 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
e91fd8c6 RV |
1666 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1667 | { | |
1668 | struct drm_info_node *node = m->private; | |
1669 | struct drm_device *dev = node->minor->dev; | |
1670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1671 | u32 psrperf = 0; |
1672 | bool enabled = false; | |
e91fd8c6 | 1673 | |
a031d709 RV |
1674 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1675 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1676 | |
a031d709 RV |
1677 | enabled = HAS_PSR(dev) && |
1678 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1679 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1680 | |
a031d709 RV |
1681 | if (HAS_PSR(dev)) |
1682 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1683 | EDP_PSR_PERF_CNT_MASK; | |
1684 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1685 | |
1686 | return 0; | |
1687 | } | |
1688 | ||
ec013e7f JB |
1689 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1690 | { | |
1691 | struct drm_info_node *node = m->private; | |
1692 | struct drm_device *dev = node->minor->dev; | |
1693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1694 | u64 power; | |
1695 | u32 units; | |
1696 | ||
1697 | if (INTEL_INFO(dev)->gen < 6) | |
1698 | return -ENODEV; | |
1699 | ||
1700 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1701 | power = (power & 0x1f00) >> 8; | |
1702 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1703 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1704 | power *= units; | |
1705 | ||
1706 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1707 | |
1708 | return 0; | |
1709 | } | |
1710 | ||
1711 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1712 | { | |
1713 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1714 | struct drm_device *dev = node->minor->dev; | |
1715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1716 | ||
1717 | if (!IS_HASWELL(dev)) { | |
1718 | seq_puts(m, "not supported\n"); | |
1719 | return 0; | |
1720 | } | |
1721 | ||
1722 | mutex_lock(&dev_priv->pc8.lock); | |
1723 | seq_printf(m, "Requirements met: %s\n", | |
1724 | yesno(dev_priv->pc8.requirements_met)); | |
1725 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1726 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1727 | seq_printf(m, "IRQs disabled: %s\n", | |
1728 | yesno(dev_priv->pc8.irqs_disabled)); | |
1729 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1730 | mutex_unlock(&dev_priv->pc8.lock); | |
1731 | ||
ec013e7f JB |
1732 | return 0; |
1733 | } | |
1734 | ||
8bf1e9f1 SH |
1735 | static int i915_pipe_crc(struct seq_file *m, void *data) |
1736 | { | |
1737 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1738 | struct drm_device *dev = node->minor->dev; | |
1739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1740 | enum pipe pipe = (enum pipe)node->info_ent->data; | |
1741 | const struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1742 | int i; | |
1743 | int start; | |
1744 | ||
1745 | if (!IS_IVYBRIDGE(dev)) { | |
1746 | seq_puts(m, "unsupported\n"); | |
1747 | return 0; | |
1748 | } | |
1749 | ||
1750 | start = atomic_read(&pipe_crc->slot) + 1; | |
1751 | seq_puts(m, " timestamp CRC1 CRC2 CRC3 CRC4 CRC5\n"); | |
1752 | for (i = 0; i < INTEL_PIPE_CRC_ENTRIES_NR; i++) { | |
1753 | const struct intel_pipe_crc_entry *entry = | |
1754 | &pipe_crc->entries[(start + i) % | |
1755 | INTEL_PIPE_CRC_ENTRIES_NR]; | |
1756 | ||
1757 | seq_printf(m, "%12u %8x %8x %8x %8x %8x\n", entry->timestamp, | |
1758 | entry->crc[0], entry->crc[1], entry->crc[2], | |
1759 | entry->crc[3], entry->crc[4]); | |
1760 | } | |
1761 | ||
1762 | return 0; | |
1763 | } | |
1764 | ||
647416f9 KC |
1765 | static int |
1766 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1767 | { |
647416f9 | 1768 | struct drm_device *dev = data; |
f3cd474b | 1769 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1770 | |
647416f9 | 1771 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1772 | |
647416f9 | 1773 | return 0; |
f3cd474b CW |
1774 | } |
1775 | ||
647416f9 KC |
1776 | static int |
1777 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1778 | { |
647416f9 | 1779 | struct drm_device *dev = data; |
f3cd474b | 1780 | |
647416f9 | 1781 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1782 | i915_handle_error(dev, val); |
f3cd474b | 1783 | |
647416f9 | 1784 | return 0; |
f3cd474b CW |
1785 | } |
1786 | ||
647416f9 KC |
1787 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1788 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1789 | "%llu\n"); |
f3cd474b | 1790 | |
647416f9 KC |
1791 | static int |
1792 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1793 | { |
647416f9 | 1794 | struct drm_device *dev = data; |
e5eb3d63 | 1795 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1796 | |
647416f9 | 1797 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1798 | |
647416f9 | 1799 | return 0; |
e5eb3d63 DV |
1800 | } |
1801 | ||
647416f9 KC |
1802 | static int |
1803 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1804 | { |
647416f9 | 1805 | struct drm_device *dev = data; |
e5eb3d63 | 1806 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1807 | int ret; |
e5eb3d63 | 1808 | |
647416f9 | 1809 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1810 | |
22bcfc6a DV |
1811 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1812 | if (ret) | |
1813 | return ret; | |
1814 | ||
99584db3 | 1815 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1816 | mutex_unlock(&dev->struct_mutex); |
1817 | ||
647416f9 | 1818 | return 0; |
e5eb3d63 DV |
1819 | } |
1820 | ||
647416f9 KC |
1821 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1822 | i915_ring_stop_get, i915_ring_stop_set, | |
1823 | "0x%08llx\n"); | |
d5442303 | 1824 | |
094f9a54 CW |
1825 | static int |
1826 | i915_ring_missed_irq_get(void *data, u64 *val) | |
1827 | { | |
1828 | struct drm_device *dev = data; | |
1829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1830 | ||
1831 | *val = dev_priv->gpu_error.missed_irq_rings; | |
1832 | return 0; | |
1833 | } | |
1834 | ||
1835 | static int | |
1836 | i915_ring_missed_irq_set(void *data, u64 val) | |
1837 | { | |
1838 | struct drm_device *dev = data; | |
1839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1840 | int ret; | |
1841 | ||
1842 | /* Lock against concurrent debugfs callers */ | |
1843 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1844 | if (ret) | |
1845 | return ret; | |
1846 | dev_priv->gpu_error.missed_irq_rings = val; | |
1847 | mutex_unlock(&dev->struct_mutex); | |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
1852 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
1853 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
1854 | "0x%08llx\n"); | |
1855 | ||
1856 | static int | |
1857 | i915_ring_test_irq_get(void *data, u64 *val) | |
1858 | { | |
1859 | struct drm_device *dev = data; | |
1860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1861 | ||
1862 | *val = dev_priv->gpu_error.test_irq_rings; | |
1863 | ||
1864 | return 0; | |
1865 | } | |
1866 | ||
1867 | static int | |
1868 | i915_ring_test_irq_set(void *data, u64 val) | |
1869 | { | |
1870 | struct drm_device *dev = data; | |
1871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1872 | int ret; | |
1873 | ||
1874 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
1875 | ||
1876 | /* Lock against concurrent debugfs callers */ | |
1877 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1878 | if (ret) | |
1879 | return ret; | |
1880 | ||
1881 | dev_priv->gpu_error.test_irq_rings = val; | |
1882 | mutex_unlock(&dev->struct_mutex); | |
1883 | ||
1884 | return 0; | |
1885 | } | |
1886 | ||
1887 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
1888 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
1889 | "0x%08llx\n"); | |
1890 | ||
dd624afd CW |
1891 | #define DROP_UNBOUND 0x1 |
1892 | #define DROP_BOUND 0x2 | |
1893 | #define DROP_RETIRE 0x4 | |
1894 | #define DROP_ACTIVE 0x8 | |
1895 | #define DROP_ALL (DROP_UNBOUND | \ | |
1896 | DROP_BOUND | \ | |
1897 | DROP_RETIRE | \ | |
1898 | DROP_ACTIVE) | |
647416f9 KC |
1899 | static int |
1900 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1901 | { |
647416f9 | 1902 | *val = DROP_ALL; |
dd624afd | 1903 | |
647416f9 | 1904 | return 0; |
dd624afd CW |
1905 | } |
1906 | ||
647416f9 KC |
1907 | static int |
1908 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1909 | { |
647416f9 | 1910 | struct drm_device *dev = data; |
dd624afd CW |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; |
1912 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1913 | struct i915_address_space *vm; |
1914 | struct i915_vma *vma, *x; | |
647416f9 | 1915 | int ret; |
dd624afd | 1916 | |
647416f9 | 1917 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1918 | |
1919 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1920 | * on ioctls on -EAGAIN. */ | |
1921 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1922 | if (ret) | |
1923 | return ret; | |
1924 | ||
1925 | if (val & DROP_ACTIVE) { | |
1926 | ret = i915_gpu_idle(dev); | |
1927 | if (ret) | |
1928 | goto unlock; | |
1929 | } | |
1930 | ||
1931 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1932 | i915_gem_retire_requests(dev); | |
1933 | ||
1934 | if (val & DROP_BOUND) { | |
ca191b13 BW |
1935 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1936 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
1937 | mm_list) { | |
1938 | if (vma->obj->pin_count) | |
1939 | continue; | |
1940 | ||
1941 | ret = i915_vma_unbind(vma); | |
1942 | if (ret) | |
1943 | goto unlock; | |
1944 | } | |
31a46c9c | 1945 | } |
dd624afd CW |
1946 | } |
1947 | ||
1948 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1949 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1950 | global_list) | |
dd624afd CW |
1951 | if (obj->pages_pin_count == 0) { |
1952 | ret = i915_gem_object_put_pages(obj); | |
1953 | if (ret) | |
1954 | goto unlock; | |
1955 | } | |
1956 | } | |
1957 | ||
1958 | unlock: | |
1959 | mutex_unlock(&dev->struct_mutex); | |
1960 | ||
647416f9 | 1961 | return ret; |
dd624afd CW |
1962 | } |
1963 | ||
647416f9 KC |
1964 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1965 | i915_drop_caches_get, i915_drop_caches_set, | |
1966 | "0x%08llx\n"); | |
dd624afd | 1967 | |
647416f9 KC |
1968 | static int |
1969 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1970 | { |
647416f9 | 1971 | struct drm_device *dev = data; |
358733e9 | 1972 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1973 | int ret; |
004777cb DV |
1974 | |
1975 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1976 | return -ENODEV; | |
1977 | ||
5c9669ce TR |
1978 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1979 | ||
4fc688ce | 1980 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1981 | if (ret) |
1982 | return ret; | |
358733e9 | 1983 | |
0a073b84 JB |
1984 | if (IS_VALLEYVIEW(dev)) |
1985 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1986 | dev_priv->rps.max_delay); | |
1987 | else | |
1988 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1989 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1990 | |
647416f9 | 1991 | return 0; |
358733e9 JB |
1992 | } |
1993 | ||
647416f9 KC |
1994 | static int |
1995 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1996 | { |
647416f9 | 1997 | struct drm_device *dev = data; |
358733e9 | 1998 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1999 | int ret; |
004777cb DV |
2000 | |
2001 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2002 | return -ENODEV; | |
358733e9 | 2003 | |
5c9669ce TR |
2004 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2005 | ||
647416f9 | 2006 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2007 | |
4fc688ce | 2008 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2009 | if (ret) |
2010 | return ret; | |
2011 | ||
358733e9 JB |
2012 | /* |
2013 | * Turbo will still be enabled, but won't go above the set value. | |
2014 | */ | |
0a073b84 JB |
2015 | if (IS_VALLEYVIEW(dev)) { |
2016 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2017 | dev_priv->rps.max_delay = val; | |
2018 | gen6_set_rps(dev, val); | |
2019 | } else { | |
2020 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2021 | dev_priv->rps.max_delay = val; | |
2022 | gen6_set_rps(dev, val); | |
2023 | } | |
2024 | ||
4fc688ce | 2025 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2026 | |
647416f9 | 2027 | return 0; |
358733e9 JB |
2028 | } |
2029 | ||
647416f9 KC |
2030 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2031 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2032 | "%llu\n"); |
358733e9 | 2033 | |
647416f9 KC |
2034 | static int |
2035 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2036 | { |
647416f9 | 2037 | struct drm_device *dev = data; |
1523c310 | 2038 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2039 | int ret; |
004777cb DV |
2040 | |
2041 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2042 | return -ENODEV; | |
2043 | ||
5c9669ce TR |
2044 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2045 | ||
4fc688ce | 2046 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2047 | if (ret) |
2048 | return ret; | |
1523c310 | 2049 | |
0a073b84 JB |
2050 | if (IS_VALLEYVIEW(dev)) |
2051 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2052 | dev_priv->rps.min_delay); | |
2053 | else | |
2054 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2055 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2056 | |
647416f9 | 2057 | return 0; |
1523c310 JB |
2058 | } |
2059 | ||
647416f9 KC |
2060 | static int |
2061 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2062 | { |
647416f9 | 2063 | struct drm_device *dev = data; |
1523c310 | 2064 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2065 | int ret; |
004777cb DV |
2066 | |
2067 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2068 | return -ENODEV; | |
1523c310 | 2069 | |
5c9669ce TR |
2070 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2071 | ||
647416f9 | 2072 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2073 | |
4fc688ce | 2074 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2075 | if (ret) |
2076 | return ret; | |
2077 | ||
1523c310 JB |
2078 | /* |
2079 | * Turbo will still be enabled, but won't go below the set value. | |
2080 | */ | |
0a073b84 JB |
2081 | if (IS_VALLEYVIEW(dev)) { |
2082 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2083 | dev_priv->rps.min_delay = val; | |
2084 | valleyview_set_rps(dev, val); | |
2085 | } else { | |
2086 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2087 | dev_priv->rps.min_delay = val; | |
2088 | gen6_set_rps(dev, val); | |
2089 | } | |
4fc688ce | 2090 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2091 | |
647416f9 | 2092 | return 0; |
1523c310 JB |
2093 | } |
2094 | ||
647416f9 KC |
2095 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2096 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2097 | "%llu\n"); |
1523c310 | 2098 | |
647416f9 KC |
2099 | static int |
2100 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2101 | { |
647416f9 | 2102 | struct drm_device *dev = data; |
07b7ddd9 | 2103 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2104 | u32 snpcr; |
647416f9 | 2105 | int ret; |
07b7ddd9 | 2106 | |
004777cb DV |
2107 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2108 | return -ENODEV; | |
2109 | ||
22bcfc6a DV |
2110 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2111 | if (ret) | |
2112 | return ret; | |
2113 | ||
07b7ddd9 JB |
2114 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2115 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2116 | ||
647416f9 | 2117 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2118 | |
647416f9 | 2119 | return 0; |
07b7ddd9 JB |
2120 | } |
2121 | ||
647416f9 KC |
2122 | static int |
2123 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2124 | { |
647416f9 | 2125 | struct drm_device *dev = data; |
07b7ddd9 | 2126 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2127 | u32 snpcr; |
07b7ddd9 | 2128 | |
004777cb DV |
2129 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2130 | return -ENODEV; | |
2131 | ||
647416f9 | 2132 | if (val > 3) |
07b7ddd9 JB |
2133 | return -EINVAL; |
2134 | ||
647416f9 | 2135 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2136 | |
2137 | /* Update the cache sharing policy here as well */ | |
2138 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2139 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2140 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2141 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2142 | ||
647416f9 | 2143 | return 0; |
07b7ddd9 JB |
2144 | } |
2145 | ||
647416f9 KC |
2146 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2147 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2148 | "%llu\n"); | |
07b7ddd9 | 2149 | |
f3cd474b CW |
2150 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2151 | * allocated we need to hook into the minor for release. */ | |
2152 | static int | |
2153 | drm_add_fake_info_node(struct drm_minor *minor, | |
2154 | struct dentry *ent, | |
2155 | const void *key) | |
2156 | { | |
2157 | struct drm_info_node *node; | |
2158 | ||
b14c5679 | 2159 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
f3cd474b CW |
2160 | if (node == NULL) { |
2161 | debugfs_remove(ent); | |
2162 | return -ENOMEM; | |
2163 | } | |
2164 | ||
2165 | node->minor = minor; | |
2166 | node->dent = ent; | |
2167 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2168 | |
2169 | mutex_lock(&minor->debugfs_lock); | |
2170 | list_add(&node->list, &minor->debugfs_list); | |
2171 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2172 | |
2173 | return 0; | |
2174 | } | |
2175 | ||
6d794d42 BW |
2176 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2177 | { | |
2178 | struct drm_device *dev = inode->i_private; | |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2180 | |
075edca4 | 2181 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2182 | return 0; |
2183 | ||
6d794d42 | 2184 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2185 | |
2186 | return 0; | |
2187 | } | |
2188 | ||
c43b5634 | 2189 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2190 | { |
2191 | struct drm_device *dev = inode->i_private; | |
2192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2193 | ||
075edca4 | 2194 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2195 | return 0; |
2196 | ||
6d794d42 | 2197 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2198 | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | static const struct file_operations i915_forcewake_fops = { | |
2203 | .owner = THIS_MODULE, | |
2204 | .open = i915_forcewake_open, | |
2205 | .release = i915_forcewake_release, | |
2206 | }; | |
2207 | ||
2208 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2209 | { | |
2210 | struct drm_device *dev = minor->dev; | |
2211 | struct dentry *ent; | |
2212 | ||
2213 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2214 | S_IRUSR, |
6d794d42 BW |
2215 | root, dev, |
2216 | &i915_forcewake_fops); | |
2217 | if (IS_ERR(ent)) | |
2218 | return PTR_ERR(ent); | |
2219 | ||
8eb57294 | 2220 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2221 | } |
2222 | ||
6a9c308d DV |
2223 | static int i915_debugfs_create(struct dentry *root, |
2224 | struct drm_minor *minor, | |
2225 | const char *name, | |
2226 | const struct file_operations *fops) | |
07b7ddd9 JB |
2227 | { |
2228 | struct drm_device *dev = minor->dev; | |
2229 | struct dentry *ent; | |
2230 | ||
6a9c308d | 2231 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2232 | S_IRUGO | S_IWUSR, |
2233 | root, dev, | |
6a9c308d | 2234 | fops); |
07b7ddd9 JB |
2235 | if (IS_ERR(ent)) |
2236 | return PTR_ERR(ent); | |
2237 | ||
6a9c308d | 2238 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2239 | } |
2240 | ||
27c202ad | 2241 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2242 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2243 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2244 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2245 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2246 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2247 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2248 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2249 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2250 | {"i915_gem_request", i915_gem_request_info, 0}, |
2251 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2252 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2253 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2254 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2255 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2256 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2257 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2258 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2259 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2260 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2261 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2262 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2263 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2264 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2265 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2266 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2267 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2268 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2269 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2270 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2271 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2272 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2273 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2274 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2275 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2276 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2277 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2278 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2279 | {"i915_pc8_status", i915_pc8_status, 0}, |
8bf1e9f1 SH |
2280 | {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A}, |
2281 | {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B}, | |
2282 | {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C}, | |
2017263e | 2283 | }; |
27c202ad | 2284 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2285 | |
2b4bd0e0 | 2286 | static struct i915_debugfs_files { |
34b9674c DV |
2287 | const char *name; |
2288 | const struct file_operations *fops; | |
2289 | } i915_debugfs_files[] = { | |
2290 | {"i915_wedged", &i915_wedged_fops}, | |
2291 | {"i915_max_freq", &i915_max_freq_fops}, | |
2292 | {"i915_min_freq", &i915_min_freq_fops}, | |
2293 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2294 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
2295 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
2296 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
2297 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
2298 | {"i915_error_state", &i915_error_state_fops}, | |
2299 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2300 | }; | |
2301 | ||
27c202ad | 2302 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2303 | { |
34b9674c | 2304 | int ret, i; |
f3cd474b | 2305 | |
6d794d42 | 2306 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2307 | if (ret) |
2308 | return ret; | |
6a9c308d | 2309 | |
34b9674c DV |
2310 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2311 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2312 | i915_debugfs_files[i].name, | |
2313 | i915_debugfs_files[i].fops); | |
2314 | if (ret) | |
2315 | return ret; | |
2316 | } | |
40633219 | 2317 | |
27c202ad BG |
2318 | return drm_debugfs_create_files(i915_debugfs_list, |
2319 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2320 | minor->debugfs_root, minor); |
2321 | } | |
2322 | ||
27c202ad | 2323 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2324 | { |
34b9674c DV |
2325 | int i; |
2326 | ||
27c202ad BG |
2327 | drm_debugfs_remove_files(i915_debugfs_list, |
2328 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2329 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2330 | 1, minor); | |
34b9674c DV |
2331 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2332 | struct drm_info_list *info_list = | |
2333 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2334 | ||
2335 | drm_debugfs_remove_files(info_list, 1, minor); | |
2336 | } | |
2017263e BG |
2337 | } |
2338 | ||
2339 | #endif /* CONFIG_DEBUG_FS */ |