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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
6d2b8885 | 33 | #include <linux/list_sort.h> |
760285e7 | 34 | #include <drm/drmP.h> |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
2017263e BG |
38 | #include "i915_drv.h" |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
56 | static int i915_capabilities(struct seq_file *m, void *data) | |
57 | { | |
58 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
59 | struct drm_device *dev = node->minor->dev; | |
60 | const struct intel_device_info *info = INTEL_INFO(dev); | |
61 | ||
62 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 63 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
65 | #define SEP_SEMICOLON ; | |
66 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
67 | #undef PRINT_FLAG | |
68 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
69 | |
70 | return 0; | |
71 | } | |
2017263e | 72 | |
05394f39 | 73 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 74 | { |
05394f39 | 75 | if (obj->user_pin_count > 0) |
a6172a80 | 76 | return "P"; |
05394f39 | 77 | else if (obj->pin_count > 0) |
a6172a80 CW |
78 | return "p"; |
79 | else | |
80 | return " "; | |
81 | } | |
82 | ||
05394f39 | 83 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 84 | { |
0206e353 AJ |
85 | switch (obj->tiling_mode) { |
86 | default: | |
87 | case I915_TILING_NONE: return " "; | |
88 | case I915_TILING_X: return "X"; | |
89 | case I915_TILING_Y: return "Y"; | |
90 | } | |
a6172a80 CW |
91 | } |
92 | ||
1d693bcc BW |
93 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
94 | { | |
95 | return obj->has_global_gtt_mapping ? "g" : " "; | |
96 | } | |
97 | ||
37811fcc CW |
98 | static void |
99 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
100 | { | |
1d693bcc BW |
101 | struct i915_vma *vma; |
102 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %d %d %d%s%s%s", | |
37811fcc CW |
103 | &obj->base, |
104 | get_pin_flag(obj), | |
105 | get_tiling_flag(obj), | |
1d693bcc | 106 | get_global_flag(obj), |
a05a5862 | 107 | obj->base.size / 1024, |
37811fcc CW |
108 | obj->base.read_domains, |
109 | obj->base.write_domain, | |
0201f1ec CW |
110 | obj->last_read_seqno, |
111 | obj->last_write_seqno, | |
caea7476 | 112 | obj->last_fenced_seqno, |
84734a04 | 113 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
114 | obj->dirty ? " dirty" : "", |
115 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
116 | if (obj->base.name) | |
117 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
118 | if (obj->pin_count) |
119 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
120 | if (obj->pin_display) |
121 | seq_printf(m, " (display)"); | |
37811fcc CW |
122 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
123 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
124 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
125 | if (!i915_is_ggtt(vma->vm)) | |
126 | seq_puts(m, " (pp"); | |
127 | else | |
128 | seq_puts(m, " (g"); | |
129 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
130 | vma->node.start, vma->node.size); | |
131 | } | |
c1ad11fc CW |
132 | if (obj->stolen) |
133 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
134 | if (obj->pin_mappable || obj->fault_mappable) { |
135 | char s[3], *t = s; | |
136 | if (obj->pin_mappable) | |
137 | *t++ = 'p'; | |
138 | if (obj->fault_mappable) | |
139 | *t++ = 'f'; | |
140 | *t = '\0'; | |
141 | seq_printf(m, " (%s mappable)", s); | |
142 | } | |
69dc4987 CW |
143 | if (obj->ring != NULL) |
144 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
145 | } |
146 | ||
433e12f7 | 147 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
148 | { |
149 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
150 | uintptr_t list = (uintptr_t) node->info_ent->data; |
151 | struct list_head *head; | |
2017263e | 152 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
153 | struct drm_i915_private *dev_priv = dev->dev_private; |
154 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 155 | struct i915_vma *vma; |
8f2480fb CW |
156 | size_t total_obj_size, total_gtt_size; |
157 | int count, ret; | |
de227ef0 CW |
158 | |
159 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
160 | if (ret) | |
161 | return ret; | |
2017263e | 162 | |
ca191b13 | 163 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
164 | switch (list) { |
165 | case ACTIVE_LIST: | |
267f0c90 | 166 | seq_puts(m, "Active:\n"); |
5cef07e1 | 167 | head = &vm->active_list; |
433e12f7 BG |
168 | break; |
169 | case INACTIVE_LIST: | |
267f0c90 | 170 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 171 | head = &vm->inactive_list; |
433e12f7 | 172 | break; |
433e12f7 | 173 | default: |
de227ef0 CW |
174 | mutex_unlock(&dev->struct_mutex); |
175 | return -EINVAL; | |
2017263e | 176 | } |
2017263e | 177 | |
8f2480fb | 178 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
179 | list_for_each_entry(vma, head, mm_list) { |
180 | seq_printf(m, " "); | |
181 | describe_obj(m, vma->obj); | |
182 | seq_printf(m, "\n"); | |
183 | total_obj_size += vma->obj->base.size; | |
184 | total_gtt_size += vma->node.size; | |
8f2480fb | 185 | count++; |
2017263e | 186 | } |
de227ef0 | 187 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 188 | |
8f2480fb CW |
189 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
190 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
191 | return 0; |
192 | } | |
193 | ||
6d2b8885 CW |
194 | static int obj_rank_by_stolen(void *priv, |
195 | struct list_head *A, struct list_head *B) | |
196 | { | |
197 | struct drm_i915_gem_object *a = | |
198 | container_of(A, struct drm_i915_gem_object, exec_list); | |
199 | struct drm_i915_gem_object *b = | |
200 | container_of(B, struct drm_i915_gem_object, exec_list); | |
201 | ||
202 | return a->stolen->start - b->stolen->start; | |
203 | } | |
204 | ||
205 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
206 | { | |
207 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
208 | struct drm_device *dev = node->minor->dev; | |
209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
210 | struct drm_i915_gem_object *obj; | |
211 | size_t total_obj_size, total_gtt_size; | |
212 | LIST_HEAD(stolen); | |
213 | int count, ret; | |
214 | ||
215 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
216 | if (ret) | |
217 | return ret; | |
218 | ||
219 | total_obj_size = total_gtt_size = count = 0; | |
220 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
221 | if (obj->stolen == NULL) | |
222 | continue; | |
223 | ||
224 | list_add(&obj->exec_list, &stolen); | |
225 | ||
226 | total_obj_size += obj->base.size; | |
227 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
228 | count++; | |
229 | } | |
230 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
231 | if (obj->stolen == NULL) | |
232 | continue; | |
233 | ||
234 | list_add(&obj->exec_list, &stolen); | |
235 | ||
236 | total_obj_size += obj->base.size; | |
237 | count++; | |
238 | } | |
239 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
240 | seq_puts(m, "Stolen:\n"); | |
241 | while (!list_empty(&stolen)) { | |
242 | obj = list_first_entry(&stolen, typeof(*obj), exec_list); | |
243 | seq_puts(m, " "); | |
244 | describe_obj(m, obj); | |
245 | seq_putc(m, '\n'); | |
246 | list_del_init(&obj->exec_list); | |
247 | } | |
248 | mutex_unlock(&dev->struct_mutex); | |
249 | ||
250 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
251 | count, total_obj_size, total_gtt_size); | |
252 | return 0; | |
253 | } | |
254 | ||
6299f992 CW |
255 | #define count_objects(list, member) do { \ |
256 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 257 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
258 | ++count; \ |
259 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 260 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
261 | ++mappable_count; \ |
262 | } \ | |
263 | } \ | |
0206e353 | 264 | } while (0) |
6299f992 | 265 | |
2db8e9d6 CW |
266 | struct file_stats { |
267 | int count; | |
268 | size_t total, active, inactive, unbound; | |
269 | }; | |
270 | ||
271 | static int per_file_stats(int id, void *ptr, void *data) | |
272 | { | |
273 | struct drm_i915_gem_object *obj = ptr; | |
274 | struct file_stats *stats = data; | |
275 | ||
276 | stats->count++; | |
277 | stats->total += obj->base.size; | |
278 | ||
f343c5f6 | 279 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
280 | if (!list_empty(&obj->ring_list)) |
281 | stats->active += obj->base.size; | |
282 | else | |
283 | stats->inactive += obj->base.size; | |
284 | } else { | |
285 | if (!list_empty(&obj->global_list)) | |
286 | stats->unbound += obj->base.size; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
ca191b13 BW |
292 | #define count_vmas(list, member) do { \ |
293 | list_for_each_entry(vma, list, member) { \ | |
294 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
295 | ++count; \ | |
296 | if (vma->obj->map_and_fenceable) { \ | |
297 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
298 | ++mappable_count; \ | |
299 | } \ | |
300 | } \ | |
301 | } while (0) | |
302 | ||
303 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
304 | { |
305 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
306 | struct drm_device *dev = node->minor->dev; | |
307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
308 | u32 count, mappable_count, purgeable_count; |
309 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 310 | struct drm_i915_gem_object *obj; |
5cef07e1 | 311 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 312 | struct drm_file *file; |
ca191b13 | 313 | struct i915_vma *vma; |
73aa808f CW |
314 | int ret; |
315 | ||
316 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
317 | if (ret) | |
318 | return ret; | |
319 | ||
6299f992 CW |
320 | seq_printf(m, "%u objects, %zu bytes\n", |
321 | dev_priv->mm.object_count, | |
322 | dev_priv->mm.object_memory); | |
323 | ||
324 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 325 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
326 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
327 | count, mappable_count, size, mappable_size); | |
328 | ||
329 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 330 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
331 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
332 | count, mappable_count, size, mappable_size); | |
333 | ||
6299f992 | 334 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 335 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
336 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
337 | count, mappable_count, size, mappable_size); | |
338 | ||
b7abb714 | 339 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 340 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 341 | size += obj->base.size, ++count; |
b7abb714 CW |
342 | if (obj->madv == I915_MADV_DONTNEED) |
343 | purgeable_size += obj->base.size, ++purgeable_count; | |
344 | } | |
6c085a72 CW |
345 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
346 | ||
6299f992 | 347 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 348 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 349 | if (obj->fault_mappable) { |
f343c5f6 | 350 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
351 | ++count; |
352 | } | |
353 | if (obj->pin_mappable) { | |
f343c5f6 | 354 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
355 | ++mappable_count; |
356 | } | |
b7abb714 CW |
357 | if (obj->madv == I915_MADV_DONTNEED) { |
358 | purgeable_size += obj->base.size; | |
359 | ++purgeable_count; | |
360 | } | |
6299f992 | 361 | } |
b7abb714 CW |
362 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
363 | purgeable_count, purgeable_size); | |
6299f992 CW |
364 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
365 | mappable_count, mappable_size); | |
366 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
367 | count, size); | |
368 | ||
93d18799 | 369 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
370 | dev_priv->gtt.base.total, |
371 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 372 | |
267f0c90 | 373 | seq_putc(m, '\n'); |
2db8e9d6 CW |
374 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
375 | struct file_stats stats; | |
376 | ||
377 | memset(&stats, 0, sizeof(stats)); | |
378 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
379 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
380 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
381 | stats.count, | |
382 | stats.total, | |
383 | stats.active, | |
384 | stats.inactive, | |
385 | stats.unbound); | |
386 | } | |
387 | ||
73aa808f CW |
388 | mutex_unlock(&dev->struct_mutex); |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
aee56cff | 393 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
394 | { |
395 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
396 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 397 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
398 | struct drm_i915_private *dev_priv = dev->dev_private; |
399 | struct drm_i915_gem_object *obj; | |
400 | size_t total_obj_size, total_gtt_size; | |
401 | int count, ret; | |
402 | ||
403 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
404 | if (ret) | |
405 | return ret; | |
406 | ||
407 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 408 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
409 | if (list == PINNED_LIST && obj->pin_count == 0) |
410 | continue; | |
411 | ||
267f0c90 | 412 | seq_puts(m, " "); |
08c18323 | 413 | describe_obj(m, obj); |
267f0c90 | 414 | seq_putc(m, '\n'); |
08c18323 | 415 | total_obj_size += obj->base.size; |
f343c5f6 | 416 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
417 | count++; |
418 | } | |
419 | ||
420 | mutex_unlock(&dev->struct_mutex); | |
421 | ||
422 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
423 | count, total_obj_size, total_gtt_size); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
4e5359cd SF |
428 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
429 | { | |
430 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
431 | struct drm_device *dev = node->minor->dev; | |
432 | unsigned long flags; | |
433 | struct intel_crtc *crtc; | |
434 | ||
435 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
436 | const char pipe = pipe_name(crtc->pipe); |
437 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
438 | struct intel_unpin_work *work; |
439 | ||
440 | spin_lock_irqsave(&dev->event_lock, flags); | |
441 | work = crtc->unpin_work; | |
442 | if (work == NULL) { | |
9db4a9c7 | 443 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
444 | pipe, plane); |
445 | } else { | |
e7d841ca | 446 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 447 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
448 | pipe, plane); |
449 | } else { | |
9db4a9c7 | 450 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
451 | pipe, plane); |
452 | } | |
453 | if (work->enable_stall_check) | |
267f0c90 | 454 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 455 | else |
267f0c90 | 456 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 457 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
458 | |
459 | if (work->old_fb_obj) { | |
05394f39 CW |
460 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
461 | if (obj) | |
f343c5f6 BW |
462 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
463 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
464 | } |
465 | if (work->pending_flip_obj) { | |
05394f39 CW |
466 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
467 | if (obj) | |
f343c5f6 BW |
468 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
469 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
470 | } |
471 | } | |
472 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
2017263e BG |
478 | static int i915_gem_request_info(struct seq_file *m, void *data) |
479 | { | |
480 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
481 | struct drm_device *dev = node->minor->dev; | |
482 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 483 | struct intel_ring_buffer *ring; |
2017263e | 484 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 485 | int ret, count, i; |
de227ef0 CW |
486 | |
487 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
488 | if (ret) | |
489 | return ret; | |
2017263e | 490 | |
c2c347a9 | 491 | count = 0; |
a2c7f6fd CW |
492 | for_each_ring(ring, dev_priv, i) { |
493 | if (list_empty(&ring->request_list)) | |
494 | continue; | |
495 | ||
496 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 497 | list_for_each_entry(gem_request, |
a2c7f6fd | 498 | &ring->request_list, |
c2c347a9 CW |
499 | list) { |
500 | seq_printf(m, " %d @ %d\n", | |
501 | gem_request->seqno, | |
502 | (int) (jiffies - gem_request->emitted_jiffies)); | |
503 | } | |
504 | count++; | |
2017263e | 505 | } |
de227ef0 CW |
506 | mutex_unlock(&dev->struct_mutex); |
507 | ||
c2c347a9 | 508 | if (count == 0) |
267f0c90 | 509 | seq_puts(m, "No requests\n"); |
c2c347a9 | 510 | |
2017263e BG |
511 | return 0; |
512 | } | |
513 | ||
b2223497 CW |
514 | static void i915_ring_seqno_info(struct seq_file *m, |
515 | struct intel_ring_buffer *ring) | |
516 | { | |
517 | if (ring->get_seqno) { | |
43a7b924 | 518 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 519 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
520 | } |
521 | } | |
522 | ||
2017263e BG |
523 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
524 | { | |
525 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
526 | struct drm_device *dev = node->minor->dev; | |
527 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 528 | struct intel_ring_buffer *ring; |
1ec14ad3 | 529 | int ret, i; |
de227ef0 CW |
530 | |
531 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
532 | if (ret) | |
533 | return ret; | |
2017263e | 534 | |
a2c7f6fd CW |
535 | for_each_ring(ring, dev_priv, i) |
536 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
537 | |
538 | mutex_unlock(&dev->struct_mutex); | |
539 | ||
2017263e BG |
540 | return 0; |
541 | } | |
542 | ||
543 | ||
544 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
545 | { | |
546 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
547 | struct drm_device *dev = node->minor->dev; | |
548 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 549 | struct intel_ring_buffer *ring; |
9db4a9c7 | 550 | int ret, i, pipe; |
de227ef0 CW |
551 | |
552 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
553 | if (ret) | |
554 | return ret; | |
2017263e | 555 | |
7e231dbe JB |
556 | if (IS_VALLEYVIEW(dev)) { |
557 | seq_printf(m, "Display IER:\t%08x\n", | |
558 | I915_READ(VLV_IER)); | |
559 | seq_printf(m, "Display IIR:\t%08x\n", | |
560 | I915_READ(VLV_IIR)); | |
561 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
562 | I915_READ(VLV_IIR_RW)); | |
563 | seq_printf(m, "Display IMR:\t%08x\n", | |
564 | I915_READ(VLV_IMR)); | |
565 | for_each_pipe(pipe) | |
566 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
567 | pipe_name(pipe), | |
568 | I915_READ(PIPESTAT(pipe))); | |
569 | ||
570 | seq_printf(m, "Master IER:\t%08x\n", | |
571 | I915_READ(VLV_MASTER_IER)); | |
572 | ||
573 | seq_printf(m, "Render IER:\t%08x\n", | |
574 | I915_READ(GTIER)); | |
575 | seq_printf(m, "Render IIR:\t%08x\n", | |
576 | I915_READ(GTIIR)); | |
577 | seq_printf(m, "Render IMR:\t%08x\n", | |
578 | I915_READ(GTIMR)); | |
579 | ||
580 | seq_printf(m, "PM IER:\t\t%08x\n", | |
581 | I915_READ(GEN6_PMIER)); | |
582 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
583 | I915_READ(GEN6_PMIIR)); | |
584 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
585 | I915_READ(GEN6_PMIMR)); | |
586 | ||
587 | seq_printf(m, "Port hotplug:\t%08x\n", | |
588 | I915_READ(PORT_HOTPLUG_EN)); | |
589 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
590 | I915_READ(VLV_DPFLIPSTAT)); | |
591 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
592 | I915_READ(DPINVGTT)); | |
593 | ||
594 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
595 | seq_printf(m, "Interrupt enable: %08x\n", |
596 | I915_READ(IER)); | |
597 | seq_printf(m, "Interrupt identity: %08x\n", | |
598 | I915_READ(IIR)); | |
599 | seq_printf(m, "Interrupt mask: %08x\n", | |
600 | I915_READ(IMR)); | |
9db4a9c7 JB |
601 | for_each_pipe(pipe) |
602 | seq_printf(m, "Pipe %c stat: %08x\n", | |
603 | pipe_name(pipe), | |
604 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
605 | } else { |
606 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
607 | I915_READ(DEIER)); | |
608 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
609 | I915_READ(DEIIR)); | |
610 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
611 | I915_READ(DEIMR)); | |
612 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
613 | I915_READ(SDEIER)); | |
614 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
615 | I915_READ(SDEIIR)); | |
616 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
617 | I915_READ(SDEIMR)); | |
618 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
619 | I915_READ(GTIER)); | |
620 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
621 | I915_READ(GTIIR)); | |
622 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
623 | I915_READ(GTIMR)); | |
624 | } | |
2017263e BG |
625 | seq_printf(m, "Interrupts received: %d\n", |
626 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 627 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 628 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
629 | seq_printf(m, |
630 | "Graphics Interrupt mask (%s): %08x\n", | |
631 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 632 | } |
a2c7f6fd | 633 | i915_ring_seqno_info(m, ring); |
9862e600 | 634 | } |
de227ef0 CW |
635 | mutex_unlock(&dev->struct_mutex); |
636 | ||
2017263e BG |
637 | return 0; |
638 | } | |
639 | ||
a6172a80 CW |
640 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
641 | { | |
642 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
643 | struct drm_device *dev = node->minor->dev; | |
644 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
645 | int i, ret; |
646 | ||
647 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
648 | if (ret) | |
649 | return ret; | |
a6172a80 CW |
650 | |
651 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
652 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
653 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 654 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 655 | |
6c085a72 CW |
656 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
657 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 658 | if (obj == NULL) |
267f0c90 | 659 | seq_puts(m, "unused"); |
c2c347a9 | 660 | else |
05394f39 | 661 | describe_obj(m, obj); |
267f0c90 | 662 | seq_putc(m, '\n'); |
a6172a80 CW |
663 | } |
664 | ||
05394f39 | 665 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
666 | return 0; |
667 | } | |
668 | ||
2017263e BG |
669 | static int i915_hws_info(struct seq_file *m, void *data) |
670 | { | |
671 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
672 | struct drm_device *dev = node->minor->dev; | |
673 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 674 | struct intel_ring_buffer *ring; |
1a240d4d | 675 | const u32 *hws; |
4066c0ae CW |
676 | int i; |
677 | ||
1ec14ad3 | 678 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 679 | hws = ring->status_page.page_addr; |
2017263e BG |
680 | if (hws == NULL) |
681 | return 0; | |
682 | ||
683 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
684 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
685 | i * 4, | |
686 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
687 | } | |
688 | return 0; | |
689 | } | |
690 | ||
d5442303 DV |
691 | static ssize_t |
692 | i915_error_state_write(struct file *filp, | |
693 | const char __user *ubuf, | |
694 | size_t cnt, | |
695 | loff_t *ppos) | |
696 | { | |
edc3d884 | 697 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 698 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 699 | int ret; |
d5442303 DV |
700 | |
701 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
702 | ||
22bcfc6a DV |
703 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
704 | if (ret) | |
705 | return ret; | |
706 | ||
d5442303 DV |
707 | i915_destroy_error_state(dev); |
708 | mutex_unlock(&dev->struct_mutex); | |
709 | ||
710 | return cnt; | |
711 | } | |
712 | ||
713 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
714 | { | |
715 | struct drm_device *dev = inode->i_private; | |
d5442303 | 716 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
717 | |
718 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
719 | if (!error_priv) | |
720 | return -ENOMEM; | |
721 | ||
722 | error_priv->dev = dev; | |
723 | ||
95d5bfb3 | 724 | i915_error_state_get(dev, error_priv); |
d5442303 | 725 | |
edc3d884 MK |
726 | file->private_data = error_priv; |
727 | ||
728 | return 0; | |
d5442303 DV |
729 | } |
730 | ||
731 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
732 | { | |
edc3d884 | 733 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 734 | |
95d5bfb3 | 735 | i915_error_state_put(error_priv); |
d5442303 DV |
736 | kfree(error_priv); |
737 | ||
edc3d884 MK |
738 | return 0; |
739 | } | |
740 | ||
4dc955f7 MK |
741 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
742 | size_t count, loff_t *pos) | |
743 | { | |
744 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
745 | struct drm_i915_error_state_buf error_str; | |
746 | loff_t tmp_pos = 0; | |
747 | ssize_t ret_count = 0; | |
748 | int ret; | |
749 | ||
750 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
751 | if (ret) | |
752 | return ret; | |
edc3d884 | 753 | |
fc16b48b | 754 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
755 | if (ret) |
756 | goto out; | |
757 | ||
edc3d884 MK |
758 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
759 | error_str.buf, | |
760 | error_str.bytes); | |
761 | ||
762 | if (ret_count < 0) | |
763 | ret = ret_count; | |
764 | else | |
765 | *pos = error_str.start + ret_count; | |
766 | out: | |
4dc955f7 | 767 | i915_error_state_buf_release(&error_str); |
edc3d884 | 768 | return ret ?: ret_count; |
d5442303 DV |
769 | } |
770 | ||
771 | static const struct file_operations i915_error_state_fops = { | |
772 | .owner = THIS_MODULE, | |
773 | .open = i915_error_state_open, | |
edc3d884 | 774 | .read = i915_error_state_read, |
d5442303 DV |
775 | .write = i915_error_state_write, |
776 | .llseek = default_llseek, | |
777 | .release = i915_error_state_release, | |
778 | }; | |
779 | ||
647416f9 KC |
780 | static int |
781 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 782 | { |
647416f9 | 783 | struct drm_device *dev = data; |
40633219 | 784 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
785 | int ret; |
786 | ||
787 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
788 | if (ret) | |
789 | return ret; | |
790 | ||
647416f9 | 791 | *val = dev_priv->next_seqno; |
40633219 MK |
792 | mutex_unlock(&dev->struct_mutex); |
793 | ||
647416f9 | 794 | return 0; |
40633219 MK |
795 | } |
796 | ||
647416f9 KC |
797 | static int |
798 | i915_next_seqno_set(void *data, u64 val) | |
799 | { | |
800 | struct drm_device *dev = data; | |
40633219 MK |
801 | int ret; |
802 | ||
40633219 MK |
803 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
804 | if (ret) | |
805 | return ret; | |
806 | ||
e94fbaa8 | 807 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
808 | mutex_unlock(&dev->struct_mutex); |
809 | ||
647416f9 | 810 | return ret; |
40633219 MK |
811 | } |
812 | ||
647416f9 KC |
813 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
814 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 815 | "0x%llx\n"); |
40633219 | 816 | |
f97108d1 JB |
817 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
818 | { | |
819 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
820 | struct drm_device *dev = node->minor->dev; | |
821 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
822 | u16 crstanddelay; |
823 | int ret; | |
824 | ||
825 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
826 | if (ret) | |
827 | return ret; | |
828 | ||
829 | crstanddelay = I915_READ16(CRSTANDVID); | |
830 | ||
831 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
832 | |
833 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
838 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
839 | { | |
840 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
841 | struct drm_device *dev = node->minor->dev; | |
842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 843 | int ret; |
3b8d8d91 JB |
844 | |
845 | if (IS_GEN5(dev)) { | |
846 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
847 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
848 | ||
849 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
850 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
851 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
852 | MEMSTAT_VID_SHIFT); | |
853 | seq_printf(m, "Current P-state: %d\n", | |
854 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 855 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
856 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
857 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
858 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 859 | u32 rpstat, cagf; |
ccab5c82 JB |
860 | u32 rpupei, rpcurup, rpprevup; |
861 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
862 | int max_freq; |
863 | ||
864 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
865 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
866 | if (ret) | |
867 | return ret; | |
868 | ||
fcca7926 | 869 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 870 | |
ccab5c82 JB |
871 | rpstat = I915_READ(GEN6_RPSTAT1); |
872 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
873 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
874 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
875 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
876 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
877 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
878 | if (IS_HASWELL(dev)) |
879 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
880 | else | |
881 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
882 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 883 | |
d1ebd816 BW |
884 | gen6_gt_force_wake_put(dev_priv); |
885 | mutex_unlock(&dev->struct_mutex); | |
886 | ||
3b8d8d91 | 887 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 888 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
889 | seq_printf(m, "Render p-state ratio: %d\n", |
890 | (gt_perf_status & 0xff00) >> 8); | |
891 | seq_printf(m, "Render p-state VID: %d\n", | |
892 | gt_perf_status & 0xff); | |
893 | seq_printf(m, "Render p-state limit: %d\n", | |
894 | rp_state_limits & 0xff); | |
f82855d3 | 895 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
896 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
897 | GEN6_CURICONT_MASK); | |
898 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
899 | GEN6_CURBSYTAVG_MASK); | |
900 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
901 | GEN6_CURBSYTAVG_MASK); | |
902 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
903 | GEN6_CURIAVG_MASK); | |
904 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
905 | GEN6_CURBSYTAVG_MASK); | |
906 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
907 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
908 | |
909 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
910 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 911 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
912 | |
913 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
914 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 915 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
916 | |
917 | max_freq = rp_state_cap & 0xff; | |
918 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 919 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
920 | |
921 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
922 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
923 | } else if (IS_VALLEYVIEW(dev)) { |
924 | u32 freq_sts, val; | |
925 | ||
259bd5d4 | 926 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 927 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
928 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
929 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
930 | ||
64936258 | 931 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
932 | seq_printf(m, "max GPU freq: %d MHz\n", |
933 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
934 | ||
64936258 | 935 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
936 | seq_printf(m, "min GPU freq: %d MHz\n", |
937 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
938 | ||
939 | seq_printf(m, "current GPU freq: %d MHz\n", | |
940 | vlv_gpu_freq(dev_priv->mem_freq, | |
941 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 942 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 943 | } else { |
267f0c90 | 944 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 945 | } |
f97108d1 JB |
946 | |
947 | return 0; | |
948 | } | |
949 | ||
950 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
951 | { | |
952 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
953 | struct drm_device *dev = node->minor->dev; | |
954 | drm_i915_private_t *dev_priv = dev->dev_private; | |
955 | u32 delayfreq; | |
616fdb5a BW |
956 | int ret, i; |
957 | ||
958 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
959 | if (ret) | |
960 | return ret; | |
f97108d1 JB |
961 | |
962 | for (i = 0; i < 16; i++) { | |
963 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
964 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
965 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
966 | } |
967 | ||
616fdb5a BW |
968 | mutex_unlock(&dev->struct_mutex); |
969 | ||
f97108d1 JB |
970 | return 0; |
971 | } | |
972 | ||
973 | static inline int MAP_TO_MV(int map) | |
974 | { | |
975 | return 1250 - (map * 25); | |
976 | } | |
977 | ||
978 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
979 | { | |
980 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
981 | struct drm_device *dev = node->minor->dev; | |
982 | drm_i915_private_t *dev_priv = dev->dev_private; | |
983 | u32 inttoext; | |
616fdb5a BW |
984 | int ret, i; |
985 | ||
986 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
987 | if (ret) | |
988 | return ret; | |
f97108d1 JB |
989 | |
990 | for (i = 1; i <= 32; i++) { | |
991 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
992 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
993 | } | |
994 | ||
616fdb5a BW |
995 | mutex_unlock(&dev->struct_mutex); |
996 | ||
f97108d1 JB |
997 | return 0; |
998 | } | |
999 | ||
4d85529d | 1000 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1001 | { |
1002 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1003 | struct drm_device *dev = node->minor->dev; | |
1004 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1005 | u32 rgvmodectl, rstdbyctl; |
1006 | u16 crstandvid; | |
1007 | int ret; | |
1008 | ||
1009 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1010 | if (ret) | |
1011 | return ret; | |
1012 | ||
1013 | rgvmodectl = I915_READ(MEMMODECTL); | |
1014 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1015 | crstandvid = I915_READ16(CRSTANDVID); | |
1016 | ||
1017 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1018 | |
1019 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1020 | "yes" : "no"); | |
1021 | seq_printf(m, "Boost freq: %d\n", | |
1022 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1023 | MEMMODE_BOOST_FREQ_SHIFT); | |
1024 | seq_printf(m, "HW control enabled: %s\n", | |
1025 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1026 | seq_printf(m, "SW control enabled: %s\n", | |
1027 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1028 | seq_printf(m, "Gated voltage change: %s\n", | |
1029 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1030 | seq_printf(m, "Starting frequency: P%d\n", | |
1031 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1032 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1033 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1034 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1035 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1036 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1037 | seq_printf(m, "Render standby enabled: %s\n", | |
1038 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1039 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1040 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1041 | case RSX_STATUS_ON: | |
267f0c90 | 1042 | seq_puts(m, "on\n"); |
88271da3 JB |
1043 | break; |
1044 | case RSX_STATUS_RC1: | |
267f0c90 | 1045 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1046 | break; |
1047 | case RSX_STATUS_RC1E: | |
267f0c90 | 1048 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1049 | break; |
1050 | case RSX_STATUS_RS1: | |
267f0c90 | 1051 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1052 | break; |
1053 | case RSX_STATUS_RS2: | |
267f0c90 | 1054 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1055 | break; |
1056 | case RSX_STATUS_RS3: | |
267f0c90 | 1057 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1058 | break; |
1059 | default: | |
267f0c90 | 1060 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1061 | break; |
1062 | } | |
f97108d1 JB |
1063 | |
1064 | return 0; | |
1065 | } | |
1066 | ||
4d85529d BW |
1067 | static int gen6_drpc_info(struct seq_file *m) |
1068 | { | |
1069 | ||
1070 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1071 | struct drm_device *dev = node->minor->dev; | |
1072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1073 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1074 | unsigned forcewake_count; |
aee56cff | 1075 | int count = 0, ret; |
4d85529d BW |
1076 | |
1077 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1078 | if (ret) | |
1079 | return ret; | |
1080 | ||
907b28c5 CW |
1081 | spin_lock_irq(&dev_priv->uncore.lock); |
1082 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1083 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1084 | |
1085 | if (forcewake_count) { | |
267f0c90 DL |
1086 | seq_puts(m, "RC information inaccurate because somebody " |
1087 | "holds a forcewake reference \n"); | |
4d85529d BW |
1088 | } else { |
1089 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1090 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1091 | udelay(10); | |
1092 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1093 | } | |
1094 | ||
1095 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1096 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1097 | |
1098 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1099 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1100 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1101 | mutex_lock(&dev_priv->rps.hw_lock); |
1102 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1103 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1104 | |
1105 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1106 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1107 | seq_printf(m, "HW control enabled: %s\n", | |
1108 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1109 | seq_printf(m, "SW control enabled: %s\n", | |
1110 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1111 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1112 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1113 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1114 | seq_printf(m, "RC6 Enabled: %s\n", | |
1115 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1116 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1117 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1118 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1119 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1120 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1121 | switch (gt_core_status & GEN6_RCn_MASK) { |
1122 | case GEN6_RC0: | |
1123 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1124 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1125 | else |
267f0c90 | 1126 | seq_puts(m, "on\n"); |
4d85529d BW |
1127 | break; |
1128 | case GEN6_RC3: | |
267f0c90 | 1129 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1130 | break; |
1131 | case GEN6_RC6: | |
267f0c90 | 1132 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1133 | break; |
1134 | case GEN6_RC7: | |
267f0c90 | 1135 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1136 | break; |
1137 | default: | |
267f0c90 | 1138 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1139 | break; |
1140 | } | |
1141 | ||
1142 | seq_printf(m, "Core Power Down: %s\n", | |
1143 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1144 | |
1145 | /* Not exactly sure what this is */ | |
1146 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1147 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1148 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1149 | I915_READ(GEN6_GT_GFX_RC6)); | |
1150 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1151 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1152 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1153 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1154 | ||
ecd8faea BW |
1155 | seq_printf(m, "RC6 voltage: %dmV\n", |
1156 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1157 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1158 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1159 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1160 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1161 | return 0; |
1162 | } | |
1163 | ||
1164 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1165 | { | |
1166 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1167 | struct drm_device *dev = node->minor->dev; | |
1168 | ||
1169 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1170 | return gen6_drpc_info(m); | |
1171 | else | |
1172 | return ironlake_drpc_info(m); | |
1173 | } | |
1174 | ||
b5e50c3f JB |
1175 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1176 | { | |
1177 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1178 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1179 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1180 | |
ee5382ae | 1181 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1182 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1183 | return 0; |
1184 | } | |
1185 | ||
ee5382ae | 1186 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1187 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1188 | } else { |
267f0c90 | 1189 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1190 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1191 | case FBC_OK: |
1192 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1193 | break; | |
1194 | case FBC_UNSUPPORTED: | |
1195 | seq_puts(m, "unsupported by this chipset"); | |
1196 | break; | |
bed4a673 | 1197 | case FBC_NO_OUTPUT: |
267f0c90 | 1198 | seq_puts(m, "no outputs"); |
bed4a673 | 1199 | break; |
b5e50c3f | 1200 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1201 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1202 | break; |
1203 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1204 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1205 | break; |
1206 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1207 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1208 | break; |
1209 | case FBC_BAD_PLANE: | |
267f0c90 | 1210 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1211 | break; |
1212 | case FBC_NOT_TILED: | |
267f0c90 | 1213 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1214 | break; |
9c928d16 | 1215 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1216 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1217 | break; |
c1a9f047 | 1218 | case FBC_MODULE_PARAM: |
267f0c90 | 1219 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1220 | break; |
8a5729a3 | 1221 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1222 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1223 | break; |
b5e50c3f | 1224 | default: |
267f0c90 | 1225 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1226 | } |
267f0c90 | 1227 | seq_putc(m, '\n'); |
b5e50c3f JB |
1228 | } |
1229 | return 0; | |
1230 | } | |
1231 | ||
92d44621 PZ |
1232 | static int i915_ips_status(struct seq_file *m, void *unused) |
1233 | { | |
1234 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1235 | struct drm_device *dev = node->minor->dev; | |
1236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1237 | ||
f5adf94e | 1238 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1239 | seq_puts(m, "not supported\n"); |
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1244 | seq_puts(m, "enabled\n"); | |
1245 | else | |
1246 | seq_puts(m, "disabled\n"); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
4a9bef37 JB |
1251 | static int i915_sr_status(struct seq_file *m, void *unused) |
1252 | { | |
1253 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1254 | struct drm_device *dev = node->minor->dev; | |
1255 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1256 | bool sr_enabled = false; | |
1257 | ||
1398261a | 1258 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1259 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1260 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1261 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1262 | else if (IS_I915GM(dev)) | |
1263 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1264 | else if (IS_PINEVIEW(dev)) | |
1265 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1266 | ||
5ba2aaaa CW |
1267 | seq_printf(m, "self-refresh: %s\n", |
1268 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1269 | |
1270 | return 0; | |
1271 | } | |
1272 | ||
7648fa99 JB |
1273 | static int i915_emon_status(struct seq_file *m, void *unused) |
1274 | { | |
1275 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1276 | struct drm_device *dev = node->minor->dev; | |
1277 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1278 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1279 | int ret; |
1280 | ||
582be6b4 CW |
1281 | if (!IS_GEN5(dev)) |
1282 | return -ENODEV; | |
1283 | ||
de227ef0 CW |
1284 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1285 | if (ret) | |
1286 | return ret; | |
7648fa99 JB |
1287 | |
1288 | temp = i915_mch_val(dev_priv); | |
1289 | chipset = i915_chipset_val(dev_priv); | |
1290 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1291 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1292 | |
1293 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1294 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1295 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1296 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1297 | ||
1298 | return 0; | |
1299 | } | |
1300 | ||
23b2f8bb JB |
1301 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1302 | { | |
1303 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1304 | struct drm_device *dev = node->minor->dev; | |
1305 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1306 | int ret; | |
1307 | int gpu_freq, ia_freq; | |
1308 | ||
1c70c0ce | 1309 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1310 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1311 | return 0; |
1312 | } | |
1313 | ||
4fc688ce | 1314 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1315 | if (ret) |
1316 | return ret; | |
1317 | ||
267f0c90 | 1318 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1319 | |
c6a828d3 DV |
1320 | for (gpu_freq = dev_priv->rps.min_delay; |
1321 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1322 | gpu_freq++) { |
42c0526c BW |
1323 | ia_freq = gpu_freq; |
1324 | sandybridge_pcode_read(dev_priv, | |
1325 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1326 | &ia_freq); | |
3ebecd07 CW |
1327 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1328 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1329 | ((ia_freq >> 0) & 0xff) * 100, | |
1330 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1331 | } |
1332 | ||
4fc688ce | 1333 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1334 | |
1335 | return 0; | |
1336 | } | |
1337 | ||
7648fa99 JB |
1338 | static int i915_gfxec(struct seq_file *m, void *unused) |
1339 | { | |
1340 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1341 | struct drm_device *dev = node->minor->dev; | |
1342 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1343 | int ret; |
1344 | ||
1345 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1346 | if (ret) | |
1347 | return ret; | |
7648fa99 JB |
1348 | |
1349 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1350 | ||
616fdb5a BW |
1351 | mutex_unlock(&dev->struct_mutex); |
1352 | ||
7648fa99 JB |
1353 | return 0; |
1354 | } | |
1355 | ||
44834a67 CW |
1356 | static int i915_opregion(struct seq_file *m, void *unused) |
1357 | { | |
1358 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1359 | struct drm_device *dev = node->minor->dev; | |
1360 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1361 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1362 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1363 | int ret; |
1364 | ||
0d38f009 DV |
1365 | if (data == NULL) |
1366 | return -ENOMEM; | |
1367 | ||
44834a67 CW |
1368 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1369 | if (ret) | |
0d38f009 | 1370 | goto out; |
44834a67 | 1371 | |
0d38f009 DV |
1372 | if (opregion->header) { |
1373 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1374 | seq_write(m, data, OPREGION_SIZE); | |
1375 | } | |
44834a67 CW |
1376 | |
1377 | mutex_unlock(&dev->struct_mutex); | |
1378 | ||
0d38f009 DV |
1379 | out: |
1380 | kfree(data); | |
44834a67 CW |
1381 | return 0; |
1382 | } | |
1383 | ||
37811fcc CW |
1384 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1385 | { | |
1386 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1387 | struct drm_device *dev = node->minor->dev; | |
1388 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1389 | struct intel_fbdev *ifbdev; | |
1390 | struct intel_framebuffer *fb; | |
1391 | int ret; | |
1392 | ||
1393 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1394 | if (ret) | |
1395 | return ret; | |
1396 | ||
1397 | ifbdev = dev_priv->fbdev; | |
1398 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1399 | ||
623f9783 | 1400 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1401 | fb->base.width, |
1402 | fb->base.height, | |
1403 | fb->base.depth, | |
623f9783 DV |
1404 | fb->base.bits_per_pixel, |
1405 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1406 | describe_obj(m, fb->obj); |
267f0c90 | 1407 | seq_putc(m, '\n'); |
4b096ac1 | 1408 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1409 | |
4b096ac1 | 1410 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1411 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1412 | if (&fb->base == ifbdev->helper.fb) | |
1413 | continue; | |
1414 | ||
623f9783 | 1415 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1416 | fb->base.width, |
1417 | fb->base.height, | |
1418 | fb->base.depth, | |
623f9783 DV |
1419 | fb->base.bits_per_pixel, |
1420 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1421 | describe_obj(m, fb->obj); |
267f0c90 | 1422 | seq_putc(m, '\n'); |
37811fcc | 1423 | } |
4b096ac1 | 1424 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
e76d3630 BW |
1429 | static int i915_context_status(struct seq_file *m, void *unused) |
1430 | { | |
1431 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1432 | struct drm_device *dev = node->minor->dev; | |
1433 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1434 | struct intel_ring_buffer *ring; |
1435 | int ret, i; | |
e76d3630 BW |
1436 | |
1437 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1438 | if (ret) | |
1439 | return ret; | |
1440 | ||
3e373948 | 1441 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1442 | seq_puts(m, "power context "); |
3e373948 | 1443 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1444 | seq_putc(m, '\n'); |
dc501fbc | 1445 | } |
e76d3630 | 1446 | |
3e373948 | 1447 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1448 | seq_puts(m, "render context "); |
3e373948 | 1449 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1450 | seq_putc(m, '\n'); |
dc501fbc | 1451 | } |
e76d3630 | 1452 | |
a168c293 BW |
1453 | for_each_ring(ring, dev_priv, i) { |
1454 | if (ring->default_context) { | |
1455 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1456 | describe_obj(m, ring->default_context->obj); | |
267f0c90 | 1457 | seq_putc(m, '\n'); |
a168c293 BW |
1458 | } |
1459 | } | |
1460 | ||
e76d3630 BW |
1461 | mutex_unlock(&dev->mode_config.mutex); |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
6d794d42 BW |
1466 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1467 | { | |
1468 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1469 | struct drm_device *dev = node->minor->dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1471 | unsigned forcewake_count; |
6d794d42 | 1472 | |
907b28c5 CW |
1473 | spin_lock_irq(&dev_priv->uncore.lock); |
1474 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1475 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1476 | |
9f1f46a4 | 1477 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1478 | |
1479 | return 0; | |
1480 | } | |
1481 | ||
ea16a3cd DV |
1482 | static const char *swizzle_string(unsigned swizzle) |
1483 | { | |
aee56cff | 1484 | switch (swizzle) { |
ea16a3cd DV |
1485 | case I915_BIT_6_SWIZZLE_NONE: |
1486 | return "none"; | |
1487 | case I915_BIT_6_SWIZZLE_9: | |
1488 | return "bit9"; | |
1489 | case I915_BIT_6_SWIZZLE_9_10: | |
1490 | return "bit9/bit10"; | |
1491 | case I915_BIT_6_SWIZZLE_9_11: | |
1492 | return "bit9/bit11"; | |
1493 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1494 | return "bit9/bit10/bit11"; | |
1495 | case I915_BIT_6_SWIZZLE_9_17: | |
1496 | return "bit9/bit17"; | |
1497 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1498 | return "bit9/bit10/bit17"; | |
1499 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1500 | return "unknown"; |
ea16a3cd DV |
1501 | } |
1502 | ||
1503 | return "bug"; | |
1504 | } | |
1505 | ||
1506 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1507 | { | |
1508 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1509 | struct drm_device *dev = node->minor->dev; | |
1510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1511 | int ret; |
1512 | ||
1513 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1514 | if (ret) | |
1515 | return ret; | |
ea16a3cd | 1516 | |
ea16a3cd DV |
1517 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1518 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1519 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1520 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1521 | ||
1522 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1523 | seq_printf(m, "DDC = 0x%08x\n", | |
1524 | I915_READ(DCC)); | |
1525 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1526 | I915_READ16(C0DRB3)); | |
1527 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1528 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1529 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1530 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1531 | I915_READ(MAD_DIMM_C0)); | |
1532 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1533 | I915_READ(MAD_DIMM_C1)); | |
1534 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1535 | I915_READ(MAD_DIMM_C2)); | |
1536 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1537 | I915_READ(TILECTL)); | |
1538 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1539 | I915_READ(ARB_MODE)); | |
1540 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1541 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1542 | } |
1543 | mutex_unlock(&dev->struct_mutex); | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
3cf17fc5 DV |
1548 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1549 | { | |
1550 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1551 | struct drm_device *dev = node->minor->dev; | |
1552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1553 | struct intel_ring_buffer *ring; | |
1554 | int i, ret; | |
1555 | ||
1556 | ||
1557 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1558 | if (ret) | |
1559 | return ret; | |
1560 | if (INTEL_INFO(dev)->gen == 6) | |
1561 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1562 | ||
a2c7f6fd | 1563 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1564 | seq_printf(m, "%s\n", ring->name); |
1565 | if (INTEL_INFO(dev)->gen == 7) | |
1566 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1567 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1568 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1569 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1570 | } | |
1571 | if (dev_priv->mm.aliasing_ppgtt) { | |
1572 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1573 | ||
267f0c90 | 1574 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1575 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1576 | } | |
1577 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1578 | mutex_unlock(&dev->struct_mutex); | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
57f350b6 JB |
1583 | static int i915_dpio_info(struct seq_file *m, void *data) |
1584 | { | |
1585 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1586 | struct drm_device *dev = node->minor->dev; | |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | int ret; | |
1589 | ||
1590 | ||
1591 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1592 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1593 | return 0; |
1594 | } | |
1595 | ||
09153000 | 1596 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1597 | if (ret) |
1598 | return ret; | |
1599 | ||
1600 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1601 | ||
1602 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
ae99258f | 1603 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
57f350b6 | 1604 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
ae99258f | 1605 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
57f350b6 JB |
1606 | |
1607 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
ae99258f | 1608 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
57f350b6 | 1609 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
ae99258f | 1610 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
57f350b6 JB |
1611 | |
1612 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
ae99258f | 1613 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
57f350b6 | 1614 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
ae99258f | 1615 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
57f350b6 | 1616 | |
4abb2c39 VS |
1617 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
1618 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); | |
1619 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", | |
1620 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); | |
57f350b6 JB |
1621 | |
1622 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ae99258f | 1623 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1624 | |
09153000 | 1625 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1626 | |
1627 | return 0; | |
1628 | } | |
1629 | ||
63573eb7 BW |
1630 | static int i915_llc(struct seq_file *m, void *data) |
1631 | { | |
1632 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1633 | struct drm_device *dev = node->minor->dev; | |
1634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1635 | ||
1636 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1637 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1638 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1639 | ||
1640 | return 0; | |
1641 | } | |
1642 | ||
e91fd8c6 RV |
1643 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1644 | { | |
1645 | struct drm_info_node *node = m->private; | |
1646 | struct drm_device *dev = node->minor->dev; | |
1647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3f51e471 | 1648 | u32 psrstat, psrperf; |
e91fd8c6 RV |
1649 | |
1650 | if (!IS_HASWELL(dev)) { | |
1651 | seq_puts(m, "PSR not supported on this platform\n"); | |
3f51e471 RV |
1652 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
1653 | seq_puts(m, "PSR enabled\n"); | |
1654 | } else { | |
1655 | seq_puts(m, "PSR disabled: "); | |
1656 | switch (dev_priv->no_psr_reason) { | |
1657 | case PSR_NO_SOURCE: | |
1658 | seq_puts(m, "not supported on this platform"); | |
1659 | break; | |
1660 | case PSR_NO_SINK: | |
1661 | seq_puts(m, "not supported by panel"); | |
1662 | break; | |
105b7c11 RV |
1663 | case PSR_MODULE_PARAM: |
1664 | seq_puts(m, "disabled by flag"); | |
1665 | break; | |
3f51e471 RV |
1666 | case PSR_CRTC_NOT_ACTIVE: |
1667 | seq_puts(m, "crtc not active"); | |
1668 | break; | |
1669 | case PSR_PWR_WELL_ENABLED: | |
1670 | seq_puts(m, "power well enabled"); | |
1671 | break; | |
1672 | case PSR_NOT_TILED: | |
1673 | seq_puts(m, "not tiled"); | |
1674 | break; | |
1675 | case PSR_SPRITE_ENABLED: | |
1676 | seq_puts(m, "sprite enabled"); | |
1677 | break; | |
1678 | case PSR_S3D_ENABLED: | |
1679 | seq_puts(m, "stereo 3d enabled"); | |
1680 | break; | |
1681 | case PSR_INTERLACED_ENABLED: | |
1682 | seq_puts(m, "interlaced enabled"); | |
1683 | break; | |
1684 | case PSR_HSW_NOT_DDIA: | |
1685 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); | |
1686 | break; | |
1687 | default: | |
1688 | seq_puts(m, "unknown reason"); | |
1689 | } | |
1690 | seq_puts(m, "\n"); | |
e91fd8c6 RV |
1691 | return 0; |
1692 | } | |
1693 | ||
e91fd8c6 RV |
1694 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
1695 | ||
1696 | seq_puts(m, "PSR Current State: "); | |
1697 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { | |
1698 | case EDP_PSR_STATUS_STATE_IDLE: | |
1699 | seq_puts(m, "Reset state\n"); | |
1700 | break; | |
1701 | case EDP_PSR_STATUS_STATE_SRDONACK: | |
1702 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); | |
1703 | break; | |
1704 | case EDP_PSR_STATUS_STATE_SRDENT: | |
1705 | seq_puts(m, "SRD entry\n"); | |
1706 | break; | |
1707 | case EDP_PSR_STATUS_STATE_BUFOFF: | |
1708 | seq_puts(m, "Wait for buffer turn off\n"); | |
1709 | break; | |
1710 | case EDP_PSR_STATUS_STATE_BUFON: | |
1711 | seq_puts(m, "Wait for buffer turn on\n"); | |
1712 | break; | |
1713 | case EDP_PSR_STATUS_STATE_AUXACK: | |
1714 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); | |
1715 | break; | |
1716 | case EDP_PSR_STATUS_STATE_SRDOFFACK: | |
1717 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); | |
1718 | break; | |
1719 | default: | |
1720 | seq_puts(m, "Unknown\n"); | |
1721 | break; | |
1722 | } | |
1723 | ||
1724 | seq_puts(m, "Link Status: "); | |
1725 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { | |
1726 | case EDP_PSR_STATUS_LINK_FULL_OFF: | |
1727 | seq_puts(m, "Link is fully off\n"); | |
1728 | break; | |
1729 | case EDP_PSR_STATUS_LINK_FULL_ON: | |
1730 | seq_puts(m, "Link is fully on\n"); | |
1731 | break; | |
1732 | case EDP_PSR_STATUS_LINK_STANDBY: | |
1733 | seq_puts(m, "Link is in standby\n"); | |
1734 | break; | |
1735 | default: | |
1736 | seq_puts(m, "Unknown\n"); | |
1737 | break; | |
1738 | } | |
1739 | ||
1740 | seq_printf(m, "PSR Entry Count: %u\n", | |
1741 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & | |
1742 | EDP_PSR_STATUS_COUNT_MASK); | |
1743 | ||
1744 | seq_printf(m, "Max Sleep Timer Counter: %u\n", | |
1745 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & | |
1746 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); | |
1747 | ||
1748 | seq_printf(m, "Had AUX error: %s\n", | |
1749 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); | |
1750 | ||
1751 | seq_printf(m, "Sending AUX: %s\n", | |
1752 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); | |
1753 | ||
1754 | seq_printf(m, "Sending Idle: %s\n", | |
1755 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); | |
1756 | ||
1757 | seq_printf(m, "Sending TP2 TP3: %s\n", | |
1758 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); | |
1759 | ||
1760 | seq_printf(m, "Sending TP1: %s\n", | |
1761 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); | |
1762 | ||
1763 | seq_printf(m, "Idle Count: %u\n", | |
1764 | psrstat & EDP_PSR_STATUS_IDLE_MASK); | |
1765 | ||
1766 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; | |
1767 | seq_printf(m, "Performance Counter: %u\n", psrperf); | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
647416f9 KC |
1772 | static int |
1773 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1774 | { |
647416f9 | 1775 | struct drm_device *dev = data; |
f3cd474b | 1776 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1777 | |
647416f9 | 1778 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1779 | |
647416f9 | 1780 | return 0; |
f3cd474b CW |
1781 | } |
1782 | ||
647416f9 KC |
1783 | static int |
1784 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1785 | { |
647416f9 | 1786 | struct drm_device *dev = data; |
f3cd474b | 1787 | |
647416f9 | 1788 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1789 | i915_handle_error(dev, val); |
f3cd474b | 1790 | |
647416f9 | 1791 | return 0; |
f3cd474b CW |
1792 | } |
1793 | ||
647416f9 KC |
1794 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1795 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1796 | "%llu\n"); |
f3cd474b | 1797 | |
647416f9 KC |
1798 | static int |
1799 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1800 | { |
647416f9 | 1801 | struct drm_device *dev = data; |
e5eb3d63 | 1802 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1803 | |
647416f9 | 1804 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1805 | |
647416f9 | 1806 | return 0; |
e5eb3d63 DV |
1807 | } |
1808 | ||
647416f9 KC |
1809 | static int |
1810 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1811 | { |
647416f9 | 1812 | struct drm_device *dev = data; |
e5eb3d63 | 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1814 | int ret; |
e5eb3d63 | 1815 | |
647416f9 | 1816 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1817 | |
22bcfc6a DV |
1818 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1819 | if (ret) | |
1820 | return ret; | |
1821 | ||
99584db3 | 1822 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1823 | mutex_unlock(&dev->struct_mutex); |
1824 | ||
647416f9 | 1825 | return 0; |
e5eb3d63 DV |
1826 | } |
1827 | ||
647416f9 KC |
1828 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1829 | i915_ring_stop_get, i915_ring_stop_set, | |
1830 | "0x%08llx\n"); | |
d5442303 | 1831 | |
dd624afd CW |
1832 | #define DROP_UNBOUND 0x1 |
1833 | #define DROP_BOUND 0x2 | |
1834 | #define DROP_RETIRE 0x4 | |
1835 | #define DROP_ACTIVE 0x8 | |
1836 | #define DROP_ALL (DROP_UNBOUND | \ | |
1837 | DROP_BOUND | \ | |
1838 | DROP_RETIRE | \ | |
1839 | DROP_ACTIVE) | |
647416f9 KC |
1840 | static int |
1841 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1842 | { |
647416f9 | 1843 | *val = DROP_ALL; |
dd624afd | 1844 | |
647416f9 | 1845 | return 0; |
dd624afd CW |
1846 | } |
1847 | ||
647416f9 KC |
1848 | static int |
1849 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1850 | { |
647416f9 | 1851 | struct drm_device *dev = data; |
dd624afd CW |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; |
1853 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1854 | struct i915_address_space *vm; |
1855 | struct i915_vma *vma, *x; | |
647416f9 | 1856 | int ret; |
dd624afd | 1857 | |
647416f9 | 1858 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1859 | |
1860 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1861 | * on ioctls on -EAGAIN. */ | |
1862 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1863 | if (ret) | |
1864 | return ret; | |
1865 | ||
1866 | if (val & DROP_ACTIVE) { | |
1867 | ret = i915_gpu_idle(dev); | |
1868 | if (ret) | |
1869 | goto unlock; | |
1870 | } | |
1871 | ||
1872 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1873 | i915_gem_retire_requests(dev); | |
1874 | ||
1875 | if (val & DROP_BOUND) { | |
ca191b13 BW |
1876 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1877 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
1878 | mm_list) { | |
1879 | if (vma->obj->pin_count) | |
1880 | continue; | |
1881 | ||
1882 | ret = i915_vma_unbind(vma); | |
1883 | if (ret) | |
1884 | goto unlock; | |
1885 | } | |
31a46c9c | 1886 | } |
dd624afd CW |
1887 | } |
1888 | ||
1889 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1890 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1891 | global_list) | |
dd624afd CW |
1892 | if (obj->pages_pin_count == 0) { |
1893 | ret = i915_gem_object_put_pages(obj); | |
1894 | if (ret) | |
1895 | goto unlock; | |
1896 | } | |
1897 | } | |
1898 | ||
1899 | unlock: | |
1900 | mutex_unlock(&dev->struct_mutex); | |
1901 | ||
647416f9 | 1902 | return ret; |
dd624afd CW |
1903 | } |
1904 | ||
647416f9 KC |
1905 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1906 | i915_drop_caches_get, i915_drop_caches_set, | |
1907 | "0x%08llx\n"); | |
dd624afd | 1908 | |
647416f9 KC |
1909 | static int |
1910 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1911 | { |
647416f9 | 1912 | struct drm_device *dev = data; |
358733e9 | 1913 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1914 | int ret; |
004777cb DV |
1915 | |
1916 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1917 | return -ENODEV; | |
1918 | ||
4fc688ce | 1919 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1920 | if (ret) |
1921 | return ret; | |
358733e9 | 1922 | |
0a073b84 JB |
1923 | if (IS_VALLEYVIEW(dev)) |
1924 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1925 | dev_priv->rps.max_delay); | |
1926 | else | |
1927 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1928 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1929 | |
647416f9 | 1930 | return 0; |
358733e9 JB |
1931 | } |
1932 | ||
647416f9 KC |
1933 | static int |
1934 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1935 | { |
647416f9 | 1936 | struct drm_device *dev = data; |
358733e9 | 1937 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1938 | int ret; |
004777cb DV |
1939 | |
1940 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1941 | return -ENODEV; | |
358733e9 | 1942 | |
647416f9 | 1943 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 1944 | |
4fc688ce | 1945 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1946 | if (ret) |
1947 | return ret; | |
1948 | ||
358733e9 JB |
1949 | /* |
1950 | * Turbo will still be enabled, but won't go above the set value. | |
1951 | */ | |
0a073b84 JB |
1952 | if (IS_VALLEYVIEW(dev)) { |
1953 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1954 | dev_priv->rps.max_delay = val; | |
1955 | gen6_set_rps(dev, val); | |
1956 | } else { | |
1957 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1958 | dev_priv->rps.max_delay = val; | |
1959 | gen6_set_rps(dev, val); | |
1960 | } | |
1961 | ||
4fc688ce | 1962 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1963 | |
647416f9 | 1964 | return 0; |
358733e9 JB |
1965 | } |
1966 | ||
647416f9 KC |
1967 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
1968 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 1969 | "%llu\n"); |
358733e9 | 1970 | |
647416f9 KC |
1971 | static int |
1972 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 1973 | { |
647416f9 | 1974 | struct drm_device *dev = data; |
1523c310 | 1975 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1976 | int ret; |
004777cb DV |
1977 | |
1978 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1979 | return -ENODEV; | |
1980 | ||
4fc688ce | 1981 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1982 | if (ret) |
1983 | return ret; | |
1523c310 | 1984 | |
0a073b84 JB |
1985 | if (IS_VALLEYVIEW(dev)) |
1986 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1987 | dev_priv->rps.min_delay); | |
1988 | else | |
1989 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1990 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1991 | |
647416f9 | 1992 | return 0; |
1523c310 JB |
1993 | } |
1994 | ||
647416f9 KC |
1995 | static int |
1996 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 1997 | { |
647416f9 | 1998 | struct drm_device *dev = data; |
1523c310 | 1999 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2000 | int ret; |
004777cb DV |
2001 | |
2002 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2003 | return -ENODEV; | |
1523c310 | 2004 | |
647416f9 | 2005 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2006 | |
4fc688ce | 2007 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2008 | if (ret) |
2009 | return ret; | |
2010 | ||
1523c310 JB |
2011 | /* |
2012 | * Turbo will still be enabled, but won't go below the set value. | |
2013 | */ | |
0a073b84 JB |
2014 | if (IS_VALLEYVIEW(dev)) { |
2015 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2016 | dev_priv->rps.min_delay = val; | |
2017 | valleyview_set_rps(dev, val); | |
2018 | } else { | |
2019 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2020 | dev_priv->rps.min_delay = val; | |
2021 | gen6_set_rps(dev, val); | |
2022 | } | |
4fc688ce | 2023 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2024 | |
647416f9 | 2025 | return 0; |
1523c310 JB |
2026 | } |
2027 | ||
647416f9 KC |
2028 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2029 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2030 | "%llu\n"); |
1523c310 | 2031 | |
647416f9 KC |
2032 | static int |
2033 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2034 | { |
647416f9 | 2035 | struct drm_device *dev = data; |
07b7ddd9 | 2036 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2037 | u32 snpcr; |
647416f9 | 2038 | int ret; |
07b7ddd9 | 2039 | |
004777cb DV |
2040 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2041 | return -ENODEV; | |
2042 | ||
22bcfc6a DV |
2043 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2044 | if (ret) | |
2045 | return ret; | |
2046 | ||
07b7ddd9 JB |
2047 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2048 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2049 | ||
647416f9 | 2050 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2051 | |
647416f9 | 2052 | return 0; |
07b7ddd9 JB |
2053 | } |
2054 | ||
647416f9 KC |
2055 | static int |
2056 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2057 | { |
647416f9 | 2058 | struct drm_device *dev = data; |
07b7ddd9 | 2059 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2060 | u32 snpcr; |
07b7ddd9 | 2061 | |
004777cb DV |
2062 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2063 | return -ENODEV; | |
2064 | ||
647416f9 | 2065 | if (val > 3) |
07b7ddd9 JB |
2066 | return -EINVAL; |
2067 | ||
647416f9 | 2068 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2069 | |
2070 | /* Update the cache sharing policy here as well */ | |
2071 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2072 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2073 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2074 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2075 | ||
647416f9 | 2076 | return 0; |
07b7ddd9 JB |
2077 | } |
2078 | ||
647416f9 KC |
2079 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2080 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2081 | "%llu\n"); | |
07b7ddd9 | 2082 | |
f3cd474b CW |
2083 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2084 | * allocated we need to hook into the minor for release. */ | |
2085 | static int | |
2086 | drm_add_fake_info_node(struct drm_minor *minor, | |
2087 | struct dentry *ent, | |
2088 | const void *key) | |
2089 | { | |
2090 | struct drm_info_node *node; | |
2091 | ||
2092 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2093 | if (node == NULL) { | |
2094 | debugfs_remove(ent); | |
2095 | return -ENOMEM; | |
2096 | } | |
2097 | ||
2098 | node->minor = minor; | |
2099 | node->dent = ent; | |
2100 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2101 | |
2102 | mutex_lock(&minor->debugfs_lock); | |
2103 | list_add(&node->list, &minor->debugfs_list); | |
2104 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2105 | |
2106 | return 0; | |
2107 | } | |
2108 | ||
6d794d42 BW |
2109 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2110 | { | |
2111 | struct drm_device *dev = inode->i_private; | |
2112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2113 | |
075edca4 | 2114 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2115 | return 0; |
2116 | ||
6d794d42 | 2117 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2118 | |
2119 | return 0; | |
2120 | } | |
2121 | ||
c43b5634 | 2122 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2123 | { |
2124 | struct drm_device *dev = inode->i_private; | |
2125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2126 | ||
075edca4 | 2127 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2128 | return 0; |
2129 | ||
6d794d42 | 2130 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2131 | |
2132 | return 0; | |
2133 | } | |
2134 | ||
2135 | static const struct file_operations i915_forcewake_fops = { | |
2136 | .owner = THIS_MODULE, | |
2137 | .open = i915_forcewake_open, | |
2138 | .release = i915_forcewake_release, | |
2139 | }; | |
2140 | ||
2141 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2142 | { | |
2143 | struct drm_device *dev = minor->dev; | |
2144 | struct dentry *ent; | |
2145 | ||
2146 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2147 | S_IRUSR, |
6d794d42 BW |
2148 | root, dev, |
2149 | &i915_forcewake_fops); | |
2150 | if (IS_ERR(ent)) | |
2151 | return PTR_ERR(ent); | |
2152 | ||
8eb57294 | 2153 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2154 | } |
2155 | ||
6a9c308d DV |
2156 | static int i915_debugfs_create(struct dentry *root, |
2157 | struct drm_minor *minor, | |
2158 | const char *name, | |
2159 | const struct file_operations *fops) | |
07b7ddd9 JB |
2160 | { |
2161 | struct drm_device *dev = minor->dev; | |
2162 | struct dentry *ent; | |
2163 | ||
6a9c308d | 2164 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2165 | S_IRUGO | S_IWUSR, |
2166 | root, dev, | |
6a9c308d | 2167 | fops); |
07b7ddd9 JB |
2168 | if (IS_ERR(ent)) |
2169 | return PTR_ERR(ent); | |
2170 | ||
6a9c308d | 2171 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2172 | } |
2173 | ||
27c202ad | 2174 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2175 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2176 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2177 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2178 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2179 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2180 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2181 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2182 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2183 | {"i915_gem_request", i915_gem_request_info, 0}, |
2184 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2185 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2186 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2187 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2188 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2189 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2190 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2191 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2192 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2193 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2194 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2195 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2196 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2197 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2198 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2199 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2200 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2201 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2202 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2203 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2204 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2205 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2206 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2207 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2208 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2209 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2210 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
2017263e | 2211 | }; |
27c202ad | 2212 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2213 | |
2b4bd0e0 | 2214 | static struct i915_debugfs_files { |
34b9674c DV |
2215 | const char *name; |
2216 | const struct file_operations *fops; | |
2217 | } i915_debugfs_files[] = { | |
2218 | {"i915_wedged", &i915_wedged_fops}, | |
2219 | {"i915_max_freq", &i915_max_freq_fops}, | |
2220 | {"i915_min_freq", &i915_min_freq_fops}, | |
2221 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2222 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
2223 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, | |
2224 | {"i915_error_state", &i915_error_state_fops}, | |
2225 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2226 | }; | |
2227 | ||
27c202ad | 2228 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2229 | { |
34b9674c | 2230 | int ret, i; |
f3cd474b | 2231 | |
6d794d42 | 2232 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2233 | if (ret) |
2234 | return ret; | |
6a9c308d | 2235 | |
34b9674c DV |
2236 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2237 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2238 | i915_debugfs_files[i].name, | |
2239 | i915_debugfs_files[i].fops); | |
2240 | if (ret) | |
2241 | return ret; | |
2242 | } | |
40633219 | 2243 | |
27c202ad BG |
2244 | return drm_debugfs_create_files(i915_debugfs_list, |
2245 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2246 | minor->debugfs_root, minor); |
2247 | } | |
2248 | ||
27c202ad | 2249 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2250 | { |
34b9674c DV |
2251 | int i; |
2252 | ||
27c202ad BG |
2253 | drm_debugfs_remove_files(i915_debugfs_list, |
2254 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2255 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2256 | 1, minor); | |
34b9674c DV |
2257 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2258 | struct drm_info_list *info_list = | |
2259 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2260 | ||
2261 | drm_debugfs_remove_files(info_list, 1, minor); | |
2262 | } | |
2017263e BG |
2263 | } |
2264 | ||
2265 | #endif /* CONFIG_DEBUG_FS */ |