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drm/i915: add noop power well handlers instead of NULL checking them
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 173}
174
3ccfd19d
BW		 175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
433e12f7 182static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
2017263e 187 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 190 struct i915_vma *vma;
8f2480fb
CW		 191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
de227ef0
CW		 193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
2017263e 197
ca191b13 198 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 199 switch (list) {
200 case ACTIVE_LIST:
267f0c90 201 seq_puts(m, "Active:\n");
5cef07e1 202 head = &vm->active_list;
433e12f7
BG		 203 break;
204 case INACTIVE_LIST:
267f0c90 205 seq_puts(m, "Inactive:\n");
5cef07e1 206 head = &vm->inactive_list;
433e12f7 207 break;
433e12f7 208 default:
de227ef0
CW		 209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
2017263e 211 }
2017263e 212
8f2480fb 213 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
8f2480fb 220 count++;
2017263e 221 }
de227ef0 222 mutex_unlock(&dev->struct_mutex);
5e118f41 223
8f2480fb
CW		 224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
2017263e
BG		 226 return 0;
227}
228
6d2b8885
CW		 229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
b25cb2f8 233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 234 struct drm_i915_gem_object *b =
b25cb2f8 235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
b25cb2f8 259 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
b25cb2f8 277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
b25cb2f8 281 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
6299f992
CW		 290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
f343c5f6 292 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 293 ++count; \
294 if (obj->map_and_fenceable) { \
f343c5f6 295 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++mappable_count; \
297 } \
298 } \
0206e353 299} while (0)
6299f992 300
2db8e9d6
CW		 301struct file_stats {
302 int count;
303 size_t total, active, inactive, unbound;
304};
305
306static int per_file_stats(int id, void *ptr, void *data)
307{
308 struct drm_i915_gem_object *obj = ptr;
309 struct file_stats *stats = data;
310
311 stats->count++;
312 stats->total += obj->base.size;
313
f343c5f6 314 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 315 if (!list_empty(&obj->ring_list))
316 stats->active += obj->base.size;
317 else
318 stats->inactive += obj->base.size;
319 } else {
320 if (!list_empty(&obj->global_list))
321 stats->unbound += obj->base.size;
322 }
323
324 return 0;
325}
326
ca191b13
BW		 327#define count_vmas(list, member) do { \
328 list_for_each_entry(vma, list, member) { \
329 size += i915_gem_obj_ggtt_size(vma->obj); \
330 ++count; \
331 if (vma->obj->map_and_fenceable) { \
332 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
333 ++mappable_count; \
334 } \
335 } \
336} while (0)
337
338static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 339{
340 struct drm_info_node *node = (struct drm_info_node *) m->private;
341 struct drm_device *dev = node->minor->dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 343 u32 count, mappable_count, purgeable_count;
344 size_t size, mappable_size, purgeable_size;
6299f992 345 struct drm_i915_gem_object *obj;
5cef07e1 346 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 347 struct drm_file *file;
ca191b13 348 struct i915_vma *vma;
73aa808f
CW		 349 int ret;
350
351 ret = mutex_lock_interruptible(&dev->struct_mutex);
352 if (ret)
353 return ret;
354
6299f992
CW		 355 seq_printf(m, "%u objects, %zu bytes\n",
356 dev_priv->mm.object_count,
357 dev_priv->mm.object_memory);
358
359 size = count = mappable_size = mappable_count = 0;
35c20a60 360 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 361 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
362 count, mappable_count, size, mappable_size);
363
364 size = count = mappable_size = mappable_count = 0;
ca191b13 365 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 366 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
367 count, mappable_count, size, mappable_size);
368
6299f992 369 size = count = mappable_size = mappable_count = 0;
ca191b13 370 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 371 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
372 count, mappable_count, size, mappable_size);
373
b7abb714 374 size = count = purgeable_size = purgeable_count = 0;
35c20a60 375 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 376 size += obj->base.size, ++count;
b7abb714
CW		 377 if (obj->madv == I915_MADV_DONTNEED)
378 purgeable_size += obj->base.size, ++purgeable_count;
379 }
6c085a72
CW		 380 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
381
6299f992 382 size = count = mappable_size = mappable_count = 0;
35c20a60 383 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 384 if (obj->fault_mappable) {
f343c5f6 385 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 386 ++count;
387 }
388 if (obj->pin_mappable) {
f343c5f6 389 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 390 ++mappable_count;
391 }
b7abb714
CW		 392 if (obj->madv == I915_MADV_DONTNEED) {
393 purgeable_size += obj->base.size;
394 ++purgeable_count;
395 }
6299f992 396 }
b7abb714
CW		 397 seq_printf(m, "%u purgeable objects, %zu bytes\n",
398 purgeable_count, purgeable_size);
6299f992
CW		 399 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
400 mappable_count, mappable_size);
401 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
402 count, size);
403
93d18799 404 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 405 dev_priv->gtt.base.total,
406 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 407
267f0c90 408 seq_putc(m, '\n');
2db8e9d6
CW		 409 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
410 struct file_stats stats;
3ec2f427 411 struct task_struct *task;
2db8e9d6
CW		 412
413 memset(&stats, 0, sizeof(stats));
414 idr_for_each(&file->object_idr, per_file_stats, &stats);
3ec2f427
TH		 415 /*
416 * Although we have a valid reference on file->pid, that does
417 * not guarantee that the task_struct who called get_pid() is
418 * still alive (e.g. get_pid(current) => fork() => exit()).
419 * Therefore, we need to protect this ->comm access using RCU.
420 */
421 rcu_read_lock();
422 task = pid_task(file->pid, PIDTYPE_PID);
2db8e9d6 423 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
3ec2f427 424 task ? task->comm : "<unknown>",
2db8e9d6
CW		 425 stats.count,
426 stats.total,
427 stats.active,
428 stats.inactive,
429 stats.unbound);
3ec2f427 430 rcu_read_unlock();
2db8e9d6
CW		 431 }
432
73aa808f
CW		 433 mutex_unlock(&dev->struct_mutex);
434
435 return 0;
436}
437
aee56cff 438static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 439{
440 struct drm_info_node *node = (struct drm_info_node *) m->private;
441 struct drm_device *dev = node->minor->dev;
1b50247a 442 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 443 struct drm_i915_private *dev_priv = dev->dev_private;
444 struct drm_i915_gem_object *obj;
445 size_t total_obj_size, total_gtt_size;
446 int count, ret;
447
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
449 if (ret)
450 return ret;
451
452 total_obj_size = total_gtt_size = count = 0;
35c20a60 453 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 454 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 455 continue;
456
267f0c90 457 seq_puts(m, " ");
08c18323 458 describe_obj(m, obj);
267f0c90 459 seq_putc(m, '\n');
08c18323 460 total_obj_size += obj->base.size;
f343c5f6 461 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 462 count++;
463 }
464
465 mutex_unlock(&dev->struct_mutex);
466
467 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
468 count, total_obj_size, total_gtt_size);
469
470 return 0;
471}
472
4e5359cd
SF		 473static int i915_gem_pageflip_info(struct seq_file *m, void *data)
474{
475 struct drm_info_node *node = (struct drm_info_node *) m->private;
476 struct drm_device *dev = node->minor->dev;
477 unsigned long flags;
478 struct intel_crtc *crtc;
479
480 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 481 const char pipe = pipe_name(crtc->pipe);
482 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 483 struct intel_unpin_work *work;
484
485 spin_lock_irqsave(&dev->event_lock, flags);
486 work = crtc->unpin_work;
487 if (work == NULL) {
9db4a9c7 488 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 489 pipe, plane);
490 } else {
e7d841ca 491 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 492 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 493 pipe, plane);
494 } else {
9db4a9c7 495 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 496 pipe, plane);
497 }
498 if (work->enable_stall_check)
267f0c90 499 seq_puts(m, "Stall check enabled, ");
4e5359cd 500 else
267f0c90 501 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 502 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 503
504 if (work->old_fb_obj) {
05394f39
CW		 505 struct drm_i915_gem_object *obj = work->old_fb_obj;
506 if (obj)
f343c5f6
BW		 507 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
508 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 509 }
510 if (work->pending_flip_obj) {
05394f39
CW		 511 struct drm_i915_gem_object *obj = work->pending_flip_obj;
512 if (obj)
f343c5f6
BW		 513 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
514 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 515 }
516 }
517 spin_unlock_irqrestore(&dev->event_lock, flags);
518 }
519
520 return 0;
521}
522
2017263e
BG		 523static int i915_gem_request_info(struct seq_file *m, void *data)
524{
525 struct drm_info_node *node = (struct drm_info_node *) m->private;
526 struct drm_device *dev = node->minor->dev;
527 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 528 struct intel_ring_buffer *ring;
2017263e 529 struct drm_i915_gem_request *gem_request;
a2c7f6fd 530 int ret, count, i;
de227ef0
CW		 531
532 ret = mutex_lock_interruptible(&dev->struct_mutex);
533 if (ret)
534 return ret;
2017263e 535
c2c347a9 536 count = 0;
a2c7f6fd
CW		 537 for_each_ring(ring, dev_priv, i) {
538 if (list_empty(&ring->request_list))
539 continue;
540
541 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 542 list_for_each_entry(gem_request,
a2c7f6fd 543 &ring->request_list,
c2c347a9
CW		 544 list) {
545 seq_printf(m, " %d @ %d\n",
546 gem_request->seqno,
547 (int) (jiffies - gem_request->emitted_jiffies));
548 }
549 count++;
2017263e 550 }
de227ef0
CW		 551 mutex_unlock(&dev->struct_mutex);
552
c2c347a9 553 if (count == 0)
267f0c90 554 seq_puts(m, "No requests\n");
c2c347a9 555
2017263e
BG		 556 return 0;
557}
558
b2223497
CW		 559static void i915_ring_seqno_info(struct seq_file *m,
560 struct intel_ring_buffer *ring)
561{
562 if (ring->get_seqno) {
43a7b924 563 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 564 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 565 }
566}
567
2017263e
BG		 568static int i915_gem_seqno_info(struct seq_file *m, void *data)
569{
570 struct drm_info_node *node = (struct drm_info_node *) m->private;
571 struct drm_device *dev = node->minor->dev;
572 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 573 struct intel_ring_buffer *ring;
1ec14ad3 574 int ret, i;
de227ef0
CW		 575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
c8c8fb33 579 intel_runtime_pm_get(dev_priv);
2017263e 580
a2c7f6fd
CW		 581 for_each_ring(ring, dev_priv, i)
582 i915_ring_seqno_info(m, ring);
de227ef0 583
c8c8fb33 584 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 585 mutex_unlock(&dev->struct_mutex);
586
2017263e
BG		 587 return 0;
588}
589
590
591static int i915_interrupt_info(struct seq_file *m, void *data)
592{
593 struct drm_info_node *node = (struct drm_info_node *) m->private;
594 struct drm_device *dev = node->minor->dev;
595 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 596 struct intel_ring_buffer *ring;
9db4a9c7 597 int ret, i, pipe;
de227ef0
CW		 598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
c8c8fb33 602 intel_runtime_pm_get(dev_priv);
2017263e 603
a123f157 604 if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 605 seq_printf(m, "Master Interrupt Control:\t%08x\n",
606 I915_READ(GEN8_MASTER_IRQ));
607
608 for (i = 0; i < 4; i++) {
609 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
610 i, I915_READ(GEN8_GT_IMR(i)));
611 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
612 i, I915_READ(GEN8_GT_IIR(i)));
613 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
614 i, I915_READ(GEN8_GT_IER(i)));
615 }
616
07d27e20 617 for_each_pipe(pipe) {
a123f157 618 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 619 pipe_name(pipe),
620 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 621 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 622 pipe_name(pipe),
623 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 624 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 625 pipe_name(pipe),
626 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 627 }
628
629 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
630 I915_READ(GEN8_DE_PORT_IMR));
631 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
632 I915_READ(GEN8_DE_PORT_IIR));
633 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
634 I915_READ(GEN8_DE_PORT_IER));
635
636 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
637 I915_READ(GEN8_DE_MISC_IMR));
638 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
639 I915_READ(GEN8_DE_MISC_IIR));
640 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
641 I915_READ(GEN8_DE_MISC_IER));
642
643 seq_printf(m, "PCU interrupt mask:\t%08x\n",
644 I915_READ(GEN8_PCU_IMR));
645 seq_printf(m, "PCU interrupt identity:\t%08x\n",
646 I915_READ(GEN8_PCU_IIR));
647 seq_printf(m, "PCU interrupt enable:\t%08x\n",
648 I915_READ(GEN8_PCU_IER));
649 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 650 seq_printf(m, "Display IER:\t%08x\n",
651 I915_READ(VLV_IER));
652 seq_printf(m, "Display IIR:\t%08x\n",
653 I915_READ(VLV_IIR));
654 seq_printf(m, "Display IIR_RW:\t%08x\n",
655 I915_READ(VLV_IIR_RW));
656 seq_printf(m, "Display IMR:\t%08x\n",
657 I915_READ(VLV_IMR));
658 for_each_pipe(pipe)
659 seq_printf(m, "Pipe %c stat:\t%08x\n",
660 pipe_name(pipe),
661 I915_READ(PIPESTAT(pipe)));
662
663 seq_printf(m, "Master IER:\t%08x\n",
664 I915_READ(VLV_MASTER_IER));
665
666 seq_printf(m, "Render IER:\t%08x\n",
667 I915_READ(GTIER));
668 seq_printf(m, "Render IIR:\t%08x\n",
669 I915_READ(GTIIR));
670 seq_printf(m, "Render IMR:\t%08x\n",
671 I915_READ(GTIMR));
672
673 seq_printf(m, "PM IER:\t\t%08x\n",
674 I915_READ(GEN6_PMIER));
675 seq_printf(m, "PM IIR:\t\t%08x\n",
676 I915_READ(GEN6_PMIIR));
677 seq_printf(m, "PM IMR:\t\t%08x\n",
678 I915_READ(GEN6_PMIMR));
679
680 seq_printf(m, "Port hotplug:\t%08x\n",
681 I915_READ(PORT_HOTPLUG_EN));
682 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
683 I915_READ(VLV_DPFLIPSTAT));
684 seq_printf(m, "DPINVGTT:\t%08x\n",
685 I915_READ(DPINVGTT));
686
687 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 688 seq_printf(m, "Interrupt enable: %08x\n",
689 I915_READ(IER));
690 seq_printf(m, "Interrupt identity: %08x\n",
691 I915_READ(IIR));
692 seq_printf(m, "Interrupt mask: %08x\n",
693 I915_READ(IMR));
9db4a9c7
JB		 694 for_each_pipe(pipe)
695 seq_printf(m, "Pipe %c stat: %08x\n",
696 pipe_name(pipe),
697 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 698 } else {
699 seq_printf(m, "North Display Interrupt enable: %08x\n",
700 I915_READ(DEIER));
701 seq_printf(m, "North Display Interrupt identity: %08x\n",
702 I915_READ(DEIIR));
703 seq_printf(m, "North Display Interrupt mask: %08x\n",
704 I915_READ(DEIMR));
705 seq_printf(m, "South Display Interrupt enable: %08x\n",
706 I915_READ(SDEIER));
707 seq_printf(m, "South Display Interrupt identity: %08x\n",
708 I915_READ(SDEIIR));
709 seq_printf(m, "South Display Interrupt mask: %08x\n",
710 I915_READ(SDEIMR));
711 seq_printf(m, "Graphics Interrupt enable: %08x\n",
712 I915_READ(GTIER));
713 seq_printf(m, "Graphics Interrupt identity: %08x\n",
714 I915_READ(GTIIR));
715 seq_printf(m, "Graphics Interrupt mask: %08x\n",
716 I915_READ(GTIMR));
717 }
a2c7f6fd 718 for_each_ring(ring, dev_priv, i) {
a123f157 719 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 720 seq_printf(m,
721 "Graphics Interrupt mask (%s): %08x\n",
722 ring->name, I915_READ_IMR(ring));
9862e600 723 }
a2c7f6fd 724 i915_ring_seqno_info(m, ring);
9862e600 725 }
c8c8fb33 726 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 727 mutex_unlock(&dev->struct_mutex);
728
2017263e
BG		 729 return 0;
730}
731
a6172a80
CW		 732static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
733{
734 struct drm_info_node *node = (struct drm_info_node *) m->private;
735 struct drm_device *dev = node->minor->dev;
736 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 737 int i, ret;
738
739 ret = mutex_lock_interruptible(&dev->struct_mutex);
740 if (ret)
741 return ret;
a6172a80
CW		 742
743 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
744 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
745 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 746 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 747
6c085a72
CW		 748 seq_printf(m, "Fence %d, pin count = %d, object = ",
749 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 750 if (obj == NULL)
267f0c90 751 seq_puts(m, "unused");
c2c347a9 752 else
05394f39 753 describe_obj(m, obj);
267f0c90 754 seq_putc(m, '\n');
a6172a80
CW		 755 }
756
05394f39 757 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 758 return 0;
759}
760
2017263e
BG		 761static int i915_hws_info(struct seq_file *m, void *data)
762{
763 struct drm_info_node *node = (struct drm_info_node *) m->private;
764 struct drm_device *dev = node->minor->dev;
765 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 766 struct intel_ring_buffer *ring;
1a240d4d 767 const u32 *hws;
4066c0ae
CW		 768 int i;
769
1ec14ad3 770 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 771 hws = ring->status_page.page_addr;
2017263e
BG		 772 if (hws == NULL)
773 return 0;
774
775 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
776 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
777 i * 4,
778 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
779 }
780 return 0;
781}
782
d5442303
DV		 783static ssize_t
784i915_error_state_write(struct file *filp,
785 const char __user *ubuf,
786 size_t cnt,
787 loff_t *ppos)
788{
edc3d884 789 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 790 struct drm_device *dev = error_priv->dev;
22bcfc6a 791 int ret;
d5442303
DV		 792
793 DRM_DEBUG_DRIVER("Resetting error state\n");
794
22bcfc6a
DV		 795 ret = mutex_lock_interruptible(&dev->struct_mutex);
796 if (ret)
797 return ret;
798
d5442303
DV		 799 i915_destroy_error_state(dev);
800 mutex_unlock(&dev->struct_mutex);
801
802 return cnt;
803}
804
805static int i915_error_state_open(struct inode *inode, struct file *file)
806{
807 struct drm_device *dev = inode->i_private;
d5442303 808 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 809
810 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
811 if (!error_priv)
812 return -ENOMEM;
813
814 error_priv->dev = dev;
815
95d5bfb3 816 i915_error_state_get(dev, error_priv);
d5442303 817
edc3d884
MK		 818 file->private_data = error_priv;
819
820 return 0;
d5442303
DV		 821}
822
823static int i915_error_state_release(struct inode *inode, struct file *file)
824{
edc3d884 825 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 826
95d5bfb3 827 i915_error_state_put(error_priv);
d5442303
DV		 828 kfree(error_priv);
829
edc3d884
MK		 830 return 0;
831}
832
4dc955f7
MK		 833static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
834 size_t count, loff_t *pos)
835{
836 struct i915_error_state_file_priv *error_priv = file->private_data;
837 struct drm_i915_error_state_buf error_str;
838 loff_t tmp_pos = 0;
839 ssize_t ret_count = 0;
840 int ret;
841
842 ret = i915_error_state_buf_init(&error_str, count, *pos);
843 if (ret)
844 return ret;
edc3d884 845
fc16b48b 846 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 847 if (ret)
848 goto out;
849
edc3d884
MK		 850 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
851 error_str.buf,
852 error_str.bytes);
853
854 if (ret_count < 0)
855 ret = ret_count;
856 else
857 *pos = error_str.start + ret_count;
858out:
4dc955f7 859 i915_error_state_buf_release(&error_str);
edc3d884 860 return ret ?: ret_count;
d5442303
DV		 861}
862
863static const struct file_operations i915_error_state_fops = {
864 .owner = THIS_MODULE,
865 .open = i915_error_state_open,
edc3d884 866 .read = i915_error_state_read,
d5442303
DV		 867 .write = i915_error_state_write,
868 .llseek = default_llseek,
869 .release = i915_error_state_release,
870};
871
647416f9
KC		 872static int
873i915_next_seqno_get(void *data, u64 *val)
40633219 874{
647416f9 875 struct drm_device *dev = data;
40633219 876 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 877 int ret;
878
879 ret = mutex_lock_interruptible(&dev->struct_mutex);
880 if (ret)
881 return ret;
882
647416f9 883 *val = dev_priv->next_seqno;
40633219
MK		 884 mutex_unlock(&dev->struct_mutex);
885
647416f9 886 return 0;
40633219
MK		 887}
888
647416f9
KC		 889static int
890i915_next_seqno_set(void *data, u64 val)
891{
892 struct drm_device *dev = data;
40633219
MK		 893 int ret;
894
40633219
MK		 895 ret = mutex_lock_interruptible(&dev->struct_mutex);
896 if (ret)
897 return ret;
898
e94fbaa8 899 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 900 mutex_unlock(&dev->struct_mutex);
901
647416f9 902 return ret;
40633219
MK		 903}
904
647416f9
KC		 905DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
906 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 907 "0x%llx\n");
40633219 908
f97108d1
JB		 909static int i915_rstdby_delays(struct seq_file *m, void *unused)
910{
911 struct drm_info_node *node = (struct drm_info_node *) m->private;
912 struct drm_device *dev = node->minor->dev;
913 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 914 u16 crstanddelay;
915 int ret;
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
c8c8fb33 920 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 921
922 crstanddelay = I915_READ16(CRSTANDVID);
923
c8c8fb33 924 intel_runtime_pm_put(dev_priv);
616fdb5a 925 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 926
927 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
928
929 return 0;
930}
931
932static int i915_cur_delayinfo(struct seq_file *m, void *unused)
933{
934 struct drm_info_node *node = (struct drm_info_node *) m->private;
935 struct drm_device *dev = node->minor->dev;
936 drm_i915_private_t *dev_priv = dev->dev_private;
c8c8fb33
PZ		 937 int ret = 0;
938
939 intel_runtime_pm_get(dev_priv);
3b8d8d91 940
5c9669ce
TR		 941 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
942
3b8d8d91
JB		 943 if (IS_GEN5(dev)) {
944 u16 rgvswctl = I915_READ16(MEMSWCTL);
945 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
946
947 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
948 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
949 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
950 MEMSTAT_VID_SHIFT);
951 seq_printf(m, "Current P-state: %d\n",
952 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 953 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 954 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
955 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
956 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 957 u32 rpstat, cagf, reqf;
ccab5c82
JB		 958 u32 rpupei, rpcurup, rpprevup;
959 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 960 int max_freq;
961
962 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 963 ret = mutex_lock_interruptible(&dev->struct_mutex);
964 if (ret)
c8c8fb33 965 goto out;
d1ebd816 966
c8d9a590 967 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 968
8e8c06cd
CW		 969 reqf = I915_READ(GEN6_RPNSWREQ);
970 reqf &= ~GEN6_TURBO_DISABLE;
971 if (IS_HASWELL(dev))
972 reqf >>= 24;
973 else
974 reqf >>= 25;
975 reqf *= GT_FREQUENCY_MULTIPLIER;
976
ccab5c82
JB		 977 rpstat = I915_READ(GEN6_RPSTAT1);
978 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
979 rpcurup = I915_READ(GEN6_RP_CUR_UP);
980 rpprevup = I915_READ(GEN6_RP_PREV_UP);
981 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
982 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
983 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 984 if (IS_HASWELL(dev))
985 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
986 else
987 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
988 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 989
c8d9a590 990 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 991 mutex_unlock(&dev->struct_mutex);
992
3b8d8d91 993 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 994 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 995 seq_printf(m, "Render p-state ratio: %d\n",
996 (gt_perf_status & 0xff00) >> 8);
997 seq_printf(m, "Render p-state VID: %d\n",
998 gt_perf_status & 0xff);
999 seq_printf(m, "Render p-state limit: %d\n",
1000 rp_state_limits & 0xff);
8e8c06cd 1001 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1002 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1003 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1004 GEN6_CURICONT_MASK);
1005 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1006 GEN6_CURBSYTAVG_MASK);
1007 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1008 GEN6_CURBSYTAVG_MASK);
1009 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1010 GEN6_CURIAVG_MASK);
1011 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1012 GEN6_CURBSYTAVG_MASK);
1013 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1014 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1015
1016 max_freq = (rp_state_cap & 0xff0000) >> 16;
1017 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1018 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1019
1020 max_freq = (rp_state_cap & 0xff00) >> 8;
1021 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1022 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1023
1024 max_freq = rp_state_cap & 0xff;
1025 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1026 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1027
1028 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1029 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1030 } else if (IS_VALLEYVIEW(dev)) {
1031 u32 freq_sts, val;
1032
259bd5d4 1033 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1034 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1035 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1036 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1037
c5bd2bf6 1038 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1039 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1040 vlv_gpu_freq(dev_priv, val));
0a073b84 1041
c5bd2bf6 1042 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1043 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1044 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1045
1046 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1047 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1048 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1049 } else {
267f0c90 1050 seq_puts(m, "no P-state info available\n");
3b8d8d91 1051 }
f97108d1 1052
c8c8fb33
PZ		 1053out:
1054 intel_runtime_pm_put(dev_priv);
1055 return ret;
f97108d1
JB		 1056}
1057
1058static int i915_delayfreq_table(struct seq_file *m, void *unused)
1059{
1060 struct drm_info_node *node = (struct drm_info_node *) m->private;
1061 struct drm_device *dev = node->minor->dev;
1062 drm_i915_private_t *dev_priv = dev->dev_private;
1063 u32 delayfreq;
616fdb5a
BW		 1064 int ret, i;
1065
1066 ret = mutex_lock_interruptible(&dev->struct_mutex);
1067 if (ret)
1068 return ret;
c8c8fb33 1069 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1070
1071 for (i = 0; i < 16; i++) {
1072 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1073 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1074 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1075 }
1076
c8c8fb33
PZ		 1077 intel_runtime_pm_put(dev_priv);
1078
616fdb5a
BW		 1079 mutex_unlock(&dev->struct_mutex);
1080
f97108d1
JB		 1081 return 0;
1082}
1083
1084static inline int MAP_TO_MV(int map)
1085{
1086 return 1250 - (map * 25);
1087}
1088
1089static int i915_inttoext_table(struct seq_file *m, void *unused)
1090{
1091 struct drm_info_node *node = (struct drm_info_node *) m->private;
1092 struct drm_device *dev = node->minor->dev;
1093 drm_i915_private_t *dev_priv = dev->dev_private;
1094 u32 inttoext;
616fdb5a
BW		 1095 int ret, i;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
c8c8fb33 1100 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1101
1102 for (i = 1; i <= 32; i++) {
1103 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1104 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1105 }
1106
c8c8fb33 1107 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1108 mutex_unlock(&dev->struct_mutex);
1109
f97108d1
JB		 1110 return 0;
1111}
1112
4d85529d 1113static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1114{
1115 struct drm_info_node *node = (struct drm_info_node *) m->private;
1116 struct drm_device *dev = node->minor->dev;
1117 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1118 u32 rgvmodectl, rstdbyctl;
1119 u16 crstandvid;
1120 int ret;
1121
1122 ret = mutex_lock_interruptible(&dev->struct_mutex);
1123 if (ret)
1124 return ret;
c8c8fb33 1125 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1126
1127 rgvmodectl = I915_READ(MEMMODECTL);
1128 rstdbyctl = I915_READ(RSTDBYCTL);
1129 crstandvid = I915_READ16(CRSTANDVID);
1130
c8c8fb33 1131 intel_runtime_pm_put(dev_priv);
616fdb5a 1132 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1133
1134 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1135 "yes" : "no");
1136 seq_printf(m, "Boost freq: %d\n",
1137 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1138 MEMMODE_BOOST_FREQ_SHIFT);
1139 seq_printf(m, "HW control enabled: %s\n",
1140 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1141 seq_printf(m, "SW control enabled: %s\n",
1142 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1143 seq_printf(m, "Gated voltage change: %s\n",
1144 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1145 seq_printf(m, "Starting frequency: P%d\n",
1146 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1147 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1148 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1149 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1150 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1151 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1152 seq_printf(m, "Render standby enabled: %s\n",
1153 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1154 seq_puts(m, "Current RS state: ");
88271da3
JB		 1155 switch (rstdbyctl & RSX_STATUS_MASK) {
1156 case RSX_STATUS_ON:
267f0c90 1157 seq_puts(m, "on\n");
88271da3
JB		 1158 break;
1159 case RSX_STATUS_RC1:
267f0c90 1160 seq_puts(m, "RC1\n");
88271da3
JB		 1161 break;
1162 case RSX_STATUS_RC1E:
267f0c90 1163 seq_puts(m, "RC1E\n");
88271da3
JB		 1164 break;
1165 case RSX_STATUS_RS1:
267f0c90 1166 seq_puts(m, "RS1\n");
88271da3
JB		 1167 break;
1168 case RSX_STATUS_RS2:
267f0c90 1169 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1170 break;
1171 case RSX_STATUS_RS3:
267f0c90 1172 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1173 break;
1174 default:
267f0c90 1175 seq_puts(m, "unknown\n");
88271da3
JB		 1176 break;
1177 }
f97108d1
JB		 1178
1179 return 0;
1180}
1181
669ab5aa
D		 1182static int vlv_drpc_info(struct seq_file *m)
1183{
1184
1185 struct drm_info_node *node = (struct drm_info_node *) m->private;
1186 struct drm_device *dev = node->minor->dev;
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 u32 rpmodectl1, rcctl1;
1189 unsigned fw_rendercount = 0, fw_mediacount = 0;
1190
1191 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1192 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1193
1194 seq_printf(m, "Video Turbo Mode: %s\n",
1195 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1196 seq_printf(m, "Turbo enabled: %s\n",
1197 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1198 seq_printf(m, "HW control enabled: %s\n",
1199 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1200 seq_printf(m, "SW control enabled: %s\n",
1201 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1202 GEN6_RP_MEDIA_SW_MODE));
1203 seq_printf(m, "RC6 Enabled: %s\n",
1204 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1205 GEN6_RC_CTL_EI_MODE(1))));
1206 seq_printf(m, "Render Power Well: %s\n",
1207 (I915_READ(VLV_GTLC_PW_STATUS) &
1208 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1209 seq_printf(m, "Media Power Well: %s\n",
1210 (I915_READ(VLV_GTLC_PW_STATUS) &
1211 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1212
1213 spin_lock_irq(&dev_priv->uncore.lock);
1214 fw_rendercount = dev_priv->uncore.fw_rendercount;
1215 fw_mediacount = dev_priv->uncore.fw_mediacount;
1216 spin_unlock_irq(&dev_priv->uncore.lock);
1217
1218 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1219 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1220
1221
1222 return 0;
1223}
1224
1225
4d85529d
BW		 1226static int gen6_drpc_info(struct seq_file *m)
1227{
1228
1229 struct drm_info_node *node = (struct drm_info_node *) m->private;
1230 struct drm_device *dev = node->minor->dev;
1231 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1232 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1233 unsigned forcewake_count;
aee56cff 1234 int count = 0, ret;
4d85529d
BW		 1235
1236 ret = mutex_lock_interruptible(&dev->struct_mutex);
1237 if (ret)
1238 return ret;
c8c8fb33 1239 intel_runtime_pm_get(dev_priv);
4d85529d 1240
907b28c5
CW		 1241 spin_lock_irq(&dev_priv->uncore.lock);
1242 forcewake_count = dev_priv->uncore.forcewake_count;
1243 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1244
1245 if (forcewake_count) {
267f0c90
DL		 1246 seq_puts(m, "RC information inaccurate because somebody "
1247 "holds a forcewake reference \n");
4d85529d
BW		 1248 } else {
1249 /* NB: we cannot use forcewake, else we read the wrong values */
1250 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1251 udelay(10);
1252 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1253 }
1254
1255 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1256 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1257
1258 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1259 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1260 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1261 mutex_lock(&dev_priv->rps.hw_lock);
1262 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1263 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1264
c8c8fb33
PZ		 1265 intel_runtime_pm_put(dev_priv);
1266
4d85529d
BW		 1267 seq_printf(m, "Video Turbo Mode: %s\n",
1268 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1269 seq_printf(m, "HW control enabled: %s\n",
1270 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1271 seq_printf(m, "SW control enabled: %s\n",
1272 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1273 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1274 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1275 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1276 seq_printf(m, "RC6 Enabled: %s\n",
1277 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1278 seq_printf(m, "Deep RC6 Enabled: %s\n",
1279 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1280 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1281 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1282 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1283 switch (gt_core_status & GEN6_RCn_MASK) {
1284 case GEN6_RC0:
1285 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1286 seq_puts(m, "Core Power Down\n");
4d85529d 1287 else
267f0c90 1288 seq_puts(m, "on\n");
4d85529d
BW		 1289 break;
1290 case GEN6_RC3:
267f0c90 1291 seq_puts(m, "RC3\n");
4d85529d
BW		 1292 break;
1293 case GEN6_RC6:
267f0c90 1294 seq_puts(m, "RC6\n");
4d85529d
BW		 1295 break;
1296 case GEN6_RC7:
267f0c90 1297 seq_puts(m, "RC7\n");
4d85529d
BW		 1298 break;
1299 default:
267f0c90 1300 seq_puts(m, "Unknown\n");
4d85529d
BW		 1301 break;
1302 }
1303
1304 seq_printf(m, "Core Power Down: %s\n",
1305 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1306
1307 /* Not exactly sure what this is */
1308 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1309 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1310 seq_printf(m, "RC6 residency since boot: %u\n",
1311 I915_READ(GEN6_GT_GFX_RC6));
1312 seq_printf(m, "RC6+ residency since boot: %u\n",
1313 I915_READ(GEN6_GT_GFX_RC6p));
1314 seq_printf(m, "RC6++ residency since boot: %u\n",
1315 I915_READ(GEN6_GT_GFX_RC6pp));
1316
ecd8faea
BW		 1317 seq_printf(m, "RC6 voltage: %dmV\n",
1318 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1319 seq_printf(m, "RC6+ voltage: %dmV\n",
1320 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1321 seq_printf(m, "RC6++ voltage: %dmV\n",
1322 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1323 return 0;
1324}
1325
1326static int i915_drpc_info(struct seq_file *m, void *unused)
1327{
1328 struct drm_info_node *node = (struct drm_info_node *) m->private;
1329 struct drm_device *dev = node->minor->dev;
1330
669ab5aa
D		 1331 if (IS_VALLEYVIEW(dev))
1332 return vlv_drpc_info(m);
1333 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1334 return gen6_drpc_info(m);
1335 else
1336 return ironlake_drpc_info(m);
1337}
1338
b5e50c3f
JB		 1339static int i915_fbc_status(struct seq_file *m, void *unused)
1340{
1341 struct drm_info_node *node = (struct drm_info_node *) m->private;
1342 struct drm_device *dev = node->minor->dev;
b5e50c3f 1343 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1344
3a77c4c4 1345 if (!HAS_FBC(dev)) {
267f0c90 1346 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1347 return 0;
1348 }
1349
36623ef8
PZ		 1350 intel_runtime_pm_get(dev_priv);
1351
ee5382ae 1352 if (intel_fbc_enabled(dev)) {
267f0c90 1353 seq_puts(m, "FBC enabled\n");
b5e50c3f 1354 } else {
267f0c90 1355 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1356 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1357 case FBC_OK:
1358 seq_puts(m, "FBC actived, but currently disabled in hardware");
1359 break;
1360 case FBC_UNSUPPORTED:
1361 seq_puts(m, "unsupported by this chipset");
1362 break;
bed4a673 1363 case FBC_NO_OUTPUT:
267f0c90 1364 seq_puts(m, "no outputs");
bed4a673 1365 break;
b5e50c3f 1366 case FBC_STOLEN_TOO_SMALL:
267f0c90 1367 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1368 break;
1369 case FBC_UNSUPPORTED_MODE:
267f0c90 1370 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1371 break;
1372 case FBC_MODE_TOO_LARGE:
267f0c90 1373 seq_puts(m, "mode too large");
b5e50c3f
JB		 1374 break;
1375 case FBC_BAD_PLANE:
267f0c90 1376 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1377 break;
1378 case FBC_NOT_TILED:
267f0c90 1379 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1380 break;
9c928d16 1381 case FBC_MULTIPLE_PIPES:
267f0c90 1382 seq_puts(m, "multiple pipes are enabled");
9c928d16 1383 break;
c1a9f047 1384 case FBC_MODULE_PARAM:
267f0c90 1385 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1386 break;
8a5729a3 1387 case FBC_CHIP_DEFAULT:
267f0c90 1388 seq_puts(m, "disabled per chip default");
8a5729a3 1389 break;
b5e50c3f 1390 default:
267f0c90 1391 seq_puts(m, "unknown reason");
b5e50c3f 1392 }
267f0c90 1393 seq_putc(m, '\n');
b5e50c3f 1394 }
36623ef8
PZ		 1395
1396 intel_runtime_pm_put(dev_priv);
1397
b5e50c3f
JB		 1398 return 0;
1399}
1400
92d44621
PZ		 1401static int i915_ips_status(struct seq_file *m, void *unused)
1402{
1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1404 struct drm_device *dev = node->minor->dev;
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406
f5adf94e 1407 if (!HAS_IPS(dev)) {
92d44621
PZ		 1408 seq_puts(m, "not supported\n");
1409 return 0;
1410 }
1411
36623ef8
PZ		 1412 intel_runtime_pm_get(dev_priv);
1413
e59150dc 1414 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1415 seq_puts(m, "enabled\n");
1416 else
1417 seq_puts(m, "disabled\n");
1418
36623ef8
PZ		 1419 intel_runtime_pm_put(dev_priv);
1420
92d44621
PZ		 1421 return 0;
1422}
1423
4a9bef37
JB		 1424static int i915_sr_status(struct seq_file *m, void *unused)
1425{
1426 struct drm_info_node *node = (struct drm_info_node *) m->private;
1427 struct drm_device *dev = node->minor->dev;
1428 drm_i915_private_t *dev_priv = dev->dev_private;
1429 bool sr_enabled = false;
1430
36623ef8
PZ		 1431 intel_runtime_pm_get(dev_priv);
1432
1398261a 1433 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1434 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1435 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1436 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1437 else if (IS_I915GM(dev))
1438 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1439 else if (IS_PINEVIEW(dev))
1440 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1441
36623ef8
PZ		 1442 intel_runtime_pm_put(dev_priv);
1443
5ba2aaaa
CW		 1444 seq_printf(m, "self-refresh: %s\n",
1445 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1446
1447 return 0;
1448}
1449
7648fa99
JB		 1450static int i915_emon_status(struct seq_file *m, void *unused)
1451{
1452 struct drm_info_node *node = (struct drm_info_node *) m->private;
1453 struct drm_device *dev = node->minor->dev;
1454 drm_i915_private_t *dev_priv = dev->dev_private;
1455 unsigned long temp, chipset, gfx;
de227ef0
CW		 1456 int ret;
1457
582be6b4
CW		 1458 if (!IS_GEN5(dev))
1459 return -ENODEV;
1460
de227ef0
CW		 1461 ret = mutex_lock_interruptible(&dev->struct_mutex);
1462 if (ret)
1463 return ret;
7648fa99
JB		 1464
1465 temp = i915_mch_val(dev_priv);
1466 chipset = i915_chipset_val(dev_priv);
1467 gfx = i915_gfx_val(dev_priv);
de227ef0 1468 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1469
1470 seq_printf(m, "GMCH temp: %ld\n", temp);
1471 seq_printf(m, "Chipset power: %ld\n", chipset);
1472 seq_printf(m, "GFX power: %ld\n", gfx);
1473 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1474
1475 return 0;
1476}
1477
23b2f8bb
JB		 1478static int i915_ring_freq_table(struct seq_file *m, void *unused)
1479{
1480 struct drm_info_node *node = (struct drm_info_node *) m->private;
1481 struct drm_device *dev = node->minor->dev;
1482 drm_i915_private_t *dev_priv = dev->dev_private;
5bfa0199 1483 int ret = 0;
23b2f8bb
JB		 1484 int gpu_freq, ia_freq;
1485
1c70c0ce 1486 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1487 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1488 return 0;
1489 }
1490
5bfa0199
PZ		 1491 intel_runtime_pm_get(dev_priv);
1492
5c9669ce
TR		 1493 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1494
4fc688ce 1495 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1496 if (ret)
5bfa0199 1497 goto out;
23b2f8bb 1498
267f0c90 1499 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1500
c6a828d3
DV		 1501 for (gpu_freq = dev_priv->rps.min_delay;
1502 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1503 gpu_freq++) {
42c0526c
BW		 1504 ia_freq = gpu_freq;
1505 sandybridge_pcode_read(dev_priv,
1506 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1507 &ia_freq);
3ebecd07
CW		 1508 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1509 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1510 ((ia_freq >> 0) & 0xff) * 100,
1511 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1512 }
1513
4fc688ce 1514 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1515
5bfa0199
PZ		 1516out:
1517 intel_runtime_pm_put(dev_priv);
1518 return ret;
23b2f8bb
JB		 1519}
1520
7648fa99
JB		 1521static int i915_gfxec(struct seq_file *m, void *unused)
1522{
1523 struct drm_info_node *node = (struct drm_info_node *) m->private;
1524 struct drm_device *dev = node->minor->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1526 int ret;
1527
1528 ret = mutex_lock_interruptible(&dev->struct_mutex);
1529 if (ret)
1530 return ret;
c8c8fb33 1531 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1532
1533 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1534 intel_runtime_pm_put(dev_priv);
7648fa99 1535
616fdb5a
BW		 1536 mutex_unlock(&dev->struct_mutex);
1537
7648fa99
JB		 1538 return 0;
1539}
1540
44834a67
CW		 1541static int i915_opregion(struct seq_file *m, void *unused)
1542{
1543 struct drm_info_node *node = (struct drm_info_node *) m->private;
1544 struct drm_device *dev = node->minor->dev;
1545 drm_i915_private_t *dev_priv = dev->dev_private;
1546 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1547 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1548 int ret;
1549
0d38f009
DV		 1550 if (data == NULL)
1551 return -ENOMEM;
1552
44834a67
CW		 1553 ret = mutex_lock_interruptible(&dev->struct_mutex);
1554 if (ret)
0d38f009 1555 goto out;
44834a67 1556
0d38f009
DV		 1557 if (opregion->header) {
1558 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1559 seq_write(m, data, OPREGION_SIZE);
1560 }
44834a67
CW		 1561
1562 mutex_unlock(&dev->struct_mutex);
1563
0d38f009
DV		 1564out:
1565 kfree(data);
44834a67
CW		 1566 return 0;
1567}
1568
37811fcc
CW		 1569static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1570{
1571 struct drm_info_node *node = (struct drm_info_node *) m->private;
1572 struct drm_device *dev = node->minor->dev;
4520f53a 1573 struct intel_fbdev *ifbdev = NULL;
37811fcc 1574 struct intel_framebuffer *fb;
37811fcc 1575
4520f53a
DV		 1576#ifdef CONFIG_DRM_I915_FBDEV
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1579 if (ret)
1580 return ret;
1581
1582 ifbdev = dev_priv->fbdev;
1583 fb = to_intel_framebuffer(ifbdev->helper.fb);
1584
623f9783 1585 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1586 fb->base.width,
1587 fb->base.height,
1588 fb->base.depth,
623f9783
DV		 1589 fb->base.bits_per_pixel,
1590 atomic_read(&fb->base.refcount.refcount));
05394f39 1591 describe_obj(m, fb->obj);
267f0c90 1592 seq_putc(m, '\n');
4b096ac1 1593 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1594#endif
37811fcc 1595
4b096ac1 1596 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1597 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1598 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1599 continue;
1600
623f9783 1601 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1602 fb->base.width,
1603 fb->base.height,
1604 fb->base.depth,
623f9783
DV		 1605 fb->base.bits_per_pixel,
1606 atomic_read(&fb->base.refcount.refcount));
05394f39 1607 describe_obj(m, fb->obj);
267f0c90 1608 seq_putc(m, '\n');
37811fcc 1609 }
4b096ac1 1610 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1611
1612 return 0;
1613}
1614
e76d3630
BW		 1615static int i915_context_status(struct seq_file *m, void *unused)
1616{
1617 struct drm_info_node *node = (struct drm_info_node *) m->private;
1618 struct drm_device *dev = node->minor->dev;
1619 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1620 struct intel_ring_buffer *ring;
a33afea5 1621 struct i915_hw_context *ctx;
a168c293 1622 int ret, i;
e76d3630
BW		 1623
1624 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1625 if (ret)
1626 return ret;
1627
3e373948 1628 if (dev_priv->ips.pwrctx) {
267f0c90 1629 seq_puts(m, "power context ");
3e373948 1630 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1631 seq_putc(m, '\n');
dc501fbc 1632 }
e76d3630 1633
3e373948 1634 if (dev_priv->ips.renderctx) {
267f0c90 1635 seq_puts(m, "render context ");
3e373948 1636 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1637 seq_putc(m, '\n');
dc501fbc 1638 }
e76d3630 1639
a33afea5
BW		 1640 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1641 seq_puts(m, "HW context ");
3ccfd19d 1642 describe_ctx(m, ctx);
a33afea5
BW		 1643 for_each_ring(ring, dev_priv, i)
1644 if (ring->default_context == ctx)
1645 seq_printf(m, "(default context %s) ", ring->name);
1646
1647 describe_obj(m, ctx->obj);
1648 seq_putc(m, '\n');
a168c293
BW		 1649 }
1650
e76d3630
BW		 1651 mutex_unlock(&dev->mode_config.mutex);
1652
1653 return 0;
1654}
1655
6d794d42
BW		 1656static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1657{
1658 struct drm_info_node *node = (struct drm_info_node *) m->private;
1659 struct drm_device *dev = node->minor->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1661 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1662
907b28c5 1663 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1664 if (IS_VALLEYVIEW(dev)) {
1665 fw_rendercount = dev_priv->uncore.fw_rendercount;
1666 fw_mediacount = dev_priv->uncore.fw_mediacount;
1667 } else
1668 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1669 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1670
43709ba0
D		 1671 if (IS_VALLEYVIEW(dev)) {
1672 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1673 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1674 } else
1675 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1676
1677 return 0;
1678}
1679
ea16a3cd
DV		 1680static const char *swizzle_string(unsigned swizzle)
1681{
aee56cff 1682 switch (swizzle) {
ea16a3cd
DV		 1683 case I915_BIT_6_SWIZZLE_NONE:
1684 return "none";
1685 case I915_BIT_6_SWIZZLE_9:
1686 return "bit9";
1687 case I915_BIT_6_SWIZZLE_9_10:
1688 return "bit9/bit10";
1689 case I915_BIT_6_SWIZZLE_9_11:
1690 return "bit9/bit11";
1691 case I915_BIT_6_SWIZZLE_9_10_11:
1692 return "bit9/bit10/bit11";
1693 case I915_BIT_6_SWIZZLE_9_17:
1694 return "bit9/bit17";
1695 case I915_BIT_6_SWIZZLE_9_10_17:
1696 return "bit9/bit10/bit17";
1697 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1698 return "unknown";
ea16a3cd
DV		 1699 }
1700
1701 return "bug";
1702}
1703
1704static int i915_swizzle_info(struct seq_file *m, void *data)
1705{
1706 struct drm_info_node *node = (struct drm_info_node *) m->private;
1707 struct drm_device *dev = node->minor->dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1709 int ret;
1710
1711 ret = mutex_lock_interruptible(&dev->struct_mutex);
1712 if (ret)
1713 return ret;
c8c8fb33 1714 intel_runtime_pm_get(dev_priv);
ea16a3cd 1715
ea16a3cd
DV		 1716 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1717 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1718 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1719 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1720
1721 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1722 seq_printf(m, "DDC = 0x%08x\n",
1723 I915_READ(DCC));
1724 seq_printf(m, "C0DRB3 = 0x%04x\n",
1725 I915_READ16(C0DRB3));
1726 seq_printf(m, "C1DRB3 = 0x%04x\n",
1727 I915_READ16(C1DRB3));
9d3203e1 1728 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1729 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1730 I915_READ(MAD_DIMM_C0));
1731 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1732 I915_READ(MAD_DIMM_C1));
1733 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1734 I915_READ(MAD_DIMM_C2));
1735 seq_printf(m, "TILECTL = 0x%08x\n",
1736 I915_READ(TILECTL));
9d3203e1
BW		 1737 if (IS_GEN8(dev))
1738 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1739 I915_READ(GAMTARBMODE));
1740 else
1741 seq_printf(m, "ARB_MODE = 0x%08x\n",
1742 I915_READ(ARB_MODE));
3fa7d235
DV		 1743 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1744 I915_READ(DISP_ARB_CTL));
ea16a3cd 1745 }
c8c8fb33 1746 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1747 mutex_unlock(&dev->struct_mutex);
1748
1749 return 0;
1750}
1751
1c60fef5
BW		 1752static int per_file_ctx(int id, void *ptr, void *data)
1753{
1754 struct i915_hw_context *ctx = ptr;
1755 struct seq_file *m = data;
1756 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1757
1758 ppgtt->debug_dump(ppgtt, m);
1759
1760 return 0;
1761}
1762
77df6772 1763static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1764{
3cf17fc5
DV		 1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_ring_buffer *ring;
77df6772
BW		 1767 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1768 int unused, i;
3cf17fc5 1769
77df6772
BW		 1770 if (!ppgtt)
1771 return;
1772
1773 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1774 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1775 for_each_ring(ring, dev_priv, unused) {
1776 seq_printf(m, "%s\n", ring->name);
1777 for (i = 0; i < 4; i++) {
1778 u32 offset = 0x270 + i * 8;
1779 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1780 pdp <<= 32;
1781 pdp |= I915_READ(ring->mmio_base + offset);
1782 for (i = 0; i < 4; i++)
1783 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1784 }
1785 }
1786}
1787
1788static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1789{
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct intel_ring_buffer *ring;
1c60fef5 1792 struct drm_file *file;
77df6772 1793 int i;
3cf17fc5 1794
3cf17fc5
DV		 1795 if (INTEL_INFO(dev)->gen == 6)
1796 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1797
a2c7f6fd 1798 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1799 seq_printf(m, "%s\n", ring->name);
1800 if (INTEL_INFO(dev)->gen == 7)
1801 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1802 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1803 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1804 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1805 }
1806 if (dev_priv->mm.aliasing_ppgtt) {
1807 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1808
267f0c90 1809 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1810 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1811
87d60b63 1812 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1813 } else
1814 return;
1815
1816 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1817 struct drm_i915_file_private *file_priv = file->driver_priv;
1818 struct i915_hw_ppgtt *pvt_ppgtt;
1819
1820 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1821 seq_printf(m, "proc: %s\n",
1822 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1823 seq_puts(m, " default context:\n");
1824 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1825 }
1826 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1827}
1828
1829static int i915_ppgtt_info(struct seq_file *m, void *data)
1830{
1831 struct drm_info_node *node = (struct drm_info_node *) m->private;
1832 struct drm_device *dev = node->minor->dev;
c8c8fb33 1833 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1834
1835 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1836 if (ret)
1837 return ret;
c8c8fb33 1838 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1839
1840 if (INTEL_INFO(dev)->gen >= 8)
1841 gen8_ppgtt_info(m, dev);
1842 else if (INTEL_INFO(dev)->gen >= 6)
1843 gen6_ppgtt_info(m, dev);
1844
c8c8fb33 1845 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1846 mutex_unlock(&dev->struct_mutex);
1847
1848 return 0;
1849}
1850
57f350b6
JB		 1851static int i915_dpio_info(struct seq_file *m, void *data)
1852{
1853 struct drm_info_node *node = (struct drm_info_node *) m->private;
1854 struct drm_device *dev = node->minor->dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 int ret;
1857
1858
1859 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1860 seq_puts(m, "unsupported\n");
57f350b6
JB		 1861 return 0;
1862 }
1863
09153000 1864 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1865 if (ret)
1866 return ret;
1867
1868 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1869
ab3c759a
CML		 1870 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1871 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1872 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1873 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1874
1875 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1876 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1877 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1878 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1879
1880 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1881 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1882 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1883 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1884
1885 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1886 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1887 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1888 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1889
1890 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1891 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1892
09153000 1893 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1894
1895 return 0;
1896}
1897
63573eb7
BW		 1898static int i915_llc(struct seq_file *m, void *data)
1899{
1900 struct drm_info_node *node = (struct drm_info_node *) m->private;
1901 struct drm_device *dev = node->minor->dev;
1902 struct drm_i915_private *dev_priv = dev->dev_private;
1903
1904 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1905 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1906 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1907
1908 return 0;
1909}
1910
e91fd8c6
RV		 1911static int i915_edp_psr_status(struct seq_file *m, void *data)
1912{
1913 struct drm_info_node *node = m->private;
1914 struct drm_device *dev = node->minor->dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1916 u32 psrperf = 0;
1917 bool enabled = false;
e91fd8c6 1918
c8c8fb33
PZ		 1919 intel_runtime_pm_get(dev_priv);
1920
a031d709
RV		 1921 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1922 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1923
a031d709
RV		 1924 enabled = HAS_PSR(dev) &&
1925 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1926 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1927
a031d709
RV		 1928 if (HAS_PSR(dev))
1929 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1930 EDP_PSR_PERF_CNT_MASK;
1931 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1932
c8c8fb33 1933 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1934 return 0;
1935}
1936
d2e216d0
RV		 1937static int i915_sink_crc(struct seq_file *m, void *data)
1938{
1939 struct drm_info_node *node = m->private;
1940 struct drm_device *dev = node->minor->dev;
1941 struct intel_encoder *encoder;
1942 struct intel_connector *connector;
1943 struct intel_dp *intel_dp = NULL;
1944 int ret;
1945 u8 crc[6];
1946
1947 drm_modeset_lock_all(dev);
1948 list_for_each_entry(connector, &dev->mode_config.connector_list,
1949 base.head) {
1950
1951 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1952 continue;
1953
b6ae3c7c
PZ		 1954 if (!connector->base.encoder)
1955 continue;
1956
d2e216d0
RV		 1957 encoder = to_intel_encoder(connector->base.encoder);
1958 if (encoder->type != INTEL_OUTPUT_EDP)
1959 continue;
1960
1961 intel_dp = enc_to_intel_dp(&encoder->base);
1962
1963 ret = intel_dp_sink_crc(intel_dp, crc);
1964 if (ret)
1965 goto out;
1966
1967 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1968 crc[0], crc[1], crc[2],
1969 crc[3], crc[4], crc[5]);
1970 goto out;
1971 }
1972 ret = -ENODEV;
1973out:
1974 drm_modeset_unlock_all(dev);
1975 return ret;
1976}
1977
ec013e7f
JB		 1978static int i915_energy_uJ(struct seq_file *m, void *data)
1979{
1980 struct drm_info_node *node = m->private;
1981 struct drm_device *dev = node->minor->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 u64 power;
1984 u32 units;
1985
1986 if (INTEL_INFO(dev)->gen < 6)
1987 return -ENODEV;
1988
36623ef8
PZ		 1989 intel_runtime_pm_get(dev_priv);
1990
ec013e7f
JB		 1991 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1992 power = (power & 0x1f00) >> 8;
1993 units = 1000000 / (1 << power); /* convert to uJ */
1994 power = I915_READ(MCH_SECP_NRG_STTS);
1995 power *= units;
1996
36623ef8
PZ		 1997 intel_runtime_pm_put(dev_priv);
1998
ec013e7f 1999 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2000
2001 return 0;
2002}
2003
2004static int i915_pc8_status(struct seq_file *m, void *unused)
2005{
2006 struct drm_info_node *node = (struct drm_info_node *) m->private;
2007 struct drm_device *dev = node->minor->dev;
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009
2010 if (!IS_HASWELL(dev)) {
2011 seq_puts(m, "not supported\n");
2012 return 0;
2013 }
2014
2015 mutex_lock(&dev_priv->pc8.lock);
2016 seq_printf(m, "Requirements met: %s\n",
2017 yesno(dev_priv->pc8.requirements_met));
86c4ec0d 2018 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a
PZ		 2019 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
2020 seq_printf(m, "IRQs disabled: %s\n",
2021 yesno(dev_priv->pc8.irqs_disabled));
2022 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2023 mutex_unlock(&dev_priv->pc8.lock);
2024
ec013e7f
JB		 2025 return 0;
2026}
2027
1da51581
ID		 2028static const char *power_domain_str(enum intel_display_power_domain domain)
2029{
2030 switch (domain) {
2031 case POWER_DOMAIN_PIPE_A:
2032 return "PIPE_A";
2033 case POWER_DOMAIN_PIPE_B:
2034 return "PIPE_B";
2035 case POWER_DOMAIN_PIPE_C:
2036 return "PIPE_C";
2037 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2038 return "PIPE_A_PANEL_FITTER";
2039 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2040 return "PIPE_B_PANEL_FITTER";
2041 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2042 return "PIPE_C_PANEL_FITTER";
2043 case POWER_DOMAIN_TRANSCODER_A:
2044 return "TRANSCODER_A";
2045 case POWER_DOMAIN_TRANSCODER_B:
2046 return "TRANSCODER_B";
2047 case POWER_DOMAIN_TRANSCODER_C:
2048 return "TRANSCODER_C";
2049 case POWER_DOMAIN_TRANSCODER_EDP:
2050 return "TRANSCODER_EDP";
2051 case POWER_DOMAIN_VGA:
2052 return "VGA";
2053 case POWER_DOMAIN_AUDIO:
2054 return "AUDIO";
2055 case POWER_DOMAIN_INIT:
2056 return "INIT";
2057 default:
2058 WARN_ON(1);
2059 return "?";
2060 }
2061}
2062
2063static int i915_power_domain_info(struct seq_file *m, void *unused)
2064{
2065 struct drm_info_node *node = (struct drm_info_node *) m->private;
2066 struct drm_device *dev = node->minor->dev;
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2069 int i;
2070
2071 mutex_lock(&power_domains->lock);
2072
2073 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2074 for (i = 0; i < power_domains->power_well_count; i++) {
2075 struct i915_power_well *power_well;
2076 enum intel_display_power_domain power_domain;
2077
2078 power_well = &power_domains->power_wells[i];
2079 seq_printf(m, "%-25s %d\n", power_well->name,
2080 power_well->count);
2081
2082 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2083 power_domain++) {
2084 if (!(BIT(power_domain) & power_well->domains))
2085 continue;
2086
2087 seq_printf(m, " %-23s %d\n",
2088 power_domain_str(power_domain),
2089 power_domains->domain_use_count[power_domain]);
2090 }
2091 }
2092
2093 mutex_unlock(&power_domains->lock);
2094
2095 return 0;
2096}
2097
53f5e3ca
JB		 2098static void intel_seq_print_mode(struct seq_file *m, int tabs,
2099 struct drm_display_mode *mode)
2100{
2101 int i;
2102
2103 for (i = 0; i < tabs; i++)
2104 seq_putc(m, '\t');
2105
2106 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2107 mode->base.id, mode->name,
2108 mode->vrefresh, mode->clock,
2109 mode->hdisplay, mode->hsync_start,
2110 mode->hsync_end, mode->htotal,
2111 mode->vdisplay, mode->vsync_start,
2112 mode->vsync_end, mode->vtotal,
2113 mode->type, mode->flags);
2114}
2115
2116static void intel_encoder_info(struct seq_file *m,
2117 struct intel_crtc *intel_crtc,
2118 struct intel_encoder *intel_encoder)
2119{
2120 struct drm_info_node *node = (struct drm_info_node *) m->private;
2121 struct drm_device *dev = node->minor->dev;
2122 struct drm_crtc *crtc = &intel_crtc->base;
2123 struct intel_connector *intel_connector;
2124 struct drm_encoder *encoder;
2125
2126 encoder = &intel_encoder->base;
2127 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2128 encoder->base.id, drm_get_encoder_name(encoder));
2129 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2130 struct drm_connector *connector = &intel_connector->base;
2131 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2132 connector->base.id,
2133 drm_get_connector_name(connector),
2134 drm_get_connector_status_name(connector->status));
2135 if (connector->status == connector_status_connected) {
2136 struct drm_display_mode *mode = &crtc->mode;
2137 seq_printf(m, ", mode:\n");
2138 intel_seq_print_mode(m, 2, mode);
2139 } else {
2140 seq_putc(m, '\n');
2141 }
2142 }
2143}
2144
2145static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2146{
2147 struct drm_info_node *node = (struct drm_info_node *) m->private;
2148 struct drm_device *dev = node->minor->dev;
2149 struct drm_crtc *crtc = &intel_crtc->base;
2150 struct intel_encoder *intel_encoder;
2151
2152 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2153 crtc->fb->base.id, crtc->x, crtc->y,
2154 crtc->fb->width, crtc->fb->height);
2155 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2156 intel_encoder_info(m, intel_crtc, intel_encoder);
2157}
2158
2159static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2160{
2161 struct drm_display_mode *mode = panel->fixed_mode;
2162
2163 seq_printf(m, "\tfixed mode:\n");
2164 intel_seq_print_mode(m, 2, mode);
2165}
2166
2167static void intel_dp_info(struct seq_file *m,
2168 struct intel_connector *intel_connector)
2169{
2170 struct intel_encoder *intel_encoder = intel_connector->encoder;
2171 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2172
2173 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2174 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2175 "no");
2176 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2177 intel_panel_info(m, &intel_connector->panel);
2178}
2179
2180static void intel_hdmi_info(struct seq_file *m,
2181 struct intel_connector *intel_connector)
2182{
2183 struct intel_encoder *intel_encoder = intel_connector->encoder;
2184 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2185
2186 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2187 "no");
2188}
2189
2190static void intel_lvds_info(struct seq_file *m,
2191 struct intel_connector *intel_connector)
2192{
2193 intel_panel_info(m, &intel_connector->panel);
2194}
2195
2196static void intel_connector_info(struct seq_file *m,
2197 struct drm_connector *connector)
2198{
2199 struct intel_connector *intel_connector = to_intel_connector(connector);
2200 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2201 struct drm_display_mode *mode;
53f5e3ca
JB		 2202
2203 seq_printf(m, "connector %d: type %s, status: %s\n",
2204 connector->base.id, drm_get_connector_name(connector),
2205 drm_get_connector_status_name(connector->status));
2206 if (connector->status == connector_status_connected) {
2207 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2208 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2209 connector->display_info.width_mm,
2210 connector->display_info.height_mm);
2211 seq_printf(m, "\tsubpixel order: %s\n",
2212 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2213 seq_printf(m, "\tCEA rev: %d\n",
2214 connector->display_info.cea_rev);
2215 }
2216 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2217 intel_encoder->type == INTEL_OUTPUT_EDP)
2218 intel_dp_info(m, intel_connector);
2219 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2220 intel_hdmi_info(m, intel_connector);
2221 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2222 intel_lvds_info(m, intel_connector);
2223
f103fc7d
JB		 2224 seq_printf(m, "\tmodes:\n");
2225 list_for_each_entry(mode, &connector->modes, head)
2226 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2227}
2228
2229static int i915_display_info(struct seq_file *m, void *unused)
2230{
2231 struct drm_info_node *node = (struct drm_info_node *) m->private;
2232 struct drm_device *dev = node->minor->dev;
2233 struct drm_crtc *crtc;
2234 struct drm_connector *connector;
2235
2236 drm_modeset_lock_all(dev);
2237 seq_printf(m, "CRTC info\n");
2238 seq_printf(m, "---------\n");
2239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241
2242 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2243 crtc->base.id, pipe_name(intel_crtc->pipe),
2244 intel_crtc->active ? "yes" : "no");
2245 if (intel_crtc->active)
2246 intel_crtc_info(m, intel_crtc);
2247 }
2248
2249 seq_printf(m, "\n");
2250 seq_printf(m, "Connector info\n");
2251 seq_printf(m, "--------------\n");
2252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2253 intel_connector_info(m, connector);
2254 }
2255 drm_modeset_unlock_all(dev);
2256
2257 return 0;
2258}
2259
07144428
DL		 2260struct pipe_crc_info {
2261 const char *name;
2262 struct drm_device *dev;
2263 enum pipe pipe;
2264};
2265
2266static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2267{
be5c7a90
DL		 2268 struct pipe_crc_info *info = inode->i_private;
2269 struct drm_i915_private *dev_priv = info->dev->dev_private;
2270 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2271
7eb1c496
DV		 2272 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2273 return -ENODEV;
2274
d538bbdf
DL		 2275 spin_lock_irq(&pipe_crc->lock);
2276
2277 if (pipe_crc->opened) {
2278 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2279 return -EBUSY; /* already open */
2280 }
2281
d538bbdf 2282 pipe_crc->opened = true;
07144428
DL		 2283 filep->private_data = inode->i_private;
2284
d538bbdf
DL		 2285 spin_unlock_irq(&pipe_crc->lock);
2286
07144428
DL		 2287 return 0;
2288}
2289
2290static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2291{
be5c7a90
DL		 2292 struct pipe_crc_info *info = inode->i_private;
2293 struct drm_i915_private *dev_priv = info->dev->dev_private;
2294 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2295
d538bbdf
DL		 2296 spin_lock_irq(&pipe_crc->lock);
2297 pipe_crc->opened = false;
2298 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2299
07144428
DL		 2300 return 0;
2301}
2302
2303/* (6 fields, 8 chars each, space separated (5) + '\n') */
2304#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2305/* account for \'0' */
2306#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2307
2308static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2309{
d538bbdf
DL		 2310 assert_spin_locked(&pipe_crc->lock);
2311 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2312 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2313}
2314
2315static ssize_t
2316i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2317 loff_t *pos)
2318{
2319 struct pipe_crc_info *info = filep->private_data;
2320 struct drm_device *dev = info->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2323 char buf[PIPE_CRC_BUFFER_LEN];
2324 int head, tail, n_entries, n;
2325 ssize_t bytes_read;
2326
2327 /*
2328 * Don't allow user space to provide buffers not big enough to hold
2329 * a line of data.
2330 */
2331 if (count < PIPE_CRC_LINE_LEN)
2332 return -EINVAL;
2333
2334 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2335 return 0;
07144428
DL		 2336
2337 /* nothing to read */
d538bbdf 2338 spin_lock_irq(&pipe_crc->lock);
07144428 2339 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2340 int ret;
2341
2342 if (filep->f_flags & O_NONBLOCK) {
2343 spin_unlock_irq(&pipe_crc->lock);
07144428 2344 return -EAGAIN;
d538bbdf 2345 }
07144428 2346
d538bbdf
DL		 2347 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2348 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2349 if (ret) {
2350 spin_unlock_irq(&pipe_crc->lock);
2351 return ret;
2352 }
8bf1e9f1
SH		 2353 }
2354
07144428 2355 /* We now have one or more entries to read */
d538bbdf
DL		 2356 head = pipe_crc->head;
2357 tail = pipe_crc->tail;
07144428
DL		 2358 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2359 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2360 spin_unlock_irq(&pipe_crc->lock);
2361
07144428
DL		 2362 bytes_read = 0;
2363 n = 0;
2364 do {
b2c88f5b 2365 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2366 int ret;
8bf1e9f1 2367
07144428
DL		 2368 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2369 "%8u %8x %8x %8x %8x %8x\n",
2370 entry->frame, entry->crc[0],
2371 entry->crc[1], entry->crc[2],
2372 entry->crc[3], entry->crc[4]);
2373
2374 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2375 buf, PIPE_CRC_LINE_LEN);
2376 if (ret == PIPE_CRC_LINE_LEN)
2377 return -EFAULT;
b2c88f5b
DL		 2378
2379 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2380 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2381 n++;
2382 } while (--n_entries);
8bf1e9f1 2383
d538bbdf
DL		 2384 spin_lock_irq(&pipe_crc->lock);
2385 pipe_crc->tail = tail;
2386 spin_unlock_irq(&pipe_crc->lock);
2387
07144428
DL		 2388 return bytes_read;
2389}
2390
2391static const struct file_operations i915_pipe_crc_fops = {
2392 .owner = THIS_MODULE,
2393 .open = i915_pipe_crc_open,
2394 .read = i915_pipe_crc_read,
2395 .release = i915_pipe_crc_release,
2396};
2397
2398static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2399 {
2400 .name = "i915_pipe_A_crc",
2401 .pipe = PIPE_A,
2402 },
2403 {
2404 .name = "i915_pipe_B_crc",
2405 .pipe = PIPE_B,
2406 },
2407 {
2408 .name = "i915_pipe_C_crc",
2409 .pipe = PIPE_C,
2410 },
2411};
2412
2413static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2414 enum pipe pipe)
2415{
2416 struct drm_device *dev = minor->dev;
2417 struct dentry *ent;
2418 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2419
2420 info->dev = dev;
2421 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2422 &i915_pipe_crc_fops);
f3c5fe97
WY		 2423 if (!ent)
2424 return -ENOMEM;
07144428
DL		 2425
2426 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2427}
2428
e8dfcf78 2429static const char * const pipe_crc_sources[] = {
926321d5
DV		 2430 "none",
2431 "plane1",
2432 "plane2",
2433 "pf",
5b3a856b 2434 "pipe",
3d099a05
DV		 2435 "TV",
2436 "DP-B",
2437 "DP-C",
2438 "DP-D",
46a19188 2439 "auto",
926321d5
DV		 2440};
2441
2442static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2443{
2444 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2445 return pipe_crc_sources[source];
2446}
2447
bd9db02f 2448static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2449{
2450 struct drm_device *dev = m->private;
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 int i;
2453
2454 for (i = 0; i < I915_MAX_PIPES; i++)
2455 seq_printf(m, "%c %s\n", pipe_name(i),
2456 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2457
2458 return 0;
2459}
2460
bd9db02f 2461static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2462{
2463 struct drm_device *dev = inode->i_private;
2464
bd9db02f 2465 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2466}
2467
46a19188 2468static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2469 uint32_t *val)
2470{
46a19188
DV		 2471 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2472 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2473
2474 switch (*source) {
52f843f6
DV		 2475 case INTEL_PIPE_CRC_SOURCE_PIPE:
2476 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2477 break;
2478 case INTEL_PIPE_CRC_SOURCE_NONE:
2479 *val = 0;
2480 break;
2481 default:
2482 return -EINVAL;
2483 }
2484
2485 return 0;
2486}
2487
46a19188
DV		 2488static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2489 enum intel_pipe_crc_source *source)
2490{
2491 struct intel_encoder *encoder;
2492 struct intel_crtc *crtc;
26756809 2493 struct intel_digital_port *dig_port;
46a19188
DV		 2494 int ret = 0;
2495
2496 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2497
2498 mutex_lock(&dev->mode_config.mutex);
2499 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2500 base.head) {
2501 if (!encoder->base.crtc)
2502 continue;
2503
2504 crtc = to_intel_crtc(encoder->base.crtc);
2505
2506 if (crtc->pipe != pipe)
2507 continue;
2508
2509 switch (encoder->type) {
2510 case INTEL_OUTPUT_TVOUT:
2511 *source = INTEL_PIPE_CRC_SOURCE_TV;
2512 break;
2513 case INTEL_OUTPUT_DISPLAYPORT:
2514 case INTEL_OUTPUT_EDP:
26756809
DV		 2515 dig_port = enc_to_dig_port(&encoder->base);
2516 switch (dig_port->port) {
2517 case PORT_B:
2518 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2519 break;
2520 case PORT_C:
2521 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2522 break;
2523 case PORT_D:
2524 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2525 break;
2526 default:
2527 WARN(1, "nonexisting DP port %c\n",
2528 port_name(dig_port->port));
2529 break;
2530 }
46a19188
DV		 2531 break;
2532 }
2533 }
2534 mutex_unlock(&dev->mode_config.mutex);
2535
2536 return ret;
2537}
2538
2539static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2540 enum pipe pipe,
2541 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2542 uint32_t *val)
2543{
8d2f24ca
DV		 2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 bool need_stable_symbols = false;
2546
46a19188
DV		 2547 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2548 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2549 if (ret)
2550 return ret;
2551 }
2552
2553 switch (*source) {
7ac0129b
DV		 2554 case INTEL_PIPE_CRC_SOURCE_PIPE:
2555 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2556 break;
2557 case INTEL_PIPE_CRC_SOURCE_DP_B:
2558 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2559 need_stable_symbols = true;
7ac0129b
DV		 2560 break;
2561 case INTEL_PIPE_CRC_SOURCE_DP_C:
2562 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2563 need_stable_symbols = true;
7ac0129b
DV		 2564 break;
2565 case INTEL_PIPE_CRC_SOURCE_NONE:
2566 *val = 0;
2567 break;
2568 default:
2569 return -EINVAL;
2570 }
2571
8d2f24ca
DV		 2572 /*
2573 * When the pipe CRC tap point is after the transcoders we need
2574 * to tweak symbol-level features to produce a deterministic series of
2575 * symbols for a given frame. We need to reset those features only once
2576 * a frame (instead of every nth symbol):
2577 * - DC-balance: used to ensure a better clock recovery from the data
2578 * link (SDVO)
2579 * - DisplayPort scrambling: used for EMI reduction
2580 */
2581 if (need_stable_symbols) {
2582 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2583
2584 WARN_ON(!IS_G4X(dev));
2585
2586 tmp |= DC_BALANCE_RESET_VLV;
2587 if (pipe == PIPE_A)
2588 tmp |= PIPE_A_SCRAMBLE_RESET;
2589 else
2590 tmp |= PIPE_B_SCRAMBLE_RESET;
2591
2592 I915_WRITE(PORT_DFT2_G4X, tmp);
2593 }
2594
7ac0129b
DV		 2595 return 0;
2596}
2597
4b79ebf7 2598static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2599 enum pipe pipe,
2600 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2601 uint32_t *val)
2602{
84093603
DV		 2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 bool need_stable_symbols = false;
2605
46a19188
DV		 2606 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2607 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2608 if (ret)
2609 return ret;
2610 }
2611
2612 switch (*source) {
4b79ebf7
DV		 2613 case INTEL_PIPE_CRC_SOURCE_PIPE:
2614 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2615 break;
2616 case INTEL_PIPE_CRC_SOURCE_TV:
2617 if (!SUPPORTS_TV(dev))
2618 return -EINVAL;
2619 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2620 break;
2621 case INTEL_PIPE_CRC_SOURCE_DP_B:
2622 if (!IS_G4X(dev))
2623 return -EINVAL;
2624 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2625 need_stable_symbols = true;
4b79ebf7
DV		 2626 break;
2627 case INTEL_PIPE_CRC_SOURCE_DP_C:
2628 if (!IS_G4X(dev))
2629 return -EINVAL;
2630 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2631 need_stable_symbols = true;
4b79ebf7
DV		 2632 break;
2633 case INTEL_PIPE_CRC_SOURCE_DP_D:
2634 if (!IS_G4X(dev))
2635 return -EINVAL;
2636 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2637 need_stable_symbols = true;
4b79ebf7
DV		 2638 break;
2639 case INTEL_PIPE_CRC_SOURCE_NONE:
2640 *val = 0;
2641 break;
2642 default:
2643 return -EINVAL;
2644 }
2645
84093603
DV		 2646 /*
2647 * When the pipe CRC tap point is after the transcoders we need
2648 * to tweak symbol-level features to produce a deterministic series of
2649 * symbols for a given frame. We need to reset those features only once
2650 * a frame (instead of every nth symbol):
2651 * - DC-balance: used to ensure a better clock recovery from the data
2652 * link (SDVO)
2653 * - DisplayPort scrambling: used for EMI reduction
2654 */
2655 if (need_stable_symbols) {
2656 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2657
2658 WARN_ON(!IS_G4X(dev));
2659
2660 I915_WRITE(PORT_DFT_I9XX,
2661 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2662
2663 if (pipe == PIPE_A)
2664 tmp |= PIPE_A_SCRAMBLE_RESET;
2665 else
2666 tmp |= PIPE_B_SCRAMBLE_RESET;
2667
2668 I915_WRITE(PORT_DFT2_G4X, tmp);
2669 }
2670
4b79ebf7
DV		 2671 return 0;
2672}
2673
8d2f24ca
DV		 2674static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2675 enum pipe pipe)
2676{
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2679
2680 if (pipe == PIPE_A)
2681 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2682 else
2683 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2684 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2685 tmp &= ~DC_BALANCE_RESET_VLV;
2686 I915_WRITE(PORT_DFT2_G4X, tmp);
2687
2688}
2689
84093603
DV		 2690static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2691 enum pipe pipe)
2692{
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2695
2696 if (pipe == PIPE_A)
2697 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2698 else
2699 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2700 I915_WRITE(PORT_DFT2_G4X, tmp);
2701
2702 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2703 I915_WRITE(PORT_DFT_I9XX,
2704 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2705 }
2706}
2707
46a19188 2708static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2709 uint32_t *val)
2710{
46a19188
DV		 2711 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2712 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2713
2714 switch (*source) {
5b3a856b
DV		 2715 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2716 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2717 break;
2718 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2719 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2720 break;
5b3a856b
DV		 2721 case INTEL_PIPE_CRC_SOURCE_PIPE:
2722 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2723 break;
3d099a05 2724 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2725 *val = 0;
2726 break;
3d099a05
DV		 2727 default:
2728 return -EINVAL;
5b3a856b
DV		 2729 }
2730
2731 return 0;
2732}
2733
46a19188 2734static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2735 uint32_t *val)
2736{
46a19188
DV		 2737 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2738 *source = INTEL_PIPE_CRC_SOURCE_PF;
2739
2740 switch (*source) {
5b3a856b
DV		 2741 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2742 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2743 break;
2744 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2745 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2746 break;
2747 case INTEL_PIPE_CRC_SOURCE_PF:
2748 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2749 break;
3d099a05 2750 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2751 *val = 0;
2752 break;
3d099a05
DV		 2753 default:
2754 return -EINVAL;
5b3a856b
DV		 2755 }
2756
2757 return 0;
2758}
2759
926321d5
DV		 2760static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2761 enum intel_pipe_crc_source source)
2762{
2763 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2764 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2765 u32 val = 0; /* shut up gcc */
5b3a856b 2766 int ret;
926321d5 2767
cc3da175
DL		 2768 if (pipe_crc->source == source)
2769 return 0;
2770
ae676fcd
DL		 2771 /* forbid changing the source without going back to 'none' */
2772 if (pipe_crc->source && source)
2773 return -EINVAL;
2774
52f843f6 2775 if (IS_GEN2(dev))
46a19188 2776 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2777 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2778 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2779 else if (IS_VALLEYVIEW(dev))
46a19188 2780 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2781 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2782 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2783 else
46a19188 2784 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2785
2786 if (ret != 0)
2787 return ret;
2788
4b584369
DL		 2789 /* none -> real source transition */
2790 if (source) {
7cd6ccff
DL		 2791 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2792 pipe_name(pipe), pipe_crc_source_name(source));
2793
e5f75aca
DL		 2794 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2795 INTEL_PIPE_CRC_ENTRIES_NR,
2796 GFP_KERNEL);
2797 if (!pipe_crc->entries)
2798 return -ENOMEM;
2799
d538bbdf
DL		 2800 spin_lock_irq(&pipe_crc->lock);
2801 pipe_crc->head = 0;
2802 pipe_crc->tail = 0;
2803 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2804 }
2805
cc3da175 2806 pipe_crc->source = source;
926321d5 2807
926321d5
DV		 2808 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2809 POSTING_READ(PIPE_CRC_CTL(pipe));
2810
e5f75aca
DL		 2811 /* real source -> none transition */
2812 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2813 struct intel_pipe_crc_entry *entries;
2814
7cd6ccff
DL		 2815 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2816 pipe_name(pipe));
2817
bcf17ab2
DV		 2818 intel_wait_for_vblank(dev, pipe);
2819
d538bbdf
DL		 2820 spin_lock_irq(&pipe_crc->lock);
2821 entries = pipe_crc->entries;
e5f75aca 2822 pipe_crc->entries = NULL;
d538bbdf
DL		 2823 spin_unlock_irq(&pipe_crc->lock);
2824
2825 kfree(entries);
84093603
DV		 2826
2827 if (IS_G4X(dev))
2828 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2829 else if (IS_VALLEYVIEW(dev))
2830 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2831 }
2832
926321d5
DV		 2833 return 0;
2834}
2835
2836/*
2837 * Parse pipe CRC command strings:
b94dec87
DL		 2838 * command: wsp* object wsp+ name wsp+ source wsp*
2839 * object: 'pipe'
2840 * name: (A | B | C)
926321d5
DV		 2841 * source: (none | plane1 | plane2 | pf)
2842 * wsp: (#0x20 | #0x9 | #0xA)+
2843 *
2844 * eg.:
b94dec87
DL		 2845 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2846 * "pipe A none" -> Stop CRC
926321d5 2847 */
bd9db02f 2848static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2849{
2850 int n_words = 0;
2851
2852 while (*buf) {
2853 char *end;
2854
2855 /* skip leading white space */
2856 buf = skip_spaces(buf);
2857 if (!*buf)
2858 break; /* end of buffer */
2859
2860 /* find end of word */
2861 for (end = buf; *end && !isspace(*end); end++)
2862 ;
2863
2864 if (n_words == max_words) {
2865 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2866 max_words);
2867 return -EINVAL; /* ran out of words[] before bytes */
2868 }
2869
2870 if (*end)
2871 *end++ = '\0';
2872 words[n_words++] = buf;
2873 buf = end;
2874 }
2875
2876 return n_words;
2877}
2878
b94dec87
DL		 2879enum intel_pipe_crc_object {
2880 PIPE_CRC_OBJECT_PIPE,
2881};
2882
e8dfcf78 2883static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2884 "pipe",
2885};
2886
2887static int
bd9db02f 2888display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2889{
2890 int i;
2891
2892 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2893 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2894 *o = i;
b94dec87
DL		 2895 return 0;
2896 }
2897
2898 return -EINVAL;
2899}
2900
bd9db02f 2901static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2902{
2903 const char name = buf[0];
2904
2905 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2906 return -EINVAL;
2907
2908 *pipe = name - 'A';
2909
2910 return 0;
2911}
2912
2913static int
bd9db02f 2914display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2915{
2916 int i;
2917
2918 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2919 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2920 *s = i;
926321d5
DV		 2921 return 0;
2922 }
2923
2924 return -EINVAL;
2925}
2926
bd9db02f 2927static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2928{
b94dec87 2929#define N_WORDS 3
926321d5 2930 int n_words;
b94dec87 2931 char *words[N_WORDS];
926321d5 2932 enum pipe pipe;
b94dec87 2933 enum intel_pipe_crc_object object;
926321d5
DV		 2934 enum intel_pipe_crc_source source;
2935
bd9db02f 2936 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2937 if (n_words != N_WORDS) {
2938 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2939 N_WORDS);
2940 return -EINVAL;
2941 }
2942
bd9db02f 2943 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2944 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2945 return -EINVAL;
2946 }
2947
bd9db02f 2948 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2949 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2950 return -EINVAL;
2951 }
2952
bd9db02f 2953 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2954 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2955 return -EINVAL;
2956 }
2957
2958 return pipe_crc_set_source(dev, pipe, source);
2959}
2960
bd9db02f
DL		 2961static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2962 size_t len, loff_t *offp)
926321d5
DV		 2963{
2964 struct seq_file *m = file->private_data;
2965 struct drm_device *dev = m->private;
2966 char *tmpbuf;
2967 int ret;
2968
2969 if (len == 0)
2970 return 0;
2971
2972 if (len > PAGE_SIZE - 1) {
2973 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2974 PAGE_SIZE);
2975 return -E2BIG;
2976 }
2977
2978 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2979 if (!tmpbuf)
2980 return -ENOMEM;
2981
2982 if (copy_from_user(tmpbuf, ubuf, len)) {
2983 ret = -EFAULT;
2984 goto out;
2985 }
2986 tmpbuf[len] = '\0';
2987
bd9db02f 2988 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2989
2990out:
2991 kfree(tmpbuf);
2992 if (ret < 0)
2993 return ret;
2994
2995 *offp += len;
2996 return len;
2997}
2998
bd9db02f 2999static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3000 .owner = THIS_MODULE,
bd9db02f 3001 .open = display_crc_ctl_open,
926321d5
DV		 3002 .read = seq_read,
3003 .llseek = seq_lseek,
3004 .release = single_release,
bd9db02f 3005 .write = display_crc_ctl_write
926321d5
DV		 3006};
3007
369a1342
VS		 3008static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3009{
3010 struct drm_device *dev = m->private;
3011 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3012 int level;
3013
3014 drm_modeset_lock_all(dev);
3015
3016 for (level = 0; level < num_levels; level++) {
3017 unsigned int latency = wm[level];
3018
3019 /* WM1+ latency values in 0.5us units */
3020 if (level > 0)
3021 latency *= 5;
3022
3023 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3024 level, wm[level],
3025 latency / 10, latency % 10);
3026 }
3027
3028 drm_modeset_unlock_all(dev);
3029}
3030
3031static int pri_wm_latency_show(struct seq_file *m, void *data)
3032{
3033 struct drm_device *dev = m->private;
3034
3035 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3036
3037 return 0;
3038}
3039
3040static int spr_wm_latency_show(struct seq_file *m, void *data)
3041{
3042 struct drm_device *dev = m->private;
3043
3044 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3045
3046 return 0;
3047}
3048
3049static int cur_wm_latency_show(struct seq_file *m, void *data)
3050{
3051 struct drm_device *dev = m->private;
3052
3053 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3054
3055 return 0;
3056}
3057
3058static int pri_wm_latency_open(struct inode *inode, struct file *file)
3059{
3060 struct drm_device *dev = inode->i_private;
3061
3062 if (!HAS_PCH_SPLIT(dev))
3063 return -ENODEV;
3064
3065 return single_open(file, pri_wm_latency_show, dev);
3066}
3067
3068static int spr_wm_latency_open(struct inode *inode, struct file *file)
3069{
3070 struct drm_device *dev = inode->i_private;
3071
3072 if (!HAS_PCH_SPLIT(dev))
3073 return -ENODEV;
3074
3075 return single_open(file, spr_wm_latency_show, dev);
3076}
3077
3078static int cur_wm_latency_open(struct inode *inode, struct file *file)
3079{
3080 struct drm_device *dev = inode->i_private;
3081
3082 if (!HAS_PCH_SPLIT(dev))
3083 return -ENODEV;
3084
3085 return single_open(file, cur_wm_latency_show, dev);
3086}
3087
3088static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3089 size_t len, loff_t *offp, uint16_t wm[5])
3090{
3091 struct seq_file *m = file->private_data;
3092 struct drm_device *dev = m->private;
3093 uint16_t new[5] = { 0 };
3094 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3095 int level;
3096 int ret;
3097 char tmp[32];
3098
3099 if (len >= sizeof(tmp))
3100 return -EINVAL;
3101
3102 if (copy_from_user(tmp, ubuf, len))
3103 return -EFAULT;
3104
3105 tmp[len] = '\0';
3106
3107 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3108 if (ret != num_levels)
3109 return -EINVAL;
3110
3111 drm_modeset_lock_all(dev);
3112
3113 for (level = 0; level < num_levels; level++)
3114 wm[level] = new[level];
3115
3116 drm_modeset_unlock_all(dev);
3117
3118 return len;
3119}
3120
3121
3122static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3123 size_t len, loff_t *offp)
3124{
3125 struct seq_file *m = file->private_data;
3126 struct drm_device *dev = m->private;
3127
3128 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3129}
3130
3131static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3132 size_t len, loff_t *offp)
3133{
3134 struct seq_file *m = file->private_data;
3135 struct drm_device *dev = m->private;
3136
3137 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3138}
3139
3140static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3141 size_t len, loff_t *offp)
3142{
3143 struct seq_file *m = file->private_data;
3144 struct drm_device *dev = m->private;
3145
3146 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3147}
3148
3149static const struct file_operations i915_pri_wm_latency_fops = {
3150 .owner = THIS_MODULE,
3151 .open = pri_wm_latency_open,
3152 .read = seq_read,
3153 .llseek = seq_lseek,
3154 .release = single_release,
3155 .write = pri_wm_latency_write
3156};
3157
3158static const struct file_operations i915_spr_wm_latency_fops = {
3159 .owner = THIS_MODULE,
3160 .open = spr_wm_latency_open,
3161 .read = seq_read,
3162 .llseek = seq_lseek,
3163 .release = single_release,
3164 .write = spr_wm_latency_write
3165};
3166
3167static const struct file_operations i915_cur_wm_latency_fops = {
3168 .owner = THIS_MODULE,
3169 .open = cur_wm_latency_open,
3170 .read = seq_read,
3171 .llseek = seq_lseek,
3172 .release = single_release,
3173 .write = cur_wm_latency_write
3174};
3175
647416f9
KC		 3176static int
3177i915_wedged_get(void *data, u64 *val)
f3cd474b 3178{
647416f9 3179 struct drm_device *dev = data;
f3cd474b 3180 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 3181
647416f9 3182 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3183
647416f9 3184 return 0;
f3cd474b
CW		 3185}
3186
647416f9
KC		 3187static int
3188i915_wedged_set(void *data, u64 val)
f3cd474b 3189{
647416f9 3190 struct drm_device *dev = data;
f3cd474b 3191
58174462
MK		 3192 i915_handle_error(dev, val,
3193 "Manually setting wedged to %llu", val);
647416f9 3194 return 0;
f3cd474b
CW		 3195}
3196
647416f9
KC		 3197DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3198 i915_wedged_get, i915_wedged_set,
3a3b4f98 3199 "%llu\n");
f3cd474b 3200
647416f9
KC		 3201static int
3202i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3203{
647416f9 3204 struct drm_device *dev = data;
e5eb3d63 3205 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 3206
647416f9 3207 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3208
647416f9 3209 return 0;
e5eb3d63
DV		 3210}
3211
647416f9
KC		 3212static int
3213i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3214{
647416f9 3215 struct drm_device *dev = data;
e5eb3d63 3216 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3217 int ret;
e5eb3d63 3218
647416f9 3219 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3220
22bcfc6a
DV		 3221 ret = mutex_lock_interruptible(&dev->struct_mutex);
3222 if (ret)
3223 return ret;
3224
99584db3 3225 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3226 mutex_unlock(&dev->struct_mutex);
3227
647416f9 3228 return 0;
e5eb3d63
DV		 3229}
3230
647416f9
KC		 3231DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3232 i915_ring_stop_get, i915_ring_stop_set,
3233 "0x%08llx\n");
d5442303 3234
094f9a54
CW		 3235static int
3236i915_ring_missed_irq_get(void *data, u64 *val)
3237{
3238 struct drm_device *dev = data;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241 *val = dev_priv->gpu_error.missed_irq_rings;
3242 return 0;
3243}
3244
3245static int
3246i915_ring_missed_irq_set(void *data, u64 val)
3247{
3248 struct drm_device *dev = data;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int ret;
3251
3252 /* Lock against concurrent debugfs callers */
3253 ret = mutex_lock_interruptible(&dev->struct_mutex);
3254 if (ret)
3255 return ret;
3256 dev_priv->gpu_error.missed_irq_rings = val;
3257 mutex_unlock(&dev->struct_mutex);
3258
3259 return 0;
3260}
3261
3262DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3263 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3264 "0x%08llx\n");
3265
3266static int
3267i915_ring_test_irq_get(void *data, u64 *val)
3268{
3269 struct drm_device *dev = data;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271
3272 *val = dev_priv->gpu_error.test_irq_rings;
3273
3274 return 0;
3275}
3276
3277static int
3278i915_ring_test_irq_set(void *data, u64 val)
3279{
3280 struct drm_device *dev = data;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 int ret;
3283
3284 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3285
3286 /* Lock against concurrent debugfs callers */
3287 ret = mutex_lock_interruptible(&dev->struct_mutex);
3288 if (ret)
3289 return ret;
3290
3291 dev_priv->gpu_error.test_irq_rings = val;
3292 mutex_unlock(&dev->struct_mutex);
3293
3294 return 0;
3295}
3296
3297DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3298 i915_ring_test_irq_get, i915_ring_test_irq_set,
3299 "0x%08llx\n");
3300
dd624afd
CW		 3301#define DROP_UNBOUND 0x1
3302#define DROP_BOUND 0x2
3303#define DROP_RETIRE 0x4
3304#define DROP_ACTIVE 0x8
3305#define DROP_ALL (DROP_UNBOUND | \
3306 DROP_BOUND | \
3307 DROP_RETIRE | \
3308 DROP_ACTIVE)
647416f9
KC		 3309static int
3310i915_drop_caches_get(void *data, u64 *val)
dd624afd 3311{
647416f9 3312 *val = DROP_ALL;
dd624afd 3313
647416f9 3314 return 0;
dd624afd
CW		 3315}
3316
647416f9
KC		 3317static int
3318i915_drop_caches_set(void *data, u64 val)
dd624afd 3319{
647416f9 3320 struct drm_device *dev = data;
dd624afd
CW		 3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3323 struct i915_address_space *vm;
3324 struct i915_vma *vma, *x;
647416f9 3325 int ret;
dd624afd 3326
2f9fe5ff 3327 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3328
3329 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3330 * on ioctls on -EAGAIN. */
3331 ret = mutex_lock_interruptible(&dev->struct_mutex);
3332 if (ret)
3333 return ret;
3334
3335 if (val & DROP_ACTIVE) {
3336 ret = i915_gpu_idle(dev);
3337 if (ret)
3338 goto unlock;
3339 }
3340
3341 if (val & (DROP_RETIRE | DROP_ACTIVE))
3342 i915_gem_retire_requests(dev);
3343
3344 if (val & DROP_BOUND) {
ca191b13
BW		 3345 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3346 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3347 mm_list) {
d7f46fc4 3348 if (vma->pin_count)
ca191b13
BW		 3349 continue;
3350
3351 ret = i915_vma_unbind(vma);
3352 if (ret)
3353 goto unlock;
3354 }
31a46c9c 3355 }
dd624afd
CW		 3356 }
3357
3358 if (val & DROP_UNBOUND) {
35c20a60
BW		 3359 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3360 global_list)
dd624afd
CW		 3361 if (obj->pages_pin_count == 0) {
3362 ret = i915_gem_object_put_pages(obj);
3363 if (ret)
3364 goto unlock;
3365 }
3366 }
3367
3368unlock:
3369 mutex_unlock(&dev->struct_mutex);
3370
647416f9 3371 return ret;
dd624afd
CW		 3372}
3373
647416f9
KC		 3374DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3375 i915_drop_caches_get, i915_drop_caches_set,
3376 "0x%08llx\n");
dd624afd 3377
647416f9
KC		 3378static int
3379i915_max_freq_get(void *data, u64 *val)
358733e9 3380{
647416f9 3381 struct drm_device *dev = data;
358733e9 3382 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3383 int ret;
004777cb
DV		 3384
3385 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3386 return -ENODEV;
3387
5c9669ce
TR		 3388 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3389
4fc688ce 3390 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3391 if (ret)
3392 return ret;
358733e9 3393
0a073b84 3394 if (IS_VALLEYVIEW(dev))
2ec3815f 3395 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84
JB		 3396 else
3397 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3398 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3399
647416f9 3400 return 0;
358733e9
JB		 3401}
3402
647416f9
KC		 3403static int
3404i915_max_freq_set(void *data, u64 val)
358733e9 3405{
647416f9 3406 struct drm_device *dev = data;
358733e9 3407 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3408 u32 rp_state_cap, hw_max, hw_min;
647416f9 3409 int ret;
004777cb
DV		 3410
3411 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3412 return -ENODEV;
358733e9 3413
5c9669ce
TR		 3414 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3415
647416f9 3416 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3417
4fc688ce 3418 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3419 if (ret)
3420 return ret;
3421
358733e9
JB		 3422 /*
3423 * Turbo will still be enabled, but won't go above the set value.
3424 */
0a073b84 3425 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3426 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3427
3428 hw_max = valleyview_rps_max_freq(dev_priv);
3429 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3430 } else {
3431 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3432
3433 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3434 hw_max = dev_priv->rps.hw_max;
3435 hw_min = (rp_state_cap >> 16) & 0xff;
3436 }
3437
3438 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
3439 mutex_unlock(&dev_priv->rps.hw_lock);
3440 return -EINVAL;
0a073b84
JB		 3441 }
3442
dd0a1aa1
JM		 3443 dev_priv->rps.max_delay = val;
3444
3445 if (IS_VALLEYVIEW(dev))
3446 valleyview_set_rps(dev, val);
3447 else
3448 gen6_set_rps(dev, val);
3449
4fc688ce 3450 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3451
647416f9 3452 return 0;
358733e9
JB		 3453}
3454
647416f9
KC		 3455DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3456 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3457 "%llu\n");
358733e9 3458
647416f9
KC		 3459static int
3460i915_min_freq_get(void *data, u64 *val)
1523c310 3461{
647416f9 3462 struct drm_device *dev = data;
1523c310 3463 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3464 int ret;
004777cb
DV		 3465
3466 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3467 return -ENODEV;
3468
5c9669ce
TR		 3469 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3470
4fc688ce 3471 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3472 if (ret)
3473 return ret;
1523c310 3474
0a073b84 3475 if (IS_VALLEYVIEW(dev))
2ec3815f 3476 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84
JB		 3477 else
3478 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3479 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3480
647416f9 3481 return 0;
1523c310
JB		 3482}
3483
647416f9
KC		 3484static int
3485i915_min_freq_set(void *data, u64 val)
1523c310 3486{
647416f9 3487 struct drm_device *dev = data;
1523c310 3488 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3489 u32 rp_state_cap, hw_max, hw_min;
647416f9 3490 int ret;
004777cb
DV		 3491
3492 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3493 return -ENODEV;
1523c310 3494
5c9669ce
TR		 3495 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3496
647416f9 3497 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3498
4fc688ce 3499 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3500 if (ret)
3501 return ret;
3502
1523c310
JB		 3503 /*
3504 * Turbo will still be enabled, but won't go below the set value.
3505 */
0a073b84 3506 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3507 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3508
3509 hw_max = valleyview_rps_max_freq(dev_priv);
3510 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3511 } else {
3512 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3513
3514 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3515 hw_max = dev_priv->rps.hw_max;
3516 hw_min = (rp_state_cap >> 16) & 0xff;
3517 }
3518
3519 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
3520 mutex_unlock(&dev_priv->rps.hw_lock);
3521 return -EINVAL;
0a073b84 3522 }
dd0a1aa1
JM		 3523
3524 dev_priv->rps.min_delay = val;
3525
3526 if (IS_VALLEYVIEW(dev))
3527 valleyview_set_rps(dev, val);
3528 else
3529 gen6_set_rps(dev, val);
3530
4fc688ce 3531 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3532
647416f9 3533 return 0;
1523c310
JB		 3534}
3535
647416f9
KC		 3536DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3537 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3538 "%llu\n");
1523c310 3539
647416f9
KC		 3540static int
3541i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3542{
647416f9 3543 struct drm_device *dev = data;
07b7ddd9 3544 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 3545 u32 snpcr;
647416f9 3546 int ret;
07b7ddd9 3547
004777cb
DV		 3548 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3549 return -ENODEV;
3550
22bcfc6a
DV		 3551 ret = mutex_lock_interruptible(&dev->struct_mutex);
3552 if (ret)
3553 return ret;
c8c8fb33 3554 intel_runtime_pm_get(dev_priv);
22bcfc6a 3555
07b7ddd9 3556 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3557
3558 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3559 mutex_unlock(&dev_priv->dev->struct_mutex);
3560
647416f9 3561 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3562
647416f9 3563 return 0;
07b7ddd9
JB		 3564}
3565
647416f9
KC		 3566static int
3567i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3568{
647416f9 3569 struct drm_device *dev = data;
07b7ddd9 3570 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3571 u32 snpcr;
07b7ddd9 3572
004777cb
DV		 3573 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3574 return -ENODEV;
3575
647416f9 3576 if (val > 3)
07b7ddd9
JB		 3577 return -EINVAL;
3578
c8c8fb33 3579 intel_runtime_pm_get(dev_priv);
647416f9 3580 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3581
3582 /* Update the cache sharing policy here as well */
3583 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3584 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3585 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3586 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3587
c8c8fb33 3588 intel_runtime_pm_put(dev_priv);
647416f9 3589 return 0;
07b7ddd9
JB		 3590}
3591
647416f9
KC		 3592DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3593 i915_cache_sharing_get, i915_cache_sharing_set,
3594 "%llu\n");
07b7ddd9 3595
6d794d42
BW		 3596static int i915_forcewake_open(struct inode *inode, struct file *file)
3597{
3598 struct drm_device *dev = inode->i_private;
3599 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3600
075edca4 3601 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3602 return 0;
3603
c8c8fb33 3604 intel_runtime_pm_get(dev_priv);
c8d9a590 3605 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3606
3607 return 0;
3608}
3609
c43b5634 3610static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3611{
3612 struct drm_device *dev = inode->i_private;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614
075edca4 3615 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3616 return 0;
3617
c8d9a590 3618 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
c8c8fb33 3619 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 3620
3621 return 0;
3622}
3623
3624static const struct file_operations i915_forcewake_fops = {
3625 .owner = THIS_MODULE,
3626 .open = i915_forcewake_open,
3627 .release = i915_forcewake_release,
3628};
3629
3630static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3631{
3632 struct drm_device *dev = minor->dev;
3633 struct dentry *ent;
3634
3635 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3636 S_IRUSR,
6d794d42
BW		 3637 root, dev,
3638 &i915_forcewake_fops);
f3c5fe97
WY		 3639 if (!ent)
3640 return -ENOMEM;
6d794d42 3641
8eb57294 3642 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3643}
3644
6a9c308d
DV		 3645static int i915_debugfs_create(struct dentry *root,
3646 struct drm_minor *minor,
3647 const char *name,
3648 const struct file_operations *fops)
07b7ddd9
JB		 3649{
3650 struct drm_device *dev = minor->dev;
3651 struct dentry *ent;
3652
6a9c308d 3653 ent = debugfs_create_file(name,
07b7ddd9
JB		 3654 S_IRUGO | S_IWUSR,
3655 root, dev,
6a9c308d 3656 fops);
f3c5fe97
WY		 3657 if (!ent)
3658 return -ENOMEM;
07b7ddd9 3659
6a9c308d 3660 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3661}
3662
06c5bf8c 3663static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3664 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3665 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3666 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3667 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3668 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3669 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3670 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3671 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3672 {"i915_gem_request", i915_gem_request_info, 0},
3673 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3674 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3675 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3676 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3677 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3678 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3679 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3680 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3681 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3682 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3683 {"i915_inttoext_table", i915_inttoext_table, 0},
3684 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3685 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3686 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3687 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3688 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3689 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3690 {"i915_sr_status", i915_sr_status, 0},
44834a67 3691 {"i915_opregion", i915_opregion, 0},
37811fcc 3692 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3693 {"i915_context_status", i915_context_status, 0},
6d794d42 3694 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3695 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3696 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3697 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3698 {"i915_llc", i915_llc, 0},
e91fd8c6 3699 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3700 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3701 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3702 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3703 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3704 {"i915_display_info", i915_display_info, 0},
2017263e 3705};
27c202ad 3706#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3707
06c5bf8c 3708static const struct i915_debugfs_files {
34b9674c
DV		 3709 const char *name;
3710 const struct file_operations *fops;
3711} i915_debugfs_files[] = {
3712 {"i915_wedged", &i915_wedged_fops},
3713 {"i915_max_freq", &i915_max_freq_fops},
3714 {"i915_min_freq", &i915_min_freq_fops},
3715 {"i915_cache_sharing", &i915_cache_sharing_fops},
3716 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3717 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3718 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3719 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3720 {"i915_error_state", &i915_error_state_fops},
3721 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3722 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3723 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3724 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3725 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3726};
3727
07144428
DL		 3728void intel_display_crc_init(struct drm_device *dev)
3729{
3730 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3731 enum pipe pipe;
07144428 3732
b378360e
DV		 3733 for_each_pipe(pipe) {
3734 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3735
d538bbdf
DL		 3736 pipe_crc->opened = false;
3737 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3738 init_waitqueue_head(&pipe_crc->wq);
3739 }
3740}
3741
27c202ad 3742int i915_debugfs_init(struct drm_minor *minor)
2017263e 3743{
34b9674c 3744 int ret, i;
f3cd474b 3745
6d794d42 3746 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3747 if (ret)
3748 return ret;
6a9c308d 3749
07144428
DL		 3750 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3751 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3752 if (ret)
3753 return ret;
3754 }
3755
34b9674c
DV		 3756 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3757 ret = i915_debugfs_create(minor->debugfs_root, minor,
3758 i915_debugfs_files[i].name,
3759 i915_debugfs_files[i].fops);
3760 if (ret)
3761 return ret;
3762 }
40633219 3763
27c202ad
BG		 3764 return drm_debugfs_create_files(i915_debugfs_list,
3765 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3766 minor->debugfs_root, minor);
3767}
3768
27c202ad 3769void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3770{
34b9674c
DV		 3771 int i;
3772
27c202ad
BG		 3773 drm_debugfs_remove_files(i915_debugfs_list,
3774 I915_DEBUGFS_ENTRIES, minor);
07144428 3775
6d794d42
BW		 3776 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3777 1, minor);
07144428 3778
e309a997 3779 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3780 struct drm_info_list *info_list =
3781 (struct drm_info_list *)&i915_pipe_crc_data[i];
3782
3783 drm_debugfs_remove_files(info_list, 1, minor);
3784 }
3785
34b9674c
DV		 3786 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3787 struct drm_info_list *info_list =
3788 (struct drm_info_list *) i915_debugfs_files[i].fops;
3789
3790 drm_debugfs_remove_files(info_list, 1, minor);
3791 }
2017263e 3792}
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