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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
760285e7 | 33 | #include <drm/drmP.h> |
4e5359cd | 34 | #include "intel_drv.h" |
e5c65260 | 35 | #include "intel_ringbuffer.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
2017263e BG |
37 | #include "i915_drv.h" |
38 | ||
39 | #define DRM_I915_RING_DEBUG 1 | |
40 | ||
41 | ||
42 | #if defined(CONFIG_DEBUG_FS) | |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 | 46 | INACTIVE_LIST, |
d21d5975 | 47 | PINNED_LIST, |
f13d3f73 | 48 | }; |
2017263e | 49 | |
70d39fe4 CW |
50 | static const char *yesno(int v) |
51 | { | |
52 | return v ? "yes" : "no"; | |
53 | } | |
54 | ||
55 | static int i915_capabilities(struct seq_file *m, void *data) | |
56 | { | |
57 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
58 | struct drm_device *dev = node->minor->dev; | |
59 | const struct intel_device_info *info = INTEL_INFO(dev); | |
60 | ||
61 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
63 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
64 | #define SEP_SEMICOLON ; | |
65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
66 | #undef PRINT_FLAG | |
67 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
68 | |
69 | return 0; | |
70 | } | |
2017263e | 71 | |
05394f39 | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 73 | { |
05394f39 | 74 | if (obj->user_pin_count > 0) |
a6172a80 | 75 | return "P"; |
05394f39 | 76 | else if (obj->pin_count > 0) |
a6172a80 CW |
77 | return "p"; |
78 | else | |
79 | return " "; | |
80 | } | |
81 | ||
05394f39 | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 83 | { |
0206e353 AJ |
84 | switch (obj->tiling_mode) { |
85 | default: | |
86 | case I915_TILING_NONE: return " "; | |
87 | case I915_TILING_X: return "X"; | |
88 | case I915_TILING_Y: return "Y"; | |
89 | } | |
a6172a80 CW |
90 | } |
91 | ||
1d693bcc BW |
92 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
93 | { | |
94 | return obj->has_global_gtt_mapping ? "g" : " "; | |
95 | } | |
96 | ||
37811fcc CW |
97 | static void |
98 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
99 | { | |
1d693bcc BW |
100 | struct i915_vma *vma; |
101 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %d %d %d%s%s%s", | |
37811fcc CW |
102 | &obj->base, |
103 | get_pin_flag(obj), | |
104 | get_tiling_flag(obj), | |
1d693bcc | 105 | get_global_flag(obj), |
a05a5862 | 106 | obj->base.size / 1024, |
37811fcc CW |
107 | obj->base.read_domains, |
108 | obj->base.write_domain, | |
0201f1ec CW |
109 | obj->last_read_seqno, |
110 | obj->last_write_seqno, | |
caea7476 | 111 | obj->last_fenced_seqno, |
84734a04 | 112 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
113 | obj->dirty ? " dirty" : "", |
114 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
115 | if (obj->base.name) | |
116 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
117 | if (obj->pin_count) |
118 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
119 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
120 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
121 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
122 | if (!i915_is_ggtt(vma->vm)) | |
123 | seq_puts(m, " (pp"); | |
124 | else | |
125 | seq_puts(m, " (g"); | |
126 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
127 | vma->node.start, vma->node.size); | |
128 | } | |
c1ad11fc CW |
129 | if (obj->stolen) |
130 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
131 | if (obj->pin_mappable || obj->fault_mappable) { |
132 | char s[3], *t = s; | |
133 | if (obj->pin_mappable) | |
134 | *t++ = 'p'; | |
135 | if (obj->fault_mappable) | |
136 | *t++ = 'f'; | |
137 | *t = '\0'; | |
138 | seq_printf(m, " (%s mappable)", s); | |
139 | } | |
69dc4987 CW |
140 | if (obj->ring != NULL) |
141 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
142 | } |
143 | ||
433e12f7 | 144 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
145 | { |
146 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
147 | uintptr_t list = (uintptr_t) node->info_ent->data; |
148 | struct list_head *head; | |
2017263e | 149 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
150 | struct drm_i915_private *dev_priv = dev->dev_private; |
151 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 152 | struct i915_vma *vma; |
8f2480fb CW |
153 | size_t total_obj_size, total_gtt_size; |
154 | int count, ret; | |
de227ef0 CW |
155 | |
156 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
157 | if (ret) | |
158 | return ret; | |
2017263e | 159 | |
ca191b13 | 160 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
161 | switch (list) { |
162 | case ACTIVE_LIST: | |
267f0c90 | 163 | seq_puts(m, "Active:\n"); |
5cef07e1 | 164 | head = &vm->active_list; |
433e12f7 BG |
165 | break; |
166 | case INACTIVE_LIST: | |
267f0c90 | 167 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 168 | head = &vm->inactive_list; |
433e12f7 | 169 | break; |
433e12f7 | 170 | default: |
de227ef0 CW |
171 | mutex_unlock(&dev->struct_mutex); |
172 | return -EINVAL; | |
2017263e | 173 | } |
2017263e | 174 | |
8f2480fb | 175 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
176 | list_for_each_entry(vma, head, mm_list) { |
177 | seq_printf(m, " "); | |
178 | describe_obj(m, vma->obj); | |
179 | seq_printf(m, "\n"); | |
180 | total_obj_size += vma->obj->base.size; | |
181 | total_gtt_size += vma->node.size; | |
8f2480fb | 182 | count++; |
2017263e | 183 | } |
de227ef0 | 184 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 185 | |
8f2480fb CW |
186 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
187 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
188 | return 0; |
189 | } | |
190 | ||
6299f992 CW |
191 | #define count_objects(list, member) do { \ |
192 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 193 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
194 | ++count; \ |
195 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 196 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
197 | ++mappable_count; \ |
198 | } \ | |
199 | } \ | |
0206e353 | 200 | } while (0) |
6299f992 | 201 | |
2db8e9d6 CW |
202 | struct file_stats { |
203 | int count; | |
204 | size_t total, active, inactive, unbound; | |
205 | }; | |
206 | ||
207 | static int per_file_stats(int id, void *ptr, void *data) | |
208 | { | |
209 | struct drm_i915_gem_object *obj = ptr; | |
210 | struct file_stats *stats = data; | |
211 | ||
212 | stats->count++; | |
213 | stats->total += obj->base.size; | |
214 | ||
f343c5f6 | 215 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
216 | if (!list_empty(&obj->ring_list)) |
217 | stats->active += obj->base.size; | |
218 | else | |
219 | stats->inactive += obj->base.size; | |
220 | } else { | |
221 | if (!list_empty(&obj->global_list)) | |
222 | stats->unbound += obj->base.size; | |
223 | } | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
ca191b13 BW |
228 | #define count_vmas(list, member) do { \ |
229 | list_for_each_entry(vma, list, member) { \ | |
230 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
231 | ++count; \ | |
232 | if (vma->obj->map_and_fenceable) { \ | |
233 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
234 | ++mappable_count; \ | |
235 | } \ | |
236 | } \ | |
237 | } while (0) | |
238 | ||
239 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
240 | { |
241 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
242 | struct drm_device *dev = node->minor->dev; | |
243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
244 | u32 count, mappable_count, purgeable_count; |
245 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 246 | struct drm_i915_gem_object *obj; |
5cef07e1 | 247 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 248 | struct drm_file *file; |
ca191b13 | 249 | struct i915_vma *vma; |
73aa808f CW |
250 | int ret; |
251 | ||
252 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
6299f992 CW |
256 | seq_printf(m, "%u objects, %zu bytes\n", |
257 | dev_priv->mm.object_count, | |
258 | dev_priv->mm.object_memory); | |
259 | ||
260 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 261 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
262 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
263 | count, mappable_count, size, mappable_size); | |
264 | ||
265 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 266 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
267 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
268 | count, mappable_count, size, mappable_size); | |
269 | ||
6299f992 | 270 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 271 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
272 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
273 | count, mappable_count, size, mappable_size); | |
274 | ||
b7abb714 | 275 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 276 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 277 | size += obj->base.size, ++count; |
b7abb714 CW |
278 | if (obj->madv == I915_MADV_DONTNEED) |
279 | purgeable_size += obj->base.size, ++purgeable_count; | |
280 | } | |
6c085a72 CW |
281 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
282 | ||
6299f992 | 283 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 284 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 285 | if (obj->fault_mappable) { |
f343c5f6 | 286 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
287 | ++count; |
288 | } | |
289 | if (obj->pin_mappable) { | |
f343c5f6 | 290 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
291 | ++mappable_count; |
292 | } | |
b7abb714 CW |
293 | if (obj->madv == I915_MADV_DONTNEED) { |
294 | purgeable_size += obj->base.size; | |
295 | ++purgeable_count; | |
296 | } | |
6299f992 | 297 | } |
b7abb714 CW |
298 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
299 | purgeable_count, purgeable_size); | |
6299f992 CW |
300 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
301 | mappable_count, mappable_size); | |
302 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
303 | count, size); | |
304 | ||
93d18799 | 305 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
306 | dev_priv->gtt.base.total, |
307 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 308 | |
267f0c90 | 309 | seq_putc(m, '\n'); |
2db8e9d6 CW |
310 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
311 | struct file_stats stats; | |
312 | ||
313 | memset(&stats, 0, sizeof(stats)); | |
314 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
315 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
316 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
317 | stats.count, | |
318 | stats.total, | |
319 | stats.active, | |
320 | stats.inactive, | |
321 | stats.unbound); | |
322 | } | |
323 | ||
73aa808f CW |
324 | mutex_unlock(&dev->struct_mutex); |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
aee56cff | 329 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
330 | { |
331 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
332 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 333 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
334 | struct drm_i915_private *dev_priv = dev->dev_private; |
335 | struct drm_i915_gem_object *obj; | |
336 | size_t total_obj_size, total_gtt_size; | |
337 | int count, ret; | |
338 | ||
339 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
340 | if (ret) | |
341 | return ret; | |
342 | ||
343 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 344 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
345 | if (list == PINNED_LIST && obj->pin_count == 0) |
346 | continue; | |
347 | ||
267f0c90 | 348 | seq_puts(m, " "); |
08c18323 | 349 | describe_obj(m, obj); |
267f0c90 | 350 | seq_putc(m, '\n'); |
08c18323 | 351 | total_obj_size += obj->base.size; |
f343c5f6 | 352 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
353 | count++; |
354 | } | |
355 | ||
356 | mutex_unlock(&dev->struct_mutex); | |
357 | ||
358 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
359 | count, total_obj_size, total_gtt_size); | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
4e5359cd SF |
364 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
365 | { | |
366 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
367 | struct drm_device *dev = node->minor->dev; | |
368 | unsigned long flags; | |
369 | struct intel_crtc *crtc; | |
370 | ||
371 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
372 | const char pipe = pipe_name(crtc->pipe); |
373 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
374 | struct intel_unpin_work *work; |
375 | ||
376 | spin_lock_irqsave(&dev->event_lock, flags); | |
377 | work = crtc->unpin_work; | |
378 | if (work == NULL) { | |
9db4a9c7 | 379 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
380 | pipe, plane); |
381 | } else { | |
e7d841ca | 382 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 383 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
384 | pipe, plane); |
385 | } else { | |
9db4a9c7 | 386 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
387 | pipe, plane); |
388 | } | |
389 | if (work->enable_stall_check) | |
267f0c90 | 390 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 391 | else |
267f0c90 | 392 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 393 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
394 | |
395 | if (work->old_fb_obj) { | |
05394f39 CW |
396 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
397 | if (obj) | |
f343c5f6 BW |
398 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
399 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
400 | } |
401 | if (work->pending_flip_obj) { | |
05394f39 CW |
402 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
403 | if (obj) | |
f343c5f6 BW |
404 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
405 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
406 | } |
407 | } | |
408 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
2017263e BG |
414 | static int i915_gem_request_info(struct seq_file *m, void *data) |
415 | { | |
416 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
417 | struct drm_device *dev = node->minor->dev; | |
418 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 419 | struct intel_ring_buffer *ring; |
2017263e | 420 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 421 | int ret, count, i; |
de227ef0 CW |
422 | |
423 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
424 | if (ret) | |
425 | return ret; | |
2017263e | 426 | |
c2c347a9 | 427 | count = 0; |
a2c7f6fd CW |
428 | for_each_ring(ring, dev_priv, i) { |
429 | if (list_empty(&ring->request_list)) | |
430 | continue; | |
431 | ||
432 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 433 | list_for_each_entry(gem_request, |
a2c7f6fd | 434 | &ring->request_list, |
c2c347a9 CW |
435 | list) { |
436 | seq_printf(m, " %d @ %d\n", | |
437 | gem_request->seqno, | |
438 | (int) (jiffies - gem_request->emitted_jiffies)); | |
439 | } | |
440 | count++; | |
2017263e | 441 | } |
de227ef0 CW |
442 | mutex_unlock(&dev->struct_mutex); |
443 | ||
c2c347a9 | 444 | if (count == 0) |
267f0c90 | 445 | seq_puts(m, "No requests\n"); |
c2c347a9 | 446 | |
2017263e BG |
447 | return 0; |
448 | } | |
449 | ||
b2223497 CW |
450 | static void i915_ring_seqno_info(struct seq_file *m, |
451 | struct intel_ring_buffer *ring) | |
452 | { | |
453 | if (ring->get_seqno) { | |
43a7b924 | 454 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 455 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
456 | } |
457 | } | |
458 | ||
2017263e BG |
459 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
460 | { | |
461 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
462 | struct drm_device *dev = node->minor->dev; | |
463 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 464 | struct intel_ring_buffer *ring; |
1ec14ad3 | 465 | int ret, i; |
de227ef0 CW |
466 | |
467 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
468 | if (ret) | |
469 | return ret; | |
2017263e | 470 | |
a2c7f6fd CW |
471 | for_each_ring(ring, dev_priv, i) |
472 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
473 | |
474 | mutex_unlock(&dev->struct_mutex); | |
475 | ||
2017263e BG |
476 | return 0; |
477 | } | |
478 | ||
479 | ||
480 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
481 | { | |
482 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
483 | struct drm_device *dev = node->minor->dev; | |
484 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 485 | struct intel_ring_buffer *ring; |
9db4a9c7 | 486 | int ret, i, pipe; |
de227ef0 CW |
487 | |
488 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
489 | if (ret) | |
490 | return ret; | |
2017263e | 491 | |
7e231dbe JB |
492 | if (IS_VALLEYVIEW(dev)) { |
493 | seq_printf(m, "Display IER:\t%08x\n", | |
494 | I915_READ(VLV_IER)); | |
495 | seq_printf(m, "Display IIR:\t%08x\n", | |
496 | I915_READ(VLV_IIR)); | |
497 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
498 | I915_READ(VLV_IIR_RW)); | |
499 | seq_printf(m, "Display IMR:\t%08x\n", | |
500 | I915_READ(VLV_IMR)); | |
501 | for_each_pipe(pipe) | |
502 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
503 | pipe_name(pipe), | |
504 | I915_READ(PIPESTAT(pipe))); | |
505 | ||
506 | seq_printf(m, "Master IER:\t%08x\n", | |
507 | I915_READ(VLV_MASTER_IER)); | |
508 | ||
509 | seq_printf(m, "Render IER:\t%08x\n", | |
510 | I915_READ(GTIER)); | |
511 | seq_printf(m, "Render IIR:\t%08x\n", | |
512 | I915_READ(GTIIR)); | |
513 | seq_printf(m, "Render IMR:\t%08x\n", | |
514 | I915_READ(GTIMR)); | |
515 | ||
516 | seq_printf(m, "PM IER:\t\t%08x\n", | |
517 | I915_READ(GEN6_PMIER)); | |
518 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
519 | I915_READ(GEN6_PMIIR)); | |
520 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
521 | I915_READ(GEN6_PMIMR)); | |
522 | ||
523 | seq_printf(m, "Port hotplug:\t%08x\n", | |
524 | I915_READ(PORT_HOTPLUG_EN)); | |
525 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
526 | I915_READ(VLV_DPFLIPSTAT)); | |
527 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
528 | I915_READ(DPINVGTT)); | |
529 | ||
530 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
531 | seq_printf(m, "Interrupt enable: %08x\n", |
532 | I915_READ(IER)); | |
533 | seq_printf(m, "Interrupt identity: %08x\n", | |
534 | I915_READ(IIR)); | |
535 | seq_printf(m, "Interrupt mask: %08x\n", | |
536 | I915_READ(IMR)); | |
9db4a9c7 JB |
537 | for_each_pipe(pipe) |
538 | seq_printf(m, "Pipe %c stat: %08x\n", | |
539 | pipe_name(pipe), | |
540 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
541 | } else { |
542 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
543 | I915_READ(DEIER)); | |
544 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
545 | I915_READ(DEIIR)); | |
546 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
547 | I915_READ(DEIMR)); | |
548 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
549 | I915_READ(SDEIER)); | |
550 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
551 | I915_READ(SDEIIR)); | |
552 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
553 | I915_READ(SDEIMR)); | |
554 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
555 | I915_READ(GTIER)); | |
556 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
557 | I915_READ(GTIIR)); | |
558 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
559 | I915_READ(GTIMR)); | |
560 | } | |
2017263e BG |
561 | seq_printf(m, "Interrupts received: %d\n", |
562 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 563 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 564 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
565 | seq_printf(m, |
566 | "Graphics Interrupt mask (%s): %08x\n", | |
567 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 568 | } |
a2c7f6fd | 569 | i915_ring_seqno_info(m, ring); |
9862e600 | 570 | } |
de227ef0 CW |
571 | mutex_unlock(&dev->struct_mutex); |
572 | ||
2017263e BG |
573 | return 0; |
574 | } | |
575 | ||
a6172a80 CW |
576 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
577 | { | |
578 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
579 | struct drm_device *dev = node->minor->dev; | |
580 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
581 | int i, ret; |
582 | ||
583 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
584 | if (ret) | |
585 | return ret; | |
a6172a80 CW |
586 | |
587 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
588 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
589 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 590 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 591 | |
6c085a72 CW |
592 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
593 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 594 | if (obj == NULL) |
267f0c90 | 595 | seq_puts(m, "unused"); |
c2c347a9 | 596 | else |
05394f39 | 597 | describe_obj(m, obj); |
267f0c90 | 598 | seq_putc(m, '\n'); |
a6172a80 CW |
599 | } |
600 | ||
05394f39 | 601 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
602 | return 0; |
603 | } | |
604 | ||
2017263e BG |
605 | static int i915_hws_info(struct seq_file *m, void *data) |
606 | { | |
607 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
608 | struct drm_device *dev = node->minor->dev; | |
609 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 610 | struct intel_ring_buffer *ring; |
1a240d4d | 611 | const u32 *hws; |
4066c0ae CW |
612 | int i; |
613 | ||
1ec14ad3 | 614 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 615 | hws = ring->status_page.page_addr; |
2017263e BG |
616 | if (hws == NULL) |
617 | return 0; | |
618 | ||
619 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
620 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
621 | i * 4, | |
622 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
623 | } | |
624 | return 0; | |
625 | } | |
626 | ||
d5442303 DV |
627 | static ssize_t |
628 | i915_error_state_write(struct file *filp, | |
629 | const char __user *ubuf, | |
630 | size_t cnt, | |
631 | loff_t *ppos) | |
632 | { | |
edc3d884 | 633 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 634 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 635 | int ret; |
d5442303 DV |
636 | |
637 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
638 | ||
22bcfc6a DV |
639 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
640 | if (ret) | |
641 | return ret; | |
642 | ||
d5442303 DV |
643 | i915_destroy_error_state(dev); |
644 | mutex_unlock(&dev->struct_mutex); | |
645 | ||
646 | return cnt; | |
647 | } | |
648 | ||
649 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
650 | { | |
651 | struct drm_device *dev = inode->i_private; | |
d5442303 | 652 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
653 | |
654 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
655 | if (!error_priv) | |
656 | return -ENOMEM; | |
657 | ||
658 | error_priv->dev = dev; | |
659 | ||
95d5bfb3 | 660 | i915_error_state_get(dev, error_priv); |
d5442303 | 661 | |
edc3d884 MK |
662 | file->private_data = error_priv; |
663 | ||
664 | return 0; | |
d5442303 DV |
665 | } |
666 | ||
667 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
668 | { | |
edc3d884 | 669 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 670 | |
95d5bfb3 | 671 | i915_error_state_put(error_priv); |
d5442303 DV |
672 | kfree(error_priv); |
673 | ||
edc3d884 MK |
674 | return 0; |
675 | } | |
676 | ||
4dc955f7 MK |
677 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
678 | size_t count, loff_t *pos) | |
679 | { | |
680 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
681 | struct drm_i915_error_state_buf error_str; | |
682 | loff_t tmp_pos = 0; | |
683 | ssize_t ret_count = 0; | |
684 | int ret; | |
685 | ||
686 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
687 | if (ret) | |
688 | return ret; | |
edc3d884 | 689 | |
fc16b48b | 690 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
691 | if (ret) |
692 | goto out; | |
693 | ||
edc3d884 MK |
694 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
695 | error_str.buf, | |
696 | error_str.bytes); | |
697 | ||
698 | if (ret_count < 0) | |
699 | ret = ret_count; | |
700 | else | |
701 | *pos = error_str.start + ret_count; | |
702 | out: | |
4dc955f7 | 703 | i915_error_state_buf_release(&error_str); |
edc3d884 | 704 | return ret ?: ret_count; |
d5442303 DV |
705 | } |
706 | ||
707 | static const struct file_operations i915_error_state_fops = { | |
708 | .owner = THIS_MODULE, | |
709 | .open = i915_error_state_open, | |
edc3d884 | 710 | .read = i915_error_state_read, |
d5442303 DV |
711 | .write = i915_error_state_write, |
712 | .llseek = default_llseek, | |
713 | .release = i915_error_state_release, | |
714 | }; | |
715 | ||
647416f9 KC |
716 | static int |
717 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 718 | { |
647416f9 | 719 | struct drm_device *dev = data; |
40633219 | 720 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
721 | int ret; |
722 | ||
723 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
647416f9 | 727 | *val = dev_priv->next_seqno; |
40633219 MK |
728 | mutex_unlock(&dev->struct_mutex); |
729 | ||
647416f9 | 730 | return 0; |
40633219 MK |
731 | } |
732 | ||
647416f9 KC |
733 | static int |
734 | i915_next_seqno_set(void *data, u64 val) | |
735 | { | |
736 | struct drm_device *dev = data; | |
40633219 MK |
737 | int ret; |
738 | ||
40633219 MK |
739 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
740 | if (ret) | |
741 | return ret; | |
742 | ||
e94fbaa8 | 743 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
744 | mutex_unlock(&dev->struct_mutex); |
745 | ||
647416f9 | 746 | return ret; |
40633219 MK |
747 | } |
748 | ||
647416f9 KC |
749 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
750 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 751 | "0x%llx\n"); |
40633219 | 752 | |
f97108d1 JB |
753 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
754 | { | |
755 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
756 | struct drm_device *dev = node->minor->dev; | |
757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
758 | u16 crstanddelay; |
759 | int ret; | |
760 | ||
761 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
762 | if (ret) | |
763 | return ret; | |
764 | ||
765 | crstanddelay = I915_READ16(CRSTANDVID); | |
766 | ||
767 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
768 | |
769 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
775 | { | |
776 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
777 | struct drm_device *dev = node->minor->dev; | |
778 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 779 | int ret; |
3b8d8d91 JB |
780 | |
781 | if (IS_GEN5(dev)) { | |
782 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
783 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
784 | ||
785 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
786 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
787 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
788 | MEMSTAT_VID_SHIFT); | |
789 | seq_printf(m, "Current P-state: %d\n", | |
790 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 791 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
792 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
793 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
794 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 795 | u32 rpstat, cagf; |
ccab5c82 JB |
796 | u32 rpupei, rpcurup, rpprevup; |
797 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
798 | int max_freq; |
799 | ||
800 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
801 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
802 | if (ret) | |
803 | return ret; | |
804 | ||
fcca7926 | 805 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 806 | |
ccab5c82 JB |
807 | rpstat = I915_READ(GEN6_RPSTAT1); |
808 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
809 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
810 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
811 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
812 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
813 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
814 | if (IS_HASWELL(dev)) |
815 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
816 | else | |
817 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
818 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 819 | |
d1ebd816 BW |
820 | gen6_gt_force_wake_put(dev_priv); |
821 | mutex_unlock(&dev->struct_mutex); | |
822 | ||
3b8d8d91 | 823 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 824 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
825 | seq_printf(m, "Render p-state ratio: %d\n", |
826 | (gt_perf_status & 0xff00) >> 8); | |
827 | seq_printf(m, "Render p-state VID: %d\n", | |
828 | gt_perf_status & 0xff); | |
829 | seq_printf(m, "Render p-state limit: %d\n", | |
830 | rp_state_limits & 0xff); | |
f82855d3 | 831 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
832 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
833 | GEN6_CURICONT_MASK); | |
834 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
835 | GEN6_CURBSYTAVG_MASK); | |
836 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
837 | GEN6_CURBSYTAVG_MASK); | |
838 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
839 | GEN6_CURIAVG_MASK); | |
840 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
841 | GEN6_CURBSYTAVG_MASK); | |
842 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
843 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
844 | |
845 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
846 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 847 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
848 | |
849 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
850 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 851 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
852 | |
853 | max_freq = rp_state_cap & 0xff; | |
854 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 855 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
856 | |
857 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
858 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
859 | } else if (IS_VALLEYVIEW(dev)) { |
860 | u32 freq_sts, val; | |
861 | ||
259bd5d4 | 862 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 863 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
864 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
865 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
866 | ||
64936258 | 867 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
868 | seq_printf(m, "max GPU freq: %d MHz\n", |
869 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
870 | ||
64936258 | 871 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
872 | seq_printf(m, "min GPU freq: %d MHz\n", |
873 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
874 | ||
875 | seq_printf(m, "current GPU freq: %d MHz\n", | |
876 | vlv_gpu_freq(dev_priv->mem_freq, | |
877 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 878 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 879 | } else { |
267f0c90 | 880 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 881 | } |
f97108d1 JB |
882 | |
883 | return 0; | |
884 | } | |
885 | ||
886 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
887 | { | |
888 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
889 | struct drm_device *dev = node->minor->dev; | |
890 | drm_i915_private_t *dev_priv = dev->dev_private; | |
891 | u32 delayfreq; | |
616fdb5a BW |
892 | int ret, i; |
893 | ||
894 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
895 | if (ret) | |
896 | return ret; | |
f97108d1 JB |
897 | |
898 | for (i = 0; i < 16; i++) { | |
899 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
900 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
901 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
902 | } |
903 | ||
616fdb5a BW |
904 | mutex_unlock(&dev->struct_mutex); |
905 | ||
f97108d1 JB |
906 | return 0; |
907 | } | |
908 | ||
909 | static inline int MAP_TO_MV(int map) | |
910 | { | |
911 | return 1250 - (map * 25); | |
912 | } | |
913 | ||
914 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
915 | { | |
916 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
917 | struct drm_device *dev = node->minor->dev; | |
918 | drm_i915_private_t *dev_priv = dev->dev_private; | |
919 | u32 inttoext; | |
616fdb5a BW |
920 | int ret, i; |
921 | ||
922 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
923 | if (ret) | |
924 | return ret; | |
f97108d1 JB |
925 | |
926 | for (i = 1; i <= 32; i++) { | |
927 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
928 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
929 | } | |
930 | ||
616fdb5a BW |
931 | mutex_unlock(&dev->struct_mutex); |
932 | ||
f97108d1 JB |
933 | return 0; |
934 | } | |
935 | ||
4d85529d | 936 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
937 | { |
938 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
939 | struct drm_device *dev = node->minor->dev; | |
940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
941 | u32 rgvmodectl, rstdbyctl; |
942 | u16 crstandvid; | |
943 | int ret; | |
944 | ||
945 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
946 | if (ret) | |
947 | return ret; | |
948 | ||
949 | rgvmodectl = I915_READ(MEMMODECTL); | |
950 | rstdbyctl = I915_READ(RSTDBYCTL); | |
951 | crstandvid = I915_READ16(CRSTANDVID); | |
952 | ||
953 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
954 | |
955 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
956 | "yes" : "no"); | |
957 | seq_printf(m, "Boost freq: %d\n", | |
958 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
959 | MEMMODE_BOOST_FREQ_SHIFT); | |
960 | seq_printf(m, "HW control enabled: %s\n", | |
961 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
962 | seq_printf(m, "SW control enabled: %s\n", | |
963 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
964 | seq_printf(m, "Gated voltage change: %s\n", | |
965 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
966 | seq_printf(m, "Starting frequency: P%d\n", | |
967 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 968 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 969 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
970 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
971 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
972 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
973 | seq_printf(m, "Render standby enabled: %s\n", | |
974 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 975 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
976 | switch (rstdbyctl & RSX_STATUS_MASK) { |
977 | case RSX_STATUS_ON: | |
267f0c90 | 978 | seq_puts(m, "on\n"); |
88271da3 JB |
979 | break; |
980 | case RSX_STATUS_RC1: | |
267f0c90 | 981 | seq_puts(m, "RC1\n"); |
88271da3 JB |
982 | break; |
983 | case RSX_STATUS_RC1E: | |
267f0c90 | 984 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
985 | break; |
986 | case RSX_STATUS_RS1: | |
267f0c90 | 987 | seq_puts(m, "RS1\n"); |
88271da3 JB |
988 | break; |
989 | case RSX_STATUS_RS2: | |
267f0c90 | 990 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
991 | break; |
992 | case RSX_STATUS_RS3: | |
267f0c90 | 993 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
994 | break; |
995 | default: | |
267f0c90 | 996 | seq_puts(m, "unknown\n"); |
88271da3 JB |
997 | break; |
998 | } | |
f97108d1 JB |
999 | |
1000 | return 0; | |
1001 | } | |
1002 | ||
4d85529d BW |
1003 | static int gen6_drpc_info(struct seq_file *m) |
1004 | { | |
1005 | ||
1006 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1007 | struct drm_device *dev = node->minor->dev; | |
1008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1009 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1010 | unsigned forcewake_count; |
aee56cff | 1011 | int count = 0, ret; |
4d85529d BW |
1012 | |
1013 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
907b28c5 CW |
1017 | spin_lock_irq(&dev_priv->uncore.lock); |
1018 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1019 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1020 | |
1021 | if (forcewake_count) { | |
267f0c90 DL |
1022 | seq_puts(m, "RC information inaccurate because somebody " |
1023 | "holds a forcewake reference \n"); | |
4d85529d BW |
1024 | } else { |
1025 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1026 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1027 | udelay(10); | |
1028 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1029 | } | |
1030 | ||
1031 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1032 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1033 | |
1034 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1035 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1036 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1037 | mutex_lock(&dev_priv->rps.hw_lock); |
1038 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1039 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1040 | |
1041 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1042 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1043 | seq_printf(m, "HW control enabled: %s\n", | |
1044 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1045 | seq_printf(m, "SW control enabled: %s\n", | |
1046 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1047 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1048 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1049 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1050 | seq_printf(m, "RC6 Enabled: %s\n", | |
1051 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1052 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1053 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1054 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1055 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1056 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1057 | switch (gt_core_status & GEN6_RCn_MASK) { |
1058 | case GEN6_RC0: | |
1059 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1060 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1061 | else |
267f0c90 | 1062 | seq_puts(m, "on\n"); |
4d85529d BW |
1063 | break; |
1064 | case GEN6_RC3: | |
267f0c90 | 1065 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1066 | break; |
1067 | case GEN6_RC6: | |
267f0c90 | 1068 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1069 | break; |
1070 | case GEN6_RC7: | |
267f0c90 | 1071 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1072 | break; |
1073 | default: | |
267f0c90 | 1074 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1075 | break; |
1076 | } | |
1077 | ||
1078 | seq_printf(m, "Core Power Down: %s\n", | |
1079 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1080 | |
1081 | /* Not exactly sure what this is */ | |
1082 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1083 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1084 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1085 | I915_READ(GEN6_GT_GFX_RC6)); | |
1086 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1087 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1088 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1089 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1090 | ||
ecd8faea BW |
1091 | seq_printf(m, "RC6 voltage: %dmV\n", |
1092 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1093 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1094 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1095 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1096 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1097 | return 0; |
1098 | } | |
1099 | ||
1100 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1101 | { | |
1102 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1103 | struct drm_device *dev = node->minor->dev; | |
1104 | ||
1105 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1106 | return gen6_drpc_info(m); | |
1107 | else | |
1108 | return ironlake_drpc_info(m); | |
1109 | } | |
1110 | ||
b5e50c3f JB |
1111 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1112 | { | |
1113 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1114 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1115 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1116 | |
ee5382ae | 1117 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1118 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1119 | return 0; |
1120 | } | |
1121 | ||
ee5382ae | 1122 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1123 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1124 | } else { |
267f0c90 | 1125 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1126 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1127 | case FBC_OK: |
1128 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1129 | break; | |
1130 | case FBC_UNSUPPORTED: | |
1131 | seq_puts(m, "unsupported by this chipset"); | |
1132 | break; | |
bed4a673 | 1133 | case FBC_NO_OUTPUT: |
267f0c90 | 1134 | seq_puts(m, "no outputs"); |
bed4a673 | 1135 | break; |
b5e50c3f | 1136 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1137 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1138 | break; |
1139 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1140 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1141 | break; |
1142 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1143 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1144 | break; |
1145 | case FBC_BAD_PLANE: | |
267f0c90 | 1146 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1147 | break; |
1148 | case FBC_NOT_TILED: | |
267f0c90 | 1149 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1150 | break; |
9c928d16 | 1151 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1152 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1153 | break; |
c1a9f047 | 1154 | case FBC_MODULE_PARAM: |
267f0c90 | 1155 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1156 | break; |
8a5729a3 | 1157 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1158 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1159 | break; |
b5e50c3f | 1160 | default: |
267f0c90 | 1161 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1162 | } |
267f0c90 | 1163 | seq_putc(m, '\n'); |
b5e50c3f JB |
1164 | } |
1165 | return 0; | |
1166 | } | |
1167 | ||
92d44621 PZ |
1168 | static int i915_ips_status(struct seq_file *m, void *unused) |
1169 | { | |
1170 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1171 | struct drm_device *dev = node->minor->dev; | |
1172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1173 | ||
f5adf94e | 1174 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1175 | seq_puts(m, "not supported\n"); |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1180 | seq_puts(m, "enabled\n"); | |
1181 | else | |
1182 | seq_puts(m, "disabled\n"); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
4a9bef37 JB |
1187 | static int i915_sr_status(struct seq_file *m, void *unused) |
1188 | { | |
1189 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1190 | struct drm_device *dev = node->minor->dev; | |
1191 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1192 | bool sr_enabled = false; | |
1193 | ||
1398261a | 1194 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1195 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1196 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1197 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1198 | else if (IS_I915GM(dev)) | |
1199 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1200 | else if (IS_PINEVIEW(dev)) | |
1201 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1202 | ||
5ba2aaaa CW |
1203 | seq_printf(m, "self-refresh: %s\n", |
1204 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1205 | |
1206 | return 0; | |
1207 | } | |
1208 | ||
7648fa99 JB |
1209 | static int i915_emon_status(struct seq_file *m, void *unused) |
1210 | { | |
1211 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1212 | struct drm_device *dev = node->minor->dev; | |
1213 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1214 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1215 | int ret; |
1216 | ||
582be6b4 CW |
1217 | if (!IS_GEN5(dev)) |
1218 | return -ENODEV; | |
1219 | ||
de227ef0 CW |
1220 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1221 | if (ret) | |
1222 | return ret; | |
7648fa99 JB |
1223 | |
1224 | temp = i915_mch_val(dev_priv); | |
1225 | chipset = i915_chipset_val(dev_priv); | |
1226 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1227 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1228 | |
1229 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1230 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1231 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1232 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
23b2f8bb JB |
1237 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1238 | { | |
1239 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1240 | struct drm_device *dev = node->minor->dev; | |
1241 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1242 | int ret; | |
1243 | int gpu_freq, ia_freq; | |
1244 | ||
1c70c0ce | 1245 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1246 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1247 | return 0; |
1248 | } | |
1249 | ||
4fc688ce | 1250 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1251 | if (ret) |
1252 | return ret; | |
1253 | ||
267f0c90 | 1254 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1255 | |
c6a828d3 DV |
1256 | for (gpu_freq = dev_priv->rps.min_delay; |
1257 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1258 | gpu_freq++) { |
42c0526c BW |
1259 | ia_freq = gpu_freq; |
1260 | sandybridge_pcode_read(dev_priv, | |
1261 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1262 | &ia_freq); | |
3ebecd07 CW |
1263 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1264 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1265 | ((ia_freq >> 0) & 0xff) * 100, | |
1266 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1267 | } |
1268 | ||
4fc688ce | 1269 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1270 | |
1271 | return 0; | |
1272 | } | |
1273 | ||
7648fa99 JB |
1274 | static int i915_gfxec(struct seq_file *m, void *unused) |
1275 | { | |
1276 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1277 | struct drm_device *dev = node->minor->dev; | |
1278 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1279 | int ret; |
1280 | ||
1281 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1282 | if (ret) | |
1283 | return ret; | |
7648fa99 JB |
1284 | |
1285 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1286 | ||
616fdb5a BW |
1287 | mutex_unlock(&dev->struct_mutex); |
1288 | ||
7648fa99 JB |
1289 | return 0; |
1290 | } | |
1291 | ||
44834a67 CW |
1292 | static int i915_opregion(struct seq_file *m, void *unused) |
1293 | { | |
1294 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1295 | struct drm_device *dev = node->minor->dev; | |
1296 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1297 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1298 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1299 | int ret; |
1300 | ||
0d38f009 DV |
1301 | if (data == NULL) |
1302 | return -ENOMEM; | |
1303 | ||
44834a67 CW |
1304 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1305 | if (ret) | |
0d38f009 | 1306 | goto out; |
44834a67 | 1307 | |
0d38f009 DV |
1308 | if (opregion->header) { |
1309 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1310 | seq_write(m, data, OPREGION_SIZE); | |
1311 | } | |
44834a67 CW |
1312 | |
1313 | mutex_unlock(&dev->struct_mutex); | |
1314 | ||
0d38f009 DV |
1315 | out: |
1316 | kfree(data); | |
44834a67 CW |
1317 | return 0; |
1318 | } | |
1319 | ||
37811fcc CW |
1320 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1321 | { | |
1322 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1323 | struct drm_device *dev = node->minor->dev; | |
1324 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1325 | struct intel_fbdev *ifbdev; | |
1326 | struct intel_framebuffer *fb; | |
1327 | int ret; | |
1328 | ||
1329 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1330 | if (ret) | |
1331 | return ret; | |
1332 | ||
1333 | ifbdev = dev_priv->fbdev; | |
1334 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1335 | ||
623f9783 | 1336 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1337 | fb->base.width, |
1338 | fb->base.height, | |
1339 | fb->base.depth, | |
623f9783 DV |
1340 | fb->base.bits_per_pixel, |
1341 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1342 | describe_obj(m, fb->obj); |
267f0c90 | 1343 | seq_putc(m, '\n'); |
4b096ac1 | 1344 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1345 | |
4b096ac1 | 1346 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1347 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1348 | if (&fb->base == ifbdev->helper.fb) | |
1349 | continue; | |
1350 | ||
623f9783 | 1351 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1352 | fb->base.width, |
1353 | fb->base.height, | |
1354 | fb->base.depth, | |
623f9783 DV |
1355 | fb->base.bits_per_pixel, |
1356 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1357 | describe_obj(m, fb->obj); |
267f0c90 | 1358 | seq_putc(m, '\n'); |
37811fcc | 1359 | } |
4b096ac1 | 1360 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1361 | |
1362 | return 0; | |
1363 | } | |
1364 | ||
e76d3630 BW |
1365 | static int i915_context_status(struct seq_file *m, void *unused) |
1366 | { | |
1367 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1368 | struct drm_device *dev = node->minor->dev; | |
1369 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1370 | struct intel_ring_buffer *ring; |
1371 | int ret, i; | |
e76d3630 BW |
1372 | |
1373 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1374 | if (ret) | |
1375 | return ret; | |
1376 | ||
3e373948 | 1377 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1378 | seq_puts(m, "power context "); |
3e373948 | 1379 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1380 | seq_putc(m, '\n'); |
dc501fbc | 1381 | } |
e76d3630 | 1382 | |
3e373948 | 1383 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1384 | seq_puts(m, "render context "); |
3e373948 | 1385 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1386 | seq_putc(m, '\n'); |
dc501fbc | 1387 | } |
e76d3630 | 1388 | |
a168c293 BW |
1389 | for_each_ring(ring, dev_priv, i) { |
1390 | if (ring->default_context) { | |
1391 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1392 | describe_obj(m, ring->default_context->obj); | |
267f0c90 | 1393 | seq_putc(m, '\n'); |
a168c293 BW |
1394 | } |
1395 | } | |
1396 | ||
e76d3630 BW |
1397 | mutex_unlock(&dev->mode_config.mutex); |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
6d794d42 BW |
1402 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1403 | { | |
1404 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1405 | struct drm_device *dev = node->minor->dev; | |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1407 | unsigned forcewake_count; |
6d794d42 | 1408 | |
907b28c5 CW |
1409 | spin_lock_irq(&dev_priv->uncore.lock); |
1410 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1411 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1412 | |
9f1f46a4 | 1413 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1414 | |
1415 | return 0; | |
1416 | } | |
1417 | ||
ea16a3cd DV |
1418 | static const char *swizzle_string(unsigned swizzle) |
1419 | { | |
aee56cff | 1420 | switch (swizzle) { |
ea16a3cd DV |
1421 | case I915_BIT_6_SWIZZLE_NONE: |
1422 | return "none"; | |
1423 | case I915_BIT_6_SWIZZLE_9: | |
1424 | return "bit9"; | |
1425 | case I915_BIT_6_SWIZZLE_9_10: | |
1426 | return "bit9/bit10"; | |
1427 | case I915_BIT_6_SWIZZLE_9_11: | |
1428 | return "bit9/bit11"; | |
1429 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1430 | return "bit9/bit10/bit11"; | |
1431 | case I915_BIT_6_SWIZZLE_9_17: | |
1432 | return "bit9/bit17"; | |
1433 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1434 | return "bit9/bit10/bit17"; | |
1435 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1436 | return "unknown"; |
ea16a3cd DV |
1437 | } |
1438 | ||
1439 | return "bug"; | |
1440 | } | |
1441 | ||
1442 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1443 | { | |
1444 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1445 | struct drm_device *dev = node->minor->dev; | |
1446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1447 | int ret; |
1448 | ||
1449 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1450 | if (ret) | |
1451 | return ret; | |
ea16a3cd | 1452 | |
ea16a3cd DV |
1453 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1454 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1455 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1456 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1457 | ||
1458 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1459 | seq_printf(m, "DDC = 0x%08x\n", | |
1460 | I915_READ(DCC)); | |
1461 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1462 | I915_READ16(C0DRB3)); | |
1463 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1464 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1465 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1466 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1467 | I915_READ(MAD_DIMM_C0)); | |
1468 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1469 | I915_READ(MAD_DIMM_C1)); | |
1470 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1471 | I915_READ(MAD_DIMM_C2)); | |
1472 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1473 | I915_READ(TILECTL)); | |
1474 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1475 | I915_READ(ARB_MODE)); | |
1476 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1477 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1478 | } |
1479 | mutex_unlock(&dev->struct_mutex); | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
3cf17fc5 DV |
1484 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1485 | { | |
1486 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1487 | struct drm_device *dev = node->minor->dev; | |
1488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1489 | struct intel_ring_buffer *ring; | |
1490 | int i, ret; | |
1491 | ||
1492 | ||
1493 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1494 | if (ret) | |
1495 | return ret; | |
1496 | if (INTEL_INFO(dev)->gen == 6) | |
1497 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1498 | ||
a2c7f6fd | 1499 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1500 | seq_printf(m, "%s\n", ring->name); |
1501 | if (INTEL_INFO(dev)->gen == 7) | |
1502 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1503 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1504 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1505 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1506 | } | |
1507 | if (dev_priv->mm.aliasing_ppgtt) { | |
1508 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1509 | ||
267f0c90 | 1510 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1511 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1512 | } | |
1513 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1514 | mutex_unlock(&dev->struct_mutex); | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
57f350b6 JB |
1519 | static int i915_dpio_info(struct seq_file *m, void *data) |
1520 | { | |
1521 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1522 | struct drm_device *dev = node->minor->dev; | |
1523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1524 | int ret; | |
1525 | ||
1526 | ||
1527 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1528 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1529 | return 0; |
1530 | } | |
1531 | ||
09153000 | 1532 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1533 | if (ret) |
1534 | return ret; | |
1535 | ||
1536 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1537 | ||
1538 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
ae99258f | 1539 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
57f350b6 | 1540 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
ae99258f | 1541 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
57f350b6 JB |
1542 | |
1543 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
ae99258f | 1544 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
57f350b6 | 1545 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
ae99258f | 1546 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
57f350b6 JB |
1547 | |
1548 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
ae99258f | 1549 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
57f350b6 | 1550 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
ae99258f | 1551 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
57f350b6 | 1552 | |
4abb2c39 VS |
1553 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
1554 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); | |
1555 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", | |
1556 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); | |
57f350b6 JB |
1557 | |
1558 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ae99258f | 1559 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1560 | |
09153000 | 1561 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1562 | |
1563 | return 0; | |
1564 | } | |
1565 | ||
63573eb7 BW |
1566 | static int i915_llc(struct seq_file *m, void *data) |
1567 | { | |
1568 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1569 | struct drm_device *dev = node->minor->dev; | |
1570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1571 | ||
1572 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1573 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1574 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
e91fd8c6 RV |
1579 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1580 | { | |
1581 | struct drm_info_node *node = m->private; | |
1582 | struct drm_device *dev = node->minor->dev; | |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3f51e471 | 1584 | u32 psrstat, psrperf; |
e91fd8c6 RV |
1585 | |
1586 | if (!IS_HASWELL(dev)) { | |
1587 | seq_puts(m, "PSR not supported on this platform\n"); | |
3f51e471 RV |
1588 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
1589 | seq_puts(m, "PSR enabled\n"); | |
1590 | } else { | |
1591 | seq_puts(m, "PSR disabled: "); | |
1592 | switch (dev_priv->no_psr_reason) { | |
1593 | case PSR_NO_SOURCE: | |
1594 | seq_puts(m, "not supported on this platform"); | |
1595 | break; | |
1596 | case PSR_NO_SINK: | |
1597 | seq_puts(m, "not supported by panel"); | |
1598 | break; | |
105b7c11 RV |
1599 | case PSR_MODULE_PARAM: |
1600 | seq_puts(m, "disabled by flag"); | |
1601 | break; | |
3f51e471 RV |
1602 | case PSR_CRTC_NOT_ACTIVE: |
1603 | seq_puts(m, "crtc not active"); | |
1604 | break; | |
1605 | case PSR_PWR_WELL_ENABLED: | |
1606 | seq_puts(m, "power well enabled"); | |
1607 | break; | |
1608 | case PSR_NOT_TILED: | |
1609 | seq_puts(m, "not tiled"); | |
1610 | break; | |
1611 | case PSR_SPRITE_ENABLED: | |
1612 | seq_puts(m, "sprite enabled"); | |
1613 | break; | |
1614 | case PSR_S3D_ENABLED: | |
1615 | seq_puts(m, "stereo 3d enabled"); | |
1616 | break; | |
1617 | case PSR_INTERLACED_ENABLED: | |
1618 | seq_puts(m, "interlaced enabled"); | |
1619 | break; | |
1620 | case PSR_HSW_NOT_DDIA: | |
1621 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); | |
1622 | break; | |
1623 | default: | |
1624 | seq_puts(m, "unknown reason"); | |
1625 | } | |
1626 | seq_puts(m, "\n"); | |
e91fd8c6 RV |
1627 | return 0; |
1628 | } | |
1629 | ||
e91fd8c6 RV |
1630 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
1631 | ||
1632 | seq_puts(m, "PSR Current State: "); | |
1633 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { | |
1634 | case EDP_PSR_STATUS_STATE_IDLE: | |
1635 | seq_puts(m, "Reset state\n"); | |
1636 | break; | |
1637 | case EDP_PSR_STATUS_STATE_SRDONACK: | |
1638 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); | |
1639 | break; | |
1640 | case EDP_PSR_STATUS_STATE_SRDENT: | |
1641 | seq_puts(m, "SRD entry\n"); | |
1642 | break; | |
1643 | case EDP_PSR_STATUS_STATE_BUFOFF: | |
1644 | seq_puts(m, "Wait for buffer turn off\n"); | |
1645 | break; | |
1646 | case EDP_PSR_STATUS_STATE_BUFON: | |
1647 | seq_puts(m, "Wait for buffer turn on\n"); | |
1648 | break; | |
1649 | case EDP_PSR_STATUS_STATE_AUXACK: | |
1650 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); | |
1651 | break; | |
1652 | case EDP_PSR_STATUS_STATE_SRDOFFACK: | |
1653 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); | |
1654 | break; | |
1655 | default: | |
1656 | seq_puts(m, "Unknown\n"); | |
1657 | break; | |
1658 | } | |
1659 | ||
1660 | seq_puts(m, "Link Status: "); | |
1661 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { | |
1662 | case EDP_PSR_STATUS_LINK_FULL_OFF: | |
1663 | seq_puts(m, "Link is fully off\n"); | |
1664 | break; | |
1665 | case EDP_PSR_STATUS_LINK_FULL_ON: | |
1666 | seq_puts(m, "Link is fully on\n"); | |
1667 | break; | |
1668 | case EDP_PSR_STATUS_LINK_STANDBY: | |
1669 | seq_puts(m, "Link is in standby\n"); | |
1670 | break; | |
1671 | default: | |
1672 | seq_puts(m, "Unknown\n"); | |
1673 | break; | |
1674 | } | |
1675 | ||
1676 | seq_printf(m, "PSR Entry Count: %u\n", | |
1677 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & | |
1678 | EDP_PSR_STATUS_COUNT_MASK); | |
1679 | ||
1680 | seq_printf(m, "Max Sleep Timer Counter: %u\n", | |
1681 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & | |
1682 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); | |
1683 | ||
1684 | seq_printf(m, "Had AUX error: %s\n", | |
1685 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); | |
1686 | ||
1687 | seq_printf(m, "Sending AUX: %s\n", | |
1688 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); | |
1689 | ||
1690 | seq_printf(m, "Sending Idle: %s\n", | |
1691 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); | |
1692 | ||
1693 | seq_printf(m, "Sending TP2 TP3: %s\n", | |
1694 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); | |
1695 | ||
1696 | seq_printf(m, "Sending TP1: %s\n", | |
1697 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); | |
1698 | ||
1699 | seq_printf(m, "Idle Count: %u\n", | |
1700 | psrstat & EDP_PSR_STATUS_IDLE_MASK); | |
1701 | ||
1702 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; | |
1703 | seq_printf(m, "Performance Counter: %u\n", psrperf); | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | ||
647416f9 KC |
1708 | static int |
1709 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1710 | { |
647416f9 | 1711 | struct drm_device *dev = data; |
f3cd474b | 1712 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1713 | |
647416f9 | 1714 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1715 | |
647416f9 | 1716 | return 0; |
f3cd474b CW |
1717 | } |
1718 | ||
647416f9 KC |
1719 | static int |
1720 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1721 | { |
647416f9 | 1722 | struct drm_device *dev = data; |
f3cd474b | 1723 | |
647416f9 | 1724 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1725 | i915_handle_error(dev, val); |
f3cd474b | 1726 | |
647416f9 | 1727 | return 0; |
f3cd474b CW |
1728 | } |
1729 | ||
647416f9 KC |
1730 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1731 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1732 | "%llu\n"); |
f3cd474b | 1733 | |
647416f9 KC |
1734 | static int |
1735 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1736 | { |
647416f9 | 1737 | struct drm_device *dev = data; |
e5eb3d63 | 1738 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1739 | |
647416f9 | 1740 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1741 | |
647416f9 | 1742 | return 0; |
e5eb3d63 DV |
1743 | } |
1744 | ||
647416f9 KC |
1745 | static int |
1746 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1747 | { |
647416f9 | 1748 | struct drm_device *dev = data; |
e5eb3d63 | 1749 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1750 | int ret; |
e5eb3d63 | 1751 | |
647416f9 | 1752 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1753 | |
22bcfc6a DV |
1754 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1755 | if (ret) | |
1756 | return ret; | |
1757 | ||
99584db3 | 1758 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1759 | mutex_unlock(&dev->struct_mutex); |
1760 | ||
647416f9 | 1761 | return 0; |
e5eb3d63 DV |
1762 | } |
1763 | ||
647416f9 KC |
1764 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1765 | i915_ring_stop_get, i915_ring_stop_set, | |
1766 | "0x%08llx\n"); | |
d5442303 | 1767 | |
dd624afd CW |
1768 | #define DROP_UNBOUND 0x1 |
1769 | #define DROP_BOUND 0x2 | |
1770 | #define DROP_RETIRE 0x4 | |
1771 | #define DROP_ACTIVE 0x8 | |
1772 | #define DROP_ALL (DROP_UNBOUND | \ | |
1773 | DROP_BOUND | \ | |
1774 | DROP_RETIRE | \ | |
1775 | DROP_ACTIVE) | |
647416f9 KC |
1776 | static int |
1777 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1778 | { |
647416f9 | 1779 | *val = DROP_ALL; |
dd624afd | 1780 | |
647416f9 | 1781 | return 0; |
dd624afd CW |
1782 | } |
1783 | ||
647416f9 KC |
1784 | static int |
1785 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1786 | { |
647416f9 | 1787 | struct drm_device *dev = data; |
dd624afd CW |
1788 | struct drm_i915_private *dev_priv = dev->dev_private; |
1789 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1790 | struct i915_address_space *vm; |
1791 | struct i915_vma *vma, *x; | |
647416f9 | 1792 | int ret; |
dd624afd | 1793 | |
647416f9 | 1794 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1795 | |
1796 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1797 | * on ioctls on -EAGAIN. */ | |
1798 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1799 | if (ret) | |
1800 | return ret; | |
1801 | ||
1802 | if (val & DROP_ACTIVE) { | |
1803 | ret = i915_gpu_idle(dev); | |
1804 | if (ret) | |
1805 | goto unlock; | |
1806 | } | |
1807 | ||
1808 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1809 | i915_gem_retire_requests(dev); | |
1810 | ||
1811 | if (val & DROP_BOUND) { | |
ca191b13 BW |
1812 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1813 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
1814 | mm_list) { | |
1815 | if (vma->obj->pin_count) | |
1816 | continue; | |
1817 | ||
1818 | ret = i915_vma_unbind(vma); | |
1819 | if (ret) | |
1820 | goto unlock; | |
1821 | } | |
31a46c9c | 1822 | } |
dd624afd CW |
1823 | } |
1824 | ||
1825 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1826 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1827 | global_list) | |
dd624afd CW |
1828 | if (obj->pages_pin_count == 0) { |
1829 | ret = i915_gem_object_put_pages(obj); | |
1830 | if (ret) | |
1831 | goto unlock; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | unlock: | |
1836 | mutex_unlock(&dev->struct_mutex); | |
1837 | ||
647416f9 | 1838 | return ret; |
dd624afd CW |
1839 | } |
1840 | ||
647416f9 KC |
1841 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1842 | i915_drop_caches_get, i915_drop_caches_set, | |
1843 | "0x%08llx\n"); | |
dd624afd | 1844 | |
647416f9 KC |
1845 | static int |
1846 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1847 | { |
647416f9 | 1848 | struct drm_device *dev = data; |
358733e9 | 1849 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1850 | int ret; |
004777cb DV |
1851 | |
1852 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1853 | return -ENODEV; | |
1854 | ||
4fc688ce | 1855 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1856 | if (ret) |
1857 | return ret; | |
358733e9 | 1858 | |
0a073b84 JB |
1859 | if (IS_VALLEYVIEW(dev)) |
1860 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1861 | dev_priv->rps.max_delay); | |
1862 | else | |
1863 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1864 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1865 | |
647416f9 | 1866 | return 0; |
358733e9 JB |
1867 | } |
1868 | ||
647416f9 KC |
1869 | static int |
1870 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1871 | { |
647416f9 | 1872 | struct drm_device *dev = data; |
358733e9 | 1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1874 | int ret; |
004777cb DV |
1875 | |
1876 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1877 | return -ENODEV; | |
358733e9 | 1878 | |
647416f9 | 1879 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 1880 | |
4fc688ce | 1881 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1882 | if (ret) |
1883 | return ret; | |
1884 | ||
358733e9 JB |
1885 | /* |
1886 | * Turbo will still be enabled, but won't go above the set value. | |
1887 | */ | |
0a073b84 JB |
1888 | if (IS_VALLEYVIEW(dev)) { |
1889 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1890 | dev_priv->rps.max_delay = val; | |
1891 | gen6_set_rps(dev, val); | |
1892 | } else { | |
1893 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1894 | dev_priv->rps.max_delay = val; | |
1895 | gen6_set_rps(dev, val); | |
1896 | } | |
1897 | ||
4fc688ce | 1898 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1899 | |
647416f9 | 1900 | return 0; |
358733e9 JB |
1901 | } |
1902 | ||
647416f9 KC |
1903 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
1904 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 1905 | "%llu\n"); |
358733e9 | 1906 | |
647416f9 KC |
1907 | static int |
1908 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 1909 | { |
647416f9 | 1910 | struct drm_device *dev = data; |
1523c310 | 1911 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1912 | int ret; |
004777cb DV |
1913 | |
1914 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1915 | return -ENODEV; | |
1916 | ||
4fc688ce | 1917 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1918 | if (ret) |
1919 | return ret; | |
1523c310 | 1920 | |
0a073b84 JB |
1921 | if (IS_VALLEYVIEW(dev)) |
1922 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1923 | dev_priv->rps.min_delay); | |
1924 | else | |
1925 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1926 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1927 | |
647416f9 | 1928 | return 0; |
1523c310 JB |
1929 | } |
1930 | ||
647416f9 KC |
1931 | static int |
1932 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 1933 | { |
647416f9 | 1934 | struct drm_device *dev = data; |
1523c310 | 1935 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1936 | int ret; |
004777cb DV |
1937 | |
1938 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1939 | return -ENODEV; | |
1523c310 | 1940 | |
647416f9 | 1941 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 1942 | |
4fc688ce | 1943 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1944 | if (ret) |
1945 | return ret; | |
1946 | ||
1523c310 JB |
1947 | /* |
1948 | * Turbo will still be enabled, but won't go below the set value. | |
1949 | */ | |
0a073b84 JB |
1950 | if (IS_VALLEYVIEW(dev)) { |
1951 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1952 | dev_priv->rps.min_delay = val; | |
1953 | valleyview_set_rps(dev, val); | |
1954 | } else { | |
1955 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1956 | dev_priv->rps.min_delay = val; | |
1957 | gen6_set_rps(dev, val); | |
1958 | } | |
4fc688ce | 1959 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1960 | |
647416f9 | 1961 | return 0; |
1523c310 JB |
1962 | } |
1963 | ||
647416f9 KC |
1964 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
1965 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 1966 | "%llu\n"); |
1523c310 | 1967 | |
647416f9 KC |
1968 | static int |
1969 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 1970 | { |
647416f9 | 1971 | struct drm_device *dev = data; |
07b7ddd9 | 1972 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 1973 | u32 snpcr; |
647416f9 | 1974 | int ret; |
07b7ddd9 | 1975 | |
004777cb DV |
1976 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1977 | return -ENODEV; | |
1978 | ||
22bcfc6a DV |
1979 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1980 | if (ret) | |
1981 | return ret; | |
1982 | ||
07b7ddd9 JB |
1983 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
1984 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1985 | ||
647416f9 | 1986 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 1987 | |
647416f9 | 1988 | return 0; |
07b7ddd9 JB |
1989 | } |
1990 | ||
647416f9 KC |
1991 | static int |
1992 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 1993 | { |
647416f9 | 1994 | struct drm_device *dev = data; |
07b7ddd9 | 1995 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 1996 | u32 snpcr; |
07b7ddd9 | 1997 | |
004777cb DV |
1998 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1999 | return -ENODEV; | |
2000 | ||
647416f9 | 2001 | if (val > 3) |
07b7ddd9 JB |
2002 | return -EINVAL; |
2003 | ||
647416f9 | 2004 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2005 | |
2006 | /* Update the cache sharing policy here as well */ | |
2007 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2008 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2009 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2010 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2011 | ||
647416f9 | 2012 | return 0; |
07b7ddd9 JB |
2013 | } |
2014 | ||
647416f9 KC |
2015 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2016 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2017 | "%llu\n"); | |
07b7ddd9 | 2018 | |
f3cd474b CW |
2019 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2020 | * allocated we need to hook into the minor for release. */ | |
2021 | static int | |
2022 | drm_add_fake_info_node(struct drm_minor *minor, | |
2023 | struct dentry *ent, | |
2024 | const void *key) | |
2025 | { | |
2026 | struct drm_info_node *node; | |
2027 | ||
2028 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2029 | if (node == NULL) { | |
2030 | debugfs_remove(ent); | |
2031 | return -ENOMEM; | |
2032 | } | |
2033 | ||
2034 | node->minor = minor; | |
2035 | node->dent = ent; | |
2036 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2037 | |
2038 | mutex_lock(&minor->debugfs_lock); | |
2039 | list_add(&node->list, &minor->debugfs_list); | |
2040 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2041 | |
2042 | return 0; | |
2043 | } | |
2044 | ||
6d794d42 BW |
2045 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2046 | { | |
2047 | struct drm_device *dev = inode->i_private; | |
2048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2049 | |
075edca4 | 2050 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2051 | return 0; |
2052 | ||
6d794d42 | 2053 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2054 | |
2055 | return 0; | |
2056 | } | |
2057 | ||
c43b5634 | 2058 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2059 | { |
2060 | struct drm_device *dev = inode->i_private; | |
2061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2062 | ||
075edca4 | 2063 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2064 | return 0; |
2065 | ||
6d794d42 | 2066 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2067 | |
2068 | return 0; | |
2069 | } | |
2070 | ||
2071 | static const struct file_operations i915_forcewake_fops = { | |
2072 | .owner = THIS_MODULE, | |
2073 | .open = i915_forcewake_open, | |
2074 | .release = i915_forcewake_release, | |
2075 | }; | |
2076 | ||
2077 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2078 | { | |
2079 | struct drm_device *dev = minor->dev; | |
2080 | struct dentry *ent; | |
2081 | ||
2082 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2083 | S_IRUSR, |
6d794d42 BW |
2084 | root, dev, |
2085 | &i915_forcewake_fops); | |
2086 | if (IS_ERR(ent)) | |
2087 | return PTR_ERR(ent); | |
2088 | ||
8eb57294 | 2089 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2090 | } |
2091 | ||
6a9c308d DV |
2092 | static int i915_debugfs_create(struct dentry *root, |
2093 | struct drm_minor *minor, | |
2094 | const char *name, | |
2095 | const struct file_operations *fops) | |
07b7ddd9 JB |
2096 | { |
2097 | struct drm_device *dev = minor->dev; | |
2098 | struct dentry *ent; | |
2099 | ||
6a9c308d | 2100 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2101 | S_IRUGO | S_IWUSR, |
2102 | root, dev, | |
6a9c308d | 2103 | fops); |
07b7ddd9 JB |
2104 | if (IS_ERR(ent)) |
2105 | return PTR_ERR(ent); | |
2106 | ||
6a9c308d | 2107 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2108 | } |
2109 | ||
27c202ad | 2110 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2111 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2112 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2113 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2114 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2115 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2116 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 2117 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2118 | {"i915_gem_request", i915_gem_request_info, 0}, |
2119 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2120 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2121 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2122 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2123 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2124 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2125 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2126 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2127 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2128 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2129 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2130 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2131 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2132 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2133 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2134 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2135 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2136 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2137 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2138 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2139 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2140 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2141 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2142 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2143 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2144 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2145 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
2017263e | 2146 | }; |
27c202ad | 2147 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2148 | |
2b4bd0e0 | 2149 | static struct i915_debugfs_files { |
34b9674c DV |
2150 | const char *name; |
2151 | const struct file_operations *fops; | |
2152 | } i915_debugfs_files[] = { | |
2153 | {"i915_wedged", &i915_wedged_fops}, | |
2154 | {"i915_max_freq", &i915_max_freq_fops}, | |
2155 | {"i915_min_freq", &i915_min_freq_fops}, | |
2156 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2157 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
2158 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, | |
2159 | {"i915_error_state", &i915_error_state_fops}, | |
2160 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2161 | }; | |
2162 | ||
27c202ad | 2163 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2164 | { |
34b9674c | 2165 | int ret, i; |
f3cd474b | 2166 | |
6d794d42 | 2167 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2168 | if (ret) |
2169 | return ret; | |
6a9c308d | 2170 | |
34b9674c DV |
2171 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2172 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2173 | i915_debugfs_files[i].name, | |
2174 | i915_debugfs_files[i].fops); | |
2175 | if (ret) | |
2176 | return ret; | |
2177 | } | |
40633219 | 2178 | |
27c202ad BG |
2179 | return drm_debugfs_create_files(i915_debugfs_list, |
2180 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2181 | minor->debugfs_root, minor); |
2182 | } | |
2183 | ||
27c202ad | 2184 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2185 | { |
34b9674c DV |
2186 | int i; |
2187 | ||
27c202ad BG |
2188 | drm_debugfs_remove_files(i915_debugfs_list, |
2189 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2190 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2191 | 1, minor); | |
34b9674c DV |
2192 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2193 | struct drm_info_list *info_list = | |
2194 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2195 | ||
2196 | drm_debugfs_remove_files(info_list, 1, minor); | |
2197 | } | |
2017263e BG |
2198 | } |
2199 | ||
2200 | #endif /* CONFIG_DEBUG_FS */ |