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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
82 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
83 | struct drm_device *dev = node->minor->dev; | |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
d7f46fc4 | 101 | else if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 BW |
126 | int pin_count = 0; |
127 | ||
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
145 | if (vma->pin_count > 0) | |
146 | pin_count++; | |
147 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
148 | if (obj->pin_display) |
149 | seq_printf(m, " (display)"); | |
37811fcc CW |
150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
151 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
153 | if (!i915_is_ggtt(vma->vm)) | |
154 | seq_puts(m, " (pp"); | |
155 | else | |
156 | seq_puts(m, " (g"); | |
157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
158 | vma->node.start, vma->node.size); | |
159 | } | |
c1ad11fc CW |
160 | if (obj->stolen) |
161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
69dc4987 CW |
171 | if (obj->ring != NULL) |
172 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
173 | } |
174 | ||
3ccfd19d BW |
175 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
176 | { | |
177 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
178 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
179 | seq_putc(m, ' '); | |
180 | } | |
181 | ||
433e12f7 | 182 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
183 | { |
184 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
185 | uintptr_t list = (uintptr_t) node->info_ent->data; |
186 | struct list_head *head; | |
2017263e | 187 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
188 | struct drm_i915_private *dev_priv = dev->dev_private; |
189 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 190 | struct i915_vma *vma; |
8f2480fb CW |
191 | size_t total_obj_size, total_gtt_size; |
192 | int count, ret; | |
de227ef0 CW |
193 | |
194 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
195 | if (ret) | |
196 | return ret; | |
2017263e | 197 | |
ca191b13 | 198 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
199 | switch (list) { |
200 | case ACTIVE_LIST: | |
267f0c90 | 201 | seq_puts(m, "Active:\n"); |
5cef07e1 | 202 | head = &vm->active_list; |
433e12f7 BG |
203 | break; |
204 | case INACTIVE_LIST: | |
267f0c90 | 205 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 206 | head = &vm->inactive_list; |
433e12f7 | 207 | break; |
433e12f7 | 208 | default: |
de227ef0 CW |
209 | mutex_unlock(&dev->struct_mutex); |
210 | return -EINVAL; | |
2017263e | 211 | } |
2017263e | 212 | |
8f2480fb | 213 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
214 | list_for_each_entry(vma, head, mm_list) { |
215 | seq_printf(m, " "); | |
216 | describe_obj(m, vma->obj); | |
217 | seq_printf(m, "\n"); | |
218 | total_obj_size += vma->obj->base.size; | |
219 | total_gtt_size += vma->node.size; | |
8f2480fb | 220 | count++; |
2017263e | 221 | } |
de227ef0 | 222 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 223 | |
8f2480fb CW |
224 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
225 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
226 | return 0; |
227 | } | |
228 | ||
6d2b8885 CW |
229 | static int obj_rank_by_stolen(void *priv, |
230 | struct list_head *A, struct list_head *B) | |
231 | { | |
232 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 233 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 234 | struct drm_i915_gem_object *b = |
b25cb2f8 | 235 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
236 | |
237 | return a->stolen->start - b->stolen->start; | |
238 | } | |
239 | ||
240 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
241 | { | |
242 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
243 | struct drm_device *dev = node->minor->dev; | |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
245 | struct drm_i915_gem_object *obj; | |
246 | size_t total_obj_size, total_gtt_size; | |
247 | LIST_HEAD(stolen); | |
248 | int count, ret; | |
249 | ||
250 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
251 | if (ret) | |
252 | return ret; | |
253 | ||
254 | total_obj_size = total_gtt_size = count = 0; | |
255 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
256 | if (obj->stolen == NULL) | |
257 | continue; | |
258 | ||
b25cb2f8 | 259 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
260 | |
261 | total_obj_size += obj->base.size; | |
262 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
263 | count++; | |
264 | } | |
265 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
266 | if (obj->stolen == NULL) | |
267 | continue; | |
268 | ||
b25cb2f8 | 269 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
270 | |
271 | total_obj_size += obj->base.size; | |
272 | count++; | |
273 | } | |
274 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
275 | seq_puts(m, "Stolen:\n"); | |
276 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 277 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
278 | seq_puts(m, " "); |
279 | describe_obj(m, obj); | |
280 | seq_putc(m, '\n'); | |
b25cb2f8 | 281 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
282 | } |
283 | mutex_unlock(&dev->struct_mutex); | |
284 | ||
285 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
286 | count, total_obj_size, total_gtt_size); | |
287 | return 0; | |
288 | } | |
289 | ||
6299f992 CW |
290 | #define count_objects(list, member) do { \ |
291 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 292 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
293 | ++count; \ |
294 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 295 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
296 | ++mappable_count; \ |
297 | } \ | |
298 | } \ | |
0206e353 | 299 | } while (0) |
6299f992 | 300 | |
2db8e9d6 CW |
301 | struct file_stats { |
302 | int count; | |
303 | size_t total, active, inactive, unbound; | |
304 | }; | |
305 | ||
306 | static int per_file_stats(int id, void *ptr, void *data) | |
307 | { | |
308 | struct drm_i915_gem_object *obj = ptr; | |
309 | struct file_stats *stats = data; | |
310 | ||
311 | stats->count++; | |
312 | stats->total += obj->base.size; | |
313 | ||
f343c5f6 | 314 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
315 | if (!list_empty(&obj->ring_list)) |
316 | stats->active += obj->base.size; | |
317 | else | |
318 | stats->inactive += obj->base.size; | |
319 | } else { | |
320 | if (!list_empty(&obj->global_list)) | |
321 | stats->unbound += obj->base.size; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
ca191b13 BW |
327 | #define count_vmas(list, member) do { \ |
328 | list_for_each_entry(vma, list, member) { \ | |
329 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
330 | ++count; \ | |
331 | if (vma->obj->map_and_fenceable) { \ | |
332 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
333 | ++mappable_count; \ | |
334 | } \ | |
335 | } \ | |
336 | } while (0) | |
337 | ||
338 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
339 | { |
340 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
341 | struct drm_device *dev = node->minor->dev; | |
342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
343 | u32 count, mappable_count, purgeable_count; |
344 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 345 | struct drm_i915_gem_object *obj; |
5cef07e1 | 346 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 347 | struct drm_file *file; |
ca191b13 | 348 | struct i915_vma *vma; |
73aa808f CW |
349 | int ret; |
350 | ||
351 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
352 | if (ret) | |
353 | return ret; | |
354 | ||
6299f992 CW |
355 | seq_printf(m, "%u objects, %zu bytes\n", |
356 | dev_priv->mm.object_count, | |
357 | dev_priv->mm.object_memory); | |
358 | ||
359 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 360 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
361 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
362 | count, mappable_count, size, mappable_size); | |
363 | ||
364 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 365 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
366 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
367 | count, mappable_count, size, mappable_size); | |
368 | ||
6299f992 | 369 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 370 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
371 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
372 | count, mappable_count, size, mappable_size); | |
373 | ||
b7abb714 | 374 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 375 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 376 | size += obj->base.size, ++count; |
b7abb714 CW |
377 | if (obj->madv == I915_MADV_DONTNEED) |
378 | purgeable_size += obj->base.size, ++purgeable_count; | |
379 | } | |
6c085a72 CW |
380 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
381 | ||
6299f992 | 382 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 383 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 384 | if (obj->fault_mappable) { |
f343c5f6 | 385 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
386 | ++count; |
387 | } | |
388 | if (obj->pin_mappable) { | |
f343c5f6 | 389 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
390 | ++mappable_count; |
391 | } | |
b7abb714 CW |
392 | if (obj->madv == I915_MADV_DONTNEED) { |
393 | purgeable_size += obj->base.size; | |
394 | ++purgeable_count; | |
395 | } | |
6299f992 | 396 | } |
b7abb714 CW |
397 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
398 | purgeable_count, purgeable_size); | |
6299f992 CW |
399 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
400 | mappable_count, mappable_size); | |
401 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
402 | count, size); | |
403 | ||
93d18799 | 404 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
405 | dev_priv->gtt.base.total, |
406 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 407 | |
267f0c90 | 408 | seq_putc(m, '\n'); |
2db8e9d6 CW |
409 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
410 | struct file_stats stats; | |
3ec2f427 | 411 | struct task_struct *task; |
2db8e9d6 CW |
412 | |
413 | memset(&stats, 0, sizeof(stats)); | |
414 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
3ec2f427 TH |
415 | /* |
416 | * Although we have a valid reference on file->pid, that does | |
417 | * not guarantee that the task_struct who called get_pid() is | |
418 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
419 | * Therefore, we need to protect this ->comm access using RCU. | |
420 | */ | |
421 | rcu_read_lock(); | |
422 | task = pid_task(file->pid, PIDTYPE_PID); | |
2db8e9d6 | 423 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", |
3ec2f427 | 424 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
425 | stats.count, |
426 | stats.total, | |
427 | stats.active, | |
428 | stats.inactive, | |
429 | stats.unbound); | |
3ec2f427 | 430 | rcu_read_unlock(); |
2db8e9d6 CW |
431 | } |
432 | ||
73aa808f CW |
433 | mutex_unlock(&dev->struct_mutex); |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
aee56cff | 438 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
439 | { |
440 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
441 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 442 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
443 | struct drm_i915_private *dev_priv = dev->dev_private; |
444 | struct drm_i915_gem_object *obj; | |
445 | size_t total_obj_size, total_gtt_size; | |
446 | int count, ret; | |
447 | ||
448 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
449 | if (ret) | |
450 | return ret; | |
451 | ||
452 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 453 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 454 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
455 | continue; |
456 | ||
267f0c90 | 457 | seq_puts(m, " "); |
08c18323 | 458 | describe_obj(m, obj); |
267f0c90 | 459 | seq_putc(m, '\n'); |
08c18323 | 460 | total_obj_size += obj->base.size; |
f343c5f6 | 461 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
462 | count++; |
463 | } | |
464 | ||
465 | mutex_unlock(&dev->struct_mutex); | |
466 | ||
467 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
468 | count, total_obj_size, total_gtt_size); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
4e5359cd SF |
473 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
474 | { | |
475 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
476 | struct drm_device *dev = node->minor->dev; | |
477 | unsigned long flags; | |
478 | struct intel_crtc *crtc; | |
479 | ||
480 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
481 | const char pipe = pipe_name(crtc->pipe); |
482 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
483 | struct intel_unpin_work *work; |
484 | ||
485 | spin_lock_irqsave(&dev->event_lock, flags); | |
486 | work = crtc->unpin_work; | |
487 | if (work == NULL) { | |
9db4a9c7 | 488 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
489 | pipe, plane); |
490 | } else { | |
e7d841ca | 491 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 492 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
493 | pipe, plane); |
494 | } else { | |
9db4a9c7 | 495 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
496 | pipe, plane); |
497 | } | |
498 | if (work->enable_stall_check) | |
267f0c90 | 499 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 500 | else |
267f0c90 | 501 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 502 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
503 | |
504 | if (work->old_fb_obj) { | |
05394f39 CW |
505 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
506 | if (obj) | |
f343c5f6 BW |
507 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
508 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
509 | } |
510 | if (work->pending_flip_obj) { | |
05394f39 CW |
511 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
512 | if (obj) | |
f343c5f6 BW |
513 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
514 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
515 | } |
516 | } | |
517 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
2017263e BG |
523 | static int i915_gem_request_info(struct seq_file *m, void *data) |
524 | { | |
525 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
526 | struct drm_device *dev = node->minor->dev; | |
527 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 528 | struct intel_ring_buffer *ring; |
2017263e | 529 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 530 | int ret, count, i; |
de227ef0 CW |
531 | |
532 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
533 | if (ret) | |
534 | return ret; | |
2017263e | 535 | |
c2c347a9 | 536 | count = 0; |
a2c7f6fd CW |
537 | for_each_ring(ring, dev_priv, i) { |
538 | if (list_empty(&ring->request_list)) | |
539 | continue; | |
540 | ||
541 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 542 | list_for_each_entry(gem_request, |
a2c7f6fd | 543 | &ring->request_list, |
c2c347a9 CW |
544 | list) { |
545 | seq_printf(m, " %d @ %d\n", | |
546 | gem_request->seqno, | |
547 | (int) (jiffies - gem_request->emitted_jiffies)); | |
548 | } | |
549 | count++; | |
2017263e | 550 | } |
de227ef0 CW |
551 | mutex_unlock(&dev->struct_mutex); |
552 | ||
c2c347a9 | 553 | if (count == 0) |
267f0c90 | 554 | seq_puts(m, "No requests\n"); |
c2c347a9 | 555 | |
2017263e BG |
556 | return 0; |
557 | } | |
558 | ||
b2223497 CW |
559 | static void i915_ring_seqno_info(struct seq_file *m, |
560 | struct intel_ring_buffer *ring) | |
561 | { | |
562 | if (ring->get_seqno) { | |
43a7b924 | 563 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 564 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
565 | } |
566 | } | |
567 | ||
2017263e BG |
568 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
569 | { | |
570 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
571 | struct drm_device *dev = node->minor->dev; | |
572 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 573 | struct intel_ring_buffer *ring; |
1ec14ad3 | 574 | int ret, i; |
de227ef0 CW |
575 | |
576 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
577 | if (ret) | |
578 | return ret; | |
c8c8fb33 | 579 | intel_runtime_pm_get(dev_priv); |
2017263e | 580 | |
a2c7f6fd CW |
581 | for_each_ring(ring, dev_priv, i) |
582 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 583 | |
c8c8fb33 | 584 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
585 | mutex_unlock(&dev->struct_mutex); |
586 | ||
2017263e BG |
587 | return 0; |
588 | } | |
589 | ||
590 | ||
591 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
592 | { | |
593 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
594 | struct drm_device *dev = node->minor->dev; | |
595 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 596 | struct intel_ring_buffer *ring; |
9db4a9c7 | 597 | int ret, i, pipe; |
de227ef0 CW |
598 | |
599 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
600 | if (ret) | |
601 | return ret; | |
c8c8fb33 | 602 | intel_runtime_pm_get(dev_priv); |
2017263e | 603 | |
a123f157 BW |
604 | if (INTEL_INFO(dev)->gen >= 8) { |
605 | int i; | |
606 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
607 | I915_READ(GEN8_MASTER_IRQ)); | |
608 | ||
609 | for (i = 0; i < 4; i++) { | |
610 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
611 | i, I915_READ(GEN8_GT_IMR(i))); | |
612 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
613 | i, I915_READ(GEN8_GT_IIR(i))); | |
614 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
615 | i, I915_READ(GEN8_GT_IER(i))); | |
616 | } | |
617 | ||
618 | for_each_pipe(i) { | |
619 | seq_printf(m, "Pipe %c IMR:\t%08x\n", | |
620 | pipe_name(i), | |
621 | I915_READ(GEN8_DE_PIPE_IMR(i))); | |
622 | seq_printf(m, "Pipe %c IIR:\t%08x\n", | |
623 | pipe_name(i), | |
624 | I915_READ(GEN8_DE_PIPE_IIR(i))); | |
625 | seq_printf(m, "Pipe %c IER:\t%08x\n", | |
626 | pipe_name(i), | |
627 | I915_READ(GEN8_DE_PIPE_IER(i))); | |
628 | } | |
629 | ||
630 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
631 | I915_READ(GEN8_DE_PORT_IMR)); | |
632 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
633 | I915_READ(GEN8_DE_PORT_IIR)); | |
634 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
635 | I915_READ(GEN8_DE_PORT_IER)); | |
636 | ||
637 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
638 | I915_READ(GEN8_DE_MISC_IMR)); | |
639 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
640 | I915_READ(GEN8_DE_MISC_IIR)); | |
641 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
642 | I915_READ(GEN8_DE_MISC_IER)); | |
643 | ||
644 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
645 | I915_READ(GEN8_PCU_IMR)); | |
646 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
647 | I915_READ(GEN8_PCU_IIR)); | |
648 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
649 | I915_READ(GEN8_PCU_IER)); | |
650 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
651 | seq_printf(m, "Display IER:\t%08x\n", |
652 | I915_READ(VLV_IER)); | |
653 | seq_printf(m, "Display IIR:\t%08x\n", | |
654 | I915_READ(VLV_IIR)); | |
655 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
656 | I915_READ(VLV_IIR_RW)); | |
657 | seq_printf(m, "Display IMR:\t%08x\n", | |
658 | I915_READ(VLV_IMR)); | |
659 | for_each_pipe(pipe) | |
660 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
661 | pipe_name(pipe), | |
662 | I915_READ(PIPESTAT(pipe))); | |
663 | ||
664 | seq_printf(m, "Master IER:\t%08x\n", | |
665 | I915_READ(VLV_MASTER_IER)); | |
666 | ||
667 | seq_printf(m, "Render IER:\t%08x\n", | |
668 | I915_READ(GTIER)); | |
669 | seq_printf(m, "Render IIR:\t%08x\n", | |
670 | I915_READ(GTIIR)); | |
671 | seq_printf(m, "Render IMR:\t%08x\n", | |
672 | I915_READ(GTIMR)); | |
673 | ||
674 | seq_printf(m, "PM IER:\t\t%08x\n", | |
675 | I915_READ(GEN6_PMIER)); | |
676 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
677 | I915_READ(GEN6_PMIIR)); | |
678 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
679 | I915_READ(GEN6_PMIMR)); | |
680 | ||
681 | seq_printf(m, "Port hotplug:\t%08x\n", | |
682 | I915_READ(PORT_HOTPLUG_EN)); | |
683 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
684 | I915_READ(VLV_DPFLIPSTAT)); | |
685 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
686 | I915_READ(DPINVGTT)); | |
687 | ||
688 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
689 | seq_printf(m, "Interrupt enable: %08x\n", |
690 | I915_READ(IER)); | |
691 | seq_printf(m, "Interrupt identity: %08x\n", | |
692 | I915_READ(IIR)); | |
693 | seq_printf(m, "Interrupt mask: %08x\n", | |
694 | I915_READ(IMR)); | |
9db4a9c7 JB |
695 | for_each_pipe(pipe) |
696 | seq_printf(m, "Pipe %c stat: %08x\n", | |
697 | pipe_name(pipe), | |
698 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
699 | } else { |
700 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
701 | I915_READ(DEIER)); | |
702 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
703 | I915_READ(DEIIR)); | |
704 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
705 | I915_READ(DEIMR)); | |
706 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
707 | I915_READ(SDEIER)); | |
708 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
709 | I915_READ(SDEIIR)); | |
710 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
711 | I915_READ(SDEIMR)); | |
712 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
713 | I915_READ(GTIER)); | |
714 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
715 | I915_READ(GTIIR)); | |
716 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
717 | I915_READ(GTIMR)); | |
718 | } | |
a2c7f6fd | 719 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 720 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
721 | seq_printf(m, |
722 | "Graphics Interrupt mask (%s): %08x\n", | |
723 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 724 | } |
a2c7f6fd | 725 | i915_ring_seqno_info(m, ring); |
9862e600 | 726 | } |
c8c8fb33 | 727 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
728 | mutex_unlock(&dev->struct_mutex); |
729 | ||
2017263e BG |
730 | return 0; |
731 | } | |
732 | ||
a6172a80 CW |
733 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
734 | { | |
735 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
736 | struct drm_device *dev = node->minor->dev; | |
737 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
738 | int i, ret; |
739 | ||
740 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
741 | if (ret) | |
742 | return ret; | |
a6172a80 CW |
743 | |
744 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
745 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
746 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 747 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 748 | |
6c085a72 CW |
749 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
750 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 751 | if (obj == NULL) |
267f0c90 | 752 | seq_puts(m, "unused"); |
c2c347a9 | 753 | else |
05394f39 | 754 | describe_obj(m, obj); |
267f0c90 | 755 | seq_putc(m, '\n'); |
a6172a80 CW |
756 | } |
757 | ||
05394f39 | 758 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
759 | return 0; |
760 | } | |
761 | ||
2017263e BG |
762 | static int i915_hws_info(struct seq_file *m, void *data) |
763 | { | |
764 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
765 | struct drm_device *dev = node->minor->dev; | |
766 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 767 | struct intel_ring_buffer *ring; |
1a240d4d | 768 | const u32 *hws; |
4066c0ae CW |
769 | int i; |
770 | ||
1ec14ad3 | 771 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 772 | hws = ring->status_page.page_addr; |
2017263e BG |
773 | if (hws == NULL) |
774 | return 0; | |
775 | ||
776 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
777 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
778 | i * 4, | |
779 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
780 | } | |
781 | return 0; | |
782 | } | |
783 | ||
d5442303 DV |
784 | static ssize_t |
785 | i915_error_state_write(struct file *filp, | |
786 | const char __user *ubuf, | |
787 | size_t cnt, | |
788 | loff_t *ppos) | |
789 | { | |
edc3d884 | 790 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 791 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 792 | int ret; |
d5442303 DV |
793 | |
794 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
795 | ||
22bcfc6a DV |
796 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
797 | if (ret) | |
798 | return ret; | |
799 | ||
d5442303 DV |
800 | i915_destroy_error_state(dev); |
801 | mutex_unlock(&dev->struct_mutex); | |
802 | ||
803 | return cnt; | |
804 | } | |
805 | ||
806 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
807 | { | |
808 | struct drm_device *dev = inode->i_private; | |
d5442303 | 809 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
810 | |
811 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
812 | if (!error_priv) | |
813 | return -ENOMEM; | |
814 | ||
815 | error_priv->dev = dev; | |
816 | ||
95d5bfb3 | 817 | i915_error_state_get(dev, error_priv); |
d5442303 | 818 | |
edc3d884 MK |
819 | file->private_data = error_priv; |
820 | ||
821 | return 0; | |
d5442303 DV |
822 | } |
823 | ||
824 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
825 | { | |
edc3d884 | 826 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 827 | |
95d5bfb3 | 828 | i915_error_state_put(error_priv); |
d5442303 DV |
829 | kfree(error_priv); |
830 | ||
edc3d884 MK |
831 | return 0; |
832 | } | |
833 | ||
4dc955f7 MK |
834 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
835 | size_t count, loff_t *pos) | |
836 | { | |
837 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
838 | struct drm_i915_error_state_buf error_str; | |
839 | loff_t tmp_pos = 0; | |
840 | ssize_t ret_count = 0; | |
841 | int ret; | |
842 | ||
843 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
844 | if (ret) | |
845 | return ret; | |
edc3d884 | 846 | |
fc16b48b | 847 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
848 | if (ret) |
849 | goto out; | |
850 | ||
edc3d884 MK |
851 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
852 | error_str.buf, | |
853 | error_str.bytes); | |
854 | ||
855 | if (ret_count < 0) | |
856 | ret = ret_count; | |
857 | else | |
858 | *pos = error_str.start + ret_count; | |
859 | out: | |
4dc955f7 | 860 | i915_error_state_buf_release(&error_str); |
edc3d884 | 861 | return ret ?: ret_count; |
d5442303 DV |
862 | } |
863 | ||
864 | static const struct file_operations i915_error_state_fops = { | |
865 | .owner = THIS_MODULE, | |
866 | .open = i915_error_state_open, | |
edc3d884 | 867 | .read = i915_error_state_read, |
d5442303 DV |
868 | .write = i915_error_state_write, |
869 | .llseek = default_llseek, | |
870 | .release = i915_error_state_release, | |
871 | }; | |
872 | ||
647416f9 KC |
873 | static int |
874 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 875 | { |
647416f9 | 876 | struct drm_device *dev = data; |
40633219 | 877 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
878 | int ret; |
879 | ||
880 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
881 | if (ret) | |
882 | return ret; | |
883 | ||
647416f9 | 884 | *val = dev_priv->next_seqno; |
40633219 MK |
885 | mutex_unlock(&dev->struct_mutex); |
886 | ||
647416f9 | 887 | return 0; |
40633219 MK |
888 | } |
889 | ||
647416f9 KC |
890 | static int |
891 | i915_next_seqno_set(void *data, u64 val) | |
892 | { | |
893 | struct drm_device *dev = data; | |
40633219 MK |
894 | int ret; |
895 | ||
40633219 MK |
896 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
897 | if (ret) | |
898 | return ret; | |
899 | ||
e94fbaa8 | 900 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
901 | mutex_unlock(&dev->struct_mutex); |
902 | ||
647416f9 | 903 | return ret; |
40633219 MK |
904 | } |
905 | ||
647416f9 KC |
906 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
907 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 908 | "0x%llx\n"); |
40633219 | 909 | |
f97108d1 JB |
910 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
911 | { | |
912 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
913 | struct drm_device *dev = node->minor->dev; | |
914 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
915 | u16 crstanddelay; |
916 | int ret; | |
917 | ||
918 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
919 | if (ret) | |
920 | return ret; | |
c8c8fb33 | 921 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
922 | |
923 | crstanddelay = I915_READ16(CRSTANDVID); | |
924 | ||
c8c8fb33 | 925 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 926 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
927 | |
928 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
934 | { | |
935 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
936 | struct drm_device *dev = node->minor->dev; | |
937 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c8c8fb33 PZ |
938 | int ret = 0; |
939 | ||
940 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 941 | |
5c9669ce TR |
942 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
943 | ||
3b8d8d91 JB |
944 | if (IS_GEN5(dev)) { |
945 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
946 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
947 | ||
948 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
949 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
950 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
951 | MEMSTAT_VID_SHIFT); | |
952 | seq_printf(m, "Current P-state: %d\n", | |
953 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 954 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
955 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
956 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
957 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 958 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
959 | u32 rpupei, rpcurup, rpprevup; |
960 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
961 | int max_freq; |
962 | ||
963 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
964 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
965 | if (ret) | |
c8c8fb33 | 966 | goto out; |
d1ebd816 | 967 | |
c8d9a590 | 968 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 969 | |
8e8c06cd CW |
970 | reqf = I915_READ(GEN6_RPNSWREQ); |
971 | reqf &= ~GEN6_TURBO_DISABLE; | |
972 | if (IS_HASWELL(dev)) | |
973 | reqf >>= 24; | |
974 | else | |
975 | reqf >>= 25; | |
976 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
977 | ||
ccab5c82 JB |
978 | rpstat = I915_READ(GEN6_RPSTAT1); |
979 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
980 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
981 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
982 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
983 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
984 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
985 | if (IS_HASWELL(dev)) |
986 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
987 | else | |
988 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
989 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 990 | |
c8d9a590 | 991 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
992 | mutex_unlock(&dev->struct_mutex); |
993 | ||
3b8d8d91 | 994 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 995 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
996 | seq_printf(m, "Render p-state ratio: %d\n", |
997 | (gt_perf_status & 0xff00) >> 8); | |
998 | seq_printf(m, "Render p-state VID: %d\n", | |
999 | gt_perf_status & 0xff); | |
1000 | seq_printf(m, "Render p-state limit: %d\n", | |
1001 | rp_state_limits & 0xff); | |
8e8c06cd | 1002 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1003 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1004 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1005 | GEN6_CURICONT_MASK); | |
1006 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1007 | GEN6_CURBSYTAVG_MASK); | |
1008 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1009 | GEN6_CURBSYTAVG_MASK); | |
1010 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1011 | GEN6_CURIAVG_MASK); | |
1012 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1013 | GEN6_CURBSYTAVG_MASK); | |
1014 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1015 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1016 | |
1017 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1018 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1019 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1020 | |
1021 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1022 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1023 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1024 | |
1025 | max_freq = rp_state_cap & 0xff; | |
1026 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1027 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1028 | |
1029 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
1030 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
1031 | } else if (IS_VALLEYVIEW(dev)) { |
1032 | u32 freq_sts, val; | |
1033 | ||
259bd5d4 | 1034 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1035 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1036 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1037 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1038 | ||
c5bd2bf6 | 1039 | val = valleyview_rps_max_freq(dev_priv); |
0a073b84 | 1040 | seq_printf(m, "max GPU freq: %d MHz\n", |
2ec3815f | 1041 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 | 1042 | |
c5bd2bf6 | 1043 | val = valleyview_rps_min_freq(dev_priv); |
0a073b84 | 1044 | seq_printf(m, "min GPU freq: %d MHz\n", |
2ec3815f | 1045 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
1046 | |
1047 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1048 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1049 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1050 | } else { |
267f0c90 | 1051 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1052 | } |
f97108d1 | 1053 | |
c8c8fb33 PZ |
1054 | out: |
1055 | intel_runtime_pm_put(dev_priv); | |
1056 | return ret; | |
f97108d1 JB |
1057 | } |
1058 | ||
1059 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1060 | { | |
1061 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1062 | struct drm_device *dev = node->minor->dev; | |
1063 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1064 | u32 delayfreq; | |
616fdb5a BW |
1065 | int ret, i; |
1066 | ||
1067 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1068 | if (ret) | |
1069 | return ret; | |
c8c8fb33 | 1070 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1071 | |
1072 | for (i = 0; i < 16; i++) { | |
1073 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1074 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1075 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1076 | } |
1077 | ||
c8c8fb33 PZ |
1078 | intel_runtime_pm_put(dev_priv); |
1079 | ||
616fdb5a BW |
1080 | mutex_unlock(&dev->struct_mutex); |
1081 | ||
f97108d1 JB |
1082 | return 0; |
1083 | } | |
1084 | ||
1085 | static inline int MAP_TO_MV(int map) | |
1086 | { | |
1087 | return 1250 - (map * 25); | |
1088 | } | |
1089 | ||
1090 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1091 | { | |
1092 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1093 | struct drm_device *dev = node->minor->dev; | |
1094 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1095 | u32 inttoext; | |
616fdb5a BW |
1096 | int ret, i; |
1097 | ||
1098 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1099 | if (ret) | |
1100 | return ret; | |
c8c8fb33 | 1101 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1102 | |
1103 | for (i = 1; i <= 32; i++) { | |
1104 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1105 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1106 | } | |
1107 | ||
c8c8fb33 | 1108 | intel_runtime_pm_put(dev_priv); |
616fdb5a BW |
1109 | mutex_unlock(&dev->struct_mutex); |
1110 | ||
f97108d1 JB |
1111 | return 0; |
1112 | } | |
1113 | ||
4d85529d | 1114 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1115 | { |
1116 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1117 | struct drm_device *dev = node->minor->dev; | |
1118 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1119 | u32 rgvmodectl, rstdbyctl; |
1120 | u16 crstandvid; | |
1121 | int ret; | |
1122 | ||
1123 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1124 | if (ret) | |
1125 | return ret; | |
c8c8fb33 | 1126 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1127 | |
1128 | rgvmodectl = I915_READ(MEMMODECTL); | |
1129 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1130 | crstandvid = I915_READ16(CRSTANDVID); | |
1131 | ||
c8c8fb33 | 1132 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1133 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1134 | |
1135 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1136 | "yes" : "no"); | |
1137 | seq_printf(m, "Boost freq: %d\n", | |
1138 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1139 | MEMMODE_BOOST_FREQ_SHIFT); | |
1140 | seq_printf(m, "HW control enabled: %s\n", | |
1141 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1142 | seq_printf(m, "SW control enabled: %s\n", | |
1143 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1144 | seq_printf(m, "Gated voltage change: %s\n", | |
1145 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1146 | seq_printf(m, "Starting frequency: P%d\n", | |
1147 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1148 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1149 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1150 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1151 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1152 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1153 | seq_printf(m, "Render standby enabled: %s\n", | |
1154 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1155 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1156 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1157 | case RSX_STATUS_ON: | |
267f0c90 | 1158 | seq_puts(m, "on\n"); |
88271da3 JB |
1159 | break; |
1160 | case RSX_STATUS_RC1: | |
267f0c90 | 1161 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1162 | break; |
1163 | case RSX_STATUS_RC1E: | |
267f0c90 | 1164 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1165 | break; |
1166 | case RSX_STATUS_RS1: | |
267f0c90 | 1167 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1168 | break; |
1169 | case RSX_STATUS_RS2: | |
267f0c90 | 1170 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1171 | break; |
1172 | case RSX_STATUS_RS3: | |
267f0c90 | 1173 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1174 | break; |
1175 | default: | |
267f0c90 | 1176 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1177 | break; |
1178 | } | |
f97108d1 JB |
1179 | |
1180 | return 0; | |
1181 | } | |
1182 | ||
669ab5aa D |
1183 | static int vlv_drpc_info(struct seq_file *m) |
1184 | { | |
1185 | ||
1186 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1187 | struct drm_device *dev = node->minor->dev; | |
1188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1189 | u32 rpmodectl1, rcctl1; | |
1190 | unsigned fw_rendercount = 0, fw_mediacount = 0; | |
1191 | ||
1192 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1193 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1194 | ||
1195 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1196 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1197 | seq_printf(m, "Turbo enabled: %s\n", | |
1198 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1199 | seq_printf(m, "HW control enabled: %s\n", | |
1200 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1201 | seq_printf(m, "SW control enabled: %s\n", | |
1202 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1203 | GEN6_RP_MEDIA_SW_MODE)); | |
1204 | seq_printf(m, "RC6 Enabled: %s\n", | |
1205 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1206 | GEN6_RC_CTL_EI_MODE(1)))); | |
1207 | seq_printf(m, "Render Power Well: %s\n", | |
1208 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1209 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1210 | seq_printf(m, "Media Power Well: %s\n", | |
1211 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1212 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1213 | ||
1214 | spin_lock_irq(&dev_priv->uncore.lock); | |
1215 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1216 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1217 | spin_unlock_irq(&dev_priv->uncore.lock); | |
1218 | ||
1219 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); | |
1220 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); | |
1221 | ||
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | ||
4d85529d BW |
1227 | static int gen6_drpc_info(struct seq_file *m) |
1228 | { | |
1229 | ||
1230 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1231 | struct drm_device *dev = node->minor->dev; | |
1232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1233 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1234 | unsigned forcewake_count; |
aee56cff | 1235 | int count = 0, ret; |
4d85529d BW |
1236 | |
1237 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1238 | if (ret) | |
1239 | return ret; | |
c8c8fb33 | 1240 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1241 | |
907b28c5 CW |
1242 | spin_lock_irq(&dev_priv->uncore.lock); |
1243 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1244 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1245 | |
1246 | if (forcewake_count) { | |
267f0c90 DL |
1247 | seq_puts(m, "RC information inaccurate because somebody " |
1248 | "holds a forcewake reference \n"); | |
4d85529d BW |
1249 | } else { |
1250 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1251 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1252 | udelay(10); | |
1253 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1254 | } | |
1255 | ||
1256 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1257 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1258 | |
1259 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1260 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1261 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1262 | mutex_lock(&dev_priv->rps.hw_lock); |
1263 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1264 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1265 | |
c8c8fb33 PZ |
1266 | intel_runtime_pm_put(dev_priv); |
1267 | ||
4d85529d BW |
1268 | seq_printf(m, "Video Turbo Mode: %s\n", |
1269 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1270 | seq_printf(m, "HW control enabled: %s\n", | |
1271 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1272 | seq_printf(m, "SW control enabled: %s\n", | |
1273 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1274 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1275 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1276 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1277 | seq_printf(m, "RC6 Enabled: %s\n", | |
1278 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1279 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1280 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1281 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1282 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1283 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1284 | switch (gt_core_status & GEN6_RCn_MASK) { |
1285 | case GEN6_RC0: | |
1286 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1287 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1288 | else |
267f0c90 | 1289 | seq_puts(m, "on\n"); |
4d85529d BW |
1290 | break; |
1291 | case GEN6_RC3: | |
267f0c90 | 1292 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1293 | break; |
1294 | case GEN6_RC6: | |
267f0c90 | 1295 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1296 | break; |
1297 | case GEN6_RC7: | |
267f0c90 | 1298 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1299 | break; |
1300 | default: | |
267f0c90 | 1301 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1302 | break; |
1303 | } | |
1304 | ||
1305 | seq_printf(m, "Core Power Down: %s\n", | |
1306 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1307 | |
1308 | /* Not exactly sure what this is */ | |
1309 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1310 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1311 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1312 | I915_READ(GEN6_GT_GFX_RC6)); | |
1313 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1314 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1315 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1316 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1317 | ||
ecd8faea BW |
1318 | seq_printf(m, "RC6 voltage: %dmV\n", |
1319 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1320 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1321 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1322 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1323 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1324 | return 0; |
1325 | } | |
1326 | ||
1327 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1328 | { | |
1329 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1330 | struct drm_device *dev = node->minor->dev; | |
1331 | ||
669ab5aa D |
1332 | if (IS_VALLEYVIEW(dev)) |
1333 | return vlv_drpc_info(m); | |
1334 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
4d85529d BW |
1335 | return gen6_drpc_info(m); |
1336 | else | |
1337 | return ironlake_drpc_info(m); | |
1338 | } | |
1339 | ||
b5e50c3f JB |
1340 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1341 | { | |
1342 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1343 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1344 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1345 | |
3a77c4c4 | 1346 | if (!HAS_FBC(dev)) { |
267f0c90 | 1347 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1348 | return 0; |
1349 | } | |
1350 | ||
ee5382ae | 1351 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1352 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1353 | } else { |
267f0c90 | 1354 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1355 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1356 | case FBC_OK: |
1357 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1358 | break; | |
1359 | case FBC_UNSUPPORTED: | |
1360 | seq_puts(m, "unsupported by this chipset"); | |
1361 | break; | |
bed4a673 | 1362 | case FBC_NO_OUTPUT: |
267f0c90 | 1363 | seq_puts(m, "no outputs"); |
bed4a673 | 1364 | break; |
b5e50c3f | 1365 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1366 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1367 | break; |
1368 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1369 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1370 | break; |
1371 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1372 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1373 | break; |
1374 | case FBC_BAD_PLANE: | |
267f0c90 | 1375 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1376 | break; |
1377 | case FBC_NOT_TILED: | |
267f0c90 | 1378 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1379 | break; |
9c928d16 | 1380 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1381 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1382 | break; |
c1a9f047 | 1383 | case FBC_MODULE_PARAM: |
267f0c90 | 1384 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1385 | break; |
8a5729a3 | 1386 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1387 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1388 | break; |
b5e50c3f | 1389 | default: |
267f0c90 | 1390 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1391 | } |
267f0c90 | 1392 | seq_putc(m, '\n'); |
b5e50c3f JB |
1393 | } |
1394 | return 0; | |
1395 | } | |
1396 | ||
92d44621 PZ |
1397 | static int i915_ips_status(struct seq_file *m, void *unused) |
1398 | { | |
1399 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1400 | struct drm_device *dev = node->minor->dev; | |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | ||
f5adf94e | 1403 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1404 | seq_puts(m, "not supported\n"); |
1405 | return 0; | |
1406 | } | |
1407 | ||
e59150dc | 1408 | if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE) |
92d44621 PZ |
1409 | seq_puts(m, "enabled\n"); |
1410 | else | |
1411 | seq_puts(m, "disabled\n"); | |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
4a9bef37 JB |
1416 | static int i915_sr_status(struct seq_file *m, void *unused) |
1417 | { | |
1418 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1419 | struct drm_device *dev = node->minor->dev; | |
1420 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1421 | bool sr_enabled = false; | |
1422 | ||
1398261a | 1423 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1424 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1425 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1426 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1427 | else if (IS_I915GM(dev)) | |
1428 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1429 | else if (IS_PINEVIEW(dev)) | |
1430 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1431 | ||
5ba2aaaa CW |
1432 | seq_printf(m, "self-refresh: %s\n", |
1433 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1434 | |
1435 | return 0; | |
1436 | } | |
1437 | ||
7648fa99 JB |
1438 | static int i915_emon_status(struct seq_file *m, void *unused) |
1439 | { | |
1440 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1441 | struct drm_device *dev = node->minor->dev; | |
1442 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1443 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1444 | int ret; |
1445 | ||
582be6b4 CW |
1446 | if (!IS_GEN5(dev)) |
1447 | return -ENODEV; | |
1448 | ||
de227ef0 CW |
1449 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1450 | if (ret) | |
1451 | return ret; | |
7648fa99 JB |
1452 | |
1453 | temp = i915_mch_val(dev_priv); | |
1454 | chipset = i915_chipset_val(dev_priv); | |
1455 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1456 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1457 | |
1458 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1459 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1460 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1461 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
23b2f8bb JB |
1466 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1467 | { | |
1468 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1469 | struct drm_device *dev = node->minor->dev; | |
1470 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1471 | int ret; | |
1472 | int gpu_freq, ia_freq; | |
1473 | ||
1c70c0ce | 1474 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1475 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1476 | return 0; |
1477 | } | |
1478 | ||
5c9669ce TR |
1479 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1480 | ||
4fc688ce | 1481 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1482 | if (ret) |
1483 | return ret; | |
c8c8fb33 | 1484 | intel_runtime_pm_get(dev_priv); |
23b2f8bb | 1485 | |
267f0c90 | 1486 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1487 | |
c6a828d3 DV |
1488 | for (gpu_freq = dev_priv->rps.min_delay; |
1489 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1490 | gpu_freq++) { |
42c0526c BW |
1491 | ia_freq = gpu_freq; |
1492 | sandybridge_pcode_read(dev_priv, | |
1493 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1494 | &ia_freq); | |
3ebecd07 CW |
1495 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1496 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1497 | ((ia_freq >> 0) & 0xff) * 100, | |
1498 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1499 | } |
1500 | ||
c8c8fb33 | 1501 | intel_runtime_pm_put(dev_priv); |
4fc688ce | 1502 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
7648fa99 JB |
1507 | static int i915_gfxec(struct seq_file *m, void *unused) |
1508 | { | |
1509 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1510 | struct drm_device *dev = node->minor->dev; | |
1511 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1512 | int ret; |
1513 | ||
1514 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1515 | if (ret) | |
1516 | return ret; | |
c8c8fb33 | 1517 | intel_runtime_pm_get(dev_priv); |
7648fa99 JB |
1518 | |
1519 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
c8c8fb33 | 1520 | intel_runtime_pm_put(dev_priv); |
7648fa99 | 1521 | |
616fdb5a BW |
1522 | mutex_unlock(&dev->struct_mutex); |
1523 | ||
7648fa99 JB |
1524 | return 0; |
1525 | } | |
1526 | ||
44834a67 CW |
1527 | static int i915_opregion(struct seq_file *m, void *unused) |
1528 | { | |
1529 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1530 | struct drm_device *dev = node->minor->dev; | |
1531 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1532 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1533 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1534 | int ret; |
1535 | ||
0d38f009 DV |
1536 | if (data == NULL) |
1537 | return -ENOMEM; | |
1538 | ||
44834a67 CW |
1539 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1540 | if (ret) | |
0d38f009 | 1541 | goto out; |
44834a67 | 1542 | |
0d38f009 DV |
1543 | if (opregion->header) { |
1544 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1545 | seq_write(m, data, OPREGION_SIZE); | |
1546 | } | |
44834a67 CW |
1547 | |
1548 | mutex_unlock(&dev->struct_mutex); | |
1549 | ||
0d38f009 DV |
1550 | out: |
1551 | kfree(data); | |
44834a67 CW |
1552 | return 0; |
1553 | } | |
1554 | ||
37811fcc CW |
1555 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1556 | { | |
1557 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1558 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1559 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1560 | struct intel_framebuffer *fb; |
37811fcc | 1561 | |
4520f53a DV |
1562 | #ifdef CONFIG_DRM_I915_FBDEV |
1563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1564 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1565 | if (ret) |
1566 | return ret; | |
1567 | ||
1568 | ifbdev = dev_priv->fbdev; | |
1569 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1570 | ||
623f9783 | 1571 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1572 | fb->base.width, |
1573 | fb->base.height, | |
1574 | fb->base.depth, | |
623f9783 DV |
1575 | fb->base.bits_per_pixel, |
1576 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1577 | describe_obj(m, fb->obj); |
267f0c90 | 1578 | seq_putc(m, '\n'); |
4b096ac1 | 1579 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1580 | #endif |
37811fcc | 1581 | |
4b096ac1 | 1582 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1583 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1584 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1585 | continue; |
1586 | ||
623f9783 | 1587 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1588 | fb->base.width, |
1589 | fb->base.height, | |
1590 | fb->base.depth, | |
623f9783 DV |
1591 | fb->base.bits_per_pixel, |
1592 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1593 | describe_obj(m, fb->obj); |
267f0c90 | 1594 | seq_putc(m, '\n'); |
37811fcc | 1595 | } |
4b096ac1 | 1596 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1597 | |
1598 | return 0; | |
1599 | } | |
1600 | ||
e76d3630 BW |
1601 | static int i915_context_status(struct seq_file *m, void *unused) |
1602 | { | |
1603 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1604 | struct drm_device *dev = node->minor->dev; | |
1605 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1606 | struct intel_ring_buffer *ring; |
a33afea5 | 1607 | struct i915_hw_context *ctx; |
a168c293 | 1608 | int ret, i; |
e76d3630 BW |
1609 | |
1610 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1611 | if (ret) | |
1612 | return ret; | |
1613 | ||
3e373948 | 1614 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1615 | seq_puts(m, "power context "); |
3e373948 | 1616 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1617 | seq_putc(m, '\n'); |
dc501fbc | 1618 | } |
e76d3630 | 1619 | |
3e373948 | 1620 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1621 | seq_puts(m, "render context "); |
3e373948 | 1622 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1623 | seq_putc(m, '\n'); |
dc501fbc | 1624 | } |
e76d3630 | 1625 | |
a33afea5 BW |
1626 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1627 | seq_puts(m, "HW context "); | |
3ccfd19d | 1628 | describe_ctx(m, ctx); |
a33afea5 BW |
1629 | for_each_ring(ring, dev_priv, i) |
1630 | if (ring->default_context == ctx) | |
1631 | seq_printf(m, "(default context %s) ", ring->name); | |
1632 | ||
1633 | describe_obj(m, ctx->obj); | |
1634 | seq_putc(m, '\n'); | |
a168c293 BW |
1635 | } |
1636 | ||
e76d3630 BW |
1637 | mutex_unlock(&dev->mode_config.mutex); |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
6d794d42 BW |
1642 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1643 | { | |
1644 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1645 | struct drm_device *dev = node->minor->dev; | |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1647 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1648 | |
907b28c5 | 1649 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1650 | if (IS_VALLEYVIEW(dev)) { |
1651 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1652 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1653 | } else | |
1654 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1655 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1656 | |
43709ba0 D |
1657 | if (IS_VALLEYVIEW(dev)) { |
1658 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1659 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1660 | } else | |
1661 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1662 | |
1663 | return 0; | |
1664 | } | |
1665 | ||
ea16a3cd DV |
1666 | static const char *swizzle_string(unsigned swizzle) |
1667 | { | |
aee56cff | 1668 | switch (swizzle) { |
ea16a3cd DV |
1669 | case I915_BIT_6_SWIZZLE_NONE: |
1670 | return "none"; | |
1671 | case I915_BIT_6_SWIZZLE_9: | |
1672 | return "bit9"; | |
1673 | case I915_BIT_6_SWIZZLE_9_10: | |
1674 | return "bit9/bit10"; | |
1675 | case I915_BIT_6_SWIZZLE_9_11: | |
1676 | return "bit9/bit11"; | |
1677 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1678 | return "bit9/bit10/bit11"; | |
1679 | case I915_BIT_6_SWIZZLE_9_17: | |
1680 | return "bit9/bit17"; | |
1681 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1682 | return "bit9/bit10/bit17"; | |
1683 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1684 | return "unknown"; |
ea16a3cd DV |
1685 | } |
1686 | ||
1687 | return "bug"; | |
1688 | } | |
1689 | ||
1690 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1691 | { | |
1692 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1693 | struct drm_device *dev = node->minor->dev; | |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1695 | int ret; |
1696 | ||
1697 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1698 | if (ret) | |
1699 | return ret; | |
c8c8fb33 | 1700 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1701 | |
ea16a3cd DV |
1702 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1703 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1704 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1705 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1706 | ||
1707 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1708 | seq_printf(m, "DDC = 0x%08x\n", | |
1709 | I915_READ(DCC)); | |
1710 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1711 | I915_READ16(C0DRB3)); | |
1712 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1713 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1714 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1715 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1716 | I915_READ(MAD_DIMM_C0)); | |
1717 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1718 | I915_READ(MAD_DIMM_C1)); | |
1719 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1720 | I915_READ(MAD_DIMM_C2)); | |
1721 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1722 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1723 | if (IS_GEN8(dev)) |
1724 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1725 | I915_READ(GAMTARBMODE)); | |
1726 | else | |
1727 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1728 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1729 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1730 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1731 | } |
c8c8fb33 | 1732 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1733 | mutex_unlock(&dev->struct_mutex); |
1734 | ||
1735 | return 0; | |
1736 | } | |
1737 | ||
1c60fef5 BW |
1738 | static int per_file_ctx(int id, void *ptr, void *data) |
1739 | { | |
1740 | struct i915_hw_context *ctx = ptr; | |
1741 | struct seq_file *m = data; | |
1742 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
1743 | ||
1744 | ppgtt->debug_dump(ppgtt, m); | |
1745 | ||
1746 | return 0; | |
1747 | } | |
1748 | ||
77df6772 | 1749 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1750 | { |
3cf17fc5 DV |
1751 | struct drm_i915_private *dev_priv = dev->dev_private; |
1752 | struct intel_ring_buffer *ring; | |
77df6772 BW |
1753 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1754 | int unused, i; | |
3cf17fc5 | 1755 | |
77df6772 BW |
1756 | if (!ppgtt) |
1757 | return; | |
1758 | ||
1759 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
1760 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages); | |
1761 | for_each_ring(ring, dev_priv, unused) { | |
1762 | seq_printf(m, "%s\n", ring->name); | |
1763 | for (i = 0; i < 4; i++) { | |
1764 | u32 offset = 0x270 + i * 8; | |
1765 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1766 | pdp <<= 32; | |
1767 | pdp |= I915_READ(ring->mmio_base + offset); | |
1768 | for (i = 0; i < 4; i++) | |
1769 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); | |
1770 | } | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1775 | { | |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1777 | struct intel_ring_buffer *ring; | |
1c60fef5 | 1778 | struct drm_file *file; |
77df6772 | 1779 | int i; |
3cf17fc5 | 1780 | |
3cf17fc5 DV |
1781 | if (INTEL_INFO(dev)->gen == 6) |
1782 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1783 | ||
a2c7f6fd | 1784 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1785 | seq_printf(m, "%s\n", ring->name); |
1786 | if (INTEL_INFO(dev)->gen == 7) | |
1787 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1788 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1789 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1790 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1791 | } | |
1792 | if (dev_priv->mm.aliasing_ppgtt) { | |
1793 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1794 | ||
267f0c90 | 1795 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 1796 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 1797 | |
87d60b63 | 1798 | ppgtt->debug_dump(ppgtt, m); |
1c60fef5 BW |
1799 | } else |
1800 | return; | |
1801 | ||
1802 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
1803 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1804 | struct i915_hw_ppgtt *pvt_ppgtt; | |
1805 | ||
1806 | pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx); | |
1807 | seq_printf(m, "proc: %s\n", | |
1808 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1809 | seq_puts(m, " default context:\n"); | |
1810 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); | |
3cf17fc5 DV |
1811 | } |
1812 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1813 | } |
1814 | ||
1815 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1816 | { | |
1817 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1818 | struct drm_device *dev = node->minor->dev; | |
c8c8fb33 | 1819 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1820 | |
1821 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1822 | if (ret) | |
1823 | return ret; | |
c8c8fb33 | 1824 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1825 | |
1826 | if (INTEL_INFO(dev)->gen >= 8) | |
1827 | gen8_ppgtt_info(m, dev); | |
1828 | else if (INTEL_INFO(dev)->gen >= 6) | |
1829 | gen6_ppgtt_info(m, dev); | |
1830 | ||
c8c8fb33 | 1831 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1832 | mutex_unlock(&dev->struct_mutex); |
1833 | ||
1834 | return 0; | |
1835 | } | |
1836 | ||
57f350b6 JB |
1837 | static int i915_dpio_info(struct seq_file *m, void *data) |
1838 | { | |
1839 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1840 | struct drm_device *dev = node->minor->dev; | |
1841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1842 | int ret; | |
1843 | ||
1844 | ||
1845 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1846 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1847 | return 0; |
1848 | } | |
1849 | ||
09153000 | 1850 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1851 | if (ret) |
1852 | return ret; | |
1853 | ||
1854 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1855 | ||
ab3c759a CML |
1856 | seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", |
1857 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); | |
1858 | seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", | |
1859 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); | |
1860 | ||
1861 | seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", | |
1862 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); | |
1863 | seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", | |
1864 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); | |
1865 | ||
1866 | seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", | |
1867 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); | |
1868 | seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", | |
1869 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); | |
1870 | ||
1871 | seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n", | |
1872 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0))); | |
1873 | seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n", | |
1874 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1))); | |
57f350b6 JB |
1875 | |
1876 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ab3c759a | 1877 | vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); |
57f350b6 | 1878 | |
09153000 | 1879 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1880 | |
1881 | return 0; | |
1882 | } | |
1883 | ||
63573eb7 BW |
1884 | static int i915_llc(struct seq_file *m, void *data) |
1885 | { | |
1886 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1887 | struct drm_device *dev = node->minor->dev; | |
1888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1889 | ||
1890 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1891 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1892 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1893 | ||
1894 | return 0; | |
1895 | } | |
1896 | ||
e91fd8c6 RV |
1897 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1898 | { | |
1899 | struct drm_info_node *node = m->private; | |
1900 | struct drm_device *dev = node->minor->dev; | |
1901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1902 | u32 psrperf = 0; |
1903 | bool enabled = false; | |
e91fd8c6 | 1904 | |
c8c8fb33 PZ |
1905 | intel_runtime_pm_get(dev_priv); |
1906 | ||
a031d709 RV |
1907 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1908 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1909 | |
a031d709 RV |
1910 | enabled = HAS_PSR(dev) && |
1911 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1912 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1913 | |
a031d709 RV |
1914 | if (HAS_PSR(dev)) |
1915 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1916 | EDP_PSR_PERF_CNT_MASK; | |
1917 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 | 1918 | |
c8c8fb33 | 1919 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1920 | return 0; |
1921 | } | |
1922 | ||
d2e216d0 RV |
1923 | static int i915_sink_crc(struct seq_file *m, void *data) |
1924 | { | |
1925 | struct drm_info_node *node = m->private; | |
1926 | struct drm_device *dev = node->minor->dev; | |
1927 | struct intel_encoder *encoder; | |
1928 | struct intel_connector *connector; | |
1929 | struct intel_dp *intel_dp = NULL; | |
1930 | int ret; | |
1931 | u8 crc[6]; | |
1932 | ||
1933 | drm_modeset_lock_all(dev); | |
1934 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
1935 | base.head) { | |
1936 | ||
1937 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
1938 | continue; | |
1939 | ||
1940 | encoder = to_intel_encoder(connector->base.encoder); | |
1941 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1942 | continue; | |
1943 | ||
1944 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1945 | ||
1946 | ret = intel_dp_sink_crc(intel_dp, crc); | |
1947 | if (ret) | |
1948 | goto out; | |
1949 | ||
1950 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
1951 | crc[0], crc[1], crc[2], | |
1952 | crc[3], crc[4], crc[5]); | |
1953 | goto out; | |
1954 | } | |
1955 | ret = -ENODEV; | |
1956 | out: | |
1957 | drm_modeset_unlock_all(dev); | |
1958 | return ret; | |
1959 | } | |
1960 | ||
ec013e7f JB |
1961 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1962 | { | |
1963 | struct drm_info_node *node = m->private; | |
1964 | struct drm_device *dev = node->minor->dev; | |
1965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1966 | u64 power; | |
1967 | u32 units; | |
1968 | ||
1969 | if (INTEL_INFO(dev)->gen < 6) | |
1970 | return -ENODEV; | |
1971 | ||
1972 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1973 | power = (power & 0x1f00) >> 8; | |
1974 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1975 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1976 | power *= units; | |
1977 | ||
1978 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1979 | |
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1984 | { | |
1985 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1986 | struct drm_device *dev = node->minor->dev; | |
1987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1988 | ||
1989 | if (!IS_HASWELL(dev)) { | |
1990 | seq_puts(m, "not supported\n"); | |
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | mutex_lock(&dev_priv->pc8.lock); | |
1995 | seq_printf(m, "Requirements met: %s\n", | |
1996 | yesno(dev_priv->pc8.requirements_met)); | |
1997 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1998 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1999 | seq_printf(m, "IRQs disabled: %s\n", | |
2000 | yesno(dev_priv->pc8.irqs_disabled)); | |
2001 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
2002 | mutex_unlock(&dev_priv->pc8.lock); | |
2003 | ||
ec013e7f JB |
2004 | return 0; |
2005 | } | |
2006 | ||
1da51581 ID |
2007 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2008 | { | |
2009 | switch (domain) { | |
2010 | case POWER_DOMAIN_PIPE_A: | |
2011 | return "PIPE_A"; | |
2012 | case POWER_DOMAIN_PIPE_B: | |
2013 | return "PIPE_B"; | |
2014 | case POWER_DOMAIN_PIPE_C: | |
2015 | return "PIPE_C"; | |
2016 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2017 | return "PIPE_A_PANEL_FITTER"; | |
2018 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2019 | return "PIPE_B_PANEL_FITTER"; | |
2020 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2021 | return "PIPE_C_PANEL_FITTER"; | |
2022 | case POWER_DOMAIN_TRANSCODER_A: | |
2023 | return "TRANSCODER_A"; | |
2024 | case POWER_DOMAIN_TRANSCODER_B: | |
2025 | return "TRANSCODER_B"; | |
2026 | case POWER_DOMAIN_TRANSCODER_C: | |
2027 | return "TRANSCODER_C"; | |
2028 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2029 | return "TRANSCODER_EDP"; | |
2030 | case POWER_DOMAIN_VGA: | |
2031 | return "VGA"; | |
2032 | case POWER_DOMAIN_AUDIO: | |
2033 | return "AUDIO"; | |
2034 | case POWER_DOMAIN_INIT: | |
2035 | return "INIT"; | |
2036 | default: | |
2037 | WARN_ON(1); | |
2038 | return "?"; | |
2039 | } | |
2040 | } | |
2041 | ||
2042 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2043 | { | |
2044 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2045 | struct drm_device *dev = node->minor->dev; | |
2046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2047 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2048 | int i; | |
2049 | ||
2050 | mutex_lock(&power_domains->lock); | |
2051 | ||
2052 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2053 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2054 | struct i915_power_well *power_well; | |
2055 | enum intel_display_power_domain power_domain; | |
2056 | ||
2057 | power_well = &power_domains->power_wells[i]; | |
2058 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2059 | power_well->count); | |
2060 | ||
2061 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2062 | power_domain++) { | |
2063 | if (!(BIT(power_domain) & power_well->domains)) | |
2064 | continue; | |
2065 | ||
2066 | seq_printf(m, " %-23s %d\n", | |
2067 | power_domain_str(power_domain), | |
2068 | power_domains->domain_use_count[power_domain]); | |
2069 | } | |
2070 | } | |
2071 | ||
2072 | mutex_unlock(&power_domains->lock); | |
2073 | ||
2074 | return 0; | |
2075 | } | |
2076 | ||
07144428 DL |
2077 | struct pipe_crc_info { |
2078 | const char *name; | |
2079 | struct drm_device *dev; | |
2080 | enum pipe pipe; | |
2081 | }; | |
2082 | ||
2083 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
2084 | { | |
be5c7a90 DL |
2085 | struct pipe_crc_info *info = inode->i_private; |
2086 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2087 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2088 | ||
7eb1c496 DV |
2089 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2090 | return -ENODEV; | |
2091 | ||
d538bbdf DL |
2092 | spin_lock_irq(&pipe_crc->lock); |
2093 | ||
2094 | if (pipe_crc->opened) { | |
2095 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2096 | return -EBUSY; /* already open */ |
2097 | } | |
2098 | ||
d538bbdf | 2099 | pipe_crc->opened = true; |
07144428 DL |
2100 | filep->private_data = inode->i_private; |
2101 | ||
d538bbdf DL |
2102 | spin_unlock_irq(&pipe_crc->lock); |
2103 | ||
07144428 DL |
2104 | return 0; |
2105 | } | |
2106 | ||
2107 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2108 | { | |
be5c7a90 DL |
2109 | struct pipe_crc_info *info = inode->i_private; |
2110 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2111 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2112 | ||
d538bbdf DL |
2113 | spin_lock_irq(&pipe_crc->lock); |
2114 | pipe_crc->opened = false; | |
2115 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2116 | |
07144428 DL |
2117 | return 0; |
2118 | } | |
2119 | ||
2120 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2121 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2122 | /* account for \'0' */ | |
2123 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2124 | ||
2125 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2126 | { |
d538bbdf DL |
2127 | assert_spin_locked(&pipe_crc->lock); |
2128 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2129 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2130 | } |
2131 | ||
2132 | static ssize_t | |
2133 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2134 | loff_t *pos) | |
2135 | { | |
2136 | struct pipe_crc_info *info = filep->private_data; | |
2137 | struct drm_device *dev = info->dev; | |
2138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2139 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2140 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2141 | int head, tail, n_entries, n; | |
2142 | ssize_t bytes_read; | |
2143 | ||
2144 | /* | |
2145 | * Don't allow user space to provide buffers not big enough to hold | |
2146 | * a line of data. | |
2147 | */ | |
2148 | if (count < PIPE_CRC_LINE_LEN) | |
2149 | return -EINVAL; | |
2150 | ||
2151 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2152 | return 0; |
07144428 DL |
2153 | |
2154 | /* nothing to read */ | |
d538bbdf | 2155 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2156 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2157 | int ret; |
2158 | ||
2159 | if (filep->f_flags & O_NONBLOCK) { | |
2160 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2161 | return -EAGAIN; |
d538bbdf | 2162 | } |
07144428 | 2163 | |
d538bbdf DL |
2164 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2165 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2166 | if (ret) { | |
2167 | spin_unlock_irq(&pipe_crc->lock); | |
2168 | return ret; | |
2169 | } | |
8bf1e9f1 SH |
2170 | } |
2171 | ||
07144428 | 2172 | /* We now have one or more entries to read */ |
d538bbdf DL |
2173 | head = pipe_crc->head; |
2174 | tail = pipe_crc->tail; | |
07144428 DL |
2175 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2176 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2177 | spin_unlock_irq(&pipe_crc->lock); |
2178 | ||
07144428 DL |
2179 | bytes_read = 0; |
2180 | n = 0; | |
2181 | do { | |
b2c88f5b | 2182 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2183 | int ret; |
8bf1e9f1 | 2184 | |
07144428 DL |
2185 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2186 | "%8u %8x %8x %8x %8x %8x\n", | |
2187 | entry->frame, entry->crc[0], | |
2188 | entry->crc[1], entry->crc[2], | |
2189 | entry->crc[3], entry->crc[4]); | |
2190 | ||
2191 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2192 | buf, PIPE_CRC_LINE_LEN); | |
2193 | if (ret == PIPE_CRC_LINE_LEN) | |
2194 | return -EFAULT; | |
b2c88f5b DL |
2195 | |
2196 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2197 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2198 | n++; |
2199 | } while (--n_entries); | |
8bf1e9f1 | 2200 | |
d538bbdf DL |
2201 | spin_lock_irq(&pipe_crc->lock); |
2202 | pipe_crc->tail = tail; | |
2203 | spin_unlock_irq(&pipe_crc->lock); | |
2204 | ||
07144428 DL |
2205 | return bytes_read; |
2206 | } | |
2207 | ||
2208 | static const struct file_operations i915_pipe_crc_fops = { | |
2209 | .owner = THIS_MODULE, | |
2210 | .open = i915_pipe_crc_open, | |
2211 | .read = i915_pipe_crc_read, | |
2212 | .release = i915_pipe_crc_release, | |
2213 | }; | |
2214 | ||
2215 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2216 | { | |
2217 | .name = "i915_pipe_A_crc", | |
2218 | .pipe = PIPE_A, | |
2219 | }, | |
2220 | { | |
2221 | .name = "i915_pipe_B_crc", | |
2222 | .pipe = PIPE_B, | |
2223 | }, | |
2224 | { | |
2225 | .name = "i915_pipe_C_crc", | |
2226 | .pipe = PIPE_C, | |
2227 | }, | |
2228 | }; | |
2229 | ||
2230 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2231 | enum pipe pipe) | |
2232 | { | |
2233 | struct drm_device *dev = minor->dev; | |
2234 | struct dentry *ent; | |
2235 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2236 | ||
2237 | info->dev = dev; | |
2238 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2239 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2240 | if (!ent) |
2241 | return -ENOMEM; | |
07144428 DL |
2242 | |
2243 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2244 | } |
2245 | ||
e8dfcf78 | 2246 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2247 | "none", |
2248 | "plane1", | |
2249 | "plane2", | |
2250 | "pf", | |
5b3a856b | 2251 | "pipe", |
3d099a05 DV |
2252 | "TV", |
2253 | "DP-B", | |
2254 | "DP-C", | |
2255 | "DP-D", | |
46a19188 | 2256 | "auto", |
926321d5 DV |
2257 | }; |
2258 | ||
2259 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2260 | { | |
2261 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2262 | return pipe_crc_sources[source]; | |
2263 | } | |
2264 | ||
bd9db02f | 2265 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2266 | { |
2267 | struct drm_device *dev = m->private; | |
2268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2269 | int i; | |
2270 | ||
2271 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2272 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2273 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2274 | ||
2275 | return 0; | |
2276 | } | |
2277 | ||
bd9db02f | 2278 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2279 | { |
2280 | struct drm_device *dev = inode->i_private; | |
2281 | ||
bd9db02f | 2282 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2283 | } |
2284 | ||
46a19188 | 2285 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2286 | uint32_t *val) |
2287 | { | |
46a19188 DV |
2288 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2289 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2290 | ||
2291 | switch (*source) { | |
52f843f6 DV |
2292 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2293 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2294 | break; | |
2295 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2296 | *val = 0; | |
2297 | break; | |
2298 | default: | |
2299 | return -EINVAL; | |
2300 | } | |
2301 | ||
2302 | return 0; | |
2303 | } | |
2304 | ||
46a19188 DV |
2305 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2306 | enum intel_pipe_crc_source *source) | |
2307 | { | |
2308 | struct intel_encoder *encoder; | |
2309 | struct intel_crtc *crtc; | |
26756809 | 2310 | struct intel_digital_port *dig_port; |
46a19188 DV |
2311 | int ret = 0; |
2312 | ||
2313 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2314 | ||
2315 | mutex_lock(&dev->mode_config.mutex); | |
2316 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
2317 | base.head) { | |
2318 | if (!encoder->base.crtc) | |
2319 | continue; | |
2320 | ||
2321 | crtc = to_intel_crtc(encoder->base.crtc); | |
2322 | ||
2323 | if (crtc->pipe != pipe) | |
2324 | continue; | |
2325 | ||
2326 | switch (encoder->type) { | |
2327 | case INTEL_OUTPUT_TVOUT: | |
2328 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2329 | break; | |
2330 | case INTEL_OUTPUT_DISPLAYPORT: | |
2331 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2332 | dig_port = enc_to_dig_port(&encoder->base); |
2333 | switch (dig_port->port) { | |
2334 | case PORT_B: | |
2335 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2336 | break; | |
2337 | case PORT_C: | |
2338 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2339 | break; | |
2340 | case PORT_D: | |
2341 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2342 | break; | |
2343 | default: | |
2344 | WARN(1, "nonexisting DP port %c\n", | |
2345 | port_name(dig_port->port)); | |
2346 | break; | |
2347 | } | |
46a19188 DV |
2348 | break; |
2349 | } | |
2350 | } | |
2351 | mutex_unlock(&dev->mode_config.mutex); | |
2352 | ||
2353 | return ret; | |
2354 | } | |
2355 | ||
2356 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2357 | enum pipe pipe, | |
2358 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2359 | uint32_t *val) |
2360 | { | |
8d2f24ca DV |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
2362 | bool need_stable_symbols = false; | |
2363 | ||
46a19188 DV |
2364 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2365 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2366 | if (ret) | |
2367 | return ret; | |
2368 | } | |
2369 | ||
2370 | switch (*source) { | |
7ac0129b DV |
2371 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2372 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2373 | break; | |
2374 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2375 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2376 | need_stable_symbols = true; |
7ac0129b DV |
2377 | break; |
2378 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2379 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2380 | need_stable_symbols = true; |
7ac0129b DV |
2381 | break; |
2382 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2383 | *val = 0; | |
2384 | break; | |
2385 | default: | |
2386 | return -EINVAL; | |
2387 | } | |
2388 | ||
8d2f24ca DV |
2389 | /* |
2390 | * When the pipe CRC tap point is after the transcoders we need | |
2391 | * to tweak symbol-level features to produce a deterministic series of | |
2392 | * symbols for a given frame. We need to reset those features only once | |
2393 | * a frame (instead of every nth symbol): | |
2394 | * - DC-balance: used to ensure a better clock recovery from the data | |
2395 | * link (SDVO) | |
2396 | * - DisplayPort scrambling: used for EMI reduction | |
2397 | */ | |
2398 | if (need_stable_symbols) { | |
2399 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2400 | ||
2401 | WARN_ON(!IS_G4X(dev)); | |
2402 | ||
2403 | tmp |= DC_BALANCE_RESET_VLV; | |
2404 | if (pipe == PIPE_A) | |
2405 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2406 | else | |
2407 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2408 | ||
2409 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2410 | } | |
2411 | ||
7ac0129b DV |
2412 | return 0; |
2413 | } | |
2414 | ||
4b79ebf7 | 2415 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2416 | enum pipe pipe, |
2417 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2418 | uint32_t *val) |
2419 | { | |
84093603 DV |
2420 | struct drm_i915_private *dev_priv = dev->dev_private; |
2421 | bool need_stable_symbols = false; | |
2422 | ||
46a19188 DV |
2423 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2424 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2425 | if (ret) | |
2426 | return ret; | |
2427 | } | |
2428 | ||
2429 | switch (*source) { | |
4b79ebf7 DV |
2430 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2431 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2432 | break; | |
2433 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2434 | if (!SUPPORTS_TV(dev)) | |
2435 | return -EINVAL; | |
2436 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2437 | break; | |
2438 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2439 | if (!IS_G4X(dev)) | |
2440 | return -EINVAL; | |
2441 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2442 | need_stable_symbols = true; |
4b79ebf7 DV |
2443 | break; |
2444 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2445 | if (!IS_G4X(dev)) | |
2446 | return -EINVAL; | |
2447 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2448 | need_stable_symbols = true; |
4b79ebf7 DV |
2449 | break; |
2450 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2451 | if (!IS_G4X(dev)) | |
2452 | return -EINVAL; | |
2453 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2454 | need_stable_symbols = true; |
4b79ebf7 DV |
2455 | break; |
2456 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2457 | *val = 0; | |
2458 | break; | |
2459 | default: | |
2460 | return -EINVAL; | |
2461 | } | |
2462 | ||
84093603 DV |
2463 | /* |
2464 | * When the pipe CRC tap point is after the transcoders we need | |
2465 | * to tweak symbol-level features to produce a deterministic series of | |
2466 | * symbols for a given frame. We need to reset those features only once | |
2467 | * a frame (instead of every nth symbol): | |
2468 | * - DC-balance: used to ensure a better clock recovery from the data | |
2469 | * link (SDVO) | |
2470 | * - DisplayPort scrambling: used for EMI reduction | |
2471 | */ | |
2472 | if (need_stable_symbols) { | |
2473 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2474 | ||
2475 | WARN_ON(!IS_G4X(dev)); | |
2476 | ||
2477 | I915_WRITE(PORT_DFT_I9XX, | |
2478 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2479 | ||
2480 | if (pipe == PIPE_A) | |
2481 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2482 | else | |
2483 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2484 | ||
2485 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2486 | } | |
2487 | ||
4b79ebf7 DV |
2488 | return 0; |
2489 | } | |
2490 | ||
8d2f24ca DV |
2491 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2492 | enum pipe pipe) | |
2493 | { | |
2494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2495 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2496 | ||
2497 | if (pipe == PIPE_A) | |
2498 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2499 | else | |
2500 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2501 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2502 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2503 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2504 | ||
2505 | } | |
2506 | ||
84093603 DV |
2507 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2508 | enum pipe pipe) | |
2509 | { | |
2510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2511 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2512 | ||
2513 | if (pipe == PIPE_A) | |
2514 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2515 | else | |
2516 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2517 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2518 | ||
2519 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2520 | I915_WRITE(PORT_DFT_I9XX, | |
2521 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2522 | } | |
2523 | } | |
2524 | ||
46a19188 | 2525 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2526 | uint32_t *val) |
2527 | { | |
46a19188 DV |
2528 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2529 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2530 | ||
2531 | switch (*source) { | |
5b3a856b DV |
2532 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2533 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2534 | break; | |
2535 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2536 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2537 | break; | |
5b3a856b DV |
2538 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2539 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2540 | break; | |
3d099a05 | 2541 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2542 | *val = 0; |
2543 | break; | |
3d099a05 DV |
2544 | default: |
2545 | return -EINVAL; | |
5b3a856b DV |
2546 | } |
2547 | ||
2548 | return 0; | |
2549 | } | |
2550 | ||
46a19188 | 2551 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2552 | uint32_t *val) |
2553 | { | |
46a19188 DV |
2554 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2555 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2556 | ||
2557 | switch (*source) { | |
5b3a856b DV |
2558 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2559 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2560 | break; | |
2561 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2562 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2563 | break; | |
2564 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2565 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2566 | break; | |
3d099a05 | 2567 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2568 | *val = 0; |
2569 | break; | |
3d099a05 DV |
2570 | default: |
2571 | return -EINVAL; | |
5b3a856b DV |
2572 | } |
2573 | ||
2574 | return 0; | |
2575 | } | |
2576 | ||
926321d5 DV |
2577 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2578 | enum intel_pipe_crc_source source) | |
2579 | { | |
2580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2581 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 2582 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 2583 | int ret; |
926321d5 | 2584 | |
cc3da175 DL |
2585 | if (pipe_crc->source == source) |
2586 | return 0; | |
2587 | ||
ae676fcd DL |
2588 | /* forbid changing the source without going back to 'none' */ |
2589 | if (pipe_crc->source && source) | |
2590 | return -EINVAL; | |
2591 | ||
52f843f6 | 2592 | if (IS_GEN2(dev)) |
46a19188 | 2593 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2594 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2595 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2596 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2597 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2598 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2599 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2600 | else |
46a19188 | 2601 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2602 | |
2603 | if (ret != 0) | |
2604 | return ret; | |
2605 | ||
4b584369 DL |
2606 | /* none -> real source transition */ |
2607 | if (source) { | |
7cd6ccff DL |
2608 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2609 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2610 | ||
e5f75aca DL |
2611 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2612 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2613 | GFP_KERNEL); | |
2614 | if (!pipe_crc->entries) | |
2615 | return -ENOMEM; | |
2616 | ||
d538bbdf DL |
2617 | spin_lock_irq(&pipe_crc->lock); |
2618 | pipe_crc->head = 0; | |
2619 | pipe_crc->tail = 0; | |
2620 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2621 | } |
2622 | ||
cc3da175 | 2623 | pipe_crc->source = source; |
926321d5 | 2624 | |
926321d5 DV |
2625 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2626 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2627 | ||
e5f75aca DL |
2628 | /* real source -> none transition */ |
2629 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf DL |
2630 | struct intel_pipe_crc_entry *entries; |
2631 | ||
7cd6ccff DL |
2632 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2633 | pipe_name(pipe)); | |
2634 | ||
bcf17ab2 DV |
2635 | intel_wait_for_vblank(dev, pipe); |
2636 | ||
d538bbdf DL |
2637 | spin_lock_irq(&pipe_crc->lock); |
2638 | entries = pipe_crc->entries; | |
e5f75aca | 2639 | pipe_crc->entries = NULL; |
d538bbdf DL |
2640 | spin_unlock_irq(&pipe_crc->lock); |
2641 | ||
2642 | kfree(entries); | |
84093603 DV |
2643 | |
2644 | if (IS_G4X(dev)) | |
2645 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2646 | else if (IS_VALLEYVIEW(dev)) |
2647 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2648 | } |
2649 | ||
926321d5 DV |
2650 | return 0; |
2651 | } | |
2652 | ||
2653 | /* | |
2654 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2655 | * command: wsp* object wsp+ name wsp+ source wsp* |
2656 | * object: 'pipe' | |
2657 | * name: (A | B | C) | |
926321d5 DV |
2658 | * source: (none | plane1 | plane2 | pf) |
2659 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2660 | * | |
2661 | * eg.: | |
b94dec87 DL |
2662 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2663 | * "pipe A none" -> Stop CRC | |
926321d5 | 2664 | */ |
bd9db02f | 2665 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2666 | { |
2667 | int n_words = 0; | |
2668 | ||
2669 | while (*buf) { | |
2670 | char *end; | |
2671 | ||
2672 | /* skip leading white space */ | |
2673 | buf = skip_spaces(buf); | |
2674 | if (!*buf) | |
2675 | break; /* end of buffer */ | |
2676 | ||
2677 | /* find end of word */ | |
2678 | for (end = buf; *end && !isspace(*end); end++) | |
2679 | ; | |
2680 | ||
2681 | if (n_words == max_words) { | |
2682 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2683 | max_words); | |
2684 | return -EINVAL; /* ran out of words[] before bytes */ | |
2685 | } | |
2686 | ||
2687 | if (*end) | |
2688 | *end++ = '\0'; | |
2689 | words[n_words++] = buf; | |
2690 | buf = end; | |
2691 | } | |
2692 | ||
2693 | return n_words; | |
2694 | } | |
2695 | ||
b94dec87 DL |
2696 | enum intel_pipe_crc_object { |
2697 | PIPE_CRC_OBJECT_PIPE, | |
2698 | }; | |
2699 | ||
e8dfcf78 | 2700 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
2701 | "pipe", |
2702 | }; | |
2703 | ||
2704 | static int | |
bd9db02f | 2705 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
2706 | { |
2707 | int i; | |
2708 | ||
2709 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
2710 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 2711 | *o = i; |
b94dec87 DL |
2712 | return 0; |
2713 | } | |
2714 | ||
2715 | return -EINVAL; | |
2716 | } | |
2717 | ||
bd9db02f | 2718 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
2719 | { |
2720 | const char name = buf[0]; | |
2721 | ||
2722 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
2723 | return -EINVAL; | |
2724 | ||
2725 | *pipe = name - 'A'; | |
2726 | ||
2727 | return 0; | |
2728 | } | |
2729 | ||
2730 | static int | |
bd9db02f | 2731 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
2732 | { |
2733 | int i; | |
2734 | ||
2735 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
2736 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 2737 | *s = i; |
926321d5 DV |
2738 | return 0; |
2739 | } | |
2740 | ||
2741 | return -EINVAL; | |
2742 | } | |
2743 | ||
bd9db02f | 2744 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 2745 | { |
b94dec87 | 2746 | #define N_WORDS 3 |
926321d5 | 2747 | int n_words; |
b94dec87 | 2748 | char *words[N_WORDS]; |
926321d5 | 2749 | enum pipe pipe; |
b94dec87 | 2750 | enum intel_pipe_crc_object object; |
926321d5 DV |
2751 | enum intel_pipe_crc_source source; |
2752 | ||
bd9db02f | 2753 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
2754 | if (n_words != N_WORDS) { |
2755 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
2756 | N_WORDS); | |
2757 | return -EINVAL; | |
2758 | } | |
2759 | ||
bd9db02f | 2760 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 2761 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
2762 | return -EINVAL; |
2763 | } | |
2764 | ||
bd9db02f | 2765 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 2766 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
2767 | return -EINVAL; |
2768 | } | |
2769 | ||
bd9db02f | 2770 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 2771 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
2772 | return -EINVAL; |
2773 | } | |
2774 | ||
2775 | return pipe_crc_set_source(dev, pipe, source); | |
2776 | } | |
2777 | ||
bd9db02f DL |
2778 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
2779 | size_t len, loff_t *offp) | |
926321d5 DV |
2780 | { |
2781 | struct seq_file *m = file->private_data; | |
2782 | struct drm_device *dev = m->private; | |
2783 | char *tmpbuf; | |
2784 | int ret; | |
2785 | ||
2786 | if (len == 0) | |
2787 | return 0; | |
2788 | ||
2789 | if (len > PAGE_SIZE - 1) { | |
2790 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
2791 | PAGE_SIZE); | |
2792 | return -E2BIG; | |
2793 | } | |
2794 | ||
2795 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
2796 | if (!tmpbuf) | |
2797 | return -ENOMEM; | |
2798 | ||
2799 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
2800 | ret = -EFAULT; | |
2801 | goto out; | |
2802 | } | |
2803 | tmpbuf[len] = '\0'; | |
2804 | ||
bd9db02f | 2805 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
2806 | |
2807 | out: | |
2808 | kfree(tmpbuf); | |
2809 | if (ret < 0) | |
2810 | return ret; | |
2811 | ||
2812 | *offp += len; | |
2813 | return len; | |
2814 | } | |
2815 | ||
bd9db02f | 2816 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 2817 | .owner = THIS_MODULE, |
bd9db02f | 2818 | .open = display_crc_ctl_open, |
926321d5 DV |
2819 | .read = seq_read, |
2820 | .llseek = seq_lseek, | |
2821 | .release = single_release, | |
bd9db02f | 2822 | .write = display_crc_ctl_write |
926321d5 DV |
2823 | }; |
2824 | ||
369a1342 VS |
2825 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
2826 | { | |
2827 | struct drm_device *dev = m->private; | |
2828 | int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; | |
2829 | int level; | |
2830 | ||
2831 | drm_modeset_lock_all(dev); | |
2832 | ||
2833 | for (level = 0; level < num_levels; level++) { | |
2834 | unsigned int latency = wm[level]; | |
2835 | ||
2836 | /* WM1+ latency values in 0.5us units */ | |
2837 | if (level > 0) | |
2838 | latency *= 5; | |
2839 | ||
2840 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
2841 | level, wm[level], | |
2842 | latency / 10, latency % 10); | |
2843 | } | |
2844 | ||
2845 | drm_modeset_unlock_all(dev); | |
2846 | } | |
2847 | ||
2848 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
2849 | { | |
2850 | struct drm_device *dev = m->private; | |
2851 | ||
2852 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); | |
2853 | ||
2854 | return 0; | |
2855 | } | |
2856 | ||
2857 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
2858 | { | |
2859 | struct drm_device *dev = m->private; | |
2860 | ||
2861 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); | |
2862 | ||
2863 | return 0; | |
2864 | } | |
2865 | ||
2866 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
2867 | { | |
2868 | struct drm_device *dev = m->private; | |
2869 | ||
2870 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); | |
2871 | ||
2872 | return 0; | |
2873 | } | |
2874 | ||
2875 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
2876 | { | |
2877 | struct drm_device *dev = inode->i_private; | |
2878 | ||
2879 | if (!HAS_PCH_SPLIT(dev)) | |
2880 | return -ENODEV; | |
2881 | ||
2882 | return single_open(file, pri_wm_latency_show, dev); | |
2883 | } | |
2884 | ||
2885 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
2886 | { | |
2887 | struct drm_device *dev = inode->i_private; | |
2888 | ||
2889 | if (!HAS_PCH_SPLIT(dev)) | |
2890 | return -ENODEV; | |
2891 | ||
2892 | return single_open(file, spr_wm_latency_show, dev); | |
2893 | } | |
2894 | ||
2895 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
2896 | { | |
2897 | struct drm_device *dev = inode->i_private; | |
2898 | ||
2899 | if (!HAS_PCH_SPLIT(dev)) | |
2900 | return -ENODEV; | |
2901 | ||
2902 | return single_open(file, cur_wm_latency_show, dev); | |
2903 | } | |
2904 | ||
2905 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
2906 | size_t len, loff_t *offp, uint16_t wm[5]) | |
2907 | { | |
2908 | struct seq_file *m = file->private_data; | |
2909 | struct drm_device *dev = m->private; | |
2910 | uint16_t new[5] = { 0 }; | |
2911 | int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; | |
2912 | int level; | |
2913 | int ret; | |
2914 | char tmp[32]; | |
2915 | ||
2916 | if (len >= sizeof(tmp)) | |
2917 | return -EINVAL; | |
2918 | ||
2919 | if (copy_from_user(tmp, ubuf, len)) | |
2920 | return -EFAULT; | |
2921 | ||
2922 | tmp[len] = '\0'; | |
2923 | ||
2924 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); | |
2925 | if (ret != num_levels) | |
2926 | return -EINVAL; | |
2927 | ||
2928 | drm_modeset_lock_all(dev); | |
2929 | ||
2930 | for (level = 0; level < num_levels; level++) | |
2931 | wm[level] = new[level]; | |
2932 | ||
2933 | drm_modeset_unlock_all(dev); | |
2934 | ||
2935 | return len; | |
2936 | } | |
2937 | ||
2938 | ||
2939 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
2940 | size_t len, loff_t *offp) | |
2941 | { | |
2942 | struct seq_file *m = file->private_data; | |
2943 | struct drm_device *dev = m->private; | |
2944 | ||
2945 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); | |
2946 | } | |
2947 | ||
2948 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
2949 | size_t len, loff_t *offp) | |
2950 | { | |
2951 | struct seq_file *m = file->private_data; | |
2952 | struct drm_device *dev = m->private; | |
2953 | ||
2954 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); | |
2955 | } | |
2956 | ||
2957 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
2958 | size_t len, loff_t *offp) | |
2959 | { | |
2960 | struct seq_file *m = file->private_data; | |
2961 | struct drm_device *dev = m->private; | |
2962 | ||
2963 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); | |
2964 | } | |
2965 | ||
2966 | static const struct file_operations i915_pri_wm_latency_fops = { | |
2967 | .owner = THIS_MODULE, | |
2968 | .open = pri_wm_latency_open, | |
2969 | .read = seq_read, | |
2970 | .llseek = seq_lseek, | |
2971 | .release = single_release, | |
2972 | .write = pri_wm_latency_write | |
2973 | }; | |
2974 | ||
2975 | static const struct file_operations i915_spr_wm_latency_fops = { | |
2976 | .owner = THIS_MODULE, | |
2977 | .open = spr_wm_latency_open, | |
2978 | .read = seq_read, | |
2979 | .llseek = seq_lseek, | |
2980 | .release = single_release, | |
2981 | .write = spr_wm_latency_write | |
2982 | }; | |
2983 | ||
2984 | static const struct file_operations i915_cur_wm_latency_fops = { | |
2985 | .owner = THIS_MODULE, | |
2986 | .open = cur_wm_latency_open, | |
2987 | .read = seq_read, | |
2988 | .llseek = seq_lseek, | |
2989 | .release = single_release, | |
2990 | .write = cur_wm_latency_write | |
2991 | }; | |
2992 | ||
647416f9 KC |
2993 | static int |
2994 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 2995 | { |
647416f9 | 2996 | struct drm_device *dev = data; |
f3cd474b | 2997 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 2998 | |
647416f9 | 2999 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3000 | |
647416f9 | 3001 | return 0; |
f3cd474b CW |
3002 | } |
3003 | ||
647416f9 KC |
3004 | static int |
3005 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3006 | { |
647416f9 | 3007 | struct drm_device *dev = data; |
f3cd474b | 3008 | |
647416f9 | 3009 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 3010 | i915_handle_error(dev, val); |
f3cd474b | 3011 | |
647416f9 | 3012 | return 0; |
f3cd474b CW |
3013 | } |
3014 | ||
647416f9 KC |
3015 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3016 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3017 | "%llu\n"); |
f3cd474b | 3018 | |
647416f9 KC |
3019 | static int |
3020 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3021 | { |
647416f9 | 3022 | struct drm_device *dev = data; |
e5eb3d63 | 3023 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 3024 | |
647416f9 | 3025 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 3026 | |
647416f9 | 3027 | return 0; |
e5eb3d63 DV |
3028 | } |
3029 | ||
647416f9 KC |
3030 | static int |
3031 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 3032 | { |
647416f9 | 3033 | struct drm_device *dev = data; |
e5eb3d63 | 3034 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3035 | int ret; |
e5eb3d63 | 3036 | |
647416f9 | 3037 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 3038 | |
22bcfc6a DV |
3039 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3040 | if (ret) | |
3041 | return ret; | |
3042 | ||
99584db3 | 3043 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
3044 | mutex_unlock(&dev->struct_mutex); |
3045 | ||
647416f9 | 3046 | return 0; |
e5eb3d63 DV |
3047 | } |
3048 | ||
647416f9 KC |
3049 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
3050 | i915_ring_stop_get, i915_ring_stop_set, | |
3051 | "0x%08llx\n"); | |
d5442303 | 3052 | |
094f9a54 CW |
3053 | static int |
3054 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3055 | { | |
3056 | struct drm_device *dev = data; | |
3057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3058 | ||
3059 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3060 | return 0; | |
3061 | } | |
3062 | ||
3063 | static int | |
3064 | i915_ring_missed_irq_set(void *data, u64 val) | |
3065 | { | |
3066 | struct drm_device *dev = data; | |
3067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3068 | int ret; | |
3069 | ||
3070 | /* Lock against concurrent debugfs callers */ | |
3071 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3072 | if (ret) | |
3073 | return ret; | |
3074 | dev_priv->gpu_error.missed_irq_rings = val; | |
3075 | mutex_unlock(&dev->struct_mutex); | |
3076 | ||
3077 | return 0; | |
3078 | } | |
3079 | ||
3080 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3081 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3082 | "0x%08llx\n"); | |
3083 | ||
3084 | static int | |
3085 | i915_ring_test_irq_get(void *data, u64 *val) | |
3086 | { | |
3087 | struct drm_device *dev = data; | |
3088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3089 | ||
3090 | *val = dev_priv->gpu_error.test_irq_rings; | |
3091 | ||
3092 | return 0; | |
3093 | } | |
3094 | ||
3095 | static int | |
3096 | i915_ring_test_irq_set(void *data, u64 val) | |
3097 | { | |
3098 | struct drm_device *dev = data; | |
3099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3100 | int ret; | |
3101 | ||
3102 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
3103 | ||
3104 | /* Lock against concurrent debugfs callers */ | |
3105 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3106 | if (ret) | |
3107 | return ret; | |
3108 | ||
3109 | dev_priv->gpu_error.test_irq_rings = val; | |
3110 | mutex_unlock(&dev->struct_mutex); | |
3111 | ||
3112 | return 0; | |
3113 | } | |
3114 | ||
3115 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
3116 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
3117 | "0x%08llx\n"); | |
3118 | ||
dd624afd CW |
3119 | #define DROP_UNBOUND 0x1 |
3120 | #define DROP_BOUND 0x2 | |
3121 | #define DROP_RETIRE 0x4 | |
3122 | #define DROP_ACTIVE 0x8 | |
3123 | #define DROP_ALL (DROP_UNBOUND | \ | |
3124 | DROP_BOUND | \ | |
3125 | DROP_RETIRE | \ | |
3126 | DROP_ACTIVE) | |
647416f9 KC |
3127 | static int |
3128 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 3129 | { |
647416f9 | 3130 | *val = DROP_ALL; |
dd624afd | 3131 | |
647416f9 | 3132 | return 0; |
dd624afd CW |
3133 | } |
3134 | ||
647416f9 KC |
3135 | static int |
3136 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 3137 | { |
647416f9 | 3138 | struct drm_device *dev = data; |
dd624afd CW |
3139 | struct drm_i915_private *dev_priv = dev->dev_private; |
3140 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
3141 | struct i915_address_space *vm; |
3142 | struct i915_vma *vma, *x; | |
647416f9 | 3143 | int ret; |
dd624afd | 3144 | |
2f9fe5ff | 3145 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
3146 | |
3147 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
3148 | * on ioctls on -EAGAIN. */ | |
3149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3150 | if (ret) | |
3151 | return ret; | |
3152 | ||
3153 | if (val & DROP_ACTIVE) { | |
3154 | ret = i915_gpu_idle(dev); | |
3155 | if (ret) | |
3156 | goto unlock; | |
3157 | } | |
3158 | ||
3159 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
3160 | i915_gem_retire_requests(dev); | |
3161 | ||
3162 | if (val & DROP_BOUND) { | |
ca191b13 BW |
3163 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3164 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
3165 | mm_list) { | |
d7f46fc4 | 3166 | if (vma->pin_count) |
ca191b13 BW |
3167 | continue; |
3168 | ||
3169 | ret = i915_vma_unbind(vma); | |
3170 | if (ret) | |
3171 | goto unlock; | |
3172 | } | |
31a46c9c | 3173 | } |
dd624afd CW |
3174 | } |
3175 | ||
3176 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
3177 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
3178 | global_list) | |
dd624afd CW |
3179 | if (obj->pages_pin_count == 0) { |
3180 | ret = i915_gem_object_put_pages(obj); | |
3181 | if (ret) | |
3182 | goto unlock; | |
3183 | } | |
3184 | } | |
3185 | ||
3186 | unlock: | |
3187 | mutex_unlock(&dev->struct_mutex); | |
3188 | ||
647416f9 | 3189 | return ret; |
dd624afd CW |
3190 | } |
3191 | ||
647416f9 KC |
3192 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
3193 | i915_drop_caches_get, i915_drop_caches_set, | |
3194 | "0x%08llx\n"); | |
dd624afd | 3195 | |
647416f9 KC |
3196 | static int |
3197 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 3198 | { |
647416f9 | 3199 | struct drm_device *dev = data; |
358733e9 | 3200 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 3201 | int ret; |
004777cb DV |
3202 | |
3203 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3204 | return -ENODEV; | |
3205 | ||
5c9669ce TR |
3206 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3207 | ||
4fc688ce | 3208 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3209 | if (ret) |
3210 | return ret; | |
358733e9 | 3211 | |
0a073b84 | 3212 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 3213 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); |
0a073b84 JB |
3214 | else |
3215 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 3216 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3217 | |
647416f9 | 3218 | return 0; |
358733e9 JB |
3219 | } |
3220 | ||
647416f9 KC |
3221 | static int |
3222 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 3223 | { |
647416f9 | 3224 | struct drm_device *dev = data; |
358733e9 | 3225 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3226 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3227 | int ret; |
004777cb DV |
3228 | |
3229 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3230 | return -ENODEV; | |
358733e9 | 3231 | |
5c9669ce TR |
3232 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3233 | ||
647416f9 | 3234 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 3235 | |
4fc688ce | 3236 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3237 | if (ret) |
3238 | return ret; | |
3239 | ||
358733e9 JB |
3240 | /* |
3241 | * Turbo will still be enabled, but won't go above the set value. | |
3242 | */ | |
0a073b84 | 3243 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3244 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3245 | |
3246 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3247 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3248 | } else { |
3249 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3250 | |
3251 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3252 | hw_max = dev_priv->rps.hw_max; | |
3253 | hw_min = (rp_state_cap >> 16) & 0xff; | |
3254 | } | |
3255 | ||
3256 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) { | |
3257 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3258 | return -EINVAL; | |
0a073b84 JB |
3259 | } |
3260 | ||
dd0a1aa1 JM |
3261 | dev_priv->rps.max_delay = val; |
3262 | ||
3263 | if (IS_VALLEYVIEW(dev)) | |
3264 | valleyview_set_rps(dev, val); | |
3265 | else | |
3266 | gen6_set_rps(dev, val); | |
3267 | ||
4fc688ce | 3268 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3269 | |
647416f9 | 3270 | return 0; |
358733e9 JB |
3271 | } |
3272 | ||
647416f9 KC |
3273 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
3274 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 3275 | "%llu\n"); |
358733e9 | 3276 | |
647416f9 KC |
3277 | static int |
3278 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 3279 | { |
647416f9 | 3280 | struct drm_device *dev = data; |
1523c310 | 3281 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 3282 | int ret; |
004777cb DV |
3283 | |
3284 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3285 | return -ENODEV; | |
3286 | ||
5c9669ce TR |
3287 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3288 | ||
4fc688ce | 3289 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3290 | if (ret) |
3291 | return ret; | |
1523c310 | 3292 | |
0a073b84 | 3293 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 3294 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); |
0a073b84 JB |
3295 | else |
3296 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 3297 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3298 | |
647416f9 | 3299 | return 0; |
1523c310 JB |
3300 | } |
3301 | ||
647416f9 KC |
3302 | static int |
3303 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3304 | { |
647416f9 | 3305 | struct drm_device *dev = data; |
1523c310 | 3306 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3307 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3308 | int ret; |
004777cb DV |
3309 | |
3310 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3311 | return -ENODEV; | |
1523c310 | 3312 | |
5c9669ce TR |
3313 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3314 | ||
647416f9 | 3315 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3316 | |
4fc688ce | 3317 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3318 | if (ret) |
3319 | return ret; | |
3320 | ||
1523c310 JB |
3321 | /* |
3322 | * Turbo will still be enabled, but won't go below the set value. | |
3323 | */ | |
0a073b84 | 3324 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3325 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3326 | |
3327 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3328 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3329 | } else { |
3330 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3331 | |
3332 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3333 | hw_max = dev_priv->rps.hw_max; | |
3334 | hw_min = (rp_state_cap >> 16) & 0xff; | |
3335 | } | |
3336 | ||
3337 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) { | |
3338 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3339 | return -EINVAL; | |
0a073b84 | 3340 | } |
dd0a1aa1 JM |
3341 | |
3342 | dev_priv->rps.min_delay = val; | |
3343 | ||
3344 | if (IS_VALLEYVIEW(dev)) | |
3345 | valleyview_set_rps(dev, val); | |
3346 | else | |
3347 | gen6_set_rps(dev, val); | |
3348 | ||
4fc688ce | 3349 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3350 | |
647416f9 | 3351 | return 0; |
1523c310 JB |
3352 | } |
3353 | ||
647416f9 KC |
3354 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3355 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3356 | "%llu\n"); |
1523c310 | 3357 | |
647416f9 KC |
3358 | static int |
3359 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3360 | { |
647416f9 | 3361 | struct drm_device *dev = data; |
07b7ddd9 | 3362 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 3363 | u32 snpcr; |
647416f9 | 3364 | int ret; |
07b7ddd9 | 3365 | |
004777cb DV |
3366 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3367 | return -ENODEV; | |
3368 | ||
22bcfc6a DV |
3369 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3370 | if (ret) | |
3371 | return ret; | |
c8c8fb33 | 3372 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3373 | |
07b7ddd9 | 3374 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3375 | |
3376 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3377 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3378 | ||
647416f9 | 3379 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3380 | |
647416f9 | 3381 | return 0; |
07b7ddd9 JB |
3382 | } |
3383 | ||
647416f9 KC |
3384 | static int |
3385 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3386 | { |
647416f9 | 3387 | struct drm_device *dev = data; |
07b7ddd9 | 3388 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3389 | u32 snpcr; |
07b7ddd9 | 3390 | |
004777cb DV |
3391 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3392 | return -ENODEV; | |
3393 | ||
647416f9 | 3394 | if (val > 3) |
07b7ddd9 JB |
3395 | return -EINVAL; |
3396 | ||
c8c8fb33 | 3397 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3398 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3399 | |
3400 | /* Update the cache sharing policy here as well */ | |
3401 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3402 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3403 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3404 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3405 | ||
c8c8fb33 | 3406 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3407 | return 0; |
07b7ddd9 JB |
3408 | } |
3409 | ||
647416f9 KC |
3410 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3411 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3412 | "%llu\n"); | |
07b7ddd9 | 3413 | |
6d794d42 BW |
3414 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3415 | { | |
3416 | struct drm_device *dev = inode->i_private; | |
3417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3418 | |
075edca4 | 3419 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3420 | return 0; |
3421 | ||
c8c8fb33 | 3422 | intel_runtime_pm_get(dev_priv); |
c8d9a590 | 3423 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3424 | |
3425 | return 0; | |
3426 | } | |
3427 | ||
c43b5634 | 3428 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3429 | { |
3430 | struct drm_device *dev = inode->i_private; | |
3431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3432 | ||
075edca4 | 3433 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3434 | return 0; |
3435 | ||
c8d9a590 | 3436 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
c8c8fb33 | 3437 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
3438 | |
3439 | return 0; | |
3440 | } | |
3441 | ||
3442 | static const struct file_operations i915_forcewake_fops = { | |
3443 | .owner = THIS_MODULE, | |
3444 | .open = i915_forcewake_open, | |
3445 | .release = i915_forcewake_release, | |
3446 | }; | |
3447 | ||
3448 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3449 | { | |
3450 | struct drm_device *dev = minor->dev; | |
3451 | struct dentry *ent; | |
3452 | ||
3453 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3454 | S_IRUSR, |
6d794d42 BW |
3455 | root, dev, |
3456 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3457 | if (!ent) |
3458 | return -ENOMEM; | |
6d794d42 | 3459 | |
8eb57294 | 3460 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3461 | } |
3462 | ||
6a9c308d DV |
3463 | static int i915_debugfs_create(struct dentry *root, |
3464 | struct drm_minor *minor, | |
3465 | const char *name, | |
3466 | const struct file_operations *fops) | |
07b7ddd9 JB |
3467 | { |
3468 | struct drm_device *dev = minor->dev; | |
3469 | struct dentry *ent; | |
3470 | ||
6a9c308d | 3471 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3472 | S_IRUGO | S_IWUSR, |
3473 | root, dev, | |
6a9c308d | 3474 | fops); |
f3c5fe97 WY |
3475 | if (!ent) |
3476 | return -ENOMEM; | |
07b7ddd9 | 3477 | |
6a9c308d | 3478 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3479 | } |
3480 | ||
06c5bf8c | 3481 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3482 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3483 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3484 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3485 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3486 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3487 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3488 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3489 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3490 | {"i915_gem_request", i915_gem_request_info, 0}, |
3491 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3492 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3493 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3494 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3495 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3496 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3497 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
3498 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
3499 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
3500 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
3501 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3502 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3503 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3504 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3505 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3506 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3507 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3508 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3509 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3510 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3511 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3512 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3513 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3514 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 3515 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 3516 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3517 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 3518 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 3519 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3520 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3521 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
2017263e | 3522 | }; |
27c202ad | 3523 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3524 | |
06c5bf8c | 3525 | static const struct i915_debugfs_files { |
34b9674c DV |
3526 | const char *name; |
3527 | const struct file_operations *fops; | |
3528 | } i915_debugfs_files[] = { | |
3529 | {"i915_wedged", &i915_wedged_fops}, | |
3530 | {"i915_max_freq", &i915_max_freq_fops}, | |
3531 | {"i915_min_freq", &i915_min_freq_fops}, | |
3532 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3533 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3534 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3535 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3536 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3537 | {"i915_error_state", &i915_error_state_fops}, | |
3538 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3539 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
3540 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
3541 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
3542 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
34b9674c DV |
3543 | }; |
3544 | ||
07144428 DL |
3545 | void intel_display_crc_init(struct drm_device *dev) |
3546 | { | |
3547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 3548 | enum pipe pipe; |
07144428 | 3549 | |
b378360e DV |
3550 | for_each_pipe(pipe) { |
3551 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 3552 | |
d538bbdf DL |
3553 | pipe_crc->opened = false; |
3554 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3555 | init_waitqueue_head(&pipe_crc->wq); |
3556 | } | |
3557 | } | |
3558 | ||
27c202ad | 3559 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3560 | { |
34b9674c | 3561 | int ret, i; |
f3cd474b | 3562 | |
6d794d42 | 3563 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3564 | if (ret) |
3565 | return ret; | |
6a9c308d | 3566 | |
07144428 DL |
3567 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3568 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3569 | if (ret) | |
3570 | return ret; | |
3571 | } | |
3572 | ||
34b9674c DV |
3573 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3574 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3575 | i915_debugfs_files[i].name, | |
3576 | i915_debugfs_files[i].fops); | |
3577 | if (ret) | |
3578 | return ret; | |
3579 | } | |
40633219 | 3580 | |
27c202ad BG |
3581 | return drm_debugfs_create_files(i915_debugfs_list, |
3582 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3583 | minor->debugfs_root, minor); |
3584 | } | |
3585 | ||
27c202ad | 3586 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3587 | { |
34b9674c DV |
3588 | int i; |
3589 | ||
27c202ad BG |
3590 | drm_debugfs_remove_files(i915_debugfs_list, |
3591 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3592 | |
6d794d42 BW |
3593 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3594 | 1, minor); | |
07144428 | 3595 | |
e309a997 | 3596 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3597 | struct drm_info_list *info_list = |
3598 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3599 | ||
3600 | drm_debugfs_remove_files(info_list, 1, minor); | |
3601 | } | |
3602 | ||
34b9674c DV |
3603 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3604 | struct drm_info_list *info_list = | |
3605 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3606 | ||
3607 | drm_debugfs_remove_files(info_list, 1, minor); | |
3608 | } | |
2017263e | 3609 | } |