]>
Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
f3cd474b | 29 | #include <linux/debugfs.h> |
e637d2cb | 30 | #include <linux/sort.h> |
d92a8cfc | 31 | #include <linux/sched/mm.h> |
4e5359cd | 32 | #include "intel_drv.h" |
9f436c46 | 33 | #include "i915_guc_submission.h" |
2017263e | 34 | |
36cdd013 DW |
35 | static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) |
36 | { | |
37 | return to_i915(node->minor->dev); | |
38 | } | |
39 | ||
418e3cd8 CW |
40 | static __always_inline void seq_print_param(struct seq_file *m, |
41 | const char *name, | |
42 | const char *type, | |
43 | const void *x) | |
44 | { | |
45 | if (!__builtin_strcmp(type, "bool")) | |
46 | seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); | |
47 | else if (!__builtin_strcmp(type, "int")) | |
48 | seq_printf(m, "i915.%s=%d\n", name, *(const int *)x); | |
49 | else if (!__builtin_strcmp(type, "unsigned int")) | |
50 | seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); | |
1d6aa7a3 CW |
51 | else if (!__builtin_strcmp(type, "char *")) |
52 | seq_printf(m, "i915.%s=%s\n", name, *(const char **)x); | |
418e3cd8 CW |
53 | else |
54 | BUILD_BUG(); | |
55 | } | |
56 | ||
70d39fe4 CW |
57 | static int i915_capabilities(struct seq_file *m, void *data) |
58 | { | |
36cdd013 DW |
59 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
60 | const struct intel_device_info *info = INTEL_INFO(dev_priv); | |
70d39fe4 | 61 | |
36cdd013 | 62 | seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); |
2e0d26f8 | 63 | seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); |
36cdd013 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); |
418e3cd8 | 65 | |
79fc46df | 66 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
604db650 | 67 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
79fc46df | 68 | #undef PRINT_FLAG |
70d39fe4 | 69 | |
418e3cd8 | 70 | kernel_param_lock(THIS_MODULE); |
7075cb85 | 71 | #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x); |
418e3cd8 CW |
72 | I915_PARAMS_FOR_EACH(PRINT_PARAM); |
73 | #undef PRINT_PARAM | |
74 | kernel_param_unlock(THIS_MODULE); | |
75 | ||
70d39fe4 CW |
76 | return 0; |
77 | } | |
2017263e | 78 | |
a7363de7 | 79 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 80 | { |
573adb39 | 81 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
82 | } |
83 | ||
a7363de7 | 84 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
85 | { |
86 | return obj->pin_display ? 'p' : ' '; | |
87 | } | |
88 | ||
a7363de7 | 89 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 90 | { |
3e510a8e | 91 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 92 | default: |
be12a86b TU |
93 | case I915_TILING_NONE: return ' '; |
94 | case I915_TILING_X: return 'X'; | |
95 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 96 | } |
a6172a80 CW |
97 | } |
98 | ||
a7363de7 | 99 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b | 100 | { |
a65adaf8 | 101 | return obj->userfault_count ? 'g' : ' '; |
be12a86b TU |
102 | } |
103 | ||
a7363de7 | 104 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 105 | { |
a4f5ea64 | 106 | return obj->mm.mapping ? 'M' : ' '; |
1d693bcc BW |
107 | } |
108 | ||
ca1543be TU |
109 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
110 | { | |
111 | u64 size = 0; | |
112 | struct i915_vma *vma; | |
113 | ||
1c7f4bca | 114 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 115 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
116 | size += vma->node.size; |
117 | } | |
118 | ||
119 | return size; | |
120 | } | |
121 | ||
7393b7ee MA |
122 | static const char * |
123 | stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) | |
124 | { | |
125 | size_t x = 0; | |
126 | ||
127 | switch (page_sizes) { | |
128 | case 0: | |
129 | return ""; | |
130 | case I915_GTT_PAGE_SIZE_4K: | |
131 | return "4K"; | |
132 | case I915_GTT_PAGE_SIZE_64K: | |
133 | return "64K"; | |
134 | case I915_GTT_PAGE_SIZE_2M: | |
135 | return "2M"; | |
136 | default: | |
137 | if (!buf) | |
138 | return "M"; | |
139 | ||
140 | if (page_sizes & I915_GTT_PAGE_SIZE_2M) | |
141 | x += snprintf(buf + x, len - x, "2M, "); | |
142 | if (page_sizes & I915_GTT_PAGE_SIZE_64K) | |
143 | x += snprintf(buf + x, len - x, "64K, "); | |
144 | if (page_sizes & I915_GTT_PAGE_SIZE_4K) | |
145 | x += snprintf(buf + x, len - x, "4K, "); | |
146 | buf[x-2] = '\0'; | |
147 | ||
148 | return buf; | |
149 | } | |
150 | } | |
151 | ||
37811fcc CW |
152 | static void |
153 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
154 | { | |
b4716185 | 155 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 156 | struct intel_engine_cs *engine; |
1d693bcc | 157 | struct i915_vma *vma; |
faf5bf0a | 158 | unsigned int frontbuffer_bits; |
d7f46fc4 BW |
159 | int pin_count = 0; |
160 | ||
188c1ab7 CW |
161 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
162 | ||
d07f0e59 | 163 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", |
37811fcc | 164 | &obj->base, |
be12a86b | 165 | get_active_flag(obj), |
37811fcc CW |
166 | get_pin_flag(obj), |
167 | get_tiling_flag(obj), | |
1d693bcc | 168 | get_global_flag(obj), |
be12a86b | 169 | get_pin_mapped_flag(obj), |
a05a5862 | 170 | obj->base.size / 1024, |
37811fcc | 171 | obj->base.read_domains, |
d07f0e59 | 172 | obj->base.write_domain, |
36cdd013 | 173 | i915_cache_level_str(dev_priv, obj->cache_level), |
a4f5ea64 CW |
174 | obj->mm.dirty ? " dirty" : "", |
175 | obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
37811fcc CW |
176 | if (obj->base.name) |
177 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 178 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 179 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 180 | pin_count++; |
ba0635ff DC |
181 | } |
182 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
183 | if (obj->pin_display) |
184 | seq_printf(m, " (display)"); | |
1c7f4bca | 185 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
186 | if (!drm_mm_node_allocated(&vma->node)) |
187 | continue; | |
188 | ||
7393b7ee | 189 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", |
3272db53 | 190 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
7393b7ee MA |
191 | vma->node.start, vma->node.size, |
192 | stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); | |
21976853 CW |
193 | if (i915_vma_is_ggtt(vma)) { |
194 | switch (vma->ggtt_view.type) { | |
195 | case I915_GGTT_VIEW_NORMAL: | |
196 | seq_puts(m, ", normal"); | |
197 | break; | |
198 | ||
199 | case I915_GGTT_VIEW_PARTIAL: | |
200 | seq_printf(m, ", partial [%08llx+%x]", | |
8bab1193 CW |
201 | vma->ggtt_view.partial.offset << PAGE_SHIFT, |
202 | vma->ggtt_view.partial.size << PAGE_SHIFT); | |
21976853 CW |
203 | break; |
204 | ||
205 | case I915_GGTT_VIEW_ROTATED: | |
206 | seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", | |
8bab1193 CW |
207 | vma->ggtt_view.rotated.plane[0].width, |
208 | vma->ggtt_view.rotated.plane[0].height, | |
209 | vma->ggtt_view.rotated.plane[0].stride, | |
210 | vma->ggtt_view.rotated.plane[0].offset, | |
211 | vma->ggtt_view.rotated.plane[1].width, | |
212 | vma->ggtt_view.rotated.plane[1].height, | |
213 | vma->ggtt_view.rotated.plane[1].stride, | |
214 | vma->ggtt_view.rotated.plane[1].offset); | |
21976853 CW |
215 | break; |
216 | ||
217 | default: | |
218 | MISSING_CASE(vma->ggtt_view.type); | |
219 | break; | |
220 | } | |
221 | } | |
49ef5294 CW |
222 | if (vma->fence) |
223 | seq_printf(m, " , fence: %d%s", | |
224 | vma->fence->id, | |
225 | i915_gem_active_isset(&vma->last_fence) ? "*" : ""); | |
596c5923 | 226 | seq_puts(m, ")"); |
1d693bcc | 227 | } |
c1ad11fc | 228 | if (obj->stolen) |
440fd528 | 229 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
27c01aae | 230 | |
d07f0e59 | 231 | engine = i915_gem_object_last_write_engine(obj); |
27c01aae CW |
232 | if (engine) |
233 | seq_printf(m, " (%s)", engine->name); | |
234 | ||
faf5bf0a CW |
235 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
236 | if (frontbuffer_bits) | |
237 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
238 | } |
239 | ||
e637d2cb | 240 | static int obj_rank_by_stolen(const void *A, const void *B) |
6d2b8885 | 241 | { |
e637d2cb CW |
242 | const struct drm_i915_gem_object *a = |
243 | *(const struct drm_i915_gem_object **)A; | |
244 | const struct drm_i915_gem_object *b = | |
245 | *(const struct drm_i915_gem_object **)B; | |
6d2b8885 | 246 | |
2d05fa16 RV |
247 | if (a->stolen->start < b->stolen->start) |
248 | return -1; | |
249 | if (a->stolen->start > b->stolen->start) | |
250 | return 1; | |
251 | return 0; | |
6d2b8885 CW |
252 | } |
253 | ||
254 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
255 | { | |
36cdd013 DW |
256 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
257 | struct drm_device *dev = &dev_priv->drm; | |
e637d2cb | 258 | struct drm_i915_gem_object **objects; |
6d2b8885 | 259 | struct drm_i915_gem_object *obj; |
c44ef60e | 260 | u64 total_obj_size, total_gtt_size; |
e637d2cb CW |
261 | unsigned long total, count, n; |
262 | int ret; | |
263 | ||
264 | total = READ_ONCE(dev_priv->mm.object_count); | |
2098105e | 265 | objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL); |
e637d2cb CW |
266 | if (!objects) |
267 | return -ENOMEM; | |
6d2b8885 CW |
268 | |
269 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
270 | if (ret) | |
e637d2cb | 271 | goto out; |
6d2b8885 CW |
272 | |
273 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 274 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
e637d2cb CW |
275 | if (count == total) |
276 | break; | |
277 | ||
6d2b8885 CW |
278 | if (obj->stolen == NULL) |
279 | continue; | |
280 | ||
e637d2cb | 281 | objects[count++] = obj; |
6d2b8885 | 282 | total_obj_size += obj->base.size; |
ca1543be | 283 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
e637d2cb | 284 | |
6d2b8885 | 285 | } |
56cea323 | 286 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
e637d2cb CW |
287 | if (count == total) |
288 | break; | |
289 | ||
6d2b8885 CW |
290 | if (obj->stolen == NULL) |
291 | continue; | |
292 | ||
e637d2cb | 293 | objects[count++] = obj; |
6d2b8885 | 294 | total_obj_size += obj->base.size; |
6d2b8885 | 295 | } |
e637d2cb CW |
296 | |
297 | sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL); | |
298 | ||
6d2b8885 | 299 | seq_puts(m, "Stolen:\n"); |
e637d2cb | 300 | for (n = 0; n < count; n++) { |
6d2b8885 | 301 | seq_puts(m, " "); |
e637d2cb | 302 | describe_obj(m, objects[n]); |
6d2b8885 | 303 | seq_putc(m, '\n'); |
6d2b8885 | 304 | } |
e637d2cb | 305 | seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n", |
6d2b8885 | 306 | count, total_obj_size, total_gtt_size); |
e637d2cb CW |
307 | |
308 | mutex_unlock(&dev->struct_mutex); | |
309 | out: | |
2098105e | 310 | kvfree(objects); |
e637d2cb | 311 | return ret; |
6d2b8885 CW |
312 | } |
313 | ||
2db8e9d6 | 314 | struct file_stats { |
6313c204 | 315 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
316 | unsigned long count; |
317 | u64 total, unbound; | |
318 | u64 global, shared; | |
319 | u64 active, inactive; | |
2db8e9d6 CW |
320 | }; |
321 | ||
322 | static int per_file_stats(int id, void *ptr, void *data) | |
323 | { | |
324 | struct drm_i915_gem_object *obj = ptr; | |
325 | struct file_stats *stats = data; | |
6313c204 | 326 | struct i915_vma *vma; |
2db8e9d6 | 327 | |
0caf81b5 CW |
328 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
329 | ||
2db8e9d6 CW |
330 | stats->count++; |
331 | stats->total += obj->base.size; | |
15717de2 CW |
332 | if (!obj->bind_count) |
333 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
334 | if (obj->base.name || obj->base.dma_buf) |
335 | stats->shared += obj->base.size; | |
336 | ||
894eeecc CW |
337 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
338 | if (!drm_mm_node_allocated(&vma->node)) | |
339 | continue; | |
6313c204 | 340 | |
3272db53 | 341 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
342 | stats->global += vma->node.size; |
343 | } else { | |
344 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 345 | |
2bfa996e | 346 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 347 | continue; |
6313c204 | 348 | } |
894eeecc | 349 | |
b0decaf7 | 350 | if (i915_vma_is_active(vma)) |
894eeecc CW |
351 | stats->active += vma->node.size; |
352 | else | |
353 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
354 | } |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
b0da1b79 CW |
359 | #define print_file_stats(m, name, stats) do { \ |
360 | if (stats.count) \ | |
c44ef60e | 361 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
362 | name, \ |
363 | stats.count, \ | |
364 | stats.total, \ | |
365 | stats.active, \ | |
366 | stats.inactive, \ | |
367 | stats.global, \ | |
368 | stats.shared, \ | |
369 | stats.unbound); \ | |
370 | } while (0) | |
493018dc BV |
371 | |
372 | static void print_batch_pool_stats(struct seq_file *m, | |
373 | struct drm_i915_private *dev_priv) | |
374 | { | |
375 | struct drm_i915_gem_object *obj; | |
376 | struct file_stats stats; | |
e2f80391 | 377 | struct intel_engine_cs *engine; |
3b3f1650 | 378 | enum intel_engine_id id; |
b4ac5afc | 379 | int j; |
493018dc BV |
380 | |
381 | memset(&stats, 0, sizeof(stats)); | |
382 | ||
3b3f1650 | 383 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 384 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 385 | list_for_each_entry(obj, |
e2f80391 | 386 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
387 | batch_pool_link) |
388 | per_file_stats(0, obj, &stats); | |
389 | } | |
06fbca71 | 390 | } |
493018dc | 391 | |
b0da1b79 | 392 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
393 | } |
394 | ||
15da9565 CW |
395 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
396 | { | |
397 | struct i915_gem_context *ctx = ptr; | |
398 | int n; | |
399 | ||
400 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
401 | if (ctx->engine[n].state) | |
bf3783e5 | 402 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 403 | if (ctx->engine[n].ring) |
57e88531 | 404 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
405 | } |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static void print_context_stats(struct seq_file *m, | |
411 | struct drm_i915_private *dev_priv) | |
412 | { | |
36cdd013 | 413 | struct drm_device *dev = &dev_priv->drm; |
15da9565 CW |
414 | struct file_stats stats; |
415 | struct drm_file *file; | |
416 | ||
417 | memset(&stats, 0, sizeof(stats)); | |
418 | ||
36cdd013 | 419 | mutex_lock(&dev->struct_mutex); |
15da9565 CW |
420 | if (dev_priv->kernel_context) |
421 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
422 | ||
36cdd013 | 423 | list_for_each_entry(file, &dev->filelist, lhead) { |
15da9565 CW |
424 | struct drm_i915_file_private *fpriv = file->driver_priv; |
425 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
426 | } | |
36cdd013 | 427 | mutex_unlock(&dev->struct_mutex); |
15da9565 CW |
428 | |
429 | print_file_stats(m, "[k]contexts", stats); | |
430 | } | |
431 | ||
36cdd013 | 432 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f | 433 | { |
36cdd013 DW |
434 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
435 | struct drm_device *dev = &dev_priv->drm; | |
72e96d64 | 436 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7393b7ee MA |
437 | u32 count, mapped_count, purgeable_count, dpy_count, huge_count; |
438 | u64 size, mapped_size, purgeable_size, dpy_size, huge_size; | |
6299f992 | 439 | struct drm_i915_gem_object *obj; |
7393b7ee | 440 | unsigned int page_sizes = 0; |
2db8e9d6 | 441 | struct drm_file *file; |
7393b7ee | 442 | char buf[80]; |
73aa808f CW |
443 | int ret; |
444 | ||
445 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
3ef7f228 | 449 | seq_printf(m, "%u objects, %llu bytes\n", |
6299f992 CW |
450 | dev_priv->mm.object_count, |
451 | dev_priv->mm.object_memory); | |
452 | ||
1544c42e CW |
453 | size = count = 0; |
454 | mapped_size = mapped_count = 0; | |
455 | purgeable_size = purgeable_count = 0; | |
7393b7ee | 456 | huge_size = huge_count = 0; |
56cea323 | 457 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { |
2bd160a1 CW |
458 | size += obj->base.size; |
459 | ++count; | |
460 | ||
a4f5ea64 | 461 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
2bd160a1 CW |
462 | purgeable_size += obj->base.size; |
463 | ++purgeable_count; | |
464 | } | |
465 | ||
a4f5ea64 | 466 | if (obj->mm.mapping) { |
2bd160a1 CW |
467 | mapped_count++; |
468 | mapped_size += obj->base.size; | |
be19b10d | 469 | } |
7393b7ee MA |
470 | |
471 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
472 | huge_count++; | |
473 | huge_size += obj->base.size; | |
474 | page_sizes |= obj->mm.page_sizes.sg; | |
475 | } | |
b7abb714 | 476 | } |
c44ef60e | 477 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 478 | |
2bd160a1 | 479 | size = count = dpy_size = dpy_count = 0; |
56cea323 | 480 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
2bd160a1 CW |
481 | size += obj->base.size; |
482 | ++count; | |
483 | ||
30154650 | 484 | if (obj->pin_display) { |
2bd160a1 CW |
485 | dpy_size += obj->base.size; |
486 | ++dpy_count; | |
6299f992 | 487 | } |
2bd160a1 | 488 | |
a4f5ea64 | 489 | if (obj->mm.madv == I915_MADV_DONTNEED) { |
b7abb714 CW |
490 | purgeable_size += obj->base.size; |
491 | ++purgeable_count; | |
492 | } | |
2bd160a1 | 493 | |
a4f5ea64 | 494 | if (obj->mm.mapping) { |
2bd160a1 CW |
495 | mapped_count++; |
496 | mapped_size += obj->base.size; | |
be19b10d | 497 | } |
7393b7ee MA |
498 | |
499 | if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { | |
500 | huge_count++; | |
501 | huge_size += obj->base.size; | |
502 | page_sizes |= obj->mm.page_sizes.sg; | |
503 | } | |
6299f992 | 504 | } |
2bd160a1 CW |
505 | seq_printf(m, "%u bound objects, %llu bytes\n", |
506 | count, size); | |
c44ef60e | 507 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 508 | purgeable_count, purgeable_size); |
2bd160a1 CW |
509 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
510 | mapped_count, mapped_size); | |
7393b7ee MA |
511 | seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n", |
512 | huge_count, | |
513 | stringify_page_sizes(page_sizes, buf, sizeof(buf)), | |
514 | huge_size); | |
2bd160a1 CW |
515 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", |
516 | dpy_count, dpy_size); | |
6299f992 | 517 | |
c44ef60e | 518 | seq_printf(m, "%llu [%llu] gtt total\n", |
381b943b | 519 | ggtt->base.total, ggtt->mappable_end); |
7393b7ee MA |
520 | seq_printf(m, "Supported page sizes: %s\n", |
521 | stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, | |
522 | buf, sizeof(buf))); | |
73aa808f | 523 | |
493018dc BV |
524 | seq_putc(m, '\n'); |
525 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
526 | mutex_unlock(&dev->struct_mutex); |
527 | ||
528 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 529 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
530 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
531 | struct file_stats stats; | |
c84455b4 CW |
532 | struct drm_i915_file_private *file_priv = file->driver_priv; |
533 | struct drm_i915_gem_request *request; | |
3ec2f427 | 534 | struct task_struct *task; |
2db8e9d6 | 535 | |
0caf81b5 CW |
536 | mutex_lock(&dev->struct_mutex); |
537 | ||
2db8e9d6 | 538 | memset(&stats, 0, sizeof(stats)); |
6313c204 | 539 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 540 | spin_lock(&file->table_lock); |
2db8e9d6 | 541 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 542 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
543 | /* |
544 | * Although we have a valid reference on file->pid, that does | |
545 | * not guarantee that the task_struct who called get_pid() is | |
546 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
547 | * Therefore, we need to protect this ->comm access using RCU. | |
548 | */ | |
c84455b4 CW |
549 | request = list_first_entry_or_null(&file_priv->mm.request_list, |
550 | struct drm_i915_gem_request, | |
c8659efa | 551 | client_link); |
3ec2f427 | 552 | rcu_read_lock(); |
c84455b4 CW |
553 | task = pid_task(request && request->ctx->pid ? |
554 | request->ctx->pid : file->pid, | |
555 | PIDTYPE_PID); | |
493018dc | 556 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 557 | rcu_read_unlock(); |
0caf81b5 | 558 | |
c84455b4 | 559 | mutex_unlock(&dev->struct_mutex); |
2db8e9d6 | 560 | } |
1d2ac403 | 561 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
562 | |
563 | return 0; | |
564 | } | |
565 | ||
aee56cff | 566 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 567 | { |
9f25d007 | 568 | struct drm_info_node *node = m->private; |
36cdd013 DW |
569 | struct drm_i915_private *dev_priv = node_to_i915(node); |
570 | struct drm_device *dev = &dev_priv->drm; | |
5f4b091a | 571 | bool show_pin_display_only = !!node->info_ent->data; |
08c18323 | 572 | struct drm_i915_gem_object *obj; |
c44ef60e | 573 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
574 | int count, ret; |
575 | ||
576 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
577 | if (ret) | |
578 | return ret; | |
579 | ||
580 | total_obj_size = total_gtt_size = count = 0; | |
56cea323 | 581 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { |
6da84829 | 582 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
583 | continue; |
584 | ||
267f0c90 | 585 | seq_puts(m, " "); |
08c18323 | 586 | describe_obj(m, obj); |
267f0c90 | 587 | seq_putc(m, '\n'); |
08c18323 | 588 | total_obj_size += obj->base.size; |
ca1543be | 589 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
590 | count++; |
591 | } | |
592 | ||
593 | mutex_unlock(&dev->struct_mutex); | |
594 | ||
c44ef60e | 595 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
596 | count, total_obj_size, total_gtt_size); |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
493018dc BV |
601 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
602 | { | |
36cdd013 DW |
603 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
604 | struct drm_device *dev = &dev_priv->drm; | |
493018dc | 605 | struct drm_i915_gem_object *obj; |
e2f80391 | 606 | struct intel_engine_cs *engine; |
3b3f1650 | 607 | enum intel_engine_id id; |
8d9d5744 | 608 | int total = 0; |
b4ac5afc | 609 | int ret, j; |
493018dc BV |
610 | |
611 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
612 | if (ret) | |
613 | return ret; | |
614 | ||
3b3f1650 | 615 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 616 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
617 | int count; |
618 | ||
619 | count = 0; | |
620 | list_for_each_entry(obj, | |
e2f80391 | 621 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
622 | batch_pool_link) |
623 | count++; | |
624 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 625 | engine->name, j, count); |
8d9d5744 CW |
626 | |
627 | list_for_each_entry(obj, | |
e2f80391 | 628 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
629 | batch_pool_link) { |
630 | seq_puts(m, " "); | |
631 | describe_obj(m, obj); | |
632 | seq_putc(m, '\n'); | |
633 | } | |
634 | ||
635 | total += count; | |
06fbca71 | 636 | } |
493018dc BV |
637 | } |
638 | ||
8d9d5744 | 639 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
640 | |
641 | mutex_unlock(&dev->struct_mutex); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
1b36595f CW |
646 | static void print_request(struct seq_file *m, |
647 | struct drm_i915_gem_request *rq, | |
648 | const char *prefix) | |
649 | { | |
20311bd3 | 650 | seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, |
65e4760e | 651 | rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, |
20311bd3 | 652 | rq->priotree.priority, |
1b36595f | 653 | jiffies_to_msecs(jiffies - rq->emitted_jiffies), |
562f5d45 | 654 | rq->timeline->common->name); |
1b36595f CW |
655 | } |
656 | ||
2017263e BG |
657 | static int i915_gem_request_info(struct seq_file *m, void *data) |
658 | { | |
36cdd013 DW |
659 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
660 | struct drm_device *dev = &dev_priv->drm; | |
eed29a5b | 661 | struct drm_i915_gem_request *req; |
3b3f1650 AG |
662 | struct intel_engine_cs *engine; |
663 | enum intel_engine_id id; | |
b4ac5afc | 664 | int ret, any; |
de227ef0 CW |
665 | |
666 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
667 | if (ret) | |
668 | return ret; | |
2017263e | 669 | |
2d1070b2 | 670 | any = 0; |
3b3f1650 | 671 | for_each_engine(engine, dev_priv, id) { |
2d1070b2 CW |
672 | int count; |
673 | ||
674 | count = 0; | |
73cb9701 | 675 | list_for_each_entry(req, &engine->timeline->requests, link) |
2d1070b2 CW |
676 | count++; |
677 | if (count == 0) | |
a2c7f6fd CW |
678 | continue; |
679 | ||
e2f80391 | 680 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
73cb9701 | 681 | list_for_each_entry(req, &engine->timeline->requests, link) |
1b36595f | 682 | print_request(m, req, " "); |
2d1070b2 CW |
683 | |
684 | any++; | |
2017263e | 685 | } |
de227ef0 CW |
686 | mutex_unlock(&dev->struct_mutex); |
687 | ||
2d1070b2 | 688 | if (any == 0) |
267f0c90 | 689 | seq_puts(m, "No requests\n"); |
c2c347a9 | 690 | |
2017263e BG |
691 | return 0; |
692 | } | |
693 | ||
b2223497 | 694 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 695 | struct intel_engine_cs *engine) |
b2223497 | 696 | { |
688e6c72 CW |
697 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
698 | struct rb_node *rb; | |
699 | ||
12471ba8 | 700 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 701 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 | 702 | |
61d3dc70 | 703 | spin_lock_irq(&b->rb_lock); |
688e6c72 | 704 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 705 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
688e6c72 CW |
706 | |
707 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
708 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
709 | } | |
61d3dc70 | 710 | spin_unlock_irq(&b->rb_lock); |
b2223497 CW |
711 | } |
712 | ||
2017263e BG |
713 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
714 | { | |
36cdd013 | 715 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 716 | struct intel_engine_cs *engine; |
3b3f1650 | 717 | enum intel_engine_id id; |
2017263e | 718 | |
3b3f1650 | 719 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 720 | i915_ring_seqno_info(m, engine); |
de227ef0 | 721 | |
2017263e BG |
722 | return 0; |
723 | } | |
724 | ||
725 | ||
726 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
727 | { | |
36cdd013 | 728 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 729 | struct intel_engine_cs *engine; |
3b3f1650 | 730 | enum intel_engine_id id; |
4bb05040 | 731 | int i, pipe; |
de227ef0 | 732 | |
c8c8fb33 | 733 | intel_runtime_pm_get(dev_priv); |
2017263e | 734 | |
36cdd013 | 735 | if (IS_CHERRYVIEW(dev_priv)) { |
74e1ca8c VS |
736 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
737 | I915_READ(GEN8_MASTER_IRQ)); | |
738 | ||
739 | seq_printf(m, "Display IER:\t%08x\n", | |
740 | I915_READ(VLV_IER)); | |
741 | seq_printf(m, "Display IIR:\t%08x\n", | |
742 | I915_READ(VLV_IIR)); | |
743 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
744 | I915_READ(VLV_IIR_RW)); | |
745 | seq_printf(m, "Display IMR:\t%08x\n", | |
746 | I915_READ(VLV_IMR)); | |
9c870d03 CW |
747 | for_each_pipe(dev_priv, pipe) { |
748 | enum intel_display_power_domain power_domain; | |
749 | ||
750 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
751 | if (!intel_display_power_get_if_enabled(dev_priv, | |
752 | power_domain)) { | |
753 | seq_printf(m, "Pipe %c power disabled\n", | |
754 | pipe_name(pipe)); | |
755 | continue; | |
756 | } | |
757 | ||
74e1ca8c VS |
758 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
759 | pipe_name(pipe), | |
760 | I915_READ(PIPESTAT(pipe))); | |
761 | ||
9c870d03 CW |
762 | intel_display_power_put(dev_priv, power_domain); |
763 | } | |
764 | ||
765 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
74e1ca8c VS |
766 | seq_printf(m, "Port hotplug:\t%08x\n", |
767 | I915_READ(PORT_HOTPLUG_EN)); | |
768 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
769 | I915_READ(VLV_DPFLIPSTAT)); | |
770 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
771 | I915_READ(DPINVGTT)); | |
9c870d03 | 772 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
74e1ca8c VS |
773 | |
774 | for (i = 0; i < 4; i++) { | |
775 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
776 | i, I915_READ(GEN8_GT_IMR(i))); | |
777 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
778 | i, I915_READ(GEN8_GT_IIR(i))); | |
779 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
780 | i, I915_READ(GEN8_GT_IER(i))); | |
781 | } | |
782 | ||
783 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
784 | I915_READ(GEN8_PCU_IMR)); | |
785 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
786 | I915_READ(GEN8_PCU_IIR)); | |
787 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
788 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 789 | } else if (INTEL_GEN(dev_priv) >= 8) { |
a123f157 BW |
790 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
791 | I915_READ(GEN8_MASTER_IRQ)); | |
792 | ||
793 | for (i = 0; i < 4; i++) { | |
794 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
795 | i, I915_READ(GEN8_GT_IMR(i))); | |
796 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
797 | i, I915_READ(GEN8_GT_IIR(i))); | |
798 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
799 | i, I915_READ(GEN8_GT_IER(i))); | |
800 | } | |
801 | ||
055e393f | 802 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
803 | enum intel_display_power_domain power_domain; |
804 | ||
805 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
806 | if (!intel_display_power_get_if_enabled(dev_priv, | |
807 | power_domain)) { | |
22c59960 PZ |
808 | seq_printf(m, "Pipe %c power disabled\n", |
809 | pipe_name(pipe)); | |
810 | continue; | |
811 | } | |
a123f157 | 812 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
813 | pipe_name(pipe), |
814 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 815 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
816 | pipe_name(pipe), |
817 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 818 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
819 | pipe_name(pipe), |
820 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
821 | |
822 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
823 | } |
824 | ||
825 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
826 | I915_READ(GEN8_DE_PORT_IMR)); | |
827 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
828 | I915_READ(GEN8_DE_PORT_IIR)); | |
829 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
830 | I915_READ(GEN8_DE_PORT_IER)); | |
831 | ||
832 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
833 | I915_READ(GEN8_DE_MISC_IMR)); | |
834 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
835 | I915_READ(GEN8_DE_MISC_IIR)); | |
836 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
837 | I915_READ(GEN8_DE_MISC_IER)); | |
838 | ||
839 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
840 | I915_READ(GEN8_PCU_IMR)); | |
841 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
842 | I915_READ(GEN8_PCU_IIR)); | |
843 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
844 | I915_READ(GEN8_PCU_IER)); | |
36cdd013 | 845 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
846 | seq_printf(m, "Display IER:\t%08x\n", |
847 | I915_READ(VLV_IER)); | |
848 | seq_printf(m, "Display IIR:\t%08x\n", | |
849 | I915_READ(VLV_IIR)); | |
850 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
851 | I915_READ(VLV_IIR_RW)); | |
852 | seq_printf(m, "Display IMR:\t%08x\n", | |
853 | I915_READ(VLV_IMR)); | |
4f4631af CW |
854 | for_each_pipe(dev_priv, pipe) { |
855 | enum intel_display_power_domain power_domain; | |
856 | ||
857 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
858 | if (!intel_display_power_get_if_enabled(dev_priv, | |
859 | power_domain)) { | |
860 | seq_printf(m, "Pipe %c power disabled\n", | |
861 | pipe_name(pipe)); | |
862 | continue; | |
863 | } | |
864 | ||
7e231dbe JB |
865 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
866 | pipe_name(pipe), | |
867 | I915_READ(PIPESTAT(pipe))); | |
4f4631af CW |
868 | intel_display_power_put(dev_priv, power_domain); |
869 | } | |
7e231dbe JB |
870 | |
871 | seq_printf(m, "Master IER:\t%08x\n", | |
872 | I915_READ(VLV_MASTER_IER)); | |
873 | ||
874 | seq_printf(m, "Render IER:\t%08x\n", | |
875 | I915_READ(GTIER)); | |
876 | seq_printf(m, "Render IIR:\t%08x\n", | |
877 | I915_READ(GTIIR)); | |
878 | seq_printf(m, "Render IMR:\t%08x\n", | |
879 | I915_READ(GTIMR)); | |
880 | ||
881 | seq_printf(m, "PM IER:\t\t%08x\n", | |
882 | I915_READ(GEN6_PMIER)); | |
883 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
884 | I915_READ(GEN6_PMIIR)); | |
885 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
886 | I915_READ(GEN6_PMIMR)); | |
887 | ||
888 | seq_printf(m, "Port hotplug:\t%08x\n", | |
889 | I915_READ(PORT_HOTPLUG_EN)); | |
890 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
891 | I915_READ(VLV_DPFLIPSTAT)); | |
892 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
893 | I915_READ(DPINVGTT)); | |
894 | ||
36cdd013 | 895 | } else if (!HAS_PCH_SPLIT(dev_priv)) { |
5f6a1695 ZW |
896 | seq_printf(m, "Interrupt enable: %08x\n", |
897 | I915_READ(IER)); | |
898 | seq_printf(m, "Interrupt identity: %08x\n", | |
899 | I915_READ(IIR)); | |
900 | seq_printf(m, "Interrupt mask: %08x\n", | |
901 | I915_READ(IMR)); | |
055e393f | 902 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
903 | seq_printf(m, "Pipe %c stat: %08x\n", |
904 | pipe_name(pipe), | |
905 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
906 | } else { |
907 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
908 | I915_READ(DEIER)); | |
909 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
910 | I915_READ(DEIIR)); | |
911 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
912 | I915_READ(DEIMR)); | |
913 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
914 | I915_READ(SDEIER)); | |
915 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
916 | I915_READ(SDEIIR)); | |
917 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
918 | I915_READ(SDEIMR)); | |
919 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
920 | I915_READ(GTIER)); | |
921 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
922 | I915_READ(GTIIR)); | |
923 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
924 | I915_READ(GTIMR)); | |
925 | } | |
3b3f1650 | 926 | for_each_engine(engine, dev_priv, id) { |
36cdd013 | 927 | if (INTEL_GEN(dev_priv) >= 6) { |
a2c7f6fd CW |
928 | seq_printf(m, |
929 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 930 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 931 | } |
e2f80391 | 932 | i915_ring_seqno_info(m, engine); |
9862e600 | 933 | } |
c8c8fb33 | 934 | intel_runtime_pm_put(dev_priv); |
de227ef0 | 935 | |
2017263e BG |
936 | return 0; |
937 | } | |
938 | ||
a6172a80 CW |
939 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
940 | { | |
36cdd013 DW |
941 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
942 | struct drm_device *dev = &dev_priv->drm; | |
de227ef0 CW |
943 | int i, ret; |
944 | ||
945 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
946 | if (ret) | |
947 | return ret; | |
a6172a80 | 948 | |
a6172a80 CW |
949 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
950 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
49ef5294 | 951 | struct i915_vma *vma = dev_priv->fence_regs[i].vma; |
a6172a80 | 952 | |
6c085a72 CW |
953 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
954 | i, dev_priv->fence_regs[i].pin_count); | |
49ef5294 | 955 | if (!vma) |
267f0c90 | 956 | seq_puts(m, "unused"); |
c2c347a9 | 957 | else |
49ef5294 | 958 | describe_obj(m, vma->obj); |
267f0c90 | 959 | seq_putc(m, '\n'); |
a6172a80 CW |
960 | } |
961 | ||
05394f39 | 962 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
963 | return 0; |
964 | } | |
965 | ||
98a2f411 | 966 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
5a4c6f1b CW |
967 | static ssize_t gpu_state_read(struct file *file, char __user *ubuf, |
968 | size_t count, loff_t *pos) | |
d5442303 | 969 | { |
5a4c6f1b CW |
970 | struct i915_gpu_state *error = file->private_data; |
971 | struct drm_i915_error_state_buf str; | |
972 | ssize_t ret; | |
973 | loff_t tmp; | |
d5442303 | 974 | |
5a4c6f1b CW |
975 | if (!error) |
976 | return 0; | |
d5442303 | 977 | |
5a4c6f1b CW |
978 | ret = i915_error_state_buf_init(&str, error->i915, count, *pos); |
979 | if (ret) | |
980 | return ret; | |
d5442303 | 981 | |
5a4c6f1b CW |
982 | ret = i915_error_state_to_str(&str, error); |
983 | if (ret) | |
984 | goto out; | |
d5442303 | 985 | |
5a4c6f1b CW |
986 | tmp = 0; |
987 | ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes); | |
988 | if (ret < 0) | |
989 | goto out; | |
d5442303 | 990 | |
5a4c6f1b CW |
991 | *pos = str.start + ret; |
992 | out: | |
993 | i915_error_state_buf_release(&str); | |
994 | return ret; | |
995 | } | |
edc3d884 | 996 | |
5a4c6f1b CW |
997 | static int gpu_state_release(struct inode *inode, struct file *file) |
998 | { | |
999 | i915_gpu_state_put(file->private_data); | |
edc3d884 | 1000 | return 0; |
d5442303 DV |
1001 | } |
1002 | ||
5a4c6f1b | 1003 | static int i915_gpu_info_open(struct inode *inode, struct file *file) |
d5442303 | 1004 | { |
090e5fe3 | 1005 | struct drm_i915_private *i915 = inode->i_private; |
5a4c6f1b | 1006 | struct i915_gpu_state *gpu; |
d5442303 | 1007 | |
090e5fe3 CW |
1008 | intel_runtime_pm_get(i915); |
1009 | gpu = i915_capture_gpu_state(i915); | |
1010 | intel_runtime_pm_put(i915); | |
5a4c6f1b CW |
1011 | if (!gpu) |
1012 | return -ENOMEM; | |
d5442303 | 1013 | |
5a4c6f1b | 1014 | file->private_data = gpu; |
edc3d884 MK |
1015 | return 0; |
1016 | } | |
1017 | ||
5a4c6f1b CW |
1018 | static const struct file_operations i915_gpu_info_fops = { |
1019 | .owner = THIS_MODULE, | |
1020 | .open = i915_gpu_info_open, | |
1021 | .read = gpu_state_read, | |
1022 | .llseek = default_llseek, | |
1023 | .release = gpu_state_release, | |
1024 | }; | |
1025 | ||
1026 | static ssize_t | |
1027 | i915_error_state_write(struct file *filp, | |
1028 | const char __user *ubuf, | |
1029 | size_t cnt, | |
1030 | loff_t *ppos) | |
4dc955f7 | 1031 | { |
5a4c6f1b | 1032 | struct i915_gpu_state *error = filp->private_data; |
4dc955f7 | 1033 | |
5a4c6f1b CW |
1034 | if (!error) |
1035 | return 0; | |
edc3d884 | 1036 | |
5a4c6f1b CW |
1037 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
1038 | i915_reset_error_state(error->i915); | |
edc3d884 | 1039 | |
5a4c6f1b CW |
1040 | return cnt; |
1041 | } | |
edc3d884 | 1042 | |
5a4c6f1b CW |
1043 | static int i915_error_state_open(struct inode *inode, struct file *file) |
1044 | { | |
1045 | file->private_data = i915_first_error_state(inode->i_private); | |
1046 | return 0; | |
d5442303 DV |
1047 | } |
1048 | ||
1049 | static const struct file_operations i915_error_state_fops = { | |
1050 | .owner = THIS_MODULE, | |
1051 | .open = i915_error_state_open, | |
5a4c6f1b | 1052 | .read = gpu_state_read, |
d5442303 DV |
1053 | .write = i915_error_state_write, |
1054 | .llseek = default_llseek, | |
5a4c6f1b | 1055 | .release = gpu_state_release, |
d5442303 | 1056 | }; |
98a2f411 CW |
1057 | #endif |
1058 | ||
647416f9 KC |
1059 | static int |
1060 | i915_next_seqno_set(void *data, u64 val) | |
1061 | { | |
36cdd013 DW |
1062 | struct drm_i915_private *dev_priv = data; |
1063 | struct drm_device *dev = &dev_priv->drm; | |
40633219 MK |
1064 | int ret; |
1065 | ||
40633219 MK |
1066 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1067 | if (ret) | |
1068 | return ret; | |
1069 | ||
73cb9701 | 1070 | ret = i915_gem_set_global_seqno(dev, val); |
40633219 MK |
1071 | mutex_unlock(&dev->struct_mutex); |
1072 | ||
647416f9 | 1073 | return ret; |
40633219 MK |
1074 | } |
1075 | ||
647416f9 | 1076 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
9b6586ae | 1077 | NULL, i915_next_seqno_set, |
3a3b4f98 | 1078 | "0x%llx\n"); |
40633219 | 1079 | |
adb4bd12 | 1080 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1081 | { |
36cdd013 | 1082 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
c8c8fb33 PZ |
1083 | int ret = 0; |
1084 | ||
1085 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1086 | |
36cdd013 | 1087 | if (IS_GEN5(dev_priv)) { |
3b8d8d91 JB |
1088 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
1089 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1090 | ||
1091 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1092 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1093 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1094 | MEMSTAT_VID_SHIFT); | |
1095 | seq_printf(m, "Current P-state: %d\n", | |
1096 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
36cdd013 | 1097 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
0d6fc92a | 1098 | u32 rpmodectl, freq_sts; |
666a4537 WB |
1099 | |
1100 | mutex_lock(&dev_priv->rps.hw_lock); | |
0d6fc92a SAK |
1101 | |
1102 | rpmodectl = I915_READ(GEN6_RP_CONTROL); | |
1103 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1104 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1105 | seq_printf(m, "HW control enabled: %s\n", | |
1106 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1107 | seq_printf(m, "SW control enabled: %s\n", | |
1108 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1109 | GEN6_RP_MEDIA_SW_MODE)); | |
1110 | ||
666a4537 WB |
1111 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
1112 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1113 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1114 | ||
1115 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1116 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1117 | ||
1118 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1119 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1120 | ||
1121 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1122 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1123 | ||
1124 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1125 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1126 | ||
1127 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1128 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1129 | ||
1130 | seq_printf(m, | |
1131 | "efficient (RPe) frequency: %d MHz\n", | |
1132 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1133 | mutex_unlock(&dev_priv->rps.hw_lock); | |
36cdd013 | 1134 | } else if (INTEL_GEN(dev_priv) >= 6) { |
35040562 BP |
1135 | u32 rp_state_limits; |
1136 | u32 gt_perf_status; | |
1137 | u32 rp_state_cap; | |
0d8f9491 | 1138 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1139 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1140 | u32 rpupei, rpcurup, rpprevup; |
1141 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1142 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1143 | int max_freq; |
1144 | ||
35040562 | 1145 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
cc3f90f0 | 1146 | if (IS_GEN9_LP(dev_priv)) { |
35040562 BP |
1147 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
1148 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1149 | } else { | |
1150 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1151 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1152 | } | |
1153 | ||
3b8d8d91 | 1154 | /* RPSTAT1 is in the GT power well */ |
59bad947 | 1155 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1156 | |
8e8c06cd | 1157 | reqf = I915_READ(GEN6_RPNSWREQ); |
35ceabf3 | 1158 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b AG |
1159 | reqf >>= 23; |
1160 | else { | |
1161 | reqf &= ~GEN6_TURBO_DISABLE; | |
36cdd013 | 1162 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60260a5b AG |
1163 | reqf >>= 24; |
1164 | else | |
1165 | reqf >>= 25; | |
1166 | } | |
7c59a9c1 | 1167 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1168 | |
0d8f9491 CW |
1169 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1170 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1171 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1172 | ||
ccab5c82 | 1173 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1174 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1175 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1176 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1177 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1178 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1179 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
35ceabf3 | 1180 | if (INTEL_GEN(dev_priv) >= 9) |
60260a5b | 1181 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
36cdd013 | 1182 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f82855d3 BW |
1183 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1184 | else | |
1185 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1186 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1187 | |
59bad947 | 1188 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 | 1189 | |
36cdd013 | 1190 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
9dd3c605 PZ |
1191 | pm_ier = I915_READ(GEN6_PMIER); |
1192 | pm_imr = I915_READ(GEN6_PMIMR); | |
1193 | pm_isr = I915_READ(GEN6_PMISR); | |
1194 | pm_iir = I915_READ(GEN6_PMIIR); | |
1195 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1196 | } else { | |
1197 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1198 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1199 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1200 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1201 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1202 | } | |
960e5465 SAK |
1203 | seq_printf(m, "Video Turbo Mode: %s\n", |
1204 | yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); | |
1205 | seq_printf(m, "HW control enabled: %s\n", | |
1206 | yesno(rpmodectl & GEN6_RP_ENABLE)); | |
1207 | seq_printf(m, "SW control enabled: %s\n", | |
1208 | yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == | |
1209 | GEN6_RP_MEDIA_SW_MODE)); | |
0d8f9491 | 1210 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1211 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
5dd04556 SAK |
1212 | seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", |
1213 | dev_priv->rps.pm_intrmsk_mbz); | |
3b8d8d91 | 1214 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1215 | seq_printf(m, "Render p-state ratio: %d\n", |
35ceabf3 | 1216 | (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1217 | seq_printf(m, "Render p-state VID: %d\n", |
1218 | gt_perf_status & 0xff); | |
1219 | seq_printf(m, "Render p-state limit: %d\n", | |
1220 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1221 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1222 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1223 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1224 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1225 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1226 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1227 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1228 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1229 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1230 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1231 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1232 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1233 | seq_printf(m, "Up threshold: %d%%\n", |
1234 | dev_priv->rps.up_threshold); | |
1235 | ||
d6cda9c7 AG |
1236 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1237 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1238 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1239 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1240 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1241 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1242 | seq_printf(m, "Down threshold: %d%%\n", |
1243 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1244 | |
cc3f90f0 | 1245 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : |
35040562 | 1246 | rp_state_cap >> 16) & 0xff; |
35ceabf3 RV |
1247 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1248 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1249 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1250 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1251 | |
1252 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
35ceabf3 RV |
1253 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1254 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1255 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1256 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1257 | |
cc3f90f0 | 1258 | max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : |
35040562 | 1259 | rp_state_cap >> 0) & 0xff; |
35ceabf3 RV |
1260 | max_freq *= (IS_GEN9_BC(dev_priv) || |
1261 | IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1262 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1263 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1264 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1265 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1266 | |
d86ed34a CW |
1267 | seq_printf(m, "Current freq: %d MHz\n", |
1268 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1269 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1270 | seq_printf(m, "Idle freq: %d MHz\n", |
1271 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1272 | seq_printf(m, "Min freq: %d MHz\n", |
1273 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1274 | seq_printf(m, "Boost freq: %d MHz\n", |
1275 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1276 | seq_printf(m, "Max freq: %d MHz\n", |
1277 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1278 | seq_printf(m, | |
1279 | "efficient (RPe) frequency: %d MHz\n", | |
1280 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1281 | } else { |
267f0c90 | 1282 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1283 | } |
f97108d1 | 1284 | |
49cd97a3 | 1285 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); |
1170f28c MK |
1286 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
1287 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1288 | ||
c8c8fb33 PZ |
1289 | intel_runtime_pm_put(dev_priv); |
1290 | return ret; | |
f97108d1 JB |
1291 | } |
1292 | ||
d636951e BW |
1293 | static void i915_instdone_info(struct drm_i915_private *dev_priv, |
1294 | struct seq_file *m, | |
1295 | struct intel_instdone *instdone) | |
1296 | { | |
f9e61372 BW |
1297 | int slice; |
1298 | int subslice; | |
1299 | ||
d636951e BW |
1300 | seq_printf(m, "\t\tINSTDONE: 0x%08x\n", |
1301 | instdone->instdone); | |
1302 | ||
1303 | if (INTEL_GEN(dev_priv) <= 3) | |
1304 | return; | |
1305 | ||
1306 | seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", | |
1307 | instdone->slice_common); | |
1308 | ||
1309 | if (INTEL_GEN(dev_priv) <= 6) | |
1310 | return; | |
1311 | ||
f9e61372 BW |
1312 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
1313 | seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
1314 | slice, subslice, instdone->sampler[slice][subslice]); | |
1315 | ||
1316 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
1317 | seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", | |
1318 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
1319 | } |
1320 | ||
f654449a CW |
1321 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1322 | { | |
36cdd013 | 1323 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
e2f80391 | 1324 | struct intel_engine_cs *engine; |
666796da TU |
1325 | u64 acthd[I915_NUM_ENGINES]; |
1326 | u32 seqno[I915_NUM_ENGINES]; | |
d636951e | 1327 | struct intel_instdone instdone; |
c3232b18 | 1328 | enum intel_engine_id id; |
f654449a | 1329 | |
8af29b0c | 1330 | if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8c185eca CW |
1331 | seq_puts(m, "Wedged\n"); |
1332 | if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) | |
1333 | seq_puts(m, "Reset in progress: struct_mutex backoff\n"); | |
1334 | if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags)) | |
1335 | seq_puts(m, "Reset in progress: reset handoff to waiter\n"); | |
8af29b0c | 1336 | if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) |
8c185eca | 1337 | seq_puts(m, "Waiter holding struct mutex\n"); |
8af29b0c | 1338 | if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) |
8c185eca | 1339 | seq_puts(m, "struct_mutex blocked for reset\n"); |
8af29b0c | 1340 | |
4f044a88 | 1341 | if (!i915_modparams.enable_hangcheck) { |
8c185eca | 1342 | seq_puts(m, "Hangcheck disabled\n"); |
f654449a CW |
1343 | return 0; |
1344 | } | |
1345 | ||
ebbc7546 MK |
1346 | intel_runtime_pm_get(dev_priv); |
1347 | ||
3b3f1650 | 1348 | for_each_engine(engine, dev_priv, id) { |
7e37f889 | 1349 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1350 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1351 | } |
1352 | ||
3b3f1650 | 1353 | intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); |
61642ff0 | 1354 | |
ebbc7546 MK |
1355 | intel_runtime_pm_put(dev_priv); |
1356 | ||
8352aea3 CW |
1357 | if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer)) |
1358 | seq_printf(m, "Hangcheck active, timer fires in %dms\n", | |
f654449a CW |
1359 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
1360 | jiffies)); | |
8352aea3 CW |
1361 | else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) |
1362 | seq_puts(m, "Hangcheck active, work pending\n"); | |
1363 | else | |
1364 | seq_puts(m, "Hangcheck inactive\n"); | |
f654449a | 1365 | |
f73b5674 CW |
1366 | seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake)); |
1367 | ||
3b3f1650 | 1368 | for_each_engine(engine, dev_priv, id) { |
33f53719 CW |
1369 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
1370 | struct rb_node *rb; | |
1371 | ||
e2f80391 | 1372 | seq_printf(m, "%s:\n", engine->name); |
f73b5674 | 1373 | seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n", |
cb399eab | 1374 | engine->hangcheck.seqno, seqno[id], |
f73b5674 CW |
1375 | intel_engine_last_submit(engine), |
1376 | engine->timeline->inflight_seqnos); | |
3fe3b030 | 1377 | seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n", |
83348ba8 CW |
1378 | yesno(intel_engine_has_waiter(engine)), |
1379 | yesno(test_bit(engine->id, | |
3fe3b030 MK |
1380 | &dev_priv->gpu_error.missed_irq_rings)), |
1381 | yesno(engine->hangcheck.stalled)); | |
1382 | ||
61d3dc70 | 1383 | spin_lock_irq(&b->rb_lock); |
33f53719 | 1384 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { |
f802cf7e | 1385 | struct intel_wait *w = rb_entry(rb, typeof(*w), node); |
33f53719 CW |
1386 | |
1387 | seq_printf(m, "\t%s [%d] waiting for %x\n", | |
1388 | w->tsk->comm, w->tsk->pid, w->seqno); | |
1389 | } | |
61d3dc70 | 1390 | spin_unlock_irq(&b->rb_lock); |
33f53719 | 1391 | |
f654449a | 1392 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1393 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1394 | (long long)acthd[id]); |
3fe3b030 MK |
1395 | seq_printf(m, "\taction = %s(%d) %d ms ago\n", |
1396 | hangcheck_action_to_str(engine->hangcheck.action), | |
1397 | engine->hangcheck.action, | |
1398 | jiffies_to_msecs(jiffies - | |
1399 | engine->hangcheck.action_timestamp)); | |
61642ff0 | 1400 | |
e2f80391 | 1401 | if (engine->id == RCS) { |
d636951e | 1402 | seq_puts(m, "\tinstdone read =\n"); |
61642ff0 | 1403 | |
d636951e | 1404 | i915_instdone_info(dev_priv, m, &instdone); |
61642ff0 | 1405 | |
d636951e | 1406 | seq_puts(m, "\tinstdone accu =\n"); |
61642ff0 | 1407 | |
d636951e BW |
1408 | i915_instdone_info(dev_priv, m, |
1409 | &engine->hangcheck.instdone); | |
61642ff0 | 1410 | } |
f654449a CW |
1411 | } |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
061d06a2 MT |
1416 | static int i915_reset_info(struct seq_file *m, void *unused) |
1417 | { | |
1418 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1419 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
1420 | struct intel_engine_cs *engine; | |
1421 | enum intel_engine_id id; | |
1422 | ||
1423 | seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); | |
1424 | ||
1425 | for_each_engine(engine, dev_priv, id) { | |
1426 | seq_printf(m, "%s = %u\n", engine->name, | |
1427 | i915_reset_engine_count(error, engine)); | |
1428 | } | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
4d85529d | 1433 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1434 | { |
36cdd013 | 1435 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
616fdb5a BW |
1436 | u32 rgvmodectl, rstdbyctl; |
1437 | u16 crstandvid; | |
616fdb5a | 1438 | |
616fdb5a BW |
1439 | rgvmodectl = I915_READ(MEMMODECTL); |
1440 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1441 | crstandvid = I915_READ16(CRSTANDVID); | |
1442 | ||
742f491d | 1443 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1444 | seq_printf(m, "Boost freq: %d\n", |
1445 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1446 | MEMMODE_BOOST_FREQ_SHIFT); | |
1447 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1448 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1449 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1450 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1451 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1452 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1453 | seq_printf(m, "Starting frequency: P%d\n", |
1454 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1455 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1456 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1457 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1458 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1459 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1460 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1461 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1462 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1463 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1464 | case RSX_STATUS_ON: | |
267f0c90 | 1465 | seq_puts(m, "on\n"); |
88271da3 JB |
1466 | break; |
1467 | case RSX_STATUS_RC1: | |
267f0c90 | 1468 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1469 | break; |
1470 | case RSX_STATUS_RC1E: | |
267f0c90 | 1471 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1472 | break; |
1473 | case RSX_STATUS_RS1: | |
267f0c90 | 1474 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1475 | break; |
1476 | case RSX_STATUS_RS2: | |
267f0c90 | 1477 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1478 | break; |
1479 | case RSX_STATUS_RS3: | |
267f0c90 | 1480 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1481 | break; |
1482 | default: | |
267f0c90 | 1483 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1484 | break; |
1485 | } | |
f97108d1 JB |
1486 | |
1487 | return 0; | |
1488 | } | |
1489 | ||
f65367b5 | 1490 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1491 | { |
233ebf57 | 1492 | struct drm_i915_private *i915 = node_to_i915(m->private); |
b2cff0db | 1493 | struct intel_uncore_forcewake_domain *fw_domain; |
d2dc94bc | 1494 | unsigned int tmp; |
b2cff0db | 1495 | |
d7a133d8 CW |
1496 | seq_printf(m, "user.bypass_count = %u\n", |
1497 | i915->uncore.user_forcewake.count); | |
1498 | ||
233ebf57 | 1499 | for_each_fw_domain(fw_domain, i915, tmp) |
b2cff0db | 1500 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1501 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
233ebf57 | 1502 | READ_ONCE(fw_domain->wake_count)); |
669ab5aa | 1503 | |
b2cff0db CW |
1504 | return 0; |
1505 | } | |
1506 | ||
1362877e MK |
1507 | static void print_rc6_res(struct seq_file *m, |
1508 | const char *title, | |
1509 | const i915_reg_t reg) | |
1510 | { | |
1511 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
1512 | ||
1513 | seq_printf(m, "%s %u (%llu us)\n", | |
1514 | title, I915_READ(reg), | |
1515 | intel_rc6_residency_us(dev_priv, reg)); | |
1516 | } | |
1517 | ||
b2cff0db CW |
1518 | static int vlv_drpc_info(struct seq_file *m) |
1519 | { | |
36cdd013 | 1520 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
0d6fc92a | 1521 | u32 rcctl1, pw_status; |
669ab5aa | 1522 | |
6b312cd3 | 1523 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1524 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
1525 | ||
669ab5aa D |
1526 | seq_printf(m, "RC6 Enabled: %s\n", |
1527 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1528 | GEN6_RC_CTL_EI_MODE(1)))); | |
1529 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1530 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1531 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1532 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1533 | |
1362877e MK |
1534 | print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6); |
1535 | print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); | |
9cc19be5 | 1536 | |
f65367b5 | 1537 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1538 | } |
1539 | ||
4d85529d BW |
1540 | static int gen6_drpc_info(struct seq_file *m) |
1541 | { | |
36cdd013 | 1542 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
960e5465 | 1543 | u32 gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1544 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1545 | unsigned forcewake_count; |
cf632bd6 | 1546 | int count = 0; |
93b525dc | 1547 | |
cf632bd6 | 1548 | forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count); |
93b525dc | 1549 | if (forcewake_count) { |
267f0c90 DL |
1550 | seq_puts(m, "RC information inaccurate because somebody " |
1551 | "holds a forcewake reference \n"); | |
4d85529d BW |
1552 | } else { |
1553 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1554 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1555 | udelay(10); | |
1556 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1557 | } | |
1558 | ||
75aa3f63 | 1559 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1560 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d | 1561 | |
4d85529d | 1562 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
36cdd013 | 1563 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1564 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); |
1565 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1566 | } | |
cf632bd6 | 1567 | |
44cbd338 BW |
1568 | mutex_lock(&dev_priv->rps.hw_lock); |
1569 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1570 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1571 | |
fff24e21 | 1572 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1573 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1574 | seq_printf(m, "RC6 Enabled: %s\n", | |
1575 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
36cdd013 | 1576 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1577 | seq_printf(m, "Render Well Gating Enabled: %s\n", |
1578 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1579 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1580 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1581 | } | |
4d85529d BW |
1582 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1583 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1584 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1585 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1586 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1587 | switch (gt_core_status & GEN6_RCn_MASK) { |
1588 | case GEN6_RC0: | |
1589 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1590 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1591 | else |
267f0c90 | 1592 | seq_puts(m, "on\n"); |
4d85529d BW |
1593 | break; |
1594 | case GEN6_RC3: | |
267f0c90 | 1595 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1596 | break; |
1597 | case GEN6_RC6: | |
267f0c90 | 1598 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1599 | break; |
1600 | case GEN6_RC7: | |
267f0c90 | 1601 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1602 | break; |
1603 | default: | |
267f0c90 | 1604 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1605 | break; |
1606 | } | |
1607 | ||
1608 | seq_printf(m, "Core Power Down: %s\n", | |
1609 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
36cdd013 | 1610 | if (INTEL_GEN(dev_priv) >= 9) { |
f2dd7578 AG |
1611 | seq_printf(m, "Render Power Well: %s\n", |
1612 | (gen9_powergate_status & | |
1613 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1614 | seq_printf(m, "Media Power Well: %s\n", | |
1615 | (gen9_powergate_status & | |
1616 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1617 | } | |
cce66a28 BW |
1618 | |
1619 | /* Not exactly sure what this is */ | |
1362877e MK |
1620 | print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", |
1621 | GEN6_GT_GFX_RC6_LOCKED); | |
1622 | print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); | |
1623 | print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); | |
1624 | print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); | |
cce66a28 | 1625 | |
ecd8faea BW |
1626 | seq_printf(m, "RC6 voltage: %dmV\n", |
1627 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1628 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1629 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1630 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1631 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1632 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1633 | } |
1634 | ||
1635 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1636 | { | |
36cdd013 | 1637 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
cf632bd6 CW |
1638 | int err; |
1639 | ||
1640 | intel_runtime_pm_get(dev_priv); | |
4d85529d | 1641 | |
36cdd013 | 1642 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
cf632bd6 | 1643 | err = vlv_drpc_info(m); |
36cdd013 | 1644 | else if (INTEL_GEN(dev_priv) >= 6) |
cf632bd6 | 1645 | err = gen6_drpc_info(m); |
4d85529d | 1646 | else |
cf632bd6 CW |
1647 | err = ironlake_drpc_info(m); |
1648 | ||
1649 | intel_runtime_pm_put(dev_priv); | |
1650 | ||
1651 | return err; | |
4d85529d BW |
1652 | } |
1653 | ||
9a851789 DV |
1654 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1655 | { | |
36cdd013 | 1656 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
9a851789 DV |
1657 | |
1658 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1659 | dev_priv->fb_tracking.busy_bits); | |
1660 | ||
1661 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1662 | dev_priv->fb_tracking.flip_bits); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
b5e50c3f JB |
1667 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1668 | { | |
36cdd013 | 1669 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b5e50c3f | 1670 | |
36cdd013 | 1671 | if (!HAS_FBC(dev_priv)) { |
267f0c90 | 1672 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1673 | return 0; |
1674 | } | |
1675 | ||
36623ef8 | 1676 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1677 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1678 | |
0e631adc | 1679 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1680 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1681 | else |
1682 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1683 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1684 | |
3fd5d1ec VS |
1685 | if (intel_fbc_is_active(dev_priv)) { |
1686 | u32 mask; | |
1687 | ||
1688 | if (INTEL_GEN(dev_priv) >= 8) | |
1689 | mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; | |
1690 | else if (INTEL_GEN(dev_priv) >= 7) | |
1691 | mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; | |
1692 | else if (INTEL_GEN(dev_priv) >= 5) | |
1693 | mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; | |
1694 | else if (IS_G4X(dev_priv)) | |
1695 | mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; | |
1696 | else | |
1697 | mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | | |
1698 | FBC_STAT_COMPRESSED); | |
1699 | ||
1700 | seq_printf(m, "Compressing: %s\n", yesno(mask)); | |
0fc6a9dc | 1701 | } |
31b9df10 | 1702 | |
25ad93fd | 1703 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1704 | intel_runtime_pm_put(dev_priv); |
1705 | ||
b5e50c3f JB |
1706 | return 0; |
1707 | } | |
1708 | ||
4127dc43 | 1709 | static int i915_fbc_false_color_get(void *data, u64 *val) |
da46f936 | 1710 | { |
36cdd013 | 1711 | struct drm_i915_private *dev_priv = data; |
da46f936 | 1712 | |
36cdd013 | 1713 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1714 | return -ENODEV; |
1715 | ||
da46f936 | 1716 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1717 | |
1718 | return 0; | |
1719 | } | |
1720 | ||
4127dc43 | 1721 | static int i915_fbc_false_color_set(void *data, u64 val) |
da46f936 | 1722 | { |
36cdd013 | 1723 | struct drm_i915_private *dev_priv = data; |
da46f936 RV |
1724 | u32 reg; |
1725 | ||
36cdd013 | 1726 | if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) |
da46f936 RV |
1727 | return -ENODEV; |
1728 | ||
25ad93fd | 1729 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1730 | |
1731 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1732 | dev_priv->fbc.false_color = val; | |
1733 | ||
1734 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1735 | (reg | FBC_CTL_FALSE_COLOR) : | |
1736 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1737 | ||
25ad93fd | 1738 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1739 | return 0; |
1740 | } | |
1741 | ||
4127dc43 VS |
1742 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, |
1743 | i915_fbc_false_color_get, i915_fbc_false_color_set, | |
da46f936 RV |
1744 | "%llu\n"); |
1745 | ||
92d44621 PZ |
1746 | static int i915_ips_status(struct seq_file *m, void *unused) |
1747 | { | |
36cdd013 | 1748 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
92d44621 | 1749 | |
36cdd013 | 1750 | if (!HAS_IPS(dev_priv)) { |
92d44621 PZ |
1751 | seq_puts(m, "not supported\n"); |
1752 | return 0; | |
1753 | } | |
1754 | ||
36623ef8 PZ |
1755 | intel_runtime_pm_get(dev_priv); |
1756 | ||
0eaa53f0 | 1757 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
4f044a88 | 1758 | yesno(i915_modparams.enable_ips)); |
0eaa53f0 | 1759 | |
36cdd013 | 1760 | if (INTEL_GEN(dev_priv) >= 8) { |
0eaa53f0 RV |
1761 | seq_puts(m, "Currently: unknown\n"); |
1762 | } else { | |
1763 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1764 | seq_puts(m, "Currently: enabled\n"); | |
1765 | else | |
1766 | seq_puts(m, "Currently: disabled\n"); | |
1767 | } | |
92d44621 | 1768 | |
36623ef8 PZ |
1769 | intel_runtime_pm_put(dev_priv); |
1770 | ||
92d44621 PZ |
1771 | return 0; |
1772 | } | |
1773 | ||
4a9bef37 JB |
1774 | static int i915_sr_status(struct seq_file *m, void *unused) |
1775 | { | |
36cdd013 | 1776 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
4a9bef37 JB |
1777 | bool sr_enabled = false; |
1778 | ||
36623ef8 | 1779 | intel_runtime_pm_get(dev_priv); |
9c870d03 | 1780 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 | 1781 | |
7342a72c CW |
1782 | if (INTEL_GEN(dev_priv) >= 9) |
1783 | /* no global SR status; inspect per-plane WM */; | |
1784 | else if (HAS_PCH_SPLIT(dev_priv)) | |
5ba2aaaa | 1785 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
c0f86832 | 1786 | else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || |
36cdd013 | 1787 | IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
4a9bef37 | 1788 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
36cdd013 | 1789 | else if (IS_I915GM(dev_priv)) |
4a9bef37 | 1790 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
36cdd013 | 1791 | else if (IS_PINEVIEW(dev_priv)) |
4a9bef37 | 1792 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
36cdd013 | 1793 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
77b64555 | 1794 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1795 | |
9c870d03 | 1796 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
36623ef8 PZ |
1797 | intel_runtime_pm_put(dev_priv); |
1798 | ||
08c4d7fc | 1799 | seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); |
4a9bef37 JB |
1800 | |
1801 | return 0; | |
1802 | } | |
1803 | ||
7648fa99 JB |
1804 | static int i915_emon_status(struct seq_file *m, void *unused) |
1805 | { | |
36cdd013 DW |
1806 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1807 | struct drm_device *dev = &dev_priv->drm; | |
7648fa99 | 1808 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1809 | int ret; |
1810 | ||
36cdd013 | 1811 | if (!IS_GEN5(dev_priv)) |
582be6b4 CW |
1812 | return -ENODEV; |
1813 | ||
de227ef0 CW |
1814 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1815 | if (ret) | |
1816 | return ret; | |
7648fa99 JB |
1817 | |
1818 | temp = i915_mch_val(dev_priv); | |
1819 | chipset = i915_chipset_val(dev_priv); | |
1820 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1821 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1822 | |
1823 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1824 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1825 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1826 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
23b2f8bb JB |
1831 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1832 | { | |
36cdd013 | 1833 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
5bfa0199 | 1834 | int ret = 0; |
23b2f8bb | 1835 | int gpu_freq, ia_freq; |
f936ec34 | 1836 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1837 | |
26310346 | 1838 | if (!HAS_LLC(dev_priv)) { |
267f0c90 | 1839 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1840 | return 0; |
1841 | } | |
1842 | ||
5bfa0199 PZ |
1843 | intel_runtime_pm_get(dev_priv); |
1844 | ||
4fc688ce | 1845 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1846 | if (ret) |
5bfa0199 | 1847 | goto out; |
23b2f8bb | 1848 | |
35ceabf3 | 1849 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
f936ec34 AG |
1850 | /* Convert GT frequency to 50 HZ units */ |
1851 | min_gpu_freq = | |
1852 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1853 | max_gpu_freq = | |
1854 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1855 | } else { | |
1856 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1857 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1858 | } | |
1859 | ||
267f0c90 | 1860 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1861 | |
f936ec34 | 1862 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1863 | ia_freq = gpu_freq; |
1864 | sandybridge_pcode_read(dev_priv, | |
1865 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1866 | &ia_freq); | |
3ebecd07 | 1867 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1868 | intel_gpu_freq(dev_priv, (gpu_freq * |
35ceabf3 RV |
1869 | (IS_GEN9_BC(dev_priv) || |
1870 | IS_CANNONLAKE(dev_priv) ? | |
b976dc53 | 1871 | GEN9_FREQ_SCALER : 1))), |
3ebecd07 CW |
1872 | ((ia_freq >> 0) & 0xff) * 100, |
1873 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1874 | } |
1875 | ||
4fc688ce | 1876 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1877 | |
5bfa0199 PZ |
1878 | out: |
1879 | intel_runtime_pm_put(dev_priv); | |
1880 | return ret; | |
23b2f8bb JB |
1881 | } |
1882 | ||
44834a67 CW |
1883 | static int i915_opregion(struct seq_file *m, void *unused) |
1884 | { | |
36cdd013 DW |
1885 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1886 | struct drm_device *dev = &dev_priv->drm; | |
44834a67 CW |
1887 | struct intel_opregion *opregion = &dev_priv->opregion; |
1888 | int ret; | |
1889 | ||
1890 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1891 | if (ret) | |
0d38f009 | 1892 | goto out; |
44834a67 | 1893 | |
2455a8e4 JN |
1894 | if (opregion->header) |
1895 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1896 | |
1897 | mutex_unlock(&dev->struct_mutex); | |
1898 | ||
0d38f009 | 1899 | out: |
44834a67 CW |
1900 | return 0; |
1901 | } | |
1902 | ||
ada8f955 JN |
1903 | static int i915_vbt(struct seq_file *m, void *unused) |
1904 | { | |
36cdd013 | 1905 | struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; |
ada8f955 JN |
1906 | |
1907 | if (opregion->vbt) | |
1908 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
37811fcc CW |
1913 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1914 | { | |
36cdd013 DW |
1915 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1916 | struct drm_device *dev = &dev_priv->drm; | |
b13b8402 | 1917 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1918 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1919 | int ret; |
1920 | ||
1921 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1922 | if (ret) | |
1923 | return ret; | |
37811fcc | 1924 | |
0695726e | 1925 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
346fb4e0 | 1926 | if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { |
36cdd013 | 1927 | fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); |
25bcce94 CW |
1928 | |
1929 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1930 | fbdev_fb->base.width, | |
1931 | fbdev_fb->base.height, | |
b00c600e | 1932 | fbdev_fb->base.format->depth, |
272725c7 | 1933 | fbdev_fb->base.format->cpp[0] * 8, |
bae781b2 | 1934 | fbdev_fb->base.modifier, |
25bcce94 CW |
1935 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
1936 | describe_obj(m, fbdev_fb->obj); | |
1937 | seq_putc(m, '\n'); | |
1938 | } | |
4520f53a | 1939 | #endif |
37811fcc | 1940 | |
4b096ac1 | 1941 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1942 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1943 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1944 | if (fb == fbdev_fb) | |
37811fcc CW |
1945 | continue; |
1946 | ||
c1ca506d | 1947 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1948 | fb->base.width, |
1949 | fb->base.height, | |
b00c600e | 1950 | fb->base.format->depth, |
272725c7 | 1951 | fb->base.format->cpp[0] * 8, |
bae781b2 | 1952 | fb->base.modifier, |
747a598f | 1953 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1954 | describe_obj(m, fb->obj); |
267f0c90 | 1955 | seq_putc(m, '\n'); |
37811fcc | 1956 | } |
4b096ac1 | 1957 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1958 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1959 | |
1960 | return 0; | |
1961 | } | |
1962 | ||
7e37f889 | 1963 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd | 1964 | { |
fe085f13 CW |
1965 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)", |
1966 | ring->space, ring->head, ring->tail); | |
c9fe99bd OM |
1967 | } |
1968 | ||
e76d3630 BW |
1969 | static int i915_context_status(struct seq_file *m, void *unused) |
1970 | { | |
36cdd013 DW |
1971 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1972 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 1973 | struct intel_engine_cs *engine; |
e2efd130 | 1974 | struct i915_gem_context *ctx; |
3b3f1650 | 1975 | enum intel_engine_id id; |
c3232b18 | 1976 | int ret; |
e76d3630 | 1977 | |
f3d28878 | 1978 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1979 | if (ret) |
1980 | return ret; | |
1981 | ||
829a0af2 | 1982 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
5d1808ec | 1983 | seq_printf(m, "HW context %u ", ctx->hw_id); |
c84455b4 | 1984 | if (ctx->pid) { |
d28b99ab CW |
1985 | struct task_struct *task; |
1986 | ||
c84455b4 | 1987 | task = get_pid_task(ctx->pid, PIDTYPE_PID); |
d28b99ab CW |
1988 | if (task) { |
1989 | seq_printf(m, "(%s [%d]) ", | |
1990 | task->comm, task->pid); | |
1991 | put_task_struct(task); | |
1992 | } | |
c84455b4 CW |
1993 | } else if (IS_ERR(ctx->file_priv)) { |
1994 | seq_puts(m, "(deleted) "); | |
d28b99ab CW |
1995 | } else { |
1996 | seq_puts(m, "(kernel) "); | |
1997 | } | |
1998 | ||
bca44d80 CW |
1999 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
2000 | seq_putc(m, '\n'); | |
c9fe99bd | 2001 | |
3b3f1650 | 2002 | for_each_engine(engine, dev_priv, id) { |
bca44d80 CW |
2003 | struct intel_context *ce = &ctx->engine[engine->id]; |
2004 | ||
2005 | seq_printf(m, "%s: ", engine->name); | |
2006 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
2007 | if (ce->state) | |
bf3783e5 | 2008 | describe_obj(m, ce->state->obj); |
dca33ecc | 2009 | if (ce->ring) |
7e37f889 | 2010 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 2011 | seq_putc(m, '\n'); |
c9fe99bd | 2012 | } |
a33afea5 | 2013 | |
a33afea5 | 2014 | seq_putc(m, '\n'); |
a168c293 BW |
2015 | } |
2016 | ||
f3d28878 | 2017 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2018 | |
2019 | return 0; | |
2020 | } | |
2021 | ||
064ca1d2 | 2022 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2023 | struct i915_gem_context *ctx, |
0bc40be8 | 2024 | struct intel_engine_cs *engine) |
064ca1d2 | 2025 | { |
bf3783e5 | 2026 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 2027 | struct page *page; |
064ca1d2 | 2028 | int j; |
064ca1d2 | 2029 | |
7069b144 CW |
2030 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2031 | ||
bf3783e5 CW |
2032 | if (!vma) { |
2033 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2034 | return; |
2035 | } | |
2036 | ||
bf3783e5 CW |
2037 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2038 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
bde13ebd | 2039 | i915_ggtt_offset(vma)); |
064ca1d2 | 2040 | |
a4f5ea64 | 2041 | if (i915_gem_object_pin_pages(vma->obj)) { |
bf3783e5 | 2042 | seq_puts(m, "\tFailed to get pages for context object\n\n"); |
064ca1d2 TD |
2043 | return; |
2044 | } | |
2045 | ||
bf3783e5 CW |
2046 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2047 | if (page) { | |
2048 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2049 | |
2050 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2051 | seq_printf(m, |
2052 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2053 | j * 4, | |
064ca1d2 TD |
2054 | reg_state[j], reg_state[j + 1], |
2055 | reg_state[j + 2], reg_state[j + 3]); | |
2056 | } | |
2057 | kunmap_atomic(reg_state); | |
2058 | } | |
2059 | ||
a4f5ea64 | 2060 | i915_gem_object_unpin_pages(vma->obj); |
064ca1d2 TD |
2061 | seq_putc(m, '\n'); |
2062 | } | |
2063 | ||
c0ab1ae9 BW |
2064 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2065 | { | |
36cdd013 DW |
2066 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2067 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 2068 | struct intel_engine_cs *engine; |
e2efd130 | 2069 | struct i915_gem_context *ctx; |
3b3f1650 | 2070 | enum intel_engine_id id; |
b4ac5afc | 2071 | int ret; |
c0ab1ae9 | 2072 | |
4f044a88 | 2073 | if (!i915_modparams.enable_execlists) { |
c0ab1ae9 BW |
2074 | seq_printf(m, "Logical Ring Contexts are disabled\n"); |
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2079 | if (ret) | |
2080 | return ret; | |
2081 | ||
829a0af2 | 2082 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) |
3b3f1650 | 2083 | for_each_engine(engine, dev_priv, id) |
24f1d3cc | 2084 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2085 | |
2086 | mutex_unlock(&dev->struct_mutex); | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
ea16a3cd DV |
2091 | static const char *swizzle_string(unsigned swizzle) |
2092 | { | |
aee56cff | 2093 | switch (swizzle) { |
ea16a3cd DV |
2094 | case I915_BIT_6_SWIZZLE_NONE: |
2095 | return "none"; | |
2096 | case I915_BIT_6_SWIZZLE_9: | |
2097 | return "bit9"; | |
2098 | case I915_BIT_6_SWIZZLE_9_10: | |
2099 | return "bit9/bit10"; | |
2100 | case I915_BIT_6_SWIZZLE_9_11: | |
2101 | return "bit9/bit11"; | |
2102 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2103 | return "bit9/bit10/bit11"; | |
2104 | case I915_BIT_6_SWIZZLE_9_17: | |
2105 | return "bit9/bit17"; | |
2106 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2107 | return "bit9/bit10/bit17"; | |
2108 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2109 | return "unknown"; |
ea16a3cd DV |
2110 | } |
2111 | ||
2112 | return "bug"; | |
2113 | } | |
2114 | ||
2115 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2116 | { | |
36cdd013 | 2117 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
22bcfc6a | 2118 | |
c8c8fb33 | 2119 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2120 | |
ea16a3cd DV |
2121 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2122 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2123 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2124 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2125 | ||
36cdd013 | 2126 | if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { |
ea16a3cd DV |
2127 | seq_printf(m, "DDC = 0x%08x\n", |
2128 | I915_READ(DCC)); | |
656bfa3a DV |
2129 | seq_printf(m, "DDC2 = 0x%08x\n", |
2130 | I915_READ(DCC2)); | |
ea16a3cd DV |
2131 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2132 | I915_READ16(C0DRB3)); | |
2133 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2134 | I915_READ16(C1DRB3)); | |
36cdd013 | 2135 | } else if (INTEL_GEN(dev_priv) >= 6) { |
3fa7d235 DV |
2136 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2137 | I915_READ(MAD_DIMM_C0)); | |
2138 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2139 | I915_READ(MAD_DIMM_C1)); | |
2140 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2141 | I915_READ(MAD_DIMM_C2)); | |
2142 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2143 | I915_READ(TILECTL)); | |
36cdd013 | 2144 | if (INTEL_GEN(dev_priv) >= 8) |
9d3203e1 BW |
2145 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2146 | I915_READ(GAMTARBMODE)); | |
2147 | else | |
2148 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2149 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2150 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2151 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2152 | } |
656bfa3a DV |
2153 | |
2154 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2155 | seq_puts(m, "L-shaped memory detected\n"); | |
2156 | ||
c8c8fb33 | 2157 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2158 | |
2159 | return 0; | |
2160 | } | |
2161 | ||
1c60fef5 BW |
2162 | static int per_file_ctx(int id, void *ptr, void *data) |
2163 | { | |
e2efd130 | 2164 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2165 | struct seq_file *m = data; |
ae6c4806 DV |
2166 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2167 | ||
2168 | if (!ppgtt) { | |
2169 | seq_printf(m, " no ppgtt for context %d\n", | |
2170 | ctx->user_handle); | |
2171 | return 0; | |
2172 | } | |
1c60fef5 | 2173 | |
f83d6518 OM |
2174 | if (i915_gem_context_is_default(ctx)) |
2175 | seq_puts(m, " default context:\n"); | |
2176 | else | |
821d66dd | 2177 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2178 | ppgtt->debug_dump(ppgtt, m); |
2179 | ||
2180 | return 0; | |
2181 | } | |
2182 | ||
36cdd013 DW |
2183 | static void gen8_ppgtt_info(struct seq_file *m, |
2184 | struct drm_i915_private *dev_priv) | |
3cf17fc5 | 2185 | { |
77df6772 | 2186 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3b3f1650 AG |
2187 | struct intel_engine_cs *engine; |
2188 | enum intel_engine_id id; | |
b4ac5afc | 2189 | int i; |
3cf17fc5 | 2190 | |
77df6772 BW |
2191 | if (!ppgtt) |
2192 | return; | |
2193 | ||
3b3f1650 | 2194 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2195 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2196 | for (i = 0; i < 4; i++) { |
e2f80391 | 2197 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2198 | pdp <<= 32; |
e2f80391 | 2199 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2200 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2201 | } |
2202 | } | |
2203 | } | |
2204 | ||
36cdd013 DW |
2205 | static void gen6_ppgtt_info(struct seq_file *m, |
2206 | struct drm_i915_private *dev_priv) | |
77df6772 | 2207 | { |
e2f80391 | 2208 | struct intel_engine_cs *engine; |
3b3f1650 | 2209 | enum intel_engine_id id; |
3cf17fc5 | 2210 | |
7e22dbbb | 2211 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2212 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2213 | ||
3b3f1650 | 2214 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 2215 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2216 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2217 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2218 | I915_READ(RING_MODE_GEN7(engine))); | |
2219 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2220 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2221 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2222 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2223 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2224 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2225 | } |
2226 | if (dev_priv->mm.aliasing_ppgtt) { | |
2227 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2228 | ||
267f0c90 | 2229 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2230 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2231 | |
87d60b63 | 2232 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2233 | } |
1c60fef5 | 2234 | |
3cf17fc5 | 2235 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2236 | } |
2237 | ||
2238 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2239 | { | |
36cdd013 DW |
2240 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2241 | struct drm_device *dev = &dev_priv->drm; | |
ea91e401 | 2242 | struct drm_file *file; |
637ee29e | 2243 | int ret; |
77df6772 | 2244 | |
637ee29e CW |
2245 | mutex_lock(&dev->filelist_mutex); |
2246 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
77df6772 | 2247 | if (ret) |
637ee29e CW |
2248 | goto out_unlock; |
2249 | ||
c8c8fb33 | 2250 | intel_runtime_pm_get(dev_priv); |
77df6772 | 2251 | |
36cdd013 DW |
2252 | if (INTEL_GEN(dev_priv) >= 8) |
2253 | gen8_ppgtt_info(m, dev_priv); | |
2254 | else if (INTEL_GEN(dev_priv) >= 6) | |
2255 | gen6_ppgtt_info(m, dev_priv); | |
77df6772 | 2256 | |
ea91e401 MT |
2257 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2258 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2259 | struct task_struct *task; |
ea91e401 | 2260 | |
7cb5dff8 | 2261 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2262 | if (!task) { |
2263 | ret = -ESRCH; | |
637ee29e | 2264 | goto out_rpm; |
06812760 | 2265 | } |
7cb5dff8 GT |
2266 | seq_printf(m, "\nproc: %s\n", task->comm); |
2267 | put_task_struct(task); | |
ea91e401 MT |
2268 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2269 | (void *)(unsigned long)m); | |
2270 | } | |
2271 | ||
637ee29e | 2272 | out_rpm: |
c8c8fb33 | 2273 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 | 2274 | mutex_unlock(&dev->struct_mutex); |
637ee29e CW |
2275 | out_unlock: |
2276 | mutex_unlock(&dev->filelist_mutex); | |
06812760 | 2277 | return ret; |
3cf17fc5 DV |
2278 | } |
2279 | ||
f5a4c67d CW |
2280 | static int count_irq_waiters(struct drm_i915_private *i915) |
2281 | { | |
e2f80391 | 2282 | struct intel_engine_cs *engine; |
3b3f1650 | 2283 | enum intel_engine_id id; |
f5a4c67d | 2284 | int count = 0; |
f5a4c67d | 2285 | |
3b3f1650 | 2286 | for_each_engine(engine, i915, id) |
688e6c72 | 2287 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2288 | |
2289 | return count; | |
2290 | } | |
2291 | ||
7466c291 CW |
2292 | static const char *rps_power_to_str(unsigned int power) |
2293 | { | |
2294 | static const char * const strings[] = { | |
2295 | [LOW_POWER] = "low power", | |
2296 | [BETWEEN] = "mixed", | |
2297 | [HIGH_POWER] = "high power", | |
2298 | }; | |
2299 | ||
2300 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2301 | return "unknown"; | |
2302 | ||
2303 | return strings[power]; | |
2304 | } | |
2305 | ||
1854d5ca CW |
2306 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2307 | { | |
36cdd013 DW |
2308 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2309 | struct drm_device *dev = &dev_priv->drm; | |
1854d5ca | 2310 | struct drm_file *file; |
1854d5ca | 2311 | |
f5a4c67d | 2312 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
28176ef4 CW |
2313 | seq_printf(m, "GPU busy? %s [%d requests]\n", |
2314 | yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); | |
f5a4c67d | 2315 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7b92c1bd CW |
2316 | seq_printf(m, "Boosts outstanding? %d\n", |
2317 | atomic_read(&dev_priv->rps.num_waiters)); | |
7466c291 CW |
2318 | seq_printf(m, "Frequency requested %d\n", |
2319 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2320 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2321 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2322 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2323 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2324 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2325 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2326 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2327 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2328 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2329 | |
2330 | mutex_lock(&dev->filelist_mutex); | |
1854d5ca CW |
2331 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2332 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2333 | struct task_struct *task; | |
2334 | ||
2335 | rcu_read_lock(); | |
2336 | task = pid_task(file->pid, PIDTYPE_PID); | |
7b92c1bd | 2337 | seq_printf(m, "%s [%d]: %d boosts\n", |
1854d5ca CW |
2338 | task ? task->comm : "<unknown>", |
2339 | task ? task->pid : -1, | |
7b92c1bd | 2340 | atomic_read(&file_priv->rps.boosts)); |
1854d5ca CW |
2341 | rcu_read_unlock(); |
2342 | } | |
7b92c1bd CW |
2343 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", |
2344 | atomic_read(&dev_priv->rps.boosts)); | |
1d2ac403 | 2345 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2346 | |
7466c291 CW |
2347 | if (INTEL_GEN(dev_priv) >= 6 && |
2348 | dev_priv->rps.enabled && | |
28176ef4 | 2349 | dev_priv->gt.active_requests) { |
7466c291 CW |
2350 | u32 rpup, rpupei; |
2351 | u32 rpdown, rpdownei; | |
2352 | ||
2353 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2354 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2355 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2356 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2357 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2358 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2359 | ||
2360 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2361 | rps_power_to_str(dev_priv->rps.power)); | |
2362 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
23f4a287 | 2363 | rpup && rpupei ? 100 * rpup / rpupei : 0, |
7466c291 CW |
2364 | dev_priv->rps.up_threshold); |
2365 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
23f4a287 | 2366 | rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, |
7466c291 CW |
2367 | dev_priv->rps.down_threshold); |
2368 | } else { | |
2369 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2370 | } | |
2371 | ||
8d3afd7d | 2372 | return 0; |
1854d5ca CW |
2373 | } |
2374 | ||
63573eb7 BW |
2375 | static int i915_llc(struct seq_file *m, void *data) |
2376 | { | |
36cdd013 | 2377 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3accaf7e | 2378 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2379 | |
36cdd013 | 2380 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); |
3accaf7e MK |
2381 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2382 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2383 | |
2384 | return 0; | |
2385 | } | |
2386 | ||
0509ead1 AS |
2387 | static int i915_huc_load_status_info(struct seq_file *m, void *data) |
2388 | { | |
2389 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2390 | struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; | |
2391 | ||
2392 | if (!HAS_HUC_UCODE(dev_priv)) | |
2393 | return 0; | |
2394 | ||
2395 | seq_puts(m, "HuC firmware status:\n"); | |
2396 | seq_printf(m, "\tpath: %s\n", huc_fw->path); | |
2397 | seq_printf(m, "\tfetch: %s\n", | |
2398 | intel_uc_fw_status_repr(huc_fw->fetch_status)); | |
2399 | seq_printf(m, "\tload: %s\n", | |
2400 | intel_uc_fw_status_repr(huc_fw->load_status)); | |
2401 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2402 | huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted); | |
2403 | seq_printf(m, "\tversion found: %d.%d\n", | |
2404 | huc_fw->major_ver_found, huc_fw->minor_ver_found); | |
2405 | seq_printf(m, "\theader: offset is %d; size = %d\n", | |
2406 | huc_fw->header_offset, huc_fw->header_size); | |
2407 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2408 | huc_fw->ucode_offset, huc_fw->ucode_size); | |
2409 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2410 | huc_fw->rsa_offset, huc_fw->rsa_size); | |
2411 | ||
3582ad13 | 2412 | intel_runtime_pm_get(dev_priv); |
0509ead1 | 2413 | seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); |
3582ad13 | 2414 | intel_runtime_pm_put(dev_priv); |
0509ead1 AS |
2415 | |
2416 | return 0; | |
2417 | } | |
2418 | ||
fdf5d357 AD |
2419 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2420 | { | |
36cdd013 | 2421 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
db0a091b | 2422 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
fdf5d357 AD |
2423 | u32 tmp, i; |
2424 | ||
2d1fe073 | 2425 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2426 | return 0; |
2427 | ||
2428 | seq_printf(m, "GuC firmware status:\n"); | |
2429 | seq_printf(m, "\tpath: %s\n", | |
db0a091b | 2430 | guc_fw->path); |
fdf5d357 | 2431 | seq_printf(m, "\tfetch: %s\n", |
db0a091b | 2432 | intel_uc_fw_status_repr(guc_fw->fetch_status)); |
fdf5d357 | 2433 | seq_printf(m, "\tload: %s\n", |
db0a091b | 2434 | intel_uc_fw_status_repr(guc_fw->load_status)); |
fdf5d357 | 2435 | seq_printf(m, "\tversion wanted: %d.%d\n", |
db0a091b | 2436 | guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted); |
fdf5d357 | 2437 | seq_printf(m, "\tversion found: %d.%d\n", |
db0a091b | 2438 | guc_fw->major_ver_found, guc_fw->minor_ver_found); |
feda33ef AD |
2439 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2440 | guc_fw->header_offset, guc_fw->header_size); | |
2441 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2442 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2443 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2444 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 | 2445 | |
3582ad13 | 2446 | intel_runtime_pm_get(dev_priv); |
2447 | ||
fdf5d357 AD |
2448 | tmp = I915_READ(GUC_STATUS); |
2449 | ||
2450 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2451 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2452 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2453 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2454 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2455 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2456 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2457 | seq_puts(m, "\nScratch registers:\n"); | |
2458 | for (i = 0; i < 16; i++) | |
2459 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2460 | ||
3582ad13 | 2461 | intel_runtime_pm_put(dev_priv); |
2462 | ||
fdf5d357 AD |
2463 | return 0; |
2464 | } | |
2465 | ||
5aa1ee4b AG |
2466 | static void i915_guc_log_info(struct seq_file *m, |
2467 | struct drm_i915_private *dev_priv) | |
2468 | { | |
2469 | struct intel_guc *guc = &dev_priv->guc; | |
2470 | ||
2471 | seq_puts(m, "\nGuC logging stats:\n"); | |
2472 | ||
2473 | seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", | |
2474 | guc->log.flush_count[GUC_ISR_LOG_BUFFER], | |
2475 | guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); | |
2476 | ||
2477 | seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", | |
2478 | guc->log.flush_count[GUC_DPC_LOG_BUFFER], | |
2479 | guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); | |
2480 | ||
2481 | seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", | |
2482 | guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], | |
2483 | guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); | |
2484 | ||
2485 | seq_printf(m, "\tTotal flush interrupt count: %u\n", | |
2486 | guc->log.flush_interrupt_count); | |
2487 | ||
2488 | seq_printf(m, "\tCapture miss count: %u\n", | |
2489 | guc->log.capture_miss_count); | |
2490 | } | |
2491 | ||
8b417c26 DG |
2492 | static void i915_guc_client_info(struct seq_file *m, |
2493 | struct drm_i915_private *dev_priv, | |
2494 | struct i915_guc_client *client) | |
2495 | { | |
e2f80391 | 2496 | struct intel_engine_cs *engine; |
c18468c4 | 2497 | enum intel_engine_id id; |
8b417c26 | 2498 | uint64_t tot = 0; |
8b417c26 | 2499 | |
b09935a6 OM |
2500 | seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", |
2501 | client->priority, client->stage_id, client->proc_desc_offset); | |
59db36cf MW |
2502 | seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", |
2503 | client->doorbell_id, client->doorbell_offset); | |
8b417c26 | 2504 | |
3b3f1650 | 2505 | for_each_engine(engine, dev_priv, id) { |
c18468c4 DG |
2506 | u64 submissions = client->submissions[id]; |
2507 | tot += submissions; | |
8b417c26 | 2508 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2509 | submissions, engine->name); |
8b417c26 DG |
2510 | } |
2511 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2512 | } | |
2513 | ||
a8b9370f | 2514 | static bool check_guc_submission(struct seq_file *m) |
8b417c26 | 2515 | { |
36cdd013 | 2516 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
334636c6 | 2517 | const struct intel_guc *guc = &dev_priv->guc; |
8b417c26 | 2518 | |
334636c6 CW |
2519 | if (!guc->execbuf_client) { |
2520 | seq_printf(m, "GuC submission %s\n", | |
2521 | HAS_GUC_SCHED(dev_priv) ? | |
2522 | "disabled" : | |
2523 | "not supported"); | |
a8b9370f | 2524 | return false; |
334636c6 | 2525 | } |
8b417c26 | 2526 | |
a8b9370f OM |
2527 | return true; |
2528 | } | |
2529 | ||
2530 | static int i915_guc_info(struct seq_file *m, void *data) | |
2531 | { | |
2532 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
2533 | const struct intel_guc *guc = &dev_priv->guc; | |
a8b9370f OM |
2534 | |
2535 | if (!check_guc_submission(m)) | |
2536 | return 0; | |
2537 | ||
9636f6db | 2538 | seq_printf(m, "Doorbell map:\n"); |
abddffdf | 2539 | seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); |
334636c6 | 2540 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline); |
9636f6db | 2541 | |
334636c6 CW |
2542 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client); |
2543 | i915_guc_client_info(m, dev_priv, guc->execbuf_client); | |
8b417c26 | 2544 | |
5aa1ee4b AG |
2545 | i915_guc_log_info(m, dev_priv); |
2546 | ||
8b417c26 DG |
2547 | /* Add more as required ... */ |
2548 | ||
2549 | return 0; | |
2550 | } | |
2551 | ||
a8b9370f | 2552 | static int i915_guc_stage_pool(struct seq_file *m, void *data) |
4c7e77fc | 2553 | { |
36cdd013 | 2554 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a8b9370f OM |
2555 | const struct intel_guc *guc = &dev_priv->guc; |
2556 | struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; | |
2557 | struct i915_guc_client *client = guc->execbuf_client; | |
2558 | unsigned int tmp; | |
2559 | int index; | |
4c7e77fc | 2560 | |
a8b9370f | 2561 | if (!check_guc_submission(m)) |
4c7e77fc AD |
2562 | return 0; |
2563 | ||
a8b9370f OM |
2564 | for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { |
2565 | struct intel_engine_cs *engine; | |
2566 | ||
2567 | if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)) | |
2568 | continue; | |
2569 | ||
2570 | seq_printf(m, "GuC stage descriptor %u:\n", index); | |
2571 | seq_printf(m, "\tIndex: %u\n", desc->stage_id); | |
2572 | seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); | |
2573 | seq_printf(m, "\tPriority: %d\n", desc->priority); | |
2574 | seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); | |
2575 | seq_printf(m, "\tEngines used: 0x%x\n", | |
2576 | desc->engines_used); | |
2577 | seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", | |
2578 | desc->db_trigger_phy, | |
2579 | desc->db_trigger_cpu, | |
2580 | desc->db_trigger_uk); | |
2581 | seq_printf(m, "\tProcess descriptor: 0x%x\n", | |
2582 | desc->process_desc); | |
9a09485d | 2583 | seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", |
a8b9370f OM |
2584 | desc->wq_addr, desc->wq_size); |
2585 | seq_putc(m, '\n'); | |
2586 | ||
2587 | for_each_engine_masked(engine, dev_priv, client->engines, tmp) { | |
2588 | u32 guc_engine_id = engine->guc_id; | |
2589 | struct guc_execlist_context *lrc = | |
2590 | &desc->lrc[guc_engine_id]; | |
2591 | ||
2592 | seq_printf(m, "\t%s LRC:\n", engine->name); | |
2593 | seq_printf(m, "\t\tContext desc: 0x%x\n", | |
2594 | lrc->context_desc); | |
2595 | seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); | |
2596 | seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); | |
2597 | seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); | |
2598 | seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); | |
2599 | seq_putc(m, '\n'); | |
2600 | } | |
2601 | } | |
2602 | ||
2603 | return 0; | |
2604 | } | |
2605 | ||
4c7e77fc AD |
2606 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2607 | { | |
ac58d2ab DCS |
2608 | struct drm_info_node *node = m->private; |
2609 | struct drm_i915_private *dev_priv = node_to_i915(node); | |
2610 | bool dump_load_err = !!node->info_ent->data; | |
2611 | struct drm_i915_gem_object *obj = NULL; | |
2612 | u32 *log; | |
2613 | int i = 0; | |
4c7e77fc | 2614 | |
ac58d2ab DCS |
2615 | if (dump_load_err) |
2616 | obj = dev_priv->guc.load_err_log; | |
2617 | else if (dev_priv->guc.log.vma) | |
2618 | obj = dev_priv->guc.log.vma->obj; | |
4c7e77fc | 2619 | |
ac58d2ab DCS |
2620 | if (!obj) |
2621 | return 0; | |
4c7e77fc | 2622 | |
ac58d2ab DCS |
2623 | log = i915_gem_object_pin_map(obj, I915_MAP_WC); |
2624 | if (IS_ERR(log)) { | |
2625 | DRM_DEBUG("Failed to pin object\n"); | |
2626 | seq_puts(m, "(log data unaccessible)\n"); | |
2627 | return PTR_ERR(log); | |
4c7e77fc AD |
2628 | } |
2629 | ||
ac58d2ab DCS |
2630 | for (i = 0; i < obj->base.size / sizeof(u32); i += 4) |
2631 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2632 | *(log + i), *(log + i + 1), | |
2633 | *(log + i + 2), *(log + i + 3)); | |
2634 | ||
4c7e77fc AD |
2635 | seq_putc(m, '\n'); |
2636 | ||
ac58d2ab DCS |
2637 | i915_gem_object_unpin_map(obj); |
2638 | ||
4c7e77fc AD |
2639 | return 0; |
2640 | } | |
2641 | ||
685534ef SAK |
2642 | static int i915_guc_log_control_get(void *data, u64 *val) |
2643 | { | |
bcc36d8a | 2644 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2645 | |
2646 | if (!dev_priv->guc.log.vma) | |
2647 | return -EINVAL; | |
2648 | ||
4f044a88 | 2649 | *val = i915_modparams.guc_log_level; |
685534ef SAK |
2650 | |
2651 | return 0; | |
2652 | } | |
2653 | ||
2654 | static int i915_guc_log_control_set(void *data, u64 val) | |
2655 | { | |
bcc36d8a | 2656 | struct drm_i915_private *dev_priv = data; |
685534ef SAK |
2657 | int ret; |
2658 | ||
2659 | if (!dev_priv->guc.log.vma) | |
2660 | return -EINVAL; | |
2661 | ||
bcc36d8a | 2662 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2663 | if (ret) |
2664 | return ret; | |
2665 | ||
2666 | intel_runtime_pm_get(dev_priv); | |
2667 | ret = i915_guc_log_control(dev_priv, val); | |
2668 | intel_runtime_pm_put(dev_priv); | |
2669 | ||
bcc36d8a | 2670 | mutex_unlock(&dev_priv->drm.struct_mutex); |
685534ef SAK |
2671 | return ret; |
2672 | } | |
2673 | ||
2674 | DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, | |
2675 | i915_guc_log_control_get, i915_guc_log_control_set, | |
2676 | "%lld\n"); | |
2677 | ||
b86bef20 CW |
2678 | static const char *psr2_live_status(u32 val) |
2679 | { | |
2680 | static const char * const live_status[] = { | |
2681 | "IDLE", | |
2682 | "CAPTURE", | |
2683 | "CAPTURE_FS", | |
2684 | "SLEEP", | |
2685 | "BUFON_FW", | |
2686 | "ML_UP", | |
2687 | "SU_STANDBY", | |
2688 | "FAST_SLEEP", | |
2689 | "DEEP_SLEEP", | |
2690 | "BUF_ON", | |
2691 | "TG_ON" | |
2692 | }; | |
2693 | ||
2694 | val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT; | |
2695 | if (val < ARRAY_SIZE(live_status)) | |
2696 | return live_status[val]; | |
2697 | ||
2698 | return "unknown"; | |
2699 | } | |
2700 | ||
e91fd8c6 RV |
2701 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2702 | { | |
36cdd013 | 2703 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
a031d709 | 2704 | u32 psrperf = 0; |
a6cbdb8e RV |
2705 | u32 stat[3]; |
2706 | enum pipe pipe; | |
a031d709 | 2707 | bool enabled = false; |
e91fd8c6 | 2708 | |
36cdd013 | 2709 | if (!HAS_PSR(dev_priv)) { |
3553a8ea DL |
2710 | seq_puts(m, "PSR not supported\n"); |
2711 | return 0; | |
2712 | } | |
2713 | ||
c8c8fb33 PZ |
2714 | intel_runtime_pm_get(dev_priv); |
2715 | ||
fa128fa6 | 2716 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2717 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2718 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2719 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2720 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2721 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2722 | dev_priv->psr.busy_frontbuffer_bits); | |
2723 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2724 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2725 | |
7e3eb599 NV |
2726 | if (HAS_DDI(dev_priv)) { |
2727 | if (dev_priv->psr.psr2_support) | |
2728 | enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; | |
2729 | else | |
2730 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; | |
2731 | } else { | |
3553a8ea | 2732 | for_each_pipe(dev_priv, pipe) { |
9c870d03 CW |
2733 | enum transcoder cpu_transcoder = |
2734 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
2735 | enum intel_display_power_domain power_domain; | |
2736 | ||
2737 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
2738 | if (!intel_display_power_get_if_enabled(dev_priv, | |
2739 | power_domain)) | |
2740 | continue; | |
2741 | ||
3553a8ea DL |
2742 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
2743 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2744 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2745 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2746 | enabled = true; | |
9c870d03 CW |
2747 | |
2748 | intel_display_power_put(dev_priv, power_domain); | |
a6cbdb8e RV |
2749 | } |
2750 | } | |
60e5ffe3 RV |
2751 | |
2752 | seq_printf(m, "Main link in standby mode: %s\n", | |
2753 | yesno(dev_priv->psr.link_standby)); | |
2754 | ||
a6cbdb8e RV |
2755 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2756 | ||
36cdd013 | 2757 | if (!HAS_DDI(dev_priv)) |
a6cbdb8e RV |
2758 | for_each_pipe(dev_priv, pipe) { |
2759 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2760 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2761 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2762 | } | |
2763 | seq_puts(m, "\n"); | |
e91fd8c6 | 2764 | |
05eec3c2 RV |
2765 | /* |
2766 | * VLV/CHV PSR has no kind of performance counter | |
2767 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2768 | */ | |
36cdd013 | 2769 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
443a389f | 2770 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2771 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2772 | |
2773 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2774 | } | |
6ba1f9e1 | 2775 | if (dev_priv->psr.psr2_support) { |
b86bef20 CW |
2776 | u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL); |
2777 | ||
2778 | seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n", | |
2779 | psr2, psr2_live_status(psr2)); | |
6ba1f9e1 | 2780 | } |
fa128fa6 | 2781 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2782 | |
c8c8fb33 | 2783 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2784 | return 0; |
2785 | } | |
2786 | ||
d2e216d0 RV |
2787 | static int i915_sink_crc(struct seq_file *m, void *data) |
2788 | { | |
36cdd013 DW |
2789 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2790 | struct drm_device *dev = &dev_priv->drm; | |
d2e216d0 | 2791 | struct intel_connector *connector; |
3f6a5e1e | 2792 | struct drm_connector_list_iter conn_iter; |
d2e216d0 RV |
2793 | struct intel_dp *intel_dp = NULL; |
2794 | int ret; | |
2795 | u8 crc[6]; | |
2796 | ||
2797 | drm_modeset_lock_all(dev); | |
3f6a5e1e DV |
2798 | drm_connector_list_iter_begin(dev, &conn_iter); |
2799 | for_each_intel_connector_iter(connector, &conn_iter) { | |
26c17cf6 | 2800 | struct drm_crtc *crtc; |
d2e216d0 | 2801 | |
26c17cf6 | 2802 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2803 | continue; |
2804 | ||
26c17cf6 ML |
2805 | crtc = connector->base.state->crtc; |
2806 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2807 | continue; |
2808 | ||
26c17cf6 | 2809 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2810 | continue; |
2811 | ||
26c17cf6 | 2812 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2813 | |
2814 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2815 | if (ret) | |
2816 | goto out; | |
2817 | ||
2818 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2819 | crc[0], crc[1], crc[2], | |
2820 | crc[3], crc[4], crc[5]); | |
2821 | goto out; | |
2822 | } | |
2823 | ret = -ENODEV; | |
2824 | out: | |
3f6a5e1e | 2825 | drm_connector_list_iter_end(&conn_iter); |
d2e216d0 RV |
2826 | drm_modeset_unlock_all(dev); |
2827 | return ret; | |
2828 | } | |
2829 | ||
ec013e7f JB |
2830 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2831 | { | |
36cdd013 | 2832 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
d38014ea | 2833 | unsigned long long power; |
ec013e7f JB |
2834 | u32 units; |
2835 | ||
36cdd013 | 2836 | if (INTEL_GEN(dev_priv) < 6) |
ec013e7f JB |
2837 | return -ENODEV; |
2838 | ||
36623ef8 PZ |
2839 | intel_runtime_pm_get(dev_priv); |
2840 | ||
d38014ea GKB |
2841 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { |
2842 | intel_runtime_pm_put(dev_priv); | |
2843 | return -ENODEV; | |
2844 | } | |
2845 | ||
2846 | units = (power & 0x1f00) >> 8; | |
ec013e7f | 2847 | power = I915_READ(MCH_SECP_NRG_STTS); |
d38014ea | 2848 | power = (1000000 * power) >> units; /* convert to uJ */ |
ec013e7f | 2849 | |
36623ef8 PZ |
2850 | intel_runtime_pm_put(dev_priv); |
2851 | ||
d38014ea | 2852 | seq_printf(m, "%llu", power); |
371db66a PZ |
2853 | |
2854 | return 0; | |
2855 | } | |
2856 | ||
6455c870 | 2857 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2858 | { |
36cdd013 | 2859 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
52a05c30 | 2860 | struct pci_dev *pdev = dev_priv->drm.pdev; |
371db66a | 2861 | |
a156e64d CW |
2862 | if (!HAS_RUNTIME_PM(dev_priv)) |
2863 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2864 | |
67d97da3 | 2865 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2866 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2867 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2868 | #ifdef CONFIG_PM |
a6aaec8b | 2869 | seq_printf(m, "Usage count: %d\n", |
36cdd013 | 2870 | atomic_read(&dev_priv->drm.dev->power.usage_count)); |
0d804184 CW |
2871 | #else |
2872 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2873 | #endif | |
a156e64d | 2874 | seq_printf(m, "PCI device power state: %s [%d]\n", |
52a05c30 DW |
2875 | pci_power_name(pdev->current_state), |
2876 | pdev->current_state); | |
371db66a | 2877 | |
ec013e7f JB |
2878 | return 0; |
2879 | } | |
2880 | ||
1da51581 ID |
2881 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2882 | { | |
36cdd013 | 2883 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
1da51581 ID |
2884 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2885 | int i; | |
2886 | ||
2887 | mutex_lock(&power_domains->lock); | |
2888 | ||
2889 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2890 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2891 | struct i915_power_well *power_well; | |
2892 | enum intel_display_power_domain power_domain; | |
2893 | ||
2894 | power_well = &power_domains->power_wells[i]; | |
2895 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2896 | power_well->count); | |
2897 | ||
8385c2ec | 2898 | for_each_power_domain(power_domain, power_well->domains) |
1da51581 | 2899 | seq_printf(m, " %-23s %d\n", |
9895ad03 | 2900 | intel_display_power_domain_str(power_domain), |
1da51581 | 2901 | power_domains->domain_use_count[power_domain]); |
1da51581 ID |
2902 | } |
2903 | ||
2904 | mutex_unlock(&power_domains->lock); | |
2905 | ||
2906 | return 0; | |
2907 | } | |
2908 | ||
b7cec66d DL |
2909 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2910 | { | |
36cdd013 | 2911 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
b7cec66d DL |
2912 | struct intel_csr *csr; |
2913 | ||
36cdd013 | 2914 | if (!HAS_CSR(dev_priv)) { |
b7cec66d DL |
2915 | seq_puts(m, "not supported\n"); |
2916 | return 0; | |
2917 | } | |
2918 | ||
2919 | csr = &dev_priv->csr; | |
2920 | ||
6fb403de MK |
2921 | intel_runtime_pm_get(dev_priv); |
2922 | ||
b7cec66d DL |
2923 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2924 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2925 | ||
2926 | if (!csr->dmc_payload) | |
6fb403de | 2927 | goto out; |
b7cec66d DL |
2928 | |
2929 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2930 | CSR_VERSION_MINOR(csr->version)); | |
2931 | ||
48de568c MK |
2932 | if (IS_KABYLAKE(dev_priv) || |
2933 | (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) { | |
8337206d DL |
2934 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2935 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2936 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2937 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
36cdd013 | 2938 | } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { |
16e11b99 MK |
2939 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
2940 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2941 | } |
2942 | ||
6fb403de MK |
2943 | out: |
2944 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2945 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2946 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2947 | ||
8337206d DL |
2948 | intel_runtime_pm_put(dev_priv); |
2949 | ||
b7cec66d DL |
2950 | return 0; |
2951 | } | |
2952 | ||
53f5e3ca JB |
2953 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2954 | struct drm_display_mode *mode) | |
2955 | { | |
2956 | int i; | |
2957 | ||
2958 | for (i = 0; i < tabs; i++) | |
2959 | seq_putc(m, '\t'); | |
2960 | ||
2961 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2962 | mode->base.id, mode->name, | |
2963 | mode->vrefresh, mode->clock, | |
2964 | mode->hdisplay, mode->hsync_start, | |
2965 | mode->hsync_end, mode->htotal, | |
2966 | mode->vdisplay, mode->vsync_start, | |
2967 | mode->vsync_end, mode->vtotal, | |
2968 | mode->type, mode->flags); | |
2969 | } | |
2970 | ||
2971 | static void intel_encoder_info(struct seq_file *m, | |
2972 | struct intel_crtc *intel_crtc, | |
2973 | struct intel_encoder *intel_encoder) | |
2974 | { | |
36cdd013 DW |
2975 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
2976 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
2977 | struct drm_crtc *crtc = &intel_crtc->base; |
2978 | struct intel_connector *intel_connector; | |
2979 | struct drm_encoder *encoder; | |
2980 | ||
2981 | encoder = &intel_encoder->base; | |
2982 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2983 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2984 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2985 | struct drm_connector *connector = &intel_connector->base; | |
2986 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2987 | connector->base.id, | |
c23cc417 | 2988 | connector->name, |
53f5e3ca JB |
2989 | drm_get_connector_status_name(connector->status)); |
2990 | if (connector->status == connector_status_connected) { | |
2991 | struct drm_display_mode *mode = &crtc->mode; | |
2992 | seq_printf(m, ", mode:\n"); | |
2993 | intel_seq_print_mode(m, 2, mode); | |
2994 | } else { | |
2995 | seq_putc(m, '\n'); | |
2996 | } | |
2997 | } | |
2998 | } | |
2999 | ||
3000 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3001 | { | |
36cdd013 DW |
3002 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3003 | struct drm_device *dev = &dev_priv->drm; | |
53f5e3ca JB |
3004 | struct drm_crtc *crtc = &intel_crtc->base; |
3005 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
3006 | struct drm_plane_state *plane_state = crtc->primary->state; |
3007 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 3008 | |
23a48d53 | 3009 | if (fb) |
5aa8a937 | 3010 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
3011 | fb->base.id, plane_state->src_x >> 16, |
3012 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
3013 | else |
3014 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
3015 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
3016 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
3017 | } | |
3018 | ||
3019 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
3020 | { | |
3021 | struct drm_display_mode *mode = panel->fixed_mode; | |
3022 | ||
3023 | seq_printf(m, "\tfixed mode:\n"); | |
3024 | intel_seq_print_mode(m, 2, mode); | |
3025 | } | |
3026 | ||
3027 | static void intel_dp_info(struct seq_file *m, | |
3028 | struct intel_connector *intel_connector) | |
3029 | { | |
3030 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
3031 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
3032 | ||
3033 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 3034 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 3035 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca | 3036 | intel_panel_info(m, &intel_connector->panel); |
80209e5f MK |
3037 | |
3038 | drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, | |
3039 | &intel_dp->aux); | |
53f5e3ca JB |
3040 | } |
3041 | ||
9a148a96 LY |
3042 | static void intel_dp_mst_info(struct seq_file *m, |
3043 | struct intel_connector *intel_connector) | |
3044 | { | |
3045 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
3046 | struct intel_dp_mst_encoder *intel_mst = | |
3047 | enc_to_mst(&intel_encoder->base); | |
3048 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
3049 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3050 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
3051 | intel_connector->port); | |
3052 | ||
3053 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
3054 | } | |
3055 | ||
53f5e3ca JB |
3056 | static void intel_hdmi_info(struct seq_file *m, |
3057 | struct intel_connector *intel_connector) | |
3058 | { | |
3059 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
3060 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
3061 | ||
742f491d | 3062 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
3063 | } |
3064 | ||
3065 | static void intel_lvds_info(struct seq_file *m, | |
3066 | struct intel_connector *intel_connector) | |
3067 | { | |
3068 | intel_panel_info(m, &intel_connector->panel); | |
3069 | } | |
3070 | ||
3071 | static void intel_connector_info(struct seq_file *m, | |
3072 | struct drm_connector *connector) | |
3073 | { | |
3074 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3075 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 3076 | struct drm_display_mode *mode; |
53f5e3ca JB |
3077 | |
3078 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 3079 | connector->base.id, connector->name, |
53f5e3ca JB |
3080 | drm_get_connector_status_name(connector->status)); |
3081 | if (connector->status == connector_status_connected) { | |
3082 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
3083 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
3084 | connector->display_info.width_mm, | |
3085 | connector->display_info.height_mm); | |
3086 | seq_printf(m, "\tsubpixel order: %s\n", | |
3087 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
3088 | seq_printf(m, "\tCEA rev: %d\n", | |
3089 | connector->display_info.cea_rev); | |
3090 | } | |
ee648a74 | 3091 | |
77d1f615 | 3092 | if (!intel_encoder) |
ee648a74 ML |
3093 | return; |
3094 | ||
3095 | switch (connector->connector_type) { | |
3096 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3097 | case DRM_MODE_CONNECTOR_eDP: | |
9a148a96 LY |
3098 | if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
3099 | intel_dp_mst_info(m, intel_connector); | |
3100 | else | |
3101 | intel_dp_info(m, intel_connector); | |
ee648a74 ML |
3102 | break; |
3103 | case DRM_MODE_CONNECTOR_LVDS: | |
3104 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 3105 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
3106 | break; |
3107 | case DRM_MODE_CONNECTOR_HDMIA: | |
3108 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
3109 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
3110 | intel_hdmi_info(m, intel_connector); | |
3111 | break; | |
3112 | default: | |
3113 | break; | |
36cd7444 | 3114 | } |
53f5e3ca | 3115 | |
f103fc7d JB |
3116 | seq_printf(m, "\tmodes:\n"); |
3117 | list_for_each_entry(mode, &connector->modes, head) | |
3118 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3119 | } |
3120 | ||
3abc4e09 RF |
3121 | static const char *plane_type(enum drm_plane_type type) |
3122 | { | |
3123 | switch (type) { | |
3124 | case DRM_PLANE_TYPE_OVERLAY: | |
3125 | return "OVL"; | |
3126 | case DRM_PLANE_TYPE_PRIMARY: | |
3127 | return "PRI"; | |
3128 | case DRM_PLANE_TYPE_CURSOR: | |
3129 | return "CUR"; | |
3130 | /* | |
3131 | * Deliberately omitting default: to generate compiler warnings | |
3132 | * when a new drm_plane_type gets added. | |
3133 | */ | |
3134 | } | |
3135 | ||
3136 | return "unknown"; | |
3137 | } | |
3138 | ||
3139 | static const char *plane_rotation(unsigned int rotation) | |
3140 | { | |
3141 | static char buf[48]; | |
3142 | /* | |
c2c446ad | 3143 | * According to doc only one DRM_MODE_ROTATE_ is allowed but this |
3abc4e09 RF |
3144 | * will print them all to visualize if the values are misused |
3145 | */ | |
3146 | snprintf(buf, sizeof(buf), | |
3147 | "%s%s%s%s%s%s(0x%08x)", | |
c2c446ad RF |
3148 | (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", |
3149 | (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", | |
3150 | (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", | |
3151 | (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", | |
3152 | (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", | |
3153 | (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3154 | rotation); |
3155 | ||
3156 | return buf; | |
3157 | } | |
3158 | ||
3159 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3160 | { | |
36cdd013 DW |
3161 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3162 | struct drm_device *dev = &dev_priv->drm; | |
3abc4e09 RF |
3163 | struct intel_plane *intel_plane; |
3164 | ||
3165 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3166 | struct drm_plane_state *state; | |
3167 | struct drm_plane *plane = &intel_plane->base; | |
b3c11ac2 | 3168 | struct drm_format_name_buf format_name; |
3abc4e09 RF |
3169 | |
3170 | if (!plane->state) { | |
3171 | seq_puts(m, "plane->state is NULL!\n"); | |
3172 | continue; | |
3173 | } | |
3174 | ||
3175 | state = plane->state; | |
3176 | ||
90844f00 | 3177 | if (state->fb) { |
438b74a5 VS |
3178 | drm_get_format_name(state->fb->format->format, |
3179 | &format_name); | |
90844f00 | 3180 | } else { |
b3c11ac2 | 3181 | sprintf(format_name.str, "N/A"); |
90844f00 EE |
3182 | } |
3183 | ||
3abc4e09 RF |
3184 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
3185 | plane->base.id, | |
3186 | plane_type(intel_plane->base.type), | |
3187 | state->crtc_x, state->crtc_y, | |
3188 | state->crtc_w, state->crtc_h, | |
3189 | (state->src_x >> 16), | |
3190 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3191 | (state->src_y >> 16), | |
3192 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3193 | (state->src_w >> 16), | |
3194 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3195 | (state->src_h >> 16), | |
3196 | ((state->src_h & 0xffff) * 15625) >> 10, | |
b3c11ac2 | 3197 | format_name.str, |
3abc4e09 RF |
3198 | plane_rotation(state->rotation)); |
3199 | } | |
3200 | } | |
3201 | ||
3202 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3203 | { | |
3204 | struct intel_crtc_state *pipe_config; | |
3205 | int num_scalers = intel_crtc->num_scalers; | |
3206 | int i; | |
3207 | ||
3208 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3209 | ||
3210 | /* Not all platformas have a scaler */ | |
3211 | if (num_scalers) { | |
3212 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3213 | num_scalers, | |
3214 | pipe_config->scaler_state.scaler_users, | |
3215 | pipe_config->scaler_state.scaler_id); | |
3216 | ||
58415918 | 3217 | for (i = 0; i < num_scalers; i++) { |
3abc4e09 RF |
3218 | struct intel_scaler *sc = |
3219 | &pipe_config->scaler_state.scalers[i]; | |
3220 | ||
3221 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3222 | i, yesno(sc->in_use), sc->mode); | |
3223 | } | |
3224 | seq_puts(m, "\n"); | |
3225 | } else { | |
3226 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3227 | } | |
3228 | } | |
3229 | ||
53f5e3ca JB |
3230 | static int i915_display_info(struct seq_file *m, void *unused) |
3231 | { | |
36cdd013 DW |
3232 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3233 | struct drm_device *dev = &dev_priv->drm; | |
065f2ec2 | 3234 | struct intel_crtc *crtc; |
53f5e3ca | 3235 | struct drm_connector *connector; |
3f6a5e1e | 3236 | struct drm_connector_list_iter conn_iter; |
53f5e3ca | 3237 | |
b0e5ddf3 | 3238 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3239 | seq_printf(m, "CRTC info\n"); |
3240 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3241 | for_each_intel_crtc(dev, crtc) { |
f77076c9 | 3242 | struct intel_crtc_state *pipe_config; |
53f5e3ca | 3243 | |
3f6a5e1e | 3244 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 ML |
3245 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3246 | ||
3abc4e09 | 3247 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3248 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3249 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3250 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3251 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3252 | ||
f77076c9 | 3253 | if (pipe_config->base.active) { |
cd5dcbf1 VS |
3254 | struct intel_plane *cursor = |
3255 | to_intel_plane(crtc->base.cursor); | |
3256 | ||
065f2ec2 CW |
3257 | intel_crtc_info(m, crtc); |
3258 | ||
cd5dcbf1 VS |
3259 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", |
3260 | yesno(cursor->base.state->visible), | |
3261 | cursor->base.state->crtc_x, | |
3262 | cursor->base.state->crtc_y, | |
3263 | cursor->base.state->crtc_w, | |
3264 | cursor->base.state->crtc_h, | |
3265 | cursor->cursor.base); | |
3abc4e09 RF |
3266 | intel_scaler_info(m, crtc); |
3267 | intel_plane_info(m, crtc); | |
a23dc658 | 3268 | } |
cace841c DV |
3269 | |
3270 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3271 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3272 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
3f6a5e1e | 3273 | drm_modeset_unlock(&crtc->base.mutex); |
53f5e3ca JB |
3274 | } |
3275 | ||
3276 | seq_printf(m, "\n"); | |
3277 | seq_printf(m, "Connector info\n"); | |
3278 | seq_printf(m, "--------------\n"); | |
3f6a5e1e DV |
3279 | mutex_lock(&dev->mode_config.mutex); |
3280 | drm_connector_list_iter_begin(dev, &conn_iter); | |
3281 | drm_for_each_connector_iter(connector, &conn_iter) | |
53f5e3ca | 3282 | intel_connector_info(m, connector); |
3f6a5e1e DV |
3283 | drm_connector_list_iter_end(&conn_iter); |
3284 | mutex_unlock(&dev->mode_config.mutex); | |
3285 | ||
b0e5ddf3 | 3286 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3287 | |
3288 | return 0; | |
3289 | } | |
3290 | ||
1b36595f CW |
3291 | static int i915_engine_info(struct seq_file *m, void *unused) |
3292 | { | |
3293 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
3294 | struct intel_engine_cs *engine; | |
3b3f1650 | 3295 | enum intel_engine_id id; |
f636edb2 | 3296 | struct drm_printer p; |
1b36595f | 3297 | |
9c870d03 CW |
3298 | intel_runtime_pm_get(dev_priv); |
3299 | ||
f73b5674 CW |
3300 | seq_printf(m, "GT awake? %s\n", |
3301 | yesno(dev_priv->gt.awake)); | |
3302 | seq_printf(m, "Global active requests: %d\n", | |
3303 | dev_priv->gt.active_requests); | |
3304 | ||
f636edb2 CW |
3305 | p = drm_seq_file_printer(m); |
3306 | for_each_engine(engine, dev_priv, id) | |
3307 | intel_engine_dump(engine, &p); | |
1b36595f | 3308 | |
9c870d03 CW |
3309 | intel_runtime_pm_put(dev_priv); |
3310 | ||
1b36595f CW |
3311 | return 0; |
3312 | } | |
3313 | ||
e04934cf BW |
3314 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3315 | { | |
36cdd013 DW |
3316 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3317 | struct drm_device *dev = &dev_priv->drm; | |
e2f80391 | 3318 | struct intel_engine_cs *engine; |
36cdd013 | 3319 | int num_rings = INTEL_INFO(dev_priv)->num_rings; |
c3232b18 DG |
3320 | enum intel_engine_id id; |
3321 | int j, ret; | |
e04934cf | 3322 | |
4f044a88 | 3323 | if (!i915_modparams.semaphores) { |
e04934cf BW |
3324 | seq_puts(m, "Semaphores are disabled\n"); |
3325 | return 0; | |
3326 | } | |
3327 | ||
3328 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3329 | if (ret) | |
3330 | return ret; | |
03872064 | 3331 | intel_runtime_pm_get(dev_priv); |
e04934cf | 3332 | |
36cdd013 | 3333 | if (IS_BROADWELL(dev_priv)) { |
e04934cf BW |
3334 | struct page *page; |
3335 | uint64_t *seqno; | |
3336 | ||
51d545d0 | 3337 | page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); |
e04934cf BW |
3338 | |
3339 | seqno = (uint64_t *)kmap_atomic(page); | |
3b3f1650 | 3340 | for_each_engine(engine, dev_priv, id) { |
e04934cf BW |
3341 | uint64_t offset; |
3342 | ||
e2f80391 | 3343 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3344 | |
3345 | seq_puts(m, " Last signal:"); | |
3346 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3347 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3348 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3349 | seqno[offset], offset * 8); | |
3350 | } | |
3351 | seq_putc(m, '\n'); | |
3352 | ||
3353 | seq_puts(m, " Last wait: "); | |
3354 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3355 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3356 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3357 | seqno[offset], offset * 8); | |
3358 | } | |
3359 | seq_putc(m, '\n'); | |
3360 | ||
3361 | } | |
3362 | kunmap_atomic(seqno); | |
3363 | } else { | |
3364 | seq_puts(m, " Last signal:"); | |
3b3f1650 | 3365 | for_each_engine(engine, dev_priv, id) |
e04934cf BW |
3366 | for (j = 0; j < num_rings; j++) |
3367 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3368 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3369 | seq_putc(m, '\n'); |
3370 | } | |
3371 | ||
03872064 | 3372 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3373 | mutex_unlock(&dev->struct_mutex); |
3374 | return 0; | |
3375 | } | |
3376 | ||
728e29d7 DV |
3377 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3378 | { | |
36cdd013 DW |
3379 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3380 | struct drm_device *dev = &dev_priv->drm; | |
728e29d7 DV |
3381 | int i; |
3382 | ||
3383 | drm_modeset_lock_all(dev); | |
3384 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3385 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3386 | ||
3387 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd | 3388 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
2c42e535 | 3389 | pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); |
728e29d7 | 3390 | seq_printf(m, " tracked hardware state:\n"); |
2c42e535 | 3391 | seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); |
3e369b76 | 3392 | seq_printf(m, " dpll_md: 0x%08x\n", |
2c42e535 ACO |
3393 | pll->state.hw_state.dpll_md); |
3394 | seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); | |
3395 | seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); | |
3396 | seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); | |
728e29d7 DV |
3397 | } |
3398 | drm_modeset_unlock_all(dev); | |
3399 | ||
3400 | return 0; | |
3401 | } | |
3402 | ||
1ed1ef9d | 3403 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3404 | { |
3405 | int i; | |
3406 | int ret; | |
e2f80391 | 3407 | struct intel_engine_cs *engine; |
36cdd013 DW |
3408 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3409 | struct drm_device *dev = &dev_priv->drm; | |
33136b06 | 3410 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3411 | enum intel_engine_id id; |
888b5995 | 3412 | |
888b5995 AS |
3413 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3414 | if (ret) | |
3415 | return ret; | |
3416 | ||
3417 | intel_runtime_pm_get(dev_priv); | |
3418 | ||
33136b06 | 3419 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
3b3f1650 | 3420 | for_each_engine(engine, dev_priv, id) |
33136b06 | 3421 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3422 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3423 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3424 | i915_reg_t addr; |
3425 | u32 mask, value, read; | |
2fa60f6d | 3426 | bool ok; |
888b5995 | 3427 | |
33136b06 AS |
3428 | addr = workarounds->reg[i].addr; |
3429 | mask = workarounds->reg[i].mask; | |
3430 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3431 | read = I915_READ(addr); |
3432 | ok = (value & mask) == (read & mask); | |
3433 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3434 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3435 | } |
3436 | ||
3437 | intel_runtime_pm_put(dev_priv); | |
3438 | mutex_unlock(&dev->struct_mutex); | |
3439 | ||
3440 | return 0; | |
3441 | } | |
3442 | ||
d2d4f39b KM |
3443 | static int i915_ipc_status_show(struct seq_file *m, void *data) |
3444 | { | |
3445 | struct drm_i915_private *dev_priv = m->private; | |
3446 | ||
3447 | seq_printf(m, "Isochronous Priority Control: %s\n", | |
3448 | yesno(dev_priv->ipc_enabled)); | |
3449 | return 0; | |
3450 | } | |
3451 | ||
3452 | static int i915_ipc_status_open(struct inode *inode, struct file *file) | |
3453 | { | |
3454 | struct drm_i915_private *dev_priv = inode->i_private; | |
3455 | ||
3456 | if (!HAS_IPC(dev_priv)) | |
3457 | return -ENODEV; | |
3458 | ||
3459 | return single_open(file, i915_ipc_status_show, dev_priv); | |
3460 | } | |
3461 | ||
3462 | static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, | |
3463 | size_t len, loff_t *offp) | |
3464 | { | |
3465 | struct seq_file *m = file->private_data; | |
3466 | struct drm_i915_private *dev_priv = m->private; | |
3467 | int ret; | |
3468 | bool enable; | |
3469 | ||
3470 | ret = kstrtobool_from_user(ubuf, len, &enable); | |
3471 | if (ret < 0) | |
3472 | return ret; | |
3473 | ||
3474 | intel_runtime_pm_get(dev_priv); | |
3475 | if (!dev_priv->ipc_enabled && enable) | |
3476 | DRM_INFO("Enabling IPC: WM will be proper only after next commit\n"); | |
3477 | dev_priv->wm.distrust_bios_wm = true; | |
3478 | dev_priv->ipc_enabled = enable; | |
3479 | intel_enable_ipc(dev_priv); | |
3480 | intel_runtime_pm_put(dev_priv); | |
3481 | ||
3482 | return len; | |
3483 | } | |
3484 | ||
3485 | static const struct file_operations i915_ipc_status_fops = { | |
3486 | .owner = THIS_MODULE, | |
3487 | .open = i915_ipc_status_open, | |
3488 | .read = seq_read, | |
3489 | .llseek = seq_lseek, | |
3490 | .release = single_release, | |
3491 | .write = i915_ipc_status_write | |
3492 | }; | |
3493 | ||
c5511e44 DL |
3494 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3495 | { | |
36cdd013 DW |
3496 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3497 | struct drm_device *dev = &dev_priv->drm; | |
c5511e44 DL |
3498 | struct skl_ddb_allocation *ddb; |
3499 | struct skl_ddb_entry *entry; | |
3500 | enum pipe pipe; | |
3501 | int plane; | |
3502 | ||
36cdd013 | 3503 | if (INTEL_GEN(dev_priv) < 9) |
2fcffe19 DL |
3504 | return 0; |
3505 | ||
c5511e44 DL |
3506 | drm_modeset_lock_all(dev); |
3507 | ||
3508 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3509 | ||
3510 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3511 | ||
3512 | for_each_pipe(dev_priv, pipe) { | |
3513 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3514 | ||
8b364b41 | 3515 | for_each_universal_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3516 | entry = &ddb->plane[pipe][plane]; |
3517 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3518 | entry->start, entry->end, | |
3519 | skl_ddb_entry_size(entry)); | |
3520 | } | |
3521 | ||
4969d33e | 3522 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3523 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3524 | entry->end, skl_ddb_entry_size(entry)); | |
3525 | } | |
3526 | ||
3527 | drm_modeset_unlock_all(dev); | |
3528 | ||
3529 | return 0; | |
3530 | } | |
3531 | ||
a54746e3 | 3532 | static void drrs_status_per_crtc(struct seq_file *m, |
36cdd013 DW |
3533 | struct drm_device *dev, |
3534 | struct intel_crtc *intel_crtc) | |
a54746e3 | 3535 | { |
fac5e23e | 3536 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3537 | struct i915_drrs *drrs = &dev_priv->drrs; |
3538 | int vrefresh = 0; | |
26875fe5 | 3539 | struct drm_connector *connector; |
3f6a5e1e | 3540 | struct drm_connector_list_iter conn_iter; |
a54746e3 | 3541 | |
3f6a5e1e DV |
3542 | drm_connector_list_iter_begin(dev, &conn_iter); |
3543 | drm_for_each_connector_iter(connector, &conn_iter) { | |
26875fe5 ML |
3544 | if (connector->state->crtc != &intel_crtc->base) |
3545 | continue; | |
3546 | ||
3547 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 | 3548 | } |
3f6a5e1e | 3549 | drm_connector_list_iter_end(&conn_iter); |
a54746e3 VK |
3550 | |
3551 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3552 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3553 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3554 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3555 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3556 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3557 | else | |
3558 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3559 | ||
3560 | seq_puts(m, "\n\n"); | |
3561 | ||
f77076c9 | 3562 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3563 | struct intel_panel *panel; |
3564 | ||
3565 | mutex_lock(&drrs->mutex); | |
3566 | /* DRRS Supported */ | |
3567 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3568 | ||
3569 | /* disable_drrs() will make drrs->dp NULL */ | |
3570 | if (!drrs->dp) { | |
3571 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3572 | mutex_unlock(&drrs->mutex); | |
3573 | return; | |
3574 | } | |
3575 | ||
3576 | panel = &drrs->dp->attached_connector->panel; | |
3577 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3578 | drrs->busy_frontbuffer_bits); | |
3579 | ||
3580 | seq_puts(m, "\n\t\t"); | |
3581 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3582 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3583 | vrefresh = panel->fixed_mode->vrefresh; | |
3584 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3585 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3586 | vrefresh = panel->downclock_mode->vrefresh; | |
3587 | } else { | |
3588 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3589 | drrs->refresh_rate_type); | |
3590 | mutex_unlock(&drrs->mutex); | |
3591 | return; | |
3592 | } | |
3593 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3594 | ||
3595 | seq_puts(m, "\n\t\t"); | |
3596 | mutex_unlock(&drrs->mutex); | |
3597 | } else { | |
3598 | /* DRRS not supported. Print the VBT parameter*/ | |
3599 | seq_puts(m, "\tDRRS Supported : No"); | |
3600 | } | |
3601 | seq_puts(m, "\n"); | |
3602 | } | |
3603 | ||
3604 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3605 | { | |
36cdd013 DW |
3606 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3607 | struct drm_device *dev = &dev_priv->drm; | |
a54746e3 VK |
3608 | struct intel_crtc *intel_crtc; |
3609 | int active_crtc_cnt = 0; | |
3610 | ||
26875fe5 | 3611 | drm_modeset_lock_all(dev); |
a54746e3 | 3612 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3613 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3614 | active_crtc_cnt++; |
3615 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3616 | ||
3617 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3618 | } | |
a54746e3 | 3619 | } |
26875fe5 | 3620 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3621 | |
3622 | if (!active_crtc_cnt) | |
3623 | seq_puts(m, "No active crtc found\n"); | |
3624 | ||
3625 | return 0; | |
3626 | } | |
3627 | ||
11bed958 DA |
3628 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3629 | { | |
36cdd013 DW |
3630 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
3631 | struct drm_device *dev = &dev_priv->drm; | |
11bed958 DA |
3632 | struct intel_encoder *intel_encoder; |
3633 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b | 3634 | struct drm_connector *connector; |
3f6a5e1e | 3635 | struct drm_connector_list_iter conn_iter; |
b6dabe3b | 3636 | |
3f6a5e1e DV |
3637 | drm_connector_list_iter_begin(dev, &conn_iter); |
3638 | drm_for_each_connector_iter(connector, &conn_iter) { | |
b6dabe3b | 3639 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
11bed958 | 3640 | continue; |
b6dabe3b ML |
3641 | |
3642 | intel_encoder = intel_attached_encoder(connector); | |
3643 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3644 | continue; | |
3645 | ||
3646 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3647 | if (!intel_dig_port->dp.can_mst) |
3648 | continue; | |
b6dabe3b | 3649 | |
40ae80cc JB |
3650 | seq_printf(m, "MST Source Port %c\n", |
3651 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3652 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3653 | } | |
3f6a5e1e DV |
3654 | drm_connector_list_iter_end(&conn_iter); |
3655 | ||
11bed958 DA |
3656 | return 0; |
3657 | } | |
3658 | ||
eb3394fa | 3659 | static ssize_t i915_displayport_test_active_write(struct file *file, |
36cdd013 DW |
3660 | const char __user *ubuf, |
3661 | size_t len, loff_t *offp) | |
eb3394fa TP |
3662 | { |
3663 | char *input_buffer; | |
3664 | int status = 0; | |
eb3394fa TP |
3665 | struct drm_device *dev; |
3666 | struct drm_connector *connector; | |
3f6a5e1e | 3667 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3668 | struct intel_dp *intel_dp; |
3669 | int val = 0; | |
3670 | ||
9aaffa34 | 3671 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 3672 | |
eb3394fa TP |
3673 | if (len == 0) |
3674 | return 0; | |
3675 | ||
261aeba8 GT |
3676 | input_buffer = memdup_user_nul(ubuf, len); |
3677 | if (IS_ERR(input_buffer)) | |
3678 | return PTR_ERR(input_buffer); | |
eb3394fa | 3679 | |
eb3394fa TP |
3680 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
3681 | ||
3f6a5e1e DV |
3682 | drm_connector_list_iter_begin(dev, &conn_iter); |
3683 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3684 | struct intel_encoder *encoder; |
3685 | ||
eb3394fa TP |
3686 | if (connector->connector_type != |
3687 | DRM_MODE_CONNECTOR_DisplayPort) | |
3688 | continue; | |
3689 | ||
a874b6a3 ML |
3690 | encoder = to_intel_encoder(connector->encoder); |
3691 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3692 | continue; | |
3693 | ||
3694 | if (encoder && connector->status == connector_status_connected) { | |
3695 | intel_dp = enc_to_intel_dp(&encoder->base); | |
eb3394fa TP |
3696 | status = kstrtoint(input_buffer, 10, &val); |
3697 | if (status < 0) | |
3f6a5e1e | 3698 | break; |
eb3394fa TP |
3699 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
3700 | /* To prevent erroneous activation of the compliance | |
3701 | * testing code, only accept an actual value of 1 here | |
3702 | */ | |
3703 | if (val == 1) | |
c1617abc | 3704 | intel_dp->compliance.test_active = 1; |
eb3394fa | 3705 | else |
c1617abc | 3706 | intel_dp->compliance.test_active = 0; |
eb3394fa TP |
3707 | } |
3708 | } | |
3f6a5e1e | 3709 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3710 | kfree(input_buffer); |
3711 | if (status < 0) | |
3712 | return status; | |
3713 | ||
3714 | *offp += len; | |
3715 | return len; | |
3716 | } | |
3717 | ||
3718 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
3719 | { | |
3720 | struct drm_device *dev = m->private; | |
3721 | struct drm_connector *connector; | |
3f6a5e1e | 3722 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3723 | struct intel_dp *intel_dp; |
3724 | ||
3f6a5e1e DV |
3725 | drm_connector_list_iter_begin(dev, &conn_iter); |
3726 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3727 | struct intel_encoder *encoder; |
3728 | ||
eb3394fa TP |
3729 | if (connector->connector_type != |
3730 | DRM_MODE_CONNECTOR_DisplayPort) | |
3731 | continue; | |
3732 | ||
a874b6a3 ML |
3733 | encoder = to_intel_encoder(connector->encoder); |
3734 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3735 | continue; | |
3736 | ||
3737 | if (encoder && connector->status == connector_status_connected) { | |
3738 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3739 | if (intel_dp->compliance.test_active) |
eb3394fa TP |
3740 | seq_puts(m, "1"); |
3741 | else | |
3742 | seq_puts(m, "0"); | |
3743 | } else | |
3744 | seq_puts(m, "0"); | |
3745 | } | |
3f6a5e1e | 3746 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3747 | |
3748 | return 0; | |
3749 | } | |
3750 | ||
3751 | static int i915_displayport_test_active_open(struct inode *inode, | |
36cdd013 | 3752 | struct file *file) |
eb3394fa | 3753 | { |
36cdd013 | 3754 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3755 | |
36cdd013 DW |
3756 | return single_open(file, i915_displayport_test_active_show, |
3757 | &dev_priv->drm); | |
eb3394fa TP |
3758 | } |
3759 | ||
3760 | static const struct file_operations i915_displayport_test_active_fops = { | |
3761 | .owner = THIS_MODULE, | |
3762 | .open = i915_displayport_test_active_open, | |
3763 | .read = seq_read, | |
3764 | .llseek = seq_lseek, | |
3765 | .release = single_release, | |
3766 | .write = i915_displayport_test_active_write | |
3767 | }; | |
3768 | ||
3769 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
3770 | { | |
3771 | struct drm_device *dev = m->private; | |
3772 | struct drm_connector *connector; | |
3f6a5e1e | 3773 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3774 | struct intel_dp *intel_dp; |
3775 | ||
3f6a5e1e DV |
3776 | drm_connector_list_iter_begin(dev, &conn_iter); |
3777 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3778 | struct intel_encoder *encoder; |
3779 | ||
eb3394fa TP |
3780 | if (connector->connector_type != |
3781 | DRM_MODE_CONNECTOR_DisplayPort) | |
3782 | continue; | |
3783 | ||
a874b6a3 ML |
3784 | encoder = to_intel_encoder(connector->encoder); |
3785 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3786 | continue; | |
3787 | ||
3788 | if (encoder && connector->status == connector_status_connected) { | |
3789 | intel_dp = enc_to_intel_dp(&encoder->base); | |
b48a5ba9 MN |
3790 | if (intel_dp->compliance.test_type == |
3791 | DP_TEST_LINK_EDID_READ) | |
3792 | seq_printf(m, "%lx", | |
3793 | intel_dp->compliance.test_data.edid); | |
611032bf MN |
3794 | else if (intel_dp->compliance.test_type == |
3795 | DP_TEST_LINK_VIDEO_PATTERN) { | |
3796 | seq_printf(m, "hdisplay: %d\n", | |
3797 | intel_dp->compliance.test_data.hdisplay); | |
3798 | seq_printf(m, "vdisplay: %d\n", | |
3799 | intel_dp->compliance.test_data.vdisplay); | |
3800 | seq_printf(m, "bpc: %u\n", | |
3801 | intel_dp->compliance.test_data.bpc); | |
3802 | } | |
eb3394fa TP |
3803 | } else |
3804 | seq_puts(m, "0"); | |
3805 | } | |
3f6a5e1e | 3806 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3807 | |
3808 | return 0; | |
3809 | } | |
3810 | static int i915_displayport_test_data_open(struct inode *inode, | |
36cdd013 | 3811 | struct file *file) |
eb3394fa | 3812 | { |
36cdd013 | 3813 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3814 | |
36cdd013 DW |
3815 | return single_open(file, i915_displayport_test_data_show, |
3816 | &dev_priv->drm); | |
eb3394fa TP |
3817 | } |
3818 | ||
3819 | static const struct file_operations i915_displayport_test_data_fops = { | |
3820 | .owner = THIS_MODULE, | |
3821 | .open = i915_displayport_test_data_open, | |
3822 | .read = seq_read, | |
3823 | .llseek = seq_lseek, | |
3824 | .release = single_release | |
3825 | }; | |
3826 | ||
3827 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
3828 | { | |
3829 | struct drm_device *dev = m->private; | |
3830 | struct drm_connector *connector; | |
3f6a5e1e | 3831 | struct drm_connector_list_iter conn_iter; |
eb3394fa TP |
3832 | struct intel_dp *intel_dp; |
3833 | ||
3f6a5e1e DV |
3834 | drm_connector_list_iter_begin(dev, &conn_iter); |
3835 | drm_for_each_connector_iter(connector, &conn_iter) { | |
a874b6a3 ML |
3836 | struct intel_encoder *encoder; |
3837 | ||
eb3394fa TP |
3838 | if (connector->connector_type != |
3839 | DRM_MODE_CONNECTOR_DisplayPort) | |
3840 | continue; | |
3841 | ||
a874b6a3 ML |
3842 | encoder = to_intel_encoder(connector->encoder); |
3843 | if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) | |
3844 | continue; | |
3845 | ||
3846 | if (encoder && connector->status == connector_status_connected) { | |
3847 | intel_dp = enc_to_intel_dp(&encoder->base); | |
c1617abc | 3848 | seq_printf(m, "%02lx", intel_dp->compliance.test_type); |
eb3394fa TP |
3849 | } else |
3850 | seq_puts(m, "0"); | |
3851 | } | |
3f6a5e1e | 3852 | drm_connector_list_iter_end(&conn_iter); |
eb3394fa TP |
3853 | |
3854 | return 0; | |
3855 | } | |
3856 | ||
3857 | static int i915_displayport_test_type_open(struct inode *inode, | |
3858 | struct file *file) | |
3859 | { | |
36cdd013 | 3860 | struct drm_i915_private *dev_priv = inode->i_private; |
eb3394fa | 3861 | |
36cdd013 DW |
3862 | return single_open(file, i915_displayport_test_type_show, |
3863 | &dev_priv->drm); | |
eb3394fa TP |
3864 | } |
3865 | ||
3866 | static const struct file_operations i915_displayport_test_type_fops = { | |
3867 | .owner = THIS_MODULE, | |
3868 | .open = i915_displayport_test_type_open, | |
3869 | .read = seq_read, | |
3870 | .llseek = seq_lseek, | |
3871 | .release = single_release | |
3872 | }; | |
3873 | ||
97e94b22 | 3874 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 | 3875 | { |
36cdd013 DW |
3876 | struct drm_i915_private *dev_priv = m->private; |
3877 | struct drm_device *dev = &dev_priv->drm; | |
369a1342 | 3878 | int level; |
de38b95c VS |
3879 | int num_levels; |
3880 | ||
36cdd013 | 3881 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 3882 | num_levels = 3; |
36cdd013 | 3883 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 3884 | num_levels = 1; |
04548cba VS |
3885 | else if (IS_G4X(dev_priv)) |
3886 | num_levels = 3; | |
de38b95c | 3887 | else |
5db94019 | 3888 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
369a1342 VS |
3889 | |
3890 | drm_modeset_lock_all(dev); | |
3891 | ||
3892 | for (level = 0; level < num_levels; level++) { | |
3893 | unsigned int latency = wm[level]; | |
3894 | ||
97e94b22 DL |
3895 | /* |
3896 | * - WM1+ latency values in 0.5us units | |
de38b95c | 3897 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 3898 | */ |
04548cba VS |
3899 | if (INTEL_GEN(dev_priv) >= 9 || |
3900 | IS_VALLEYVIEW(dev_priv) || | |
3901 | IS_CHERRYVIEW(dev_priv) || | |
3902 | IS_G4X(dev_priv)) | |
97e94b22 DL |
3903 | latency *= 10; |
3904 | else if (level > 0) | |
369a1342 VS |
3905 | latency *= 5; |
3906 | ||
3907 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3908 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3909 | } |
3910 | ||
3911 | drm_modeset_unlock_all(dev); | |
3912 | } | |
3913 | ||
3914 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3915 | { | |
36cdd013 | 3916 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3917 | const uint16_t *latencies; |
3918 | ||
36cdd013 | 3919 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3920 | latencies = dev_priv->wm.skl_latency; |
3921 | else | |
36cdd013 | 3922 | latencies = dev_priv->wm.pri_latency; |
369a1342 | 3923 | |
97e94b22 | 3924 | wm_latency_show(m, latencies); |
369a1342 VS |
3925 | |
3926 | return 0; | |
3927 | } | |
3928 | ||
3929 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3930 | { | |
36cdd013 | 3931 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3932 | const uint16_t *latencies; |
3933 | ||
36cdd013 | 3934 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3935 | latencies = dev_priv->wm.skl_latency; |
3936 | else | |
36cdd013 | 3937 | latencies = dev_priv->wm.spr_latency; |
369a1342 | 3938 | |
97e94b22 | 3939 | wm_latency_show(m, latencies); |
369a1342 VS |
3940 | |
3941 | return 0; | |
3942 | } | |
3943 | ||
3944 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3945 | { | |
36cdd013 | 3946 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
3947 | const uint16_t *latencies; |
3948 | ||
36cdd013 | 3949 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
3950 | latencies = dev_priv->wm.skl_latency; |
3951 | else | |
36cdd013 | 3952 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 3953 | |
97e94b22 | 3954 | wm_latency_show(m, latencies); |
369a1342 VS |
3955 | |
3956 | return 0; | |
3957 | } | |
3958 | ||
3959 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3960 | { | |
36cdd013 | 3961 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3962 | |
04548cba | 3963 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
369a1342 VS |
3964 | return -ENODEV; |
3965 | ||
36cdd013 | 3966 | return single_open(file, pri_wm_latency_show, dev_priv); |
369a1342 VS |
3967 | } |
3968 | ||
3969 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3970 | { | |
36cdd013 | 3971 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3972 | |
36cdd013 | 3973 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3974 | return -ENODEV; |
3975 | ||
36cdd013 | 3976 | return single_open(file, spr_wm_latency_show, dev_priv); |
369a1342 VS |
3977 | } |
3978 | ||
3979 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3980 | { | |
36cdd013 | 3981 | struct drm_i915_private *dev_priv = inode->i_private; |
369a1342 | 3982 | |
36cdd013 | 3983 | if (HAS_GMCH_DISPLAY(dev_priv)) |
369a1342 VS |
3984 | return -ENODEV; |
3985 | ||
36cdd013 | 3986 | return single_open(file, cur_wm_latency_show, dev_priv); |
369a1342 VS |
3987 | } |
3988 | ||
3989 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3990 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3991 | { |
3992 | struct seq_file *m = file->private_data; | |
36cdd013 DW |
3993 | struct drm_i915_private *dev_priv = m->private; |
3994 | struct drm_device *dev = &dev_priv->drm; | |
97e94b22 | 3995 | uint16_t new[8] = { 0 }; |
de38b95c | 3996 | int num_levels; |
369a1342 VS |
3997 | int level; |
3998 | int ret; | |
3999 | char tmp[32]; | |
4000 | ||
36cdd013 | 4001 | if (IS_CHERRYVIEW(dev_priv)) |
de38b95c | 4002 | num_levels = 3; |
36cdd013 | 4003 | else if (IS_VALLEYVIEW(dev_priv)) |
de38b95c | 4004 | num_levels = 1; |
04548cba VS |
4005 | else if (IS_G4X(dev_priv)) |
4006 | num_levels = 3; | |
de38b95c | 4007 | else |
5db94019 | 4008 | num_levels = ilk_wm_max_level(dev_priv) + 1; |
de38b95c | 4009 | |
369a1342 VS |
4010 | if (len >= sizeof(tmp)) |
4011 | return -EINVAL; | |
4012 | ||
4013 | if (copy_from_user(tmp, ubuf, len)) | |
4014 | return -EFAULT; | |
4015 | ||
4016 | tmp[len] = '\0'; | |
4017 | ||
97e94b22 DL |
4018 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4019 | &new[0], &new[1], &new[2], &new[3], | |
4020 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4021 | if (ret != num_levels) |
4022 | return -EINVAL; | |
4023 | ||
4024 | drm_modeset_lock_all(dev); | |
4025 | ||
4026 | for (level = 0; level < num_levels; level++) | |
4027 | wm[level] = new[level]; | |
4028 | ||
4029 | drm_modeset_unlock_all(dev); | |
4030 | ||
4031 | return len; | |
4032 | } | |
4033 | ||
4034 | ||
4035 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4036 | size_t len, loff_t *offp) | |
4037 | { | |
4038 | struct seq_file *m = file->private_data; | |
36cdd013 | 4039 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4040 | uint16_t *latencies; |
369a1342 | 4041 | |
36cdd013 | 4042 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4043 | latencies = dev_priv->wm.skl_latency; |
4044 | else | |
36cdd013 | 4045 | latencies = dev_priv->wm.pri_latency; |
97e94b22 DL |
4046 | |
4047 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4048 | } |
4049 | ||
4050 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4051 | size_t len, loff_t *offp) | |
4052 | { | |
4053 | struct seq_file *m = file->private_data; | |
36cdd013 | 4054 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 | 4055 | uint16_t *latencies; |
369a1342 | 4056 | |
36cdd013 | 4057 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4058 | latencies = dev_priv->wm.skl_latency; |
4059 | else | |
36cdd013 | 4060 | latencies = dev_priv->wm.spr_latency; |
97e94b22 DL |
4061 | |
4062 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4063 | } |
4064 | ||
4065 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4066 | size_t len, loff_t *offp) | |
4067 | { | |
4068 | struct seq_file *m = file->private_data; | |
36cdd013 | 4069 | struct drm_i915_private *dev_priv = m->private; |
97e94b22 DL |
4070 | uint16_t *latencies; |
4071 | ||
36cdd013 | 4072 | if (INTEL_GEN(dev_priv) >= 9) |
97e94b22 DL |
4073 | latencies = dev_priv->wm.skl_latency; |
4074 | else | |
36cdd013 | 4075 | latencies = dev_priv->wm.cur_latency; |
369a1342 | 4076 | |
97e94b22 | 4077 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4078 | } |
4079 | ||
4080 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4081 | .owner = THIS_MODULE, | |
4082 | .open = pri_wm_latency_open, | |
4083 | .read = seq_read, | |
4084 | .llseek = seq_lseek, | |
4085 | .release = single_release, | |
4086 | .write = pri_wm_latency_write | |
4087 | }; | |
4088 | ||
4089 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4090 | .owner = THIS_MODULE, | |
4091 | .open = spr_wm_latency_open, | |
4092 | .read = seq_read, | |
4093 | .llseek = seq_lseek, | |
4094 | .release = single_release, | |
4095 | .write = spr_wm_latency_write | |
4096 | }; | |
4097 | ||
4098 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4099 | .owner = THIS_MODULE, | |
4100 | .open = cur_wm_latency_open, | |
4101 | .read = seq_read, | |
4102 | .llseek = seq_lseek, | |
4103 | .release = single_release, | |
4104 | .write = cur_wm_latency_write | |
4105 | }; | |
4106 | ||
647416f9 KC |
4107 | static int |
4108 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4109 | { |
36cdd013 | 4110 | struct drm_i915_private *dev_priv = data; |
f3cd474b | 4111 | |
d98c52cf | 4112 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4113 | |
647416f9 | 4114 | return 0; |
f3cd474b CW |
4115 | } |
4116 | ||
647416f9 KC |
4117 | static int |
4118 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4119 | { |
598b6b5a CW |
4120 | struct drm_i915_private *i915 = data; |
4121 | struct intel_engine_cs *engine; | |
4122 | unsigned int tmp; | |
d46c0517 | 4123 | |
b8d24a06 MK |
4124 | /* |
4125 | * There is no safeguard against this debugfs entry colliding | |
4126 | * with the hangcheck calling same i915_handle_error() in | |
4127 | * parallel, causing an explosion. For now we assume that the | |
4128 | * test harness is responsible enough not to inject gpu hangs | |
4129 | * while it is writing to 'i915_wedged' | |
4130 | */ | |
4131 | ||
598b6b5a | 4132 | if (i915_reset_backoff(&i915->gpu_error)) |
b8d24a06 MK |
4133 | return -EAGAIN; |
4134 | ||
598b6b5a CW |
4135 | for_each_engine_masked(engine, i915, val, tmp) { |
4136 | engine->hangcheck.seqno = intel_engine_get_seqno(engine); | |
4137 | engine->hangcheck.stalled = true; | |
4138 | } | |
4139 | ||
4140 | i915_handle_error(i915, val, "Manually setting wedged to %llu", val); | |
d46c0517 | 4141 | |
598b6b5a | 4142 | wait_on_bit(&i915->gpu_error.flags, |
d3df42b7 CW |
4143 | I915_RESET_HANDOFF, |
4144 | TASK_UNINTERRUPTIBLE); | |
4145 | ||
647416f9 | 4146 | return 0; |
f3cd474b CW |
4147 | } |
4148 | ||
647416f9 KC |
4149 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4150 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4151 | "%llu\n"); |
f3cd474b | 4152 | |
64486ae7 CW |
4153 | static int |
4154 | fault_irq_set(struct drm_i915_private *i915, | |
4155 | unsigned long *irq, | |
4156 | unsigned long val) | |
4157 | { | |
4158 | int err; | |
4159 | ||
4160 | err = mutex_lock_interruptible(&i915->drm.struct_mutex); | |
4161 | if (err) | |
4162 | return err; | |
4163 | ||
4164 | err = i915_gem_wait_for_idle(i915, | |
4165 | I915_WAIT_LOCKED | | |
4166 | I915_WAIT_INTERRUPTIBLE); | |
4167 | if (err) | |
4168 | goto err_unlock; | |
4169 | ||
64486ae7 CW |
4170 | *irq = val; |
4171 | mutex_unlock(&i915->drm.struct_mutex); | |
4172 | ||
4173 | /* Flush idle worker to disarm irq */ | |
7c26240e | 4174 | drain_delayed_work(&i915->gt.idle_work); |
64486ae7 CW |
4175 | |
4176 | return 0; | |
4177 | ||
4178 | err_unlock: | |
4179 | mutex_unlock(&i915->drm.struct_mutex); | |
4180 | return err; | |
4181 | } | |
4182 | ||
094f9a54 CW |
4183 | static int |
4184 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4185 | { | |
36cdd013 | 4186 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4187 | |
4188 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4189 | return 0; | |
4190 | } | |
4191 | ||
4192 | static int | |
4193 | i915_ring_missed_irq_set(void *data, u64 val) | |
4194 | { | |
64486ae7 | 4195 | struct drm_i915_private *i915 = data; |
094f9a54 | 4196 | |
64486ae7 | 4197 | return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val); |
094f9a54 CW |
4198 | } |
4199 | ||
4200 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4201 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4202 | "0x%08llx\n"); | |
4203 | ||
4204 | static int | |
4205 | i915_ring_test_irq_get(void *data, u64 *val) | |
4206 | { | |
36cdd013 | 4207 | struct drm_i915_private *dev_priv = data; |
094f9a54 CW |
4208 | |
4209 | *val = dev_priv->gpu_error.test_irq_rings; | |
4210 | ||
4211 | return 0; | |
4212 | } | |
4213 | ||
4214 | static int | |
4215 | i915_ring_test_irq_set(void *data, u64 val) | |
4216 | { | |
64486ae7 | 4217 | struct drm_i915_private *i915 = data; |
094f9a54 | 4218 | |
64486ae7 | 4219 | val &= INTEL_INFO(i915)->ring_mask; |
094f9a54 | 4220 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4221 | |
64486ae7 | 4222 | return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val); |
094f9a54 CW |
4223 | } |
4224 | ||
4225 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4226 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4227 | "0x%08llx\n"); | |
4228 | ||
dd624afd CW |
4229 | #define DROP_UNBOUND 0x1 |
4230 | #define DROP_BOUND 0x2 | |
4231 | #define DROP_RETIRE 0x4 | |
4232 | #define DROP_ACTIVE 0x8 | |
fbbd37b3 | 4233 | #define DROP_FREED 0x10 |
8eadc19b | 4234 | #define DROP_SHRINK_ALL 0x20 |
fbbd37b3 CW |
4235 | #define DROP_ALL (DROP_UNBOUND | \ |
4236 | DROP_BOUND | \ | |
4237 | DROP_RETIRE | \ | |
4238 | DROP_ACTIVE | \ | |
8eadc19b CW |
4239 | DROP_FREED | \ |
4240 | DROP_SHRINK_ALL) | |
647416f9 KC |
4241 | static int |
4242 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4243 | { |
647416f9 | 4244 | *val = DROP_ALL; |
dd624afd | 4245 | |
647416f9 | 4246 | return 0; |
dd624afd CW |
4247 | } |
4248 | ||
647416f9 KC |
4249 | static int |
4250 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4251 | { |
36cdd013 DW |
4252 | struct drm_i915_private *dev_priv = data; |
4253 | struct drm_device *dev = &dev_priv->drm; | |
00c26cf9 | 4254 | int ret = 0; |
dd624afd | 4255 | |
2f9fe5ff | 4256 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4257 | |
4258 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4259 | * on ioctls on -EAGAIN. */ | |
00c26cf9 CW |
4260 | if (val & (DROP_ACTIVE | DROP_RETIRE)) { |
4261 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
dd624afd | 4262 | if (ret) |
00c26cf9 | 4263 | return ret; |
dd624afd | 4264 | |
00c26cf9 CW |
4265 | if (val & DROP_ACTIVE) |
4266 | ret = i915_gem_wait_for_idle(dev_priv, | |
4267 | I915_WAIT_INTERRUPTIBLE | | |
4268 | I915_WAIT_LOCKED); | |
4269 | ||
4270 | if (val & DROP_RETIRE) | |
4271 | i915_gem_retire_requests(dev_priv); | |
4272 | ||
4273 | mutex_unlock(&dev->struct_mutex); | |
4274 | } | |
dd624afd | 4275 | |
d92a8cfc | 4276 | fs_reclaim_acquire(GFP_KERNEL); |
21ab4e74 | 4277 | if (val & DROP_BOUND) |
912d572d | 4278 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND); |
4ad72b7f | 4279 | |
21ab4e74 | 4280 | if (val & DROP_UNBOUND) |
912d572d | 4281 | i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND); |
dd624afd | 4282 | |
8eadc19b CW |
4283 | if (val & DROP_SHRINK_ALL) |
4284 | i915_gem_shrink_all(dev_priv); | |
d92a8cfc | 4285 | fs_reclaim_release(GFP_KERNEL); |
8eadc19b | 4286 | |
fbbd37b3 CW |
4287 | if (val & DROP_FREED) { |
4288 | synchronize_rcu(); | |
bdeb9785 | 4289 | i915_gem_drain_freed_objects(dev_priv); |
fbbd37b3 CW |
4290 | } |
4291 | ||
647416f9 | 4292 | return ret; |
dd624afd CW |
4293 | } |
4294 | ||
647416f9 KC |
4295 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4296 | i915_drop_caches_get, i915_drop_caches_set, | |
4297 | "0x%08llx\n"); | |
dd624afd | 4298 | |
647416f9 KC |
4299 | static int |
4300 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4301 | { |
36cdd013 | 4302 | struct drm_i915_private *dev_priv = data; |
004777cb | 4303 | |
36cdd013 | 4304 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4305 | return -ENODEV; |
4306 | ||
7c59a9c1 | 4307 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4308 | return 0; |
358733e9 JB |
4309 | } |
4310 | ||
647416f9 KC |
4311 | static int |
4312 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4313 | { |
36cdd013 | 4314 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4315 | u32 hw_max, hw_min; |
647416f9 | 4316 | int ret; |
004777cb | 4317 | |
36cdd013 | 4318 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4319 | return -ENODEV; |
358733e9 | 4320 | |
647416f9 | 4321 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4322 | |
4fc688ce | 4323 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4324 | if (ret) |
4325 | return ret; | |
4326 | ||
358733e9 JB |
4327 | /* |
4328 | * Turbo will still be enabled, but won't go above the set value. | |
4329 | */ | |
bc4d91f6 | 4330 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4331 | |
bc4d91f6 AG |
4332 | hw_max = dev_priv->rps.max_freq; |
4333 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4334 | |
b39fb297 | 4335 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4336 | mutex_unlock(&dev_priv->rps.hw_lock); |
4337 | return -EINVAL; | |
0a073b84 JB |
4338 | } |
4339 | ||
b39fb297 | 4340 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4341 | |
9fcee2f7 CW |
4342 | if (intel_set_rps(dev_priv, val)) |
4343 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4344 | |
4fc688ce | 4345 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4346 | |
647416f9 | 4347 | return 0; |
358733e9 JB |
4348 | } |
4349 | ||
647416f9 KC |
4350 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4351 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4352 | "%llu\n"); |
358733e9 | 4353 | |
647416f9 KC |
4354 | static int |
4355 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4356 | { |
36cdd013 | 4357 | struct drm_i915_private *dev_priv = data; |
004777cb | 4358 | |
62e1baa1 | 4359 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4360 | return -ENODEV; |
4361 | ||
7c59a9c1 | 4362 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4363 | return 0; |
1523c310 JB |
4364 | } |
4365 | ||
647416f9 KC |
4366 | static int |
4367 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4368 | { |
36cdd013 | 4369 | struct drm_i915_private *dev_priv = data; |
bc4d91f6 | 4370 | u32 hw_max, hw_min; |
647416f9 | 4371 | int ret; |
004777cb | 4372 | |
62e1baa1 | 4373 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4374 | return -ENODEV; |
1523c310 | 4375 | |
647416f9 | 4376 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4377 | |
4fc688ce | 4378 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4379 | if (ret) |
4380 | return ret; | |
4381 | ||
1523c310 JB |
4382 | /* |
4383 | * Turbo will still be enabled, but won't go below the set value. | |
4384 | */ | |
bc4d91f6 | 4385 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4386 | |
bc4d91f6 AG |
4387 | hw_max = dev_priv->rps.max_freq; |
4388 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4389 | |
36cdd013 DW |
4390 | if (val < hw_min || |
4391 | val > hw_max || val > dev_priv->rps.max_freq_softlimit) { | |
dd0a1aa1 JM |
4392 | mutex_unlock(&dev_priv->rps.hw_lock); |
4393 | return -EINVAL; | |
0a073b84 | 4394 | } |
dd0a1aa1 | 4395 | |
b39fb297 | 4396 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4397 | |
9fcee2f7 CW |
4398 | if (intel_set_rps(dev_priv, val)) |
4399 | DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n"); | |
dd0a1aa1 | 4400 | |
4fc688ce | 4401 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4402 | |
647416f9 | 4403 | return 0; |
1523c310 JB |
4404 | } |
4405 | ||
647416f9 KC |
4406 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4407 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4408 | "%llu\n"); |
1523c310 | 4409 | |
647416f9 KC |
4410 | static int |
4411 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4412 | { |
36cdd013 | 4413 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4414 | u32 snpcr; |
07b7ddd9 | 4415 | |
36cdd013 | 4416 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4417 | return -ENODEV; |
4418 | ||
c8c8fb33 | 4419 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4420 | |
07b7ddd9 | 4421 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4422 | |
4423 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 | 4424 | |
647416f9 | 4425 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4426 | |
647416f9 | 4427 | return 0; |
07b7ddd9 JB |
4428 | } |
4429 | ||
647416f9 KC |
4430 | static int |
4431 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4432 | { |
36cdd013 | 4433 | struct drm_i915_private *dev_priv = data; |
07b7ddd9 | 4434 | u32 snpcr; |
07b7ddd9 | 4435 | |
36cdd013 | 4436 | if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) |
004777cb DV |
4437 | return -ENODEV; |
4438 | ||
647416f9 | 4439 | if (val > 3) |
07b7ddd9 JB |
4440 | return -EINVAL; |
4441 | ||
c8c8fb33 | 4442 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4443 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4444 | |
4445 | /* Update the cache sharing policy here as well */ | |
4446 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4447 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4448 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4449 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4450 | ||
c8c8fb33 | 4451 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4452 | return 0; |
07b7ddd9 JB |
4453 | } |
4454 | ||
647416f9 KC |
4455 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4456 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4457 | "%llu\n"); | |
07b7ddd9 | 4458 | |
36cdd013 | 4459 | static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4460 | struct sseu_dev_info *sseu) |
5d39525a | 4461 | { |
0a0b457f | 4462 | int ss_max = 2; |
5d39525a JM |
4463 | int ss; |
4464 | u32 sig1[ss_max], sig2[ss_max]; | |
4465 | ||
4466 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4467 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4468 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4469 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4470 | ||
4471 | for (ss = 0; ss < ss_max; ss++) { | |
4472 | unsigned int eu_cnt; | |
4473 | ||
4474 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4475 | /* skip disabled subslice */ | |
4476 | continue; | |
4477 | ||
f08a0c92 | 4478 | sseu->slice_mask = BIT(0); |
57ec171e | 4479 | sseu->subslice_mask |= BIT(ss); |
5d39525a JM |
4480 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
4481 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4482 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4483 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
915490d5 ID |
4484 | sseu->eu_total += eu_cnt; |
4485 | sseu->eu_per_subslice = max_t(unsigned int, | |
4486 | sseu->eu_per_subslice, eu_cnt); | |
5d39525a | 4487 | } |
5d39525a JM |
4488 | } |
4489 | ||
36cdd013 | 4490 | static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4491 | struct sseu_dev_info *sseu) |
5d39525a | 4492 | { |
1c046bc1 | 4493 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4494 | int s, ss; |
4495 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4496 | ||
1c046bc1 | 4497 | /* BXT has a single slice and at most 3 subslices. */ |
cc3f90f0 | 4498 | if (IS_GEN9_LP(dev_priv)) { |
1c046bc1 JM |
4499 | s_max = 1; |
4500 | ss_max = 3; | |
4501 | } | |
4502 | ||
4503 | for (s = 0; s < s_max; s++) { | |
4504 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4505 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4506 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4507 | } | |
4508 | ||
5d39525a JM |
4509 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4510 | GEN9_PGCTL_SSA_EU19_ACK | | |
4511 | GEN9_PGCTL_SSA_EU210_ACK | | |
4512 | GEN9_PGCTL_SSA_EU311_ACK; | |
4513 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4514 | GEN9_PGCTL_SSB_EU19_ACK | | |
4515 | GEN9_PGCTL_SSB_EU210_ACK | | |
4516 | GEN9_PGCTL_SSB_EU311_ACK; | |
4517 | ||
4518 | for (s = 0; s < s_max; s++) { | |
4519 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4520 | /* skip disabled slice */ | |
4521 | continue; | |
4522 | ||
f08a0c92 | 4523 | sseu->slice_mask |= BIT(s); |
1c046bc1 | 4524 | |
7ea1adf3 | 4525 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) |
57ec171e ID |
4526 | sseu->subslice_mask = |
4527 | INTEL_INFO(dev_priv)->sseu.subslice_mask; | |
1c046bc1 | 4528 | |
5d39525a JM |
4529 | for (ss = 0; ss < ss_max; ss++) { |
4530 | unsigned int eu_cnt; | |
4531 | ||
cc3f90f0 | 4532 | if (IS_GEN9_LP(dev_priv)) { |
57ec171e ID |
4533 | if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
4534 | /* skip disabled subslice */ | |
4535 | continue; | |
1c046bc1 | 4536 | |
57ec171e ID |
4537 | sseu->subslice_mask |= BIT(ss); |
4538 | } | |
1c046bc1 | 4539 | |
5d39525a JM |
4540 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4541 | eu_mask[ss%2]); | |
915490d5 ID |
4542 | sseu->eu_total += eu_cnt; |
4543 | sseu->eu_per_subslice = max_t(unsigned int, | |
4544 | sseu->eu_per_subslice, | |
4545 | eu_cnt); | |
5d39525a JM |
4546 | } |
4547 | } | |
4548 | } | |
4549 | ||
36cdd013 | 4550 | static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, |
915490d5 | 4551 | struct sseu_dev_info *sseu) |
91bedd34 | 4552 | { |
91bedd34 | 4553 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
36cdd013 | 4554 | int s; |
91bedd34 | 4555 | |
f08a0c92 | 4556 | sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; |
91bedd34 | 4557 | |
f08a0c92 | 4558 | if (sseu->slice_mask) { |
57ec171e | 4559 | sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; |
43b67998 ID |
4560 | sseu->eu_per_subslice = |
4561 | INTEL_INFO(dev_priv)->sseu.eu_per_subslice; | |
57ec171e ID |
4562 | sseu->eu_total = sseu->eu_per_subslice * |
4563 | sseu_subslice_total(sseu); | |
91bedd34 ŁD |
4564 | |
4565 | /* subtract fused off EU(s) from enabled slice(s) */ | |
795b38b3 | 4566 | for (s = 0; s < fls(sseu->slice_mask); s++) { |
43b67998 ID |
4567 | u8 subslice_7eu = |
4568 | INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; | |
91bedd34 | 4569 | |
915490d5 | 4570 | sseu->eu_total -= hweight8(subslice_7eu); |
91bedd34 ŁD |
4571 | } |
4572 | } | |
4573 | } | |
4574 | ||
615d8908 ID |
4575 | static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, |
4576 | const struct sseu_dev_info *sseu) | |
4577 | { | |
4578 | struct drm_i915_private *dev_priv = node_to_i915(m->private); | |
4579 | const char *type = is_available_info ? "Available" : "Enabled"; | |
4580 | ||
c67ba538 ID |
4581 | seq_printf(m, " %s Slice Mask: %04x\n", type, |
4582 | sseu->slice_mask); | |
615d8908 | 4583 | seq_printf(m, " %s Slice Total: %u\n", type, |
f08a0c92 | 4584 | hweight8(sseu->slice_mask)); |
615d8908 | 4585 | seq_printf(m, " %s Subslice Total: %u\n", type, |
57ec171e | 4586 | sseu_subslice_total(sseu)); |
c67ba538 ID |
4587 | seq_printf(m, " %s Subslice Mask: %04x\n", type, |
4588 | sseu->subslice_mask); | |
615d8908 | 4589 | seq_printf(m, " %s Subslice Per Slice: %u\n", type, |
57ec171e | 4590 | hweight8(sseu->subslice_mask)); |
615d8908 ID |
4591 | seq_printf(m, " %s EU Total: %u\n", type, |
4592 | sseu->eu_total); | |
4593 | seq_printf(m, " %s EU Per Subslice: %u\n", type, | |
4594 | sseu->eu_per_subslice); | |
4595 | ||
4596 | if (!is_available_info) | |
4597 | return; | |
4598 | ||
4599 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); | |
4600 | if (HAS_POOLED_EU(dev_priv)) | |
4601 | seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); | |
4602 | ||
4603 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4604 | yesno(sseu->has_slice_pg)); | |
4605 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4606 | yesno(sseu->has_subslice_pg)); | |
4607 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4608 | yesno(sseu->has_eu_pg)); | |
4609 | } | |
4610 | ||
3873218f JM |
4611 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4612 | { | |
36cdd013 | 4613 | struct drm_i915_private *dev_priv = node_to_i915(m->private); |
915490d5 | 4614 | struct sseu_dev_info sseu; |
3873218f | 4615 | |
36cdd013 | 4616 | if (INTEL_GEN(dev_priv) < 8) |
3873218f JM |
4617 | return -ENODEV; |
4618 | ||
4619 | seq_puts(m, "SSEU Device Info\n"); | |
615d8908 | 4620 | i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); |
3873218f | 4621 | |
7f992aba | 4622 | seq_puts(m, "SSEU Device Status\n"); |
915490d5 | 4623 | memset(&sseu, 0, sizeof(sseu)); |
238010ed DW |
4624 | |
4625 | intel_runtime_pm_get(dev_priv); | |
4626 | ||
36cdd013 | 4627 | if (IS_CHERRYVIEW(dev_priv)) { |
915490d5 | 4628 | cherryview_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4629 | } else if (IS_BROADWELL(dev_priv)) { |
915490d5 | 4630 | broadwell_sseu_device_status(dev_priv, &sseu); |
36cdd013 | 4631 | } else if (INTEL_GEN(dev_priv) >= 9) { |
915490d5 | 4632 | gen9_sseu_device_status(dev_priv, &sseu); |
7f992aba | 4633 | } |
238010ed DW |
4634 | |
4635 | intel_runtime_pm_put(dev_priv); | |
4636 | ||
615d8908 | 4637 | i915_print_sseu_info(m, false, &sseu); |
7f992aba | 4638 | |
3873218f JM |
4639 | return 0; |
4640 | } | |
4641 | ||
6d794d42 BW |
4642 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4643 | { | |
d7a133d8 | 4644 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4645 | |
d7a133d8 | 4646 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4647 | return 0; |
4648 | ||
d7a133d8 CW |
4649 | intel_runtime_pm_get(i915); |
4650 | intel_uncore_forcewake_user_get(i915); | |
6d794d42 BW |
4651 | |
4652 | return 0; | |
4653 | } | |
4654 | ||
c43b5634 | 4655 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 | 4656 | { |
d7a133d8 | 4657 | struct drm_i915_private *i915 = inode->i_private; |
6d794d42 | 4658 | |
d7a133d8 | 4659 | if (INTEL_GEN(i915) < 6) |
6d794d42 BW |
4660 | return 0; |
4661 | ||
d7a133d8 CW |
4662 | intel_uncore_forcewake_user_put(i915); |
4663 | intel_runtime_pm_put(i915); | |
6d794d42 BW |
4664 | |
4665 | return 0; | |
4666 | } | |
4667 | ||
4668 | static const struct file_operations i915_forcewake_fops = { | |
4669 | .owner = THIS_MODULE, | |
4670 | .open = i915_forcewake_open, | |
4671 | .release = i915_forcewake_release, | |
4672 | }; | |
4673 | ||
317eaa95 L |
4674 | static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) |
4675 | { | |
4676 | struct drm_i915_private *dev_priv = m->private; | |
4677 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4678 | ||
4679 | seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); | |
4680 | seq_printf(m, "Detected: %s\n", | |
4681 | yesno(delayed_work_pending(&hotplug->reenable_work))); | |
4682 | ||
4683 | return 0; | |
4684 | } | |
4685 | ||
4686 | static ssize_t i915_hpd_storm_ctl_write(struct file *file, | |
4687 | const char __user *ubuf, size_t len, | |
4688 | loff_t *offp) | |
4689 | { | |
4690 | struct seq_file *m = file->private_data; | |
4691 | struct drm_i915_private *dev_priv = m->private; | |
4692 | struct i915_hotplug *hotplug = &dev_priv->hotplug; | |
4693 | unsigned int new_threshold; | |
4694 | int i; | |
4695 | char *newline; | |
4696 | char tmp[16]; | |
4697 | ||
4698 | if (len >= sizeof(tmp)) | |
4699 | return -EINVAL; | |
4700 | ||
4701 | if (copy_from_user(tmp, ubuf, len)) | |
4702 | return -EFAULT; | |
4703 | ||
4704 | tmp[len] = '\0'; | |
4705 | ||
4706 | /* Strip newline, if any */ | |
4707 | newline = strchr(tmp, '\n'); | |
4708 | if (newline) | |
4709 | *newline = '\0'; | |
4710 | ||
4711 | if (strcmp(tmp, "reset") == 0) | |
4712 | new_threshold = HPD_STORM_DEFAULT_THRESHOLD; | |
4713 | else if (kstrtouint(tmp, 10, &new_threshold) != 0) | |
4714 | return -EINVAL; | |
4715 | ||
4716 | if (new_threshold > 0) | |
4717 | DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n", | |
4718 | new_threshold); | |
4719 | else | |
4720 | DRM_DEBUG_KMS("Disabling HPD storm detection\n"); | |
4721 | ||
4722 | spin_lock_irq(&dev_priv->irq_lock); | |
4723 | hotplug->hpd_storm_threshold = new_threshold; | |
4724 | /* Reset the HPD storm stats so we don't accidentally trigger a storm */ | |
4725 | for_each_hpd_pin(i) | |
4726 | hotplug->stats[i].count = 0; | |
4727 | spin_unlock_irq(&dev_priv->irq_lock); | |
4728 | ||
4729 | /* Re-enable hpd immediately if we were in an irq storm */ | |
4730 | flush_delayed_work(&dev_priv->hotplug.reenable_work); | |
4731 | ||
4732 | return len; | |
4733 | } | |
4734 | ||
4735 | static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) | |
4736 | { | |
4737 | return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); | |
4738 | } | |
4739 | ||
4740 | static const struct file_operations i915_hpd_storm_ctl_fops = { | |
4741 | .owner = THIS_MODULE, | |
4742 | .open = i915_hpd_storm_ctl_open, | |
4743 | .read = seq_read, | |
4744 | .llseek = seq_lseek, | |
4745 | .release = single_release, | |
4746 | .write = i915_hpd_storm_ctl_write | |
4747 | }; | |
4748 | ||
06c5bf8c | 4749 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4750 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4751 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4752 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 4753 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 4754 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
2017263e BG |
4755 | {"i915_gem_request", i915_gem_request_info, 0}, |
4756 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4757 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4758 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
493018dc | 4759 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 4760 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 4761 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 4762 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
ac58d2ab | 4763 | {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, |
a8b9370f | 4764 | {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, |
0509ead1 | 4765 | {"i915_huc_load_status", i915_huc_load_status_info, 0}, |
adb4bd12 | 4766 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4767 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
061d06a2 | 4768 | {"i915_reset_info", i915_reset_info, 0}, |
f97108d1 | 4769 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4770 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4771 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 4772 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 4773 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4774 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4775 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4776 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 4777 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 4778 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4779 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4780 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
f65367b5 | 4781 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4782 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4783 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4784 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4785 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4786 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4787 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 4788 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 4789 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 4790 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 4791 | {"i915_display_info", i915_display_info, 0}, |
1b36595f | 4792 | {"i915_engine_info", i915_engine_info, 0}, |
e04934cf | 4793 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4794 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4795 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4796 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4797 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4798 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4799 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 4800 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 4801 | }; |
27c202ad | 4802 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4803 | |
06c5bf8c | 4804 | static const struct i915_debugfs_files { |
34b9674c DV |
4805 | const char *name; |
4806 | const struct file_operations *fops; | |
4807 | } i915_debugfs_files[] = { | |
4808 | {"i915_wedged", &i915_wedged_fops}, | |
4809 | {"i915_max_freq", &i915_max_freq_fops}, | |
4810 | {"i915_min_freq", &i915_min_freq_fops}, | |
4811 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
4812 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4813 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c | 4814 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
98a2f411 | 4815 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
34b9674c | 4816 | {"i915_error_state", &i915_error_state_fops}, |
5a4c6f1b | 4817 | {"i915_gpu_info", &i915_gpu_info_fops}, |
98a2f411 | 4818 | #endif |
34b9674c | 4819 | {"i915_next_seqno", &i915_next_seqno_fops}, |
bd9db02f | 4820 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4821 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4822 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4823 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
4127dc43 | 4824 | {"i915_fbc_false_color", &i915_fbc_false_color_fops}, |
eb3394fa TP |
4825 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
4826 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
685534ef | 4827 | {"i915_dp_test_active", &i915_displayport_test_active_fops}, |
317eaa95 | 4828 | {"i915_guc_log_control", &i915_guc_log_control_fops}, |
d2d4f39b KM |
4829 | {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, |
4830 | {"i915_ipc_status", &i915_ipc_status_fops} | |
34b9674c DV |
4831 | }; |
4832 | ||
1dac891c | 4833 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 4834 | { |
91c8a326 | 4835 | struct drm_minor *minor = dev_priv->drm.primary; |
b05eeb0f | 4836 | struct dentry *ent; |
34b9674c | 4837 | int ret, i; |
f3cd474b | 4838 | |
b05eeb0f NT |
4839 | ent = debugfs_create_file("i915_forcewake_user", S_IRUSR, |
4840 | minor->debugfs_root, to_i915(minor->dev), | |
4841 | &i915_forcewake_fops); | |
4842 | if (!ent) | |
4843 | return -ENOMEM; | |
6a9c308d | 4844 | |
731035fe TV |
4845 | ret = intel_pipe_crc_create(minor); |
4846 | if (ret) | |
4847 | return ret; | |
07144428 | 4848 | |
34b9674c | 4849 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
b05eeb0f NT |
4850 | ent = debugfs_create_file(i915_debugfs_files[i].name, |
4851 | S_IRUGO | S_IWUSR, | |
4852 | minor->debugfs_root, | |
4853 | to_i915(minor->dev), | |
34b9674c | 4854 | i915_debugfs_files[i].fops); |
b05eeb0f NT |
4855 | if (!ent) |
4856 | return -ENOMEM; | |
34b9674c | 4857 | } |
40633219 | 4858 | |
27c202ad BG |
4859 | return drm_debugfs_create_files(i915_debugfs_list, |
4860 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4861 | minor->debugfs_root, minor); |
4862 | } | |
4863 | ||
aa7471d2 JN |
4864 | struct dpcd_block { |
4865 | /* DPCD dump start address. */ | |
4866 | unsigned int offset; | |
4867 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
4868 | unsigned int end; | |
4869 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
4870 | size_t size; | |
4871 | /* Only valid for eDP. */ | |
4872 | bool edp; | |
4873 | }; | |
4874 | ||
4875 | static const struct dpcd_block i915_dpcd_debug[] = { | |
4876 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
4877 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
4878 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
4879 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
4880 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
4881 | { .offset = DP_SET_POWER }, | |
4882 | { .offset = DP_EDP_DPCD_REV }, | |
4883 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
4884 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
4885 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
4886 | }; | |
4887 | ||
4888 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
4889 | { | |
4890 | struct drm_connector *connector = m->private; | |
4891 | struct intel_dp *intel_dp = | |
4892 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4893 | uint8_t buf[16]; | |
4894 | ssize_t err; | |
4895 | int i; | |
4896 | ||
5c1a8875 MK |
4897 | if (connector->status != connector_status_connected) |
4898 | return -ENODEV; | |
4899 | ||
aa7471d2 JN |
4900 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
4901 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
4902 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
4903 | ||
4904 | if (b->edp && | |
4905 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
4906 | continue; | |
4907 | ||
4908 | /* low tech for now */ | |
4909 | if (WARN_ON(size > sizeof(buf))) | |
4910 | continue; | |
4911 | ||
4912 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
4913 | if (err <= 0) { | |
4914 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
4915 | size, b->offset, err); | |
4916 | continue; | |
4917 | } | |
4918 | ||
4919 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 4920 | } |
aa7471d2 JN |
4921 | |
4922 | return 0; | |
4923 | } | |
4924 | ||
4925 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
4926 | { | |
4927 | return single_open(file, i915_dpcd_show, inode->i_private); | |
4928 | } | |
4929 | ||
4930 | static const struct file_operations i915_dpcd_fops = { | |
4931 | .owner = THIS_MODULE, | |
4932 | .open = i915_dpcd_open, | |
4933 | .read = seq_read, | |
4934 | .llseek = seq_lseek, | |
4935 | .release = single_release, | |
4936 | }; | |
4937 | ||
ecbd6781 DW |
4938 | static int i915_panel_show(struct seq_file *m, void *data) |
4939 | { | |
4940 | struct drm_connector *connector = m->private; | |
4941 | struct intel_dp *intel_dp = | |
4942 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
4943 | ||
4944 | if (connector->status != connector_status_connected) | |
4945 | return -ENODEV; | |
4946 | ||
4947 | seq_printf(m, "Panel power up delay: %d\n", | |
4948 | intel_dp->panel_power_up_delay); | |
4949 | seq_printf(m, "Panel power down delay: %d\n", | |
4950 | intel_dp->panel_power_down_delay); | |
4951 | seq_printf(m, "Backlight on delay: %d\n", | |
4952 | intel_dp->backlight_on_delay); | |
4953 | seq_printf(m, "Backlight off delay: %d\n", | |
4954 | intel_dp->backlight_off_delay); | |
4955 | ||
4956 | return 0; | |
4957 | } | |
4958 | ||
4959 | static int i915_panel_open(struct inode *inode, struct file *file) | |
4960 | { | |
4961 | return single_open(file, i915_panel_show, inode->i_private); | |
4962 | } | |
4963 | ||
4964 | static const struct file_operations i915_panel_fops = { | |
4965 | .owner = THIS_MODULE, | |
4966 | .open = i915_panel_open, | |
4967 | .read = seq_read, | |
4968 | .llseek = seq_lseek, | |
4969 | .release = single_release, | |
4970 | }; | |
4971 | ||
aa7471d2 JN |
4972 | /** |
4973 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
4974 | * @connector: pointer to a registered drm_connector | |
4975 | * | |
4976 | * Cleanup will be done by drm_connector_unregister() through a call to | |
4977 | * drm_debugfs_connector_remove(). | |
4978 | * | |
4979 | * Returns 0 on success, negative error codes on error. | |
4980 | */ | |
4981 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
4982 | { | |
4983 | struct dentry *root = connector->debugfs_entry; | |
4984 | ||
4985 | /* The connector must have been registered beforehands. */ | |
4986 | if (!root) | |
4987 | return -ENODEV; | |
4988 | ||
4989 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
4990 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
ecbd6781 DW |
4991 | debugfs_create_file("i915_dpcd", S_IRUGO, root, |
4992 | connector, &i915_dpcd_fops); | |
4993 | ||
4994 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
4995 | debugfs_create_file("i915_panel_timings", S_IRUGO, root, | |
4996 | connector, &i915_panel_fops); | |
aa7471d2 JN |
4997 | |
4998 | return 0; | |
4999 | } |