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drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
2017263e
BG		 43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
497666d8
DL		 56/* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58static int
59drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62{
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80}
81
70d39fe4
CW		 82static int i915_capabilities(struct seq_file *m, void *data)
83{
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 90#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91#define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93#undef PRINT_FLAG
94#undef SEP_SEMICOLON
70d39fe4
CW		 95
96 return 0;
97}
2017263e 98
05394f39 99static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 if (obj->user_pin_count > 0)
a6172a80 102 return "P";
05394f39 103 else if (obj->pin_count > 0)
a6172a80
CW		 104 return "p";
105 else
106 return " ";
107}
108
05394f39 109static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 110{
0206e353
AJ		 111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
a6172a80
CW		 117}
118
1d693bcc
BW		 119static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120{
121 return obj->has_global_gtt_mapping ? "g" : " ";
122}
123
37811fcc
CW		 124static void
125describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126{
1d693bcc 127 struct i915_vma *vma;
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 144 if (obj->pin_count)
145 seq_printf(m, " (pinned x %d)", obj->pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
c1ad11fc
CW		 158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
69dc4987
CW		 169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 171}
172
3ccfd19d
BW		 173static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
174{
175 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
176 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
177 seq_putc(m, ' ');
178}
179
433e12f7 180static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 181{
182 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 183 uintptr_t list = (uintptr_t) node->info_ent->data;
184 struct list_head *head;
2017263e 185 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 188 struct i915_vma *vma;
8f2480fb
CW		 189 size_t total_obj_size, total_gtt_size;
190 int count, ret;
de227ef0
CW		 191
192 ret = mutex_lock_interruptible(&dev->struct_mutex);
193 if (ret)
194 return ret;
2017263e 195
ca191b13 196 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 197 switch (list) {
198 case ACTIVE_LIST:
267f0c90 199 seq_puts(m, "Active:\n");
5cef07e1 200 head = &vm->active_list;
433e12f7
BG		 201 break;
202 case INACTIVE_LIST:
267f0c90 203 seq_puts(m, "Inactive:\n");
5cef07e1 204 head = &vm->inactive_list;
433e12f7 205 break;
433e12f7 206 default:
de227ef0
CW		 207 mutex_unlock(&dev->struct_mutex);
208 return -EINVAL;
2017263e 209 }
2017263e 210
8f2480fb 211 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 212 list_for_each_entry(vma, head, mm_list) {
213 seq_printf(m, " ");
214 describe_obj(m, vma->obj);
215 seq_printf(m, "\n");
216 total_obj_size += vma->obj->base.size;
217 total_gtt_size += vma->node.size;
8f2480fb 218 count++;
2017263e 219 }
de227ef0 220 mutex_unlock(&dev->struct_mutex);
5e118f41 221
8f2480fb
CW		 222 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count, total_obj_size, total_gtt_size);
2017263e
BG		 224 return 0;
225}
226
6d2b8885
CW		 227static int obj_rank_by_stolen(void *priv,
228 struct list_head *A, struct list_head *B)
229{
230 struct drm_i915_gem_object *a =
b25cb2f8 231 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 232 struct drm_i915_gem_object *b =
b25cb2f8 233 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 234
235 return a->stolen->start - b->stolen->start;
236}
237
238static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
239{
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct drm_i915_gem_object *obj;
244 size_t total_obj_size, total_gtt_size;
245 LIST_HEAD(stolen);
246 int count, ret;
247
248 ret = mutex_lock_interruptible(&dev->struct_mutex);
249 if (ret)
250 return ret;
251
252 total_obj_size = total_gtt_size = count = 0;
253 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
254 if (obj->stolen == NULL)
255 continue;
256
b25cb2f8 257 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 258
259 total_obj_size += obj->base.size;
260 total_gtt_size += i915_gem_obj_ggtt_size(obj);
261 count++;
262 }
263 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
264 if (obj->stolen == NULL)
265 continue;
266
b25cb2f8 267 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 268
269 total_obj_size += obj->base.size;
270 count++;
271 }
272 list_sort(NULL, &stolen, obj_rank_by_stolen);
273 seq_puts(m, "Stolen:\n");
274 while (!list_empty(&stolen)) {
b25cb2f8 275 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 276 seq_puts(m, " ");
277 describe_obj(m, obj);
278 seq_putc(m, '\n');
b25cb2f8 279 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 280 }
281 mutex_unlock(&dev->struct_mutex);
282
283 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count, total_obj_size, total_gtt_size);
285 return 0;
286}
287
6299f992
CW		 288#define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
f343c5f6 290 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 291 ++count; \
292 if (obj->map_and_fenceable) { \
f343c5f6 293 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 294 ++mappable_count; \
295 } \
296 } \
0206e353 297} while (0)
6299f992 298
2db8e9d6
CW		 299struct file_stats {
300 int count;
301 size_t total, active, inactive, unbound;
302};
303
304static int per_file_stats(int id, void *ptr, void *data)
305{
306 struct drm_i915_gem_object *obj = ptr;
307 struct file_stats *stats = data;
308
309 stats->count++;
310 stats->total += obj->base.size;
311
f343c5f6 312 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 313 if (!list_empty(&obj->ring_list))
314 stats->active += obj->base.size;
315 else
316 stats->inactive += obj->base.size;
317 } else {
318 if (!list_empty(&obj->global_list))
319 stats->unbound += obj->base.size;
320 }
321
322 return 0;
323}
324
ca191b13
BW		 325#define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
328 ++count; \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
331 ++mappable_count; \
332 } \
333 } \
334} while (0)
335
336static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 337{
338 struct drm_info_node *node = (struct drm_info_node *) m->private;
339 struct drm_device *dev = node->minor->dev;
340 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 341 u32 count, mappable_count, purgeable_count;
342 size_t size, mappable_size, purgeable_size;
6299f992 343 struct drm_i915_gem_object *obj;
5cef07e1 344 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 345 struct drm_file *file;
ca191b13 346 struct i915_vma *vma;
73aa808f
CW		 347 int ret;
348
349 ret = mutex_lock_interruptible(&dev->struct_mutex);
350 if (ret)
351 return ret;
352
6299f992
CW		 353 seq_printf(m, "%u objects, %zu bytes\n",
354 dev_priv->mm.object_count,
355 dev_priv->mm.object_memory);
356
357 size = count = mappable_size = mappable_count = 0;
35c20a60 358 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 359 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count, mappable_count, size, mappable_size);
361
362 size = count = mappable_size = mappable_count = 0;
ca191b13 363 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 364 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count, mappable_count, size, mappable_size);
366
6299f992 367 size = count = mappable_size = mappable_count = 0;
ca191b13 368 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 369 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count, mappable_count, size, mappable_size);
371
b7abb714 372 size = count = purgeable_size = purgeable_count = 0;
35c20a60 373 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 374 size += obj->base.size, ++count;
b7abb714
CW		 375 if (obj->madv == I915_MADV_DONTNEED)
376 purgeable_size += obj->base.size, ++purgeable_count;
377 }
6c085a72
CW		 378 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
379
6299f992 380 size = count = mappable_size = mappable_count = 0;
35c20a60 381 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 382 if (obj->fault_mappable) {
f343c5f6 383 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 384 ++count;
385 }
386 if (obj->pin_mappable) {
f343c5f6 387 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 388 ++mappable_count;
389 }
b7abb714
CW		 390 if (obj->madv == I915_MADV_DONTNEED) {
391 purgeable_size += obj->base.size;
392 ++purgeable_count;
393 }
6299f992 394 }
b7abb714
CW		 395 seq_printf(m, "%u purgeable objects, %zu bytes\n",
396 purgeable_count, purgeable_size);
6299f992
CW		 397 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count, mappable_size);
399 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
400 count, size);
401
93d18799 402 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 403 dev_priv->gtt.base.total,
404 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 405
267f0c90 406 seq_putc(m, '\n');
2db8e9d6
CW		 407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
408 struct file_stats stats;
409
410 memset(&stats, 0, sizeof(stats));
411 idr_for_each(&file->object_idr, per_file_stats, &stats);
412 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file->pid, PIDTYPE_PID)->comm,
414 stats.count,
415 stats.total,
416 stats.active,
417 stats.inactive,
418 stats.unbound);
419 }
420
73aa808f
CW		 421 mutex_unlock(&dev->struct_mutex);
422
423 return 0;
424}
425
aee56cff 426static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 427{
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
1b50247a 430 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 431 struct drm_i915_private *dev_priv = dev->dev_private;
432 struct drm_i915_gem_object *obj;
433 size_t total_obj_size, total_gtt_size;
434 int count, ret;
435
436 ret = mutex_lock_interruptible(&dev->struct_mutex);
437 if (ret)
438 return ret;
439
440 total_obj_size = total_gtt_size = count = 0;
35c20a60 441 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1b50247a
CW		 442 if (list == PINNED_LIST && obj->pin_count == 0)
443 continue;
444
267f0c90 445 seq_puts(m, " ");
08c18323 446 describe_obj(m, obj);
267f0c90 447 seq_putc(m, '\n');
08c18323 448 total_obj_size += obj->base.size;
f343c5f6 449 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 450 count++;
451 }
452
453 mutex_unlock(&dev->struct_mutex);
454
455 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count, total_obj_size, total_gtt_size);
457
458 return 0;
459}
460
4e5359cd
SF		 461static int i915_gem_pageflip_info(struct seq_file *m, void *data)
462{
463 struct drm_info_node *node = (struct drm_info_node *) m->private;
464 struct drm_device *dev = node->minor->dev;
465 unsigned long flags;
466 struct intel_crtc *crtc;
467
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 469 const char pipe = pipe_name(crtc->pipe);
470 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 471 struct intel_unpin_work *work;
472
473 spin_lock_irqsave(&dev->event_lock, flags);
474 work = crtc->unpin_work;
475 if (work == NULL) {
9db4a9c7 476 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 477 pipe, plane);
478 } else {
e7d841ca 479 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 480 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 481 pipe, plane);
482 } else {
9db4a9c7 483 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 484 pipe, plane);
485 }
486 if (work->enable_stall_check)
267f0c90 487 seq_puts(m, "Stall check enabled, ");
4e5359cd 488 else
267f0c90 489 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 490 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 491
492 if (work->old_fb_obj) {
05394f39
CW		 493 struct drm_i915_gem_object *obj = work->old_fb_obj;
494 if (obj)
f343c5f6
BW		 495 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 497 }
498 if (work->pending_flip_obj) {
05394f39
CW		 499 struct drm_i915_gem_object *obj = work->pending_flip_obj;
500 if (obj)
f343c5f6
BW		 501 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 503 }
504 }
505 spin_unlock_irqrestore(&dev->event_lock, flags);
506 }
507
508 return 0;
509}
510
2017263e
BG		 511static int i915_gem_request_info(struct seq_file *m, void *data)
512{
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 516 struct intel_ring_buffer *ring;
2017263e 517 struct drm_i915_gem_request *gem_request;
a2c7f6fd 518 int ret, count, i;
de227ef0
CW		 519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
2017263e 523
c2c347a9 524 count = 0;
a2c7f6fd
CW		 525 for_each_ring(ring, dev_priv, i) {
526 if (list_empty(&ring->request_list))
527 continue;
528
529 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 530 list_for_each_entry(gem_request,
a2c7f6fd 531 &ring->request_list,
c2c347a9
CW		 532 list) {
533 seq_printf(m, " %d @ %d\n",
534 gem_request->seqno,
535 (int) (jiffies - gem_request->emitted_jiffies));
536 }
537 count++;
2017263e 538 }
de227ef0
CW		 539 mutex_unlock(&dev->struct_mutex);
540
c2c347a9 541 if (count == 0)
267f0c90 542 seq_puts(m, "No requests\n");
c2c347a9 543
2017263e
BG		 544 return 0;
545}
546
b2223497
CW		 547static void i915_ring_seqno_info(struct seq_file *m,
548 struct intel_ring_buffer *ring)
549{
550 if (ring->get_seqno) {
43a7b924 551 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 552 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 553 }
554}
555
2017263e
BG		 556static int i915_gem_seqno_info(struct seq_file *m, void *data)
557{
558 struct drm_info_node *node = (struct drm_info_node *) m->private;
559 struct drm_device *dev = node->minor->dev;
560 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 561 struct intel_ring_buffer *ring;
1ec14ad3 562 int ret, i;
de227ef0
CW		 563
564 ret = mutex_lock_interruptible(&dev->struct_mutex);
565 if (ret)
566 return ret;
2017263e 567
a2c7f6fd
CW		 568 for_each_ring(ring, dev_priv, i)
569 i915_ring_seqno_info(m, ring);
de227ef0
CW		 570
571 mutex_unlock(&dev->struct_mutex);
572
2017263e
BG		 573 return 0;
574}
575
576
577static int i915_interrupt_info(struct seq_file *m, void *data)
578{
579 struct drm_info_node *node = (struct drm_info_node *) m->private;
580 struct drm_device *dev = node->minor->dev;
581 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 582 struct intel_ring_buffer *ring;
9db4a9c7 583 int ret, i, pipe;
de227ef0
CW		 584
585 ret = mutex_lock_interruptible(&dev->struct_mutex);
586 if (ret)
587 return ret;
2017263e 588
a123f157
BW		 589 if (INTEL_INFO(dev)->gen >= 8) {
590 int i;
591 seq_printf(m, "Master Interrupt Control:\t%08x\n",
592 I915_READ(GEN8_MASTER_IRQ));
593
594 for (i = 0; i < 4; i++) {
595 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
596 i, I915_READ(GEN8_GT_IMR(i)));
597 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
598 i, I915_READ(GEN8_GT_IIR(i)));
599 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
600 i, I915_READ(GEN8_GT_IER(i)));
601 }
602
603 for_each_pipe(i) {
604 seq_printf(m, "Pipe %c IMR:\t%08x\n",
605 pipe_name(i),
606 I915_READ(GEN8_DE_PIPE_IMR(i)));
607 seq_printf(m, "Pipe %c IIR:\t%08x\n",
608 pipe_name(i),
609 I915_READ(GEN8_DE_PIPE_IIR(i)));
610 seq_printf(m, "Pipe %c IER:\t%08x\n",
611 pipe_name(i),
612 I915_READ(GEN8_DE_PIPE_IER(i)));
613 }
614
615 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
616 I915_READ(GEN8_DE_PORT_IMR));
617 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
618 I915_READ(GEN8_DE_PORT_IIR));
619 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
620 I915_READ(GEN8_DE_PORT_IER));
621
622 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
623 I915_READ(GEN8_DE_MISC_IMR));
624 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
625 I915_READ(GEN8_DE_MISC_IIR));
626 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
627 I915_READ(GEN8_DE_MISC_IER));
628
629 seq_printf(m, "PCU interrupt mask:\t%08x\n",
630 I915_READ(GEN8_PCU_IMR));
631 seq_printf(m, "PCU interrupt identity:\t%08x\n",
632 I915_READ(GEN8_PCU_IIR));
633 seq_printf(m, "PCU interrupt enable:\t%08x\n",
634 I915_READ(GEN8_PCU_IER));
635 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 636 seq_printf(m, "Display IER:\t%08x\n",
637 I915_READ(VLV_IER));
638 seq_printf(m, "Display IIR:\t%08x\n",
639 I915_READ(VLV_IIR));
640 seq_printf(m, "Display IIR_RW:\t%08x\n",
641 I915_READ(VLV_IIR_RW));
642 seq_printf(m, "Display IMR:\t%08x\n",
643 I915_READ(VLV_IMR));
644 for_each_pipe(pipe)
645 seq_printf(m, "Pipe %c stat:\t%08x\n",
646 pipe_name(pipe),
647 I915_READ(PIPESTAT(pipe)));
648
649 seq_printf(m, "Master IER:\t%08x\n",
650 I915_READ(VLV_MASTER_IER));
651
652 seq_printf(m, "Render IER:\t%08x\n",
653 I915_READ(GTIER));
654 seq_printf(m, "Render IIR:\t%08x\n",
655 I915_READ(GTIIR));
656 seq_printf(m, "Render IMR:\t%08x\n",
657 I915_READ(GTIMR));
658
659 seq_printf(m, "PM IER:\t\t%08x\n",
660 I915_READ(GEN6_PMIER));
661 seq_printf(m, "PM IIR:\t\t%08x\n",
662 I915_READ(GEN6_PMIIR));
663 seq_printf(m, "PM IMR:\t\t%08x\n",
664 I915_READ(GEN6_PMIMR));
665
666 seq_printf(m, "Port hotplug:\t%08x\n",
667 I915_READ(PORT_HOTPLUG_EN));
668 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
669 I915_READ(VLV_DPFLIPSTAT));
670 seq_printf(m, "DPINVGTT:\t%08x\n",
671 I915_READ(DPINVGTT));
672
673 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 674 seq_printf(m, "Interrupt enable: %08x\n",
675 I915_READ(IER));
676 seq_printf(m, "Interrupt identity: %08x\n",
677 I915_READ(IIR));
678 seq_printf(m, "Interrupt mask: %08x\n",
679 I915_READ(IMR));
9db4a9c7
JB		 680 for_each_pipe(pipe)
681 seq_printf(m, "Pipe %c stat: %08x\n",
682 pipe_name(pipe),
683 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 684 } else {
685 seq_printf(m, "North Display Interrupt enable: %08x\n",
686 I915_READ(DEIER));
687 seq_printf(m, "North Display Interrupt identity: %08x\n",
688 I915_READ(DEIIR));
689 seq_printf(m, "North Display Interrupt mask: %08x\n",
690 I915_READ(DEIMR));
691 seq_printf(m, "South Display Interrupt enable: %08x\n",
692 I915_READ(SDEIER));
693 seq_printf(m, "South Display Interrupt identity: %08x\n",
694 I915_READ(SDEIIR));
695 seq_printf(m, "South Display Interrupt mask: %08x\n",
696 I915_READ(SDEIMR));
697 seq_printf(m, "Graphics Interrupt enable: %08x\n",
698 I915_READ(GTIER));
699 seq_printf(m, "Graphics Interrupt identity: %08x\n",
700 I915_READ(GTIIR));
701 seq_printf(m, "Graphics Interrupt mask: %08x\n",
702 I915_READ(GTIMR));
703 }
2017263e
BG		 704 seq_printf(m, "Interrupts received: %d\n",
705 atomic_read(&dev_priv->irq_received));
a2c7f6fd 706 for_each_ring(ring, dev_priv, i) {
a123f157 707 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 708 seq_printf(m,
709 "Graphics Interrupt mask (%s): %08x\n",
710 ring->name, I915_READ_IMR(ring));
9862e600 711 }
a2c7f6fd 712 i915_ring_seqno_info(m, ring);
9862e600 713 }
de227ef0
CW		 714 mutex_unlock(&dev->struct_mutex);
715
2017263e
BG		 716 return 0;
717}
718
a6172a80
CW		 719static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
720{
721 struct drm_info_node *node = (struct drm_info_node *) m->private;
722 struct drm_device *dev = node->minor->dev;
723 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 724 int i, ret;
725
726 ret = mutex_lock_interruptible(&dev->struct_mutex);
727 if (ret)
728 return ret;
a6172a80
CW		 729
730 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
731 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
732 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 733 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 734
6c085a72
CW		 735 seq_printf(m, "Fence %d, pin count = %d, object = ",
736 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 737 if (obj == NULL)
267f0c90 738 seq_puts(m, "unused");
c2c347a9 739 else
05394f39 740 describe_obj(m, obj);
267f0c90 741 seq_putc(m, '\n');
a6172a80
CW		 742 }
743
05394f39 744 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 745 return 0;
746}
747
2017263e
BG		 748static int i915_hws_info(struct seq_file *m, void *data)
749{
750 struct drm_info_node *node = (struct drm_info_node *) m->private;
751 struct drm_device *dev = node->minor->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 753 struct intel_ring_buffer *ring;
1a240d4d 754 const u32 *hws;
4066c0ae
CW		 755 int i;
756
1ec14ad3 757 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 758 hws = ring->status_page.page_addr;
2017263e
BG		 759 if (hws == NULL)
760 return 0;
761
762 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
763 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
764 i * 4,
765 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
766 }
767 return 0;
768}
769
d5442303
DV		 770static ssize_t
771i915_error_state_write(struct file *filp,
772 const char __user *ubuf,
773 size_t cnt,
774 loff_t *ppos)
775{
edc3d884 776 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 777 struct drm_device *dev = error_priv->dev;
22bcfc6a 778 int ret;
d5442303
DV		 779
780 DRM_DEBUG_DRIVER("Resetting error state\n");
781
22bcfc6a
DV		 782 ret = mutex_lock_interruptible(&dev->struct_mutex);
783 if (ret)
784 return ret;
785
d5442303
DV		 786 i915_destroy_error_state(dev);
787 mutex_unlock(&dev->struct_mutex);
788
789 return cnt;
790}
791
792static int i915_error_state_open(struct inode *inode, struct file *file)
793{
794 struct drm_device *dev = inode->i_private;
d5442303 795 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 796
797 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
798 if (!error_priv)
799 return -ENOMEM;
800
801 error_priv->dev = dev;
802
95d5bfb3 803 i915_error_state_get(dev, error_priv);
d5442303 804
edc3d884
MK		 805 file->private_data = error_priv;
806
807 return 0;
d5442303
DV		 808}
809
810static int i915_error_state_release(struct inode *inode, struct file *file)
811{
edc3d884 812 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 813
95d5bfb3 814 i915_error_state_put(error_priv);
d5442303
DV		 815 kfree(error_priv);
816
edc3d884
MK		 817 return 0;
818}
819
4dc955f7
MK		 820static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
821 size_t count, loff_t *pos)
822{
823 struct i915_error_state_file_priv *error_priv = file->private_data;
824 struct drm_i915_error_state_buf error_str;
825 loff_t tmp_pos = 0;
826 ssize_t ret_count = 0;
827 int ret;
828
829 ret = i915_error_state_buf_init(&error_str, count, *pos);
830 if (ret)
831 return ret;
edc3d884 832
fc16b48b 833 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 834 if (ret)
835 goto out;
836
edc3d884
MK		 837 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
838 error_str.buf,
839 error_str.bytes);
840
841 if (ret_count < 0)
842 ret = ret_count;
843 else
844 *pos = error_str.start + ret_count;
845out:
4dc955f7 846 i915_error_state_buf_release(&error_str);
edc3d884 847 return ret ?: ret_count;
d5442303
DV		 848}
849
850static const struct file_operations i915_error_state_fops = {
851 .owner = THIS_MODULE,
852 .open = i915_error_state_open,
edc3d884 853 .read = i915_error_state_read,
d5442303
DV		 854 .write = i915_error_state_write,
855 .llseek = default_llseek,
856 .release = i915_error_state_release,
857};
858
647416f9
KC		 859static int
860i915_next_seqno_get(void *data, u64 *val)
40633219 861{
647416f9 862 struct drm_device *dev = data;
40633219 863 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 864 int ret;
865
866 ret = mutex_lock_interruptible(&dev->struct_mutex);
867 if (ret)
868 return ret;
869
647416f9 870 *val = dev_priv->next_seqno;
40633219
MK		 871 mutex_unlock(&dev->struct_mutex);
872
647416f9 873 return 0;
40633219
MK		 874}
875
647416f9
KC		 876static int
877i915_next_seqno_set(void *data, u64 val)
878{
879 struct drm_device *dev = data;
40633219
MK		 880 int ret;
881
40633219
MK		 882 ret = mutex_lock_interruptible(&dev->struct_mutex);
883 if (ret)
884 return ret;
885
e94fbaa8 886 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 887 mutex_unlock(&dev->struct_mutex);
888
647416f9 889 return ret;
40633219
MK		 890}
891
647416f9
KC		 892DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
893 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 894 "0x%llx\n");
40633219 895
f97108d1
JB		 896static int i915_rstdby_delays(struct seq_file *m, void *unused)
897{
898 struct drm_info_node *node = (struct drm_info_node *) m->private;
899 struct drm_device *dev = node->minor->dev;
900 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 901 u16 crstanddelay;
902 int ret;
903
904 ret = mutex_lock_interruptible(&dev->struct_mutex);
905 if (ret)
906 return ret;
907
908 crstanddelay = I915_READ16(CRSTANDVID);
909
910 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 911
912 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
913
914 return 0;
915}
916
917static int i915_cur_delayinfo(struct seq_file *m, void *unused)
918{
919 struct drm_info_node *node = (struct drm_info_node *) m->private;
920 struct drm_device *dev = node->minor->dev;
921 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 922 int ret;
3b8d8d91 923
5c9669ce
TR		 924 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
925
3b8d8d91
JB		 926 if (IS_GEN5(dev)) {
927 u16 rgvswctl = I915_READ16(MEMSWCTL);
928 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
929
930 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
931 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
932 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
933 MEMSTAT_VID_SHIFT);
934 seq_printf(m, "Current P-state: %d\n",
935 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 936 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 937 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
938 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
939 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 940 u32 rpstat, cagf, reqf;
ccab5c82
JB		 941 u32 rpupei, rpcurup, rpprevup;
942 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 943 int max_freq;
944
945 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 946 ret = mutex_lock_interruptible(&dev->struct_mutex);
947 if (ret)
948 return ret;
949
fcca7926 950 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 951
8e8c06cd
CW		 952 reqf = I915_READ(GEN6_RPNSWREQ);
953 reqf &= ~GEN6_TURBO_DISABLE;
954 if (IS_HASWELL(dev))
955 reqf >>= 24;
956 else
957 reqf >>= 25;
958 reqf *= GT_FREQUENCY_MULTIPLIER;
959
ccab5c82
JB		 960 rpstat = I915_READ(GEN6_RPSTAT1);
961 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
962 rpcurup = I915_READ(GEN6_RP_CUR_UP);
963 rpprevup = I915_READ(GEN6_RP_PREV_UP);
964 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
965 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
966 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 967 if (IS_HASWELL(dev))
968 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
969 else
970 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
971 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 972
d1ebd816
BW		 973 gen6_gt_force_wake_put(dev_priv);
974 mutex_unlock(&dev->struct_mutex);
975
3b8d8d91 976 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 977 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 978 seq_printf(m, "Render p-state ratio: %d\n",
979 (gt_perf_status & 0xff00) >> 8);
980 seq_printf(m, "Render p-state VID: %d\n",
981 gt_perf_status & 0xff);
982 seq_printf(m, "Render p-state limit: %d\n",
983 rp_state_limits & 0xff);
8e8c06cd 984 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 985 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 986 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
987 GEN6_CURICONT_MASK);
988 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
989 GEN6_CURBSYTAVG_MASK);
990 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
991 GEN6_CURBSYTAVG_MASK);
992 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
993 GEN6_CURIAVG_MASK);
994 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
995 GEN6_CURBSYTAVG_MASK);
996 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
997 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 998
999 max_freq = (rp_state_cap & 0xff0000) >> 16;
1000 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1001 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1002
1003 max_freq = (rp_state_cap & 0xff00) >> 8;
1004 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1005 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1006
1007 max_freq = rp_state_cap & 0xff;
1008 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1009 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1010
1011 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1012 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1013 } else if (IS_VALLEYVIEW(dev)) {
1014 u32 freq_sts, val;
1015
259bd5d4 1016 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1017 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1018 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1019 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1020
64936258 1021 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
0a073b84
JB		 1022 seq_printf(m, "max GPU freq: %d MHz\n",
1023 vlv_gpu_freq(dev_priv->mem_freq, val));
1024
64936258 1025 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
0a073b84
JB		 1026 seq_printf(m, "min GPU freq: %d MHz\n",
1027 vlv_gpu_freq(dev_priv->mem_freq, val));
1028
1029 seq_printf(m, "current GPU freq: %d MHz\n",
1030 vlv_gpu_freq(dev_priv->mem_freq,
1031 (freq_sts >> 8) & 0xff));
259bd5d4 1032 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1033 } else {
267f0c90 1034 seq_puts(m, "no P-state info available\n");
3b8d8d91 1035 }
f97108d1
JB		 1036
1037 return 0;
1038}
1039
1040static int i915_delayfreq_table(struct seq_file *m, void *unused)
1041{
1042 struct drm_info_node *node = (struct drm_info_node *) m->private;
1043 struct drm_device *dev = node->minor->dev;
1044 drm_i915_private_t *dev_priv = dev->dev_private;
1045 u32 delayfreq;
616fdb5a
BW		 1046 int ret, i;
1047
1048 ret = mutex_lock_interruptible(&dev->struct_mutex);
1049 if (ret)
1050 return ret;
f97108d1
JB		 1051
1052 for (i = 0; i < 16; i++) {
1053 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1054 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1055 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1056 }
1057
616fdb5a
BW		 1058 mutex_unlock(&dev->struct_mutex);
1059
f97108d1
JB		 1060 return 0;
1061}
1062
1063static inline int MAP_TO_MV(int map)
1064{
1065 return 1250 - (map * 25);
1066}
1067
1068static int i915_inttoext_table(struct seq_file *m, void *unused)
1069{
1070 struct drm_info_node *node = (struct drm_info_node *) m->private;
1071 struct drm_device *dev = node->minor->dev;
1072 drm_i915_private_t *dev_priv = dev->dev_private;
1073 u32 inttoext;
616fdb5a
BW		 1074 int ret, i;
1075
1076 ret = mutex_lock_interruptible(&dev->struct_mutex);
1077 if (ret)
1078 return ret;
f97108d1
JB		 1079
1080 for (i = 1; i <= 32; i++) {
1081 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1082 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1083 }
1084
616fdb5a
BW		 1085 mutex_unlock(&dev->struct_mutex);
1086
f97108d1
JB		 1087 return 0;
1088}
1089
4d85529d 1090static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1091{
1092 struct drm_info_node *node = (struct drm_info_node *) m->private;
1093 struct drm_device *dev = node->minor->dev;
1094 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1095 u32 rgvmodectl, rstdbyctl;
1096 u16 crstandvid;
1097 int ret;
1098
1099 ret = mutex_lock_interruptible(&dev->struct_mutex);
1100 if (ret)
1101 return ret;
1102
1103 rgvmodectl = I915_READ(MEMMODECTL);
1104 rstdbyctl = I915_READ(RSTDBYCTL);
1105 crstandvid = I915_READ16(CRSTANDVID);
1106
1107 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1108
1109 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1110 "yes" : "no");
1111 seq_printf(m, "Boost freq: %d\n",
1112 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1113 MEMMODE_BOOST_FREQ_SHIFT);
1114 seq_printf(m, "HW control enabled: %s\n",
1115 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1116 seq_printf(m, "SW control enabled: %s\n",
1117 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1118 seq_printf(m, "Gated voltage change: %s\n",
1119 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1120 seq_printf(m, "Starting frequency: P%d\n",
1121 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1122 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1123 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1124 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1125 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1126 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1127 seq_printf(m, "Render standby enabled: %s\n",
1128 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1129 seq_puts(m, "Current RS state: ");
88271da3
JB		 1130 switch (rstdbyctl & RSX_STATUS_MASK) {
1131 case RSX_STATUS_ON:
267f0c90 1132 seq_puts(m, "on\n");
88271da3
JB		 1133 break;
1134 case RSX_STATUS_RC1:
267f0c90 1135 seq_puts(m, "RC1\n");
88271da3
JB		 1136 break;
1137 case RSX_STATUS_RC1E:
267f0c90 1138 seq_puts(m, "RC1E\n");
88271da3
JB		 1139 break;
1140 case RSX_STATUS_RS1:
267f0c90 1141 seq_puts(m, "RS1\n");
88271da3
JB		 1142 break;
1143 case RSX_STATUS_RS2:
267f0c90 1144 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1145 break;
1146 case RSX_STATUS_RS3:
267f0c90 1147 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1148 break;
1149 default:
267f0c90 1150 seq_puts(m, "unknown\n");
88271da3
JB		 1151 break;
1152 }
f97108d1
JB		 1153
1154 return 0;
1155}
1156
4d85529d
BW		 1157static int gen6_drpc_info(struct seq_file *m)
1158{
1159
1160 struct drm_info_node *node = (struct drm_info_node *) m->private;
1161 struct drm_device *dev = node->minor->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1163 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1164 unsigned forcewake_count;
aee56cff 1165 int count = 0, ret;
4d85529d
BW		 1166
1167 ret = mutex_lock_interruptible(&dev->struct_mutex);
1168 if (ret)
1169 return ret;
1170
907b28c5
CW		 1171 spin_lock_irq(&dev_priv->uncore.lock);
1172 forcewake_count = dev_priv->uncore.forcewake_count;
1173 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1174
1175 if (forcewake_count) {
267f0c90
DL		 1176 seq_puts(m, "RC information inaccurate because somebody "
1177 "holds a forcewake reference \n");
4d85529d
BW		 1178 } else {
1179 /* NB: we cannot use forcewake, else we read the wrong values */
1180 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1181 udelay(10);
1182 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1183 }
1184
1185 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1186 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1187
1188 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1189 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1190 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1191 mutex_lock(&dev_priv->rps.hw_lock);
1192 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1193 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1194
1195 seq_printf(m, "Video Turbo Mode: %s\n",
1196 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1197 seq_printf(m, "HW control enabled: %s\n",
1198 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1199 seq_printf(m, "SW control enabled: %s\n",
1200 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1201 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1202 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1203 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1204 seq_printf(m, "RC6 Enabled: %s\n",
1205 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1206 seq_printf(m, "Deep RC6 Enabled: %s\n",
1207 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1208 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1209 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1210 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1211 switch (gt_core_status & GEN6_RCn_MASK) {
1212 case GEN6_RC0:
1213 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1214 seq_puts(m, "Core Power Down\n");
4d85529d 1215 else
267f0c90 1216 seq_puts(m, "on\n");
4d85529d
BW		 1217 break;
1218 case GEN6_RC3:
267f0c90 1219 seq_puts(m, "RC3\n");
4d85529d
BW		 1220 break;
1221 case GEN6_RC6:
267f0c90 1222 seq_puts(m, "RC6\n");
4d85529d
BW		 1223 break;
1224 case GEN6_RC7:
267f0c90 1225 seq_puts(m, "RC7\n");
4d85529d
BW		 1226 break;
1227 default:
267f0c90 1228 seq_puts(m, "Unknown\n");
4d85529d
BW		 1229 break;
1230 }
1231
1232 seq_printf(m, "Core Power Down: %s\n",
1233 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1234
1235 /* Not exactly sure what this is */
1236 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1237 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1238 seq_printf(m, "RC6 residency since boot: %u\n",
1239 I915_READ(GEN6_GT_GFX_RC6));
1240 seq_printf(m, "RC6+ residency since boot: %u\n",
1241 I915_READ(GEN6_GT_GFX_RC6p));
1242 seq_printf(m, "RC6++ residency since boot: %u\n",
1243 I915_READ(GEN6_GT_GFX_RC6pp));
1244
ecd8faea
BW		 1245 seq_printf(m, "RC6 voltage: %dmV\n",
1246 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1247 seq_printf(m, "RC6+ voltage: %dmV\n",
1248 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1249 seq_printf(m, "RC6++ voltage: %dmV\n",
1250 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1251 return 0;
1252}
1253
1254static int i915_drpc_info(struct seq_file *m, void *unused)
1255{
1256 struct drm_info_node *node = (struct drm_info_node *) m->private;
1257 struct drm_device *dev = node->minor->dev;
1258
1259 if (IS_GEN6(dev) || IS_GEN7(dev))
1260 return gen6_drpc_info(m);
1261 else
1262 return ironlake_drpc_info(m);
1263}
1264
b5e50c3f
JB		 1265static int i915_fbc_status(struct seq_file *m, void *unused)
1266{
1267 struct drm_info_node *node = (struct drm_info_node *) m->private;
1268 struct drm_device *dev = node->minor->dev;
b5e50c3f 1269 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1270
ee5382ae 1271 if (!I915_HAS_FBC(dev)) {
267f0c90 1272 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1273 return 0;
1274 }
1275
ee5382ae 1276 if (intel_fbc_enabled(dev)) {
267f0c90 1277 seq_puts(m, "FBC enabled\n");
b5e50c3f 1278 } else {
267f0c90 1279 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1280 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1281 case FBC_OK:
1282 seq_puts(m, "FBC actived, but currently disabled in hardware");
1283 break;
1284 case FBC_UNSUPPORTED:
1285 seq_puts(m, "unsupported by this chipset");
1286 break;
bed4a673 1287 case FBC_NO_OUTPUT:
267f0c90 1288 seq_puts(m, "no outputs");
bed4a673 1289 break;
b5e50c3f 1290 case FBC_STOLEN_TOO_SMALL:
267f0c90 1291 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1292 break;
1293 case FBC_UNSUPPORTED_MODE:
267f0c90 1294 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1295 break;
1296 case FBC_MODE_TOO_LARGE:
267f0c90 1297 seq_puts(m, "mode too large");
b5e50c3f
JB		 1298 break;
1299 case FBC_BAD_PLANE:
267f0c90 1300 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1301 break;
1302 case FBC_NOT_TILED:
267f0c90 1303 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1304 break;
9c928d16 1305 case FBC_MULTIPLE_PIPES:
267f0c90 1306 seq_puts(m, "multiple pipes are enabled");
9c928d16 1307 break;
c1a9f047 1308 case FBC_MODULE_PARAM:
267f0c90 1309 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1310 break;
8a5729a3 1311 case FBC_CHIP_DEFAULT:
267f0c90 1312 seq_puts(m, "disabled per chip default");
8a5729a3 1313 break;
b5e50c3f 1314 default:
267f0c90 1315 seq_puts(m, "unknown reason");
b5e50c3f 1316 }
267f0c90 1317 seq_putc(m, '\n');
b5e50c3f
JB		 1318 }
1319 return 0;
1320}
1321
92d44621
PZ		 1322static int i915_ips_status(struct seq_file *m, void *unused)
1323{
1324 struct drm_info_node *node = (struct drm_info_node *) m->private;
1325 struct drm_device *dev = node->minor->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327
f5adf94e 1328 if (!HAS_IPS(dev)) {
92d44621
PZ		 1329 seq_puts(m, "not supported\n");
1330 return 0;
1331 }
1332
1333 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1334 seq_puts(m, "enabled\n");
1335 else
1336 seq_puts(m, "disabled\n");
1337
1338 return 0;
1339}
1340
4a9bef37
JB		 1341static int i915_sr_status(struct seq_file *m, void *unused)
1342{
1343 struct drm_info_node *node = (struct drm_info_node *) m->private;
1344 struct drm_device *dev = node->minor->dev;
1345 drm_i915_private_t *dev_priv = dev->dev_private;
1346 bool sr_enabled = false;
1347
1398261a 1348 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1349 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1350 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1351 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1352 else if (IS_I915GM(dev))
1353 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1354 else if (IS_PINEVIEW(dev))
1355 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1356
5ba2aaaa
CW		 1357 seq_printf(m, "self-refresh: %s\n",
1358 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1359
1360 return 0;
1361}
1362
7648fa99
JB		 1363static int i915_emon_status(struct seq_file *m, void *unused)
1364{
1365 struct drm_info_node *node = (struct drm_info_node *) m->private;
1366 struct drm_device *dev = node->minor->dev;
1367 drm_i915_private_t *dev_priv = dev->dev_private;
1368 unsigned long temp, chipset, gfx;
de227ef0
CW		 1369 int ret;
1370
582be6b4
CW		 1371 if (!IS_GEN5(dev))
1372 return -ENODEV;
1373
de227ef0
CW		 1374 ret = mutex_lock_interruptible(&dev->struct_mutex);
1375 if (ret)
1376 return ret;
7648fa99
JB		 1377
1378 temp = i915_mch_val(dev_priv);
1379 chipset = i915_chipset_val(dev_priv);
1380 gfx = i915_gfx_val(dev_priv);
de227ef0 1381 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1382
1383 seq_printf(m, "GMCH temp: %ld\n", temp);
1384 seq_printf(m, "Chipset power: %ld\n", chipset);
1385 seq_printf(m, "GFX power: %ld\n", gfx);
1386 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1387
1388 return 0;
1389}
1390
23b2f8bb
JB		 1391static int i915_ring_freq_table(struct seq_file *m, void *unused)
1392{
1393 struct drm_info_node *node = (struct drm_info_node *) m->private;
1394 struct drm_device *dev = node->minor->dev;
1395 drm_i915_private_t *dev_priv = dev->dev_private;
1396 int ret;
1397 int gpu_freq, ia_freq;
1398
1c70c0ce 1399 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1400 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1401 return 0;
1402 }
1403
5c9669ce
TR		 1404 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1405
4fc688ce 1406 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1407 if (ret)
1408 return ret;
1409
267f0c90 1410 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1411
c6a828d3
DV		 1412 for (gpu_freq = dev_priv->rps.min_delay;
1413 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1414 gpu_freq++) {
42c0526c
BW		 1415 ia_freq = gpu_freq;
1416 sandybridge_pcode_read(dev_priv,
1417 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1418 &ia_freq);
3ebecd07
CW		 1419 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1420 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1421 ((ia_freq >> 0) & 0xff) * 100,
1422 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1423 }
1424
4fc688ce 1425 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1426
1427 return 0;
1428}
1429
7648fa99
JB		 1430static int i915_gfxec(struct seq_file *m, void *unused)
1431{
1432 struct drm_info_node *node = (struct drm_info_node *) m->private;
1433 struct drm_device *dev = node->minor->dev;
1434 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1435 int ret;
1436
1437 ret = mutex_lock_interruptible(&dev->struct_mutex);
1438 if (ret)
1439 return ret;
7648fa99
JB		 1440
1441 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1442
616fdb5a
BW		 1443 mutex_unlock(&dev->struct_mutex);
1444
7648fa99
JB		 1445 return 0;
1446}
1447
44834a67
CW		 1448static int i915_opregion(struct seq_file *m, void *unused)
1449{
1450 struct drm_info_node *node = (struct drm_info_node *) m->private;
1451 struct drm_device *dev = node->minor->dev;
1452 drm_i915_private_t *dev_priv = dev->dev_private;
1453 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1454 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1455 int ret;
1456
0d38f009
DV		 1457 if (data == NULL)
1458 return -ENOMEM;
1459
44834a67
CW		 1460 ret = mutex_lock_interruptible(&dev->struct_mutex);
1461 if (ret)
0d38f009 1462 goto out;
44834a67 1463
0d38f009
DV		 1464 if (opregion->header) {
1465 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1466 seq_write(m, data, OPREGION_SIZE);
1467 }
44834a67
CW		 1468
1469 mutex_unlock(&dev->struct_mutex);
1470
0d38f009
DV		 1471out:
1472 kfree(data);
44834a67
CW		 1473 return 0;
1474}
1475
37811fcc
CW		 1476static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1477{
1478 struct drm_info_node *node = (struct drm_info_node *) m->private;
1479 struct drm_device *dev = node->minor->dev;
4520f53a 1480 struct intel_fbdev *ifbdev = NULL;
37811fcc 1481 struct intel_framebuffer *fb;
37811fcc 1482
4520f53a
DV		 1483#ifdef CONFIG_DRM_I915_FBDEV
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1486 if (ret)
1487 return ret;
1488
1489 ifbdev = dev_priv->fbdev;
1490 fb = to_intel_framebuffer(ifbdev->helper.fb);
1491
623f9783 1492 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1493 fb->base.width,
1494 fb->base.height,
1495 fb->base.depth,
623f9783
DV		 1496 fb->base.bits_per_pixel,
1497 atomic_read(&fb->base.refcount.refcount));
05394f39 1498 describe_obj(m, fb->obj);
267f0c90 1499 seq_putc(m, '\n');
4b096ac1 1500 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1501#endif
37811fcc 1502
4b096ac1 1503 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1504 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1505 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1506 continue;
1507
623f9783 1508 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1509 fb->base.width,
1510 fb->base.height,
1511 fb->base.depth,
623f9783
DV		 1512 fb->base.bits_per_pixel,
1513 atomic_read(&fb->base.refcount.refcount));
05394f39 1514 describe_obj(m, fb->obj);
267f0c90 1515 seq_putc(m, '\n');
37811fcc 1516 }
4b096ac1 1517 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1518
1519 return 0;
1520}
1521
e76d3630
BW		 1522static int i915_context_status(struct seq_file *m, void *unused)
1523{
1524 struct drm_info_node *node = (struct drm_info_node *) m->private;
1525 struct drm_device *dev = node->minor->dev;
1526 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1527 struct intel_ring_buffer *ring;
a33afea5 1528 struct i915_hw_context *ctx;
a168c293 1529 int ret, i;
e76d3630
BW		 1530
1531 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1532 if (ret)
1533 return ret;
1534
3e373948 1535 if (dev_priv->ips.pwrctx) {
267f0c90 1536 seq_puts(m, "power context ");
3e373948 1537 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1538 seq_putc(m, '\n');
dc501fbc 1539 }
e76d3630 1540
3e373948 1541 if (dev_priv->ips.renderctx) {
267f0c90 1542 seq_puts(m, "render context ");
3e373948 1543 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1544 seq_putc(m, '\n');
dc501fbc 1545 }
e76d3630 1546
a33afea5
BW		 1547 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1548 seq_puts(m, "HW context ");
3ccfd19d 1549 describe_ctx(m, ctx);
a33afea5
BW		 1550 for_each_ring(ring, dev_priv, i)
1551 if (ring->default_context == ctx)
1552 seq_printf(m, "(default context %s) ", ring->name);
1553
1554 describe_obj(m, ctx->obj);
1555 seq_putc(m, '\n');
a168c293
BW		 1556 }
1557
e76d3630
BW		 1558 mutex_unlock(&dev->mode_config.mutex);
1559
1560 return 0;
1561}
1562
6d794d42
BW		 1563static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1564{
1565 struct drm_info_node *node = (struct drm_info_node *) m->private;
1566 struct drm_device *dev = node->minor->dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1568 unsigned forcewake_count;
6d794d42 1569
907b28c5
CW		 1570 spin_lock_irq(&dev_priv->uncore.lock);
1571 forcewake_count = dev_priv->uncore.forcewake_count;
1572 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1573
9f1f46a4 1574 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1575
1576 return 0;
1577}
1578
ea16a3cd
DV		 1579static const char *swizzle_string(unsigned swizzle)
1580{
aee56cff 1581 switch (swizzle) {
ea16a3cd
DV		 1582 case I915_BIT_6_SWIZZLE_NONE:
1583 return "none";
1584 case I915_BIT_6_SWIZZLE_9:
1585 return "bit9";
1586 case I915_BIT_6_SWIZZLE_9_10:
1587 return "bit9/bit10";
1588 case I915_BIT_6_SWIZZLE_9_11:
1589 return "bit9/bit11";
1590 case I915_BIT_6_SWIZZLE_9_10_11:
1591 return "bit9/bit10/bit11";
1592 case I915_BIT_6_SWIZZLE_9_17:
1593 return "bit9/bit17";
1594 case I915_BIT_6_SWIZZLE_9_10_17:
1595 return "bit9/bit10/bit17";
1596 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1597 return "unknown";
ea16a3cd
DV		 1598 }
1599
1600 return "bug";
1601}
1602
1603static int i915_swizzle_info(struct seq_file *m, void *data)
1604{
1605 struct drm_info_node *node = (struct drm_info_node *) m->private;
1606 struct drm_device *dev = node->minor->dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1608 int ret;
1609
1610 ret = mutex_lock_interruptible(&dev->struct_mutex);
1611 if (ret)
1612 return ret;
ea16a3cd 1613
ea16a3cd
DV		 1614 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1615 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1616 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1617 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1618
1619 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1620 seq_printf(m, "DDC = 0x%08x\n",
1621 I915_READ(DCC));
1622 seq_printf(m, "C0DRB3 = 0x%04x\n",
1623 I915_READ16(C0DRB3));
1624 seq_printf(m, "C1DRB3 = 0x%04x\n",
1625 I915_READ16(C1DRB3));
9d3203e1 1626 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1627 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1628 I915_READ(MAD_DIMM_C0));
1629 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1630 I915_READ(MAD_DIMM_C1));
1631 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1632 I915_READ(MAD_DIMM_C2));
1633 seq_printf(m, "TILECTL = 0x%08x\n",
1634 I915_READ(TILECTL));
9d3203e1
BW		 1635 if (IS_GEN8(dev))
1636 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1637 I915_READ(GAMTARBMODE));
1638 else
1639 seq_printf(m, "ARB_MODE = 0x%08x\n",
1640 I915_READ(ARB_MODE));
3fa7d235
DV		 1641 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1642 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1643 }
1644 mutex_unlock(&dev->struct_mutex);
1645
1646 return 0;
1647}
1648
3cf17fc5
DV		 1649static int i915_ppgtt_info(struct seq_file *m, void *data)
1650{
1651 struct drm_info_node *node = (struct drm_info_node *) m->private;
1652 struct drm_device *dev = node->minor->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct intel_ring_buffer *ring;
1655 int i, ret;
1656
1657
1658 ret = mutex_lock_interruptible(&dev->struct_mutex);
1659 if (ret)
1660 return ret;
1661 if (INTEL_INFO(dev)->gen == 6)
1662 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1663
a2c7f6fd 1664 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1665 seq_printf(m, "%s\n", ring->name);
1666 if (INTEL_INFO(dev)->gen == 7)
1667 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1668 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1669 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1670 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1671 }
1672 if (dev_priv->mm.aliasing_ppgtt) {
1673 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1674
267f0c90 1675 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5
DV		 1676 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1677 }
1678 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1679 mutex_unlock(&dev->struct_mutex);
1680
1681 return 0;
1682}
1683
57f350b6
JB		 1684static int i915_dpio_info(struct seq_file *m, void *data)
1685{
1686 struct drm_info_node *node = (struct drm_info_node *) m->private;
1687 struct drm_device *dev = node->minor->dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 int ret;
1690
1691
1692 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1693 seq_puts(m, "unsupported\n");
57f350b6
JB		 1694 return 0;
1695 }
1696
09153000 1697 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1698 if (ret)
1699 return ret;
1700
1701 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1702
1703 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
5e69f97f 1704 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
57f350b6 1705 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
5e69f97f 1706 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
57f350b6
JB		 1707
1708 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
5e69f97f 1709 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
57f350b6 1710 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
5e69f97f 1711 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
57f350b6
JB		 1712
1713 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
5e69f97f 1714 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
57f350b6 1715 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
5e69f97f 1716 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
57f350b6 1717
4abb2c39 1718 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
5e69f97f 1719 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
4abb2c39 1720 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
5e69f97f 1721 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
57f350b6
JB		 1722
1723 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
5e69f97f 1724 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
57f350b6 1725
09153000 1726 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1727
1728 return 0;
1729}
1730
63573eb7
BW		 1731static int i915_llc(struct seq_file *m, void *data)
1732{
1733 struct drm_info_node *node = (struct drm_info_node *) m->private;
1734 struct drm_device *dev = node->minor->dev;
1735 struct drm_i915_private *dev_priv = dev->dev_private;
1736
1737 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1738 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1739 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1740
1741 return 0;
1742}
1743
e91fd8c6
RV		 1744static int i915_edp_psr_status(struct seq_file *m, void *data)
1745{
1746 struct drm_info_node *node = m->private;
1747 struct drm_device *dev = node->minor->dev;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1749 u32 psrperf = 0;
1750 bool enabled = false;
e91fd8c6 1751
a031d709
RV		 1752 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1753 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1754
a031d709
RV		 1755 enabled = HAS_PSR(dev) &&
1756 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1757 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1758
a031d709
RV		 1759 if (HAS_PSR(dev))
1760 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1761 EDP_PSR_PERF_CNT_MASK;
1762 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6
RV		 1763
1764 return 0;
1765}
1766
ec013e7f
JB		 1767static int i915_energy_uJ(struct seq_file *m, void *data)
1768{
1769 struct drm_info_node *node = m->private;
1770 struct drm_device *dev = node->minor->dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 u64 power;
1773 u32 units;
1774
1775 if (INTEL_INFO(dev)->gen < 6)
1776 return -ENODEV;
1777
1778 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1779 power = (power & 0x1f00) >> 8;
1780 units = 1000000 / (1 << power); /* convert to uJ */
1781 power = I915_READ(MCH_SECP_NRG_STTS);
1782 power *= units;
1783
1784 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1785
1786 return 0;
1787}
1788
1789static int i915_pc8_status(struct seq_file *m, void *unused)
1790{
1791 struct drm_info_node *node = (struct drm_info_node *) m->private;
1792 struct drm_device *dev = node->minor->dev;
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794
1795 if (!IS_HASWELL(dev)) {
1796 seq_puts(m, "not supported\n");
1797 return 0;
1798 }
1799
1800 mutex_lock(&dev_priv->pc8.lock);
1801 seq_printf(m, "Requirements met: %s\n",
1802 yesno(dev_priv->pc8.requirements_met));
1803 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1804 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1805 seq_printf(m, "IRQs disabled: %s\n",
1806 yesno(dev_priv->pc8.irqs_disabled));
1807 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1808 mutex_unlock(&dev_priv->pc8.lock);
1809
ec013e7f
JB		 1810 return 0;
1811}
1812
07144428
DL		 1813struct pipe_crc_info {
1814 const char *name;
1815 struct drm_device *dev;
1816 enum pipe pipe;
1817};
1818
1819static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1820{
be5c7a90
DL		 1821 struct pipe_crc_info *info = inode->i_private;
1822 struct drm_i915_private *dev_priv = info->dev->dev_private;
1823 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1824
d538bbdf
DL		 1825 spin_lock_irq(&pipe_crc->lock);
1826
1827 if (pipe_crc->opened) {
1828 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 1829 return -EBUSY; /* already open */
1830 }
1831
d538bbdf 1832 pipe_crc->opened = true;
07144428
DL		 1833 filep->private_data = inode->i_private;
1834
d538bbdf
DL		 1835 spin_unlock_irq(&pipe_crc->lock);
1836
07144428
DL		 1837 return 0;
1838}
1839
1840static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1841{
be5c7a90
DL		 1842 struct pipe_crc_info *info = inode->i_private;
1843 struct drm_i915_private *dev_priv = info->dev->dev_private;
1844 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1845
d538bbdf
DL		 1846 spin_lock_irq(&pipe_crc->lock);
1847 pipe_crc->opened = false;
1848 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 1849
07144428
DL		 1850 return 0;
1851}
1852
1853/* (6 fields, 8 chars each, space separated (5) + '\n') */
1854#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1855/* account for \'0' */
1856#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1857
1858static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 1859{
d538bbdf
DL		 1860 assert_spin_locked(&pipe_crc->lock);
1861 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1862 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 1863}
1864
1865static ssize_t
1866i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1867 loff_t *pos)
1868{
1869 struct pipe_crc_info *info = filep->private_data;
1870 struct drm_device *dev = info->dev;
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1872 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1873 char buf[PIPE_CRC_BUFFER_LEN];
1874 int head, tail, n_entries, n;
1875 ssize_t bytes_read;
1876
1877 /*
1878 * Don't allow user space to provide buffers not big enough to hold
1879 * a line of data.
1880 */
1881 if (count < PIPE_CRC_LINE_LEN)
1882 return -EINVAL;
1883
1884 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 1885 return 0;
07144428
DL		 1886
1887 /* nothing to read */
d538bbdf 1888 spin_lock_irq(&pipe_crc->lock);
07144428 1889 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 1890 int ret;
1891
1892 if (filep->f_flags & O_NONBLOCK) {
1893 spin_unlock_irq(&pipe_crc->lock);
07144428 1894 return -EAGAIN;
d538bbdf 1895 }
07144428 1896
d538bbdf
DL		 1897 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
1898 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
1899 if (ret) {
1900 spin_unlock_irq(&pipe_crc->lock);
1901 return ret;
1902 }
8bf1e9f1
SH		 1903 }
1904
07144428 1905 /* We now have one or more entries to read */
d538bbdf
DL		 1906 head = pipe_crc->head;
1907 tail = pipe_crc->tail;
07144428
DL		 1908 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
1909 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 1910 spin_unlock_irq(&pipe_crc->lock);
1911
07144428
DL		 1912 bytes_read = 0;
1913 n = 0;
1914 do {
b2c88f5b 1915 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 1916 int ret;
8bf1e9f1 1917
07144428
DL		 1918 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
1919 "%8u %8x %8x %8x %8x %8x\n",
1920 entry->frame, entry->crc[0],
1921 entry->crc[1], entry->crc[2],
1922 entry->crc[3], entry->crc[4]);
1923
1924 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
1925 buf, PIPE_CRC_LINE_LEN);
1926 if (ret == PIPE_CRC_LINE_LEN)
1927 return -EFAULT;
b2c88f5b
DL		 1928
1929 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
1930 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 1931 n++;
1932 } while (--n_entries);
8bf1e9f1 1933
d538bbdf
DL		 1934 spin_lock_irq(&pipe_crc->lock);
1935 pipe_crc->tail = tail;
1936 spin_unlock_irq(&pipe_crc->lock);
1937
07144428
DL		 1938 return bytes_read;
1939}
1940
1941static const struct file_operations i915_pipe_crc_fops = {
1942 .owner = THIS_MODULE,
1943 .open = i915_pipe_crc_open,
1944 .read = i915_pipe_crc_read,
1945 .release = i915_pipe_crc_release,
1946};
1947
1948static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
1949 {
1950 .name = "i915_pipe_A_crc",
1951 .pipe = PIPE_A,
1952 },
1953 {
1954 .name = "i915_pipe_B_crc",
1955 .pipe = PIPE_B,
1956 },
1957 {
1958 .name = "i915_pipe_C_crc",
1959 .pipe = PIPE_C,
1960 },
1961};
1962
1963static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
1964 enum pipe pipe)
1965{
1966 struct drm_device *dev = minor->dev;
1967 struct dentry *ent;
1968 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
1969
1970 info->dev = dev;
1971 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
1972 &i915_pipe_crc_fops);
1973 if (IS_ERR(ent))
1974 return PTR_ERR(ent);
1975
1976 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 1977}
1978
e8dfcf78 1979static const char * const pipe_crc_sources[] = {
926321d5
DV		 1980 "none",
1981 "plane1",
1982 "plane2",
1983 "pf",
5b3a856b 1984 "pipe",
3d099a05
DV		 1985 "TV",
1986 "DP-B",
1987 "DP-C",
1988 "DP-D",
46a19188 1989 "auto",
926321d5
DV		 1990};
1991
1992static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
1993{
1994 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
1995 return pipe_crc_sources[source];
1996}
1997
bd9db02f 1998static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 1999{
2000 struct drm_device *dev = m->private;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 int i;
2003
2004 for (i = 0; i < I915_MAX_PIPES; i++)
2005 seq_printf(m, "%c %s\n", pipe_name(i),
2006 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2007
2008 return 0;
2009}
2010
bd9db02f 2011static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2012{
2013 struct drm_device *dev = inode->i_private;
2014
bd9db02f 2015 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2016}
2017
46a19188 2018static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2019 uint32_t *val)
2020{
46a19188
DV		 2021 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2022 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2023
2024 switch (*source) {
52f843f6
DV		 2025 case INTEL_PIPE_CRC_SOURCE_PIPE:
2026 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2027 break;
2028 case INTEL_PIPE_CRC_SOURCE_NONE:
2029 *val = 0;
2030 break;
2031 default:
2032 return -EINVAL;
2033 }
2034
2035 return 0;
2036}
2037
46a19188
DV		 2038static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2039 enum intel_pipe_crc_source *source)
2040{
2041 struct intel_encoder *encoder;
2042 struct intel_crtc *crtc;
26756809 2043 struct intel_digital_port *dig_port;
46a19188
DV		 2044 int ret = 0;
2045
2046 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2047
2048 mutex_lock(&dev->mode_config.mutex);
2049 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2050 base.head) {
2051 if (!encoder->base.crtc)
2052 continue;
2053
2054 crtc = to_intel_crtc(encoder->base.crtc);
2055
2056 if (crtc->pipe != pipe)
2057 continue;
2058
2059 switch (encoder->type) {
2060 case INTEL_OUTPUT_TVOUT:
2061 *source = INTEL_PIPE_CRC_SOURCE_TV;
2062 break;
2063 case INTEL_OUTPUT_DISPLAYPORT:
2064 case INTEL_OUTPUT_EDP:
26756809
DV		 2065 dig_port = enc_to_dig_port(&encoder->base);
2066 switch (dig_port->port) {
2067 case PORT_B:
2068 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2069 break;
2070 case PORT_C:
2071 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2072 break;
2073 case PORT_D:
2074 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2075 break;
2076 default:
2077 WARN(1, "nonexisting DP port %c\n",
2078 port_name(dig_port->port));
2079 break;
2080 }
46a19188
DV		 2081 break;
2082 }
2083 }
2084 mutex_unlock(&dev->mode_config.mutex);
2085
2086 return ret;
2087}
2088
2089static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2090 enum pipe pipe,
2091 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2092 uint32_t *val)
2093{
8d2f24ca
DV		 2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 bool need_stable_symbols = false;
2096
46a19188
DV		 2097 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2098 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2099 if (ret)
2100 return ret;
2101 }
2102
2103 switch (*source) {
7ac0129b
DV		 2104 case INTEL_PIPE_CRC_SOURCE_PIPE:
2105 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2106 break;
2107 case INTEL_PIPE_CRC_SOURCE_DP_B:
2108 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2109 need_stable_symbols = true;
7ac0129b
DV		 2110 break;
2111 case INTEL_PIPE_CRC_SOURCE_DP_C:
2112 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2113 need_stable_symbols = true;
7ac0129b
DV		 2114 break;
2115 case INTEL_PIPE_CRC_SOURCE_NONE:
2116 *val = 0;
2117 break;
2118 default:
2119 return -EINVAL;
2120 }
2121
8d2f24ca
DV		 2122 /*
2123 * When the pipe CRC tap point is after the transcoders we need
2124 * to tweak symbol-level features to produce a deterministic series of
2125 * symbols for a given frame. We need to reset those features only once
2126 * a frame (instead of every nth symbol):
2127 * - DC-balance: used to ensure a better clock recovery from the data
2128 * link (SDVO)
2129 * - DisplayPort scrambling: used for EMI reduction
2130 */
2131 if (need_stable_symbols) {
2132 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2133
2134 WARN_ON(!IS_G4X(dev));
2135
2136 tmp |= DC_BALANCE_RESET_VLV;
2137 if (pipe == PIPE_A)
2138 tmp |= PIPE_A_SCRAMBLE_RESET;
2139 else
2140 tmp |= PIPE_B_SCRAMBLE_RESET;
2141
2142 I915_WRITE(PORT_DFT2_G4X, tmp);
2143 }
2144
7ac0129b
DV		 2145 return 0;
2146}
2147
4b79ebf7 2148static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2149 enum pipe pipe,
2150 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2151 uint32_t *val)
2152{
84093603
DV		 2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 bool need_stable_symbols = false;
2155
46a19188
DV		 2156 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2157 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2158 if (ret)
2159 return ret;
2160 }
2161
2162 switch (*source) {
4b79ebf7
DV		 2163 case INTEL_PIPE_CRC_SOURCE_PIPE:
2164 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2165 break;
2166 case INTEL_PIPE_CRC_SOURCE_TV:
2167 if (!SUPPORTS_TV(dev))
2168 return -EINVAL;
2169 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2170 break;
2171 case INTEL_PIPE_CRC_SOURCE_DP_B:
2172 if (!IS_G4X(dev))
2173 return -EINVAL;
2174 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2175 need_stable_symbols = true;
4b79ebf7
DV		 2176 break;
2177 case INTEL_PIPE_CRC_SOURCE_DP_C:
2178 if (!IS_G4X(dev))
2179 return -EINVAL;
2180 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2181 need_stable_symbols = true;
4b79ebf7
DV		 2182 break;
2183 case INTEL_PIPE_CRC_SOURCE_DP_D:
2184 if (!IS_G4X(dev))
2185 return -EINVAL;
2186 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2187 need_stable_symbols = true;
4b79ebf7
DV		 2188 break;
2189 case INTEL_PIPE_CRC_SOURCE_NONE:
2190 *val = 0;
2191 break;
2192 default:
2193 return -EINVAL;
2194 }
2195
84093603
DV		 2196 /*
2197 * When the pipe CRC tap point is after the transcoders we need
2198 * to tweak symbol-level features to produce a deterministic series of
2199 * symbols for a given frame. We need to reset those features only once
2200 * a frame (instead of every nth symbol):
2201 * - DC-balance: used to ensure a better clock recovery from the data
2202 * link (SDVO)
2203 * - DisplayPort scrambling: used for EMI reduction
2204 */
2205 if (need_stable_symbols) {
2206 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2207
2208 WARN_ON(!IS_G4X(dev));
2209
2210 I915_WRITE(PORT_DFT_I9XX,
2211 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2212
2213 if (pipe == PIPE_A)
2214 tmp |= PIPE_A_SCRAMBLE_RESET;
2215 else
2216 tmp |= PIPE_B_SCRAMBLE_RESET;
2217
2218 I915_WRITE(PORT_DFT2_G4X, tmp);
2219 }
2220
4b79ebf7
DV		 2221 return 0;
2222}
2223
8d2f24ca
DV		 2224static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2225 enum pipe pipe)
2226{
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2229
2230 if (pipe == PIPE_A)
2231 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2232 else
2233 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2234 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2235 tmp &= ~DC_BALANCE_RESET_VLV;
2236 I915_WRITE(PORT_DFT2_G4X, tmp);
2237
2238}
2239
84093603
DV		 2240static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2241 enum pipe pipe)
2242{
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2245
2246 if (pipe == PIPE_A)
2247 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2248 else
2249 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2250 I915_WRITE(PORT_DFT2_G4X, tmp);
2251
2252 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2253 I915_WRITE(PORT_DFT_I9XX,
2254 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2255 }
2256}
2257
46a19188 2258static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2259 uint32_t *val)
2260{
46a19188
DV		 2261 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2262 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2263
2264 switch (*source) {
5b3a856b
DV		 2265 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2266 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2267 break;
2268 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2269 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2270 break;
5b3a856b
DV		 2271 case INTEL_PIPE_CRC_SOURCE_PIPE:
2272 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2273 break;
3d099a05 2274 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2275 *val = 0;
2276 break;
3d099a05
DV		 2277 default:
2278 return -EINVAL;
5b3a856b
DV		 2279 }
2280
2281 return 0;
2282}
2283
46a19188 2284static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2285 uint32_t *val)
2286{
46a19188
DV		 2287 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2288 *source = INTEL_PIPE_CRC_SOURCE_PF;
2289
2290 switch (*source) {
5b3a856b
DV		 2291 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2292 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2293 break;
2294 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2295 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2296 break;
2297 case INTEL_PIPE_CRC_SOURCE_PF:
2298 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2299 break;
3d099a05 2300 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2301 *val = 0;
2302 break;
3d099a05
DV		 2303 default:
2304 return -EINVAL;
5b3a856b
DV		 2305 }
2306
2307 return 0;
2308}
2309
926321d5
DV		 2310static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2311 enum intel_pipe_crc_source source)
2312{
2313 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2314 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
926321d5 2315 u32 val;
5b3a856b 2316 int ret;
926321d5 2317
cc3da175
DL		 2318 if (pipe_crc->source == source)
2319 return 0;
2320
ae676fcd
DL		 2321 /* forbid changing the source without going back to 'none' */
2322 if (pipe_crc->source && source)
2323 return -EINVAL;
2324
52f843f6 2325 if (IS_GEN2(dev))
46a19188 2326 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2327 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2328 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2329 else if (IS_VALLEYVIEW(dev))
46a19188 2330 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2331 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2332 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2333 else
46a19188 2334 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2335
2336 if (ret != 0)
2337 return ret;
2338
4b584369
DL		 2339 /* none -> real source transition */
2340 if (source) {
7cd6ccff
DL		 2341 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2342 pipe_name(pipe), pipe_crc_source_name(source));
2343
e5f75aca
DL		 2344 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2345 INTEL_PIPE_CRC_ENTRIES_NR,
2346 GFP_KERNEL);
2347 if (!pipe_crc->entries)
2348 return -ENOMEM;
2349
d538bbdf
DL		 2350 spin_lock_irq(&pipe_crc->lock);
2351 pipe_crc->head = 0;
2352 pipe_crc->tail = 0;
2353 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2354 }
2355
cc3da175 2356 pipe_crc->source = source;
926321d5 2357
926321d5
DV		 2358 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2359 POSTING_READ(PIPE_CRC_CTL(pipe));
2360
e5f75aca
DL		 2361 /* real source -> none transition */
2362 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2363 struct intel_pipe_crc_entry *entries;
2364
7cd6ccff
DL		 2365 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2366 pipe_name(pipe));
2367
bcf17ab2
DV		 2368 intel_wait_for_vblank(dev, pipe);
2369
d538bbdf
DL		 2370 spin_lock_irq(&pipe_crc->lock);
2371 entries = pipe_crc->entries;
e5f75aca 2372 pipe_crc->entries = NULL;
d538bbdf
DL		 2373 spin_unlock_irq(&pipe_crc->lock);
2374
2375 kfree(entries);
84093603
DV		 2376
2377 if (IS_G4X(dev))
2378 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2379 else if (IS_VALLEYVIEW(dev))
2380 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2381 }
2382
926321d5
DV		 2383 return 0;
2384}
2385
2386/*
2387 * Parse pipe CRC command strings:
b94dec87
DL		 2388 * command: wsp* object wsp+ name wsp+ source wsp*
2389 * object: 'pipe'
2390 * name: (A | B | C)
926321d5
DV		 2391 * source: (none | plane1 | plane2 | pf)
2392 * wsp: (#0x20 | #0x9 | #0xA)+
2393 *
2394 * eg.:
b94dec87
DL		 2395 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2396 * "pipe A none" -> Stop CRC
926321d5 2397 */
bd9db02f 2398static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2399{
2400 int n_words = 0;
2401
2402 while (*buf) {
2403 char *end;
2404
2405 /* skip leading white space */
2406 buf = skip_spaces(buf);
2407 if (!*buf)
2408 break; /* end of buffer */
2409
2410 /* find end of word */
2411 for (end = buf; *end && !isspace(*end); end++)
2412 ;
2413
2414 if (n_words == max_words) {
2415 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2416 max_words);
2417 return -EINVAL; /* ran out of words[] before bytes */
2418 }
2419
2420 if (*end)
2421 *end++ = '\0';
2422 words[n_words++] = buf;
2423 buf = end;
2424 }
2425
2426 return n_words;
2427}
2428
b94dec87
DL		 2429enum intel_pipe_crc_object {
2430 PIPE_CRC_OBJECT_PIPE,
2431};
2432
e8dfcf78 2433static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2434 "pipe",
2435};
2436
2437static int
bd9db02f 2438display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2439{
2440 int i;
2441
2442 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2443 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2444 *o = i;
b94dec87
DL		 2445 return 0;
2446 }
2447
2448 return -EINVAL;
2449}
2450
bd9db02f 2451static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2452{
2453 const char name = buf[0];
2454
2455 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2456 return -EINVAL;
2457
2458 *pipe = name - 'A';
2459
2460 return 0;
2461}
2462
2463static int
bd9db02f 2464display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2465{
2466 int i;
2467
2468 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2469 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2470 *s = i;
926321d5
DV		 2471 return 0;
2472 }
2473
2474 return -EINVAL;
2475}
2476
bd9db02f 2477static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2478{
b94dec87 2479#define N_WORDS 3
926321d5 2480 int n_words;
b94dec87 2481 char *words[N_WORDS];
926321d5 2482 enum pipe pipe;
b94dec87 2483 enum intel_pipe_crc_object object;
926321d5
DV		 2484 enum intel_pipe_crc_source source;
2485
bd9db02f 2486 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2487 if (n_words != N_WORDS) {
2488 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2489 N_WORDS);
2490 return -EINVAL;
2491 }
2492
bd9db02f 2493 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2494 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2495 return -EINVAL;
2496 }
2497
bd9db02f 2498 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2499 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2500 return -EINVAL;
2501 }
2502
bd9db02f 2503 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2504 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2505 return -EINVAL;
2506 }
2507
2508 return pipe_crc_set_source(dev, pipe, source);
2509}
2510
bd9db02f
DL		 2511static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2512 size_t len, loff_t *offp)
926321d5
DV		 2513{
2514 struct seq_file *m = file->private_data;
2515 struct drm_device *dev = m->private;
2516 char *tmpbuf;
2517 int ret;
2518
2519 if (len == 0)
2520 return 0;
2521
2522 if (len > PAGE_SIZE - 1) {
2523 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2524 PAGE_SIZE);
2525 return -E2BIG;
2526 }
2527
2528 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2529 if (!tmpbuf)
2530 return -ENOMEM;
2531
2532 if (copy_from_user(tmpbuf, ubuf, len)) {
2533 ret = -EFAULT;
2534 goto out;
2535 }
2536 tmpbuf[len] = '\0';
2537
bd9db02f 2538 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2539
2540out:
2541 kfree(tmpbuf);
2542 if (ret < 0)
2543 return ret;
2544
2545 *offp += len;
2546 return len;
2547}
2548
bd9db02f 2549static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 2550 .owner = THIS_MODULE,
bd9db02f 2551 .open = display_crc_ctl_open,
926321d5
DV		 2552 .read = seq_read,
2553 .llseek = seq_lseek,
2554 .release = single_release,
bd9db02f 2555 .write = display_crc_ctl_write
926321d5
DV		 2556};
2557
647416f9
KC		 2558static int
2559i915_wedged_get(void *data, u64 *val)
f3cd474b 2560{
647416f9 2561 struct drm_device *dev = data;
f3cd474b 2562 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 2563
647416f9 2564 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 2565
647416f9 2566 return 0;
f3cd474b
CW		 2567}
2568
647416f9
KC		 2569static int
2570i915_wedged_set(void *data, u64 val)
f3cd474b 2571{
647416f9 2572 struct drm_device *dev = data;
f3cd474b 2573
647416f9 2574 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 2575 i915_handle_error(dev, val);
f3cd474b 2576
647416f9 2577 return 0;
f3cd474b
CW		 2578}
2579
647416f9
KC		 2580DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2581 i915_wedged_get, i915_wedged_set,
3a3b4f98 2582 "%llu\n");
f3cd474b 2583
647416f9
KC		 2584static int
2585i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 2586{
647416f9 2587 struct drm_device *dev = data;
e5eb3d63 2588 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 2589
647416f9 2590 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 2591
647416f9 2592 return 0;
e5eb3d63
DV		 2593}
2594
647416f9
KC		 2595static int
2596i915_ring_stop_set(void *data, u64 val)
e5eb3d63 2597{
647416f9 2598 struct drm_device *dev = data;
e5eb3d63 2599 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2600 int ret;
e5eb3d63 2601
647416f9 2602 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 2603
22bcfc6a
DV		 2604 ret = mutex_lock_interruptible(&dev->struct_mutex);
2605 if (ret)
2606 return ret;
2607
99584db3 2608 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 2609 mutex_unlock(&dev->struct_mutex);
2610
647416f9 2611 return 0;
e5eb3d63
DV		 2612}
2613
647416f9
KC		 2614DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2615 i915_ring_stop_get, i915_ring_stop_set,
2616 "0x%08llx\n");
d5442303 2617
094f9a54
CW		 2618static int
2619i915_ring_missed_irq_get(void *data, u64 *val)
2620{
2621 struct drm_device *dev = data;
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623
2624 *val = dev_priv->gpu_error.missed_irq_rings;
2625 return 0;
2626}
2627
2628static int
2629i915_ring_missed_irq_set(void *data, u64 val)
2630{
2631 struct drm_device *dev = data;
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 int ret;
2634
2635 /* Lock against concurrent debugfs callers */
2636 ret = mutex_lock_interruptible(&dev->struct_mutex);
2637 if (ret)
2638 return ret;
2639 dev_priv->gpu_error.missed_irq_rings = val;
2640 mutex_unlock(&dev->struct_mutex);
2641
2642 return 0;
2643}
2644
2645DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2646 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2647 "0x%08llx\n");
2648
2649static int
2650i915_ring_test_irq_get(void *data, u64 *val)
2651{
2652 struct drm_device *dev = data;
2653 struct drm_i915_private *dev_priv = dev->dev_private;
2654
2655 *val = dev_priv->gpu_error.test_irq_rings;
2656
2657 return 0;
2658}
2659
2660static int
2661i915_ring_test_irq_set(void *data, u64 val)
2662{
2663 struct drm_device *dev = data;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 int ret;
2666
2667 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2668
2669 /* Lock against concurrent debugfs callers */
2670 ret = mutex_lock_interruptible(&dev->struct_mutex);
2671 if (ret)
2672 return ret;
2673
2674 dev_priv->gpu_error.test_irq_rings = val;
2675 mutex_unlock(&dev->struct_mutex);
2676
2677 return 0;
2678}
2679
2680DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2681 i915_ring_test_irq_get, i915_ring_test_irq_set,
2682 "0x%08llx\n");
2683
dd624afd
CW		 2684#define DROP_UNBOUND 0x1
2685#define DROP_BOUND 0x2
2686#define DROP_RETIRE 0x4
2687#define DROP_ACTIVE 0x8
2688#define DROP_ALL (DROP_UNBOUND | \
2689 DROP_BOUND | \
2690 DROP_RETIRE | \
2691 DROP_ACTIVE)
647416f9
KC		 2692static int
2693i915_drop_caches_get(void *data, u64 *val)
dd624afd 2694{
647416f9 2695 *val = DROP_ALL;
dd624afd 2696
647416f9 2697 return 0;
dd624afd
CW		 2698}
2699
647416f9
KC		 2700static int
2701i915_drop_caches_set(void *data, u64 val)
dd624afd 2702{
647416f9 2703 struct drm_device *dev = data;
dd624afd
CW		 2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 2706 struct i915_address_space *vm;
2707 struct i915_vma *vma, *x;
647416f9 2708 int ret;
dd624afd 2709
647416f9 2710 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 2711
2712 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2713 * on ioctls on -EAGAIN. */
2714 ret = mutex_lock_interruptible(&dev->struct_mutex);
2715 if (ret)
2716 return ret;
2717
2718 if (val & DROP_ACTIVE) {
2719 ret = i915_gpu_idle(dev);
2720 if (ret)
2721 goto unlock;
2722 }
2723
2724 if (val & (DROP_RETIRE | DROP_ACTIVE))
2725 i915_gem_retire_requests(dev);
2726
2727 if (val & DROP_BOUND) {
ca191b13
BW		 2728 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2729 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2730 mm_list) {
2731 if (vma->obj->pin_count)
2732 continue;
2733
2734 ret = i915_vma_unbind(vma);
2735 if (ret)
2736 goto unlock;
2737 }
31a46c9c 2738 }
dd624afd
CW		 2739 }
2740
2741 if (val & DROP_UNBOUND) {
35c20a60
BW		 2742 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2743 global_list)
dd624afd
CW		 2744 if (obj->pages_pin_count == 0) {
2745 ret = i915_gem_object_put_pages(obj);
2746 if (ret)
2747 goto unlock;
2748 }
2749 }
2750
2751unlock:
2752 mutex_unlock(&dev->struct_mutex);
2753
647416f9 2754 return ret;
dd624afd
CW		 2755}
2756
647416f9
KC		 2757DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2758 i915_drop_caches_get, i915_drop_caches_set,
2759 "0x%08llx\n");
dd624afd 2760
647416f9
KC		 2761static int
2762i915_max_freq_get(void *data, u64 *val)
358733e9 2763{
647416f9 2764 struct drm_device *dev = data;
358733e9 2765 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2766 int ret;
004777cb
DV		 2767
2768 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2769 return -ENODEV;
2770
5c9669ce
TR		 2771 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2772
4fc688ce 2773 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2774 if (ret)
2775 return ret;
358733e9 2776
0a073b84
JB		 2777 if (IS_VALLEYVIEW(dev))
2778 *val = vlv_gpu_freq(dev_priv->mem_freq,
2779 dev_priv->rps.max_delay);
2780 else
2781 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2782 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2783
647416f9 2784 return 0;
358733e9
JB		 2785}
2786
647416f9
KC		 2787static int
2788i915_max_freq_set(void *data, u64 val)
358733e9 2789{
647416f9 2790 struct drm_device *dev = data;
358733e9 2791 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2792 int ret;
004777cb
DV		 2793
2794 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2795 return -ENODEV;
358733e9 2796
5c9669ce
TR		 2797 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2798
647416f9 2799 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 2800
4fc688ce 2801 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2802 if (ret)
2803 return ret;
2804
358733e9
JB		 2805 /*
2806 * Turbo will still be enabled, but won't go above the set value.
2807 */
0a073b84
JB		 2808 if (IS_VALLEYVIEW(dev)) {
2809 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2810 dev_priv->rps.max_delay = val;
2811 gen6_set_rps(dev, val);
2812 } else {
2813 do_div(val, GT_FREQUENCY_MULTIPLIER);
2814 dev_priv->rps.max_delay = val;
2815 gen6_set_rps(dev, val);
2816 }
2817
4fc688ce 2818 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2819
647416f9 2820 return 0;
358733e9
JB		 2821}
2822
647416f9
KC		 2823DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2824 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 2825 "%llu\n");
358733e9 2826
647416f9
KC		 2827static int
2828i915_min_freq_get(void *data, u64 *val)
1523c310 2829{
647416f9 2830 struct drm_device *dev = data;
1523c310 2831 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2832 int ret;
004777cb
DV		 2833
2834 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2835 return -ENODEV;
2836
5c9669ce
TR		 2837 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2838
4fc688ce 2839 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2840 if (ret)
2841 return ret;
1523c310 2842
0a073b84
JB		 2843 if (IS_VALLEYVIEW(dev))
2844 *val = vlv_gpu_freq(dev_priv->mem_freq,
2845 dev_priv->rps.min_delay);
2846 else
2847 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2848 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2849
647416f9 2850 return 0;
1523c310
JB		 2851}
2852
647416f9
KC		 2853static int
2854i915_min_freq_set(void *data, u64 val)
1523c310 2855{
647416f9 2856 struct drm_device *dev = data;
1523c310 2857 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2858 int ret;
004777cb
DV		 2859
2860 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2861 return -ENODEV;
1523c310 2862
5c9669ce
TR		 2863 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2864
647416f9 2865 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 2866
4fc688ce 2867 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2868 if (ret)
2869 return ret;
2870
1523c310
JB		 2871 /*
2872 * Turbo will still be enabled, but won't go below the set value.
2873 */
0a073b84
JB		 2874 if (IS_VALLEYVIEW(dev)) {
2875 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2876 dev_priv->rps.min_delay = val;
2877 valleyview_set_rps(dev, val);
2878 } else {
2879 do_div(val, GT_FREQUENCY_MULTIPLIER);
2880 dev_priv->rps.min_delay = val;
2881 gen6_set_rps(dev, val);
2882 }
4fc688ce 2883 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2884
647416f9 2885 return 0;
1523c310
JB		 2886}
2887
647416f9
KC		 2888DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2889 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 2890 "%llu\n");
1523c310 2891
647416f9
KC		 2892static int
2893i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 2894{
647416f9 2895 struct drm_device *dev = data;
07b7ddd9 2896 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 2897 u32 snpcr;
647416f9 2898 int ret;
07b7ddd9 2899
004777cb
DV		 2900 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2901 return -ENODEV;
2902
22bcfc6a
DV		 2903 ret = mutex_lock_interruptible(&dev->struct_mutex);
2904 if (ret)
2905 return ret;
2906
07b7ddd9
JB		 2907 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2908 mutex_unlock(&dev_priv->dev->struct_mutex);
2909
647416f9 2910 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 2911
647416f9 2912 return 0;
07b7ddd9
JB		 2913}
2914
647416f9
KC		 2915static int
2916i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 2917{
647416f9 2918 struct drm_device *dev = data;
07b7ddd9 2919 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 2920 u32 snpcr;
07b7ddd9 2921
004777cb
DV		 2922 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2923 return -ENODEV;
2924
647416f9 2925 if (val > 3)
07b7ddd9
JB		 2926 return -EINVAL;
2927
647416f9 2928 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 2929
2930 /* Update the cache sharing policy here as well */
2931 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2932 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2933 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2934 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2935
647416f9 2936 return 0;
07b7ddd9
JB		 2937}
2938
647416f9
KC		 2939DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2940 i915_cache_sharing_get, i915_cache_sharing_set,
2941 "%llu\n");
07b7ddd9 2942
6d794d42
BW		 2943static int i915_forcewake_open(struct inode *inode, struct file *file)
2944{
2945 struct drm_device *dev = inode->i_private;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 2947
075edca4 2948 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2949 return 0;
2950
6d794d42 2951 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 2952
2953 return 0;
2954}
2955
c43b5634 2956static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 2957{
2958 struct drm_device *dev = inode->i_private;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960
075edca4 2961 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 2962 return 0;
2963
6d794d42 2964 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 2965
2966 return 0;
2967}
2968
2969static const struct file_operations i915_forcewake_fops = {
2970 .owner = THIS_MODULE,
2971 .open = i915_forcewake_open,
2972 .release = i915_forcewake_release,
2973};
2974
2975static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2976{
2977 struct drm_device *dev = minor->dev;
2978 struct dentry *ent;
2979
2980 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 2981 S_IRUSR,
6d794d42
BW		 2982 root, dev,
2983 &i915_forcewake_fops);
2984 if (IS_ERR(ent))
2985 return PTR_ERR(ent);
2986
8eb57294 2987 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2988}
2989
6a9c308d
DV		 2990static int i915_debugfs_create(struct dentry *root,
2991 struct drm_minor *minor,
2992 const char *name,
2993 const struct file_operations *fops)
07b7ddd9
JB		 2994{
2995 struct drm_device *dev = minor->dev;
2996 struct dentry *ent;
2997
6a9c308d 2998 ent = debugfs_create_file(name,
07b7ddd9
JB		 2999 S_IRUGO | S_IWUSR,
3000 root, dev,
6a9c308d 3001 fops);
07b7ddd9
JB		 3002 if (IS_ERR(ent))
3003 return PTR_ERR(ent);
3004
6a9c308d 3005 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3006}
3007
27c202ad 3008static struct drm_info_list i915_debugfs_list[] = {
311bd68e 3009 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3010 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3011 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3012 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3013 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3014 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3015 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3016 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3017 {"i915_gem_request", i915_gem_request_info, 0},
3018 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3019 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3020 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3021 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3022 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3023 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3024 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3025 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3026 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3027 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3028 {"i915_inttoext_table", i915_inttoext_table, 0},
3029 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3030 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3031 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3032 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3033 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3034 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3035 {"i915_sr_status", i915_sr_status, 0},
44834a67 3036 {"i915_opregion", i915_opregion, 0},
37811fcc 3037 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3038 {"i915_context_status", i915_context_status, 0},
6d794d42 3039 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3040 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3041 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3042 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3043 {"i915_llc", i915_llc, 0},
e91fd8c6 3044 {"i915_edp_psr_status", i915_edp_psr_status, 0},
ec013e7f 3045 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3046 {"i915_pc8_status", i915_pc8_status, 0},
2017263e 3047};
27c202ad 3048#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3049
2b4bd0e0 3050static struct i915_debugfs_files {
34b9674c
DV		 3051 const char *name;
3052 const struct file_operations *fops;
3053} i915_debugfs_files[] = {
3054 {"i915_wedged", &i915_wedged_fops},
3055 {"i915_max_freq", &i915_max_freq_fops},
3056 {"i915_min_freq", &i915_min_freq_fops},
3057 {"i915_cache_sharing", &i915_cache_sharing_fops},
3058 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3059 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3060 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3061 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3062 {"i915_error_state", &i915_error_state_fops},
3063 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3064 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
34b9674c
DV		 3065};
3066
07144428
DL		 3067void intel_display_crc_init(struct drm_device *dev)
3068{
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 int i;
3071
3072 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
3073 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i];
3074
d538bbdf
DL		 3075 pipe_crc->opened = false;
3076 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3077 init_waitqueue_head(&pipe_crc->wq);
3078 }
3079}
3080
27c202ad 3081int i915_debugfs_init(struct drm_minor *minor)
2017263e 3082{
34b9674c 3083 int ret, i;
f3cd474b 3084
6d794d42 3085 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3086 if (ret)
3087 return ret;
6a9c308d 3088
07144428
DL		 3089 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3090 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3091 if (ret)
3092 return ret;
3093 }
3094
34b9674c
DV		 3095 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3096 ret = i915_debugfs_create(minor->debugfs_root, minor,
3097 i915_debugfs_files[i].name,
3098 i915_debugfs_files[i].fops);
3099 if (ret)
3100 return ret;
3101 }
40633219 3102
27c202ad
BG		 3103 return drm_debugfs_create_files(i915_debugfs_list,
3104 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3105 minor->debugfs_root, minor);
3106}
3107
27c202ad 3108void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3109{
34b9674c
DV		 3110 int i;
3111
27c202ad
BG		 3112 drm_debugfs_remove_files(i915_debugfs_list,
3113 I915_DEBUGFS_ENTRIES, minor);
07144428 3114
6d794d42
BW		 3115 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3116 1, minor);
07144428 3117
e309a997 3118 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3119 struct drm_info_list *info_list =
3120 (struct drm_info_list *)&i915_pipe_crc_data[i];
3121
3122 drm_debugfs_remove_files(info_list, 1, minor);
3123 }
3124
34b9674c
DV		 3125 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3126 struct drm_info_list *info_list =
3127 (struct drm_info_list *) i915_debugfs_files[i].fops;
3128
3129 drm_debugfs_remove_files(info_list, 1, minor);
3130 }
2017263e
BG		 3131}
3132
3133#endif /* CONFIG_DEBUG_FS */
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